Re: [PATCH libdrm 2/2] libdrm: clean up non list code path for vamgr

[Chunming Zhou]

On 2018年02月08日 17:13, Chunming Zhou wrote:



On 2018年02月08日 17:01, Michel Dänzer wrote:

Hi David,


this change completely broke radeonsi due to memory management errors
(see valgrind output for glxgears below), so I had to revert it.

ok, I will look into what happens. Sorry for broken.
The patch lost a "goto out" in free_va when applying patch from hybrid 
to opensource.

The attached fixes that, I tested successfully in my local side.
 please review or test, if no problem, I will submit it again.

Thanks,
David Zhou



Regards,
David Zhou



==4831== Memcheck, a memory error detector
==4831== Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al.
==4831== Using Valgrind-3.13.0 and LibVEX; rerun with -h for 
copyright info

==4831== Command: glxgears
==4831==
==4831== Invalid read of size 8
==4831==    at 0xAE4E79B: list_add (util_double_list.h:56)
==4831==    by 0xAE4E79B: amdgpu_vamgr_free_va.part.0 
(amdgpu_vamgr.c:184)

==4831==    by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==    by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==    by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==    by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==    by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==    by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==    by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==    by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==    by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==    by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==    by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==    by 0x535BCCE: FreeScreenConfigs.isra.3 (glxext.c:221)
==4831==  Address 0x151eccb8 is 8 bytes inside a block of size 32 free'd
==4831==    at 0x4C2DDBB: free (vg_replace_malloc.c:530)
==4831==    by 0xAE4E85B: amdgpu_vamgr_free_va.part.0 
(amdgpu_vamgr.c:165)

==4831==    by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==    by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==    by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==    by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==    by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==    by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==    by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==    by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==    by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==    by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==    by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==  Block was alloc'd at
==4831==    at 0x4C2EBA5: calloc (vg_replace_malloc.c:711)
==4831==    by 0xAE4E795: amdgpu_vamgr_free_va.part.0 
(amdgpu_vamgr.c:180)

==4831==    by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==    by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==    by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==    by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==    by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==    by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==    by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==    by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==    by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==    by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==    by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==
==4831== Invalid read of size 8
==4831==    at 0xAE4E7B0: list_add (util_double_list.h:57)
==4831==    by 0xAE4E7B0: amdgpu_vamgr_free_va.part.0 
(amdgpu_vamgr.c:184)

==4831==    by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==    by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==    by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==    by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==    by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==    by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==    by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==    by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==    by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==    by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==    by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==    by 0x535BCCE: FreeScreenConfigs.isra.3 (glxext.c:221)
==4831==  Address 0x151eccb8 is 8 bytes inside a block of size 32 free'd
==4831==    at 0x4C2DDBB: free (vg_replace_malloc.c:530)
==4831==    by 0xAE4E85B: amdgpu_vamgr_free_va.part.0 
(amdgpu_vamgr.c:165)

==4831==    by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==    by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==    by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==    by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==    by 

RE: [PATCH 3/4] drm/ttm: add input parameter force_alloc for ttm_bo_evict_mm

[He, Roger]

I can't think of an use case when we don't want this to succeed.

That is true. seems I can simplify more here.

Thanks
Roger(Hongbo.He)
-Original Message-
From: Koenig, Christian 
Sent: Thursday, February 08, 2018 8:58 PM
To: He, Roger ; amd-gfx@lists.freedesktop.org; 
dri-de...@lists.freedesktop.org
Subject: Re: [PATCH 3/4] drm/ttm: add input parameter force_alloc for 
ttm_bo_evict_mm

Am 08.02.2018 um 10:06 schrieb Roger He:
> if true, allocate TTM pages regardless of zone global memory account 
> limit. For suspend, We should avoid TTM memory allocate failure then 
> result in suspend failure.

Why the extra parameter for amdgpu_bo_evict_vram ?

I can't think of an use case when we don't want this to succeed.

Christian.

>
> Signed-off-by: Roger He 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  |  4 ++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  |  4 ++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.h  |  2 +-
>   drivers/gpu/drm/nouveau/nouveau_drm.c   |  2 +-
>   drivers/gpu/drm/qxl/qxl_object.c|  4 ++--
>   drivers/gpu/drm/radeon/radeon_device.c  |  6 +++---
>   drivers/gpu/drm/radeon/radeon_object.c  |  5 +++--
>   drivers/gpu/drm/radeon/radeon_object.h  |  3 ++-
>   drivers/gpu/drm/ttm/ttm_bo.c| 16 ++--
>   drivers/gpu/drm/vmwgfx/vmwgfx_drv.c |  6 +++---
>   include/drm/ttm/ttm_bo_api.h|  5 -
>   12 files changed, 34 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> index ee76b46..59ee12c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> @@ -763,7 +763,7 @@ static int amdgpu_debugfs_evict_vram(struct seq_file *m, 
> void *data)
>   struct drm_device *dev = node->minor->dev;
>   struct amdgpu_device *adev = dev->dev_private;
>   
> - seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev));
> + seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev, true));
>   return 0;
>   }
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index e3fa3d7..3c5f9ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2168,7 +2168,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
> suspend, bool fbcon)
>   }
>   }
>   /* evict vram memory */
> - amdgpu_bo_evict_vram(adev);
> + amdgpu_bo_evict_vram(adev, true);
>   
>   amdgpu_fence_driver_suspend(adev);
>   
> @@ -2178,7 +2178,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
> suspend, bool fbcon)
>* This second call to evict vram is to evict the gart page table
>* using the CPU.
>*/
> - amdgpu_bo_evict_vram(adev);
> + amdgpu_bo_evict_vram(adev, true);
>   
>   pci_save_state(dev->pdev);
>   if (suspend) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 0338ef6..db813f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -803,14 +803,14 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
>   return r;
>   }
>   
> -int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
> +int amdgpu_bo_evict_vram(struct amdgpu_device *adev, bool 
> +force_alloc)
>   {
>   /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
>   if (0 && (adev->flags & AMD_IS_APU)) {
>   /* Useless to evict on IGP chips */
>   return 0;
>   }
> - return ttm_bo_evict_mm(>mman.bdev, TTM_PL_VRAM);
> + return ttm_bo_evict_mm(>mman.bdev, TTM_PL_VRAM, force_alloc);
>   }
>   
>   static const char *amdgpu_vram_names[] = { diff --git 
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> index c2b02f5..6724cdc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> @@ -227,7 +227,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
> domain,
>u64 min_offset, u64 max_offset,
>u64 *gpu_addr);
>   int amdgpu_bo_unpin(struct amdgpu_bo *bo); -int 
> amdgpu_bo_evict_vram(struct amdgpu_device *adev);
> +int amdgpu_bo_evict_vram(struct amdgpu_device *adev, bool 
> +force_alloc);
>   int amdgpu_bo_init(struct amdgpu_device *adev);
>   void amdgpu_bo_fini(struct amdgpu_device *adev);
>   int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, diff --git 
> a/drivers/gpu/drm/nouveau/nouveau_drm.c 
> b/drivers/gpu/drm/nouveau/nouveau_drm.c
> index 8d4a5be..c9627ef 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_drm.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
> @@ -702,7 +702,7 @@ 

[PATCH 3/3] drm/radeon: only enable swiotlb path when need v2

[Chunming Zhou]

swiotlb expands our card accessing range, but its path always is slower
than ttm pool allocation.
So add condition to use it.
v2: move a bit later

Change-Id: I1802645833155a9cd808913f863981173a82145f
Signed-off-by: Chunming Zhou 
Reviewed-by: Monk Liu 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/radeon/radeon.h| 1 +
 drivers/gpu/drm/radeon/radeon_device.c | 2 ++
 drivers/gpu/drm/radeon/radeon_ttm.c| 6 +++---
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index d34887873dea..4a2eb409aacc 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2387,6 +2387,7 @@ struct radeon_device {
struct radeon_dummy_pagedummy_page;
boolshutdown;
boolneed_dma32;
+   boolneed_swiotlb;
boolaccel_working;
boolfastfb_working; /* IGP feature*/
boolneeds_reset, in_reset;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c 
b/drivers/gpu/drm/radeon/radeon_device.c
index 8d3e3d2e0090..7f40c6f7c4dd 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1378,6 +1379,7 @@ int radeon_device_init(struct radeon_device *rdev,
pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
pr_warn("radeon: No coherent DMA available\n");
}
+   rdev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 
/* Registers mapping */
/* TODO: block userspace mapping of io register */
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
b/drivers/gpu/drm/radeon/radeon_ttm.c
index a0a839bc39bf..c1e3862a48a4 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -756,7 +756,7 @@ static int radeon_ttm_tt_populate(struct ttm_tt *ttm,
 #endif
 
 #ifdef CONFIG_SWIOTLB
-   if (swiotlb_nr_tbl()) {
+   if (rdev->need_swiotlb && swiotlb_nr_tbl()) {
return ttm_dma_populate(>ttm, rdev->dev, ctx);
}
 #endif
@@ -788,7 +788,7 @@ static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
 #endif
 
 #ifdef CONFIG_SWIOTLB
-   if (swiotlb_nr_tbl()) {
+   if (rdev->need_swiotlb && swiotlb_nr_tbl()) {
ttm_dma_unpopulate(>ttm, rdev->dev);
return;
}
@@ -1155,7 +1155,7 @@ static int radeon_ttm_debugfs_init(struct radeon_device 
*rdev)
count = ARRAY_SIZE(radeon_ttm_debugfs_list);
 
 #ifdef CONFIG_SWIOTLB
-   if (!swiotlb_nr_tbl())
+   if (!(rdev->need_swiotlb && swiotlb_nr_tbl()))
--count;
 #endif
 
-- 
2.14.1

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[PATCH 1/3] drm: add func to get max iomem address v2

[Chunming Zhou]

it will be used to check if the driver needs swiotlb
v2: Don't use inline, instead, move function to drm_memory.c (Mechel Daenzer 
)

Change-Id: Idbe47af8f12032d4803bb3d47273e807f19169c3
Signed-off-by: Chunming Zhou 
Reviewed-by: Monk Liu 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/drm_memory.c | 13 +
 include/drm/drm_cache.h  |  2 ++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/drm_memory.c b/drivers/gpu/drm/drm_memory.c
index fc0ebd273ef8..7ca500b8c399 100644
--- a/drivers/gpu/drm/drm_memory.c
+++ b/drivers/gpu/drm/drm_memory.c
@@ -149,3 +149,16 @@ void drm_legacy_ioremapfree(struct drm_local_map *map, 
struct drm_device *dev)
iounmap(map->handle);
 }
 EXPORT_SYMBOL(drm_legacy_ioremapfree);
+
+u64 drm_get_max_iomem(void)
+{
+   struct resource *tmp;
+   u64 max_iomem = 0;
+
+   for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
+   max_iomem = max(max_iomem,  tmp->end);
+   }
+
+   return max_iomem;
+}
+EXPORT_SYMBOL(drm_get_max_iomem);
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index beab0f0d0cfb..bfe1639df02d 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -38,6 +38,8 @@
 void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
 void drm_clflush_sg(struct sg_table *st);
 void drm_clflush_virt_range(void *addr, unsigned long length);
+u64 drm_get_max_iomem(void);
+
 
 static inline bool drm_arch_can_wc_memory(void)
 {
-- 
2.14.1

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[PATCH 2/3] drm/amdgpu: only enable swiotlb alloc when need v2

[Chunming Zhou]

get the max io mapping address of system memory to see if it is over
our card accessing range.
v2: move checking later

Change-Id: Ibc38dbd34a20af5b4a4b1ed154c14e1c58aa4c55
Signed-off-by: Chunming Zhou 
Reviewed-by: Monk Liu 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 2 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 2 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 3 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 2 ++
 6 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 257424dd8a52..627a06185368 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1437,6 +1437,7 @@ struct amdgpu_device {
const struct amdgpu_asic_funcs  *asic_funcs;
boolshutdown;
boolneed_dma32;
+   boolneed_swiotlb;
boolaccel_working;
struct work_struct  reset_work;
struct notifier_block   acpi_nb;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 95f990140f2a..a021de9629ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1018,7 +1018,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
}
 
 #ifdef CONFIG_SWIOTLB
-   if (swiotlb_nr_tbl()) {
+   if (adev->need_swiotlb && swiotlb_nr_tbl()) {
return ttm_dma_populate(>ttm, adev->dev, ctx);
}
 #endif
@@ -1045,7 +1045,7 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
adev = amdgpu_ttm_adev(ttm->bdev);
 
 #ifdef CONFIG_SWIOTLB
-   if (swiotlb_nr_tbl()) {
+   if (adev->need_swiotlb && swiotlb_nr_tbl()) {
ttm_dma_unpopulate(>ttm, adev->dev);
return;
}
@@ -2007,7 +2007,7 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device 
*adev)
count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
 
 #ifdef CONFIG_SWIOTLB
-   if (!swiotlb_nr_tbl())
+   if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
--count;
 #endif
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 5eacc0819b66..1945fe842188 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -22,6 +22,7 @@
  */
 #include 
 #include 
+#include 
 #include "amdgpu.h"
 #include "gmc_v6_0.h"
 #include "amdgpu_ucode.h"
@@ -866,6 +867,7 @@ static int gmc_v6_0_sw_init(void *handle)
pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
}
+   adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 
r = gmc_v6_0_init_microcode(adev);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index ce7f484f86f9..761def04f93f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -22,6 +22,7 @@
  */
 #include 
 #include 
+#include 
 #include "amdgpu.h"
 #include "cikd.h"
 #include "cik.h"
@@ -1014,6 +1015,7 @@ static int gmc_v7_0_sw_init(void *handle)
pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
pr_warn("amdgpu: No coherent DMA available\n");
}
+   adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 
r = gmc_v7_0_init_microcode(adev);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index f53f3936fd4f..2489be7ad62b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -22,6 +22,7 @@
  */
 #include 
 #include 
+#include 
 #include "amdgpu.h"
 #include "gmc_v8_0.h"
 #include "amdgpu_ucode.h"
@@ -1101,6 +1102,7 @@ static int gmc_v8_0_sw_init(void *handle)
 */
adev->need_dma32 = false;
dma_bits = adev->need_dma32 ? 32 : 40;
+   adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
if (r) {
adev->need_dma32 = true;
@@ -1112,6 +1114,7 @@ static int gmc_v8_0_sw_init(void *handle)
pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
pr_warn("amdgpu: No coherent DMA available\n");
}
+   adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 
r = gmc_v8_0_init_microcode(adev);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 2c60981d2eec..0f4a9a8575a4 100644
--- 

Re: [PATCH v3 4/4] amdgpu/dc/calcs: Support clang option for stack alignment

[Matthias Kaehlcke]

El Thu, Feb 08, 2018 at 04:44:21PM -0500 Harry Wentland ha dit:

> On 2018-02-08 04:03 PM, Harry Wentland wrote:
> > On 2018-02-08 03:53 PM, Matthias Kaehlcke wrote:
> >> calcs uses the compiler option -mpreferred-stack-boundary=4 to configure
> >> a stack alignment of 16 bytes. Clang uses the option -mstack-alignment
> >> instead, which expects as parameter the alignment in bytes, and not a
> >> power of two like -mpreferred-stack-boundary.
> >>
> >> Probe for both compiler options and use the correct one, similar to
> >> what is done in arch/x86/Makefile.
> >>
> >> Signed-off-by: Matthias Kaehlcke 
> > 
> > Series is
> > Reviewed-by: Harry Wentland 
> 
> ... and merged to amd-staging-drm-next.

Thanks!

> I had to resolve a small conflict with patches 1 & 2. Not a big deal but 
> curious what development branch you use. We normally use this for amd-gfx 
> development: 
> https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next 
> (although it might be a bit behind our internal dev tree).

I typically use Linus' tree as base, will try to remember to check
future patches against amd-staging-drm-next.

> >> ---
> >> Changes in v3:
> >> - patch added
> >>
> >> Note to self: if this patterns proliferates further we probably want to
> >> put the evaluation of the correct compiler flag in some common place.
> >>
> >>  drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +++-
> >>  1 file changed, 7 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
> >> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> >> index af0f452f3c9f..95f332ee3e7e 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> >> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> >> @@ -24,7 +24,13 @@
> >>  # It calculates Bandwidth and Watermarks values for HW programming
> >>  #
> >>  
> >> -calcs_ccflags := -mhard-float -msse -mpreferred-stack-boundary=4
> >> +ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
> >> +  cc_stack_align := -mpreferred-stack-boundary=4
> >> +else ifneq ($(call cc-option, -mstack-alignment=16),)
> >> +  cc_stack_align := -mstack-alignment=16
> >> +endif
> >> +
> >> +calcs_ccflags := -mhard-float -msse $(cc_stack_align)
> >>  
> >>  CFLAGS_dcn_calcs.o := $(calcs_ccflags)
> >>  CFLAGS_dcn_calc_auto.o := $(calcs_ccflags)
> >>
> > ___
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> > dri-de...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> > 
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Re: [PATCH] drm/amd/display: Remove unused CFLAGS entry in DML Makefile

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Harry 
Wentland 
Sent: Thursday, February 8, 2018 4:47:28 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry
Subject: [PATCH] drm/amd/display: Remove unused CFLAGS entry in DML Makefile

Missed that with a previous change that removed unused files.

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dml/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile 
b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 0271043cf6a2..f83a608f93e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -32,7 +32,6 @@ endif

 dml_ccflags := -mhard-float -msse $(cc_stack_align)

-CFLAGS_display_mode_vba.o := $(dml_ccflags)
 CFLAGS_display_mode_lib.o := $(dml_ccflags)
 CFLAGS_display_pipe_clocks.o := $(dml_ccflags)
 CFLAGS_dml1_display_rq_dlg_calc.o := $(dml_ccflags)
--
2.14.1

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[PATCH] drm/amd/display: Remove unused CFLAGS entry in DML Makefile

[Harry Wentland]

Missed that with a previous change that removed unused files.

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dml/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile 
b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 0271043cf6a2..f83a608f93e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -32,7 +32,6 @@ endif
 
 dml_ccflags := -mhard-float -msse $(cc_stack_align)
 
-CFLAGS_display_mode_vba.o := $(dml_ccflags)
 CFLAGS_display_mode_lib.o := $(dml_ccflags)
 CFLAGS_display_pipe_clocks.o := $(dml_ccflags)
 CFLAGS_dml1_display_rq_dlg_calc.o := $(dml_ccflags)
-- 
2.14.1

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Re: [PATCH v3 4/4] amdgpu/dc/calcs: Support clang option for stack alignment

[Harry Wentland]

On 2018-02-08 04:03 PM, Harry Wentland wrote:
> On 2018-02-08 03:53 PM, Matthias Kaehlcke wrote:
>> calcs uses the compiler option -mpreferred-stack-boundary=4 to configure
>> a stack alignment of 16 bytes. Clang uses the option -mstack-alignment
>> instead, which expects as parameter the alignment in bytes, and not a
>> power of two like -mpreferred-stack-boundary.
>>
>> Probe for both compiler options and use the correct one, similar to
>> what is done in arch/x86/Makefile.
>>
>> Signed-off-by: Matthias Kaehlcke 
> 
> Series is
> Reviewed-by: Harry Wentland 

... and merged to amd-staging-drm-next.

I had to resolve a small conflict with patches 1 & 2. Not a big deal but 
curious what development branch you use. We normally use this for amd-gfx 
development: 
https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next (although 
it might be a bit behind our internal dev tree).

Harry

> 
> Harry
> 
>> ---
>> Changes in v3:
>> - patch added
>>
>> Note to self: if this patterns proliferates further we probably want to
>> put the evaluation of the correct compiler flag in some common place.
>>
>>  drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
>> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> index af0f452f3c9f..95f332ee3e7e 100644
>> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> @@ -24,7 +24,13 @@
>>  # It calculates Bandwidth and Watermarks values for HW programming
>>  #
>>  
>> -calcs_ccflags := -mhard-float -msse -mpreferred-stack-boundary=4
>> +ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
>> +cc_stack_align := -mpreferred-stack-boundary=4
>> +else ifneq ($(call cc-option, -mstack-alignment=16),)
>> +cc_stack_align := -mstack-alignment=16
>> +endif
>> +
>> +calcs_ccflags := -mhard-float -msse $(cc_stack_align)
>>  
>>  CFLAGS_dcn_calcs.o := $(calcs_ccflags)
>>  CFLAGS_dcn_calc_auto.o := $(calcs_ccflags)
>>
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Re: [PATCH v3 4/4] amdgpu/dc/calcs: Support clang option for stack alignment

[Harry Wentland]

On 2018-02-08 03:53 PM, Matthias Kaehlcke wrote:
> calcs uses the compiler option -mpreferred-stack-boundary=4 to configure
> a stack alignment of 16 bytes. Clang uses the option -mstack-alignment
> instead, which expects as parameter the alignment in bytes, and not a
> power of two like -mpreferred-stack-boundary.
> 
> Probe for both compiler options and use the correct one, similar to
> what is done in arch/x86/Makefile.
> 
> Signed-off-by: Matthias Kaehlcke 

Series is
Reviewed-by: Harry Wentland 

Harry

> ---
> Changes in v3:
> - patch added
> 
> Note to self: if this patterns proliferates further we probably want to
> put the evaluation of the correct compiler flag in some common place.
> 
>  drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> index af0f452f3c9f..95f332ee3e7e 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> @@ -24,7 +24,13 @@
>  # It calculates Bandwidth and Watermarks values for HW programming
>  #
>  
> -calcs_ccflags := -mhard-float -msse -mpreferred-stack-boundary=4
> +ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
> + cc_stack_align := -mpreferred-stack-boundary=4
> +else ifneq ($(call cc-option, -mstack-alignment=16),)
> + cc_stack_align := -mstack-alignment=16
> +endif
> +
> +calcs_ccflags := -mhard-float -msse $(cc_stack_align)
>  
>  CFLAGS_dcn_calcs.o := $(calcs_ccflags)
>  CFLAGS_dcn_calc_auto.o := $(calcs_ccflags)
> 
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[PATCH v3 3/4] amdgpu/dc/dml: Support clang option for stack alignment

[Matthias Kaehlcke]

DML uses the compiler option -mpreferred-stack-boundary=4 to configure
a stack alignment of 16 bytes. Clang uses the option -mstack-alignment
instead, which expects as parameter the alignment in bytes, and not a
power of two like -mpreferred-stack-boundary.

Probe for both compiler options and use the correct one, similar to
what is done in arch/x86/Makefile.

Reported-by: Guenter Roeck 
Signed-off-by: Matthias Kaehlcke 
---
Changes in v3:
- adapted use of variable instead of subdir-ccflags-y

 drivers/gpu/drm/amd/display/dc/dml/Makefile | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile 
b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 96b337a03172..782886cac61c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -24,7 +24,13 @@
 # It provides the general basic services required by other DAL
 # subcomponents.
 
-dml_ccflags := -mhard-float -msse -mpreferred-stack-boundary=4
+ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+   cc_stack_align := -mpreferred-stack-boundary=4
+else ifneq ($(call cc-option, -mstack-alignment=16),)
+   cc_stack_align := -mstack-alignment=16
+endif
+
+dml_ccflags := -mhard-float -msse $(cc_stack_align)
 
 CFLAGS_display_mode_vba.o := $(dml_ccflags)
 CFLAGS_display_mode_lib.o := $(dml_ccflags)
-- 
2.16.0.rc1.238.g530d649a79-goog

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[PATCH v3 2/4] amdgpu/dc/calcs: Consolidate redundant CFLAGS

[Matthias Kaehlcke]

Use a variable for common CFLAGS instead of specifying the same flags
for every source file.

Signed-off-by: Matthias Kaehlcke 
---
Changes in v3:
- patch added

 drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 7959e382ed28..af0f452f3c9f 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -24,9 +24,11 @@
 # It calculates Bandwidth and Watermarks values for HW programming
 #
 
-CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
-CFLAGS_dcn_calc_auto.o := -mhard-float -msse -mpreferred-stack-boundary=4
-CFLAGS_dcn_calc_math.o := -mhard-float -msse -mpreferred-stack-boundary=4 
-Wno-tautological-compare
+calcs_ccflags := -mhard-float -msse -mpreferred-stack-boundary=4
+
+CFLAGS_dcn_calcs.o := $(calcs_ccflags)
+CFLAGS_dcn_calc_auto.o := $(calcs_ccflags)
+CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare
 
 BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
 
-- 
2.16.0.rc1.238.g530d649a79-goog

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[PATCH v3 4/4] amdgpu/dc/calcs: Support clang option for stack alignment

[Matthias Kaehlcke]

calcs uses the compiler option -mpreferred-stack-boundary=4 to configure
a stack alignment of 16 bytes. Clang uses the option -mstack-alignment
instead, which expects as parameter the alignment in bytes, and not a
power of two like -mpreferred-stack-boundary.

Probe for both compiler options and use the correct one, similar to
what is done in arch/x86/Makefile.

Signed-off-by: Matthias Kaehlcke 
---
Changes in v3:
- patch added

Note to self: if this patterns proliferates further we probably want to
put the evaluation of the correct compiler flag in some common place.

 drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index af0f452f3c9f..95f332ee3e7e 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -24,7 +24,13 @@
 # It calculates Bandwidth and Watermarks values for HW programming
 #
 
-calcs_ccflags := -mhard-float -msse -mpreferred-stack-boundary=4
+ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+   cc_stack_align := -mpreferred-stack-boundary=4
+else ifneq ($(call cc-option, -mstack-alignment=16),)
+   cc_stack_align := -mstack-alignment=16
+endif
+
+calcs_ccflags := -mhard-float -msse $(cc_stack_align)
 
 CFLAGS_dcn_calcs.o := $(calcs_ccflags)
 CFLAGS_dcn_calc_auto.o := $(calcs_ccflags)
-- 
2.16.0.rc1.238.g530d649a79-goog

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[PATCH 3/3] drm/amd/powerplay/hwmgr: Delete an unnecessary return statement in three functions

[SF Markus Elfring]

From: Markus Elfring 
Date: Thu, 8 Feb 2018 21:10:58 +0100

The script "checkpatch.pl" pointed information out like the following.

WARNING: void function return statements are not generally useful

Thus remove such a statement in the affected functions.

Signed-off-by: Markus Elfring 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 3 ---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 1 -
 2 files changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 2681c9317d25..e07b32491092 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -653,8 +653,6 @@ void phm_trim_voltage_table_to_fit_state_table(uint32_t 
max_vol_steps,
vol_table->entries[i] = vol_table->entries[i + diff];
 
vol_table->count = max_vol_steps;
-
-   return;
 }
 
 int phm_reset_single_dpm_table(void *table,
@@ -906,7 +904,6 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
 
phm_cap_set(hwmgr->platform_descriptor.platformCaps,

PHM_PlatformCaps_FanSpeedInTableIsRPM);
-   return;
 }
 
 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 2d55dabc77d4..fcdb3563d860 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3618,7 +3618,6 @@ static uint32_t vega10_find_highest_dpm_level(
 static void vega10_apply_dal_minimum_voltage_request(
struct pp_hwmgr *hwmgr)
 {
-   return;
 }
 
 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
-- 
2.16.1

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[PATCH 0/3] drm/amd/powerplay/hwmgr: Adjustments for eight function implementations

[SF Markus Elfring]

From: Markus Elfring 
Date: Thu, 8 Feb 2018 21:37:42 +0100

Three update suggestions were taken into account
from static source code analysis.

Markus Elfring (3):
  Delete an error message for a failed memory allocation in three functions
  Adjust layout for source code from five if statements
  Delete an unnecessary return statement in three functions

 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 37 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 35 +---
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c   |  5 +--
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c |  4 +--
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  1 -
 5 files changed, 35 insertions(+), 47 deletions(-)

-- 
2.16.1

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[PATCH 2/3] drm/amd/powerplay/hwmgr: Adjust layout for source code from five if statements

[SF Markus Elfring]

From: Markus Elfring 
Date: Thu, 8 Feb 2018 21:01:24 +0100

The script "checkpatch.pl" pointed information out like the following.

WARNING: Comparisons should place the constant on the right side
of the test
WARNING: else is not generally useful after a break or return

Thus fix the affected source code places.

Signed-off-by: Markus Elfring 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c   | 33 +++-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c  | 31 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c |  5 ++--
 3 files changed, 33 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index c0699b884894..870c517f2057 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1772,37 +1772,34 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int 
idx,
return 0;
case AMDGPU_PP_SENSOR_UVD_VCLK:
if (!cz_hwmgr->uvd_power_gated) {
-   if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
+   if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS)
return -EINVAL;
-   } else {
-   vclk = uvd_table->entries[uvd_index].vclk;
-   *((uint32_t *)value) = vclk;
-   return 0;
-   }
+
+   vclk = uvd_table->entries[uvd_index].vclk;
+   *((uint32_t *)value) = vclk;
+   return 0;
}
*((uint32_t *)value) = 0;
return 0;
case AMDGPU_PP_SENSOR_UVD_DCLK:
if (!cz_hwmgr->uvd_power_gated) {
-   if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
+   if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS)
return -EINVAL;
-   } else {
-   dclk = uvd_table->entries[uvd_index].dclk;
-   *((uint32_t *)value) = dclk;
-   return 0;
-   }
+
+   dclk = uvd_table->entries[uvd_index].dclk;
+   *((uint32_t *)value) = dclk;
+   return 0;
}
*((uint32_t *)value) = 0;
return 0;
case AMDGPU_PP_SENSOR_VCE_ECCLK:
if (!cz_hwmgr->vce_power_gated) {
-   if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
+   if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS)
return -EINVAL;
-   } else {
-   ecclk = vce_table->entries[vce_index].ecclk;
-   *((uint32_t *)value) = ecclk;
-   return 0;
-   }
+
+   ecclk = vce_table->entries[vce_index].ecclk;
+   *((uint32_t *)value) = ecclk;
+   return 0;
}
*((uint32_t *)value) = 0;
return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index ded33ed03f11..2681c9317d25 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -813,24 +813,23 @@ int 
phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr
/* initialize vddc_dep_on_dal_pwrl table */
table_size = sizeof(uint32_t) + 4 * sizeof(struct 
phm_clock_voltage_dependency_record);
table_clk_vlt = kzalloc(table_size, GFP_KERNEL);
-
-   if (NULL == table_clk_vlt) {
+   if (!table_clk_vlt)
return -ENOMEM;
-   } else {
-   table_clk_vlt->count = 4;
-   table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
-   table_clk_vlt->entries[0].v = 0;
-   table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
-   table_clk_vlt->entries[1].v = 720;
-   table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
-   table_clk_vlt->entries[2].v = 810;
-   table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
-   table_clk_vlt->entries[3].v = 900;
-   if (pptable_info != NULL)
-   pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
-   hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
-   }
 
+   table_clk_vlt->count = 4;
+   table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
+   table_clk_vlt->entries[0].v = 0;
+   table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
+   table_clk_vlt->entries[1].v = 720;

[PATCH 1/3] drm/amd/powerplay/hwmgr: Delete an error message for a failed memory allocation in three functions

[SF Markus Elfring]

From: Markus Elfring 
Date: Thu, 8 Feb 2018 20:32:39 +0100

Omit an extra message for a memory allocation failure in these functions.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 4 +---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 4 +---
 3 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index b314d09d41af..c0699b884894 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -286,10 +286,8 @@ static int cz_init_dynamic_state_adjustment_rule_settings(
struct phm_clock_voltage_dependency_table *table_clk_vlt =
kzalloc(table_size, GFP_KERNEL);
 
-   if (NULL == table_clk_vlt) {
-   pr_err("Can not allocate memory!\n");
+   if (!table_clk_vlt)
return -ENOMEM;
-   }
 
table_clk_vlt->count = 8;
table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 0229f774f7a9..ded33ed03f11 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -815,7 +815,6 @@ int 
phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr
table_clk_vlt = kzalloc(table_size, GFP_KERNEL);
 
if (NULL == table_clk_vlt) {
-   pr_err("Can not allocate space for vddc_dep_on_dal_pwrl! \n");
return -ENOMEM;
} else {
table_clk_vlt->count = 4;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 569073e3a5a1..967b93e56113 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -107,10 +107,8 @@ static int rv_init_dynamic_state_adjustment_rule_settings(
struct phm_clock_voltage_dependency_table *table_clk_vlt =
kzalloc(table_size, GFP_KERNEL);
 
-   if (NULL == table_clk_vlt) {
-   pr_err("Can not allocate memory!\n");
+   if (!table_clk_vlt)
return -ENOMEM;
-   }
 
table_clk_vlt->count = 8;
table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
-- 
2.16.1

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Re: [PATCH v2 1/2] amdgpu/dc/dml: Consolidate redundant CFLAGS

[Matthias Kaehlcke]

El Thu, Feb 08, 2018 at 09:33:53AM -0500 Harry Wentland ha dit:

> On 2018-02-07 08:51 PM, Matthias Kaehlcke wrote:
> > Use subdir-ccflags instead of specifying the same flags for every source
> > file.
> > 
> > Signed-off-by: Matthias Kaehlcke 
> > Reviewed-by: Guenter Roeck 
> > ---
> > Changes in v2:
> > - added 'Reviewed-by: Guenter Roeck ' tag
> > 
> >  drivers/gpu/drm/amd/display/dc/dml/Makefile | 10 +-
> >  1 file changed, 1 insertion(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile 
> > b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> > index 3488af2b5786..b8cadf833e71 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
> > +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> > @@ -24,15 +24,7 @@
> >  # It provides the general basic services required by other DAL
> >  # subcomponents.
> >  
> > -CFLAGS_display_mode_vba.o := -mhard-float -msse 
> > -mpreferred-stack-boundary=4
> > -CFLAGS_display_mode_lib.o := -mhard-float -msse 
> > -mpreferred-stack-boundary=4
> > -CFLAGS_display_pipe_clocks.o := -mhard-float -msse 
> > -mpreferred-stack-boundary=4
> > -CFLAGS_display_rq_dlg_calc.o := -mhard-float -msse 
> > -mpreferred-stack-boundary=4
> > -CFLAGS_dml1_display_rq_dlg_calc.o := -mhard-float -msse 
> > -mpreferred-stack-boundary=4
> > -CFLAGS_display_rq_dlg_helpers.o := -mhard-float -msse 
> > -mpreferred-stack-boundary=4
> > -CFLAGS_soc_bounding_box.o := -mhard-float -msse 
> > -mpreferred-stack-boundary=4
> > -CFLAGS_dml_common_defs.o := -mhard-float -msse -mpreferred-stack-boundary=4
> > -
> > +subdir-ccflags-y += -mhard-float -msse -mpreferred-stack-boundary=4
> 
> Are you sure this will only apply to dc/dml?
> 
> The way the amdgpu build is setup I've seen this flag apply to all of amdgpu, 
> even if specified in a subdirectories build file. The reason being that 
> amdgpu/Makefile recursively includes all other Makefiles in the module.
> 
> According to kbuild/makefiles.txt this will have effect for the kbuild file 
> where it's present and all subdirectories:
> 
> https://www.kernel.org/doc/Documentation/kbuild/makefiles.txt:
> > subdir-ccflags-y, subdir-asflags-y
> > The two flags listed above are similar to ccflags-y and asflags-y.
> > The difference is that the subdir- variants have effect for the kbuild
> > file where they are present and all subdirectories.
> > Options specified using subdir-* are added to the commandline before
> > the options specified using the non-subdir variants.
> > 
> > Example:
> > subdir-ccflags-y := -Werror

Thanks, I didn't realize the recursive inclusion from amdgpu/Makefile,
in this case using subdir-ccflags-y indeed isn't a good idea.

> For your 2nd patch you probably want to make a dml_cflags variable
> that's set different for clang and gcc, and then still set it for
> all files in DML individually.

Yep, that was my first impulse and then I remembered
subdir-ccflags-y. Will go back to that.

> You'll probably also have to do the same for dc/calcs/Makefile.

Thanks for the heads up!
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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Eric Huang]

Is the switching automatically by driver or manually by user?


Regards,

Eric


On 2018-02-08 11:54 AM, Zhu, Rex wrote:


>In case of compute, we have auto switching mechanism. when compute ring 
is coming, it switches to the default compute profile or user set 
profile, >and switches back when it's done. So VR should be doing the 
same thing with compute. Auto wattman will be disabled when profile 
auto switching >happens.



Rex: Ok, the logic is same.

when computer ring begins,  set manual dpm mode(pp do nothing except 
disable auto wattman feature), and set compute profile or  custom profile.


set clock range. and set auto dpm mode, switch back


Best Regards

Rex





*From:* amd-gfx  on behalf of 
Eric Huang 

*Sent:* Friday, February 9, 2018 12:47 AM
*To:* amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature 
on Polaris




On 2018-02-08 11:35 AM, Zhu, Rex wrote:


>But in auto mode, we may want to force a particular profile within the
>driver for a specific use case.  E.g., for VR, we may want to select
>the VR profile when the user sets the priority to high in the context
>ioctl, and then switch it back to autowattman or the default profile
>when the context if freed or the priority is changes.  We may want to
>do something similar for video when the user submits work to the
>multi-media engines.

>  I guess it should just be
>a matter of disabling autowattman and switching to a profile when the
>driver needs it and then switching back when it's done.


Rex:

       For MM, we can disable auto wattman (if enabled), and set 
video profile mode when enable uvd/vce dpm on smu7.


      restore to default when disable uvd/vce dpm when engine idle.

         VR, may be similar to compute case Eric have implemented, 
need user ctrl through sysfs.




In case of compute, we have auto switching mechanism. when compute 
ring is coming, it switches to the default compute profile or user set 
profile, and switches back when it's done. So VR should be doing the 
same thing with compute. Auto wattman will be disabled when profile 
auto switching happens.


Regards,
Eric

           Enter manual dpm mode(driver disable auto wattman), and 
select prefered profile mode, set sclk/mclk range(smu7).


            when enter auto dpm mode, restore default value.


>It's possible autowattman will perform ok and we
>don't need to manually change the profile in the driver, but we'll
>have to do some profiling to sorhat out.


Rex: Idealy, if autowan feature enabled, the proflling mode should be 
adjusted based on workload with  some time delay caused by the work 
queue.


But need some time to verify.


Best Regards

Rex




*From:* Alex Deucher  


*Sent:* Thursday, February 8, 2018 11:28 PM
*To:* Zhu, Rex
*Cc:* amd-gfx list
*Subject:* Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature 
on Polaris
On Thu, Feb 8, 2018 at 10:14 AM, Zhu, Rex  
 wrote:

> if user select manual dpm mode，we will disabe autowattman.
> When switch to auto, we will restart the auto wattman on Polaris,
> Restore to default profile mode on other ASICS.
>

But in auto mode, we may want to force a particular profile within the
driver for a specific use case.  E.g., for VR, we may want to select
the VR profile when the user sets the priority to high in the context
ioctl, and then switch it back to autowattman or the default profile
when the context if freed or the priority is changes.  We may want to
do something similar for video when the user submits work to the
multi-media engines.  It's possible autowattman will perform ok and we
don't need to manually change the profile in the driver, but we'll
have to do some profiling to sort that out.  I guess it should just be
a matter of disabling autowattman and switching to a profile when the
driver needs it and then switching back when it's done.

Alex

>
> Best Regards
> Rex
> 
> From: Alex Deucher  


> Sent: Thursday, February 8, 2018 11:02:21 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on
> Polaris
>
> On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  
 wrote:

>> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
>> Signed-off-by: Rex Zhu  
>
> Would be good to give a brief description of what autowattman actually
> does in the patch description.  Also, we may need to manually select a
> profile in some cases (e.g., VR).  Would that be a problem with
> autowattman?
>
> Alex
>
>> ---
>> 

Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Zhu, Rex]

>In case of compute, we have auto switching mechanism. when compute ring is 
>coming, it switches to the default compute profile or user set profile, >and 
>switches back when it's done. So VR should be doing the same thing with 
>compute. Auto wattman will be disabled when profile auto switching >happens.


Rex: Ok, the logic is same.



when computer ring begins,  set manual dpm mode(pp do nothing except disable 
auto wattman feature), and set compute profile or  custom profile.

set clock range. and set auto dpm mode, switch back


Best Regards

Rex






From: amd-gfx  on behalf of Eric Huang 

Sent: Friday, February 9, 2018 12:47 AM
To: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris



On 2018-02-08 11:35 AM, Zhu, Rex wrote:

>But in auto mode, we may want to force a particular profile within the
>driver for a specific use case.  E.g., for VR, we may want to select
>the VR profile when the user sets the priority to high in the context
>ioctl, and then switch it back to autowattman or the default profile
>when the context if freed or the priority is changes.  We may want to
>do something similar for video when the user submits work to the
>multi-media engines.

>  I guess it should just be
>a matter of disabling autowattman and switching to a profile when the
>driver needs it and then switching back when it's done.


Rex:

 For MM, we can disable auto wattman (if enabled), and set video 
profile mode when enable uvd/vce dpm on smu7.

restore to default when disable uvd/vce dpm when engine idle.



 VR, may be similar to compute case Eric have implemented, need user 
ctrl through sysfs.

In case of compute, we have auto switching mechanism. when compute ring is 
coming, it switches to the default compute profile or user set profile, and 
switches back when it's done. So VR should be doing the same thing with 
compute. Auto wattman will be disabled when profile auto switching happens.

Regards,
Eric


   Enter manual dpm mode(driver disable auto wattman), and select 
prefered profile mode, set sclk/mclk range(smu7).

when enter auto dpm mode, restore default value.


>It's possible autowattman will perform ok and we
>don't need to manually change the profile in the driver, but we'll
>have to do some profiling to sorhat out.


Rex: Idealy, if autowan feature enabled, the proflling mode should be adjusted 
based on workload with  some time delay caused by the work queue.

But need some time to verify.


Best Regards

Rex





From: Alex Deucher 
Sent: Thursday, February 8, 2018 11:28 PM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

On Thu, Feb 8, 2018 at 10:14 AM, Zhu, Rex 
 wrote:
> if user select manual dpm mode，we will disabe autowattman.
> When switch to auto, we will restart the auto wattman on Polaris,
> Restore to default profile mode on other ASICS.
>

But in auto mode, we may want to force a particular profile within the
driver for a specific use case.  E.g., for VR, we may want to select
the VR profile when the user sets the priority to high in the context
ioctl, and then switch it back to autowattman or the default profile
when the context if freed or the priority is changes.  We may want to
do something similar for video when the user submits work to the
multi-media engines.  It's possible autowattman will perform ok and we
don't need to manually change the profile in the driver, but we'll
have to do some profiling to sort that out.  I guess it should just be
a matter of disabling autowattman and switching to a profile when the
driver needs it and then switching back when it's done.

Alex

>
> Best Regards
> Rex
> 
> From: Alex Deucher 
> Sent: Thursday, February 8, 2018 11:02:21 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on
> Polaris
>
> On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu 
>  wrote:
>> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
>> Signed-off-by: Rex Zhu 
>
> Would be good to give a brief description of what autowattman actually
> does in the patch description.  Also, we may need to manually select a
> profile in some cases (e.g., VR).  Would that be a problem with
> autowattman?
>
> Alex
>
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> index f50b6cd..549e830 100644
>> --- 

Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Eric Huang]

On 2018-02-08 11:35 AM, Zhu, Rex wrote:


>But in auto mode, we may want to force a particular profile within the
>driver for a specific use case.  E.g., for VR, we may want to select
>the VR profile when the user sets the priority to high in the context
>ioctl, and then switch it back to autowattman or the default profile
>when the context if freed or the priority is changes.  We may want to
>do something similar for video when the user submits work to the
>multi-media engines.

>  I guess it should just be
>a matter of disabling autowattman and switching to a profile when the
>driver needs it and then switching back when it's done.


Rex:

         For MM, we can disable auto wattman (if enabled), and set 
video profile mode when enable uvd/vce dpm on smu7.


        restore to default when disable uvd/vce dpm when engine idle.

         VR, may be similar to compute case Eric have implemented, 
need user ctrl through sysfs.




In case of compute, we have auto switching mechanism. when compute ring 
is coming, it switches to the default compute profile or user set 
profile, and switches back when it's done. So VR should be doing the 
same thing with compute. Auto wattman will be disabled when profile auto 
switching happens.


Regards,
Eric

           Enter manual dpm mode(driver disable auto wattman), and 
select prefered profile mode, set sclk/mclk range(smu7).


            when enter auto dpm mode, restore default value.


>It's possible autowattman will perform ok and we
>don't need to manually change the profile in the driver, but we'll
>have to do some profiling to sorhat out. 



Rex: Idealy, if autowan feature enabled, the proflling mode should be 
adjusted based on workload with  some time delay caused by the work queue.


But need some time to verify.


Best Regards

Rex




*From:* Alex Deucher 
*Sent:* Thursday, February 8, 2018 11:28 PM
*To:* Zhu, Rex
*Cc:* amd-gfx list
*Subject:* Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature 
on Polaris

On Thu, Feb 8, 2018 at 10:14 AM, Zhu, Rex  wrote:
> if user select manual dpm mode，we will disabe autowattman.
> When switch to auto, we will restart the auto wattman on Polaris,
> Restore to default profile mode on other ASICS.
>

But in auto mode, we may want to force a particular profile within the
driver for a specific use case.  E.g., for VR, we may want to select
the VR profile when the user sets the priority to high in the context
ioctl, and then switch it back to autowattman or the default profile
when the context if freed or the priority is changes. We may want to
do something similar for video when the user submits work to the
multi-media engines.  It's possible autowattman will perform ok and we
don't need to manually change the profile in the driver, but we'll
have to do some profiling to sort that out.  I guess it should just be
a matter of disabling autowattman and switching to a profile when the
driver needs it and then switching back when it's done.

Alex

>
> Best Regards
> Rex
> 
> From: Alex Deucher 
> Sent: Thursday, February 8, 2018 11:02:21 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on
> Polaris
>
> On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
>> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
>> Signed-off-by: Rex Zhu 
>
> Would be good to give a brief description of what autowattman actually
> does in the patch description.  Also, we may need to manually select a
> profile in some cases (e.g., VR).  Would that be a problem with
> autowattman?
>
> Alex
>
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> index f50b6cd..549e830 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct 
pp_hwmgr

>> *hwmgr)
>> phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>>
>> PHM_PlatformCaps_TCPRamping);
>> }
>> +
>> +   if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
>> +   hwmgr->autowattman_enabled = true; /* currently only
>> enabled on polaris */
>> +
>> return 0;
>>  }
>>
>> --
>> 1.9.1
>>
>> ___
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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Zhu, Rex]

>But in auto mode, we may want to force a particular profile within the
>driver for a specific use case.  E.g., for VR, we may want to select
>the VR profile when the user sets the priority to high in the context
>ioctl, and then switch it back to autowattman or the default profile
>when the context if freed or the priority is changes.  We may want to
>do something similar for video when the user submits work to the
>multi-media engines.

>  I guess it should just be
>a matter of disabling autowattman and switching to a profile when the
>driver needs it and then switching back when it's done.


Rex:

 For MM, we can disable auto wattman (if enabled), and set video 
profile mode when enable uvd/vce dpm on smu7.

restore to default when disable uvd/vce dpm when engine idle.



 VR, may be similar to compute case Eric have implemented, need user 
ctrl through sysfs.



   Enter manual dpm mode(driver disable auto wattman), and select 
prefered profile mode, set sclk/mclk range(smu7).

when enter auto dpm mode, restore default value.


>It's possible autowattman will perform ok and we
>don't need to manually change the profile in the driver, but we'll
>have to do some profiling to sorhat out.


Rex: Idealy, if autowan feature enabled, the proflling mode should be adjusted 
based on workload with  some time delay caused by the work queue.

But need some time to verify.


Best Regards

Rex





From: Alex Deucher 
Sent: Thursday, February 8, 2018 11:28 PM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

On Thu, Feb 8, 2018 at 10:14 AM, Zhu, Rex  wrote:
> if user select manual dpm mode，we will disabe autowattman.
> When switch to auto, we will restart the auto wattman on Polaris,
> Restore to default profile mode on other ASICS.
>

But in auto mode, we may want to force a particular profile within the
driver for a specific use case.  E.g., for VR, we may want to select
the VR profile when the user sets the priority to high in the context
ioctl, and then switch it back to autowattman or the default profile
when the context if freed or the priority is changes.  We may want to
do something similar for video when the user submits work to the
multi-media engines.  It's possible autowattman will perform ok and we
don't need to manually change the profile in the driver, but we'll
have to do some profiling to sort that out.  I guess it should just be
a matter of disabling autowattman and switching to a profile when the
driver needs it and then switching back when it's done.

Alex

>
> Best Regards
> Rex
> 
> From: Alex Deucher 
> Sent: Thursday, February 8, 2018 11:02:21 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on
> Polaris
>
> On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
>> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
>> Signed-off-by: Rex Zhu 
>
> Would be good to give a brief description of what autowattman actually
> does in the patch description.  Also, we may need to manually select a
> profile in some cases (e.g., VR).  Would that be a problem with
> autowattman?
>
> Alex
>
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> index f50b6cd..549e830 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr
>> *hwmgr)
>> phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>>
>> PHM_PlatformCaps_TCPRamping);
>> }
>> +
>> +   if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
>> +   hwmgr->autowattman_enabled = true; /* currently only
>> enabled on polaris */
>> +
>> return 0;
>>  }
>>
>> --
>> 1.9.1
>>
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH] drm/amdgpu: add new device to use atpx quirk

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:46 AM, Kai-Heng Feng
 wrote:
> The affected system (0x0813) is pretty similar to another one (0x0812),
> it also needs to use ATPX power control.
>
> Signed-off-by: Kai-Heng Feng 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
> index e2c3c5ec42d1..c53095b3b0fb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
> @@ -568,6 +568,7 @@ static const struct amdgpu_px_quirk 
> amdgpu_px_quirk_list[] = {
> /* HG _PR3 doesn't seem to work on this A+A weston board */
> { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
> { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
> +   { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
> { 0, 0, 0, 0, 0 },
>  };
>
> --
> 2.15.1
>
> ___
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Re: [PATCH 04/10] drm/amd/pp: Implement update_dpm_settings on Polaris

[Eric Huang]

Again, it still has risk when updating smc table without calling 
smu7_freeze/unfreeze_sclk_mclk_dpm().


Regards,
Eric


On 2018-02-08 04:14 AM, Rex Zhu wrote:

Change-Id: I4533826ef6e18df125ae4445016873be3b5fe0ce
Signed-off-by: Rex Zhu 
---
  .../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 104 +
  1 file changed, 104 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index bfb2c85..559572d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -2575,6 +2575,109 @@ static int 
polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
array_size, SMC_RAM_END);
  }
  
+uint32_t polaris10_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)

+{
+   u32 mask = 0;
+   u32 shift = 0;
+
+   shift = (offset % 4) << 3;
+   if (size == sizeof(uint8_t))
+   mask = 0xFF << shift;
+   else if (size == sizeof(uint16_t))
+   mask = 0x << shift;
+
+   original_data &= ~mask;
+   original_data |= (field << shift);
+   return original_data;
+}
+
+static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
+   void *profile_setting)
+{
+   struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
+   (hwmgr->smu_backend);
+   struct profile_mode_setting *setting;
+   struct SMU74_Discrete_GraphicsLevel *levels =
+   smu_data->smc_state_table.GraphicsLevel;
+   uint32_t array = smu_data->smu7_data.dpm_table_start +
+   offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
+
+   uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
+   offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
+   struct SMU74_Discrete_MemoryLevel *mclk_levels =
+   smu_data->smc_state_table.MemoryLevel;
+   uint32_t i;
+   uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, 
tmp;
+
+   if (profile_setting == NULL)
+   return -EINVAL;
+
+   setting = (struct profile_mode_setting *)profile_setting;
+
+   if (setting->bupdate_sclk) {
+   for (i = 0; i < 
smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
+   if (levels[i].ActivityLevel !=
+   cpu_to_be16(setting->sclk_activity)) {
+   levels[i].ActivityLevel = 
cpu_to_be16(setting->sclk_activity);
+
+   clk_activity_offset = array + 
(sizeof(SMU74_Discrete_GraphicsLevel) * i)
+   + 
offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
+   offset = clk_activity_offset & ~0x3;
+   tmp = 
PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
offset));
+   tmp = 
polaris10_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, 
sizeof(uint16_t));
+   cgs_write_ind_register(hwmgr->device, 
CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+
+   }
+   if (levels[i].UpHyst != setting->sclk_up_hyst ||
+   levels[i].DownHyst != setting->sclk_down_hyst) {
+   levels[i].UpHyst = setting->sclk_up_hyst;
+   levels[i].DownHyst = setting->sclk_down_hyst;
+   up_hyst_offset = array + 
(sizeof(SMU74_Discrete_GraphicsLevel) * i)
+   + 
offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
+   down_hyst_offset = array + 
(sizeof(SMU74_Discrete_GraphicsLevel) * i)
+   + 
offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
+   offset = up_hyst_offset & ~0x3;
+   tmp = 
PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
offset));
+   tmp = 
polaris10_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, 
sizeof(uint8_t));
+   tmp = 
polaris10_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, 
sizeof(uint8_t));
+   cgs_write_ind_register(hwmgr->device, 
CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+   }
+   }
+   }
+
+   if (setting->bupdate_mclk) {
+   for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; 
i++) {
+   if (mclk_levels[i].ActivityLevel !=
+   cpu_to_be16(setting->mclk_activity)) {
+   

Re: [PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto wattman

[Zhu, Rex]

Thanks Harry for clarify this question thoroughly.


>We'll still need a patch to call this interface from DC. Is that on your plate 
>or is this something we should hook up?

No, I just implemented the interface in pp. DC need to call this function to 
enable/disable the auto wattman feature when  Freesync disable/enable.


Best Regards

Rex


From: Wentland, Harry
Sent: Thursday, February 8, 2018 11:28 PM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Cc: Koo, Anthony; Cyr, Aric
Subject: Re: [PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto wattman

On 2018-02-08 10:10 AM, Harry Wentland wrote:
> On 2018-02-08 10:07 AM, Zhu, Rex wrote:
>> when autowattman enabled，we will update uphyst/downhyst/min-sclk/mclk 
>> activity  value to smu based on the workload.
>>
>
> Why is this incompatible with Freesync?
>

Just had a chat with the Windows guys. Apparently AutoWattman changes clocks 
quite aggressively which can make framerates jump significantly and lead to a 
subpar experience when using Freesync.

We'll still need a patch to call this interface from DC. Is that on your plate 
or is this something we should hook up?

Harry

> Harry
>
>> Best Regards
>> Rex
>>
>> --
>> *From:* Wentland, Harry
>> *Sent:* Thursday, February 8, 2018 10:22:16 PM
>> *To:* Zhu, Rex; amd-gfx@lists.freedesktop.org
>> *Subject:* Re: [PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto 
>> wattman
>>
>> On 2018-02-08 06:20 AM, Rex Zhu wrote:
>>> Disable AutoWattman (if enabled) when FreeSync is enabled.
>>
>> Do you have a DC change calling this?
>>
>> What's the use case for this and why do we need to disable AutoWattman when 
>> Freesync is enabled?
>>
>> What does AutoWattman do?
>>
>> Harry
>>
>>>
>>> Change-Id: I9a531321d7913b8b40e60070c569a01c4f202002
>>> Signed-off-by: Rex Zhu 
>>> ---
>>>   drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
>>>   drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 25 
>>> +
>>>   2 files changed, 26 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
>>> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
>>> index 22c2fa3..f7bb565 100644
>>> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
>>> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
>>> @@ -313,6 +313,7 @@ struct amd_pm_funcs {
>>> int (*set_power_profile_mode)(void *handle, long *input, uint32_t 
>>> size);
>>> int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, 
>>> uint32_t size);
>>> int (*set_mmhub_powergating_by_smu)(void *handle);
>>> + int (*notify_free_sync_change)(void *handle, bool en);
>>>   };
>>>
>>>   #endif
>>> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
>>> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> index 376ed2d..d0306b6 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> @@ -1555,6 +1555,30 @@ static int pp_set_mmhub_powergating_by_smu(void 
>>> *handle)
>>> return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
>>>   }
>>>
>>> +static int pp_notify_free_sync_change(void *handle, bool en)
>>> +{
>>> + struct pp_hwmgr *hwmgr;
>>> + struct pp_instance *pp_handle = (struct pp_instance *)handle;
>>> + int ret = 0;
>>> +
>>> + ret = pp_check(pp_handle);
>>> +
>>> + if (ret)
>>> + return ret;
>>> +
>>> + hwmgr = pp_handle->hwmgr;
>>> +
>>> + mutex_lock(_handle->pp_lock);
>>> + if (hwmgr->autowattman_enabled) {
>>> + if (hwmgr->hwmgr_func->start_auto_wattman != NULL) {
>>> + if 
>>> (!cancel_delayed_work_sync(>wattman_update_work))
>>> + hwmgr->hwmgr_func->start_auto_wattman(hwmgr, 
>>> en);
>>> + }
>>> + }
>>> + mutex_unlock(_handle->pp_lock);
>>> + return 0;
>>> +}
>>> +
>>>   const struct amd_pm_funcs pp_dpm_funcs = {
>>> .load_firmware = 

Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Alex Deucher]

On Thu, Feb 8, 2018 at 10:14 AM, Zhu, Rex  wrote:
> if user select manual dpm mode，we will disabe autowattman.
> When switch to auto, we will restart the auto wattman on Polaris,
> Restore to default profile mode on other ASICS.
>

But in auto mode, we may want to force a particular profile within the
driver for a specific use case.  E.g., for VR, we may want to select
the VR profile when the user sets the priority to high in the context
ioctl, and then switch it back to autowattman or the default profile
when the context if freed or the priority is changes.  We may want to
do something similar for video when the user submits work to the
multi-media engines.  It's possible autowattman will perform ok and we
don't need to manually change the profile in the driver, but we'll
have to do some profiling to sort that out.  I guess it should just be
a matter of disabling autowattman and switching to a profile when the
driver needs it and then switching back when it's done.

Alex

>
> Best Regards
> Rex
> 
> From: Alex Deucher 
> Sent: Thursday, February 8, 2018 11:02:21 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on
> Polaris
>
> On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
>> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
>> Signed-off-by: Rex Zhu 
>
> Would be good to give a brief description of what autowattman actually
> does in the patch description.  Also, we may need to manually select a
> profile in some cases (e.g., VR).  Would that be a problem with
> autowattman?
>
> Alex
>
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> index f50b6cd..549e830 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr
>> *hwmgr)
>> phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>>
>> PHM_PlatformCaps_TCPRamping);
>> }
>> +
>> +   if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
>> +   hwmgr->autowattman_enabled = true; /* currently only
>> enabled on polaris */
>> +
>> return 0;
>>  }
>>
>> --
>> 1.9.1
>>
>> ___
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>> amd-gfx@lists.freedesktop.org
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Re: [PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto wattman

[Harry Wentland]

On 2018-02-08 10:10 AM, Harry Wentland wrote:
> On 2018-02-08 10:07 AM, Zhu, Rex wrote:
>> when autowattman enabled，we will update uphyst/downhyst/min-sclk/mclk 
>> activity  value to smu based on the workload.
>>
> 
> Why is this incompatible with Freesync?
> 

Just had a chat with the Windows guys. Apparently AutoWattman changes clocks 
quite aggressively which can make framerates jump significantly and lead to a 
subpar experience when using Freesync.

We'll still need a patch to call this interface from DC. Is that on your plate 
or is this something we should hook up?

Harry

> Harry
> 
>> Best Regards
>> Rex
>>
>> --
>> *From:* Wentland, Harry
>> *Sent:* Thursday, February 8, 2018 10:22:16 PM
>> *To:* Zhu, Rex; amd-gfx@lists.freedesktop.org
>> *Subject:* Re: [PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto 
>> wattman
>>  
>> On 2018-02-08 06:20 AM, Rex Zhu wrote:
>>> Disable AutoWattman (if enabled) when FreeSync is enabled.
>>
>> Do you have a DC change calling this?
>>
>> What's the use case for this and why do we need to disable AutoWattman when 
>> Freesync is enabled?
>>
>> What does AutoWattman do?
>>
>> Harry
>>
>>>
>>> Change-Id: I9a531321d7913b8b40e60070c569a01c4f202002
>>> Signed-off-by: Rex Zhu 
>>> ---
>>>   drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
>>>   drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 25 
>>> +
>>>   2 files changed, 26 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
>>> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
>>> index 22c2fa3..f7bb565 100644
>>> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
>>> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
>>> @@ -313,6 +313,7 @@ struct amd_pm_funcs {
>>>     int (*set_power_profile_mode)(void *handle, long *input, uint32_t 
>>> size);
>>>     int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, 
>>> uint32_t size);
>>>     int (*set_mmhub_powergating_by_smu)(void *handle);
>>> + int (*notify_free_sync_change)(void *handle, bool en);
>>>   };
>>>   
>>>   #endif
>>> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
>>> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> index 376ed2d..d0306b6 100644
>>> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>>> @@ -1555,6 +1555,30 @@ static int pp_set_mmhub_powergating_by_smu(void 
>>> *handle)
>>>     return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
>>>   }
>>>   
>>> +static int pp_notify_free_sync_change(void *handle, bool en)
>>> +{
>>> + struct pp_hwmgr *hwmgr;
>>> + struct pp_instance *pp_handle = (struct pp_instance *)handle;
>>> + int ret = 0;
>>> +
>>> + ret = pp_check(pp_handle);
>>> +
>>> + if (ret)
>>> + return ret;
>>> +
>>> + hwmgr = pp_handle->hwmgr;
>>> +
>>> + mutex_lock(_handle->pp_lock);
>>> + if (hwmgr->autowattman_enabled) {
>>> + if (hwmgr->hwmgr_func->start_auto_wattman != NULL) {
>>> + if 
>>> (!cancel_delayed_work_sync(>wattman_update_work))
>>> + hwmgr->hwmgr_func->start_auto_wattman(hwmgr, 
>>> en);
>>> + }
>>> + }
>>> + mutex_unlock(_handle->pp_lock);
>>> + return 0;
>>> +}
>>> +
>>>   const struct amd_pm_funcs pp_dpm_funcs = {
>>>     .load_firmware = pp_dpm_load_fw,
>>>     .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
>>> @@ -1604,4 +1628,5 @@ static int pp_set_mmhub_powergating_by_smu(void 
>>> *handle)
>>>     .display_clock_voltage_request = pp_display_clock_voltage_request,
>>>     .get_display_mode_validation_clocks = 
>>> pp_get_display_mode_validation_clocks,
>>>     .set_mmhub_powergating_by_smu = pp_set_mmhub_powergating_by_smu,
>>> + .notify_free_sync_change = pp_notify_free_sync_change,
>>>   };
>>>
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> amd-gfx mailing list
> 

Re: [PATCH v2 09/10] drm/amd/pp: Restore power profile mode in auto dpm level on smu7

[Alex Deucher]

On Thu, Feb 8, 2018 at 6:19 AM, Rex Zhu  wrote:
> v2: cancel or wait current work finish before restart auto wattman.
>
> Disable auto wattman feature in manual mode if feature is enabled
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

>
> Change-Id: I4361d16df27d2666dd978c3e33e05c020d65fe6a
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 19 +++
>  1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index b89b530..937b30a 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -82,6 +82,7 @@
>  #define TCLK(PCIE_BUS_CLK / 10)
>  #define WATTMAM_SAMPLE_PERIOD msecs_to_jiffies(1000)
>
> +static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, 
> uint32_t size);
>  static const struct profile_mode_setting smu7_profiling[5] =
> {{1, 0, 100, 30, 1, 0, 100, 10},
>  {1, 10, 0, 30, 0, 0, 0, 0},
> @@ -2792,6 +2793,19 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
> ret = smu7_force_dpm_lowest(hwmgr);
> break;
> case AMD_DPM_FORCED_LEVEL_AUTO:
> +   if (hwmgr->autowattman_enabled) {
> +   if (hwmgr->hwmgr_func->start_auto_wattman != NULL) {
> +   if 
> (!cancel_delayed_work_sync(>wattman_update_work))
> +   
> hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
> +   }
> +   } else {
> +   if (hwmgr->default_power_profile_mode != 
> hwmgr->power_profile_mode) {
> +   long mode = hwmgr->default_power_profile_mode;
> +
> +   smu7_set_power_profile_mode(hwmgr, , 0);
> +   }
> +
> +   }
> ret = smu7_unforce_dpm_levels(hwmgr);
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> @@ -2806,6 +2820,11 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
> smu7_force_clock_level(hwmgr, PP_PCIE, 1< break;
> case AMD_DPM_FORCED_LEVEL_MANUAL:
> +   if (hwmgr->autowattman_enabled) {
> +   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
> +   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, 
> false);
> +   }
> +   break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
> default:
> break;
> --
> 1.9.1
>
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Re: [PATCH v2 08/10] drm/amd/pp: Implement auto wattman feature on Smu7

[Alex Deucher]

On Thu, Feb 8, 2018 at 6:18 AM, Rex Zhu  wrote:
> v2: refine work queue name.
>
> Change-Id: I2521d83cbea9b3418bed63de86cf93deafaab3fb
> Signed-off-by: Rex Zhu 

Please provide a patch description.  With that fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c  |  35 
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 200 
> ++-
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h |  26 +++
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h|   2 +
>  4 files changed, 262 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 33eabc1..b7f4a31 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -236,6 +236,20 @@ int hwmgr_early_init(struct pp_instance *handle)
> return 0;
>  }
>
> +static void wattman_sample_handler(struct work_struct *work)
> +{
> +   struct pp_hwmgr *hwmgr =
> +   container_of(work, struct pp_hwmgr, wattman_update_work.work);
> +
> +   if (hwmgr->autowattman_enabled) {
> +   if (hwmgr->hwmgr_func->update_auto_wattman != NULL)
> +   hwmgr->hwmgr_func->update_auto_wattman(hwmgr);
> +
> +   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
> +   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
> +   }
> +}
> +
>  int hwmgr_hw_init(struct pp_instance *handle)
>  {
> struct pp_hwmgr *hwmgr;
> @@ -246,6 +260,8 @@ int hwmgr_hw_init(struct pp_instance *handle)
>
> hwmgr = handle->hwmgr;
>
> +   INIT_DELAYED_WORK(>wattman_update_work, 
> wattman_sample_handler);
> +
> if (hwmgr->pptable_func == NULL ||
> hwmgr->pptable_func->pptable_init == NULL ||
> hwmgr->hwmgr_func->backend_init == NULL)
> @@ -279,6 +295,11 @@ int hwmgr_hw_init(struct pp_instance *handle)
> if (ret)
> goto err2;
>
> +   if (hwmgr->autowattman_enabled) {
> +   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
> +   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
> +   }
> +
> return 0;
>  err2:
> if (hwmgr->hwmgr_func->backend_fini)
> @@ -300,6 +321,10 @@ int hwmgr_hw_fini(struct pp_instance *handle)
>
> hwmgr = handle->hwmgr;
>
> +   if (hwmgr->autowattman_enabled) {
> +   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
> +   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, false);
> +   }
> phm_stop_thermal_controller(hwmgr);
> psm_set_boot_states(hwmgr);
> psm_adjust_power_state_dynamic(hwmgr, false, NULL);
> @@ -322,6 +347,11 @@ int hwmgr_hw_suspend(struct pp_instance *handle)
> return -EINVAL;
>
> hwmgr = handle->hwmgr;
> +
> +   if (hwmgr->autowattman_enabled) {
> +   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
> +   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, false);
> +   }
> phm_disable_smc_firmware_ctf(hwmgr);
> ret = psm_set_boot_states(hwmgr);
> if (ret)
> @@ -360,6 +390,11 @@ int hwmgr_hw_resume(struct pp_instance *handle)
>
> ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
>
> +   if (hwmgr->autowattman_enabled) {
> +   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
> +   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
> +   }
> +
> return ret;
>  }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 08e9e44..b89b530 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -80,6 +80,7 @@
>
>  #define PCIE_BUS_CLK1
>  #define TCLK(PCIE_BUS_CLK / 10)
> +#define WATTMAM_SAMPLE_PERIOD msecs_to_jiffies(1000)
>
>  static const struct profile_mode_setting smu7_profiling[5] =
> {{1, 0, 100, 30, 1, 0, 100, 10},
> @@ -2540,9 +2541,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr 
> *hwmgr)
> data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
> else
> data->pcie_gen_cap = (uint32_t)sys_info.value;
> +
> if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
> data->pcie_spc_cap = 20;
> -   sys_info.size = sizeof(struct cgs_system_info);
> +
> sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
> result = cgs_query_system_info(hwmgr->device, _info);
> if (result)
> @@ -2550,6 +2552,11 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr 
> *hwmgr)
> else
>

Re: [PATCH 07/10] drm/amd/pp: Add new hw interface for auto wattman feature.

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
> Change-Id: Ib34c2815ab95890ba91f9a61bc0594b0f5e0c3fd
> Signed-off-by: Rex Zhu 

Please provide a patch description.  With that fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 31988d7..d809d96 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -351,6 +351,8 @@ struct pp_hwmgr_func {
> long *input, uint32_t size);
> int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
> int (*set_mmhub_powergating_by_smu)(struct pp_hwmgr *hwmgr);
> +   int (*update_auto_wattman)(struct pp_hwmgr *hwmgr);
> +   void (*start_auto_wattman)(struct pp_hwmgr *hwmgr, bool en);
>  };
>
>  struct pp_table_func {
> --
> 1.9.1
>
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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Zhu, Rex]

if user select manual dpm mode，we will disabe autowattman.
When switch to auto, we will restart the auto wattman on Polaris,
Restore to default profile mode on other ASICS.


Best Regards
Rex

From: Alex Deucher 
Sent: Thursday, February 8, 2018 11:02:21 PM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
> Signed-off-by: Rex Zhu 

Would be good to give a brief description of what autowattman actually
does in the patch description.  Also, we may need to manually select a
profile in some cases (e.g., VR).  Would that be a problem with
autowattman?

Alex

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index f50b6cd..549e830 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr 
> *hwmgr)
> phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> 
> PHM_PlatformCaps_TCPRamping);
> }
> +
> +   if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
> +   hwmgr->autowattman_enabled = true; /* currently only enabled 
> on polaris */
> +
> return 0;
>  }
>
> --
> 1.9.1
>
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Re: [PATCH 06/10] drm/amd/pp: Implement set_power_profile_mode on smu7

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
> User can set smu7 dpm pamameters through sysfs
>
> Depending on the workloads,
> user can echo "0/1/2/3/4">pp_power_profile_mode
> to select 3D_FULL_SCREEN/POWER_SAVING/VIDEO/VR/COMPUTE
> mode.
>
> echo "5 * * * * * * * *">pp_power_profile_mode
> to config custom mode.
> "5 * * * * * * * *" mean "CUSTOM enable_sclk SCLK_UP_HYST
> SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL enable_mclk MCLK_UP_HYST
> MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL"
>
> if the parameter enable_sclk/enable_mclk is true,
> driver will update the following parameters to dpm table.
> if false, ignore the following parameters.
>
> Change-Id: I8b5fc6fb2e20e6cd50b4184458452ac22c562469
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 52 
> 
>  1 file changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 8cf95d9..08e9e44 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -5019,6 +5019,57 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr 
> *hwmgr, char *buf)
> return size;
>  }
>
> +static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, 
> uint32_t size)
> +{
> +   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +   struct profile_mode_setting tmp;
> +
> +   hwmgr->power_profile_mode = input[size];
> +
> +   switch (hwmgr->power_profile_mode) {
> +   case PP_SMC_POWER_PROFILE_CUSTOM:
> +   if (size < 8)
> +   return -EINVAL;
> +
> +   data->custom_profile_setting.bupdate_sclk = input[0];
> +   data->custom_profile_setting.sclk_up_hyst = input[1];
> +   data->custom_profile_setting.sclk_down_hyst = input[2];
> +   data->custom_profile_setting.sclk_activity =  input[3];
> +   data->custom_profile_setting.bupdate_mclk = input[4];
> +   data->custom_profile_setting.mclk_up_hyst = input[5];
> +   data->custom_profile_setting.mclk_down_hyst = input[6];
> +   data->custom_profile_setting.mclk_activity =  input[7];
> +   if (!smum_update_dpm_settings(hwmgr, 
> >custom_profile_setting))
> +   memcpy(>current_profile_setting, 
> >custom_profile_setting, sizeof(struct profile_mode_setting));
> +   break;
> +   case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
> +   case PP_SMC_POWER_PROFILE_POWERSAVING:
> +   case PP_SMC_POWER_PROFILE_VIDEO:
> +   case PP_SMC_POWER_PROFILE_VR:
> +   case PP_SMC_POWER_PROFILE_COMPUTE:
> +   memcpy(, _profiling[hwmgr->power_profile_mode], 
> sizeof(struct profile_mode_setting));
> +   if (!smum_update_dpm_settings(hwmgr, )) {

Won't the lack of an update_dpm_settings mean we can't manually select
power profiles on non-polaris asics?  Didn't your previous patches
allow this on non-polaris parts?

Alex

> +   if (tmp.bupdate_sclk) {
> +   data->current_profile_setting.bupdate_sclk = 
> tmp.bupdate_sclk;
> +   data->current_profile_setting.sclk_up_hyst = 
> tmp.sclk_up_hyst;
> +   data->current_profile_setting.sclk_down_hyst 
> = tmp.sclk_down_hyst;
> +   data->current_profile_setting.sclk_activity = 
> tmp.sclk_activity;
> +   }
> +   if (tmp.bupdate_mclk) {
> +   data->current_profile_setting.bupdate_mclk = 
> tmp.bupdate_mclk;
> +   data->current_profile_setting.mclk_up_hyst = 
> tmp.mclk_up_hyst;
> +   data->current_profile_setting.mclk_down_hyst 
> = tmp.mclk_down_hyst;
> +   data->current_profile_setting.mclk_activity = 
> tmp.mclk_activity;
> +   }
> +   }
> +   break;
> +   default:
> +   return -EINVAL;
> +   }
> +
> +   return 0;
> +}
> +
>  static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
> .backend_init = _hwmgr_backend_init,
> .backend_fini = _hwmgr_backend_fini,
> @@ -5075,6 +5126,7 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr 
> *hwmgr, char *buf)
> .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
> .set_power_limit = smu7_set_power_limit,
> .get_power_profile_mode = smu7_get_power_profile_mode,
> +   .set_power_profile_mode = smu7_set_power_profile_mode,
>  };
>
>  uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> --
> 1.9.1
>
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Re: [PATCH 05/10] drm/amd/pp: Implement get_power_profile_mode on smu7

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
> It show what parameters can be setted on smu7(vi/ci asics)
> to get better performance.
>
> Also show some profiling modes, user can select directly
> by serial number based on workloads.
>
> cat pp_power_profile_mode
> NUMMODE_NAME SCLK_UP_HYST   SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL 
> MCLK_UP_HYST   MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL
>   0   3D_FULL_SCREEN:0  100   30  
>   0  100   10
>   1 POWER_SAVING:   100   30  
>   ---
>   2VIDEO:---  
>  10   16   31
>   3   VR:0   11   50  
>   0  100   10
>   4  COMPUTE:05   30  
>   ---
>   5   CUSTOM:000  
>   000
>   *  CURRENT:0  100   30  
>   0  100   10
>
> Change-Id: If0e9796d6cbe531ce1eb5ff181fe2f5f956437b6
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 87 
> 
>  1 file changed, 87 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 9379713..8cf95d9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -81,6 +81,21 @@
>  #define PCIE_BUS_CLK1
>  #define TCLK(PCIE_BUS_CLK / 10)
>
> +static const struct profile_mode_setting smu7_profiling[5] =
> +   {{1, 0, 100, 30, 1, 0, 100, 10},
> +{1, 10, 0, 30, 0, 0, 0, 0},
> +{0, 0, 0, 0, 1, 10, 16, 31},
> +{1, 0, 11, 50, 1, 0, 100, 10},
> +{1, 0, 5, 30, 0, 0, 0, 0},
> +   };
> +
> +static const struct profile_mode_setting polaris11_profiling[5] =
> +   {{1, 0, 100, 30, 1, 0, 100, 10},
> +{1, 10, 0, 30, 0, 0, 0, 0},
> +{0, 0, 0, 0, 1, 10, 16, 62},
> +{1, 0, 11, 50, 1, 0, 100, 10},
> +{1, 0, 5, 30, 0, 0, 0, 0},
> +   };
>
>  /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
>  enum DPM_EVENT_SRC {
> @@ -4932,6 +4947,77 @@ static int smu7_odn_edit_dpm_table(struct pp_hwmgr 
> *hwmgr,
> return 0;
>  }
>
> +static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
> +{
> +   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +   uint32_t i, size = 0;
> +   uint32_t len;
> +
> +   static const char *profile_name[6] = {"3D_FULL_SCREEN",
> +   "POWER_SAVING",
> +   "VIDEO",
> +   "VR",
> +   "COMPUTE",
> +   "CUSTOM"};
> +
> +   static const char *title[8] = {"NUM",
> +   "MODE_NAME",
> +   "SCLK_UP_HYST",
> +   "SCLK_DOWN_HYST",
> +   "SCLK_ACTIVE_LEVEL",
> +   "MCLK_UP_HYST",
> +   "MCLK_DOWN_HYST",
> +   "MCLK_ACTIVE_LEVEL"};
> +
> +   if (!buf)
> +   return -EINVAL;
> +
> +   size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
> +   title[0], title[1], title[2], title[3],
> +   title[4], title[5], title[6], title[7]);
> +
> +   len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
> +
> +   for (i = 0; i < len; i++) {
> +   if (smu7_profiling[i].bupdate_sclk)
> +   size += sprintf(buf + size, "%3d %16s: %8d %16d %16d 
> ",
> +   i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
> +   smu7_profiling[i].sclk_down_hyst,
> +   smu7_profiling[i].sclk_activity);
> +   else
> +   size += sprintf(buf + size, "%3d %16s: %8s %16s %16s 
> ",
> +   i, profile_name[i], "-", "-", "-");
> +
> +   if (smu7_profiling[i].bupdate_mclk)
> +   size += 

Re: [PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto wattman

[Harry Wentland]

On 2018-02-08 10:07 AM, Zhu, Rex wrote:
> when autowattman enabled，we will update uphyst/downhyst/min-sclk/mclk 
> activity  value to smu based on the workload.
> 

Why is this incompatible with Freesync?

Harry

> Best Regards
> Rex
> 
> --
> *From:* Wentland, Harry
> *Sent:* Thursday, February 8, 2018 10:22:16 PM
> *To:* Zhu, Rex; amd-gfx@lists.freedesktop.org
> *Subject:* Re: [PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto 
> wattman
>  
> On 2018-02-08 06:20 AM, Rex Zhu wrote:
>> Disable AutoWattman (if enabled) when FreeSync is enabled.
> 
> Do you have a DC change calling this?
> 
> What's the use case for this and why do we need to disable AutoWattman when 
> Freesync is enabled?
> 
> What does AutoWattman do?
> 
> Harry
> 
>> 
>> Change-Id: I9a531321d7913b8b40e60070c569a01c4f202002
>> Signed-off-by: Rex Zhu 
>> ---
>>  drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
>>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 25 
>>+
>>  2 files changed, 26 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
>> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
>> index 22c2fa3..f7bb565 100644
>> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
>> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
>> @@ -313,6 +313,7 @@ struct amd_pm_funcs {
>>    int (*set_power_profile_mode)(void *handle, long *input, uint32_t 
>>size);
>>    int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, 
>>uint32_t size);
>>    int (*set_mmhub_powergating_by_smu)(void *handle);
>> + int (*notify_free_sync_change)(void *handle, bool en);
>>  };
>>  
>>  #endif
>> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
>> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> index 376ed2d..d0306b6 100644
>> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>> @@ -1555,6 +1555,30 @@ static int pp_set_mmhub_powergating_by_smu(void 
>> *handle)
>>    return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
>>  }
>>  
>> +static int pp_notify_free_sync_change(void *handle, bool en)
>> +{
>> + struct pp_hwmgr *hwmgr;
>> + struct pp_instance *pp_handle = (struct pp_instance *)handle;
>> + int ret = 0;
>> +
>> + ret = pp_check(pp_handle);
>> +
>> + if (ret)
>> + return ret;
>> +
>> + hwmgr = pp_handle->hwmgr;
>> +
>> + mutex_lock(_handle->pp_lock);
>> + if (hwmgr->autowattman_enabled) {
>> + if (hwmgr->hwmgr_func->start_auto_wattman != NULL) {
>> + if 
>> (!cancel_delayed_work_sync(>wattman_update_work))
>> + hwmgr->hwmgr_func->start_auto_wattman(hwmgr, 
>> en);
>> + }
>> + }
>> + mutex_unlock(_handle->pp_lock);
>> + return 0;
>> +}
>> +
>>  const struct amd_pm_funcs pp_dpm_funcs = {
>>    .load_firmware = pp_dpm_load_fw,
>>    .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
>> @@ -1604,4 +1628,5 @@ static int pp_set_mmhub_powergating_by_smu(void 
>> *handle)
>>    .display_clock_voltage_request = pp_display_clock_voltage_request,
>>    .get_display_mode_validation_clocks = 
>>pp_get_display_mode_validation_clocks,
>>    .set_mmhub_powergating_by_smu = pp_set_mmhub_powergating_by_smu,
>> + .notify_free_sync_change = pp_notify_free_sync_change,
>>  };
>> 
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Re: [PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto wattman

[Zhu, Rex]

when autowattman enabled，we will update uphyst/downhyst/min-sclk/mclk activity  
value to smu based on the workload.

Best Regards
Rex


From: Wentland, Harry
Sent: Thursday, February 8, 2018 10:22:16 PM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto wattman

On 2018-02-08 06:20 AM, Rex Zhu wrote:
> Disable AutoWattman (if enabled) when FreeSync is enabled.

Do you have a DC change calling this?

What's the use case for this and why do we need to disable AutoWattman when 
Freesync is enabled?

What does AutoWattman do?

Harry

>
> Change-Id: I9a531321d7913b8b40e60070c569a01c4f202002
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 25 +
>  2 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 22c2fa3..f7bb565 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -313,6 +313,7 @@ struct amd_pm_funcs {
>int (*set_power_profile_mode)(void *handle, long *input, uint32_t 
> size);
>int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, 
> uint32_t size);
>int (*set_mmhub_powergating_by_smu)(void *handle);
> + int (*notify_free_sync_change)(void *handle, bool en);
>  };
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 376ed2d..d0306b6 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1555,6 +1555,30 @@ static int pp_set_mmhub_powergating_by_smu(void 
> *handle)
>return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
>  }
>
> +static int pp_notify_free_sync_change(void *handle, bool en)
> +{
> + struct pp_hwmgr *hwmgr;
> + struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + int ret = 0;
> +
> + ret = pp_check(pp_handle);
> +
> + if (ret)
> + return ret;
> +
> + hwmgr = pp_handle->hwmgr;
> +
> + mutex_lock(_handle->pp_lock);
> + if (hwmgr->autowattman_enabled) {
> + if (hwmgr->hwmgr_func->start_auto_wattman != NULL) {
> + if 
> (!cancel_delayed_work_sync(>wattman_update_work))
> + hwmgr->hwmgr_func->start_auto_wattman(hwmgr, 
> en);
> + }
> + }
> + mutex_unlock(_handle->pp_lock);
> + return 0;
> +}
> +
>  const struct amd_pm_funcs pp_dpm_funcs = {
>.load_firmware = pp_dpm_load_fw,
>.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
> @@ -1604,4 +1628,5 @@ static int pp_set_mmhub_powergating_by_smu(void *handle)
>.display_clock_voltage_request = pp_display_clock_voltage_request,
>.get_display_mode_validation_clocks = 
> pp_get_display_mode_validation_clocks,
>.set_mmhub_powergating_by_smu = pp_set_mmhub_powergating_by_smu,
> + .notify_free_sync_change = pp_notify_free_sync_change,
>  };
>
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Re: [PATCH 04/10] drm/amd/pp: Implement update_dpm_settings on Polaris

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
> Change-Id: I4533826ef6e18df125ae4445016873be3b5fe0ce
> Signed-off-by: Rex Zhu 

Please provide a patch description, with that fixed:
Reviewed-by: Alex Deucher 

> ---
>  .../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 104 
> +
>  1 file changed, 104 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> index bfb2c85..559572d 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> @@ -2575,6 +2575,109 @@ static int 
> polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
> array_size, SMC_RAM_END);
>  }
>
> +uint32_t polaris10_set_field_to_u32(u32 offset, u32 original_data, u32 
> field, u32 size)
> +{
> +   u32 mask = 0;
> +   u32 shift = 0;
> +
> +   shift = (offset % 4) << 3;
> +   if (size == sizeof(uint8_t))
> +   mask = 0xFF << shift;
> +   else if (size == sizeof(uint16_t))
> +   mask = 0x << shift;
> +
> +   original_data &= ~mask;
> +   original_data |= (field << shift);
> +   return original_data;
> +}
> +
> +static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
> +   void *profile_setting)
> +{
> +   struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
> +   (hwmgr->smu_backend);
> +   struct profile_mode_setting *setting;
> +   struct SMU74_Discrete_GraphicsLevel *levels =
> +   smu_data->smc_state_table.GraphicsLevel;
> +   uint32_t array = smu_data->smu7_data.dpm_table_start +
> +   offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
> +
> +   uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
> +   offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
> +   struct SMU74_Discrete_MemoryLevel *mclk_levels =
> +   smu_data->smc_state_table.MemoryLevel;
> +   uint32_t i;
> +   uint32_t offset, up_hyst_offset, down_hyst_offset, 
> clk_activity_offset, tmp;
> +
> +   if (profile_setting == NULL)
> +   return -EINVAL;
> +
> +   setting = (struct profile_mode_setting *)profile_setting;
> +
> +   if (setting->bupdate_sclk) {
> +   for (i = 0; i < 
> smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
> +   if (levels[i].ActivityLevel !=
> +   cpu_to_be16(setting->sclk_activity)) {
> +   levels[i].ActivityLevel = 
> cpu_to_be16(setting->sclk_activity);
> +
> +   clk_activity_offset = array + 
> (sizeof(SMU74_Discrete_GraphicsLevel) * i)
> +   + 
> offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
> +   offset = clk_activity_offset & ~0x3;
> +   tmp = 
> PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
> offset));
> +   tmp = 
> polaris10_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, 
> sizeof(uint16_t));
> +   cgs_write_ind_register(hwmgr->device, 
> CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
> +
> +   }
> +   if (levels[i].UpHyst != setting->sclk_up_hyst ||
> +   levels[i].DownHyst != 
> setting->sclk_down_hyst) {
> +   levels[i].UpHyst = setting->sclk_up_hyst;
> +   levels[i].DownHyst = setting->sclk_down_hyst;
> +   up_hyst_offset = array + 
> (sizeof(SMU74_Discrete_GraphicsLevel) * i)
> +   + 
> offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
> +   down_hyst_offset = array + 
> (sizeof(SMU74_Discrete_GraphicsLevel) * i)
> +   + 
> offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
> +   offset = up_hyst_offset & ~0x3;
> +   tmp = 
> PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
> offset));
> +   tmp = 
> polaris10_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, 
> sizeof(uint8_t));
> +   tmp = 
> polaris10_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, 
> sizeof(uint8_t));
> +   cgs_write_ind_register(hwmgr->device, 
> CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
> +   }
> +   }
> +   }
> +
> +   if (setting->bupdate_mclk) {
> +   for (i = 0; i < 
> 

Re: [PATCH 03/10] drm/amd/pp: Add new smu callback function

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
> it is used for adjust part of dpm settigs
> to get better performance under different
> workloads.
>
> Change-Id: I1e1ed786e9c07c91fb7e810af5b1ec5dd5cc4791
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
>  drivers/gpu/drm/amd/powerplay/inc/smumgr.h| 1 +
>  drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 8 
>  3 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 77d7f49..31988d7 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -239,6 +239,7 @@ struct pp_smumgr_func {
> int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
> struct amd_pp_profile *request);
> bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
> +   int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void 
> *profile_setting);
>  };
>
>  struct pp_hwmgr_func {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
> b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
> index b1b27b2..e05a57e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
> @@ -134,5 +134,6 @@ extern int smum_populate_requested_graphic_levels(struct 
> pp_hwmgr *hwmgr,
>
>  extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
>
> +extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void 
> *profile_setting);
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 
> b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
> index 8673884..1ce4959 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
> @@ -253,3 +253,11 @@ bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
>
> return false;
>  }
> +
> +int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting)
> +{
> +   if (hwmgr->smumgr_funcs->update_dpm_settings)
> +   return hwmgr->smumgr_funcs->update_dpm_settings(hwmgr, 
> profile_setting);
> +
> +   return -EINVAL;
> +}
> --
> 1.9.1
>
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Re: [PATCH 02/10] drm/amdgpu: Add a pp feature mask bit for autowattman

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
> Change-Id: Ie329d6c806fc5ab71417ffabe413ddbdf9d367ea
> Signed-off-by: Rex Zhu 

Please provide a better patch description.  With that fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 2 +-
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index d3f5ee5..e2011d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -121,7 +121,7 @@
>  uint amdgpu_sdma_phase_quantum = 32;
>  char *amdgpu_disable_cu = NULL;
>  char *amdgpu_virtual_display = NULL;
> -uint amdgpu_pp_feature_mask = 0x3fff;
> +uint amdgpu_pp_feature_mask = 0xbfff;
>  int amdgpu_ngg = 0;
>  int amdgpu_prim_buf_per_se = 0;
>  int amdgpu_pos_buf_per_se = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 2a59ee8..77d7f49 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -85,6 +85,7 @@ enum PP_FEATURE_MASK {
> PP_SOCCLK_DPM_MASK = 0x1000,
> PP_DCEFCLK_DPM_MASK = 0x2000,
> PP_OVERDRIVE_MASK = 0x4000,
> +   PP_AUTOWATTMAN_MASK = 0x8000,
>  };
>
>  enum PHM_BackEnd_Magic {
> --
> 1.9.1
>
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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
> Signed-off-by: Rex Zhu 

Would be good to give a brief description of what autowattman actually
does in the patch description.  Also, we may need to manually select a
profile in some cases (e.g., VR).  Would that be a problem with
autowattman?

Alex

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index f50b6cd..549e830 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr 
> *hwmgr)
> phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> 
> PHM_PlatformCaps_TCPRamping);
> }
> +
> +   if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
> +   hwmgr->autowattman_enabled = true; /* currently only enabled 
> on polaris */
> +
> return 0;
>  }
>
> --
> 1.9.1
>
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Re: [PATCH v2 1/2] amdgpu/dc/dml: Consolidate redundant CFLAGS

[Harry Wentland]

On 2018-02-07 08:51 PM, Matthias Kaehlcke wrote:
> Use subdir-ccflags instead of specifying the same flags for every source
> file.
> 
> Signed-off-by: Matthias Kaehlcke 
> Reviewed-by: Guenter Roeck 
> ---
> Changes in v2:
> - added 'Reviewed-by: Guenter Roeck ' tag
> 
>  drivers/gpu/drm/amd/display/dc/dml/Makefile | 10 +-
>  1 file changed, 1 insertion(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile 
> b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> index 3488af2b5786..b8cadf833e71 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> @@ -24,15 +24,7 @@
>  # It provides the general basic services required by other DAL
>  # subcomponents.
>  
> -CFLAGS_display_mode_vba.o := -mhard-float -msse -mpreferred-stack-boundary=4
> -CFLAGS_display_mode_lib.o := -mhard-float -msse -mpreferred-stack-boundary=4
> -CFLAGS_display_pipe_clocks.o := -mhard-float -msse 
> -mpreferred-stack-boundary=4
> -CFLAGS_display_rq_dlg_calc.o := -mhard-float -msse 
> -mpreferred-stack-boundary=4
> -CFLAGS_dml1_display_rq_dlg_calc.o := -mhard-float -msse 
> -mpreferred-stack-boundary=4
> -CFLAGS_display_rq_dlg_helpers.o := -mhard-float -msse 
> -mpreferred-stack-boundary=4
> -CFLAGS_soc_bounding_box.o := -mhard-float -msse -mpreferred-stack-boundary=4
> -CFLAGS_dml_common_defs.o := -mhard-float -msse -mpreferred-stack-boundary=4
> -
> +subdir-ccflags-y += -mhard-float -msse -mpreferred-stack-boundary=4

Are you sure this will only apply to dc/dml?

The way the amdgpu build is setup I've seen this flag apply to all of amdgpu, 
even if specified in a subdirectories build file. The reason being that 
amdgpu/Makefile recursively includes all other Makefiles in the module.

According to kbuild/makefiles.txt this will have effect for the kbuild file 
where it's present and all subdirectories:

https://www.kernel.org/doc/Documentation/kbuild/makefiles.txt:
> subdir-ccflags-y, subdir-asflags-y
>   The two flags listed above are similar to ccflags-y and asflags-y.
>   The difference is that the subdir- variants have effect for the kbuild
>   file where they are present and all subdirectories.
>   Options specified using subdir-* are added to the commandline before
>   the options specified using the non-subdir variants.
> 
>   Example:
>   subdir-ccflags-y := -Werror

For your 2nd patch you probably want to make a dml_cflags variable that's set 
different for clang and gcc, and then still set it for all files in DML 
individually.

You'll probably also have to do the same for dc/calcs/Makefile.

Thanks for finding a good solution for supporting clang. It's been on my list 
but I haven't had time to find the right flag yet.

Harry

>  
>  DML = display_mode_lib.o display_rq_dlg_calc.o \
> display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
> 
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Re: [PATCH 01/10] drm/amd/amdgpu: Add query vram width in CGS query system info

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu  wrote:
> Change-Id: I4bf7abab944253c8c744c1290b8a9fb5a62b6240
> Signed-off-by: Rex Zhu 

Please add a patch description that explains what we will be using
this for.  With that fixed:

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 3 +++
>  drivers/gpu/drm/amd/include/cgs_common.h | 1 +
>  2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> index 71b4aec..1f4e37b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> @@ -905,6 +905,9 @@ static int amdgpu_cgs_query_system_info(struct cgs_device 
> *cgs_device,
> case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN:
> sys_info->value = adev->pdev->devfn;
> break;
> +   case CGS_SYSTEM_INFO_VRAM_WIDTH:
> +   sys_info->value = adev->gmc.vram_width;
> +   break;
> default:
> return -ENODEV;
> }
> diff --git a/drivers/gpu/drm/amd/include/cgs_common.h 
> b/drivers/gpu/drm/amd/include/cgs_common.h
> index f5c7397..98cf4ce 100644
> --- a/drivers/gpu/drm/amd/include/cgs_common.h
> +++ b/drivers/gpu/drm/amd/include/cgs_common.h
> @@ -101,6 +101,7 @@ enum cgs_system_info_id {
> CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
> CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
> CGS_SYSTEM_INFO_PCIE_BUS_DEVFN,
> +   CGS_SYSTEM_INFO_VRAM_WIDTH,
> CGS_SYSTEM_INFO_ID_MAXIMUM,
>  };
>
> --
> 1.9.1
>
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Re: [PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto wattman

[Harry Wentland]

On 2018-02-08 06:20 AM, Rex Zhu wrote:
> Disable AutoWattman (if enabled) when FreeSync is enabled.

Do you have a DC change calling this?

What's the use case for this and why do we need to disable AutoWattman when 
Freesync is enabled?

What does AutoWattman do?

Harry

> 
> Change-Id: I9a531321d7913b8b40e60070c569a01c4f202002
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 25 +
>  2 files changed, 26 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 22c2fa3..f7bb565 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -313,6 +313,7 @@ struct amd_pm_funcs {
>   int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
>   int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, 
> uint32_t size);
>   int (*set_mmhub_powergating_by_smu)(void *handle);
> + int (*notify_free_sync_change)(void *handle, bool en);
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 376ed2d..d0306b6 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1555,6 +1555,30 @@ static int pp_set_mmhub_powergating_by_smu(void 
> *handle)
>   return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
>  }
>  
> +static int pp_notify_free_sync_change(void *handle, bool en)
> +{
> + struct pp_hwmgr *hwmgr;
> + struct pp_instance *pp_handle = (struct pp_instance *)handle;
> + int ret = 0;
> +
> + ret = pp_check(pp_handle);
> +
> + if (ret)
> + return ret;
> +
> + hwmgr = pp_handle->hwmgr;
> +
> + mutex_lock(_handle->pp_lock);
> + if (hwmgr->autowattman_enabled) {
> + if (hwmgr->hwmgr_func->start_auto_wattman != NULL) {
> + if 
> (!cancel_delayed_work_sync(>wattman_update_work))
> + hwmgr->hwmgr_func->start_auto_wattman(hwmgr, 
> en);
> + }
> + }
> + mutex_unlock(_handle->pp_lock);
> + return 0;
> +}
> +
>  const struct amd_pm_funcs pp_dpm_funcs = {
>   .load_firmware = pp_dpm_load_fw,
>   .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
> @@ -1604,4 +1628,5 @@ static int pp_set_mmhub_powergating_by_smu(void *handle)
>   .display_clock_voltage_request = pp_display_clock_voltage_request,
>   .get_display_mode_validation_clocks = 
> pp_get_display_mode_validation_clocks,
>   .set_mmhub_powergating_by_smu = pp_set_mmhub_powergating_by_smu,
> + .notify_free_sync_change = pp_notify_free_sync_change,
>  };
> 
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Re: [PATCH 3/4] drm/ttm: add input parameter force_alloc for ttm_bo_evict_mm

[Christian König]

Am 08.02.2018 um 10:06 schrieb Roger He:

if true, allocate TTM pages regardless of zone global memory
account limit. For suspend, We should avoid TTM memory allocate
failure then result in suspend failure.


Why the extra parameter for amdgpu_bo_evict_vram ?

I can't think of an use case when we don't want this to succeed.

Christian.



Signed-off-by: Roger He 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h  |  2 +-
  drivers/gpu/drm/nouveau/nouveau_drm.c   |  2 +-
  drivers/gpu/drm/qxl/qxl_object.c|  4 ++--
  drivers/gpu/drm/radeon/radeon_device.c  |  6 +++---
  drivers/gpu/drm/radeon/radeon_object.c  |  5 +++--
  drivers/gpu/drm/radeon/radeon_object.h  |  3 ++-
  drivers/gpu/drm/ttm/ttm_bo.c| 16 ++--
  drivers/gpu/drm/vmwgfx/vmwgfx_drv.c |  6 +++---
  include/drm/ttm/ttm_bo_api.h|  5 -
  12 files changed, 34 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index ee76b46..59ee12c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -763,7 +763,7 @@ static int amdgpu_debugfs_evict_vram(struct seq_file *m, 
void *data)
struct drm_device *dev = node->minor->dev;
struct amdgpu_device *adev = dev->dev_private;
  
-	seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev));

+   seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev, true));
return 0;
  }
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index e3fa3d7..3c5f9ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2168,7 +2168,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
suspend, bool fbcon)
}
}
/* evict vram memory */
-   amdgpu_bo_evict_vram(adev);
+   amdgpu_bo_evict_vram(adev, true);
  
  	amdgpu_fence_driver_suspend(adev);
  
@@ -2178,7 +2178,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)

 * This second call to evict vram is to evict the gart page table
 * using the CPU.
 */
-   amdgpu_bo_evict_vram(adev);
+   amdgpu_bo_evict_vram(adev, true);
  
  	pci_save_state(dev->pdev);

if (suspend) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0338ef6..db813f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -803,14 +803,14 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
return r;
  }
  
-int amdgpu_bo_evict_vram(struct amdgpu_device *adev)

+int amdgpu_bo_evict_vram(struct amdgpu_device *adev, bool force_alloc)
  {
/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
if (0 && (adev->flags & AMD_IS_APU)) {
/* Useless to evict on IGP chips */
return 0;
}
-   return ttm_bo_evict_mm(>mman.bdev, TTM_PL_VRAM);
+   return ttm_bo_evict_mm(>mman.bdev, TTM_PL_VRAM, force_alloc);
  }
  
  static const char *amdgpu_vram_names[] = {

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index c2b02f5..6724cdc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -227,7 +227,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
 u64 min_offset, u64 max_offset,
 u64 *gpu_addr);
  int amdgpu_bo_unpin(struct amdgpu_bo *bo);
-int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
+int amdgpu_bo_evict_vram(struct amdgpu_device *adev, bool force_alloc);
  int amdgpu_bo_init(struct amdgpu_device *adev);
  void amdgpu_bo_fini(struct amdgpu_device *adev);
  int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c 
b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 8d4a5be..c9627ef 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -702,7 +702,7 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime)
}
  
  	NV_DEBUG(drm, "evicting buffers...\n");

-   ttm_bo_evict_mm(>ttm.bdev, TTM_PL_VRAM);
+   ttm_bo_evict_mm(>ttm.bdev, TTM_PL_VRAM, true);
  
  	NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");

if (drm->cechan) {
diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c
index f6b80fe..d8d26c8 100644
--- a/drivers/gpu/drm/qxl/qxl_object.c
+++ b/drivers/gpu/drm/qxl/qxl_object.c
@@ -350,10 +350,10 @@ int qxl_bo_check_id(struct qxl_device *qdev, struct 
qxl_bo *bo)
  
  int 

Re: [PATCH 2/4] drm/ttm: add bit flag TTM_OPT_FLAG_FORCE_ALLOC

[Christian König]

Am 08.02.2018 um 10:05 schrieb Roger He:

set TTM_OPT_FLAG_FORCE_ALLOC when we are servicing for page
fault routine.

for ttm_mem_global_reserve if in page fault routine, allow the gtt
pages reservation always. because page fault routing already grabbed
system memory and the allowance of this exception is harmless.
Otherwise, it will trigger OOM killer.

the subsequent patche will use this.

v2: keep original behavior except ttm bo with flag no_retry

Signed-off-by: Roger He 
---
  drivers/gpu/drm/ttm/ttm_bo_vm.c  | 6 --
  drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 1 -
  include/drm/ttm/ttm_bo_api.h | 4 +++-
  3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index 716e724..f10b8a0 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -224,7 +224,7 @@ static int ttm_bo_vm_fault(struct vm_fault *vmf)
cvma.vm_page_prot = ttm_io_prot(bo->mem.placement,
cvma.vm_page_prot);
} else {
-   struct ttm_operation_ctx ctx = {
+   struct ttm_operation_ctx ttm_opt_ctx = {
.interruptible = false,
.no_wait_gpu = false
};
@@ -233,8 +233,10 @@ static int ttm_bo_vm_fault(struct vm_fault *vmf)
cvma.vm_page_prot = ttm_io_prot(bo->mem.placement,
cvma.vm_page_prot);
  
+		if (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY)

+   ttm_opt_ctx.flags |= TTM_OPT_FLAG_FORCE_ALLOC;


Can't we always set the TTM_OPT_FLAG_FORCE_ALLOC flag here?

I don't see a reason why we should ever not set it.

Christian.


/* Allocate all page at once, most common usage */
-   if (ttm->bdev->driver->ttm_tt_populate(ttm, )) {
+   if (ttm->bdev->driver->ttm_tt_populate(ttm, _opt_ctx)) {
ret = VM_FAULT_OOM;
goto out_io_unlock;
}
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index b122f6e..354e0e1 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -944,7 +944,6 @@ int ttm_dma_populate(struct ttm_dma_tt *ttm_dma, struct 
device *dev,
i = 0;
  
  	type = ttm_to_type(ttm->page_flags, ttm->caching_state);

-
  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
if (ttm->page_flags & TTM_PAGE_FLAG_DMA32)
goto skip_huge;
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index 872ff6c..2142639 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -278,7 +278,9 @@ struct ttm_operation_ctx {
  };
  
  /* Allow eviction of reserved BOs */

-#define TTM_OPT_FLAG_ALLOW_RES_EVICT   0x1
+#define TTM_OPT_FLAG_ALLOW_RES_EVICT   0x1
+/* when serving page fault or suspend, allow alloc anyway */
+#define TTM_OPT_FLAG_FORCE_ALLOC   0x2
  
  /**

   * ttm_bo_reference - reference a struct ttm_buffer_object


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[PATCH] drm/amd/pp: Expose new interface to DC to ctrl auto wattman

[Rex Zhu]

Disable AutoWattman (if enabled) when FreeSync is enabled.

Change-Id: I9a531321d7913b8b40e60070c569a01c4f202002
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 25 +
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 22c2fa3..f7bb565 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -313,6 +313,7 @@ struct amd_pm_funcs {
int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, 
uint32_t size);
int (*set_mmhub_powergating_by_smu)(void *handle);
+   int (*notify_free_sync_change)(void *handle, bool en);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 376ed2d..d0306b6 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1555,6 +1555,30 @@ static int pp_set_mmhub_powergating_by_smu(void *handle)
return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
 }
 
+static int pp_notify_free_sync_change(void *handle, bool en)
+{
+   struct pp_hwmgr *hwmgr;
+   struct pp_instance *pp_handle = (struct pp_instance *)handle;
+   int ret = 0;
+
+   ret = pp_check(pp_handle);
+
+   if (ret)
+   return ret;
+
+   hwmgr = pp_handle->hwmgr;
+
+   mutex_lock(_handle->pp_lock);
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL) {
+   if 
(!cancel_delayed_work_sync(>wattman_update_work))
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, 
en);
+   }
+   }
+   mutex_unlock(_handle->pp_lock);
+   return 0;
+}
+
 const struct amd_pm_funcs pp_dpm_funcs = {
.load_firmware = pp_dpm_load_fw,
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1604,4 +1628,5 @@ static int pp_set_mmhub_powergating_by_smu(void *handle)
.display_clock_voltage_request = pp_display_clock_voltage_request,
.get_display_mode_validation_clocks = 
pp_get_display_mode_validation_clocks,
.set_mmhub_powergating_by_smu = pp_set_mmhub_powergating_by_smu,
+   .notify_free_sync_change = pp_notify_free_sync_change,
 };
-- 
1.9.1

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[PATCH v2 09/10] drm/amd/pp: Restore power profile mode in auto dpm level on smu7

[Rex Zhu]

v2: cancel or wait current work finish before restart auto wattman.

Disable auto wattman feature in manual mode if feature is enabled
Signed-off-by: Rex Zhu 

Change-Id: I4361d16df27d2666dd978c3e33e05c020d65fe6a
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b89b530..937b30a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -82,6 +82,7 @@
 #define TCLK(PCIE_BUS_CLK / 10)
 #define WATTMAM_SAMPLE_PERIOD msecs_to_jiffies(1000)
 
+static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, 
uint32_t size);
 static const struct profile_mode_setting smu7_profiling[5] =
{{1, 0, 100, 30, 1, 0, 100, 10},
 {1, 10, 0, 30, 0, 0, 0, 0},
@@ -2792,6 +2793,19 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
ret = smu7_force_dpm_lowest(hwmgr);
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL) {
+   if 
(!cancel_delayed_work_sync(>wattman_update_work))
+   
hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+   }
+   } else {
+   if (hwmgr->default_power_profile_mode != 
hwmgr->power_profile_mode) {
+   long mode = hwmgr->default_power_profile_mode;
+
+   smu7_set_power_profile_mode(hwmgr, , 0);
+   }
+
+   }
ret = smu7_unforce_dpm_levels(hwmgr);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
@@ -2806,6 +2820,11 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
smu7_force_clock_level(hwmgr, PP_PCIE, 1<autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, 
false);
+   }
+   break;
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
default:
break;
-- 
1.9.1

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[PATCH v2 08/10] drm/amd/pp: Implement auto wattman feature on Smu7

[Rex Zhu]

v2: refine work queue name.

Change-Id: I2521d83cbea9b3418bed63de86cf93deafaab3fb
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c  |  35 
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 200 ++-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h |  26 +++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h|   2 +
 4 files changed, 262 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 33eabc1..b7f4a31 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -236,6 +236,20 @@ int hwmgr_early_init(struct pp_instance *handle)
return 0;
 }
 
+static void wattman_sample_handler(struct work_struct *work)
+{
+   struct pp_hwmgr *hwmgr =
+   container_of(work, struct pp_hwmgr, wattman_update_work.work);
+
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->update_auto_wattman != NULL)
+   hwmgr->hwmgr_func->update_auto_wattman(hwmgr);
+
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+   }
+}
+
 int hwmgr_hw_init(struct pp_instance *handle)
 {
struct pp_hwmgr *hwmgr;
@@ -246,6 +260,8 @@ int hwmgr_hw_init(struct pp_instance *handle)
 
hwmgr = handle->hwmgr;
 
+   INIT_DELAYED_WORK(>wattman_update_work, wattman_sample_handler);
+
if (hwmgr->pptable_func == NULL ||
hwmgr->pptable_func->pptable_init == NULL ||
hwmgr->hwmgr_func->backend_init == NULL)
@@ -279,6 +295,11 @@ int hwmgr_hw_init(struct pp_instance *handle)
if (ret)
goto err2;
 
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+   }
+
return 0;
 err2:
if (hwmgr->hwmgr_func->backend_fini)
@@ -300,6 +321,10 @@ int hwmgr_hw_fini(struct pp_instance *handle)
 
hwmgr = handle->hwmgr;
 
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, false);
+   }
phm_stop_thermal_controller(hwmgr);
psm_set_boot_states(hwmgr);
psm_adjust_power_state_dynamic(hwmgr, false, NULL);
@@ -322,6 +347,11 @@ int hwmgr_hw_suspend(struct pp_instance *handle)
return -EINVAL;
 
hwmgr = handle->hwmgr;
+
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, false);
+   }
phm_disable_smc_firmware_ctf(hwmgr);
ret = psm_set_boot_states(hwmgr);
if (ret)
@@ -360,6 +390,11 @@ int hwmgr_hw_resume(struct pp_instance *handle)
 
ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+   }
+
return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 08e9e44..b89b530 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -80,6 +80,7 @@
 
 #define PCIE_BUS_CLK1
 #define TCLK(PCIE_BUS_CLK / 10)
+#define WATTMAM_SAMPLE_PERIOD msecs_to_jiffies(1000)
 
 static const struct profile_mode_setting smu7_profiling[5] =
{{1, 0, 100, 30, 1, 0, 100, 10},
@@ -2540,9 +2541,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr 
*hwmgr)
data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
else
data->pcie_gen_cap = (uint32_t)sys_info.value;
+
if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
data->pcie_spc_cap = 20;
-   sys_info.size = sizeof(struct cgs_system_info);
+
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
result = cgs_query_system_info(hwmgr->device, _info);
if (result)
@@ -2550,6 +2552,11 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr 
*hwmgr)
else
data->pcie_lane_cap = (uint32_t)sys_info.value;
 
+   sys_info.info_id = CGS_SYSTEM_INFO_VRAM_WIDTH;
+   result = cgs_query_system_info(hwmgr->device, _info);
+   if (!result)
+   data->memory_bit_width = (uint32_t)sys_info.value;
+
hwmgr->platform_descriptor.vbiosInterruptId = 0x2400; /* 
IRQ_SOURCE1_SW_INT */
 

[PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Rex Zhu]

Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index f50b6cd..549e830 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,

PHM_PlatformCaps_TCPRamping);
}
+
+   if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
+   hwmgr->autowattman_enabled = true; /* currently only enabled on 
polaris */
+
return 0;
 }
 
-- 
1.9.1

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[PATCH 09/10] drm/amd/pp: Restore power profile mode in auto dpm level on smu7

[Rex Zhu]

Disable auto wattman feature in manual mode if feature is enabled
Signed-off-by: Rex Zhu 

Change-Id: I4361d16df27d2666dd978c3e33e05c020d65fe6a
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 943d3ec..3ecd869 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -82,6 +82,7 @@
 #define TCLK(PCIE_BUS_CLK / 10)
 #define WATTMAM_SAMPLE_PERIOD msecs_to_jiffies(1000)
 
+static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, 
uint32_t size);
 static const struct profile_mode_setting smu7_profiling[5] =
{{1, 0, 100, 30, 1, 0, 100, 10},
 {1, 10, 0, 30, 0, 0, 0, 0},
@@ -2792,6 +2793,17 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
ret = smu7_force_dpm_lowest(hwmgr);
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, 
true);
+   } else {
+   if (hwmgr->default_power_profile_mode != 
hwmgr->power_profile_mode) {
+   long mode = hwmgr->default_power_profile_mode;
+
+   smu7_set_power_profile_mode(hwmgr, , 0);
+   }
+
+   }
ret = smu7_unforce_dpm_levels(hwmgr);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
@@ -2806,6 +2818,11 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
smu7_force_clock_level(hwmgr, PP_PCIE, 1<autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, 
false);
+   }
+   break;
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
default:
break;
-- 
1.9.1

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[PATCH 08/10] drm/amd/pp: Implement auto wattman feature on Smu7

[Rex Zhu]

Change-Id: Id0826f7a12a30461fca38862904f2f20c811989a
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c  |  35 
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 200 ++-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h |  26 +++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h|   2 +
 4 files changed, 262 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 33eabc1..f50b6cd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -236,6 +236,20 @@ int hwmgr_early_init(struct pp_instance *handle)
return 0;
 }
 
+static void wattman_sample_handler(struct work_struct *work)
+{
+   struct pp_hwmgr *hwmgr =
+   container_of(work, struct pp_hwmgr, wattman_idle_work.work);
+
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->update_auto_wattman != NULL)
+   hwmgr->hwmgr_func->update_auto_wattman(hwmgr);
+
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+   }
+}
+
 int hwmgr_hw_init(struct pp_instance *handle)
 {
struct pp_hwmgr *hwmgr;
@@ -246,6 +260,8 @@ int hwmgr_hw_init(struct pp_instance *handle)
 
hwmgr = handle->hwmgr;
 
+   INIT_DELAYED_WORK(>wattman_idle_work, wattman_sample_handler);
+
if (hwmgr->pptable_func == NULL ||
hwmgr->pptable_func->pptable_init == NULL ||
hwmgr->hwmgr_func->backend_init == NULL)
@@ -279,6 +295,11 @@ int hwmgr_hw_init(struct pp_instance *handle)
if (ret)
goto err2;
 
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+   }
+
return 0;
 err2:
if (hwmgr->hwmgr_func->backend_fini)
@@ -300,6 +321,10 @@ int hwmgr_hw_fini(struct pp_instance *handle)
 
hwmgr = handle->hwmgr;
 
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, false);
+   }
phm_stop_thermal_controller(hwmgr);
psm_set_boot_states(hwmgr);
psm_adjust_power_state_dynamic(hwmgr, false, NULL);
@@ -322,6 +347,11 @@ int hwmgr_hw_suspend(struct pp_instance *handle)
return -EINVAL;
 
hwmgr = handle->hwmgr;
+
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, false);
+   }
phm_disable_smc_firmware_ctf(hwmgr);
ret = psm_set_boot_states(hwmgr);
if (ret)
@@ -360,6 +390,11 @@ int hwmgr_hw_resume(struct pp_instance *handle)
 
ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 
+   if (hwmgr->autowattman_enabled) {
+   if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+   hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+   }
+
return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 08e9e44..943d3ec 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -80,6 +80,7 @@
 
 #define PCIE_BUS_CLK1
 #define TCLK(PCIE_BUS_CLK / 10)
+#define WATTMAM_SAMPLE_PERIOD msecs_to_jiffies(1000)
 
 static const struct profile_mode_setting smu7_profiling[5] =
{{1, 0, 100, 30, 1, 0, 100, 10},
@@ -2540,9 +2541,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr 
*hwmgr)
data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
else
data->pcie_gen_cap = (uint32_t)sys_info.value;
+
if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
data->pcie_spc_cap = 20;
-   sys_info.size = sizeof(struct cgs_system_info);
+
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
result = cgs_query_system_info(hwmgr->device, _info);
if (result)
@@ -2550,6 +2552,11 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr 
*hwmgr)
else
data->pcie_lane_cap = (uint32_t)sys_info.value;
 
+   sys_info.info_id = CGS_SYSTEM_INFO_VRAM_WIDTH;
+   result = cgs_query_system_info(hwmgr->device, _info);
+   if (!result)
+   data->memory_bit_width = (uint32_t)sys_info.value;
+
hwmgr->platform_descriptor.vbiosInterruptId = 0x2400; /* 
IRQ_SOURCE1_SW_INT */
 /* The true clock step depends on 

[PATCH 06/10] drm/amd/pp: Implement set_power_profile_mode on smu7

[Rex Zhu]

User can set smu7 dpm pamameters through sysfs

Depending on the workloads,
user can echo "0/1/2/3/4">pp_power_profile_mode
to select 3D_FULL_SCREEN/POWER_SAVING/VIDEO/VR/COMPUTE
mode.

echo "5 * * * * * * * *">pp_power_profile_mode
to config custom mode.
"5 * * * * * * * *" mean "CUSTOM enable_sclk SCLK_UP_HYST
SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL enable_mclk MCLK_UP_HYST
MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL"

if the parameter enable_sclk/enable_mclk is true,
driver will update the following parameters to dpm table.
if false, ignore the following parameters.

Change-Id: I8b5fc6fb2e20e6cd50b4184458452ac22c562469
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 52 
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 8cf95d9..08e9e44 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -5019,6 +5019,57 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr 
*hwmgr, char *buf)
return size;
 }
 
+static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, 
uint32_t size)
+{
+   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+   struct profile_mode_setting tmp;
+
+   hwmgr->power_profile_mode = input[size];
+
+   switch (hwmgr->power_profile_mode) {
+   case PP_SMC_POWER_PROFILE_CUSTOM:
+   if (size < 8)
+   return -EINVAL;
+
+   data->custom_profile_setting.bupdate_sclk = input[0];
+   data->custom_profile_setting.sclk_up_hyst = input[1];
+   data->custom_profile_setting.sclk_down_hyst = input[2];
+   data->custom_profile_setting.sclk_activity =  input[3];
+   data->custom_profile_setting.bupdate_mclk = input[4];
+   data->custom_profile_setting.mclk_up_hyst = input[5];
+   data->custom_profile_setting.mclk_down_hyst = input[6];
+   data->custom_profile_setting.mclk_activity =  input[7];
+   if (!smum_update_dpm_settings(hwmgr, 
>custom_profile_setting))
+   memcpy(>current_profile_setting, 
>custom_profile_setting, sizeof(struct profile_mode_setting));
+   break;
+   case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
+   case PP_SMC_POWER_PROFILE_POWERSAVING:
+   case PP_SMC_POWER_PROFILE_VIDEO:
+   case PP_SMC_POWER_PROFILE_VR:
+   case PP_SMC_POWER_PROFILE_COMPUTE:
+   memcpy(, _profiling[hwmgr->power_profile_mode], 
sizeof(struct profile_mode_setting));
+   if (!smum_update_dpm_settings(hwmgr, )) {
+   if (tmp.bupdate_sclk) {
+   data->current_profile_setting.bupdate_sclk = 
tmp.bupdate_sclk;
+   data->current_profile_setting.sclk_up_hyst = 
tmp.sclk_up_hyst;
+   data->current_profile_setting.sclk_down_hyst = 
tmp.sclk_down_hyst;
+   data->current_profile_setting.sclk_activity = 
tmp.sclk_activity;
+   }
+   if (tmp.bupdate_mclk) {
+   data->current_profile_setting.bupdate_mclk = 
tmp.bupdate_mclk;
+   data->current_profile_setting.mclk_up_hyst = 
tmp.mclk_up_hyst;
+   data->current_profile_setting.mclk_down_hyst = 
tmp.mclk_down_hyst;
+   data->current_profile_setting.mclk_activity = 
tmp.mclk_activity;
+   }
+   }
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = _hwmgr_backend_init,
.backend_fini = _hwmgr_backend_fini,
@@ -5075,6 +5126,7 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr 
*hwmgr, char *buf)
.odn_edit_dpm_table = smu7_odn_edit_dpm_table,
.set_power_limit = smu7_set_power_limit,
.get_power_profile_mode = smu7_get_power_profile_mode,
+   .set_power_profile_mode = smu7_set_power_profile_mode,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
-- 
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[PATCH 05/10] drm/amd/pp: Implement get_power_profile_mode on smu7

[Rex Zhu]

It show what parameters can be setted on smu7(vi/ci asics)
to get better performance.

Also show some profiling modes, user can select directly
by serial number based on workloads.

cat pp_power_profile_mode
NUMMODE_NAME SCLK_UP_HYST   SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL 
MCLK_UP_HYST   MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL
  0   3D_FULL_SCREEN:0  100   30
0  100   10
  1 POWER_SAVING:   100   30
---
  2VIDEO:---   
10   16   31
  3   VR:0   11   50
0  100   10
  4  COMPUTE:05   30
---
  5   CUSTOM:000
000
  *  CURRENT:0  100   30
0  100   10

Change-Id: If0e9796d6cbe531ce1eb5ff181fe2f5f956437b6
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 87 
 1 file changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 9379713..8cf95d9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -81,6 +81,21 @@
 #define PCIE_BUS_CLK1
 #define TCLK(PCIE_BUS_CLK / 10)
 
+static const struct profile_mode_setting smu7_profiling[5] =
+   {{1, 0, 100, 30, 1, 0, 100, 10},
+{1, 10, 0, 30, 0, 0, 0, 0},
+{0, 0, 0, 0, 1, 10, 16, 31},
+{1, 0, 11, 50, 1, 0, 100, 10},
+{1, 0, 5, 30, 0, 0, 0, 0},
+   };
+
+static const struct profile_mode_setting polaris11_profiling[5] =
+   {{1, 0, 100, 30, 1, 0, 100, 10},
+{1, 10, 0, 30, 0, 0, 0, 0},
+{0, 0, 0, 0, 1, 10, 16, 62},
+{1, 0, 11, 50, 1, 0, 100, 10},
+{1, 0, 5, 30, 0, 0, 0, 0},
+   };
 
 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 enum DPM_EVENT_SRC {
@@ -4932,6 +4947,77 @@ static int smu7_odn_edit_dpm_table(struct pp_hwmgr 
*hwmgr,
return 0;
 }
 
+static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
+{
+   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+   uint32_t i, size = 0;
+   uint32_t len;
+
+   static const char *profile_name[6] = {"3D_FULL_SCREEN",
+   "POWER_SAVING",
+   "VIDEO",
+   "VR",
+   "COMPUTE",
+   "CUSTOM"};
+
+   static const char *title[8] = {"NUM",
+   "MODE_NAME",
+   "SCLK_UP_HYST",
+   "SCLK_DOWN_HYST",
+   "SCLK_ACTIVE_LEVEL",
+   "MCLK_UP_HYST",
+   "MCLK_DOWN_HYST",
+   "MCLK_ACTIVE_LEVEL"};
+
+   if (!buf)
+   return -EINVAL;
+
+   size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
+   title[0], title[1], title[2], title[3],
+   title[4], title[5], title[6], title[7]);
+
+   len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
+
+   for (i = 0; i < len; i++) {
+   if (smu7_profiling[i].bupdate_sclk)
+   size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
+   i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
+   smu7_profiling[i].sclk_down_hyst,
+   smu7_profiling[i].sclk_activity);
+   else
+   size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ",
+   i, profile_name[i], "-", "-", "-");
+
+   if (smu7_profiling[i].bupdate_mclk)
+   size += sprintf(buf + size, "%16d %16d %16d\n",
+   smu7_profiling[i].mclk_up_hyst,
+   smu7_profiling[i].mclk_down_hyst,
+   smu7_profiling[i].mclk_activity);
+   else
+   size += sprintf(buf + size, "%16s %16s %16s\n",
+   "-", 

[PATCH 07/10] drm/amd/pp: Add new hw interface for auto wattman feature.

[Rex Zhu]

Change-Id: Ib34c2815ab95890ba91f9a61bc0594b0f5e0c3fd
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 31988d7..d809d96 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -351,6 +351,8 @@ struct pp_hwmgr_func {
long *input, uint32_t size);
int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
int (*set_mmhub_powergating_by_smu)(struct pp_hwmgr *hwmgr);
+   int (*update_auto_wattman)(struct pp_hwmgr *hwmgr);
+   void (*start_auto_wattman)(struct pp_hwmgr *hwmgr, bool en);
 };
 
 struct pp_table_func {
-- 
1.9.1

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[PATCH 04/10] drm/amd/pp: Implement update_dpm_settings on Polaris

[Rex Zhu]

Change-Id: I4533826ef6e18df125ae4445016873be3b5fe0ce
Signed-off-by: Rex Zhu 
---
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 104 +
 1 file changed, 104 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index bfb2c85..559572d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -2575,6 +2575,109 @@ static int 
polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
array_size, SMC_RAM_END);
 }
 
+uint32_t polaris10_set_field_to_u32(u32 offset, u32 original_data, u32 field, 
u32 size)
+{
+   u32 mask = 0;
+   u32 shift = 0;
+
+   shift = (offset % 4) << 3;
+   if (size == sizeof(uint8_t))
+   mask = 0xFF << shift;
+   else if (size == sizeof(uint16_t))
+   mask = 0x << shift;
+
+   original_data &= ~mask;
+   original_data |= (field << shift);
+   return original_data;
+}
+
+static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
+   void *profile_setting)
+{
+   struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
+   (hwmgr->smu_backend);
+   struct profile_mode_setting *setting;
+   struct SMU74_Discrete_GraphicsLevel *levels =
+   smu_data->smc_state_table.GraphicsLevel;
+   uint32_t array = smu_data->smu7_data.dpm_table_start +
+   offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
+
+   uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
+   offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
+   struct SMU74_Discrete_MemoryLevel *mclk_levels =
+   smu_data->smc_state_table.MemoryLevel;
+   uint32_t i;
+   uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, 
tmp;
+
+   if (profile_setting == NULL)
+   return -EINVAL;
+
+   setting = (struct profile_mode_setting *)profile_setting;
+
+   if (setting->bupdate_sclk) {
+   for (i = 0; i < 
smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
+   if (levels[i].ActivityLevel !=
+   cpu_to_be16(setting->sclk_activity)) {
+   levels[i].ActivityLevel = 
cpu_to_be16(setting->sclk_activity);
+
+   clk_activity_offset = array + 
(sizeof(SMU74_Discrete_GraphicsLevel) * i)
+   + 
offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
+   offset = clk_activity_offset & ~0x3;
+   tmp = 
PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
offset));
+   tmp = 
polaris10_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, 
sizeof(uint16_t));
+   cgs_write_ind_register(hwmgr->device, 
CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+
+   }
+   if (levels[i].UpHyst != setting->sclk_up_hyst ||
+   levels[i].DownHyst != setting->sclk_down_hyst) {
+   levels[i].UpHyst = setting->sclk_up_hyst;
+   levels[i].DownHyst = setting->sclk_down_hyst;
+   up_hyst_offset = array + 
(sizeof(SMU74_Discrete_GraphicsLevel) * i)
+   + 
offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
+   down_hyst_offset = array + 
(sizeof(SMU74_Discrete_GraphicsLevel) * i)
+   + 
offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
+   offset = up_hyst_offset & ~0x3;
+   tmp = 
PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
offset));
+   tmp = 
polaris10_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, 
sizeof(uint8_t));
+   tmp = 
polaris10_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, 
sizeof(uint8_t));
+   cgs_write_ind_register(hwmgr->device, 
CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+   }
+   }
+   }
+
+   if (setting->bupdate_mclk) {
+   for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; 
i++) {
+   if (mclk_levels[i].ActivityLevel !=
+   cpu_to_be16(setting->mclk_activity)) {
+   mclk_levels[i].ActivityLevel = 
cpu_to_be16(setting->mclk_activity);
+
+   clk_activity_offset = mclk_array + 
(sizeof(SMU74_Discrete_MemoryLevel) * i)
+  

[PATCH 03/10] drm/amd/pp: Add new smu callback function

[Rex Zhu]

it is used for adjust part of dpm settigs
to get better performance under different
workloads.

Change-Id: I1e1ed786e9c07c91fb7e810af5b1ec5dd5cc4791
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h| 1 +
 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 8 
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 77d7f49..31988d7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -239,6 +239,7 @@ struct pp_smumgr_func {
int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
struct amd_pp_profile *request);
bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
+   int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void 
*profile_setting);
 };
 
 struct pp_hwmgr_func {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index b1b27b2..e05a57e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -134,5 +134,6 @@ extern int smum_populate_requested_graphic_levels(struct 
pp_hwmgr *hwmgr,
 
 extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
 
+extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void 
*profile_setting);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index 8673884..1ce4959 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -253,3 +253,11 @@ bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
 
return false;
 }
+
+int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting)
+{
+   if (hwmgr->smumgr_funcs->update_dpm_settings)
+   return hwmgr->smumgr_funcs->update_dpm_settings(hwmgr, 
profile_setting);
+
+   return -EINVAL;
+}
-- 
1.9.1

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[PATCH 02/10] drm/amdgpu: Add a pp feature mask bit for autowattman

[Rex Zhu]

Change-Id: Ie329d6c806fc5ab71417ffabe413ddbdf9d367ea
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d3f5ee5..e2011d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -121,7 +121,7 @@
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-uint amdgpu_pp_feature_mask = 0x3fff;
+uint amdgpu_pp_feature_mask = 0xbfff;
 int amdgpu_ngg = 0;
 int amdgpu_prim_buf_per_se = 0;
 int amdgpu_pos_buf_per_se = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 2a59ee8..77d7f49 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -85,6 +85,7 @@ enum PP_FEATURE_MASK {
PP_SOCCLK_DPM_MASK = 0x1000,
PP_DCEFCLK_DPM_MASK = 0x2000,
PP_OVERDRIVE_MASK = 0x4000,
+   PP_AUTOWATTMAN_MASK = 0x8000,
 };
 
 enum PHM_BackEnd_Magic {
-- 
1.9.1

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[PATCH 01/10] drm/amd/amdgpu: Add query vram width in CGS query system info

[Rex Zhu]

Change-Id: I4bf7abab944253c8c744c1290b8a9fb5a62b6240
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 3 +++
 drivers/gpu/drm/amd/include/cgs_common.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 71b4aec..1f4e37b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -905,6 +905,9 @@ static int amdgpu_cgs_query_system_info(struct cgs_device 
*cgs_device,
case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN:
sys_info->value = adev->pdev->devfn;
break;
+   case CGS_SYSTEM_INFO_VRAM_WIDTH:
+   sys_info->value = adev->gmc.vram_width;
+   break;
default:
return -ENODEV;
}
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h 
b/drivers/gpu/drm/amd/include/cgs_common.h
index f5c7397..98cf4ce 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -101,6 +101,7 @@ enum cgs_system_info_id {
CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
CGS_SYSTEM_INFO_PCIE_BUS_DEVFN,
+   CGS_SYSTEM_INFO_VRAM_WIDTH,
CGS_SYSTEM_INFO_ID_MAXIMUM,
 };
 
-- 
1.9.1

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[PATCH 00/10] Enable auto wattman feature on Polaris

[Rex Zhu]

Enable auto wattman on polaris.
Manual set wattman feature related parameters on other smu7 asics.

In manual dpm mode, auto wattman feature was disabled.
user can change auto wattman related parameters through sysfs
pp_power_profile_mode.

Rex Zhu (10):
  drm/amd/amdgpu: Add query vram width in CGS query system info
  drm/amdgpu: Add a pp feature mask bit for autowattman
  drm/amd/pp: Add new smu callback function
  drm/amd/pp: Implement update_dpm_settings on Polaris
  drm/amd/pp: Implement get_power_profile_mode on smu7
  drm/amd/pp: Implement set_power_profile_mode on smu7
  drm/amd/pp: Add new hw interface for auto wattman feature.
  drm/amd/pp: Implement auto wattman feature on Smu7
  drm/amd/pp: Restore power profile mode in auto dpm level on smu7
  drm/amd/pp: Enable auto automan feature on Polaris

 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c|   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|   2 +-
 drivers/gpu/drm/amd/include/cgs_common.h   |   1 +
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c|  39 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 358 -
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h   |  26 ++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |   6 +
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h |   1 +
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c| 104 ++
 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c  |   8 +
 10 files changed, 545 insertions(+), 3 deletions(-)

-- 
1.9.1

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Re: [PATCH 1/4] drm/ttm: use bit flag to replace allow_reserved_eviction in ttm_operation_ctx

[Christian König]

Am 08.02.2018 um 10:05 schrieb Roger He:

for saving memory and more bit flag can be used in future

Signed-off-by: Roger He 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++--
  drivers/gpu/drm/ttm/ttm_bo.c   | 3 ++-
  include/drm/ttm/ttm_bo_api.h   | 7 +--
  4 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index eaa3cb0..dc34b50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -346,8 +346,8 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
struct ttm_operation_ctx ctx = {
.interruptible = true,
.no_wait_gpu = false,
-   .allow_reserved_eviction = false,
-   .resv = bo->tbo.resv
+   .resv = bo->tbo.resv,
+   .flags = 0
};
uint32_t domain;
int r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 512612e..0338ef6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -341,8 +341,8 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
struct ttm_operation_ctx ctx = {
.interruptible = !kernel,
.no_wait_gpu = false,
-   .allow_reserved_eviction = true,
-   .resv = resv
+   .resv = resv,
+   .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
};
struct amdgpu_bo *bo;
enum ttm_bo_type type;
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index d90b1cf1..a907311 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -730,7 +730,8 @@ static bool ttm_bo_evict_swapout_allowable(struct 
ttm_buffer_object *bo,
*locked = false;
if (bo->resv == ctx->resv) {
reservation_object_assert_held(bo->resv);
-   if (ctx->allow_reserved_eviction || !list_empty(>ddestroy))
+   if (ctx->flags & TTM_OPT_FLAG_ALLOW_RES_EVICT
+   || !list_empty(>ddestroy))
ret = true;
} else {
*locked = reservation_object_trylock(bo->resv);
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index 2cd025c..872ff6c 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -263,8 +263,8 @@ struct ttm_bo_kmap_obj {
   *
   * @interruptible: Sleep interruptible if sleeping.
   * @no_wait_gpu: Return immediately if the GPU is busy.
- * @allow_reserved_eviction: Allow eviction of reserved BOs.
   * @resv: Reservation object to allow reserved evictions with.
+ * @flags: Including the following flags
   *
   * Context for TTM operations like changing buffer placement or general memory
   * allocation.
@@ -272,11 +272,14 @@ struct ttm_bo_kmap_obj {
  struct ttm_operation_ctx {
bool interruptible;
bool no_wait_gpu;
-   bool allow_reserved_eviction;
struct reservation_object *resv;
uint64_t bytes_moved;
+   uint32_t flags;
  };
  
+/* Allow eviction of reserved BOs */

+#define TTM_OPT_FLAG_ALLOW_RES_EVICT   0x1
+
  /**
   * ttm_bo_reference - reference a struct ttm_buffer_object
   *


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Re: [PATCH 1/3] drm: add func to get max iomem address

[Michel Dänzer]

On 2018-02-08 10:15 AM, Chunming Zhou wrote:
> On 2018年02月08日 17:09, Michel Dänzer wrote:
>> On 2018-02-08 09:32 AM, Chunming Zhou wrote:
>>> it will be used to check if the driver needs swiotlb
>>>
>>> Change-Id: Idbe47af8f12032d4803bb3d47273e807f19169c3
>>> Signed-off-by: Chunming Zhou 
>>> Reviewed-by: Monk Liu 
>>> ---
>>>   include/drm/drm_cache.h | 13 +
>>>   1 file changed, 13 insertions(+)
>>>
>>> diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
>>> index beab0f0d0cfb..442c9ba63d03 100644
>>> --- a/include/drm/drm_cache.h
>>> +++ b/include/drm/drm_cache.h
>>> @@ -39,6 +39,19 @@ void drm_clflush_pages(struct page *pages[],
>>> unsigned long num_pages);
>>>   void drm_clflush_sg(struct sg_table *st);
>>>   void drm_clflush_virt_range(void *addr, unsigned long length);
>>>   +static inline u64 drm_get_max_iomem(void)
>>> +{
>>> +    struct resource *tmp;
>>> +    u64 max_iomem = 0;
>>> +
>>> +    for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
>>> +    max_iomem = max(max_iomem,  tmp->end);
>>> +    }
>>> +
>>> +    return max_iomem;
>>> +}
>> I don't think this needs to be an inline function, does it?
> If no inline, will report building warning that this function is defined
> but not used in some files including drm_cache.h

What I mean is that it can be a normal function in drivers/gpu/drm/*.c
with EXPORT_SYMBOL.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [PATCH 1/3] drm: add func to get max iomem address

[Chunming Zhou]

On 2018年02月08日 17:09, Michel Dänzer wrote:

On 2018-02-08 09:32 AM, Chunming Zhou wrote:

it will be used to check if the driver needs swiotlb

Change-Id: Idbe47af8f12032d4803bb3d47273e807f19169c3
Signed-off-by: Chunming Zhou 
Reviewed-by: Monk Liu 
---
  include/drm/drm_cache.h | 13 +
  1 file changed, 13 insertions(+)

diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index beab0f0d0cfb..442c9ba63d03 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -39,6 +39,19 @@ void drm_clflush_pages(struct page *pages[], unsigned long 
num_pages);
  void drm_clflush_sg(struct sg_table *st);
  void drm_clflush_virt_range(void *addr, unsigned long length);
  
+static inline u64 drm_get_max_iomem(void)

+{
+   struct resource *tmp;
+   u64 max_iomem = 0;
+
+   for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
+   max_iomem = max(max_iomem,  tmp->end);
+   }
+
+   return max_iomem;
+}

I don't think this needs to be an inline function, does it?
If no inline, will report building warning that this function is defined 
but not used in some files including drm_cache.h


Regards,
David Zhou





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Re: [PATCH libdrm 2/2] libdrm: clean up non list code path for vamgr

[Chunming Zhou]

On 2018年02月08日 17:01, Michel Dänzer wrote:

Hi David,


this change completely broke radeonsi due to memory management errors
(see valgrind output for glxgears below), so I had to revert it.

ok, I will look into what happens. Sorry for broken.

Regards,
David Zhou



==4831== Memcheck, a memory error detector
==4831== Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al.
==4831== Using Valgrind-3.13.0 and LibVEX; rerun with -h for copyright info
==4831== Command: glxgears
==4831==
==4831== Invalid read of size 8
==4831==at 0xAE4E79B: list_add (util_double_list.h:56)
==4831==by 0xAE4E79B: amdgpu_vamgr_free_va.part.0 (amdgpu_vamgr.c:184)
==4831==by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==by 0x535BCCE: FreeScreenConfigs.isra.3 (glxext.c:221)
==4831==  Address 0x151eccb8 is 8 bytes inside a block of size 32 free'd
==4831==at 0x4C2DDBB: free (vg_replace_malloc.c:530)
==4831==by 0xAE4E85B: amdgpu_vamgr_free_va.part.0 (amdgpu_vamgr.c:165)
==4831==by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==  Block was alloc'd at
==4831==at 0x4C2EBA5: calloc (vg_replace_malloc.c:711)
==4831==by 0xAE4E795: amdgpu_vamgr_free_va.part.0 (amdgpu_vamgr.c:180)
==4831==by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==
==4831== Invalid read of size 8
==4831==at 0xAE4E7B0: list_add (util_double_list.h:57)
==4831==by 0xAE4E7B0: amdgpu_vamgr_free_va.part.0 (amdgpu_vamgr.c:184)
==4831==by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==by 0x535BCCE: FreeScreenConfigs.isra.3 (glxext.c:221)
==4831==  Address 0x151eccb8 is 8 bytes inside a block of size 32 free'd
==4831==at 0x4C2DDBB: free (vg_replace_malloc.c:530)
==4831==by 0xAE4E85B: amdgpu_vamgr_free_va.part.0 (amdgpu_vamgr.c:165)
==4831==by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==by 0x9D85475: dri_destroy_screen 

[PATCH 3/4] drm/ttm: add input parameter force_alloc for ttm_bo_evict_mm

[Roger He]

if true, allocate TTM pages regardless of zone global memory
account limit. For suspend, We should avoid TTM memory allocate
failure then result in suspend failure.

Signed-off-by: Roger He 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h  |  2 +-
 drivers/gpu/drm/nouveau/nouveau_drm.c   |  2 +-
 drivers/gpu/drm/qxl/qxl_object.c|  4 ++--
 drivers/gpu/drm/radeon/radeon_device.c  |  6 +++---
 drivers/gpu/drm/radeon/radeon_object.c  |  5 +++--
 drivers/gpu/drm/radeon/radeon_object.h  |  3 ++-
 drivers/gpu/drm/ttm/ttm_bo.c| 16 ++--
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c |  6 +++---
 include/drm/ttm/ttm_bo_api.h|  5 -
 12 files changed, 34 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index ee76b46..59ee12c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -763,7 +763,7 @@ static int amdgpu_debugfs_evict_vram(struct seq_file *m, 
void *data)
struct drm_device *dev = node->minor->dev;
struct amdgpu_device *adev = dev->dev_private;
 
-   seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev));
+   seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev, true));
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e3fa3d7..3c5f9ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2168,7 +2168,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
suspend, bool fbcon)
}
}
/* evict vram memory */
-   amdgpu_bo_evict_vram(adev);
+   amdgpu_bo_evict_vram(adev, true);
 
amdgpu_fence_driver_suspend(adev);
 
@@ -2178,7 +2178,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
suspend, bool fbcon)
 * This second call to evict vram is to evict the gart page table
 * using the CPU.
 */
-   amdgpu_bo_evict_vram(adev);
+   amdgpu_bo_evict_vram(adev, true);
 
pci_save_state(dev->pdev);
if (suspend) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0338ef6..db813f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -803,14 +803,14 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
return r;
 }
 
-int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
+int amdgpu_bo_evict_vram(struct amdgpu_device *adev, bool force_alloc)
 {
/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
if (0 && (adev->flags & AMD_IS_APU)) {
/* Useless to evict on IGP chips */
return 0;
}
-   return ttm_bo_evict_mm(>mman.bdev, TTM_PL_VRAM);
+   return ttm_bo_evict_mm(>mman.bdev, TTM_PL_VRAM, force_alloc);
 }
 
 static const char *amdgpu_vram_names[] = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index c2b02f5..6724cdc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -227,7 +227,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 
domain,
 u64 min_offset, u64 max_offset,
 u64 *gpu_addr);
 int amdgpu_bo_unpin(struct amdgpu_bo *bo);
-int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
+int amdgpu_bo_evict_vram(struct amdgpu_device *adev, bool force_alloc);
 int amdgpu_bo_init(struct amdgpu_device *adev);
 void amdgpu_bo_fini(struct amdgpu_device *adev);
 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c 
b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 8d4a5be..c9627ef 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -702,7 +702,7 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime)
}
 
NV_DEBUG(drm, "evicting buffers...\n");
-   ttm_bo_evict_mm(>ttm.bdev, TTM_PL_VRAM);
+   ttm_bo_evict_mm(>ttm.bdev, TTM_PL_VRAM, true);
 
NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
if (drm->cechan) {
diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c
index f6b80fe..d8d26c8 100644
--- a/drivers/gpu/drm/qxl/qxl_object.c
+++ b/drivers/gpu/drm/qxl/qxl_object.c
@@ -350,10 +350,10 @@ int qxl_bo_check_id(struct qxl_device *qdev, struct 
qxl_bo *bo)
 
 int qxl_surf_evict(struct qxl_device *qdev)
 {
-   return ttm_bo_evict_mm(>mman.bdev, TTM_PL_PRIV);
+   return ttm_bo_evict_mm(>mman.bdev, TTM_PL_PRIV, true);
 }
 
 int qxl_vram_evict(struct 

[PATCH 4/4] drm/ttm: check if the mem free space is under lower limit

[Roger He]

mem free space and lower limit both include two parts:
system memory and swap space.

For the OOM triggered by TTM, that is the case as below:
swap space is full of swapped pages and then system
memory will be filled up with ttm pages. and then any
memory allocation request will run into OOM.

to cover two cases:
a. if no swap disk at all or free swap space is under
   swap mem limit but available system mem is bigger than
   sys mem limit, allow TTM allocation;

b. if the available system mem is less than sys mem limit
   but free swap space is bigger than swap mem limit, allow
   TTM allocation.

v2: merge two memory limit(swap and system) into one
v3: keep original behavior except with ttm->page_flags
TTM_PAGE_FLAG_NO_RETRY

Signed-off-by: Roger He 
---
 drivers/gpu/drm/ttm/ttm_memory.c | 34 
 drivers/gpu/drm/ttm/ttm_page_alloc.c | 22 ++---
 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 31 ++---
 include/drm/ttm/ttm_memory.h |  5 +
 4 files changed, 73 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c
index aa0c381..16ab324 100644
--- a/drivers/gpu/drm/ttm/ttm_memory.c
+++ b/drivers/gpu/drm/ttm/ttm_memory.c
@@ -36,6 +36,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define TTM_MEMORY_ALLOC_RETRIES 4
 
@@ -375,6 +376,11 @@ int ttm_mem_global_init(struct ttm_mem_global *glob)
 
si_meminfo();
 
+   /* lower limit of swap space and 256MB is enough */
+   glob->lower_mem_limit = 256 << 8;
+   /* lower limit of ram and keep consistent with each zone->emer_mem */
+   glob->lower_mem_limit += si.totalram >> 2;
+
ret = ttm_mem_init_kernel_zone(glob, );
if (unlikely(ret != 0))
goto out_no_zone;
@@ -469,6 +475,34 @@ void ttm_mem_global_free(struct ttm_mem_global *glob,
 }
 EXPORT_SYMBOL(ttm_mem_global_free);
 
+/*
+ * check if the available mem is under total memory limit
+ *
+ * a. if no swap disk at all or free swap space is under swap_mem_limit
+ * but available system mem is bigger than sys_mem_limit, allow TTM
+ * allocation;
+ *
+ * b. if the available system mem is less than sys_mem_limit but free
+ * swap disk is bigger than swap_mem_limit, allow TTM allocation.
+ */
+bool
+ttm_check_under_lowerlimit(struct ttm_mem_global *glob, bool force_alloc)
+{
+   bool ret = false;
+   uint64_t available;
+
+   /* always allow allocation, e.g. when serving page fault or suspend */
+   if (force_alloc)
+   return false;
+
+   available = get_nr_swap_pages() + si_mem_available();
+   if (available < glob->lower_mem_limit)
+   ret = true;
+
+   return ret;
+}
+EXPORT_SYMBOL(ttm_check_under_lowerlimit);
+
 static int ttm_mem_global_reserve(struct ttm_mem_global *glob,
  struct ttm_mem_zone *single_zone,
  uint64_t amount, bool reserve)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c 
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 5edcd89..1457a1c 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -1094,7 +1094,8 @@ ttm_pool_unpopulate_helper(struct ttm_tt *ttm, unsigned 
mem_count_update)
 int ttm_pool_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
 {
struct ttm_mem_global *mem_glob = ttm->glob->mem_glob;
-   unsigned i;
+   unsigned i, unpopulate_count = 0;
+   bool force_alloc = true;
int ret;
 
if (ttm->state != tt_unpopulated)
@@ -1102,17 +1103,20 @@ int ttm_pool_populate(struct ttm_tt *ttm, struct 
ttm_operation_ctx *ctx)
 
ret = ttm_get_pages(ttm->pages, ttm->num_pages, ttm->page_flags,
ttm->caching_state);
-   if (unlikely(ret != 0)) {
-   ttm_pool_unpopulate_helper(ttm, 0);
-   return ret;
-   }
+   if (unlikely(ret != 0))
+   goto error_populate;
+
+   if (ttm->page_flags & TTM_PAGE_FLAG_NO_RETRY)
+   force_alloc = ctx->flags & TTM_OPT_FLAG_FORCE_ALLOC;
+   if (ttm_check_under_lowerlimit(mem_glob, force_alloc))
+   goto error_populate;
 
for (i = 0; i < ttm->num_pages; ++i) {
ret = ttm_mem_global_alloc_page(mem_glob, ttm->pages[i],
PAGE_SIZE, ctx);
if (unlikely(ret != 0)) {
-   ttm_pool_unpopulate_helper(ttm, i);
-   return -ENOMEM;
+   unpopulate_count = i;
+   goto error_populate;
}
}
 
@@ -1126,6 +1130,10 @@ int ttm_pool_populate(struct ttm_tt *ttm, struct 
ttm_operation_ctx *ctx)
 
ttm->state = tt_unbound;
return 0;
+
+error_populate:
+   ttm_pool_unpopulate_helper(ttm, unpopulate_count);
+   return -ENOMEM;
 }
 

[PATCH 1/4] drm/ttm: use bit flag to replace allow_reserved_eviction in ttm_operation_ctx

[Roger He]

for saving memory and more bit flag can be used in future

Signed-off-by: Roger He 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++--
 drivers/gpu/drm/ttm/ttm_bo.c   | 3 ++-
 include/drm/ttm/ttm_bo_api.h   | 7 +--
 4 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index eaa3cb0..dc34b50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -346,8 +346,8 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
struct ttm_operation_ctx ctx = {
.interruptible = true,
.no_wait_gpu = false,
-   .allow_reserved_eviction = false,
-   .resv = bo->tbo.resv
+   .resv = bo->tbo.resv,
+   .flags = 0
};
uint32_t domain;
int r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 512612e..0338ef6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -341,8 +341,8 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
struct ttm_operation_ctx ctx = {
.interruptible = !kernel,
.no_wait_gpu = false,
-   .allow_reserved_eviction = true,
-   .resv = resv
+   .resv = resv,
+   .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
};
struct amdgpu_bo *bo;
enum ttm_bo_type type;
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index d90b1cf1..a907311 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -730,7 +730,8 @@ static bool ttm_bo_evict_swapout_allowable(struct 
ttm_buffer_object *bo,
*locked = false;
if (bo->resv == ctx->resv) {
reservation_object_assert_held(bo->resv);
-   if (ctx->allow_reserved_eviction || !list_empty(>ddestroy))
+   if (ctx->flags & TTM_OPT_FLAG_ALLOW_RES_EVICT
+   || !list_empty(>ddestroy))
ret = true;
} else {
*locked = reservation_object_trylock(bo->resv);
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index 2cd025c..872ff6c 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -263,8 +263,8 @@ struct ttm_bo_kmap_obj {
  *
  * @interruptible: Sleep interruptible if sleeping.
  * @no_wait_gpu: Return immediately if the GPU is busy.
- * @allow_reserved_eviction: Allow eviction of reserved BOs.
  * @resv: Reservation object to allow reserved evictions with.
+ * @flags: Including the following flags
  *
  * Context for TTM operations like changing buffer placement or general memory
  * allocation.
@@ -272,11 +272,14 @@ struct ttm_bo_kmap_obj {
 struct ttm_operation_ctx {
bool interruptible;
bool no_wait_gpu;
-   bool allow_reserved_eviction;
struct reservation_object *resv;
uint64_t bytes_moved;
+   uint32_t flags;
 };
 
+/* Allow eviction of reserved BOs */
+#define TTM_OPT_FLAG_ALLOW_RES_EVICT   0x1
+
 /**
  * ttm_bo_reference - reference a struct ttm_buffer_object
  *
-- 
2.7.4

___
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Re: [PATCH libdrm 2/2] libdrm: clean up non list code path for vamgr

[Michel Dänzer]

Hi David,


this change completely broke radeonsi due to memory management errors
(see valgrind output for glxgears below), so I had to revert it.


==4831== Memcheck, a memory error detector
==4831== Copyright (C) 2002-2017, and GNU GPL'd, by Julian Seward et al.
==4831== Using Valgrind-3.13.0 and LibVEX; rerun with -h for copyright info
==4831== Command: glxgears
==4831== 
==4831== Invalid read of size 8
==4831==at 0xAE4E79B: list_add (util_double_list.h:56)
==4831==by 0xAE4E79B: amdgpu_vamgr_free_va.part.0 (amdgpu_vamgr.c:184)
==4831==by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==by 0x535BCCE: FreeScreenConfigs.isra.3 (glxext.c:221)
==4831==  Address 0x151eccb8 is 8 bytes inside a block of size 32 free'd
==4831==at 0x4C2DDBB: free (vg_replace_malloc.c:530)
==4831==by 0xAE4E85B: amdgpu_vamgr_free_va.part.0 (amdgpu_vamgr.c:165)
==4831==by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==  Block was alloc'd at
==4831==at 0x4C2EBA5: calloc (vg_replace_malloc.c:711)
==4831==by 0xAE4E795: amdgpu_vamgr_free_va.part.0 (amdgpu_vamgr.c:180)
==4831==by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831== 
==4831== Invalid read of size 8
==4831==at 0xAE4E7B0: list_add (util_double_list.h:57)
==4831==by 0xAE4E7B0: amdgpu_vamgr_free_va.part.0 (amdgpu_vamgr.c:184)
==4831==by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==by 0x5386222: dri3_destroy_screen (dri3_glx.c:584)
==4831==by 0x535BCCE: FreeScreenConfigs.isra.3 (glxext.c:221)
==4831==  Address 0x151eccb8 is 8 bytes inside a block of size 32 free'd
==4831==at 0x4C2DDBB: free (vg_replace_malloc.c:530)
==4831==by 0xAE4E85B: amdgpu_vamgr_free_va.part.0 (amdgpu_vamgr.c:165)
==4831==by 0xAE4EB2C: amdgpu_vamgr_free_va (amdgpu_vamgr.c:141)
==4831==by 0xAE4EB2C: amdgpu_va_range_free (amdgpu_vamgr.c:246)
==4831==by 0xA0FA53E: amdgpu_bo_destroy (amdgpu_bo.c:178)
==4831==by 0x9DD5067: pb_cache_release_all_buffers (pb_cache.c:241)
==4831==by 0x9DD5260: pb_cache_deinit (pb_cache.c:313)
==4831==by 0xA0FFD82: amdgpu_winsys_destroy (amdgpu_winsys.c:99)
==4831==by 0xA051D76: si_destroy_screen (si_pipe.c:515)
==4831==by 0x9D85448: dri_destroy_screen_helper (dri_screen.c:454)
==4831==by 0x9D85475: dri_destroy_screen (dri_screen.c:464)
==4831==by 0x9D82076: driDestroyScreen (dri_util.c:231)
==4831==by 0x5386222: dri3_destroy_screen 

Re: [PATCH 1/3] drm: add func to get max iomem address

[Christian König]

Am 08.02.2018 um 09:32 schrieb Chunming Zhou:

it will be used to check if the driver needs swiotlb

Change-Id: Idbe47af8f12032d4803bb3d47273e807f19169c3
Signed-off-by: Chunming Zhou 
Reviewed-by: Monk Liu 


Reviewed-by: Christian König  for the whole 
series.



---
  include/drm/drm_cache.h | 13 +
  1 file changed, 13 insertions(+)

diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index beab0f0d0cfb..442c9ba63d03 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -39,6 +39,19 @@ void drm_clflush_pages(struct page *pages[], unsigned long 
num_pages);
  void drm_clflush_sg(struct sg_table *st);
  void drm_clflush_virt_range(void *addr, unsigned long length);
  
+static inline u64 drm_get_max_iomem(void)

+{
+   struct resource *tmp;
+   u64 max_iomem = 0;
+
+   for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
+   max_iomem = max(max_iomem,  tmp->end);
+   }
+
+   return max_iomem;
+}
+
+
  static inline bool drm_arch_can_wc_memory(void)
  {
  #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)


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[PATCH 1/3] drm: add func to get max iomem address

[Chunming Zhou]

it will be used to check if the driver needs swiotlb

Change-Id: Idbe47af8f12032d4803bb3d47273e807f19169c3
Signed-off-by: Chunming Zhou 
Reviewed-by: Monk Liu 
---
 include/drm/drm_cache.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index beab0f0d0cfb..442c9ba63d03 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -39,6 +39,19 @@ void drm_clflush_pages(struct page *pages[], unsigned long 
num_pages);
 void drm_clflush_sg(struct sg_table *st);
 void drm_clflush_virt_range(void *addr, unsigned long length);
 
+static inline u64 drm_get_max_iomem(void)
+{
+   struct resource *tmp;
+   u64 max_iomem = 0;
+
+   for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
+   max_iomem = max(max_iomem,  tmp->end);
+   }
+
+   return max_iomem;
+}
+
+
 static inline bool drm_arch_can_wc_memory(void)
 {
 #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
-- 
2.14.1

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Re: [PATCH 11/25] drm/amdkfd: Centralize IOMMUv2 code and make it conditional

[Christian König]

Am 07.02.2018 um 21:51 schrieb Felix Kuehling:

On 2018-02-07 06:20 AM, Christian König wrote:

Am 07.02.2018 um 02:32 schrieb Felix Kuehling:

dGPUs work without IOMMUv2. Make IOMMUv2 initialization dependent on
ASIC information. Also allow building KFD without IOMMUv2 support.
This is still useful for dGPUs and prepares for enabling KFD on
architectures that don't support AMD IOMMUv2.

v2:
* Centralize IOMMUv2 code to avoid #ifdefs in too many places

Signed-off-by: Felix Kuehling 
---
   drivers/gpu/drm/amd/amdkfd/Kconfig    |   2 +-
   drivers/gpu/drm/amd/amdkfd/Makefile   |   4 +
   drivers/gpu/drm/amd/amdkfd/kfd_crat.c |  14 +-
   drivers/gpu/drm/amd/amdkfd/kfd_device.c   | 127 +++
   drivers/gpu/drm/amd/amdkfd/kfd_events.c   |   3 +
   drivers/gpu/drm/amd/amdkfd/kfd_iommu.c    | 356
++
   drivers/gpu/drm/amd/amdkfd/kfd_iommu.h    |  78 +++
   drivers/gpu/drm/amd/amdkfd/kfd_priv.h |  14 +-
   drivers/gpu/drm/amd/amdkfd/kfd_process.c  | 138 +---
   drivers/gpu/drm/amd/amdkfd/kfd_topology.c |  16 +-
   drivers/gpu/drm/amd/amdkfd/kfd_topology.h |   6 +-
   11 files changed, 493 insertions(+), 265 deletions(-)
   create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
   create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_iommu.h

diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig
b/drivers/gpu/drm/amd/amdkfd/Kconfig
index bc5a294..5bbeb95 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -4,6 +4,6 @@
     config HSA_AMD
   tristate "HSA kernel driver for AMD GPU devices"
-    depends on DRM_AMDGPU && AMD_IOMMU_V2 && X86_64
+    depends on DRM_AMDGPU && X86_64

You still need a weak dependency on AMD_IOMMU_V2 here, in other words
add "imply AMD_IOMMU_V2".

This prevents illegal combinations like linking amdkfd into the kernel
while amd_iommu_v2 is a module.

But it should still allow to completely disable amd_iommu_v2 and
compile amdkfd without support for it.

Thanks, that's good to know. An updated patch is attached (to avoid
resending the whole series).


Patch is Acked-by: Christian König .

Regards,
Christian.



Regards,
   Felix


Christian.


   help
     Enable this if you want to use HSA features on AMD GPU devices.
diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile
b/drivers/gpu/drm/amd/amdkfd/Makefile
index a317e76..0d02422 100644
--- a/drivers/gpu/drm/amd/amdkfd/Makefile
+++ b/drivers/gpu/drm/amd/amdkfd/Makefile
@@ -37,6 +37,10 @@ amdkfd-y    := kfd_module.o kfd_device.o
kfd_chardev.o kfd_topology.o \
   kfd_interrupt.o kfd_events.o cik_event_interrupt.o \
   kfd_dbgdev.o kfd_dbgmgr.o kfd_crat.o
   +ifneq ($(CONFIG_AMD_IOMMU_V2),)
+amdkfd-y += kfd_iommu.o
+endif
+
   amdkfd-$(CONFIG_DEBUG_FS) += kfd_debugfs.o
     obj-$(CONFIG_HSA_AMD)    += amdkfd.o
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 2bc2816..7493f47 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -22,10 +22,10 @@
     #include 
   #include 
-#include 
   #include "kfd_crat.h"
   #include "kfd_priv.h"
   #include "kfd_topology.h"
+#include "kfd_iommu.h"
     /* GPU Processor ID base for dGPUs for which VCRAT needs to be
created.
    * GPU processor ID are expressed with Bit[31]=1.
@@ -1037,15 +1037,11 @@ static int kfd_create_vcrat_image_gpu(void
*pcrat_image,
   struct crat_subtype_generic *sub_type_hdr;
   struct crat_subtype_computeunit *cu;
   struct kfd_cu_info cu_info;
-    struct amd_iommu_device_info iommu_info;
   int avail_size = *size;
   uint32_t total_num_of_cu;
   int num_of_cache_entries = 0;
   int cache_mem_filled = 0;
   int ret = 0;
-    const u32 required_iommu_flags = AMD_IOMMU_DEVICE_FLAG_ATS_SUP |
- AMD_IOMMU_DEVICE_FLAG_PRI_SUP |
- AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
   struct kfd_local_mem_info local_mem_info;
     if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_GPU)
@@ -1106,12 +1102,8 @@ static int kfd_create_vcrat_image_gpu(void
*pcrat_image,
   /* Check if this node supports IOMMU. During parsing this flag
will
    * translate to HSA_CAP_ATS_PRESENT
    */
-    iommu_info.flags = 0;
-    if (amd_iommu_device_info(kdev->pdev, _info) == 0) {
-    if ((iommu_info.flags & required_iommu_flags) ==
-    required_iommu_flags)
-    cu->hsa_capability |= CRAT_CU_FLAGS_IOMMU_PRESENT;
-    }
+    if (!kfd_iommu_check_device(kdev))
+    cu->hsa_capability |= CRAT_CU_FLAGS_IOMMU_PRESENT;
     crat_table->length += sub_type_hdr->length;
   crat_table->total_entries++;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 83d6f41..4ac2d61 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -20,7 +20,9 @@
    * OTHER 

Re: [PATCH 3/9] drm/amdgpu: add amdgpu module parameter for zfb

[Christian König]

Am 08.02.2018 um 05:51 schrieb Zhang, Hawking:

Apart from the allocation failure, reserving 1024M cma is also not realistic


Sure it is, I just tried it and it works perfectly fine. The option even 
accepts a G postfix for gigabytes, e.g. I can specify cma=8G on my 32GB 
Ryzen box and get exactly 8GB CMA space reserved.


Regarding the allocation failure using the DMA path there was a thread 
quite some time ago. IIRC the argument was that TTM only allocates a 
single page at a time and so should never run into any CMA allocator and 
according to my tests at least with IOMMU enabled that seems to be fixed 
now.


The key point is that CMA was specially crafted to avoid all those mem= 
workarounds and I think this is now a must have. See here 
https://de.slideshare.net/kerneltlv/continguous-memory-allocator-in-the-linux-kernel 
as well.


Regards,
Christian.



Regards,
Hawking

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of 
Chunming Zhou
Sent: Thursday, February 08, 2018 12:35
To: Koenig, Christian ; Xu, Feifei 
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/9] drm/amdgpu: add amdgpu module parameter for zfb



On 2018年02月08日 02:48, Christian König wrote:

Hi Feifei,

ok the correct approach of doing this:
1. Compile the kernel with CONFIG_DMA_CMA.
2. Specify cma=1025M on the kernel command line.
3. Call dma_alloc_coherent() to allocate up to 1GB of memory for ZFB.

Have you tried CMA? In early time, I tried it. If CMA is enabled, then ttm dma 
pool allocation will use cma, and when cma is used up, then ttm dma pool 
allocation will fail.
Not sure if the issue is fixed now.

Regards,
David Zhou

Couldn't figure out of hand what alignment is necessary here, but that
should just be a typing exercise.

Regards,
Christian.

Am 07.02.2018 um 14:18 schrieb Christian König:

Hi Feifei,

mhm, so you're approach is to limit the memory the Linux kernel grab
using the mem= parameter and then give that memory to amdgpu, correct?

If that's the case then this is most likely a NAK. Cause this sounds
like a perfect example for the CMA.

Never worked with that subsystem before, but in theory you should be
able to give the cma=1G parameter to the kernel and by doing so you
reserve 1GB of contiguous memory for use by device drivers.

Going to dig a bit deeper into that and trying to find to
documentation about it, Christian.

Am 07.02.2018 um 13:34 schrieb Feifei Xu:

Users can pass in an array to decide enable/disable Zero Frame Buffer.
zfb[0] = zfb_size(MB), zfb[1] = zfb_phys_addr(MB).
If zbf_size > 0, zfb is enabled. Otherwise disabled.
Usage for example:
  modprobe amdgpu zfb={256,4096}

Change-Id: I340fcb36b5655f24551056e685b74559d7599680
Signed-off-by: Feifei Xu 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
   2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1b4c5ad..be79cb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -129,6 +129,7 @@ extern int amdgpu_job_hang_limit;
   extern int amdgpu_lbpw;
   extern int amdgpu_compute_multipipe;
   extern int amdgpu_gpu_recovery;
+extern ulong amdgpu_zfb[];
     #ifdef CONFIG_DRM_AMDGPU_SI
   extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3897179..af84815 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -132,6 +132,7 @@ int amdgpu_job_hang_limit = 0;
   int amdgpu_lbpw = -1;
   int amdgpu_compute_multipipe = -1;
   int amdgpu_gpu_recovery = -1; /* auto */
+ulong amdgpu_zfb[2] = {0,4096UL}; /* {0,0x1} */
     MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in
megabytes");
   module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); @@
-290,6 +291,10 @@ module_param_named(compute_multipipe,
amdgpu_compute_multipipe, int, 0444);
   MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1
= enable, 0 = disable, -1 = auto");
   module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
   +MODULE_PARM_DESC(zfb,
+ "Enable Zero Frame Buffer feature (zfb will be set like
,(zfb_size MB,zfb_phys_addr MB),default disabled)");
+module_param_array_named(zfb, amdgpu_zfb, ulong, NULL, 0444);
+
   #ifdef CONFIG_DRM_AMDGPU_SI
     int amdgpu_si_support = 1;

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