Re: 答复: [BUG] amdgpu: System freezes after resuming from suspend to ram the second time

[Alex Deucher]

On Tue, May 8, 2018 at 10:51 PM, Qu, Jim  wrote:
> Hi John,
>
> What driver version did you used? Did you try our last release driver?

Looks like a similar issue to this bug:
https://bugs.freedesktop.org/show_bug.cgi?id=105760
Seems to be an issue with Hybrid/PX configurations in some cases.

Alex

>
> Thanks
> JimQu
>
> 
> 发件人: amd-gfx  代表 John Smith 
> 
> 发送时间: 2018年5月8日 23:17:47
> 收件人: amd-gfx@lists.freedesktop.org
> 抄送: Deucher, Alexander; Zhou, David(ChunMing); Koenig, Christian
> 主题: [BUG] amdgpu: System freezes after resuming from suspend to ram the 
> second time
>
> The amdgpu driver freezes the kernel, when suspending for the second time. 
> When blacklisting amdgpu the suspend/resume works correctly.
> Please see the attached logs.
>
> Hardware: hp-zbook 15u 5g i7-8550
>
> $ uname -a
> Linux MYPCNAME 4.17.0-rc3-ARCH+ #1 SMP PREEMPT Sun May 6 09:50:29 CEST 2018 
> x86_64 GNU/Linux
>
> $ lspci -v
> 00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 620 (rev 
> 07) (prog-if 00 [VGA controller])
> Subsystem: Hewlett-Packard Company UHD Graphics 620
> Flags: bus master, fast devsel, latency 0, IRQ 137
> Memory at 1ff200 (64-bit, non-prefetchable) [size=16M]
> Memory at b000 (64-bit, prefetchable) [size=256M]
> I/O ports at 4000 [size=64]
> [virtual] Expansion ROM at 000c [disabled] [size=128K]
> Capabilities: 
> Kernel driver in use: i915
> Kernel modules: i915
>
> $ dmesg | grep amdgpu
> [2.032619] [drm] amdgpu kernel modesetting enabled.
> [2.047191] amdgpu :01:00.0: enabling device (0006 -> 0007)
> [2.078141] amdgpu :01:00.0: BAR 2: releasing [mem 
> 0xd000-0xd01f 64bit pref]
> [2.078142] amdgpu :01:00.0: BAR 0: releasing [mem 
> 0xc000-0xcfff 64bit pref]
> [2.078152] amdgpu :01:00.0: BAR 0: assigned [mem 
> 0xc000-0xcfff 64bit pref]
> [2.078161] amdgpu :01:00.0: BAR 2: assigned [mem 
> 0xd000-0xd01f 64bit pref]
> [2.078181] amdgpu :01:00.0: VRAM: 2048M 0x00F4 - 
> 0x00F47FFF (2048M used)
> [2.078182] amdgpu :01:00.0: GTT: 256M 0x - 
> 0x0FFF
> [2.078294] [drm] amdgpu: 2048M of VRAM memory ready
> [2.078295] [drm] amdgpu: 3072M of GTT memory ready.
> [2.142916] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
> it's not patched
> [2.142923] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
> it's not patched
> [2.142926] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
> it's not patched
> [2.142934] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
> it's not patched
> [2.142935] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
> it's not patched
> [2.142935] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
> it's not patched
> [2.142936] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
> it's not patched
> [2.157406] [drm:dc_create [amdgpu]] *ERROR* DC: Number of connectors is 
> zero!
> [2.325272] [drm] Initialized amdgpu 3.25.0 20150101 for :01:00.0 on 
> minor 0
> [9.666277] amdgpu :01:00.0: GPU pci config reset
> [   18.670067] amdgpu :01:00.0: GPU pci config reset
> [   69.598425] amdgpu :01:00.0: GPU pci config reset
> [   79.670532] amdgpu :01:00.0: GPU pci config reset
>
>
> $ dmesg
> [0.00] Linux version 4.17.0-rc3-ARCH+ (USER@MYPCNAME) (gcc version 
> 7.3.1 20180406 (GCC)) #1 SMP PREEMPT Sun May 6 09:50:29 CEST 2018
> [0.00] Command line: BOOT_IMAGE=/vmlinuz-linux-custom 
> root=UUID=1e8ed61d-f399-465f-b0f3-0216a6bf3adc rw 
> resume=UUID=3811a093-acc8-4399-aa1e-d2628543f87d
> [0.00] KERNEL supported cpus:
> [0.00]   Intel GenuineIntel
> [0.00]   AMD AuthenticAMD
> [0.00]   Centaur CentaurHauls
> [0.00] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point 
> registers'
> [0.00] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
> [0.00] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
> [0.00] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
> [0.00] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
> [0.00] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
> [0.00] x86/fpu: xstate_offset[3]:  832, xstate_sizes[3]:   64
> [0.00] x86/fpu: xstate_offset[4]:  896, xstate_sizes[4]:   64
> [0.00] x86/fpu: Enabled xstate features 0x1f, context size is 960 
> bytes, using 'compacted' format.
> [0.00] e820: BIOS-provided physical RAM map:
> [0.00] BIOS-e820: [mem 0x-0x00057fff] usable
> [0.00] BIOS-e820: [mem 0x00058000-0x00058fff] reserved
> [0.00] 

答复: [BUG] amdgpu: System freezes after resuming from suspend to ram the second time

[Qu, Jim]

Hi John,

What driver version did you used? Did you try our last release driver?

Thanks
JimQu


发件人: amd-gfx  代表 John Smith 

发送时间: 2018年5月8日 23:17:47
收件人: amd-gfx@lists.freedesktop.org
抄送: Deucher, Alexander; Zhou, David(ChunMing); Koenig, Christian
主题: [BUG] amdgpu: System freezes after resuming from suspend to ram the second 
time

The amdgpu driver freezes the kernel, when suspending for the second time. When 
blacklisting amdgpu the suspend/resume works correctly.
Please see the attached logs.

Hardware: hp-zbook 15u 5g i7-8550

$ uname -a
Linux MYPCNAME 4.17.0-rc3-ARCH+ #1 SMP PREEMPT Sun May 6 09:50:29 CEST 2018 
x86_64 GNU/Linux

$ lspci -v
00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 620 (rev 07) 
(prog-if 00 [VGA controller])
Subsystem: Hewlett-Packard Company UHD Graphics 620
Flags: bus master, fast devsel, latency 0, IRQ 137
Memory at 1ff200 (64-bit, non-prefetchable) [size=16M]
Memory at b000 (64-bit, prefetchable) [size=256M]
I/O ports at 4000 [size=64]
[virtual] Expansion ROM at 000c [disabled] [size=128K]
Capabilities: 
Kernel driver in use: i915
Kernel modules: i915

$ dmesg | grep amdgpu
[2.032619] [drm] amdgpu kernel modesetting enabled.
[2.047191] amdgpu :01:00.0: enabling device (0006 -> 0007)
[2.078141] amdgpu :01:00.0: BAR 2: releasing [mem 0xd000-0xd01f 
64bit pref]
[2.078142] amdgpu :01:00.0: BAR 0: releasing [mem 0xc000-0xcfff 
64bit pref]
[2.078152] amdgpu :01:00.0: BAR 0: assigned [mem 0xc000-0xcfff 
64bit pref]
[2.078161] amdgpu :01:00.0: BAR 2: assigned [mem 0xd000-0xd01f 
64bit pref]
[2.078181] amdgpu :01:00.0: VRAM: 2048M 0x00F4 - 
0x00F47FFF (2048M used)
[2.078182] amdgpu :01:00.0: GTT: 256M 0x - 
0x0FFF
[2.078294] [drm] amdgpu: 2048M of VRAM memory ready
[2.078295] [drm] amdgpu: 3072M of GTT memory ready.
[2.142916] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched
[2.142923] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched
[2.142926] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched
[2.142934] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched
[2.142935] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched
[2.142935] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched
[2.142936] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched
[2.157406] [drm:dc_create [amdgpu]] *ERROR* DC: Number of connectors is 
zero!
[2.325272] [drm] Initialized amdgpu 3.25.0 20150101 for :01:00.0 on 
minor 0
[9.666277] amdgpu :01:00.0: GPU pci config reset
[   18.670067] amdgpu :01:00.0: GPU pci config reset
[   69.598425] amdgpu :01:00.0: GPU pci config reset
[   79.670532] amdgpu :01:00.0: GPU pci config reset


$ dmesg
[0.00] Linux version 4.17.0-rc3-ARCH+ (USER@MYPCNAME) (gcc version 
7.3.1 20180406 (GCC)) #1 SMP PREEMPT Sun May 6 09:50:29 CEST 2018
[0.00] Command line: BOOT_IMAGE=/vmlinuz-linux-custom 
root=UUID=1e8ed61d-f399-465f-b0f3-0216a6bf3adc rw 
resume=UUID=3811a093-acc8-4399-aa1e-d2628543f87d
[0.00] KERNEL supported cpus:
[0.00]   Intel GenuineIntel
[0.00]   AMD AuthenticAMD
[0.00]   Centaur CentaurHauls
[0.00] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point 
registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
[0.00] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
[0.00] x86/fpu: xstate_offset[3]:  832, xstate_sizes[3]:   64
[0.00] x86/fpu: xstate_offset[4]:  896, xstate_sizes[4]:   64
[0.00] x86/fpu: Enabled xstate features 0x1f, context size is 960 
bytes, using 'compacted' format.
[0.00] e820: BIOS-provided physical RAM map:
[0.00] BIOS-e820: [mem 0x-0x00057fff] usable
[0.00] BIOS-e820: [mem 0x00058000-0x00058fff] reserved
[0.00] BIOS-e820: [mem 0x00059000-0x0009dfff] usable
[0.00] BIOS-e820: [mem 0x0009e000-0x0009efff] reserved
[0.00] BIOS-e820: [mem 0x0009f000-0x0009] usable
[0.00] BIOS-e820: [mem 0x000a-0x000f] reserved
[0.00] BIOS-e820: [mem 0x0010-0x879d9fff] usable
[0.00] BIOS-e820: [mem 

Re: amdgpu hangs on boot or shutdown on AMD Raven Ridge CPU (Engineer Sample)

[Daniel Drake]

WHi Alex,

On Thu, Apr 19, 2018 at 4:13 PM, Alex Deucher  wrote:
 https://bugs.freedesktop.org/show_bug.cgi?id=105684
>>>
>>> No progress made on that bug report so far.
>>> What can we do to help this advance?
>>
>> Ping, any news here? How can we help advance on this bug?
>
> Can you try one of these branches?
> https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next
> https://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-4.18-wip
> do they work any better?

It's been over 3 months since we reported this bug by email, over 6
weeks since we reported it on bugzilla, and still there has been no
meaningful diagnostics help from AMD. This follows a similar pattern
to what we have seen with other issues prior to this one.

What can we do so that this bug gets some attention from your team?

Secondarily https://bugs.freedesktop.org/show_bug.cgi?id=106228 is
another bug that needs attention. We have a growing number of consumer
platforms affected by this. When booted, the amdgpu screen brightness
value is incorrectly read back as 0, which systemd will then store on
shutdown. On next boot, it restores the very low brightness level.
This can reproduce out of the box on Fedora, Ubuntu, etc.

Thanks,
Daniel
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Re: [PATCH v3] drm/amdgpu: Don't default to DC support for Kaveri and older

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Harry 
Wentland 
Sent: Tuesday, May 8, 2018 11:33:42 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
Cc: Wentland, Harry
Subject: [PATCH v3] drm/amdgpu: Don't default to DC support for Kaveri and older

We've had a number of users report failures to detect and light up
display with DC with LVDS and VGA. These connector types are not
currently supported with DC. I'd like to add support but unfortunately
don't have a system with LVDS or VGA available.

In order not to cause regressions we should probably fallback to the
non-DC driver for ASICs that support VGA and LVDS.

These ASICs are:
 * Bonaire
 * Kabini
 * Kaveri
 * Mullins

ASIC support can always be force enabled with amdgpu.dc=1

v2: Keep Hawaii on DC
v3: Added Mullins to the list

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 887f7c9e84e0..f3ed4950d129 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2141,10 +2141,18 @@ bool amdgpu_device_asic_has_dc_support(enum 
amd_asic_type asic_type)
 switch (asic_type) {
 #if defined(CONFIG_DRM_AMD_DC)
 case CHIP_BONAIRE:
-   case CHIP_HAWAII:
 case CHIP_KAVERI:
 case CHIP_KABINI:
 case CHIP_MULLINS:
+   /*
+* We have systems in the wild with these ASICs that require
+* LVDS and VGA support which is not supported with DC.
+*
+* Fallback to the non-DC driver here by default so as not to
+* cause regressions.
+*/
+   return amdgpu_dc > 0;
+   case CHIP_HAWAII:
 case CHIP_CARRIZO:
 case CHIP_STONEY:
 case CHIP_POLARIS10:
--
2.17.0

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[PATCH 15/25] drm/amd/display: Fix up dm logging functionality

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  5 
 .../drm/amd/display/dc/basics/log_helpers.c   |  1 -
 .../gpu/drm/amd/display/dc/basics/logger.c|  1 +
 drivers/gpu/drm/amd/display/dc/dm_services.h  |  4 
 .../gpu/drm/amd/display/modules/stats/stats.c | 24 ---
 5 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index ca0b08bfa2cf..bd449351803f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -330,11 +330,6 @@ bool dm_helpers_dp_mst_send_payload_allocation(
return true;
 }
 
-bool dm_helpers_dc_conn_log(struct dc_context *ctx, struct log_entry *entry, 
enum dc_log_type event)
-{
-   return true;
-}
-
 void dm_dtn_log_begin(struct dc_context *ctx)
 {}
 
diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c 
b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
index 854678a0c54b..021451549ff7 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
@@ -94,7 +94,6 @@ void dc_conn_log(struct dc_context *ctx,
dm_logger_append(, "%2.2X ", hex_data[i]);
 
dm_logger_append(, "^\n");
-   dm_helpers_dc_conn_log(ctx, , event);
 
 fail:
dm_logger_close();
diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c 
b/drivers/gpu/drm/amd/display/dc/basics/logger.c
index 0001a3c5b862..738a818d58d1 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
@@ -402,3 +402,4 @@ void dm_logger_close(struct log_entry *entry)
entry->max_buf_bytes = 0;
}
 }
+
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h 
b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 8eafe1af8a5e..4ff9b2bba178 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -355,10 +355,6 @@ void dm_perf_trace_timestamp(const char *func_name, 
unsigned int line);
 /*
  * Debug and verification hooks
  */
-bool dm_helpers_dc_conn_log(
-   struct dc_context *ctx,
-   struct log_entry *entry,
-   enum dc_log_type event);
 
 void dm_dtn_log_begin(struct dc_context *ctx);
 void dm_dtn_log_append_v(struct dc_context *ctx, const char *msg, ...);
diff --git a/drivers/gpu/drm/amd/display/modules/stats/stats.c 
b/drivers/gpu/drm/amd/display/modules/stats/stats.c
index d16aac7b30b3..ae2d92b73cf1 100644
--- a/drivers/gpu/drm/amd/display/modules/stats/stats.c
+++ b/drivers/gpu/drm/amd/display/modules/stats/stats.c
@@ -168,6 +168,7 @@ void mod_stats_dump(struct mod_stats *mod_stats)
struct core_stats *core_stats = NULL;
struct stats_time_cache *time = NULL;
unsigned int index = 0;
+   struct log_entry log_entry;
 
if (mod_stats == NULL)
return;
@@ -177,17 +178,22 @@ void mod_stats_dump(struct mod_stats *mod_stats)
logger = dc->ctx->logger;
time = core_stats->time;
 
-   dm_logger_write(logger, LOG_DISPLAYSTATS, "==Display Caps==");
-   dm_logger_write(logger, LOG_DISPLAYSTATS, " ");
+   dm_logger_open(
+   dc->ctx->logger,
+   _entry,
+   LOG_DISPLAYSTATS);
 
-   dm_logger_write(logger, LOG_DISPLAYSTATS, "==Display Stats==");
-   dm_logger_write(logger, LOG_DISPLAYSTATS, " ");
+   dm_logger_append(_entry, "==Display Caps==\n");
+   dm_logger_append(_entry, "\n");
 
-   dm_logger_write(logger, LOG_DISPLAYSTATS,
+   dm_logger_append(_entry, "==Display Stats==\n");
+   dm_logger_append(_entry, "\n");
+
+   dm_logger_append(_entry,
"%10s %10s %10s %10s %10s"
" %11s %11s %17s %10s %14s"
" %10s %10s %10s %10s %10s"
-   " %10s %10s %10s %10s",
+   " %10s %10s %10s %10s\n",
"render", "avgRender",
"minWindow", "midPoint", "maxWindow",
"vsyncToFlip", "flipToVsync", "vsyncsBetweenFlip",
@@ -197,11 +203,11 @@ void mod_stats_dump(struct mod_stats *mod_stats)
"vSyncTime4", "vSyncTime5", "flags");
 
for (int i = 0; i < core_stats->index && i < core_stats->entries; i++) {
-   dm_logger_write(logger, LOG_DISPLAYSTATS,
+   dm_logger_append(_entry,
"%10u %10u %10u %10u %10u"
" %11u %11u %17u %10u %14u"
" %10u %10u %10u %10u %10u"
-   " %10u %10u %10u %10u",
+   " %10u 

[PATCH 20/25] drm/amd/display: Add fullscreen transitions to log

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/modules/inc/mod_stats.h   |   4 +
 .../gpu/drm/amd/display/modules/stats/stats.c | 137 ++
 2 files changed, 114 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h 
b/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
index 3230e2adb870..3812094b52e8 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
@@ -46,6 +46,10 @@ void mod_stats_dump(struct mod_stats *mod_stats);
 
 void mod_stats_reset_data(struct mod_stats *mod_stats);
 
+void mod_stats_update_event(struct mod_stats *mod_stats,
+   char *event_string,
+   unsigned int length);
+
 void mod_stats_update_flip(struct mod_stats *mod_stats,
unsigned long timestamp_in_ns);
 
diff --git a/drivers/gpu/drm/amd/display/modules/stats/stats.c 
b/drivers/gpu/drm/amd/display/modules/stats/stats.c
index 45acdbc3c08a..4b00bae725b9 100644
--- a/drivers/gpu/drm/amd/display/modules/stats/stats.c
+++ b/drivers/gpu/drm/amd/display/modules/stats/stats.c
@@ -36,9 +36,14 @@
 #define DAL_STATS_ENTRIES_REGKEY_DEFAULT   0x0035
 #define DAL_STATS_ENTRIES_REGKEY_MAX   0x0100
 
+#define DAL_STATS_EVENT_ENTRIES_DEFAULT0x0100
+
 #define MOD_STATS_NUM_VSYNCS   5
+#define MOD_STATS_EVENT_STRING_MAX 512
 
 struct stats_time_cache {
+   unsigned int entry_id;
+
unsigned long flip_timestamp_in_ns;
unsigned long vupdate_timestamp_in_ns;
 
@@ -63,15 +68,26 @@ struct stats_time_cache {
unsigned int flags;
 };
 
+struct stats_event_cache {
+   unsigned int entry_id;
+   char event_string[MOD_STATS_EVENT_STRING_MAX];
+};
+
 struct core_stats {
struct mod_stats public;
struct dc *dc;
 
+   bool enabled;
+   unsigned int entries;
+   unsigned int event_entries;
+   unsigned int entry_id;
+
struct stats_time_cache *time;
unsigned int index;
 
-   bool enabled;
-   unsigned int entries;
+   struct stats_event_cache *events;
+   unsigned int event_index;
+
 };
 
 #define MOD_STATS_TO_CORE(mod_stats)\
@@ -125,9 +141,18 @@ struct mod_stats *mod_stats_create(struct dc *dc)
else
core_stats->entries = reg_data;
}
+   core_stats->time = kzalloc(
+   sizeof(struct stats_time_cache) *
+   core_stats->entries,
+   GFP_KERNEL);
 
-   core_stats->time = kzalloc(sizeof(struct stats_time_cache) * 
core_stats->entries,
+
+   core_stats->event_entries = DAL_STATS_EVENT_ENTRIES_DEFAULT;
+   core_stats->events = kzalloc(
+   sizeof(struct stats_event_cache) *
+   core_stats->event_entries,
GFP_KERNEL);
+
} else {
core_stats->entries = 0;
}
@@ -139,6 +164,10 @@ struct mod_stats *mod_stats_create(struct dc *dc)
 * handle calculation cases that depend on previous flip data.
 */
core_stats->index = 1;
+   core_stats->event_index = 0;
+
+   // Keeps track of ordering within the different stats structures
+   core_stats->entry_id = 0;
 
return _stats->public;
 
@@ -167,6 +196,9 @@ void mod_stats_dump(struct mod_stats *mod_stats)
struct dal_logger *logger = NULL;
struct core_stats *core_stats = NULL;
struct stats_time_cache *time = NULL;
+   struct stats_event_cache *events = NULL;
+   unsigned int time_index = 1;
+   unsigned int event_index = 0;
unsigned int index = 0;
struct log_entry log_entry;
 
@@ -177,6 +209,7 @@ void mod_stats_dump(struct mod_stats *mod_stats)
dc = core_stats->dc;
logger = dc->ctx->logger;
time = core_stats->time;
+   events = core_stats->events;
 
DISPLAY_STATS_BEGIN(log_entry);
 
@@ -196,30 +229,39 @@ void mod_stats_dump(struct mod_stats *mod_stats)
"vSyncTime1", "vSyncTime2", "vSyncTime3",
"vSyncTime4", "vSyncTime5", "flags");
 
-   for (int i = 0; i < core_stats->index && i < core_stats->entries; i++) {
-   DISPLAY_STATS("%10u %10u %10u %10u %10u"
-   " %11u %11u %17u %10u %14u"
-   " %10u %10u %10u %10u %10u"
-   " %10u %10u %10u %10u\n",
-   time[i].render_time_in_us,
-   time[i].avg_render_time_in_us_last_ten,
-   time[i].min_window,
- 

[PATCH 24/25] drm/amd/display: fix memory leaks

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/modules/stats/stats.c | 24 ---
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/stats/stats.c 
b/drivers/gpu/drm/amd/display/modules/stats/stats.c
index fe9e4b316d3a..3f7d47fdc367 100644
--- a/drivers/gpu/drm/amd/display/modules/stats/stats.c
+++ b/drivers/gpu/drm/amd/display/modules/stats/stats.c
@@ -115,12 +115,12 @@ struct mod_stats *mod_stats_create(struct dc *dc)
unsigned int reg_data;
int i = 0;
 
+   if (dc == NULL)
+   goto fail_construct;
+
core_stats = kzalloc(sizeof(struct core_stats), GFP_KERNEL);
 
if (core_stats == NULL)
-   goto fail_alloc_context;
-
-   if (dc == NULL)
goto fail_construct;
 
core_stats->dc = dc;
@@ -146,6 +146,8 @@ struct mod_stats *mod_stats_create(struct dc *dc)
core_stats->entries,
GFP_KERNEL);
 
+   if (core_stats->time == NULL)
+   goto fail_construct_time;
 
core_stats->event_entries = DAL_STATS_EVENT_ENTRIES_DEFAULT;
core_stats->events = kzalloc(
@@ -153,13 +155,13 @@ struct mod_stats *mod_stats_create(struct dc *dc)
core_stats->event_entries,
GFP_KERNEL);
 
+   if (core_stats->events == NULL)
+   goto fail_construct_events;
+
} else {
core_stats->entries = 0;
}
 
-   if (core_stats->time == NULL)
-   goto fail_construct;
-
/* Purposely leave index 0 unused so we don't need special logic to
 * handle calculation cases that depend on previous flip data.
 */
@@ -171,10 +173,13 @@ struct mod_stats *mod_stats_create(struct dc *dc)
 
return _stats->public;
 
-fail_construct:
+fail_construct_events:
+   kfree(core_stats->time);
+
+fail_construct_time:
kfree(core_stats);
 
-fail_alloc_context:
+fail_construct:
return NULL;
 }
 
@@ -186,6 +191,9 @@ void mod_stats_destroy(struct mod_stats *mod_stats)
if (core_stats->time != NULL)
kfree(core_stats->time);
 
+   if (core_stats->events != NULL)
+   kfree(core_stats->events);
+
kfree(core_stats);
}
 }
-- 
2.17.0

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[PATCH 16/25] drm/amd/display: use macro for logs

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../amd/display/include/logger_interface.h|  9 +
 .../gpu/drm/amd/display/modules/stats/stats.c | 19 ++-
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h 
b/drivers/gpu/drm/amd/display/include/logger_interface.h
index 28dee960d509..dc98d6d4b2bd 100644
--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
@@ -190,4 +190,13 @@ void context_clock_trace(
} \
 } while (0)
 
+#define DISPLAY_STATS_BEGIN(entry) \
+   dm_logger_open(dc->ctx->logger, , LOG_DISPLAYSTATS)
+
+#define DISPLAY_STATS(msg, ...) \
+   dm_logger_append(_entry, msg, ##__VA_ARGS__)
+
+#define DISPLAY_STATS_END(entry) \
+   dm_logger_close()
+
 #endif /* __DAL_LOGGER_INTERFACE_H__ */
diff --git a/drivers/gpu/drm/amd/display/modules/stats/stats.c 
b/drivers/gpu/drm/amd/display/modules/stats/stats.c
index ae2d92b73cf1..45acdbc3c08a 100644
--- a/drivers/gpu/drm/amd/display/modules/stats/stats.c
+++ b/drivers/gpu/drm/amd/display/modules/stats/stats.c
@@ -178,19 +178,13 @@ void mod_stats_dump(struct mod_stats *mod_stats)
logger = dc->ctx->logger;
time = core_stats->time;
 
-   dm_logger_open(
-   dc->ctx->logger,
-   _entry,
-   LOG_DISPLAYSTATS);
+   DISPLAY_STATS_BEGIN(log_entry);
 
-   dm_logger_append(_entry, "==Display Caps==\n");
-   dm_logger_append(_entry, "\n");
+   DISPLAY_STATS("==Display Caps==\n");
 
-   dm_logger_append(_entry, "==Display Stats==\n");
-   dm_logger_append(_entry, "\n");
+   DISPLAY_STATS("==Display Stats==\n");
 
-   dm_logger_append(_entry,
-   "%10s %10s %10s %10s %10s"
+   DISPLAY_STATS("%10s %10s %10s %10s %10s"
" %11s %11s %17s %10s %14s"
" %10s %10s %10s %10s %10s"
" %10s %10s %10s %10s\n",
@@ -203,8 +197,7 @@ void mod_stats_dump(struct mod_stats *mod_stats)
"vSyncTime4", "vSyncTime5", "flags");
 
for (int i = 0; i < core_stats->index && i < core_stats->entries; i++) {
-   dm_logger_append(_entry,
-   "%10u %10u %10u %10u %10u"
+   DISPLAY_STATS("%10u %10u %10u %10u %10u"
" %11u %11u %17u %10u %14u"
" %10u %10u %10u %10u %10u"
" %10u %10u %10u %10u\n",
@@ -229,7 +222,7 @@ void mod_stats_dump(struct mod_stats *mod_stats)
time[i].flags);
}
 
-   dm_logger_close(_entry);
+   DISPLAY_STATS_END(log_entry);
 }
 
 void mod_stats_reset_data(struct mod_stats *mod_stats)
-- 
2.17.0

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[PATCH 22/25] drm/amd/display: Clear underflow status for debug purposes

[Harry Wentland]

From: Nikola Cornij 

We want to keep underflow sticky bit on for the longevity tests outside
of test environment. For debug purposes it is, however, useful to clear
underflow status after the test that caused it so that the following
tests are not affected. This change fullfils both requirements by clearing
the underflow only from within Windows or Diags test environment.

Signed-off-by: Nikola Cornij 
Reviewed-by: Nikola Cornij 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 400d0ca85110..c40993a59ca4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -326,6 +326,12 @@ void dcn10_log_hw_state(struct dc *dc)
s.h_total,
s.v_total,
s.underflow_occurred_status);
+
+   // Clear underflow for debug purposes
+   // We want to keep underflow sticky bit on for the longevity 
tests outside of test environment.
+   // This function is called only from Windows or Diags test 
environment, hence it's safe to clear
+   // it from here without affecting the original intent.
+   tg->funcs->clear_optc_underflow(tg);
}
DTN_INFO("\n");
 
-- 
2.17.0

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[PATCH 18/25] drm/amd/display: Only limit VSR downscaling when actually downscaling

[Harry Wentland]

From: Xingyue Tao 

Signed-off-by: Xingyue Tao 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  | 21 +--
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 2da138904312..46a35c7f01df 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -145,18 +145,17 @@ bool dpp_get_optimal_number_of_taps(
else
pixel_width = scl_data->viewport.width;
 
+   /* Some ASICs does not support  FP16 scaling, so we reject modes 
require this*/
if (scl_data->viewport.width  != scl_data->h_active &&
-   scl_data->viewport.height != scl_data->v_active) {
-
-   /* Some ASICs does not support  FP16 scaling, so we reject 
modes require this*/
-   if (dpp->caps->dscl_data_proc_format == 
DSCL_DATA_PRCESSING_FIXED_FORMAT &&
-   scl_data->format == PIXEL_FORMAT_FP16)
-   return false;
-
-   if (dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
-   scl_data->viewport.width > 
dpp->ctx->dc->debug.max_downscale_src_width)
-   return false;
-   }
+   scl_data->viewport.height != scl_data->v_active &&
+   dpp->caps->dscl_data_proc_format == 
DSCL_DATA_PRCESSING_FIXED_FORMAT &&
+   scl_data->format == PIXEL_FORMAT_FP16)
+   return false;
+
+   if (scl_data->viewport.width > scl_data->h_active &&
+   dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
+   scl_data->viewport.width > 
dpp->ctx->dc->debug.max_downscale_src_width)
+   return false;
 
/* TODO: add lb check */
 
-- 
2.17.0

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[PATCH 23/25] drm/amd/display: DCN1 link encoder

[Harry Wentland]

From: Eric Bernstein 

Create DCN1 link encoder files and update AUX and HPD register access.

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/core/dc_link_hwss.c|2 -
 drivers/gpu/drm/amd/display/dc/dcn10/Makefile |2 +-
 .../amd/display/dc/dcn10/dcn10_link_encoder.c | 1362 +
 .../amd/display/dc/dcn10/dcn10_link_encoder.h |  330 
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |   43 +-
 5 files changed, 1716 insertions(+), 23 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 7c866a7d5e77..82cd1d6e6e59 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -11,8 +11,6 @@
 #include "dc_link_dp.h"
 #include "dc_link_ddc.h"
 #include "dm_helpers.h"
-#include "dce/dce_link_encoder.h"
-#include "dce/dce_stream_encoder.h"
 #include "dpcd_defs.h"
 
 enum dc_status core_link_read_dpcd(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
index 5c69743a4b4f..84f52c63d95c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
@@ -26,7 +26,7 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
dcn10_hubp.o dcn10_mpc.o \
dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
-   dcn10_hubbub.o dcn10_stream_encoder.o
+   dcn10_hubbub.o dcn10_stream_encoder.o dcn10_link_encoder.o
 
 AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
new file mode 100644
index ..21fa40ac0786
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -0,0 +1,1362 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+
+#include "core_types.h"
+#include "link_encoder.h"
+#include "dcn10_link_encoder.h"
+#include "stream_encoder.h"
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+
+#include "gpio_service_interface.h"
+
+#define CTX \
+   enc10->base.ctx
+#define DC_LOGGER \
+   enc10->base.ctx->logger
+
+#define REG(reg)\
+   (enc10->link_regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+   enc10->link_shift->field_name, enc10->link_mask->field_name
+
+
+/*
+ * @brief
+ * Trigger Source Select
+ * ASIC-dependent, actual values for register programming
+ */
+#define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40
+
+enum {
+   DP_MST_UPDATE_MAX_RETRY = 50
+};
+
+
+
+static void aux_initialize(struct dcn10_link_encoder *enc10);
+
+
+static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
+   .validate_output_with_stream =
+   dcn10_link_encoder_validate_output_with_stream,
+   .hw_init = dcn10_link_encoder_hw_init,
+   .setup = dcn10_link_encoder_setup,
+   .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+   .enable_dp_output = dcn10_link_encoder_enable_dp_output,
+   .enable_dp_mst_output = 

[PATCH 11/25] drm/amd/display: Add dc cap to restrict VSR downscaling src size

[Harry Wentland]

From: Xingyue Tao 

- Adds int max_downscale_src_width in dc struct
- Checks and does not support if downscale size is more than 4k (width > 3840)

Signed-off-by: Xingyue Tao 
Reviewed-by: Charlene Liu 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h  |  1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 16 +++-
 .../drm/amd/display/dc/dcn10/dcn10_resource.c|  1 +
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1c39c9996a04..08b29a742921 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -203,6 +203,7 @@ struct dc_debug {
bool clock_trace;
bool validation_trace;
bool bandwidth_calcs_trace;
+   int max_downscale_src_width;
 
/* stutter efficiency related */
bool disable_stutter;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 20796da36de4..2da138904312 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -145,12 +145,18 @@ bool dpp_get_optimal_number_of_taps(
else
pixel_width = scl_data->viewport.width;
 
-   /* Some ASICs does not support  FP16 scaling, so we reject modes 
require this*/
if (scl_data->viewport.width  != scl_data->h_active &&
-   scl_data->viewport.height != scl_data->v_active &&
-   dpp->caps->dscl_data_proc_format == 
DSCL_DATA_PRCESSING_FIXED_FORMAT &&
-   scl_data->format == PIXEL_FORMAT_FP16)
-   return false;
+   scl_data->viewport.height != scl_data->v_active) {
+
+   /* Some ASICs does not support  FP16 scaling, so we reject 
modes require this*/
+   if (dpp->caps->dscl_data_proc_format == 
DSCL_DATA_PRCESSING_FIXED_FORMAT &&
+   scl_data->format == PIXEL_FORMAT_FP16)
+   return false;
+
+   if (dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
+   scl_data->viewport.width > 
dpp->ctx->dc->debug.max_downscale_src_width)
+   return false;
+   }
 
/* TODO: add lb check */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 16c84e9ee33b..f69f3a54f001 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -447,6 +447,7 @@ static const struct dc_debug debug_defaults_drv = {
.performance_trace = false,
.az_endpoint_mute_only = true,
.recovery_enabled = false, /*enable this by default after 
testing.*/
+   .max_downscale_src_width = 3840,
 };
 
 static const struct dc_debug debug_defaults_diags = {
-- 
2.17.0

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[PATCH 25/25] drm/amd/display: Clear connector's edid pointer

[Harry Wentland]

From: Mikita Lipski 

Clear connector's edid pointer on coonnector update, when unplugging
the display.

Fix poison EDID when hotplugging on previously used connector.

Signed-off-by: Mikita Lipski 
Reviewed-by: Harry Wentland 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1a63c04b2016..b80d2134b9ea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -907,6 +907,7 @@ amdgpu_dm_update_connector_after_detect(struct 
amdgpu_dm_connector *aconnector)
drm_mode_connector_update_edid_property(connector, NULL);
aconnector->num_modes = 0;
aconnector->dc_sink = NULL;
+   aconnector->edid = NULL;
}
 
mutex_unlock(>mode_config.mutex);
-- 
2.17.0

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[PATCH 21/25] drm/amd/display: fix bug with index check

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/modules/stats/stats.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/stats/stats.c 
b/drivers/gpu/drm/amd/display/modules/stats/stats.c
index 4b00bae725b9..fe9e4b316d3a 100644
--- a/drivers/gpu/drm/amd/display/modules/stats/stats.c
+++ b/drivers/gpu/drm/amd/display/modules/stats/stats.c
@@ -305,7 +305,7 @@ void mod_stats_update_event(struct mod_stats *mod_stats,
 
core_stats = MOD_STATS_TO_CORE(mod_stats);
 
-   if (core_stats->index >= core_stats->entries)
+   if (core_stats->event_index >= core_stats->event_entries)
return;
 
events = core_stats->events;
-- 
2.17.0

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[PATCH 19/25] drm/amd/display: constify a few dc_surface_update fields

[Harry Wentland]

From: Jun Lei 

Signed-off-by: Jun Lei 
Reviewed-by: Jun Lei 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7a9f600662ce..9cfde0ccf4e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -503,18 +503,18 @@ struct dc_surface_update {
struct dc_plane_state *surface;
 
/* isr safe update parameters.  null means no updates */
-   struct dc_flip_addrs *flip_addr;
-   struct dc_plane_info *plane_info;
-   struct dc_scaling_info *scaling_info;
+   const struct dc_flip_addrs *flip_addr;
+   const struct dc_plane_info *plane_info;
+   const struct dc_scaling_info *scaling_info;
 
/* following updates require alloc/sleep/spin that is not isr safe,
 * null means no updates
 */
-   struct dc_gamma *gamma;
-   struct dc_transfer_func *in_transfer_func;
+   const struct dc_gamma *gamma;
+   const struct dc_transfer_func *in_transfer_func;
 
-   struct dc_csc_transform *input_csc_color_matrix;
-   struct fixed31_32 *coeff_reduction_factor;
+   const struct dc_csc_transform *input_csc_color_matrix;
+   const struct fixed31_32 *coeff_reduction_factor;
 };
 
 /*
-- 
2.17.0

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[PATCH 17/25] drm/amd/display: don't create new dc_sink if nothing changed at detection

[Harry Wentland]

From: Samson Tam 

Signed-off-by: Samson Tam 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 95 +++
 1 file changed, 77 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ea5d5ffd5522..2fa521812d23 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -469,6 +469,13 @@ static void link_disconnect_sink(struct dc_link *link)
link->dpcd_sink_count = 0;
 }
 
+static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link 
*link)
+{
+   dc_sink_release(link->local_sink);
+   link->local_sink = prev_sink;
+}
+
+
 static bool detect_dp(
struct dc_link *link,
struct display_sink_capability *sink_caps,
@@ -551,6 +558,17 @@ static bool detect_dp(
return true;
 }
 
+static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
+{
+   if (old_edid->length != new_edid->length)
+   return false;
+
+   if (new_edid->length == 0)
+   return false;
+
+   return (memcmp(old_edid->raw_edid, new_edid->raw_edid, 
new_edid->length) == 0);
+}
+
 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 {
struct dc_sink_init_data sink_init_data = { 0 };
@@ -558,9 +576,13 @@ bool dc_link_detect(struct dc_link *link, enum 
dc_detect_reason reason)
uint8_t i;
bool converter_disable_audio = false;
struct audio_support *aud_support = >dc->res_pool->audio_support;
+   bool same_edid = false;
enum dc_edid_status edid_status;
struct dc_context *dc_ctx = link->ctx;
struct dc_sink *sink = NULL;
+   struct dc_sink *prev_sink = NULL;
+   struct dpcd_caps prev_dpcd_caps;
+   bool same_dpcd = true;
enum dc_connection_type new_connection_type = dc_connection_none;
DC_LOGGER_INIT(link->ctx->logger);
if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
@@ -575,6 +597,11 @@ bool dc_link_detect(struct dc_link *link, enum 
dc_detect_reason reason)
link->local_sink)
return true;
 
+   prev_sink = link->local_sink;
+   if (prev_sink != NULL) {
+   dc_sink_retain(prev_sink);
+   memcpy(_dpcd_caps, >dpcd_caps, sizeof(struct 
dpcd_caps));
+   }
link_disconnect_sink(link);
 
if (new_connection_type != dc_connection_none) {
@@ -616,14 +643,25 @@ bool dc_link_detect(struct dc_link *link, enum 
dc_detect_reason reason)
link,
_caps,
_disable_audio,
-   aud_support, reason))
+   aud_support, reason)) {
+   if (prev_sink != NULL)
+   dc_sink_release(prev_sink);
return false;
+   }
 
+   // Check if dpcp block is the same
+   if (prev_sink != NULL) {
+   if (memcmp(>dpcd_caps, _dpcd_caps, 
sizeof(struct dpcd_caps)))
+   same_dpcd = false;
+   }
/* Active dongle downstream unplug */
if (link->type == dc_connection_active_dongle
&& link->dpcd_caps.sink_count.
-   bits.SINK_COUNT == 0)
+   bits.SINK_COUNT == 0) {
+   if (prev_sink != NULL)
+   dc_sink_release(prev_sink);
return true;
+   }
 
if (link->type == dc_connection_mst_branch) {
LINK_INFO("link=%d, mst branch is now 
Connected\n",
@@ -634,6 +672,8 @@ bool dc_link_detect(struct dc_link *link, enum 
dc_detect_reason reason)
 * pbn_per_slot value leading to exception on 
dc_fixpt_div()
 */
link->verified_link_cap = 
link->reported_link_cap;
+   if (prev_sink != NULL)
+   dc_sink_release(prev_sink);
return false;
}
 
@@ -643,6 +683,8 @@ bool dc_link_detect(struct dc_link *link, enum 
dc_detect_reason reason)
default:
DC_ERROR("Invalid connector type! signal:%d\n",
link->connector_signal);
+   if (prev_sink != NULL)
+   dc_sink_release(prev_sink);

[PATCH 14/25] drm/amd/display: update dml to allow sync with DV

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../amd/display/dc/dml/display_mode_enums.h   |  13 +
 .../amd/display/dc/dml/display_mode_structs.h | 962 +-
 .../drm/amd/display/dc/dml/dml_inline_defs.h  |  10 +
 3 files changed, 515 insertions(+), 470 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index b1ad3553f900..47c19f8fe7d1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -108,4 +108,17 @@ enum output_standard {
dm_std_uninitialized = 0, dm_std_cvtr2, dm_std_cvt
 };
 
+enum mpc_combine_affinity {
+   dm_mpc_always_when_possible,
+   dm_mpc_reduce_voltage,
+   dm_mpc_reduce_voltage_and_clocks
+};
+
+enum self_refresh_affinity {
+   dm_try_to_allow_self_refresh_and_mclk_switch,
+   dm_allow_self_refresh_and_mclk_switch,
+   dm_allow_self_refresh,
+   dm_neither_self_refresh_nor_mclk_switch
+};
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index ce750edc1e5f..7fa0375939ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -25,39 +25,39 @@
 #ifndef __DISPLAY_MODE_STRUCTS_H__
 #define __DISPLAY_MODE_STRUCTS_H__
 
-typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
-typedef struct _vcs_dpi_soc_bounding_box_stsoc_bounding_box_st;
-typedef struct _vcs_dpi_ip_params_st   ip_params_st;
-typedef struct _vcs_dpi_display_pipe_source_params_st  
display_pipe_source_params_st;
-typedef struct _vcs_dpi_display_output_params_st   
display_output_params_st;
-typedef struct _vcs_dpi_display_bandwidth_st   display_bandwidth_st;
-typedef struct _vcs_dpi_scaler_ratio_depth_st  scaler_ratio_depth_st;
-typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
-typedef struct _vcs_dpi_display_pipe_dest_params_st
display_pipe_dest_params_st;
-typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
-typedef struct _vcs_dpi_display_clocks_and_cfg_st  
display_clocks_and_cfg_st;
-typedef struct _vcs_dpi_display_e2e_pipe_params_st 
display_e2e_pipe_params_st;
-typedef struct _vcs_dpi_dchub_buffer_sizing_st dchub_buffer_sizing_st;
-typedef struct _vcs_dpi_watermarks_perf_st watermarks_perf_st;
-typedef struct _vcs_dpi_cstate_pstate_watermarks_st
cstate_pstate_watermarks_st;
-typedef struct _vcs_dpi_wm_calc_pipe_params_st wm_calc_pipe_params_st;
-typedef struct _vcs_dpi_vratio_pre_st  vratio_pre_st;
-typedef struct _vcs_dpi_display_data_rq_misc_params_st 
display_data_rq_misc_params_st;
-typedef struct _vcs_dpi_display_data_rq_sizing_params_st   
display_data_rq_sizing_params_st;
-typedef struct _vcs_dpi_display_data_rq_dlg_params_st  
display_data_rq_dlg_params_st;
-typedef struct _vcs_dpi_display_cur_rq_dlg_params_st   
display_cur_rq_dlg_params_st;
-typedef struct _vcs_dpi_display_rq_dlg_params_st   
display_rq_dlg_params_st;
-typedef struct _vcs_dpi_display_rq_sizing_params_st
display_rq_sizing_params_st;
-typedef struct _vcs_dpi_display_rq_misc_params_st  
display_rq_misc_params_st;
-typedef struct _vcs_dpi_display_rq_params_st   display_rq_params_st;
-typedef struct _vcs_dpi_display_dlg_regs_stdisplay_dlg_regs_st;
-typedef struct _vcs_dpi_display_ttu_regs_stdisplay_ttu_regs_st;
-typedef struct _vcs_dpi_display_data_rq_regs_stdisplay_data_rq_regs_st;
-typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
-typedef struct _vcs_dpi_display_dlg_sys_params_st  
display_dlg_sys_params_st;
-typedef struct _vcs_dpi_display_dlg_prefetch_param_st  
display_dlg_prefetch_param_st;
-typedef struct _vcs_dpi_display_pipe_clock_st  display_pipe_clock_st;
-typedef struct _vcs_dpi_display_arb_params_st  display_arb_params_st;
+typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
+typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
+typedef struct _vcs_dpi_ip_params_st ip_params_st;
+typedef struct _vcs_dpi_display_pipe_source_params_st 
display_pipe_source_params_st;
+typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
+typedef struct _vcs_dpi_display_bandwidth_st display_bandwidth_st;
+typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
+typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
+typedef struct _vcs_dpi_display_pipe_dest_params_st 
display_pipe_dest_params_st;
+typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
+typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
+typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;

[PATCH 13/25] drm/amd/display: Log DTN only after the atomic commit in Diag

[Harry Wentland]

From: Nikola Cornij 

Also print HUBP info only if pipe enabled. This fixes having different
DTN logs for different test sequences.

Signed-off-by: Nikola Cornij 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 119 +-
 1 file changed, 62 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 858529e43282..400d0ca85110 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -127,24 +127,26 @@ static void dcn10_log_hubp_states(struct dc *dc)
 
hubp->funcs->hubp_read_state(hubp);
 
-   DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh"
-   "  %6d  %8d  %7d  %8xh",
-   hubp->inst,
-   s->pixel_format,
-   s->inuse_addr_hi,
-   s->viewport_width,
-   s->viewport_height,
-   s->rotation_angle,
-   s->h_mirror_en,
-   s->sw_mode,
-   s->dcc_en,
-   s->blank_en,
-   s->ttu_disable,
-   s->underflow_status);
-   DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
-   DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
-   DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
-   DTN_INFO("\n");
+   if (!s->blank_en) {
+   DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  
%6xh"
+   "  %6d  %8d  %7d  %8xh",
+   hubp->inst,
+   s->pixel_format,
+   s->inuse_addr_hi,
+   s->viewport_width,
+   s->viewport_height,
+   s->rotation_angle,
+   s->h_mirror_en,
+   s->sw_mode,
+   s->dcc_en,
+   s->blank_en,
+   s->ttu_disable,
+   s->underflow_status);
+   DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
+   DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
+   DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
+   DTN_INFO("\n");
+   }
}
 
DTN_INFO("\n=RQ\n");
@@ -155,16 +157,17 @@ static void dcn10_log_hubp_states(struct dc *dc)
struct dcn_hubp_state *s = 
&(TO_DCN10_HUBP(pool->hubps[i])->state);
struct _vcs_dpi_display_rq_regs_st *rq_regs = >rq_regs;
 
-   DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  
%8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  
%8xh\n",
-   i, rq_regs->drq_expansion_mode, 
rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
-   rq_regs->crq_expansion_mode, 
rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
-   rq_regs->rq_regs_l.min_chunk_size, 
rq_regs->rq_regs_l.meta_chunk_size,
-   rq_regs->rq_regs_l.min_meta_chunk_size, 
rq_regs->rq_regs_l.dpte_group_size,
-   rq_regs->rq_regs_l.mpte_group_size, 
rq_regs->rq_regs_l.swath_height,
-   rq_regs->rq_regs_l.pte_row_height_linear, 
rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
-   rq_regs->rq_regs_c.meta_chunk_size, 
rq_regs->rq_regs_c.min_meta_chunk_size,
-   rq_regs->rq_regs_c.dpte_group_size, 
rq_regs->rq_regs_c.mpte_group_size,
-   rq_regs->rq_regs_c.swath_height, 
rq_regs->rq_regs_c.pte_row_height_linear);
+   if (!s->blank_en)
+   DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  
%8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  
%8xh  %8xh\n",
+   pool->hubps[i]->inst, 
rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, 
rq_regs->mrq_expansion_mode,
+   rq_regs->crq_expansion_mode, 
rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
+   rq_regs->rq_regs_l.min_chunk_size, 
rq_regs->rq_regs_l.meta_chunk_size,
+   rq_regs->rq_regs_l.min_meta_chunk_size, 
rq_regs->rq_regs_l.dpte_group_size,
+ 

[PATCH 12/25] drm/amd/display: disable mpo if brightness adjusted

[Harry Wentland]

From: Yue Hin Lau 

Signed-off-by: Yue Hin Lau 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h   | 1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 08b29a742921..7a9f600662ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -75,6 +75,7 @@ struct dc_caps {
bool dynamic_audio;
bool is_apu;
bool dual_link_dvi;
+   bool post_blend_color_processing;
 };
 
 struct dc_dcc_surface_param {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index f69f3a54f001..ace2e03dced4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1023,6 +1023,7 @@ static bool construct(
dc->caps.max_cursor_size = 256;
dc->caps.max_slave_planes = 1;
dc->caps.is_apu = true;
+   dc->caps.post_blend_color_processing = false;
 
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
-- 
2.17.0

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[PATCH 09/25] drm/amd/display: fix 31_32_fixpt shift functions

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Yang 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/include/fixed31_32.h  | 26 +--
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 61f11e23bf70..bd8a30462258 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -27,6 +27,12 @@
 #define __DAL_FIXED31_32_H__
 
 #define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
+#ifndef LLONG_MIN
+#define LLONG_MIN (1LL<<63)
+#endif
+#ifndef LLONG_MAX
+#define LLONG_MAX (-1LL>>1)
+#endif
 
 /*
  * @brief
@@ -45,6 +51,7 @@ struct fixed31_32 {
long long value;
 };
 
+
 /*
  * @brief
  * Useful constants
@@ -201,14 +208,12 @@ static inline struct fixed31_32 dc_fixpt_clamp(
  */
 static inline struct fixed31_32 dc_fixpt_shl(struct fixed31_32 arg, unsigned 
char shift)
 {
-   struct fixed31_32 res;
-
ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
-   ((arg.value < 0) && (arg.value >= LLONG_MIN >> shift)));
+   ((arg.value < 0) && (arg.value >= (LLONG_MIN / (1 << shift);
 
-   res.value = arg.value << shift;
+   arg.value = arg.value << shift;
 
-   return res;
+   return arg;
 }
 
 /*
@@ -217,9 +222,14 @@ static inline struct fixed31_32 dc_fixpt_shl(struct 
fixed31_32 arg, unsigned cha
  */
 static inline struct fixed31_32 dc_fixpt_shr(struct fixed31_32 arg, unsigned 
char shift)
 {
-   struct fixed31_32 res;
-   res.value = arg.value >> shift;
-   return res;
+   bool negative = arg.value < 0;
+
+   if (negative)
+   arg.value = -arg.value;
+   arg.value = arg.value >> shift;
+   if (negative)
+   arg.value = -arg.value;
+   return arg;
 }
 
 /*
-- 
2.17.0

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[PATCH 07/25] drm/amd/display: underflow/blankscreen recovery

[Harry Wentland]

From: Charlene Liu 

[Description]
for any reason, if driver detects HUBP underflow,
if a debug option enabled to enable recovery.
it will kick in a sequence of recovery.

Signed-off-by: Charlene Liu 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h   |  2 +
 .../drm/amd/display/dc/dcn10/dcn10_hubbub.c   |  8 ++
 .../drm/amd/display/dc/dcn10/dcn10_hubbub.h   |  7 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 24 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  3 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 90 ++-
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |  2 +
 8 files changed, 135 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index cd4f4341cb53..1c39c9996a04 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -239,6 +239,8 @@ struct dc_debug {
bool az_endpoint_mute_only;
bool always_use_regamma;
bool p010_mpo_support;
+   bool recovery_enabled;
+
 };
 struct dc_state;
 struct resource_pool;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index b9fb14a3224b..943143efbb82 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -476,6 +476,14 @@ void hubbub1_toggle_watermark_change_req(struct hubbub 
*hubbub)
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 
watermark_change_req);
 }
 
+void hubbub1_soft_reset(struct hubbub *hubbub, bool reset)
+{
+   uint32_t reset_en = reset ? 1 : 0;
+
+   REG_UPDATE(DCHUBBUB_SOFT_RESET,
+   DCHUBBUB_GLOBAL_SOFT_RESET, reset_en);
+}
+
 static bool hubbub1_dcc_support_swizzle(
enum swizzle_mode_values swizzle,
unsigned int bytes_per_element,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index f479f54e5bb2..6315a0e6b0d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -48,7 +48,8 @@
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
SR(DCHUBBUB_TEST_DEBUG_INDEX), \
-   SR(DCHUBBUB_TEST_DEBUG_DATA)
+   SR(DCHUBBUB_TEST_DEBUG_DATA),\
+   SR(DCHUBBUB_SOFT_RESET)
 
 #define HUBBUB_SR_WATERMARK_REG_LIST()\
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
@@ -105,6 +106,7 @@ struct dcn_hubbub_registers {
uint32_t DCHUBBUB_SDPIF_AGP_BOT;
uint32_t DCHUBBUB_SDPIF_AGP_TOP;
uint32_t DCHUBBUB_CRC_CTRL;
+   uint32_t DCHUBBUB_SOFT_RESET;
 };
 
 /* set field name */
@@ -114,6 +116,7 @@ struct dcn_hubbub_registers {
 
 #define HUBBUB_MASK_SH_LIST_DCN(mask_sh)\
HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, 
DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
+   HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, 
mask_sh), \
HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, 
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, 
DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, 
DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
@@ -143,6 +146,7 @@ struct dcn_hubbub_registers {
type DCHUBBUB_ARB_SAT_LEVEL;\
type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
type DCHUBBUB_GLOBAL_TIMER_REFDIV;\
+   type DCHUBBUB_GLOBAL_SOFT_RESET; \
type SDPIF_FB_TOP;\
type SDPIF_FB_BASE;\
type SDPIF_FB_OFFSET;\
@@ -201,6 +205,7 @@ void hubbub1_toggle_watermark_change_req(
 void hubbub1_wm_read_state(struct hubbub *hubbub,
struct dcn_hubbub_wm *wm);
 
+void hubbub1_soft_reset(struct hubbub *hubbub, bool reset);
 void hubbub1_construct(struct hubbub *hubbub,
struct dc_context *ctx,
const struct dcn_hubbub_registers *hubbub_regs,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 185f93bda41b..d2ab78b35a7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -78,6 +78,27 @@ static void hubp1_disconnect(struct hubp *hubp)
CURSOR_ENABLE, 0);
 }
 
+static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)
+{
+   struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+   uint32_t disable = disable_hubp ? 1 : 0;
+
+   REG_UPDATE(DCHUBP_CNTL,
+   HUBP_DISABLE, disable);
+}
+
+static unsigned int 

[PATCH 10/25] drm/amd/display: fix a 32 bit shift meant to be 64 warning

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/include/fixed31_32.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index bd8a30462258..76f64e910422 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -209,7 +209,7 @@ static inline struct fixed31_32 dc_fixpt_clamp(
 static inline struct fixed31_32 dc_fixpt_shl(struct fixed31_32 arg, unsigned 
char shift)
 {
ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
-   ((arg.value < 0) && (arg.value >= (LLONG_MIN / (1 << shift);
+   ((arg.value < 0) && (arg.value >= (LLONG_MIN / (1LL << 
shift);
 
arg.value = arg.value << shift;
 
-- 
2.17.0

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[PATCH 08/25] drm/amd/display: Update HW sequencer initialization

[Harry Wentland]

From: Eric Bernstein 

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  6 +++---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h  |  2 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c  | 10 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h  | 10 ++
 4 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ada55a920d93..858529e43282 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -864,7 +864,7 @@ static void dcn10_verify_allow_pstate_change_high(struct dc 
*dc)
 }
 
 /* trigger HW to start disconnect plane from stream on the next vsync */
-static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
struct hubp *hubp = pipe_ctx->plane_res.hubp;
int dpp_id = pipe_ctx->plane_res.dpp->inst;
@@ -1047,7 +1047,7 @@ static void dcn10_init_hw(struct dc *dc)

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = 
true;
pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
 
-   plane_atomic_disconnect(dc, pipe_ctx);
+   hwss1_plane_atomic_disconnect(dc, pipe_ctx);
}
 
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -2282,7 +2282,7 @@ static void dcn10_apply_ctx_for_surface(
old_pipe_ctx->plane_state &&
old_pipe_ctx->stream_res.tg == tg) {
 
-   plane_atomic_disconnect(dc, old_pipe_ctx);
+   hwss1_plane_atomic_disconnect(dc, old_pipe_ctx);
removed_pipe[i] = true;
 
DC_LOG_DC(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 6c526b5095d9..44f734b73f9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -37,4 +37,6 @@ extern void fill_display_configs(
 
 bool is_rgb_cspace(enum dc_color_space output_color_space);
 
+void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
+
 #endif /* __DC_HWSS_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index c734b7fa5835..f2fbce0e3fc5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -360,7 +360,7 @@ void optc1_program_timing(
 
 }
 
-static void optc1_set_blank_data_double_buffer(struct timing_generator *optc, 
bool enable)
+void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool 
enable)
 {
struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
@@ -1257,20 +1257,20 @@ void optc1_read_otg_state(struct optc *optc1,
OPTC_UNDERFLOW_OCCURRED_STATUS, 
>underflow_occurred_status);
 }
 
-static void optc1_clear_optc_underflow(struct timing_generator *optc)
+void optc1_clear_optc_underflow(struct timing_generator *optc)
 {
struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
 }
 
-static void optc1_tg_init(struct timing_generator *optc)
+void optc1_tg_init(struct timing_generator *optc)
 {
optc1_set_blank_data_double_buffer(optc, true);
optc1_clear_optc_underflow(optc);
 }
 
-static bool optc1_is_tg_enabled(struct timing_generator *optc)
+bool optc1_is_tg_enabled(struct timing_generator *optc)
 {
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t otg_enabled = 0;
@@ -1281,7 +1281,7 @@ static bool optc1_is_tg_enabled(struct timing_generator 
*optc)
 
 }
 
-static bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
+bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
 {
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t underflow_occurred = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 89e09e5327a2..c62052f46460 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -497,4 +497,14 @@ void optc1_program_stereo(struct timing_generator *optc,
 
 bool optc1_is_stereo_left_eye(struct timing_generator *optc);
 
+void optc1_clear_optc_underflow(struct timing_generator *optc);
+
+void optc1_tg_init(struct timing_generator *optc);
+
+bool optc1_is_tg_enabled(struct timing_generator *optc);
+
+bool 

[PATCH 05/25] drm/amd/display: add fixed point fractional bit truncation function

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/include/fixed31_32.h| 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index ebfd33e91ee8..61f11e23bf70 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -496,4 +496,21 @@ unsigned int dc_fixpt_clamp_u0d10(struct fixed31_32 arg);
 
 int dc_fixpt_s4d19(struct fixed31_32 arg);
 
+static inline struct fixed31_32 dc_fixpt_truncate(struct fixed31_32 arg, 
unsigned int frac_bits)
+{
+   bool negative = arg.value < 0;
+
+   if (frac_bits >= FIXED31_32_BITS_PER_FRACTIONAL_PART) {
+   ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART);
+   return arg;
+   }
+
+   if (negative)
+   arg.value = -arg.value;
+   arg.value &= (~0LL) << (FIXED31_32_BITS_PER_FRACTIONAL_PART - 
frac_bits);
+   if (negative)
+   arg.value = -arg.value;
+   return arg;
+}
+
 #endif
-- 
2.17.0

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[PATCH 01/25] drm/amd/display: Cleanup unused SetPlaneConfig

[Harry Wentland]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 .../display/dc/dce110/dce110_hw_sequencer.c   | 69 ---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 ---
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  5 --
 3 files changed, 84 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 55ef690609c3..dd87afc7790e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2287,74 +2287,6 @@ static void program_gamut_remap(struct pipe_ctx 
*pipe_ctx)
 

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm,
 );
 }
-
-/**
- * TODO REMOVE, USE UPDATE INSTEAD
- */
-static void set_plane_config(
-   const struct dc *dc,
-   struct pipe_ctx *pipe_ctx,
-   struct resource_context *res_ctx)
-{
-   struct mem_input *mi = pipe_ctx->plane_res.mi;
-   struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-   struct xfm_grph_csc_adjustment adjust;
-   struct out_csc_color_matrix tbl_entry;
-   unsigned int i;
-
-   memset(, 0, sizeof(adjust));
-   memset(_entry, 0, sizeof(tbl_entry));
-   adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
-
-   dce_enable_fe_clock(dc->hwseq, mi->inst, true);
-
-   set_default_colors(pipe_ctx);
-   if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
-   tbl_entry.color_space =
-   pipe_ctx->stream->output_color_space;
-
-   for (i = 0; i < 12; i++)
-   tbl_entry.regval[i] =
-   pipe_ctx->stream->csc_color_matrix.matrix[i];
-
-   pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
-   (pipe_ctx->plane_res.xfm, _entry);
-   }
-
-   if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
-   adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
-
-   for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
-   adjust.temperature_matrix[i] =
-   pipe_ctx->stream->gamut_remap_matrix.matrix[i];
-   }
-
-   
pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm,
 );
-
-   pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe 
!= 0;
-   program_scaler(dc, pipe_ctx);
-
-   program_surface_visibility(dc, pipe_ctx);
-
-   mi->funcs->mem_input_program_surface_config(
-   mi,
-   plane_state->format,
-   _state->tiling_info,
-   _state->plane_size,
-   plane_state->rotation,
-   NULL,
-   false);
-   if (mi->funcs->set_blank)
-   mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
-
-   if (dc->config.gpu_vm_support)
-   mi->funcs->mem_input_program_pte_vm(
-   pipe_ctx->plane_res.mi,
-   plane_state->format,
-   _state->tiling_info,
-   plane_state->rotation);
-}
-
 static void update_plane_addr(const struct dc *dc,
struct pipe_ctx *pipe_ctx)
 {
@@ -3041,7 +2973,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.init_hw = init_hw,
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = dce110_apply_ctx_for_surface,
-   .set_plane_config = set_plane_config,
.update_plane_addr = update_plane_addr,
.update_pending_status = dce110_update_pending_status,
.set_input_transfer_func = dce110_set_input_transfer_func,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index fe52cbc8990f..b88e020eb58c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2510,15 +2510,6 @@ static void set_static_screen_control(struct pipe_ctx 
**pipe_ctx,
set_static_screen_control(pipe_ctx[i]->stream_res.tg, 
value);
 }
 
-static void set_plane_config(
-   const struct dc *dc,
-   struct pipe_ctx *pipe_ctx,
-   struct resource_context *res_ctx)
-{
-   /* TODO */
-   program_gamut_remap(pipe_ctx);
-}
-
 static void dcn10_config_stereo_parameters(
struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
 {
@@ -2696,7 +2687,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.init_hw = dcn10_init_hw,
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,

[PATCH 06/25] drm/amd/display: truncate scaling ratios and inits to 19 bit precision

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 25 +--
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 80aa8a63338f..e2ad6ed0bf42 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -656,6 +656,14 @@ static void calculate_scaling_ratios(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
}
+   pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
+   pipe_ctx->plane_res.scl_data.ratios.horz, 19);
+   pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
+   pipe_ctx->plane_res.scl_data.ratios.vert, 19);
+   pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
+   pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
+   pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
+   pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
 }
 
 static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view 
*recout_skip)
@@ -692,17 +700,18 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx 
*pipe_ctx, struct view *r
 *  init_bot = init + scaling_ratio
 *  init_c = init + truncated_vp_c_offset(from calculate viewport)
 */
-   data->inits.h = dc_fixpt_div_int(
-   dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 
1), 2);
+   data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
+   dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 
1), 2), 19);
 
-   data->inits.h_c = dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
-   dc_fixpt_add_int(data->ratios.horz_c, 
data->taps.h_taps_c + 1), 2));
+   data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, 
dc_fixpt_div_int(
+   dc_fixpt_add_int(data->ratios.horz_c, 
data->taps.h_taps_c + 1), 2)), 19);
 
-   data->inits.v = dc_fixpt_div_int(
-   dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 
1), 2);
+   data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
+   dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 
1), 2), 19);
+
+   data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, 
dc_fixpt_div_int(
+   dc_fixpt_add_int(data->ratios.vert_c, 
data->taps.v_taps_c + 1), 2)), 19);
 
-   data->inits.v_c = dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
-   dc_fixpt_add_int(data->ratios.vert_c, 
data->taps.v_taps_c + 1), 2));
 
 
/* Adjust for viewport end clip-off */
-- 
2.17.0

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[PATCH 03/25] drm/amd/display: inline more of fixed point code

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/basics/fixpt31_32.c| 156 ++---
 .../gpu/drm/amd/display/include/fixed31_32.h  | 207 ++
 .../amd/display/modules/color/color_gamma.c   |   8 +-
 3 files changed, 135 insertions(+), 236 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c 
b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index e398ecdf742c..e61dd97d0928 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -64,9 +64,7 @@ static inline unsigned long long 
complete_integer_division_u64(
 #define GET_FRACTIONAL_PART(x) \
(FRACTIONAL_PART_MASK & (x))
 
-struct fixed31_32 dc_fixpt_from_fraction(
-   long long numerator,
-   long long denominator)
+struct fixed31_32 dc_fixpt_from_fraction(long long numerator, long long 
denominator)
 {
struct fixed31_32 res;
 
@@ -118,63 +116,7 @@ struct fixed31_32 dc_fixpt_from_fraction(
return res;
 }
 
-struct fixed31_32 dc_fixpt_from_int_nonconst(
-   long long arg)
-{
-   struct fixed31_32 res;
-
-   ASSERT((LONG_MIN <= arg) && (arg <= LONG_MAX));
-
-   res.value = arg << FIXED31_32_BITS_PER_FRACTIONAL_PART;
-
-   return res;
-}
-
-struct fixed31_32 dc_fixpt_shl(
-   struct fixed31_32 arg,
-   unsigned char shift)
-{
-   struct fixed31_32 res;
-
-   ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
-   ((arg.value < 0) && (arg.value >= LLONG_MIN >> shift)));
-
-   res.value = arg.value << shift;
-
-   return res;
-}
-
-struct fixed31_32 dc_fixpt_add(
-   struct fixed31_32 arg1,
-   struct fixed31_32 arg2)
-{
-   struct fixed31_32 res;
-
-   ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) ||
-   ((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value)));
-
-   res.value = arg1.value + arg2.value;
-
-   return res;
-}
-
-struct fixed31_32 dc_fixpt_sub(
-   struct fixed31_32 arg1,
-   struct fixed31_32 arg2)
-{
-   struct fixed31_32 res;
-
-   ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) ||
-   ((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value)));
-
-   res.value = arg1.value - arg2.value;
-
-   return res;
-}
-
-struct fixed31_32 dc_fixpt_mul(
-   struct fixed31_32 arg1,
-   struct fixed31_32 arg2)
+struct fixed31_32 dc_fixpt_mul(struct fixed31_32 arg1, struct fixed31_32 arg2)
 {
struct fixed31_32 res;
 
@@ -225,8 +167,7 @@ struct fixed31_32 dc_fixpt_mul(
return res;
 }
 
-struct fixed31_32 dc_fixpt_sqr(
-   struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_sqr(struct fixed31_32 arg)
 {
struct fixed31_32 res;
 
@@ -266,8 +207,7 @@ struct fixed31_32 dc_fixpt_sqr(
return res;
 }
 
-struct fixed31_32 dc_fixpt_recip(
-   struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_recip(struct fixed31_32 arg)
 {
/*
 * @note
@@ -281,8 +221,7 @@ struct fixed31_32 dc_fixpt_recip(
arg.value);
 }
 
-struct fixed31_32 dc_fixpt_sinc(
-   struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_sinc(struct fixed31_32 arg)
 {
struct fixed31_32 square;
 
@@ -326,16 +265,14 @@ struct fixed31_32 dc_fixpt_sinc(
return res;
 }
 
-struct fixed31_32 dc_fixpt_sin(
-   struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_sin(struct fixed31_32 arg)
 {
return dc_fixpt_mul(
arg,
dc_fixpt_sinc(arg));
 }
 
-struct fixed31_32 dc_fixpt_cos(
-   struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_cos(struct fixed31_32 arg)
 {
/* TODO implement argument normalization */
 
@@ -367,8 +304,7 @@ struct fixed31_32 dc_fixpt_cos(
  *
  * Calculated as Taylor series.
  */
-static struct fixed31_32 fixed31_32_exp_from_taylor_series(
-   struct fixed31_32 arg)
+static struct fixed31_32 fixed31_32_exp_from_taylor_series(struct fixed31_32 
arg)
 {
unsigned int n = 9;
 
@@ -396,8 +332,7 @@ static struct fixed31_32 fixed31_32_exp_from_taylor_series(
res));
 }
 
-struct fixed31_32 dc_fixpt_exp(
-   struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_exp(struct fixed31_32 arg)
 {
/*
 * @brief
@@ -440,8 +375,7 @@ struct fixed31_32 dc_fixpt_exp(
return dc_fixpt_one;
 }
 
-struct fixed31_32 dc_fixpt_log(
-   struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_log(struct fixed31_32 arg)
 {
struct fixed31_32 res = dc_fixpt_neg(dc_fixpt_one);
/* TODO improve 1st estimation */
@@ -472,61 +406,6 @@ struct fixed31_32 dc_fixpt_log(
return res;
 }
 
-struct fixed31_32 dc_fixpt_pow(
-   struct fixed31_32 arg1,
-   struct fixed31_32 arg2)

[PATCH 00/25] DC Patches May 8, 2018

[Harry Wentland]

 * Fix poison EDID read when hotplugging display (Mikita)
 * Clean up fixed point code

Anthony Koo (7):
  drm/amd/display: Cleanup unused SetPlaneConfig
  drm/amd/display: Make DisplayStats work with just DC DisplayStats
minor
  drm/amd/display: Fix up dm logging functionality
  drm/amd/display: use macro for logs
  drm/amd/display: Add fullscreen transitions to log
  drm/amd/display: fix bug with index check
  drm/amd/display: fix memory leaks

Charlene Liu (1):
  drm/amd/display: underflow/blankscreen recovery

Dmytro Laktyushkin (7):
  drm/amd/display: get rid of 32.32 unsigned fixed point
  drm/amd/display: inline more of fixed point code
  drm/amd/display: add fixed point fractional bit truncation function
  drm/amd/display: truncate scaling ratios and inits to 19 bit precision
  drm/amd/display: fix 31_32_fixpt shift functions
  drm/amd/display: fix a 32 bit shift meant to be 64 warning
  drm/amd/display: update dml to allow sync with DV

Eric Bernstein (2):
  drm/amd/display: Update HW sequencer initialization
  drm/amd/display: DCN1 link encoder

Jun Lei (1):
  drm/amd/display: constify a few dc_surface_update fields

Mikita Lipski (1):
  drm/amd/display: Clear connector's edid pointer

Nikola Cornij (2):
  drm/amd/display: Log DTN only after the atomic commit in Diag
  drm/amd/display: Clear underflow status for debug purposes

Samson Tam (1):
  drm/amd/display: don't create new dc_sink if nothing changed at
detection

Xingyue Tao (2):
  drm/amd/display: Add dc cap to restrict VSR downscaling src size
  drm/amd/display: Only limit VSR downscaling when actually downscaling

Yue Hin Lau (1):
  drm/amd/display: disable mpo if brightness adjusted

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   |   14 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |5 -
 .../gpu/drm/amd/display/dc/basics/Makefile|2 +-
 .../drm/amd/display/dc/basics/conversion.c|   28 +-
 .../drm/amd/display/dc/basics/fixpt31_32.c|  276 +---
 .../drm/amd/display/dc/basics/fixpt32_32.c|  161 --
 .../drm/amd/display/dc/basics/log_helpers.c   |1 -
 .../gpu/drm/amd/display/dc/basics/logger.c|3 +-
 .../drm/amd/display/dc/calcs/custom_float.c   |   46 +-
 .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  |8 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  107 +-
 .../drm/amd/display/dc/core/dc_link_hwss.c|2 -
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   77 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |   18 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |2 +
 drivers/gpu/drm/amd/display/dc/dc_types.h |2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  |2 +-
 .../drm/amd/display/dc/dce/dce_clock_source.c |   60 +-
 .../gpu/drm/amd/display/dc/dce/dce_clocks.c   |   26 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c |2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c  |6 +-
 .../drm/amd/display/dc/dce/dce_scl_filters.c  |   48 +-
 .../amd/display/dc/dce/dce_stream_encoder.c   |8 +-
 .../drm/amd/display/dc/dce/dce_transform.c|   26 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  105 +-
 .../display/dc/dce110/dce110_transform_v.c|8 +-
 drivers/gpu/drm/amd/display/dc/dcn10/Makefile |2 +-
 .../amd/display/dc/dcn10/dcn10_cm_common.c|   86 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  |7 +-
 .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c   |6 +-
 .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c |   38 +-
 .../drm/amd/display/dc/dcn10/dcn10_hubbub.c   |8 +
 .../drm/amd/display/dc/dcn10/dcn10_hubbub.h   |7 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   28 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |3 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  259 +++-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |2 +
 .../amd/display/dc/dcn10/dcn10_link_encoder.c | 1362 +
 .../amd/display/dc/dcn10/dcn10_link_encoder.h |  330 
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |   10 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   10 +
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |   46 +-
 .../display/dc/dcn10/dcn10_stream_encoder.c   |8 +-
 drivers/gpu/drm/amd/display/dc/dm_services.h  |4 -
 .../amd/display/dc/dml/display_mode_enums.h   |   13 +
 .../amd/display/dc/dml/display_mode_structs.h |  962 ++--
 .../drm/amd/display/dc/dml/dml_inline_defs.h  |   10 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |2 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |5 -
 drivers/gpu/drm/amd/display/dc/irq_types.h|2 +
 .../gpu/drm/amd/display/include/fixed31_32.h  |  268 ++--
 .../gpu/drm/amd/display/include/fixed32_32.h  |  129 --
 .../amd/display/include/logger_interface.h|9 +
 .../drm/amd/display/include/logger_types.h|2 +-
 .../amd/display/modules/color/color_gamma.c   |  446 +++---
 .../drm/amd/display/modules/inc/mod_stats.h   |4 +
 

[PATCH 04/25] drm/amd/display: Make DisplayStats work with just DC DisplayStats minor

[Harry Wentland]

From: Anthony Koo 

Remove dependency on the old FREESYNC_SW_STATS log mask used by DAL2
Also rename from profiling to displaystats

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/basics/logger.c|  2 +-
 .../drm/amd/display/include/logger_types.h|  2 +-
 .../gpu/drm/amd/display/modules/stats/stats.c | 81 ++-
 3 files changed, 46 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c 
b/drivers/gpu/drm/amd/display/dc/basics/logger.c
index 31bee054f43a..0001a3c5b862 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
@@ -61,7 +61,7 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
{LOG_EVENT_UNDERFLOW,   "Underflow"},
{LOG_IF_TRACE,  "InterfaceTrace"},
{LOG_DTN,   "DTN"},
-   {LOG_PROFILING, "Profiling"}
+   {LOG_DISPLAYSTATS,  "DisplayStats"}
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h 
b/drivers/gpu/drm/amd/display/include/logger_types.h
index b608a0830801..0a540b9897a6 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -98,7 +98,7 @@ enum dc_log_type {
LOG_EVENT_UNDERFLOW,
LOG_IF_TRACE,
LOG_PERF_TRACE,
-   LOG_PROFILING,
+   LOG_DISPLAYSTATS,
 
LOG_SECTION_TOTAL_COUNT
 };
diff --git a/drivers/gpu/drm/amd/display/modules/stats/stats.c 
b/drivers/gpu/drm/amd/display/modules/stats/stats.c
index 48e02197919f..d16aac7b30b3 100644
--- a/drivers/gpu/drm/amd/display/modules/stats/stats.c
+++ b/drivers/gpu/drm/amd/display/modules/stats/stats.c
@@ -177,44 +177,51 @@ void mod_stats_dump(struct mod_stats *mod_stats)
logger = dc->ctx->logger;
time = core_stats->time;
 
-   //LogEntry* pLog = GetLog()->Open(LogMajor_ISR, 
LogMinor_ISR_FreeSyncSW);
-
-   //if (!pLog->IsDummyEntry())
-   {
-   dm_logger_write(logger, LOG_PROFILING, "==Display Caps==\n");
-   dm_logger_write(logger, LOG_PROFILING, "\n");
-   dm_logger_write(logger, LOG_PROFILING, "\n");
-
-   dm_logger_write(logger, LOG_PROFILING, "==Stats==\n");
-   dm_logger_write(logger, LOG_PROFILING,
-   "render avgRender minWindow midPoint maxWindow 
vsyncToFlip flipToVsync #vsyncBetweenFlip #frame insertDuration vTotalMin 
vTotalMax eventTrigs vSyncTime1 vSyncTime2 vSyncTime3 vSyncTime4 vSyncTime5 
flags\n");
-
-   for (int i = 0; i < core_stats->index && i < 
core_stats->entries; i++) {
-   dm_logger_write(logger, LOG_PROFILING,
-   "%u  %u  %u  %u  %u  %u  %u  %u  %u  %u 
 %u  %u  %u  %u  %u  %u  %u  %u  %u",
-   time[i].render_time_in_us,
-   time[i].avg_render_time_in_us_last_ten,
-   time[i].min_window,
-   time[i].lfc_mid_point_in_us,
-   time[i].max_window,
-   time[i].vsync_to_flip_time_in_us,
-   time[i].flip_to_vsync_time_in_us,
-   time[i].num_vsync_between_flips,
-   time[i].num_frames_inserted,
-   time[i].inserted_duration_in_us,
-   time[i].v_total_min,
-   time[i].v_total_max,
-   time[i].event_triggers,
-   time[i].v_sync_time_in_us[0],
-   time[i].v_sync_time_in_us[1],
-   time[i].v_sync_time_in_us[2],
-   time[i].v_sync_time_in_us[3],
-   time[i].v_sync_time_in_us[4],
-   time[i].flags);
-   }
+   dm_logger_write(logger, LOG_DISPLAYSTATS, "==Display Caps==");
+   dm_logger_write(logger, LOG_DISPLAYSTATS, " ");
+
+   dm_logger_write(logger, LOG_DISPLAYSTATS, "==Display Stats==");
+   dm_logger_write(logger, LOG_DISPLAYSTATS, " ");
+
+   dm_logger_write(logger, LOG_DISPLAYSTATS,
+   "%10s %10s %10s %10s %10s"
+   " %11s %11s %17s %10s %14s"
+   " %10s %10s %10s %10s %10s"
+   " %10s %10s %10s %10s",
+   "render", "avgRender",
+   "minWindow", "midPoint", "maxWindow",
+   "vsyncToFlip", "flipToVsync", "vsyncsBetweenFlip",
+ 

[BUG] amdgpu: System freezes after resuming from suspend to ram the second time

[John Smith]

The amdgpu driver freezes the kernel, when suspending for the second time. When 
blacklisting amdgpu the suspend/resume works correctly.
Please see the attached logs.

Hardware: hp-zbook 15u 5g i7-8550

$ uname -a
Linux MYPCNAME 4.17.0-rc3-ARCH+ #1 SMP PREEMPT Sun May 6 09:50:29 CEST 2018 
x86_64 GNU/Linux

$ lspci -v
00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 620 (rev 07) 
(prog-if 00 [VGA controller])
Subsystem: Hewlett-Packard Company UHD Graphics 620
Flags: bus master, fast devsel, latency 0, IRQ 137
Memory at 1ff200 (64-bit, non-prefetchable) [size=16M]
Memory at b000 (64-bit, prefetchable) [size=256M]
I/O ports at 4000 [size=64]
[virtual] Expansion ROM at 000c [disabled] [size=128K]
Capabilities: 
Kernel driver in use: i915
Kernel modules: i915

$ dmesg | grep amdgpu
[2.032619] [drm] amdgpu kernel modesetting enabled.
[2.047191] amdgpu :01:00.0: enabling device (0006 -> 0007)
[2.078141] amdgpu :01:00.0: BAR 2: releasing [mem 0xd000-0xd01f 
64bit pref]
[2.078142] amdgpu :01:00.0: BAR 0: releasing [mem 0xc000-0xcfff 
64bit pref]
[2.078152] amdgpu :01:00.0: BAR 0: assigned [mem 0xc000-0xcfff 
64bit pref]
[2.078161] amdgpu :01:00.0: BAR 2: assigned [mem 0xd000-0xd01f 
64bit pref]
[2.078181] amdgpu :01:00.0: VRAM: 2048M 0x00F4 - 
0x00F47FFF (2048M used)
[2.078182] amdgpu :01:00.0: GTT: 256M 0x - 
0x0FFF
[2.078294] [drm] amdgpu: 2048M of VRAM memory ready
[2.078295] [drm] amdgpu: 3072M of GTT memory ready.
[2.142916] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[2.142923] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[2.142926] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched
[2.142934] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched
[2.142935] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[2.142935] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[2.142936] amdgpu: [powerplay] Voltage value looks like a Leakage ID but 
it's not patched 
[2.157406] [drm:dc_create [amdgpu]] *ERROR* DC: Number of connectors is 
zero!
[2.325272] [drm] Initialized amdgpu 3.25.0 20150101 for :01:00.0 on 
minor 0
[9.666277] amdgpu :01:00.0: GPU pci config reset
[   18.670067] amdgpu :01:00.0: GPU pci config reset
[   69.598425] amdgpu :01:00.0: GPU pci config reset
[   79.670532] amdgpu :01:00.0: GPU pci config reset


$ dmesg 
[0.00] Linux version 4.17.0-rc3-ARCH+ (USER@MYPCNAME) (gcc version 
7.3.1 20180406 (GCC)) #1 SMP PREEMPT Sun May 6 09:50:29 CEST 2018
[0.00] Command line: BOOT_IMAGE=/vmlinuz-linux-custom 
root=UUID=1e8ed61d-f399-465f-b0f3-0216a6bf3adc rw 
resume=UUID=3811a093-acc8-4399-aa1e-d2628543f87d
[0.00] KERNEL supported cpus:
[0.00]   Intel GenuineIntel
[0.00]   AMD AuthenticAMD
[0.00]   Centaur CentaurHauls
[0.00] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point 
registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
[0.00] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
[0.00] x86/fpu: xstate_offset[3]:  832, xstate_sizes[3]:   64
[0.00] x86/fpu: xstate_offset[4]:  896, xstate_sizes[4]:   64
[0.00] x86/fpu: Enabled xstate features 0x1f, context size is 960 
bytes, using 'compacted' format.
[0.00] e820: BIOS-provided physical RAM map:
[0.00] BIOS-e820: [mem 0x-0x00057fff] usable
[0.00] BIOS-e820: [mem 0x00058000-0x00058fff] reserved
[0.00] BIOS-e820: [mem 0x00059000-0x0009dfff] usable
[0.00] BIOS-e820: [mem 0x0009e000-0x0009efff] reserved
[0.00] BIOS-e820: [mem 0x0009f000-0x0009] usable
[0.00] BIOS-e820: [mem 0x000a-0x000f] reserved
[0.00] BIOS-e820: [mem 0x0010-0x879d9fff] usable
[0.00] BIOS-e820: [mem 0x879da000-0x879dafff] reserved
[0.00] BIOS-e820: [mem 0x879db000-0x87cf7fff] usable
[0.00] BIOS-e820: [mem 0x87cf8000-0x87cf8fff] reserved
[0.00] BIOS-e820: [mem 0x87cf9000-0x9606afff] usable
[0.00] BIOS-e820: [mem 0x9606b000-0x9606bfff] ACPI NVS
[0.00] BIOS-e820: [mem 0x9606c000-0x9606cfff] reserved
[0.00] 

Re: [PATCH] drm/amdgpu: add HDP flush dummy for UVD 6/7

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Christian 
König 
Sent: Tuesday, May 8, 2018 6:30:06 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: add HDP flush dummy for UVD 6/7

The UVD firmware doesn't seem to like the HDP flush here.

This worked for years without HDP flush, so just skip it.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 16 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 -
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 6d3359889c0b..8041b26a7a21 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -963,6 +963,16 @@ static void uvd_v6_0_enc_ring_emit_fence(struct 
amdgpu_ring *ring, u64 addr,
 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }

+/**
+ * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+   /* The firmware doesn't seem to like touching registers at this point. 
*/
+}
+
 /**
  * uvd_v6_0_ring_test_ring - register write test
  *
@@ -1528,12 +1538,13 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_phys_funcs = {
 .set_wptr = uvd_v6_0_ring_set_wptr,
 .parse_cs = amdgpu_uvd_ring_parse_cs,
 .emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
 .emit_ib = uvd_v6_0_ring_emit_ib,
 .emit_fence = uvd_v6_0_ring_emit_fence,
+   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
 .test_ring = uvd_v6_0_ring_test_ring,
 .test_ib = amdgpu_uvd_ring_test_ib,
 .insert_nop = amdgpu_ring_insert_nop,
@@ -1552,7 +1563,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_vm_funcs = {
 .get_wptr = uvd_v6_0_ring_get_wptr,
 .set_wptr = uvd_v6_0_ring_set_wptr,
 .emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* 
uvd_v6_0_ring_emit_vm_flush */
 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
@@ -1561,6 +1572,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_vm_funcs = {
 .emit_fence = uvd_v6_0_ring_emit_fence,
 .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
 .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
+   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
 .test_ring = uvd_v6_0_ring_test_ring,
 .test_ib = amdgpu_uvd_ring_test_ib,
 .insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 2251db4048f5..b0de1e04093b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1135,6 +1135,16 @@ static void uvd_v7_0_enc_ring_emit_fence(struct 
amdgpu_ring *ring, u64 addr,
 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }

+/**
+ * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+   /* The firmware doesn't seem to like touching registers at this point. 
*/
+}
+
 /**
  * uvd_v7_0_ring_test_ring - register write test
  *
@@ -1654,7 +1664,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_ring_vm_funcs = {
 .get_wptr = uvd_v7_0_ring_get_wptr,
 .set_wptr = uvd_v7_0_ring_set_wptr,
 .emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 8 + /* uvd_v7_0_ring_emit_vm_flush */
@@ -1663,6 +1673,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_ring_vm_funcs = {
 .emit_ib = uvd_v7_0_ring_emit_ib,
 .emit_fence = uvd_v7_0_ring_emit_fence,
 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
+   .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
 .test_ring = uvd_v7_0_ring_test_ring,
 .test_ib = amdgpu_uvd_ring_test_ib,
 .insert_nop = uvd_v7_0_ring_insert_nop,
--
2.14.1

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Re: [PATCH v2] drm/amdgpu: Don't default to DC support for Kaveri and older

[Harry Wentland]

On 2018-05-08 11:28 AM, Deucher, Alexander wrote:
> You need to include mullins as well.  It's the same feature set as kabini.
> 

Good catch. v3 incoming.

> 
> Alex
> 
> 
> 
> --
> *From:* amd-gfx  on behalf of Harry 
> Wentland 
> *Sent:* Monday, May 7, 2018 7:24 PM
> *To:* amd-gfx@lists.freedesktop.org; Deucher, Alexander
> *Cc:* Wentland, Harry
> *Subject:* [PATCH v2] drm/amdgpu: Don't default to DC support for Kaveri and 
> older
>  
> We've had a number of users report failures to detect and light up
> display with DC with LVDS and VGA. These connector types are not
> currently supported with DC. I'd like to add support but unfortunately
> don't have a system with LVDS or VGA available.
> 
> In order not to cause regressions we should probably fallback to the
> non-DC driver for ASICs that support VGA and LVDS.
> 
> These ASICs are:
>  * Bonaire
>  * Kabini
>  * Kaveri
> 
> ASIC support can always be force enabled with amdgpu.dc=1
> 
> v2: Keep Hawaii on DC
> 
> Signed-off-by: Harry Wentland 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 887f7c9e84e0..0a23134147b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2141,9 +2141,17 @@ bool amdgpu_device_asic_has_dc_support(enum 
> amd_asic_type asic_type)
>  switch (asic_type) {
>  #if defined(CONFIG_DRM_AMD_DC)
>  case CHIP_BONAIRE:
> -   case CHIP_HAWAII:
>  case CHIP_KAVERI:
>  case CHIP_KABINI:
> +   /*
> +    * We have systems in the wild with these ASICs that require
> +    * LVDS and VGA support which is not supported with DC.
> +    *
> +    * Fallback to the non-DC driver here by default so as not to
> +    * cause regressions.
> +    */
> +   return amdgpu_dc > 0;
> +   case CHIP_HAWAII:
>  case CHIP_MULLINS:
>  case CHIP_CARRIZO:
>  case CHIP_STONEY:
> -- 
> 2.17.0
> 
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[PATCH v3] drm/amdgpu: Don't default to DC support for Kaveri and older

[Harry Wentland]

We've had a number of users report failures to detect and light up
display with DC with LVDS and VGA. These connector types are not
currently supported with DC. I'd like to add support but unfortunately
don't have a system with LVDS or VGA available.

In order not to cause regressions we should probably fallback to the
non-DC driver for ASICs that support VGA and LVDS.

These ASICs are:
 * Bonaire
 * Kabini
 * Kaveri
 * Mullins

ASIC support can always be force enabled with amdgpu.dc=1

v2: Keep Hawaii on DC
v3: Added Mullins to the list

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 887f7c9e84e0..f3ed4950d129 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2141,10 +2141,18 @@ bool amdgpu_device_asic_has_dc_support(enum 
amd_asic_type asic_type)
switch (asic_type) {
 #if defined(CONFIG_DRM_AMD_DC)
case CHIP_BONAIRE:
-   case CHIP_HAWAII:
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_MULLINS:
+   /*
+* We have systems in the wild with these ASICs that require
+* LVDS and VGA support which is not supported with DC.
+*
+* Fallback to the non-DC driver here by default so as not to
+* cause regressions.
+*/
+   return amdgpu_dc > 0;
+   case CHIP_HAWAII:
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_POLARIS10:
-- 
2.17.0

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Re: [PATCH v2] drm/amdgpu: Don't default to DC support for Kaveri and older

[Deucher, Alexander]

You need to include mullins as well.  It's the same feature set as kabini.


Alex



From: amd-gfx  on behalf of Harry 
Wentland 
Sent: Monday, May 7, 2018 7:24 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
Cc: Wentland, Harry
Subject: [PATCH v2] drm/amdgpu: Don't default to DC support for Kaveri and older

We've had a number of users report failures to detect and light up
display with DC with LVDS and VGA. These connector types are not
currently supported with DC. I'd like to add support but unfortunately
don't have a system with LVDS or VGA available.

In order not to cause regressions we should probably fallback to the
non-DC driver for ASICs that support VGA and LVDS.

These ASICs are:
 * Bonaire
 * Kabini
 * Kaveri

ASIC support can always be force enabled with amdgpu.dc=1

v2: Keep Hawaii on DC

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 887f7c9e84e0..0a23134147b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2141,9 +2141,17 @@ bool amdgpu_device_asic_has_dc_support(enum 
amd_asic_type asic_type)
 switch (asic_type) {
 #if defined(CONFIG_DRM_AMD_DC)
 case CHIP_BONAIRE:
-   case CHIP_HAWAII:
 case CHIP_KAVERI:
 case CHIP_KABINI:
+   /*
+* We have systems in the wild with these ASICs that require
+* LVDS and VGA support which is not supported with DC.
+*
+* Fallback to the non-DC driver here by default so as not to
+* cause regressions.
+*/
+   return amdgpu_dc > 0;
+   case CHIP_HAWAII:
 case CHIP_MULLINS:
 case CHIP_CARRIZO:
 case CHIP_STONEY:
--
2.17.0

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[PATCH] drm/amdgpu: add HDP flush dummy for UVD 6/7

[Christian König]

The UVD firmware doesn't seem to like the HDP flush here.

This worked for years without HDP flush, so just skip it.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 16 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 -
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 6d3359889c0b..8041b26a7a21 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -963,6 +963,16 @@ static void uvd_v6_0_enc_ring_emit_fence(struct 
amdgpu_ring *ring, u64 addr,
amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }
 
+/**
+ * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+   /* The firmware doesn't seem to like touching registers at this point. 
*/
+}
+
 /**
  * uvd_v6_0_ring_test_ring - register write test
  *
@@ -1528,12 +1538,13 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_phys_funcs = {
.set_wptr = uvd_v6_0_ring_set_wptr,
.parse_cs = amdgpu_uvd_ring_parse_cs,
.emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
10 + /* uvd_v6_0_ring_emit_pipeline_sync */
14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
.emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
.emit_ib = uvd_v6_0_ring_emit_ib,
.emit_fence = uvd_v6_0_ring_emit_fence,
+   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
.test_ring = uvd_v6_0_ring_test_ring,
.test_ib = amdgpu_uvd_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
@@ -1552,7 +1563,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_vm_funcs = {
.get_wptr = uvd_v6_0_ring_get_wptr,
.set_wptr = uvd_v6_0_ring_set_wptr,
.emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
10 + /* uvd_v6_0_ring_emit_pipeline_sync */
VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* 
uvd_v6_0_ring_emit_vm_flush */
14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
@@ -1561,6 +1572,7 @@ static const struct amdgpu_ring_funcs 
uvd_v6_0_ring_vm_funcs = {
.emit_fence = uvd_v6_0_ring_emit_fence,
.emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
.emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
+   .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
.test_ring = uvd_v6_0_ring_test_ring,
.test_ib = amdgpu_uvd_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 2251db4048f5..b0de1e04093b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1135,6 +1135,16 @@ static void uvd_v7_0_enc_ring_emit_fence(struct 
amdgpu_ring *ring, u64 addr,
amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }
 
+/**
+ * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
+ *
+ * @ring: amdgpu_ring pointer
+ */
+static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+   /* The firmware doesn't seem to like touching registers at this point. 
*/
+}
+
 /**
  * uvd_v7_0_ring_test_ring - register write test
  *
@@ -1654,7 +1664,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_ring_vm_funcs = {
.get_wptr = uvd_v7_0_ring_get_wptr,
.set_wptr = uvd_v7_0_ring_set_wptr,
.emit_frame_size =
-   6 + 6 + /* hdp flush / invalidate */
+   6 + /* hdp invalidate */
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
8 + /* uvd_v7_0_ring_emit_vm_flush */
@@ -1663,6 +1673,7 @@ static const struct amdgpu_ring_funcs 
uvd_v7_0_ring_vm_funcs = {
.emit_ib = uvd_v7_0_ring_emit_ib,
.emit_fence = uvd_v7_0_ring_emit_fence,
.emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
+   .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
.test_ring = uvd_v7_0_ring_test_ring,
.test_ib = amdgpu_uvd_ring_test_ib,
.insert_nop = uvd_v7_0_ring_insert_nop,
-- 
2.14.1

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答复: [PATCH] drm/amd/pp: Implement force_clock_level for RV

[Quan, Evan]

Reviewed-by: Evan Quan 


发件人: amd-gfx  代表 Rex Zhu 

发送时间: 2018年5月8日 14:23:35
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhu, Rex
主题: [PATCH] drm/amd/pp: Implement force_clock_level for RV

under manual dpm mode, user can set gfx/mem clock
through sysfs pp_dpm_sclk/mclk on Rv.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 47 ++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 68e78256..2152cf4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -404,7 +404,7 @@ static int smu10_populate_clock_table(struct pp_hwmgr 
*hwmgr)
 "Attempt to copy clock table from smc failed",
 return result);

-   if (0 == result && table->DcefClocks[0].Freq != 0) {
+   if (table->DcefClocks[0].Freq != 0) {
 smu10_get_clock_voltage_dependency_table(hwmgr, 
>vdd_dep_on_dcefclk,
 NUM_DCEFCLK_DPM_LEVELS,
 
_data->clock_table.DcefClocks[0]);
@@ -775,6 +775,51 @@ static int smu10_get_dal_power_level(struct pp_hwmgr 
*hwmgr,
 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
 enum pp_clock_type type, uint32_t mask)
 {
+   struct smu10_hwmgr *data = hwmgr->backend;
+   struct smu10_voltage_dependency_table *mclk_table =
+   data->clock_vol_info.vdd_dep_on_fclk;
+   uint32_t low, high;
+
+   low = mask ? (ffs(mask) - 1) : 0;
+   high = mask ? (fls(mask) - 1) : 0;
+
+   switch (type) {
+   case PP_SCLK:
+   if (low > 2 || high > 2) {
+   pr_info("Currently sclk only support 3 levels on RV\n");
+   return -EINVAL;
+   }
+
+   smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_SetHardMinGfxClk,
+   low == 2 ? 
data->gfx_max_freq_limit/100 :
+   low == 1 ? 
SMU10_UMD_PSTATE_GFXCLK :
+   data->gfx_min_freq_limit/100);
+
+   smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_SetSoftMaxGfxClk,
+   high == 0 ? 
data->gfx_min_freq_limit/100 :
+   high == 1 ? 
SMU10_UMD_PSTATE_GFXCLK :
+   data->gfx_max_freq_limit/100);
+   break;
+
+   case PP_MCLK:
+   if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
+   return -EINVAL;
+
+   smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_SetHardMinFclkByFreq,
+   
mclk_table->entries[low].clk/100);
+
+   smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_SetSoftMaxFclkByFreq,
+   
mclk_table->entries[high].clk/100);
+   break;
+
+   case PP_PCIE:
+   default:
+   break;
+   }
 return 0;
 }

--
1.9.1

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[PATCH] drm/amd/pp: Implement force_clock_level for RV

[Rex Zhu]

under manual dpm mode, user can set gfx/mem clock
through sysfs pp_dpm_sclk/mclk on Rv.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 47 ++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 68e78256..2152cf4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -404,7 +404,7 @@ static int smu10_populate_clock_table(struct pp_hwmgr 
*hwmgr)
"Attempt to copy clock table from smc failed",
return result);
 
-   if (0 == result && table->DcefClocks[0].Freq != 0) {
+   if (table->DcefClocks[0].Freq != 0) {
smu10_get_clock_voltage_dependency_table(hwmgr, 
>vdd_dep_on_dcefclk,
NUM_DCEFCLK_DPM_LEVELS,

_data->clock_table.DcefClocks[0]);
@@ -775,6 +775,51 @@ static int smu10_get_dal_power_level(struct pp_hwmgr 
*hwmgr,
 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask)
 {
+   struct smu10_hwmgr *data = hwmgr->backend;
+   struct smu10_voltage_dependency_table *mclk_table =
+   data->clock_vol_info.vdd_dep_on_fclk;
+   uint32_t low, high;
+
+   low = mask ? (ffs(mask) - 1) : 0;
+   high = mask ? (fls(mask) - 1) : 0;
+
+   switch (type) {
+   case PP_SCLK:
+   if (low > 2 || high > 2) {
+   pr_info("Currently sclk only support 3 levels on RV\n");
+   return -EINVAL;
+   }
+
+   smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_SetHardMinGfxClk,
+   low == 2 ? 
data->gfx_max_freq_limit/100 :
+   low == 1 ? 
SMU10_UMD_PSTATE_GFXCLK :
+   data->gfx_min_freq_limit/100);
+
+   smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_SetSoftMaxGfxClk,
+   high == 0 ? 
data->gfx_min_freq_limit/100 :
+   high == 1 ? 
SMU10_UMD_PSTATE_GFXCLK :
+   data->gfx_max_freq_limit/100);
+   break;
+
+   case PP_MCLK:
+   if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
+   return -EINVAL;
+
+   smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_SetHardMinFclkByFreq,
+   
mclk_table->entries[low].clk/100);
+
+   smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_SetSoftMaxFclkByFreq,
+   
mclk_table->entries[high].clk/100);
+   break;
+
+   case PP_PCIE:
+   default:
+   break;
+   }
return 0;
 }
 
-- 
1.9.1

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