Re: [PATCH 2/2] amdgpu: kfd: use modern ktime accessors

[Felix Kuehling]

On 2018-06-18 11:35 AM, Arnd Bergmann wrote:
> getrawmonotonic64() and get_monotonic_boottime64() are deprecated
> because of the nonstandard naming.
>
> The replacement functions ktime_get_raw_ns() and ktime_get_boot_ns()
> also simplify the callers.
>
> Signed-off-by: Arnd Bergmann 

In case this hasn't been submitted yet, this patch is Reviewed-by: Felix
Kuehling .

> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 8 ++--
>  1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> index f64c5551cdba..7e717716b90e 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> @@ -754,7 +754,6 @@ static int kfd_ioctl_get_clock_counters(struct file 
> *filep,
>  {
>   struct kfd_ioctl_get_clock_counters_args *args = data;
>   struct kfd_dev *dev;
> - struct timespec64 time;
>  
>   dev = kfd_device_by_id(args->gpu_id);
>   if (dev)
> @@ -766,11 +765,8 @@ static int kfd_ioctl_get_clock_counters(struct file 
> *filep,
>   args->gpu_clock_counter = 0;
>  
>   /* No access to rdtsc. Using raw monotonic time */
> - getrawmonotonic64();
> - args->cpu_clock_counter = (uint64_t)timespec64_to_ns();
> -
> - get_monotonic_boottime64();
> - args->system_clock_counter = (uint64_t)timespec64_to_ns();
> + args->cpu_clock_counter = ktime_get_raw_ns();
> + args->system_clock_counter = ktime_get_boot_ns();
>  
>   /* Since the counter is in nano-seconds we use 1GHz frequency */
>   args->system_clock_freq = 10;

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Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs (v2)

[Alex Deucher]

On Wed, Jun 20, 2018 at 12:48 PM, Tom St Denis  wrote:
> This adds what should be a stable interface to read GPU
> load from userspace.
>
> (v2): Fix comments and name of file per recommendations.
>
> Signed-off-by: Tom St Denis 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 47 
> ++
>  1 file changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 113edffb5960..49138ac2be24 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -918,6 +918,43 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
> device *dev,
> return -EINVAL;
>  }
>
> +/**
> + * DOC: busy_percent
> + *
> + * The firmware computes a percentage of load based on the activity
> + * level in the IP cores.
> + */

I would reword this a bit.  the tag next to the DOC is only for
reference purposes, it doesn't show up when you reference a DOC
section in the amdgpu.rst file.  In order to make it clear what file
you are referring to, you might want to so something like:

/**
 * DOC: busy_percent
 *
 * The amdgpu driver provides a sysfs API for reading how busy the GPU
is as a percentage.
 * The file gpu_busy_percent is used for this.  The SMU firmware
computes a percentage of
 * load based on the aggregate activity level in the IP cores.
 */

Bonus points if you add the reference to this in the "GPU
Power/Thermal Controls and Monitoring" chapter in amdgpu.rst in
Documentation/gpu/.  But that can be a separate follow on patch.

With the fix above, patch is:
Reviewed-by: Alex Deucher 


> +static ssize_t amdgpu_get_busy_percent(struct device *dev,
> +   struct device_attribute *attr,
> +   char *buf)
> +{
> +   struct drm_device *ddev = dev_get_drvdata(dev);
> +   struct amdgpu_device *adev = ddev->dev_private;
> +   int r, value, size = sizeof(value);
> +
> +   /* sanity check PP is enabled */
> +   if (!(adev->powerplay.pp_funcs &&
> + adev->powerplay.pp_funcs->read_sensor))
> +   return -EINVAL;
> +
> +   /* read the IP busy sensor */
> +   r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
> +  (void *), );
> +   if (r)
> +   return r;
> +
> +   return snprintf(buf, PAGE_SIZE, "%d\n", value);
> +}
> +
> +static ssize_t amdgpu_set_busy_percent(struct device *dev,
> +   struct device_attribute *attr,
> +   const char *buf,
> +   size_t count)
> +{
> +   return -EINVAL;
> +}
> +
> +
>  static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, 
> amdgpu_set_dpm_state);
>  static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
>amdgpu_get_dpm_forced_performance_level,
> @@ -951,6 +988,8 @@ static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | 
> S_IWUSR,
>  static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
> amdgpu_get_pp_od_clk_voltage,
> amdgpu_set_pp_od_clk_voltage);
> +static DEVICE_ATTR(gpu_busy_percent, S_IRUGO | S_IWUSR,
> +   amdgpu_get_busy_percent, amdgpu_set_busy_percent);
>
>  static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
>   struct device_attribute *attr,
> @@ -1854,6 +1893,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
> "pp_od_clk_voltage\n");
> return ret;
> }
> +   ret = device_create_file(adev->dev,
> +   _attr_gpu_busy_percent);
> +   if (ret) {
> +   DRM_ERROR("failed to create device file "
> +   "gpu_busy_level\n");
> +   return ret;
> +   }
> ret = amdgpu_debugfs_pm_init(adev);
> if (ret) {
> DRM_ERROR("Failed to register debugfs file for dpm!\n");
> @@ -1889,6 +1935,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
> _attr_pp_power_profile_mode);
> device_remove_file(adev->dev,
> _attr_pp_od_clk_voltage);
> +   device_remove_file(adev->dev, _attr_gpu_busy_percent);
>  }
>
>  void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
> --
> 2.14.4
>
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Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs (v2)

[Abramov, Slava]

Acked-by: Slava Abramov 


From: amd-gfx  on behalf of Tom St Denis 

Sent: Wednesday, June 20, 2018 12:48:52 PM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs (v2)

This adds what should be a stable interface to read GPU
load from userspace.

(v2): Fix comments and name of file per recommendations.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 47 ++
 1 file changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 113edffb5960..49138ac2be24 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -918,6 +918,43 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
device *dev,
 return -EINVAL;
 }

+/**
+ * DOC: busy_percent
+ *
+ * The firmware computes a percentage of load based on the activity
+ * level in the IP cores.
+ */
+static ssize_t amdgpu_get_busy_percent(struct device *dev,
+   struct device_attribute *attr,
+   char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   int r, value, size = sizeof(value);
+
+   /* sanity check PP is enabled */
+   if (!(adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->read_sensor))
+   return -EINVAL;
+
+   /* read the IP busy sensor */
+   r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
+  (void *), );
+   if (r)
+   return r;
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", value);
+}
+
+static ssize_t amdgpu_set_busy_percent(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf,
+   size_t count)
+{
+   return -EINVAL;
+}
+
+
 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
amdgpu_get_dpm_forced_performance_level,
@@ -951,6 +988,8 @@ static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 amdgpu_get_pp_od_clk_voltage,
 amdgpu_set_pp_od_clk_voltage);
+static DEVICE_ATTR(gpu_busy_percent, S_IRUGO | S_IWUSR,
+   amdgpu_get_busy_percent, amdgpu_set_busy_percent);

 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
   struct device_attribute *attr,
@@ -1854,6 +1893,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 "pp_od_clk_voltage\n");
 return ret;
 }
+   ret = device_create_file(adev->dev,
+   _attr_gpu_busy_percent);
+   if (ret) {
+   DRM_ERROR("failed to create device file "
+   "gpu_busy_level\n");
+   return ret;
+   }
 ret = amdgpu_debugfs_pm_init(adev);
 if (ret) {
 DRM_ERROR("Failed to register debugfs file for dpm!\n");
@@ -1889,6 +1935,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 _attr_pp_power_profile_mode);
 device_remove_file(adev->dev,
 _attr_pp_od_clk_voltage);
+   device_remove_file(adev->dev, _attr_gpu_busy_percent);
 }

 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
--
2.14.4

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[pull] amdgpu drm-fixes-4.18

[Alex Deucher]

Hi Dave,

A few fixes for amdgpu for 4.18, nothing major.  Most going to stable.

The following changes since commit ce397d215ccd07b8ae3f71db689aedb85d56ab40:

  Linux 4.18-rc1 (2018-06-17 08:04:49 +0900)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.18

for you to fetch changes up to 7303b39e46b2f523334591f05fd9566cf929eb26:

  drm/amdgpu: Make amdgpu_vram_mgr_bo_invisible_size always accurate 
(2018-06-19 13:51:45 -0500)


Harry Wentland (1):
  drm/amdgpu: Don't default to DC support for Kaveri and older

James Zhu (1):
  drm/amdgpu:All UVD instances share one idle_work handle

Michel Dänzer (4):
  drm/amdgpu: Use kvmalloc_array for allocating VRAM manager nodes array
  drm/amdgpu: Update pin_size values before unpinning BO
  drm/amdgpu: Refactor amdgpu_vram_mgr_bo_invisible_size helper
  drm/amdgpu: Make amdgpu_vram_mgr_bo_invisible_size always accurate

Rajan Vaja (1):
  drm/amd/pp: Fix uninitialized variable

 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 24 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h|  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c| 14 
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c   | 39 --
 .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c |  2 +-
 7 files changed, 65 insertions(+), 27 deletions(-)
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[PATCH] drm/amdgpu/pm: Remove VLA usage

[Kees Cook]

In the quest to remove all stack VLA usage from the kernel[1], this
uses the maximum sane buffer size and removes copy/paste code.

[1] 
https://lkml.kernel.org/r/CA+55aFzCG-zNmZwX4A2FQpadafLfEzK6CC=qpxydaacu1rq...@mail.gmail.com

Signed-off-by: Kees Cook 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 100 +++--
 1 file changed, 42 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index b455da487782..5eb98cde22ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -593,40 +593,59 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
return snprintf(buf, PAGE_SIZE, "\n");
 }
 
-static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
-   struct device_attribute *attr,
-   const char *buf,
-   size_t count)
+/*
+ * Worst case: 32 bits individually specified, in octal at 12 characters
+ * per line (+1 for \n).
+ */
+#define AMDGPU_MASK_BUF_MAX(32 * 13)
+
+static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 {
-   struct drm_device *ddev = dev_get_drvdata(dev);
-   struct amdgpu_device *adev = ddev->dev_private;
int ret;
long level;
-   uint32_t mask = 0;
char *sub_str = NULL;
char *tmp;
-   char buf_cpy[count];
+   char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
const char delimiter[3] = {' ', '\n', '\0'};
+   size_t bytes;
 
-   memcpy(buf_cpy, buf, count+1);
+   *mask = 0;
+
+   bytes = min(count, sizeof(buf_cpy) - 1);
+   memcpy(buf_cpy, buf, bytes);
+   buf_cpy[bytes] = '\0';
tmp = buf_cpy;
while (tmp[0]) {
-   sub_str =  strsep(, delimiter);
+   sub_str = strsep(, delimiter);
if (strlen(sub_str)) {
ret = kstrtol(sub_str, 0, );
-
-   if (ret) {
-   count = -EINVAL;
-   goto fail;
-   }
-   mask |= 1 << level;
+   if (ret)
+   return -EINVAL;
+   *mask |= 1 << level;
} else
break;
}
+
+   return 0;
+}
+
+static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf,
+   size_t count)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   int ret;
+   uint32_t mask = 0;
+
+   ret = amdgpu_read_mask(buf, count, );
+   if (ret)
+   return ret;
+
if (adev->powerplay.pp_funcs->force_clock_level)
amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 
-fail:
return count;
 }
 
@@ -651,32 +670,15 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
int ret;
-   long level;
uint32_t mask = 0;
-   char *sub_str = NULL;
-   char *tmp;
-   char buf_cpy[count];
-   const char delimiter[3] = {' ', '\n', '\0'};
 
-   memcpy(buf_cpy, buf, count+1);
-   tmp = buf_cpy;
-   while (tmp[0]) {
-   sub_str =  strsep(, delimiter);
-   if (strlen(sub_str)) {
-   ret = kstrtol(sub_str, 0, );
+   ret = amdgpu_read_mask(buf, count, );
+   if (ret)
+   return ret;
 
-   if (ret) {
-   count = -EINVAL;
-   goto fail;
-   }
-   mask |= 1 << level;
-   } else
-   break;
-   }
if (adev->powerplay.pp_funcs->force_clock_level)
amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 
-fail:
return count;
 }
 
@@ -701,33 +703,15 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
int ret;
-   long level;
uint32_t mask = 0;
-   char *sub_str = NULL;
-   char *tmp;
-   char buf_cpy[count];
-   const char delimiter[3] = {' ', '\n', '\0'};
-
-   memcpy(buf_cpy, buf, count+1);
-   tmp = buf_cpy;
 
-   while (tmp[0]) {
-   sub_str =  strsep(, delimiter);
-   if (strlen(sub_str)) {
-   ret = kstrtol(sub_str, 0, );
+   ret = amdgpu_read_mask(buf, count, );
+   if (ret)
+   return ret;
 
-   if (ret) {
-   count = -EINVAL;
-   goto fail;
-   }
-   mask |= 1 << level;
-   } 

Re: [PATCH v3 1/2] drm/amdgpu: Polish SQ IH.

[Deucher, Alexander]

Series is:

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Andrey 
Grodzovsky 
Sent: Wednesday, June 20, 2018 2:17:22 PM
To: amd-gfx@lists.freedesktop.org; ckoenig.leichtzumer...@gmail.com
Cc: Panariti, David; Haehnle, Nicolai; Grodzovsky, Andrey
Subject: [PATCH v3 1/2] drm/amdgpu: Polish SQ IH.

Switch to using reg fields defines istead of magic values.
Add SH_ID and PRIV fields reading for instr. and err cases.

Signed-off-by: Andrey Grodzovsky 
Acked-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 36 +++
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 15e61e1..93904a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6958,10 +6958,11 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
 {
 u8 enc, se_id;
 char type[20];
+   unsigned ih_data = entry->src_data[0];

-   /* Parse all fields according to SQ_INTERRUPT* registers */
-   enc = (entry->src_data[0] >> 26) & 0x3;
-   se_id = (entry->src_data[0] >> 24) & 0x3;
+
+   enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
+   se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);

 switch (enc) {
 case 0:
@@ -6971,14 +6972,14 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
 "reg_timestamp %d, 
thread_trace_buff_full %d,"
 "wlt %d, thread_trace %d.\n",
 se_id,
-   (entry->src_data[0] >> 7) & 0x1,
-   (entry->src_data[0] >> 6) & 0x1,
-   (entry->src_data[0] >> 5) & 0x1,
-   (entry->src_data[0] >> 4) & 0x1,
-   (entry->src_data[0] >> 3) & 0x1,
-   (entry->src_data[0] >> 2) & 0x1,
-   (entry->src_data[0] >> 1) & 0x1,
-   entry->src_data[0] & 0x1
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, WLT),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
 );
 break;
 case 1:
@@ -6991,12 +6992,15 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,

 DRM_INFO(
 "SQ %s detected: "
-   "se_id %d, cu_id %d, simd_id %d, 
wave_id %d, vm_id %d\n",
+   "se_id %d, cu_id %d, simd_id %d, 
wave_id %d, vm_id %d\n"
+   "trap %s, sh_id %d. ",
 type, se_id,
-   (entry->src_data[0] >> 20) & 0xf,
-   (entry->src_data[0] >> 18) & 0x3,
-   (entry->src_data[0] >> 14) & 0xf,
-   (entry->src_data[0] >> 10) & 0xf
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, CU_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, VM_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, SH_ID)
 );
 break;
 default:
--
2.7.4

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[PATCH v3 2/2] drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH.

[Andrey Grodzovsky]

Access to SQ_EDC_INFO requires selecting register instance and
hence mutex lock when accessing GRBM_GFX_INDEX for which a work
is schedueled from IH. But SQ interrupt can be raised on many instances
at once which means queuing work will usually succeed for the first one
but fail for the rest since the work takes time to process. To avoid
losing info about other interrupt instances call the parsing function
directly from high IRQ when current work hasn't finished and avoid
accessing SQ_EDC_INFO in that case.

v2:
Simplify high IRQ and BH handlers synchronization using work_pending.
Remove {READ,WRITE}_ONCE notations since smp_{r,w}mb are implicit
compiler barriers.

v3:
Remove exlicit memory barriers as scedule_work has r/w barriers.

Signed-off-by: Andrey Grodzovsky 
Acked-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  7 +++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 82 +--
 2 files changed, 76 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d8e0cc0..c328c39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -930,6 +930,11 @@ struct amdgpu_ngg {
boolinit;
 };
 
+struct sq_work {
+   struct work_struct  work;
+   unsigned ih_data;
+};
+
 struct amdgpu_gfx {
struct mutexgpu_clock_mutex;
struct amdgpu_gfx_configconfig;
@@ -970,6 +975,8 @@ struct amdgpu_gfx {
struct amdgpu_irq_src   priv_inst_irq;
struct amdgpu_irq_src   cp_ecc_error_irq;
struct amdgpu_irq_src   sq_irq;
+   struct sq_work  sq_work;
+
/* gfx status */
uint32_tgfx_current_status;
/* ce ram size*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 93904a7..25fb5fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -704,6 +704,17 @@ static const u32 stoney_mgcg_cgcg_init[] =
mmCGTS_SM_CTRL_REG, 0x, 0x96940200,
 };
 
+
+static const char * const sq_edc_source_names[] = {
+   "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
+   "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
+   "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
+   "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
+   "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
+   "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
+   "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
+};
+
 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
@@ -2003,6 +2014,8 @@ static int gfx_v8_0_compute_ring_init(struct 
amdgpu_device *adev, int ring_id,
return 0;
 }
 
+static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
+
 static int gfx_v8_0_sw_init(void *handle)
 {
int i, j, k, r, ring_id;
@@ -2066,6 +2079,8 @@ static int gfx_v8_0_sw_init(void *handle)
return r;
}
 
+   INIT_WORK(>gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
+
adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 
gfx_v8_0_scratch_init(adev);
@@ -6952,14 +6967,11 @@ static int gfx_v8_0_cp_ecc_error_irq(struct 
amdgpu_device *adev,
return 0;
 }
 
-static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
-  struct amdgpu_irq_src *source,
-  struct amdgpu_iv_entry *entry)
+static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data)
 {
-   u8 enc, se_id;
+   u32 enc, se_id, sh_id, cu_id;
char type[20];
-   unsigned ih_data = entry->src_data[0];
-
+   int sq_edc_source = -1;
 
enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
@@ -6985,6 +6997,24 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
case 1:
case 2:
 
+   cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, 
CU_ID);
+   sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, 
SH_ID);
+
+   /*
+* This function can be called either directly from ISR
+* or from BH in which case we can access SQ_EDC_INFO
+* instance
+*/
+   if (in_task()) {
+   mutex_lock(>grbm_idx_mutex);
+   gfx_v8_0_select_se_sh(adev, se_id, sh_id, 
cu_id);
+
+   sq_edc_source = 
REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
+
+   gfx_v8_0_select_se_sh(adev, 

[PATCH v3 1/2] drm/amdgpu: Polish SQ IH.

[Andrey Grodzovsky]

Switch to using reg fields defines istead of magic values.
Add SH_ID and PRIV fields reading for instr. and err cases.

Signed-off-by: Andrey Grodzovsky 
Acked-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 36 +++
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 15e61e1..93904a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6958,10 +6958,11 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
 {
u8 enc, se_id;
char type[20];
+   unsigned ih_data = entry->src_data[0];
 
-   /* Parse all fields according to SQ_INTERRUPT* registers */
-   enc = (entry->src_data[0] >> 26) & 0x3;
-   se_id = (entry->src_data[0] >> 24) & 0x3;
+
+   enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
+   se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
 
switch (enc) {
case 0:
@@ -6971,14 +6972,14 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
"reg_timestamp %d, 
thread_trace_buff_full %d,"
"wlt %d, thread_trace %d.\n",
se_id,
-   (entry->src_data[0] >> 7) & 0x1,
-   (entry->src_data[0] >> 6) & 0x1,
-   (entry->src_data[0] >> 5) & 0x1,
-   (entry->src_data[0] >> 4) & 0x1,
-   (entry->src_data[0] >> 3) & 0x1,
-   (entry->src_data[0] >> 2) & 0x1,
-   (entry->src_data[0] >> 1) & 0x1,
-   entry->src_data[0] & 0x1
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, WLT),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
);
break;
case 1:
@@ -6991,12 +6992,15 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
 
DRM_INFO(
"SQ %s detected: "
-   "se_id %d, cu_id %d, simd_id %d, 
wave_id %d, vm_id %d\n",
+   "se_id %d, cu_id %d, simd_id %d, 
wave_id %d, vm_id %d\n"
+   "trap %s, sh_id %d. ",
type, se_id,
-   (entry->src_data[0] >> 20) & 0xf,
-   (entry->src_data[0] >> 18) & 0x3,
-   (entry->src_data[0] >> 14) & 0xf,
-   (entry->src_data[0] >> 10) & 0xf
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, CU_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, VM_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, SH_ID)
);
break;
default:
-- 
2.7.4

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[PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs (v2)

[Tom St Denis]

This adds what should be a stable interface to read GPU
load from userspace.

(v2): Fix comments and name of file per recommendations.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 47 ++
 1 file changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 113edffb5960..49138ac2be24 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -918,6 +918,43 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
device *dev,
return -EINVAL;
 }
 
+/**
+ * DOC: busy_percent
+ *
+ * The firmware computes a percentage of load based on the activity
+ * level in the IP cores.
+ */
+static ssize_t amdgpu_get_busy_percent(struct device *dev,
+   struct device_attribute *attr,
+   char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   int r, value, size = sizeof(value);
+
+   /* sanity check PP is enabled */
+   if (!(adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->read_sensor))
+   return -EINVAL;
+
+   /* read the IP busy sensor */
+   r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
+  (void *), );
+   if (r)
+   return r;
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", value);
+}
+
+static ssize_t amdgpu_set_busy_percent(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf,
+   size_t count)
+{
+   return -EINVAL;
+}
+
+
 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
   amdgpu_get_dpm_forced_performance_level,
@@ -951,6 +988,8 @@ static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
amdgpu_get_pp_od_clk_voltage,
amdgpu_set_pp_od_clk_voltage);
+static DEVICE_ATTR(gpu_busy_percent, S_IRUGO | S_IWUSR,
+   amdgpu_get_busy_percent, amdgpu_set_busy_percent);
 
 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
  struct device_attribute *attr,
@@ -1854,6 +1893,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
"pp_od_clk_voltage\n");
return ret;
}
+   ret = device_create_file(adev->dev,
+   _attr_gpu_busy_percent);
+   if (ret) {
+   DRM_ERROR("failed to create device file "
+   "gpu_busy_level\n");
+   return ret;
+   }
ret = amdgpu_debugfs_pm_init(adev);
if (ret) {
DRM_ERROR("Failed to register debugfs file for dpm!\n");
@@ -1889,6 +1935,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
_attr_pp_power_profile_mode);
device_remove_file(adev->dev,
_attr_pp_od_clk_voltage);
+   device_remove_file(adev->dev, _attr_gpu_busy_percent);
 }
 
 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
-- 
2.14.4

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Re: [PATCH v2 2/2] drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH v2.

[Andrey Grodzovsky]

OK, according to 
https://www.kernel.org/doc/Documentation/memory-barriers.txt, SLEEP AND 
WAKE-UP FUNCTIONS sections implies that.


Will respin the patch.

Andrey


On 06/20/2018 11:02 AM, Andrey Grodzovsky wrote:


Are you referring to insert_work->smp_mb(); ?

Andrey


On 06/20/2018 10:50 AM, Christian König wrote:

+ * Try to submit work so SQ_EDC_INFO can be accessed from
+ * BH. If previous work submission hasn't finished yet
+ * just print whatever info is possible directly from the ISR.
+ */
+    if (work_pending(>gfx.sq_work.work)) {
+    gfx_v8_0_parse_sq_irq(adev, ih_data);
+    } else {
+    adev->gfx.sq_work.ih_data = ih_data;
+    /* Verify the new value visible in BH handler */
+    smp_wmb();


You can drop the barrier here and in gfx_v8_0_sq_irq_work_func(), the 
schedule_work() function is a barrier itself for both reads and 
writes anyway.


Apart from that the both patches are Acked-by: Christian König 
.


Regards,
Christian. 




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Re: [PATCH] drm/amd/display: Missed to set some display requests to powerplay

[Alex Deucher]

On Wed, Jun 20, 2018 at 4:19 AM, Rex Zhu  wrote:
> Missed to set some clock requests and display info which were needed
> by powerplay.
>
> Signed-off-by: Rex Zhu 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> index 329cf3a..f348c6f 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> @@ -77,6 +77,7 @@ bool dm_pp_apply_display_requirements(
> const struct dm_pp_display_configuration *pp_display_cfg)
>  {
> struct amdgpu_device *adev = ctx->driver_context;
> +   int i;
>
> if (adev->pm.dpm_enabled) {
>
> @@ -107,6 +108,9 @@ bool dm_pp_apply_display_requirements(
> adev->pm.pm_display_cfg.min_mem_set_clock =
> pp_display_cfg->min_memory_clock_khz/10;
>
> +   adev->pm.pm_display_cfg.min_dcef_deep_sleep_set_clk = 
> pp_display_cfg->min_engine_clock_deep_sleep_khz / 10;
> +   adev->pm.pm_display_cfg.min_dcef_set_clk = 
> pp_display_cfg->min_dcfclock_khz / 10;
> +
> adev->pm.pm_display_cfg.multi_monitor_in_sync =
> pp_display_cfg->all_displays_in_sync;
> adev->pm.pm_display_cfg.min_vblank_time =
> @@ -126,6 +130,11 @@ bool dm_pp_apply_display_requirements(
> adev->pm.pm_display_cfg.crossfire_display_index = -1;
> adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
>
> +   for (i = 0; i < pp_display_cfg->display_count; i++) {
> +   const struct dm_pp_single_disp_config *dc_cfg =
> +   
> _display_cfg->disp_configs[i];
> +   adev->pm.pm_display_cfg.displays[i].controller_id = 
> dc_cfg->pipe_idx + 1;
> +   }
> /* TODO: complete implementation of
>  * pp_display_configuration_change().
>  * Follow example of:
> --
> 1.9.1
>
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Re: [PATCH v2 2/2] drm/amd/pp: Unify the shared struct between pp and display

[Alex Deucher]

On Wed, Jun 20, 2018 at 3:09 AM, Rex Zhu  wrote:
> v2: not change the header file dm_service_types.h, as it was
> shared with other Os. PP need to include this header file and
> remove same data struct defines.
>
> 1. move shared struct dm_pp_wm_sets_with_clock_ranges_soc15 to
>dm_pp_interface.h.
> 2. delete the same struct define in powerplay, use the struct
>display defined.
>
> Signed-off-by: Rex Zhu 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/include/dm_pp_interface.h  | 37 
> ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c   | 28 
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h   |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c |  2 +-
>  6 files changed, 20 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h 
> b/drivers/gpu/drm/amd/include/dm_pp_interface.h
> index 7852952..1d93a0c 100644
> --- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
> @@ -23,6 +23,8 @@
>  #ifndef _DM_PP_INTERFACE_
>  #define _DM_PP_INTERFACE_
>
> +#include "dm_services_types.h"
> +
>  #define PP_MAX_CLOCK_LEVELS 16
>
>  enum amd_pp_display_config_type{
> @@ -189,39 +191,4 @@ struct pp_display_clock_request {
> uint32_t clock_freq_in_khz;
>  };
>
> -#define PP_MAX_WM_SETS 4
> -
> -enum pp_wm_set_id {
> -   DC_WM_SET_A = 0,
> -   DC_WM_SET_B,
> -   DC_WM_SET_C,
> -   DC_WM_SET_D,
> -   DC_WM_SET_INVALID = 0x,
> -};
> -
> -struct pp_wm_set_with_dmif_clock_range_soc15 {
> -   enum pp_wm_set_id wm_set_id;
> -   uint32_t wm_min_dcefclk_in_khz;
> -   uint32_t wm_max_dcefclk_in_khz;
> -   uint32_t wm_min_memclk_in_khz;
> -   uint32_t wm_max_memclk_in_khz;
> -};
> -
> -struct pp_wm_set_with_mcif_clock_range_soc15 {
> -   enum pp_wm_set_id wm_set_id;
> -   uint32_t wm_min_socclk_in_khz;
> -   uint32_t wm_max_socclk_in_khz;
> -   uint32_t wm_min_memclk_in_khz;
> -   uint32_t wm_max_memclk_in_khz;
> -};
> -
> -struct pp_wm_sets_with_clock_ranges_soc15 {
> -   uint32_t num_wm_sets_dmif;
> -   uint32_t num_wm_sets_mcif;
> -   struct pp_wm_set_with_dmif_clock_range_soc15
> -   wm_sets_dmif[PP_MAX_WM_SETS];
> -   struct pp_wm_set_with_mcif_clock_range_soc15
> -   wm_sets_mcif[PP_MAX_WM_SETS];
> -};
> -
>  #endif /* _DM_PP_INTERFACE_ */
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 4ca8033..48ae990 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1134,7 +1134,7 @@ static int 
> smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> void *clock_ranges)
>  {
> struct smu10_hwmgr *data = hwmgr->backend;
> -   struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = 
> clock_ranges;
> +   struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = 
> clock_ranges;
> Watermarks_t *table = &(data->water_marks_table);
> int result = 0;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> index 93a3d02..5dd375d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> @@ -652,7 +652,7 @@ int smu_get_voltage_dependency_table_ppt_v1(
>  }
>
>  int smu_set_watermarks_for_clocks_ranges(void *wt_table,
> -   struct pp_wm_sets_with_clock_ranges_soc15 
> *wm_with_clock_ranges)
> +   struct dm_pp_wm_sets_with_clock_ranges_soc15 
> *wm_with_clock_ranges)
>  {
> uint32_t i;
> struct watermarks *table = wt_table;
> @@ -660,49 +660,49 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
> if (!table || !wm_with_clock_ranges)
> return -EINVAL;
>
> -   if (wm_with_clock_ranges->num_wm_sets_dmif > 4 || 
> wm_with_clock_ranges->num_wm_sets_mcif > 4)
> +   if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || 
> wm_with_clock_ranges->num_wm_mcif_sets > 4)
> return -EINVAL;
>
> -   for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
> +   for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
> table->WatermarkRow[1][i].MinClock =
> cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
> +   
> (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
> 100);
> table->WatermarkRow[1][i].MaxClock =
> cpu_to_le16((uint16_t)
> -   
> 

Re: [PATCH] drm/amd/powerplay: initialize uvd/vce powergate status v3

[Alex Deucher]

On Wed, Jun 20, 2018 at 2:40 AM, Evan Quan  wrote:
> On UVD/VCE dpm enabled/disabled, the powergate status will be
> set as false/true. So that we will not try to ungate/gate them(
> enable/disable their dpm) again.
>
> v2: added check for uvd/vce powergate status before gating
> v3: fix typo in description
>
> Change-Id: I569a5aa216b5e7d64a2b504f2ff98cc83ca802d5
> Signed-off-by: Evan Quan 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 23 
> ++
>  1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 45c8f2d..28b172e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -777,6 +777,21 @@ static int vega12_set_allowed_featuresmask(struct 
> pp_hwmgr *hwmgr)
> return 0;
>  }
>
> +static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
> +{
> +   struct vega12_hwmgr *data =
> +   (struct vega12_hwmgr *)(hwmgr->backend);
> +
> +   data->uvd_power_gated = true;
> +   data->vce_power_gated = true;
> +
> +   if (data->smu_features[GNLD_DPM_UVD].enabled)
> +   data->uvd_power_gated = false;
> +
> +   if (data->smu_features[GNLD_DPM_VCE].enabled)
> +   data->vce_power_gated = false;
> +}
> +
>  static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
>  {
> struct vega12_hwmgr *data =
> @@ -801,6 +816,8 @@ static int vega12_enable_all_smu_features(struct pp_hwmgr 
> *hwmgr)
> }
> }
>
> +   vega12_init_powergate_state(hwmgr);
> +
> return 0;
>  }
>
> @@ -1985,6 +2002,9 @@ static void vega12_power_gate_vce(struct pp_hwmgr 
> *hwmgr, bool bgate)
>  {
> struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
>
> +   if (data->vce_power_gated == bgate)
> +   return 0;
> +
> data->vce_power_gated = bgate;
> vega12_enable_disable_vce_dpm(hwmgr, !bgate);
>  }
> @@ -1993,6 +2013,9 @@ static void vega12_power_gate_uvd(struct pp_hwmgr 
> *hwmgr, bool bgate)
>  {
> struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
>
> +   if (data->uvd_power_gated == bgate)
> +   return 0;
> +
> data->uvd_power_gated = bgate;
> vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
>  }
> --
> 2.7.4
>
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Re: [PATCH 1/2] drm/amd/pp: Remove duplicate code in vega12_hwmgr.c

[Alex Deucher]

On Wed, Jun 20, 2018 at 1:58 AM, Rex Zhu  wrote:
> use smu_helper function smu_set_watermarks_for_clocks_ranges
> in vega12_set_watermarks_for_clocks_ranges.
>
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 43 
> +-
>  1 file changed, 1 insertion(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index bcb64cd..81b20d1 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1719,52 +1719,11 @@ static int 
> vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> Watermarks_t *table = &(data->smc_state_table.water_marks_table);
> struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = 
> clock_ranges;
> int result = 0;
> -   uint32_t i;
>
> if (!data->registry_data.disable_water_mark &&
> data->smu_features[GNLD_DPM_DCEFCLK].supported &&
> data->smu_features[GNLD_DPM_SOCCLK].supported) {
> -   for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
> -   table->WatermarkRow[WM_DCEFCLK][i].MinClock =
> -   cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
> -   100);
> -   table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
> -   cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
> -   100);
> -   table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
> -   cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
> -   100);
> -   table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
> -   cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
> -   100);
> -   table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 
> (uint8_t)
> -   
> wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
> -   }
> -
> -   for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
> -   table->WatermarkRow[WM_SOCCLK][i].MinClock =
> -   cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
> -   100);
> -   table->WatermarkRow[WM_SOCCLK][i].MaxClock =
> -   cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
> -   100);
> -   table->WatermarkRow[WM_SOCCLK][i].MinUclk =
> -   cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
> -   100);
> -   table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
> -   cpu_to_le16((uint16_t)
> -   
> (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
> -   100);
> -   table->WatermarkRow[WM_SOCCLK][i].WmSetting = 
> (uint8_t)
> -   
> wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
> -   }
> +   smu_set_watermarks_for_clocks_ranges(table, 
> wm_with_clock_ranges);
> data->water_marks_bitmap |= WaterMarksExist;
> data->water_marks_bitmap &= ~WaterMarksLoaded;
> }
> --
> 1.9.1
>
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Re: [PATCH] drm/amd/display: Fix a typo

[Alex Deucher]

On Wed, Jun 20, 2018 at 12:56 AM, Rex Zhu  wrote:
> change wm_min_memg_clk_in_khz -> wm_min_mem_clk_in_khz
>
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 8 
>  drivers/gpu/drm/amd/display/dc/dm_services_types.h  | 6 +++---
>  2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
> index 00c0a1e..943d74d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
> @@ -1000,7 +1000,7 @@ static void bw_calcs_data_update_from_pplib(struct dc 
> *dc)
> eng_clks.data[0].clocks_in_khz;
> clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
> eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz 
> - 1;
> -   clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
> +   clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
> mem_clks.data[0].clocks_in_khz;
> clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
> mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 
> 1;
> @@ -1010,7 +1010,7 @@ static void bw_calcs_data_update_from_pplib(struct dc 
> *dc)
> eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
> /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
> clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 500;
> -   clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz =
> +   clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
> mem_clks.data[0].clocks_in_khz;
> clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
> mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 
> 1;
> @@ -1020,7 +1020,7 @@ static void bw_calcs_data_update_from_pplib(struct dc 
> *dc)
> eng_clks.data[0].clocks_in_khz;
> clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
> eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz 
> - 1;
> -   clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz =
> +   clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
> mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
> /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
> clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 500;
> @@ -1030,7 +1030,7 @@ static void bw_calcs_data_update_from_pplib(struct dc 
> *dc)
> eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
> /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
> clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 500;
> -   clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz =
> +   clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
> mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
> /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
> clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 500;
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h 
> b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> index ab8c77d..2b83f92 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> @@ -137,7 +137,7 @@ struct dm_pp_clock_range_for_wm_set {
> enum dm_pp_wm_set_id wm_set_id;
> uint32_t wm_min_eng_clk_in_khz;
> uint32_t wm_max_eng_clk_in_khz;
> -   uint32_t wm_min_memg_clk_in_khz;
> +   uint32_t wm_min_mem_clk_in_khz;
> uint32_t wm_max_mem_clk_in_khz;
>  };
>
> @@ -150,7 +150,7 @@ struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
> enum dm_pp_wm_set_id wm_set_id;
> uint32_t wm_min_dcfclk_clk_in_khz;
> uint32_t wm_max_dcfclk_clk_in_khz;
> -   uint32_t wm_min_memg_clk_in_khz;
> +   uint32_t wm_min_mem_clk_in_khz;
> uint32_t wm_max_mem_clk_in_khz;
>  };
>
> @@ -158,7 +158,7 @@ struct dm_pp_clock_range_for_mcif_wm_set_soc15 {
> enum dm_pp_wm_set_id wm_set_id;
> uint32_t wm_min_socclk_clk_in_khz;
> uint32_t wm_max_socclk_clk_in_khz;
> -   uint32_t wm_min_memg_clk_in_khz;
> +   uint32_t wm_min_mem_clk_in_khz;
> uint32_t wm_max_mem_clk_in_khz;
>  };
>
> --
> 1.9.1
>
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Re: [PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display

[Alex Deucher]

Yes, understood.  I just wanted to make sure we didn't merge both and break
things.

Alex


On Wed, Jun 20, 2018 at 10:51 AM, Zhu, Rex  wrote:

> Hi Alex,
>
>
> Mikita's patch was still not in drm-next.
>
> I reviewed the interfaces between powerplay and display.
>
> Most of them were still not implemented. so the services powerplay
> exported to dc will not be called.
>
> I tried to implement them.
>
> and then we can  try to test  the strutter mode on raven in linux.
>
>
> Best Regards
>
> Rex
>
>
> --
> *From:* Alex Deucher 
> *Sent:* Wednesday, June 20, 2018 11:47 AM
> *To:* Wentland, Harry
> *Cc:* amd-gfx list; Wu, Hersen; Lipski, Mikita; Laktyushkin, Dmytro; Zhu,
> Rex
> *Subject:* Re: [PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to
> Display
>
> On Tue, Jun 19, 2018 at 5:17 PM, Harry Wentland 
> wrote:
> > From: Rex Zhu 
> >
> > Transfer 10KHz (requested by smu) to KHz needed by Display
> > component.
> >
> > This can fix the issue 4k Monitor can't be lit up on Vega/Raven.
> >
> > Signed-off-by: Rex Zhu 
> > Acked-by: Alex Deucher 
>
> Need to make sure we drop Mikita's patch if we apply this one
> otherwise the clocks will be wrong again.
>
> Alex
>
> > ---
> >  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  |  4 ++--
> >  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 +-
> >  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 10 +-
> >  3 files changed, 12 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > index d4bc83e81389..c905df42adc5 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > @@ -993,7 +993,7 @@ static int smu10_get_clock_by_type_with_latency(struct
> pp_hwmgr *hwmgr,
> >
> > clocks->num_levels = 0;
> > for (i = 0; i < pclk_vol_table->count; i++) {
> > -   clocks->data[i].clocks_in_khz =
> pclk_vol_table->entries[i].clk;
> > +   clocks->data[i].clocks_in_khz =
> pclk_vol_table->entries[i].clk * 10;
> > clocks->data[i].latency_in_us = latency_required ?
> >
> smu10_get_mem_latency(hwmgr,
> >
> pclk_vol_table->entries[i].clk) :
> > @@ -1044,7 +1044,7 @@ static int smu10_get_clock_by_type_with_voltage(struct
> pp_hwmgr *hwmgr,
> >
> > clocks->num_levels = 0;
> > for (i = 0; i < pclk_vol_table->count; i++) {
> > -   clocks->data[i].clocks_in_khz =
> pclk_vol_table->entries[i].clk;
> > +   clocks->data[i].clocks_in_khz =
> pclk_vol_table->entries[i].clk  * 10;
> > clocks->data[i].voltage_in_mv =
> pclk_vol_table->entries[i].vol;
> > clocks->num_levels++;
> > }
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> > index 3b8d36df52e9..e9a8b527d481 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> > @@ -4067,7 +4067,7 @@ static void vega10_get_sclks(struct pp_hwmgr
> *hwmgr,
> > for (i = 0; i < dep_table->count; i++) {
> > if (dep_table->entries[i].clk) {
> > clocks->data[clocks->num_levels].clocks_in_khz =
> > -   dep_table->entries[i].clk;
> > +   dep_table->entries[i].clk * 10;
> > clocks->num_levels++;
> > }
> > }
> > @@ -4104,7 +4104,7 @@ static void vega10_get_memclocks(struct pp_hwmgr
> *hwmgr,
> > clocks->data[clocks->num_levels].clocks_in_khz =
> > data->mclk_latency_table.entries
> > [data->mclk_latency_table.count].frequency =
> > -   dep_table->entries[i].clk;
> > +   dep_table->entries[i].clk * 10;
> > clocks->data[clocks->num_levels].latency_in_us =
> > data->mclk_latency_table.entries
> > [data->mclk_latency_table.count].latency =
> > @@ -4126,7 +4126,7 @@ static void vega10_get_dcefclocks(struct pp_hwmgr
> *hwmgr,
> > uint32_t i;
> >
> > for (i = 0; i < dep_table->count; i++) {
> > -   clocks->data[i].clocks_in_khz =
> dep_table->entries[i].clk;
> > +   clocks->data[i].clocks_in_khz =
> dep_table->entries[i].clk * 10;
> > clocks->data[i].latency_in_us = 0;
> > clocks->num_levels++;
> > }
> > @@ -4142,7 +4142,7 @@ static void vega10_get_socclocks(struct pp_hwmgr
> *hwmgr,
> > uint32_t i;
> >
> > for (i = 0; i < dep_table->count; i++) {
> > -   clocks->data[i].clocks_in_khz =
> dep_table->entries[i].clk;
> > +   clocks->data[i].clocks_in_khz =
> 

Re: [PATCH v2 2/2] drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH v2.

[Andrey Grodzovsky]

Are you referring to insert_work->smp_mb(); ?

Andrey


On 06/20/2018 10:50 AM, Christian König wrote:

+ * Try to submit work so SQ_EDC_INFO can be accessed from
+ * BH. If previous work submission hasn't finished yet
+ * just print whatever info is possible directly from the ISR.
+ */
+    if (work_pending(>gfx.sq_work.work)) {
+    gfx_v8_0_parse_sq_irq(adev, ih_data);
+    } else {
+    adev->gfx.sq_work.ih_data = ih_data;
+    /* Verify the new value visible in BH handler */
+    smp_wmb();


You can drop the barrier here and in gfx_v8_0_sq_irq_work_func(), the 
schedule_work() function is a barrier itself for both reads and writes 
anyway.


Apart from that the both patches are Acked-by: Christian König 
.


Regards,
Christian. 


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Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs

[Alex Deucher]

On Wed, Jun 20, 2018 at 8:31 AM, Tom St Denis  wrote:
> This adds what should be a stable interface to read GPU
> load from userspace.
>
> Signed-off-by: Tom St Denis 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 41 
> ++
>  1 file changed, 41 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 113edffb5960..d57b414ac228 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -918,6 +918,37 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
> device *dev,
> return -EINVAL;
>  }
>
> +static ssize_t amdgpu_get_busy_level(struct device *dev,
> +   struct device_attribute *attr,
> +   char *buf)
> +{
> +   struct drm_device *ddev = dev_get_drvdata(dev);
> +   struct amdgpu_device *adev = ddev->dev_private;
> +   int r, value, size = sizeof(value);
> +
> +   /* sanity check PP is enabled */
> +   if (!(adev->powerplay.pp_funcs &&
> + adev->powerplay.pp_funcs->read_sensor))
> +   return -EINVAL;
> +
> +   /* get the temperature */
> +   r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
> +  (void *), );
> +   if (r)
> +   return r;
> +
> +   return snprintf(buf, PAGE_SIZE, "%d\n", value);
> +}
> +
> +static ssize_t amdgpu_set_gpu_busy_level(struct device *dev,
> +   struct device_attribute *attr,
> +   const char *buf,
> +   size_t count)
> +{
> +   return -EINVAL;
> +}
> +
> +
>  static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, 
> amdgpu_set_dpm_state);
>  static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
>amdgpu_get_dpm_forced_performance_level,
> @@ -951,6 +982,8 @@ static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | 
> S_IWUSR,
>  static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
> amdgpu_get_pp_od_clk_voltage,
> amdgpu_set_pp_od_clk_voltage);
> +static DEVICE_ATTR(gpu_busy_level, S_IRUGO | S_IWUSR,
> +   amdgpu_get_busy_level, amdgpu_set_gpu_busy_level);


Maybe call the node gpu_busy_percent since it returns a percentage?

>
>  static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
>   struct device_attribute *attr,
> @@ -1854,6 +1887,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
> "pp_od_clk_voltage\n");
> return ret;
> }
> +   ret = device_create_file(adev->dev,
> +   _attr_gpu_busy_level);
> +   if (ret) {
> +   DRM_ERROR("failed to create device file "
> +   "gpu_busy_level\n");
> +   return ret;
> +   }
> ret = amdgpu_debugfs_pm_init(adev);
> if (ret) {
> DRM_ERROR("Failed to register debugfs file for dpm!\n");
> @@ -1889,6 +1929,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
> _attr_pp_power_profile_mode);
> device_remove_file(adev->dev,
> _attr_pp_od_clk_voltage);
> +   device_remove_file(adev->dev, _attr_gpu_busy_level);
>  }
>
>  void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
> --
> 2.14.4
>
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Re: [PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display

[Zhu, Rex]

Hi Alex,


Mikita's patch was still not in drm-next.

I reviewed the interfaces between powerplay and display.

Most of them were still not implemented. so the services powerplay exported to 
dc will not be called.

I tried to implement them.

and then we can  try to test  the strutter mode on raven in linux.


Best Regards

Rex



From: Alex Deucher 
Sent: Wednesday, June 20, 2018 11:47 AM
To: Wentland, Harry
Cc: amd-gfx list; Wu, Hersen; Lipski, Mikita; Laktyushkin, Dmytro; Zhu, Rex
Subject: Re: [PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display

On Tue, Jun 19, 2018 at 5:17 PM, Harry Wentland  wrote:
> From: Rex Zhu 
>
> Transfer 10KHz (requested by smu) to KHz needed by Display
> component.
>
> This can fix the issue 4k Monitor can't be lit up on Vega/Raven.
>
> Signed-off-by: Rex Zhu 
> Acked-by: Alex Deucher 

Need to make sure we drop Mikita's patch if we apply this one
otherwise the clocks will be wrong again.

Alex

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  |  4 ++--
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 10 +-
>  3 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index d4bc83e81389..c905df42adc5 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -993,7 +993,7 @@ static int smu10_get_clock_by_type_with_latency(struct 
> pp_hwmgr *hwmgr,
>
> clocks->num_levels = 0;
> for (i = 0; i < pclk_vol_table->count; i++) {
> -   clocks->data[i].clocks_in_khz = 
> pclk_vol_table->entries[i].clk;
> +   clocks->data[i].clocks_in_khz = 
> pclk_vol_table->entries[i].clk * 10;
> clocks->data[i].latency_in_us = latency_required ?
> smu10_get_mem_latency(hwmgr,
> 
> pclk_vol_table->entries[i].clk) :
> @@ -1044,7 +1044,7 @@ static int smu10_get_clock_by_type_with_voltage(struct 
> pp_hwmgr *hwmgr,
>
> clocks->num_levels = 0;
> for (i = 0; i < pclk_vol_table->count; i++) {
> -   clocks->data[i].clocks_in_khz = 
> pclk_vol_table->entries[i].clk;
> +   clocks->data[i].clocks_in_khz = 
> pclk_vol_table->entries[i].clk  * 10;
> clocks->data[i].voltage_in_mv = 
> pclk_vol_table->entries[i].vol;
> clocks->num_levels++;
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 3b8d36df52e9..e9a8b527d481 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4067,7 +4067,7 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
> for (i = 0; i < dep_table->count; i++) {
> if (dep_table->entries[i].clk) {
> clocks->data[clocks->num_levels].clocks_in_khz =
> -   dep_table->entries[i].clk;
> +   dep_table->entries[i].clk * 10;
> clocks->num_levels++;
> }
> }
> @@ -4104,7 +4104,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
> clocks->data[clocks->num_levels].clocks_in_khz =
> data->mclk_latency_table.entries
> [data->mclk_latency_table.count].frequency =
> -   dep_table->entries[i].clk;
> +   dep_table->entries[i].clk * 10;
> clocks->data[clocks->num_levels].latency_in_us =
> data->mclk_latency_table.entries
> [data->mclk_latency_table.count].latency =
> @@ -4126,7 +4126,7 @@ static void vega10_get_dcefclocks(struct pp_hwmgr 
> *hwmgr,
> uint32_t i;
>
> for (i = 0; i < dep_table->count; i++) {
> -   clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> +   clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 
> 10;
> clocks->data[i].latency_in_us = 0;
> clocks->num_levels++;
> }
> @@ -4142,7 +4142,7 @@ static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
> uint32_t i;
>
> for (i = 0; i < dep_table->count; i++) {
> -   clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> +   clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 
> 10;
> clocks->data[i].latency_in_us = 0;
> clocks->num_levels++;
> }
> @@ -4202,7 +4202,7 @@ static int vega10_get_clock_by_type_with_voltage(struct 
> pp_hwmgr *hwmgr,
> }
>
> 

Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs

[Alex Deucher]

On Wed, Jun 20, 2018 at 10:39 AM, Tom St Denis  wrote:
>
>
> On 06/20/2018 10:37 AM, Abramov, Slava wrote:
>>
>> I see some functions in amdgpu_pm.c have function level documentation, so
>> that it would be good to have this for newly added functions.
>
>
> Sure I can add some comments/docs.
>
>
>> Another comment is inline.
>>
>>
>>> From: amd-gfx  on behalf of Tom St
>>> Denis 
>>
>>
>>  >Sent: Wednesday, June 20, 2018 8:31 AM
>>  >To: amd-gfx@lists.freedesktop.org
>>  >Cc: StDenis, Tom
>>  >Subject: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs
>>  >
>>  >This adds what should be a stable interface to read GPU
>>  >load from userspace.
>>  >
>>  >Signed-off-by: Tom St Denis 
>>  >---
>>  > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 41
>> ++
>>  > 1 file changed, 41 insertions(+)
>>  >
>>  >diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>>  >index 113edffb5960..d57b414ac228 100644
>>  >--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>>  >+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>>  >@@ -918,6 +918,37 @@ static ssize_t
>> amdgpu_set_pp_power_profile_mode(struct device *dev,
>>  > return -EINVAL;
>>  > }
>>  >
>>  >+static ssize_t amdgpu_get_busy_level(struct device *dev,
>>  >+   struct device_attribute *attr,
>>  >+   char *buf)
>>  >+{
>>  >+   struct drm_device *ddev = dev_get_drvdata(dev);
>>  >+   struct amdgpu_device *adev = ddev->dev_private;
>>  >+   int r, value, size = sizeof(value);
>>  >+
>>  >+   /* sanity check PP is enabled */
>>  >+   if (!(adev->powerplay.pp_funcs &&
>>  >+ adev->powerplay.pp_funcs->read_sensor))
>>  >+   return -EINVAL;
>>  >+
>>  >+   /* get the temperature */
>>
>> Is load is the same thing as temperature?
>
>
>
> Nope, there is a separate sensor for that but it is included in hwmon and
> Alex would rather not duplicate it.
>
> GPU_LOAD is a value returned by firmware based on the RLC busy status (I
> think...).

It's the overall busy status of all blocks that contribute to what the
SMU considers busy for the purpose of dynamic clocking.

Alex

>
> Tom
>
> ___
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Re: [PATCH v2 2/2] drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH v2.

[Christian König]

Am 20.06.2018 um 16:43 schrieb Andrey Grodzovsky:

Access to SQ_EDC_INFO requires selecting register instance and
hence mutex lock when accessing GRBM_GFX_INDEX for which a work
is schedueled from IH. But SQ interrupt can be raised on many instances
at once which means queuing work will usually succeed for the first one
but fail for the reset since the work takes time to process. To avoid
losing info about other interrupt instances call the parsing function
directly from high IRQ when current work hasn't finished and avoid
accessing SQ_EDC_INFO in that case.

v2:
Simplify high IRQ and BH handlers synchronization using work_pending.
Remove {READ,WRITE}_ONCE notations since smp_{r,w}mb are implicit
compiler barriers.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  7 +++
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 86 +--
  2 files changed, 80 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d8e0cc0..c328c39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -930,6 +930,11 @@ struct amdgpu_ngg {
boolinit;
  };
  
+struct sq_work {

+   struct work_struct  work;
+   unsigned ih_data;
+};
+
  struct amdgpu_gfx {
struct mutexgpu_clock_mutex;
struct amdgpu_gfx_configconfig;
@@ -970,6 +975,8 @@ struct amdgpu_gfx {
struct amdgpu_irq_src   priv_inst_irq;
struct amdgpu_irq_src   cp_ecc_error_irq;
struct amdgpu_irq_src   sq_irq;
+   struct sq_work  sq_work;
+
/* gfx status */
uint32_tgfx_current_status;
/* ce ram size*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 93904a7..f6e0401 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -704,6 +704,17 @@ static const u32 stoney_mgcg_cgcg_init[] =
mmCGTS_SM_CTRL_REG, 0x, 0x96940200,
  };
  
+

+static const char * const sq_edc_source_names[] = {
+   "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
+   "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
+   "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
+   "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
+   "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
+   "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
+   "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
+};
+
  static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
  static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
@@ -2003,6 +2014,8 @@ static int gfx_v8_0_compute_ring_init(struct 
amdgpu_device *adev, int ring_id,
return 0;
  }
  
+static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);

+
  static int gfx_v8_0_sw_init(void *handle)
  {
int i, j, k, r, ring_id;
@@ -2066,6 +2079,8 @@ static int gfx_v8_0_sw_init(void *handle)
return r;
}
  
+	INIT_WORK(>gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);

+
adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
  
  	gfx_v8_0_scratch_init(adev);

@@ -6952,14 +6967,11 @@ static int gfx_v8_0_cp_ecc_error_irq(struct 
amdgpu_device *adev,
return 0;
  }
  
-static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,

-  struct amdgpu_irq_src *source,
-  struct amdgpu_iv_entry *entry)
+static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data)
  {
-   u8 enc, se_id;
+   u32 enc, se_id, sh_id, cu_id;
char type[20];
-   unsigned ih_data = entry->src_data[0];
-
+   int sq_edc_source = -1;
  
  	enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);

se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
@@ -6985,6 +6997,24 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
case 1:
case 2:
  
+			cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);

+   sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, 
SH_ID);
+
+   /*
+* This function can be called either directly from ISR
+* or from BH in which case we can access SQ_EDC_INFO
+* instance
+*/
+   if (in_task()) {
+   mutex_lock(>grbm_idx_mutex);
+   gfx_v8_0_select_se_sh(adev, se_id, sh_id, 
cu_id);
+
+   sq_edc_source = 
REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
+
+   gfx_v8_0_select_se_sh(adev, 0x, 
0x, 0x);
+   

Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs

[Tom St Denis]

Hi Slava,

Ah yes, I copied it from another function (because the struct path to 
the pp functions is annoying to look up hehehehe).


Thanks!

I'll submit a v2 in a bit.

Cheers,
Tom

On 06/20/2018 10:41 AM, Abramov, Slava wrote:

Should the comment then say 'get the load' instead of 'get the temperature'?


*From:* StDenis, Tom
*Sent:* Wednesday, June 20, 2018 10:39:25 AM
*To:* Abramov, Slava; amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs


On 06/20/2018 10:37 AM, Abramov, Slava wrote:
I see some functions in amdgpu_pm.c have function level documentation, 
so that it would be good to have this for newly added functions.


Sure I can add some comments/docs.


Another comment is inline.



From: amd-gfx  on behalf of Tom St Denis 



  >Sent: Wednesday, June 20, 2018 8:31 AM
  >To: amd-gfx@lists.freedesktop.org
  >Cc: StDenis, Tom
  >Subject: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs
  >
  >This adds what should be a stable interface to read GPU
  >load from userspace.
  >
  >Signed-off-by: Tom St Denis 
  >---
  > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 41 
++

  > 1 file changed, 41 insertions(+)
  >
  >diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

  >index 113edffb5960..d57b414ac228 100644
  >--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
  >+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
  >@@ -918,6 +918,37 @@ static ssize_t 
amdgpu_set_pp_power_profile_mode(struct device *dev,

  >         return -EINVAL;
  > }
  >
  >+static ssize_t amdgpu_get_busy_level(struct device *dev,
  >+               struct device_attribute *attr,
  >+               char *buf)
  >+{
  >+       struct drm_device *ddev = dev_get_drvdata(dev);
  >+       struct amdgpu_device *adev = ddev->dev_private;
  >+       int r, value, size = sizeof(value);
  >+
  >+       /* sanity check PP is enabled */
  >+       if (!(adev->powerplay.pp_funcs &&
  >+             adev->powerplay.pp_funcs->read_sensor))
  >+               return -EINVAL;
  >+
  >+       /* get the temperature */

Is load is the same thing as temperature?



Nope, there is a separate sensor for that but it is included in hwmon
and Alex would rather not duplicate it.

GPU_LOAD is a value returned by firmware based on the RLC busy status (I
think...).

Tom

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Re: [PATCH] drm/amdgpu: band aid validating VM PTs

[Christian König]

Am 20.06.2018 um 13:25 schrieb Huang Rui:

On Tue, Jun 19, 2018 at 02:57:00PM +0200, Christian König wrote:

Always validating the VM PTs takes to much time. Only always validate
the per VM BOs for now.

Christian, you delete PTE BO instead of moving them into idle list. The
intention is to avoid them do evction back when do vm_validate_pt_bos,
right?


No, the intention is to avoid the extra command submission overhead with 
moving them on the LRU.


This messes the LRU for VMs up a bit, but that shouldn't matter much 
because when we need to evict PTs the performance is not relevant 
anymore anyway.


Christian.



But in that function, I just see that it will walk over the idle list and
move the bo into lru list, and didn't find the evction behaviour called
explicitly. So why will it save the performance cost?

Thanks,
Ray


Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 819949418495..7c30451ba897 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1082,7 +1082,7 @@ int amdgpu_vm_update_directories(struct amdgpu_device 
*adev,
   struct amdgpu_vm_bo_base,
   vm_status);
bo_base->moved = false;
-   list_move(_base->vm_status, >idle);
+   list_del_init(_base->vm_status);
  
  		bo = bo_base->bo->parent;

if (!bo)
--
2.14.1

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[PATCH v2 2/2] drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH v2.

[Andrey Grodzovsky]

Access to SQ_EDC_INFO requires selecting register instance and
hence mutex lock when accessing GRBM_GFX_INDEX for which a work
is schedueled from IH. But SQ interrupt can be raised on many instances
at once which means queuing work will usually succeed for the first one
but fail for the reset since the work takes time to process. To avoid
losing info about other interrupt instances call the parsing function
directly from high IRQ when current work hasn't finished and avoid
accessing SQ_EDC_INFO in that case.

v2:
Simplify high IRQ and BH handlers synchronization using work_pending.
Remove {READ,WRITE}_ONCE notations since smp_{r,w}mb are implicit
compiler barriers.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  7 +++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 86 +--
 2 files changed, 80 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d8e0cc0..c328c39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -930,6 +930,11 @@ struct amdgpu_ngg {
boolinit;
 };
 
+struct sq_work {
+   struct work_struct  work;
+   unsigned ih_data;
+};
+
 struct amdgpu_gfx {
struct mutexgpu_clock_mutex;
struct amdgpu_gfx_configconfig;
@@ -970,6 +975,8 @@ struct amdgpu_gfx {
struct amdgpu_irq_src   priv_inst_irq;
struct amdgpu_irq_src   cp_ecc_error_irq;
struct amdgpu_irq_src   sq_irq;
+   struct sq_work  sq_work;
+
/* gfx status */
uint32_tgfx_current_status;
/* ce ram size*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 93904a7..f6e0401 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -704,6 +704,17 @@ static const u32 stoney_mgcg_cgcg_init[] =
mmCGTS_SM_CTRL_REG, 0x, 0x96940200,
 };
 
+
+static const char * const sq_edc_source_names[] = {
+   "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
+   "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
+   "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
+   "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
+   "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
+   "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
+   "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
+};
+
 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
@@ -2003,6 +2014,8 @@ static int gfx_v8_0_compute_ring_init(struct 
amdgpu_device *adev, int ring_id,
return 0;
 }
 
+static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
+
 static int gfx_v8_0_sw_init(void *handle)
 {
int i, j, k, r, ring_id;
@@ -2066,6 +2079,8 @@ static int gfx_v8_0_sw_init(void *handle)
return r;
}
 
+   INIT_WORK(>gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
+
adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 
gfx_v8_0_scratch_init(adev);
@@ -6952,14 +6967,11 @@ static int gfx_v8_0_cp_ecc_error_irq(struct 
amdgpu_device *adev,
return 0;
 }
 
-static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
-  struct amdgpu_irq_src *source,
-  struct amdgpu_iv_entry *entry)
+static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data)
 {
-   u8 enc, se_id;
+   u32 enc, se_id, sh_id, cu_id;
char type[20];
-   unsigned ih_data = entry->src_data[0];
-
+   int sq_edc_source = -1;
 
enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
@@ -6985,6 +6997,24 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
case 1:
case 2:
 
+   cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, 
CU_ID);
+   sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, 
SH_ID);
+
+   /*
+* This function can be called either directly from ISR
+* or from BH in which case we can access SQ_EDC_INFO
+* instance
+*/
+   if (in_task()) {
+   mutex_lock(>grbm_idx_mutex);
+   gfx_v8_0_select_se_sh(adev, se_id, sh_id, 
cu_id);
+
+   sq_edc_source = 
REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
+
+   gfx_v8_0_select_se_sh(adev, 0x, 
0x, 0x);
+   mutex_unlock(>grbm_idx_mutex);
+ 

[PATCH v2 1/2] drm/amdgpu: Polish SQ IH.

[Andrey Grodzovsky]

Switch to using reg fields defines istead of magic values.
Add SH_ID and PRIV fields reading for instr. and err cases.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 36 +++
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 15e61e1..93904a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6958,10 +6958,11 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
 {
u8 enc, se_id;
char type[20];
+   unsigned ih_data = entry->src_data[0];
 
-   /* Parse all fields according to SQ_INTERRUPT* registers */
-   enc = (entry->src_data[0] >> 26) & 0x3;
-   se_id = (entry->src_data[0] >> 24) & 0x3;
+
+   enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
+   se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
 
switch (enc) {
case 0:
@@ -6971,14 +6972,14 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
"reg_timestamp %d, 
thread_trace_buff_full %d,"
"wlt %d, thread_trace %d.\n",
se_id,
-   (entry->src_data[0] >> 7) & 0x1,
-   (entry->src_data[0] >> 6) & 0x1,
-   (entry->src_data[0] >> 5) & 0x1,
-   (entry->src_data[0] >> 4) & 0x1,
-   (entry->src_data[0] >> 3) & 0x1,
-   (entry->src_data[0] >> 2) & 0x1,
-   (entry->src_data[0] >> 1) & 0x1,
-   entry->src_data[0] & 0x1
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, WLT),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
);
break;
case 1:
@@ -6991,12 +6992,15 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
 
DRM_INFO(
"SQ %s detected: "
-   "se_id %d, cu_id %d, simd_id %d, 
wave_id %d, vm_id %d\n",
+   "se_id %d, cu_id %d, simd_id %d, 
wave_id %d, vm_id %d\n"
+   "trap %s, sh_id %d. ",
type, se_id,
-   (entry->src_data[0] >> 20) & 0xf,
-   (entry->src_data[0] >> 18) & 0x3,
-   (entry->src_data[0] >> 14) & 0xf,
-   (entry->src_data[0] >> 10) & 0xf
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, CU_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, VM_ID),
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
+   REG_GET_FIELD(ih_data, 
SQ_INTERRUPT_WORD_WAVE, SH_ID)
);
break;
default:
-- 
2.7.4

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Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs

[Abramov, Slava]

Should the comment then say 'get the load' instead of 'get the temperature'?


From: StDenis, Tom
Sent: Wednesday, June 20, 2018 10:39:25 AM
To: Abramov, Slava; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs



On 06/20/2018 10:37 AM, Abramov, Slava wrote:
> I see some functions in amdgpu_pm.c have function level documentation,
> so that it would be good to have this for newly added functions.

Sure I can add some comments/docs.

> Another comment is inline.
>
>
>>From: amd-gfx  on behalf of Tom St 
>>Denis 
>
>  >Sent: Wednesday, June 20, 2018 8:31 AM
>  >To: amd-gfx@lists.freedesktop.org
>  >Cc: StDenis, Tom
>  >Subject: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs
>  >
>  >This adds what should be a stable interface to read GPU
>  >load from userspace.
>  >
>  >Signed-off-by: Tom St Denis 
>  >---
>  > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 41
> ++
>  > 1 file changed, 41 insertions(+)
>  >
>  >diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>  >index 113edffb5960..d57b414ac228 100644
>  >--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>  >+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>  >@@ -918,6 +918,37 @@ static ssize_t
> amdgpu_set_pp_power_profile_mode(struct device *dev,
>  > return -EINVAL;
>  > }
>  >
>  >+static ssize_t amdgpu_get_busy_level(struct device *dev,
>  >+   struct device_attribute *attr,
>  >+   char *buf)
>  >+{
>  >+   struct drm_device *ddev = dev_get_drvdata(dev);
>  >+   struct amdgpu_device *adev = ddev->dev_private;
>  >+   int r, value, size = sizeof(value);
>  >+
>  >+   /* sanity check PP is enabled */
>  >+   if (!(adev->powerplay.pp_funcs &&
>  >+ adev->powerplay.pp_funcs->read_sensor))
>  >+   return -EINVAL;
>  >+
>  >+   /* get the temperature */
>
> Is load is the same thing as temperature?


Nope, there is a separate sensor for that but it is included in hwmon
and Alex would rather not duplicate it.

GPU_LOAD is a value returned by firmware based on the RLC busy status (I
think...).

Tom
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Re: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs

[Abramov, Slava]

I see some functions in amdgpu_pm.c have function level documentation, so that 
it would be good to have this for newly added functions.


Another comment is inline.


>From: amd-gfx  on behalf of Tom St 
>Denis 

>Sent: Wednesday, June 20, 2018 8:31 AM
>To: amd-gfx@lists.freedesktop.org
>Cc: StDenis, Tom
>Subject: [PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs
>
>This adds what should be a stable interface to read GPU
>load from userspace.
>
>Signed-off-by: Tom St Denis 
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 41 ++
> 1 file changed, 41 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>index 113edffb5960..d57b414ac228 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>@@ -918,6 +918,37 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
>device *dev,
> return -EINVAL;
> }
>
>+static ssize_t amdgpu_get_busy_level(struct device *dev,
>+   struct device_attribute *attr,
>+   char *buf)
>+{
>+   struct drm_device *ddev = dev_get_drvdata(dev);
>+   struct amdgpu_device *adev = ddev->dev_private;
>+   int r, value, size = sizeof(value);
>+
>+   /* sanity check PP is enabled */
>+   if (!(adev->powerplay.pp_funcs &&
>+ adev->powerplay.pp_funcs->read_sensor))
>+   return -EINVAL;
>+
>+   /* get the temperature */

Is load is the same thing as temperature?

[snap]


Slava A
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Re: [PATCH 2/5] dma-buf: remove kmap_atomic interface

[Christian König]

Am 20.06.2018 um 16:04 schrieb Christian König:

Am 20.06.2018 um 14:52 schrieb Daniel Vetter:

On Wed, Jun 20, 2018 at 2:46 PM, Christian König
 wrote:

[SNIP]

Go ahead, that's the point of commit rights. dim might complain if you
cherry picked them and didn't pick them up using dim apply though ...


I've fixed up the Link tags, but when I try "dim push-branch 
drm-misc-next"

I only get the error message "error: dst ref refs/heads/drm-misc-next
receives from more than one src."

Any idea what is going wrong here?

Sounds like multiple upstreams for your local drm-misc-next branch,
and git then can't decide which one to pick. If you delete the branch
and create it using dim checkout drm-misc-next this shouldn't happen.
We're trying to fit into existing check-outs and branches, but if you
set things up slightly different than dim would have you're off script
and there's limited support for that.

Alternative check out your .git/config and remove the other upstreams.
Or attach your git config if this isn't the issue (I'm just doing some
guessing here).


I've tried to delete my drm-misc-next branch and recreate it, but that 
doesn't seem to help.


Attached is my .git/config, but at least on first glance it looks ok 
as well.


Any ideas?


Ok that seems to be a bug in dim.

"bash -x dim push drm-misc-next" looks like it tries to push the branch 
drm-misc-next twice to the drm-misc remote: git push drm-misc 
drm-misc-next drm-misc-next


When I try that manually I get the same result, but "git push drm-misc 
drm-misc-next" just seemed to work fine.


Let's hope that I haven't messed things up totally on the server now.

Christian.



Thanks,
Christian.


-Daniel






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Re: [PATCH] drm/amd/display: Fix a loop timeout in wait_for_fbc_state_changed()

[Harry Wentland]

On 2018-06-20 08:05 AM, Dan Carpenter wrote:
> We changed this loop so now it loops 1000 times instead of 10.  We need
> to make the counter larger because a uint8_t can't go up to 1000 and
> we need to update the test at the end to test for 1000 instead of 10.
> 
> Fixes: 2b6199a1d1b7 ("drm/amd/display: replace msleep with udelay in fbc 
> path")
> Signed-off-by: Dan Carpenter 

Thanks for the patch. An equivalent one is already on-route to be merged: 
https://patchwork.freedesktop.org/patch/230412/

Harry

> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 
> b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
> index e2994d337044..8e83ec66fd22 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
> @@ -143,7 +143,7 @@ static void wait_for_fbc_state_changed(
>   struct dce110_compressor *cp110,
>   bool enabled)
>  {
> - uint8_t counter = 0;
> + int counter = 0;
>   uint32_t addr = mmFBC_STATUS;
>   uint32_t value;
>  
> @@ -158,7 +158,7 @@ static void wait_for_fbc_state_changed(
>   counter++;
>   }
>  
> - if (counter == 10) {
> + if (counter == 1000) {
>   DC_LOG_WARNING("%s: wait counter exceeded, changes to HW not 
> applied",
>   __func__);
>   } else {
> 
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Re: [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on power state change

[Deucher, Alexander]

With your proposed changes patch is:

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Quan, Evan 

Sent: Wednesday, June 20, 2018 2:17:57 AM
To: Alex Deucher
Cc: amd-gfx list
Subject: RE: [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on 
power state change

Hi Alex,

Comment inline.

> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Tuesday, June 19, 2018 11:17 PM
> To: Quan, Evan 
> Cc: amd-gfx list 
> Subject: Re: [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on
> power state change
>
> On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan  wrote:
> > The clocks hard/soft min/max clock levels will be adjusted
> > correspondingly.
>
>
> Also note that this add the apply_clocks_adjust_rules callback which is used
> to validate the clock settings on a power state change.  One other comment
> below.
Yes, this is for the apply_clocks_adjust_rules callback. I updated the patch 
description as below

drm/amd/powerplay: apply clocks adjust rules on power state change

This add the apply_clocks_adjust_rules callback which is used
to validate the clock settings on a power state change.
> >
> > Change-Id: I2c4b6cd6756d40a28933f0c26b9e1a3d5078bab8
> > Signed-off-by: Evan Quan 
> > ---
> >  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 162
> +
> >  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h |   2 +
> >  2 files changed, 164 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > index a227ace..26bdfff 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > @@ -1950,6 +1950,166 @@ static int vega12_print_clock_levels(struct
> pp_hwmgr *hwmgr,
> > return size;
> >  }
> >
> > +static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) {
> > +   struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr-
> >backend);
> > +   struct vega12_single_dpm_table *dpm_table;
> > +   bool vblank_too_short = false;
> > +   bool disable_mclk_switching;
> > +   uint32_t i, latency;
> > +
> > +   disable_mclk_switching = ((1 < hwmgr->display_config->num_display)
> &&
> > + 
> > !hwmgr->display_config->multi_monitor_in_sync) ||
> > + vblank_too_short;
> > +   latency =
> > + hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
> > +
> > +   /* gfxclk */
> > +   dpm_table = &(data->dpm_table.gfx_table);
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[dpm_table->count - 1].value;
> > +   dpm_table->dpm_state.hard_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.hard_max_level =
> > + dpm_table->dpm_levels[dpm_table->count - 1].value;
> > +
> > +   if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
> > +   if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
> > +   }
> > +
> > +   if (hwmgr->dpm_level ==
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[0].value;
> > +   }
> > +
> > +   if (hwmgr->dpm_level ==
> AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[dpm_table->count - 1].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[dpm_table->count - 1].value;
> > +   }
> > +   }
> > +
> > +   /* memclk */
> > +   dpm_table = &(data->dpm_table.mem_table);
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[dpm_table->count - 1].value;
> > +   dpm_table->dpm_state.hard_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.hard_max_level =
> > + dpm_table->dpm_levels[dpm_table->count - 1].value;
> > +
> > +   if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
> > +   if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
> > +   }
> > +

Re: [PATCH 2/5] dma-buf: remove kmap_atomic interface

[Christian König]

Am 20.06.2018 um 14:52 schrieb Daniel Vetter:

On Wed, Jun 20, 2018 at 2:46 PM, Christian König
 wrote:

[SNIP]

Go ahead, that's the point of commit rights. dim might complain if you
cherry picked them and didn't pick them up using dim apply though ...


I've fixed up the Link tags, but when I try "dim push-branch drm-misc-next"
I only get the error message "error: dst ref refs/heads/drm-misc-next
receives from more than one src."

Any idea what is going wrong here?

Sounds like multiple upstreams for your local drm-misc-next branch,
and git then can't decide which one to pick. If you delete the branch
and create it using dim checkout drm-misc-next this shouldn't happen.
We're trying to fit into existing check-outs and branches, but if you
set things up slightly different than dim would have you're off script
and there's limited support for that.

Alternative check out your .git/config and remove the other upstreams.
Or attach your git config if this isn't the issue (I'm just doing some
guessing here).


I've tried to delete my drm-misc-next branch and recreate it, but that 
doesn't seem to help.


Attached is my .git/config, but at least on first glance it looks ok as 
well.


Any ideas?

Thanks,
Christian.


-Daniel




[core]
repositoryformatversion = 0
filemode = true
bare = false
logallrefupdates = true
[remote "origin"]
url = git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
fetch = +refs/heads/*:refs/remotes/origin/*
[branch "master"]
remote = origin
merge = refs/heads/master
[remote "drm-tip"]
url = ssh://git.freedesktop.org/git/drm-tip
fetch = +refs/heads/*:refs/remotes/drm-tip/*
[branch "maintainer-tools"]
remote = drm-tip
merge = refs/heads/maintainer-tools
[branch "rerere-cache"]
remote = drm-tip
merge = refs/heads/rerere-cache
[branch "drm-tip"]
remote = drm-tip
merge = refs/heads/drm-tip
[remote "airlied"]
url = git://people.freedesktop.org/~airlied/linux
fetch = +refs/heads/*:refs/remotes/airlied/*
[remote "sound"]
url = git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git
fetch = +refs/heads/*:refs/remotes/sound/*
[remote "drm-intel"]
url = ssh://git.freedesktop.org/git/drm/drm-intel
fetch = +refs/heads/*:refs/remotes/drm-intel/*
[remote "drm-amd"]
url = ssh://git.freedesktop.org/git/drm/drm-amd
fetch = +refs/heads/*:refs/remotes/drm-amd/*
[remote "drm"]
url = ssh://git.freedesktop.org/git/drm/drm
fetch = +refs/heads/*:refs/remotes/drm/*
[remote "drm-misc"]
url = ssh://git.freedesktop.org/git/drm/drm-misc
fetch = +refs/heads/*:refs/remotes/drm-misc/*
[remote "baker"]
url = ssh://baker.local/usr/src/linux
fetch = +refs/heads/*:refs/remotes/baker/*
[branch "drm-misc-next"]
remote = drm-misc
merge = refs/heads/drm-misc-next
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Re: [PATCH 2/5] dma-buf: remove kmap_atomic interface

[Daniel Vetter]

On Wed, Jun 20, 2018 at 2:46 PM, Christian König
 wrote:
> Am 19.06.2018 um 17:35 schrieb Daniel Vetter:
>>
>> On Tue, Jun 19, 2018 at 4:47 PM, Christian König
>>  wrote:
>>>
>>> Am 18.06.2018 um 10:18 schrieb Daniel Vetter:

 On Fri, Jun 01, 2018 at 02:00:17PM +0200, Christian König wrote:
>
> Neither used nor correctly implemented anywhere. Just completely remove
> the interface.
>
> Signed-off-by: Christian König 

 I wonder whether we can nuke the normal kmap stuff too ... everyone
 seems
 to want/use the vmap stuff for kernel-internal mapping needs.

 Anyway, this looks good.
>
> ---
>drivers/dma-buf/dma-buf.c  | 44
> --
>drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c  |  2 -
>drivers/gpu/drm/armada/armada_gem.c|  2 -
>drivers/gpu/drm/drm_prime.c| 26
> -
>drivers/gpu/drm/i915/i915_gem_dmabuf.c | 11 --
>drivers/gpu/drm/i915/selftests/mock_dmabuf.c   |  2 -
>drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c  |  2 -
>drivers/gpu/drm/tegra/gem.c| 14 ---
>drivers/gpu/drm/udl/udl_dmabuf.c   | 17 -
>drivers/gpu/drm/vmwgfx/vmwgfx_prime.c  | 13 ---
>.../media/common/videobuf2/videobuf2-dma-contig.c  |  1 -
>drivers/media/common/videobuf2/videobuf2-dma-sg.c  |  1 -
>drivers/media/common/videobuf2/videobuf2-vmalloc.c |  1 -
>drivers/staging/android/ion/ion.c  |  2 -
>drivers/tee/tee_shm.c  |  6 ---
>include/drm/drm_prime.h|  4 --
>include/linux/dma-buf.h|  4 --
>17 files changed, 152 deletions(-)
>
> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
> index e99a8d19991b..e4c657d9fad7 100644
> --- a/drivers/dma-buf/dma-buf.c
> +++ b/drivers/dma-buf/dma-buf.c
> @@ -405,7 +405,6 @@ struct dma_buf *dma_buf_export(const struct
> dma_buf_export_info *exp_info)
>|| !exp_info->ops->map_dma_buf
>|| !exp_info->ops->unmap_dma_buf
>|| !exp_info->ops->release
> - || !exp_info->ops->map_atomic
>|| !exp_info->ops->map
>|| !exp_info->ops->mmap)) {
>  return ERR_PTR(-EINVAL);
> @@ -687,14 +686,6 @@ EXPORT_SYMBOL_GPL(dma_buf_unmap_attachment);
> *  void \*dma_buf_kmap(struct dma_buf \*, unsigned long);
> *  void dma_buf_kunmap(struct dma_buf \*, unsigned long, void
> \*);
> *
> - *   There are also atomic variants of these interfaces. Like for kmap
> they
> - *   facilitate non-blocking fast-paths. Neither the importer nor the
> exporter
> - *   (in the callback) is allowed to block when using these.
> - *
> - *   Interfaces::
> - *  void \*dma_buf_kmap_atomic(struct dma_buf \*, unsigned long);
> - *  void dma_buf_kunmap_atomic(struct dma_buf \*, unsigned long,
> void \*);
> - *
> *   For importers all the restrictions of using kmap apply, like
> the
> limited
> *   supply of kmap_atomic slots. Hence an importer shall only hold
> onto at
> *   max 2 atomic dma_buf kmaps at the same time (in any given
> process
> context).

 This is also about atomic kmap ...

 And the subsequent language around "Note that these calls need to always
 succeed." is also not true, might be good to update that stating that
 kmap
 is optional (like we say already for vmap).

 With those docs nits addressed:

 Reviewed-by: Daniel Vetter 
>>>
>>>
>>> I've fixed up patch #1 and #2 and added your Reviewed-by tag.
>>>
>>> Since I finally had time to install dim do you have any objections that I
>>> now run "dim push drm-misc-next" with those two applied?
>>
>> Go ahead, that's the point of commit rights. dim might complain if you
>> cherry picked them and didn't pick them up using dim apply though ...
>
>
> I've fixed up the Link tags, but when I try "dim push-branch drm-misc-next"
> I only get the error message "error: dst ref refs/heads/drm-misc-next
> receives from more than one src."
>
> Any idea what is going wrong here?

Sounds like multiple upstreams for your local drm-misc-next branch,
and git then can't decide which one to pick. If you delete the branch
and create it using dim checkout drm-misc-next this shouldn't happen.
We're trying to fit into existing check-outs and branches, but if you
set things up slightly different than dim would have you're off script
and there's limited support for that.

Alternative check out your 

Re: [PATCH 2/5] dma-buf: remove kmap_atomic interface

[Christian König]

Am 19.06.2018 um 17:35 schrieb Daniel Vetter:

On Tue, Jun 19, 2018 at 4:47 PM, Christian König
 wrote:

Am 18.06.2018 um 10:18 schrieb Daniel Vetter:

On Fri, Jun 01, 2018 at 02:00:17PM +0200, Christian König wrote:

Neither used nor correctly implemented anywhere. Just completely remove
the interface.

Signed-off-by: Christian König 

I wonder whether we can nuke the normal kmap stuff too ... everyone seems
to want/use the vmap stuff for kernel-internal mapping needs.

Anyway, this looks good.

---
   drivers/dma-buf/dma-buf.c  | 44
--
   drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c  |  2 -
   drivers/gpu/drm/armada/armada_gem.c|  2 -
   drivers/gpu/drm/drm_prime.c| 26 -
   drivers/gpu/drm/i915/i915_gem_dmabuf.c | 11 --
   drivers/gpu/drm/i915/selftests/mock_dmabuf.c   |  2 -
   drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c  |  2 -
   drivers/gpu/drm/tegra/gem.c| 14 ---
   drivers/gpu/drm/udl/udl_dmabuf.c   | 17 -
   drivers/gpu/drm/vmwgfx/vmwgfx_prime.c  | 13 ---
   .../media/common/videobuf2/videobuf2-dma-contig.c  |  1 -
   drivers/media/common/videobuf2/videobuf2-dma-sg.c  |  1 -
   drivers/media/common/videobuf2/videobuf2-vmalloc.c |  1 -
   drivers/staging/android/ion/ion.c  |  2 -
   drivers/tee/tee_shm.c  |  6 ---
   include/drm/drm_prime.h|  4 --
   include/linux/dma-buf.h|  4 --
   17 files changed, 152 deletions(-)

diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index e99a8d19991b..e4c657d9fad7 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -405,7 +405,6 @@ struct dma_buf *dma_buf_export(const struct
dma_buf_export_info *exp_info)
   || !exp_info->ops->map_dma_buf
   || !exp_info->ops->unmap_dma_buf
   || !exp_info->ops->release
- || !exp_info->ops->map_atomic
   || !exp_info->ops->map
   || !exp_info->ops->mmap)) {
 return ERR_PTR(-EINVAL);
@@ -687,14 +686,6 @@ EXPORT_SYMBOL_GPL(dma_buf_unmap_attachment);
*  void \*dma_buf_kmap(struct dma_buf \*, unsigned long);
*  void dma_buf_kunmap(struct dma_buf \*, unsigned long, void \*);
*
- *   There are also atomic variants of these interfaces. Like for kmap
they
- *   facilitate non-blocking fast-paths. Neither the importer nor the
exporter
- *   (in the callback) is allowed to block when using these.
- *
- *   Interfaces::
- *  void \*dma_buf_kmap_atomic(struct dma_buf \*, unsigned long);
- *  void dma_buf_kunmap_atomic(struct dma_buf \*, unsigned long,
void \*);
- *
*   For importers all the restrictions of using kmap apply, like the
limited
*   supply of kmap_atomic slots. Hence an importer shall only hold
onto at
*   max 2 atomic dma_buf kmaps at the same time (in any given process
context).

This is also about atomic kmap ...

And the subsequent language around "Note that these calls need to always
succeed." is also not true, might be good to update that stating that kmap
is optional (like we say already for vmap).

With those docs nits addressed:

Reviewed-by: Daniel Vetter 


I've fixed up patch #1 and #2 and added your Reviewed-by tag.

Since I finally had time to install dim do you have any objections that I
now run "dim push drm-misc-next" with those two applied?

Go ahead, that's the point of commit rights. dim might complain if you
cherry picked them and didn't pick them up using dim apply though ...


I've fixed up the Link tags, but when I try "dim push-branch 
drm-misc-next" I only get the error message "error: dst ref 
refs/heads/drm-misc-next receives from more than one src."


Any idea what is going wrong here?

Christian.


-Daniel



Regards,
Christian.



@@ -859,41 +850,6 @@ int dma_buf_end_cpu_access(struct dma_buf *dmabuf,
   }
   EXPORT_SYMBOL_GPL(dma_buf_end_cpu_access);
   -/**
- * dma_buf_kmap_atomic - Map a page of the buffer object into kernel
address
- * space. The same restrictions as for kmap_atomic and friends apply.
- * @dmabuf:[in]buffer to map page from.
- * @page_num:  [in]page in PAGE_SIZE units to map.
- *
- * This call must always succeed, any necessary preparations that might
fail
- * need to be done in begin_cpu_access.
- */
-void *dma_buf_kmap_atomic(struct dma_buf *dmabuf, unsigned long
page_num)
-{
-   WARN_ON(!dmabuf);
-
-   return dmabuf->ops->map_atomic(dmabuf, page_num);
-}
-EXPORT_SYMBOL_GPL(dma_buf_kmap_atomic);
-
-/**
- * dma_buf_kunmap_atomic - Unmap a page obtained by dma_buf_kmap_atomic.
- * @dmabuf:[in]buffer to unmap page from.
- * @page_num:  [in]page in PAGE_SIZE units to unmap.
- * @vaddr: [in]kernel space pointer 

[PATCH] drm/amd/amdgpu: Add a GPU_LOAD entry to sysfs

[Tom St Denis]

This adds what should be a stable interface to read GPU
load from userspace.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 41 ++
 1 file changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 113edffb5960..d57b414ac228 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -918,6 +918,37 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
device *dev,
return -EINVAL;
 }
 
+static ssize_t amdgpu_get_busy_level(struct device *dev,
+   struct device_attribute *attr,
+   char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   int r, value, size = sizeof(value);
+
+   /* sanity check PP is enabled */
+   if (!(adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->read_sensor))
+   return -EINVAL;
+
+   /* get the temperature */
+   r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
+  (void *), );
+   if (r)
+   return r;
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", value);
+}
+
+static ssize_t amdgpu_set_gpu_busy_level(struct device *dev,
+   struct device_attribute *attr,
+   const char *buf,
+   size_t count)
+{
+   return -EINVAL;
+}
+
+
 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
   amdgpu_get_dpm_forced_performance_level,
@@ -951,6 +982,8 @@ static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
amdgpu_get_pp_od_clk_voltage,
amdgpu_set_pp_od_clk_voltage);
+static DEVICE_ATTR(gpu_busy_level, S_IRUGO | S_IWUSR,
+   amdgpu_get_busy_level, amdgpu_set_gpu_busy_level);
 
 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
  struct device_attribute *attr,
@@ -1854,6 +1887,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
"pp_od_clk_voltage\n");
return ret;
}
+   ret = device_create_file(adev->dev,
+   _attr_gpu_busy_level);
+   if (ret) {
+   DRM_ERROR("failed to create device file "
+   "gpu_busy_level\n");
+   return ret;
+   }
ret = amdgpu_debugfs_pm_init(adev);
if (ret) {
DRM_ERROR("Failed to register debugfs file for dpm!\n");
@@ -1889,6 +1929,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
_attr_pp_power_profile_mode);
device_remove_file(adev->dev,
_attr_pp_od_clk_voltage);
+   device_remove_file(adev->dev, _attr_gpu_busy_level);
 }
 
 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
-- 
2.14.4

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[PATCH] drm/amd/display: Fix a loop timeout in wait_for_fbc_state_changed()

[Dan Carpenter]

We changed this loop so now it loops 1000 times instead of 10.  We need
to make the counter larger because a uint8_t can't go up to 1000 and
we need to update the test at the end to test for 1000 instead of 10.

Fixes: 2b6199a1d1b7 ("drm/amd/display: replace msleep with udelay in fbc path")
Signed-off-by: Dan Carpenter 

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index e2994d337044..8e83ec66fd22 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -143,7 +143,7 @@ static void wait_for_fbc_state_changed(
struct dce110_compressor *cp110,
bool enabled)
 {
-   uint8_t counter = 0;
+   int counter = 0;
uint32_t addr = mmFBC_STATUS;
uint32_t value;
 
@@ -158,7 +158,7 @@ static void wait_for_fbc_state_changed(
counter++;
}
 
-   if (counter == 10) {
+   if (counter == 1000) {
DC_LOG_WARNING("%s: wait counter exceeded, changes to HW not 
applied",
__func__);
} else {
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RE: [PATCH 2/2] drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH.

[Grodzovsky, Andrey]

> -Original Message-
> From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
> Sent: Wednesday, June 20, 2018 2:37 AM
> To: Grodzovsky, Andrey ; amd-
> g...@lists.freedesktop.org
> Cc: Panariti, David ; Haehnle, Nicolai
> 
> Subject: Re: [PATCH 2/2] drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH.
> 
> Am 19.06.2018 um 18:09 schrieb Andrey Grodzovsky:
> > Access to SQ_EDC_INFO requires selecting register instance and hence
> > mutex lock when accessing GRBM_GFX_INDEX for which a work is
> > schedueled from IH. But SQ interrupt can be raised on many instances
> > at once which means queuing work will usually succeed for the first
> > one but fail for the reset since the work takes time to process. To
> > avoid losing info about other interrupt instances call the parsing
> > function directly from high IRQ when current work hasn't finished and
> > avoid accessing SQ_EDC_INFO in that case.
> >
> > Signed-off-by: Andrey Grodzovsky 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  7 +++
> >   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 97
> ++-
> >   2 files changed, 91 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index e8c6cc1..a7b9ef5 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -930,6 +930,11 @@ struct amdgpu_ngg {
> > boolinit;
> >   };
> >
> > +struct sq_work {
> > +   struct work_struct  work;
> > +   unsigned ih_data;
> > +};
> > +
> >   struct amdgpu_gfx {
> > struct mutexgpu_clock_mutex;
> > struct amdgpu_gfx_configconfig;
> > @@ -970,6 +975,8 @@ struct amdgpu_gfx {
> > struct amdgpu_irq_src   priv_inst_irq;
> > struct amdgpu_irq_src   cp_ecc_error_irq;
> > struct amdgpu_irq_src   sq_irq;
> > +   struct sq_work  sq_work;
> > +
> > /* gfx status */
> > uint32_tgfx_current_status;
> > /* ce ram size*/
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > index 93904a7..0add7fc 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > @@ -704,6 +704,17 @@ static const u32 stoney_mgcg_cgcg_init[] =
> > mmCGTS_SM_CTRL_REG, 0x, 0x96940200,
> >   };
> >
> > +
> > +static const char * const sq_edc_source_names[] = {
> > +   "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
> > +   "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
> > +   "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data
> return",
> > +   "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
> > +   "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
> > +   "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
> > +   "SQ_EDC_INFO_SOURCE_TA: EDC source is TA", };
> > +
> >   static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
> >   static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
> >   static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); @@
> > -2003,6 +2014,8 @@ static int gfx_v8_0_compute_ring_init(struct
> amdgpu_device *adev, int ring_id,
> > return 0;
> >   }
> >
> > +static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
> > +
> >   static int gfx_v8_0_sw_init(void *handle)
> >   {
> > int i, j, k, r, ring_id;
> > @@ -2066,6 +2079,8 @@ static int gfx_v8_0_sw_init(void *handle)
> > return r;
> > }
> >
> > +   INIT_WORK(>gfx.sq_work.work,
> gfx_v8_0_sq_irq_work_func);
> > +
> > adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
> >
> > gfx_v8_0_scratch_init(adev);
> > @@ -6952,14 +6967,11 @@ static int gfx_v8_0_cp_ecc_error_irq(struct
> amdgpu_device *adev,
> > return 0;
> >   }
> >
> > -static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
> > -  struct amdgpu_irq_src *source,
> > -  struct amdgpu_iv_entry *entry)
> > +static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev,
> > +unsigned ih_data)
> >   {
> > -   u8 enc, se_id;
> > +   u32 enc, se_id, sh_id, cu_id;
> > char type[20];
> > -   unsigned ih_data = entry->src_data[0];
> > -
> > +   int sq_edc_source = -1;
> >
> > enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN,
> ENCODING);
> > se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN,
> SE_ID); @@
> > -6985,6 +6997,24 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device
> *adev,
> > case 1:
> > case 2:
> >
> > +   cu_id = REG_GET_FIELD(ih_data,
> SQ_INTERRUPT_WORD_WAVE, CU_ID);
> > +   sh_id = REG_GET_FIELD(ih_data,
> SQ_INTERRUPT_WORD_WAVE, SH_ID);
> > +
> > +   /*
> > +* This function can be called either directly from ISR
> > +* or from BH in which case we can access
> SQ_EDC_INFO
> > +* instance

[PATCH] drm/amd/display: Missed to set some display requests to powerplay

[Rex Zhu]

Missed to set some clock requests and display info which were needed
by powerplay.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 329cf3a..f348c6f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -77,6 +77,7 @@ bool dm_pp_apply_display_requirements(
const struct dm_pp_display_configuration *pp_display_cfg)
 {
struct amdgpu_device *adev = ctx->driver_context;
+   int i;
 
if (adev->pm.dpm_enabled) {
 
@@ -107,6 +108,9 @@ bool dm_pp_apply_display_requirements(
adev->pm.pm_display_cfg.min_mem_set_clock =
pp_display_cfg->min_memory_clock_khz/10;
 
+   adev->pm.pm_display_cfg.min_dcef_deep_sleep_set_clk = 
pp_display_cfg->min_engine_clock_deep_sleep_khz / 10;
+   adev->pm.pm_display_cfg.min_dcef_set_clk = 
pp_display_cfg->min_dcfclock_khz / 10;
+
adev->pm.pm_display_cfg.multi_monitor_in_sync =
pp_display_cfg->all_displays_in_sync;
adev->pm.pm_display_cfg.min_vblank_time =
@@ -126,6 +130,11 @@ bool dm_pp_apply_display_requirements(
adev->pm.pm_display_cfg.crossfire_display_index = -1;
adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
 
+   for (i = 0; i < pp_display_cfg->display_count; i++) {
+   const struct dm_pp_single_disp_config *dc_cfg =
+   
_display_cfg->disp_configs[i];
+   adev->pm.pm_display_cfg.displays[i].controller_id = 
dc_cfg->pipe_idx + 1;
+   }
/* TODO: complete implementation of
 * pp_display_configuration_change().
 * Follow example of:
-- 
1.9.1

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[PATCH v2 2/2] drm/amd/pp: Unify the shared struct between pp and display

[Rex Zhu]

v2: not change the header file dm_service_types.h, as it was
shared with other Os. PP need to include this header file and
remove same data struct defines.

1. move shared struct dm_pp_wm_sets_with_clock_ranges_soc15 to
   dm_pp_interface.h.
2. delete the same struct define in powerplay, use the struct
   display defined.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/include/dm_pp_interface.h  | 37 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c   | 28 
 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h   |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c |  2 +-
 6 files changed, 20 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h 
b/drivers/gpu/drm/amd/include/dm_pp_interface.h
index 7852952..1d93a0c 100644
--- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -23,6 +23,8 @@
 #ifndef _DM_PP_INTERFACE_
 #define _DM_PP_INTERFACE_
 
+#include "dm_services_types.h"
+
 #define PP_MAX_CLOCK_LEVELS 16
 
 enum amd_pp_display_config_type{
@@ -189,39 +191,4 @@ struct pp_display_clock_request {
uint32_t clock_freq_in_khz;
 };
 
-#define PP_MAX_WM_SETS 4
-
-enum pp_wm_set_id {
-   DC_WM_SET_A = 0,
-   DC_WM_SET_B,
-   DC_WM_SET_C,
-   DC_WM_SET_D,
-   DC_WM_SET_INVALID = 0x,
-};
-
-struct pp_wm_set_with_dmif_clock_range_soc15 {
-   enum pp_wm_set_id wm_set_id;
-   uint32_t wm_min_dcefclk_in_khz;
-   uint32_t wm_max_dcefclk_in_khz;
-   uint32_t wm_min_memclk_in_khz;
-   uint32_t wm_max_memclk_in_khz;
-};
-
-struct pp_wm_set_with_mcif_clock_range_soc15 {
-   enum pp_wm_set_id wm_set_id;
-   uint32_t wm_min_socclk_in_khz;
-   uint32_t wm_max_socclk_in_khz;
-   uint32_t wm_min_memclk_in_khz;
-   uint32_t wm_max_memclk_in_khz;
-};
-
-struct pp_wm_sets_with_clock_ranges_soc15 {
-   uint32_t num_wm_sets_dmif;
-   uint32_t num_wm_sets_mcif;
-   struct pp_wm_set_with_dmif_clock_range_soc15
-   wm_sets_dmif[PP_MAX_WM_SETS];
-   struct pp_wm_set_with_mcif_clock_range_soc15
-   wm_sets_mcif[PP_MAX_WM_SETS];
-};
-
 #endif /* _DM_PP_INTERFACE_ */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 4ca8033..48ae990 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1134,7 +1134,7 @@ static int smu10_set_watermarks_for_clocks_ranges(struct 
pp_hwmgr *hwmgr,
void *clock_ranges)
 {
struct smu10_hwmgr *data = hwmgr->backend;
-   struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = 
clock_ranges;
+   struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = 
clock_ranges;
Watermarks_t *table = &(data->water_marks_table);
int result = 0;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
index 93a3d02..5dd375d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -652,7 +652,7 @@ int smu_get_voltage_dependency_table_ppt_v1(
 }
 
 int smu_set_watermarks_for_clocks_ranges(void *wt_table,
-   struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
+   struct dm_pp_wm_sets_with_clock_ranges_soc15 
*wm_with_clock_ranges)
 {
uint32_t i;
struct watermarks *table = wt_table;
@@ -660,49 +660,49 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
if (!table || !wm_with_clock_ranges)
return -EINVAL;
 
-   if (wm_with_clock_ranges->num_wm_sets_dmif > 4 || 
wm_with_clock_ranges->num_wm_sets_mcif > 4)
+   if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || 
wm_with_clock_ranges->num_wm_mcif_sets > 4)
return -EINVAL;
 
-   for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
+   for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
table->WatermarkRow[1][i].MinClock =
cpu_to_le16((uint16_t)
-   
(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
+   
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
100);
table->WatermarkRow[1][i].MaxClock =
cpu_to_le16((uint16_t)
-   
(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
+   
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
100);
table->WatermarkRow[1][i].MinUclk =
cpu_to_le16((uint16_t)
-   

[PATCH] drm/amd/powerplay: initialize uvd/vce powergate status v3

[Evan Quan]

On UVD/VCE dpm enabled/disabled, the powergate status will be
set as false/true. So that we will not try to ungate/gate them(
enable/disable their dpm) again.

v2: added check for uvd/vce powergate status before gating
v3: fix typo in description

Change-Id: I569a5aa216b5e7d64a2b504f2ff98cc83ca802d5
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 23 ++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 45c8f2d..28b172e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -777,6 +777,21 @@ static int vega12_set_allowed_featuresmask(struct pp_hwmgr 
*hwmgr)
return 0;
 }
 
+static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
+{
+   struct vega12_hwmgr *data =
+   (struct vega12_hwmgr *)(hwmgr->backend);
+
+   data->uvd_power_gated = true;
+   data->vce_power_gated = true;
+
+   if (data->smu_features[GNLD_DPM_UVD].enabled)
+   data->uvd_power_gated = false;
+
+   if (data->smu_features[GNLD_DPM_VCE].enabled)
+   data->vce_power_gated = false;
+}
+
 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 {
struct vega12_hwmgr *data =
@@ -801,6 +816,8 @@ static int vega12_enable_all_smu_features(struct pp_hwmgr 
*hwmgr)
}
}
 
+   vega12_init_powergate_state(hwmgr);
+
return 0;
 }
 
@@ -1985,6 +2002,9 @@ static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, 
bool bgate)
 {
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 
+   if (data->vce_power_gated == bgate)
+   return 0;
+
data->vce_power_gated = bgate;
vega12_enable_disable_vce_dpm(hwmgr, !bgate);
 }
@@ -1993,6 +2013,9 @@ static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, 
bool bgate)
 {
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 
+   if (data->uvd_power_gated == bgate)
+   return 0;
+
data->uvd_power_gated = bgate;
vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
 }
-- 
2.7.4

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RE: [PATCH] drm/amd/powerplay: initialize uvd/vce powergate status v2

[Quan, Evan]

> that we will not try to gate them(enable dpm for now).
Sorry, there seems a typo in the description(enable -> disable).
I will send out another patch with this typo addressed.

Regards,
Evan
> -Original Message-
> From: Evan Quan [mailto:evan.q...@amd.com]
> Sent: Wednesday, June 20, 2018 2:09 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan 
> Subject: [PATCH] drm/amd/powerplay: initialize uvd/vce powergate status
> v2
> 
> On UVD/VCE dpm disabled, the powergate status should be set as true. So
> that we will not try to gate them(enable dpm for now).
> 
> v2: added check for uvd/vce powergate status before gating
> 
> Change-Id: I569a5aa216b5e7d64a2b504f2ff98cc83ca802d5
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 23
> ++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 45c8f2d..28b172e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -777,6 +777,21 @@ static int vega12_set_allowed_featuresmask(struct
> pp_hwmgr *hwmgr)
>   return 0;
>  }
> 
> +static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr) {
> + struct vega12_hwmgr *data =
> + (struct vega12_hwmgr *)(hwmgr->backend);
> +
> + data->uvd_power_gated = true;
> + data->vce_power_gated = true;
> +
> + if (data->smu_features[GNLD_DPM_UVD].enabled)
> + data->uvd_power_gated = false;
> +
> + if (data->smu_features[GNLD_DPM_VCE].enabled)
> + data->vce_power_gated = false;
> +}
> +
>  static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)  {
>   struct vega12_hwmgr *data =
> @@ -801,6 +816,8 @@ static int vega12_enable_all_smu_features(struct
> pp_hwmgr *hwmgr)
>   }
>   }
> 
> + vega12_init_powergate_state(hwmgr);
> +
>   return 0;
>  }
> 
> @@ -1985,6 +2002,9 @@ static void vega12_power_gate_vce(struct
> pp_hwmgr *hwmgr, bool bgate)  {
>   struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr-
> >backend);
> 
> + if (data->vce_power_gated == bgate)
> + return 0;
> +
>   data->vce_power_gated = bgate;
>   vega12_enable_disable_vce_dpm(hwmgr, !bgate);  } @@ -1993,6
> +2013,9 @@ static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr,
> bool bgate)  {
>   struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr-
> >backend);
> 
> + if (data->uvd_power_gated == bgate)
> + return 0;
> +
>   data->uvd_power_gated = bgate;
>   vega12_enable_disable_uvd_dpm(hwmgr, !bgate);  }
> --
> 2.7.4

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Re: [PATCH 2/2] drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH.

[Christian König]

Am 19.06.2018 um 18:09 schrieb Andrey Grodzovsky:

Access to SQ_EDC_INFO requires selecting register instance and
hence mutex lock when accessing GRBM_GFX_INDEX for which a work
is schedueled from IH. But SQ interrupt can be raised on many instances
at once which means queuing work will usually succeed for the first one
but fail for the reset since the work takes time to process. To avoid
losing info about other interrupt instances call the parsing function
directly from high IRQ when current work hasn't finished and avoid
accessing SQ_EDC_INFO in that case.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  7 +++
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 97 ++-
  2 files changed, 91 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e8c6cc1..a7b9ef5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -930,6 +930,11 @@ struct amdgpu_ngg {
boolinit;
  };
  
+struct sq_work {

+   struct work_struct  work;
+   unsigned ih_data;
+};
+
  struct amdgpu_gfx {
struct mutexgpu_clock_mutex;
struct amdgpu_gfx_configconfig;
@@ -970,6 +975,8 @@ struct amdgpu_gfx {
struct amdgpu_irq_src   priv_inst_irq;
struct amdgpu_irq_src   cp_ecc_error_irq;
struct amdgpu_irq_src   sq_irq;
+   struct sq_work  sq_work;
+
/* gfx status */
uint32_tgfx_current_status;
/* ce ram size*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 93904a7..0add7fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -704,6 +704,17 @@ static const u32 stoney_mgcg_cgcg_init[] =
mmCGTS_SM_CTRL_REG, 0x, 0x96940200,
  };
  
+

+static const char * const sq_edc_source_names[] = {
+   "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
+   "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
+   "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
+   "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
+   "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
+   "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
+   "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
+};
+
  static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
  static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
@@ -2003,6 +2014,8 @@ static int gfx_v8_0_compute_ring_init(struct 
amdgpu_device *adev, int ring_id,
return 0;
  }
  
+static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);

+
  static int gfx_v8_0_sw_init(void *handle)
  {
int i, j, k, r, ring_id;
@@ -2066,6 +2079,8 @@ static int gfx_v8_0_sw_init(void *handle)
return r;
}
  
+	INIT_WORK(>gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);

+
adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
  
  	gfx_v8_0_scratch_init(adev);

@@ -6952,14 +6967,11 @@ static int gfx_v8_0_cp_ecc_error_irq(struct 
amdgpu_device *adev,
return 0;
  }
  
-static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,

-  struct amdgpu_irq_src *source,
-  struct amdgpu_iv_entry *entry)
+static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data)
  {
-   u8 enc, se_id;
+   u32 enc, se_id, sh_id, cu_id;
char type[20];
-   unsigned ih_data = entry->src_data[0];
-
+   int sq_edc_source = -1;
  
  	enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);

se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
@@ -6985,6 +6997,24 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
case 1:
case 2:
  
+			cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);

+   sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, 
SH_ID);
+
+   /*
+* This function can be called either directly from ISR
+* or from BH in which case we can access SQ_EDC_INFO
+* instance
+*/
+   if (in_task()) {
+   mutex_lock(>grbm_idx_mutex);
+   gfx_v8_0_select_se_sh(adev, se_id, sh_id, 
cu_id);
+
+   sq_edc_source = 
REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
+
+   gfx_v8_0_select_se_sh(adev, 0x, 
0x, 0x);
+   mutex_unlock(>grbm_idx_mutex);
+   }
+
if (enc == 1)
sprintf(type, 

RE: [PATCH 07/13] drm/amd/powerplay: initialize uvd/vce powergate status

[Quan, Evan]

Hi Alex,

Just sent out a v2 version for this patch.

On UVD/VCE dpm disabled, the powergate status will be set as true. 
So that we will not try to gate them(disable their dpm again).

Regards,
Evan
> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Tuesday, June 19, 2018 11:10 PM
> To: Quan, Evan 
> Cc: amd-gfx list 
> Subject: Re: [PATCH 07/13] drm/amd/powerplay: initialize uvd/vce
> powergate status
> 
> On Tue, Jun 19, 2018 at 3:38 AM, Evan Quan  wrote:
> > On UVD/VCE dpm disabled, the powergate status should be set as true.
> 
> Can you explain this patch a bit?  Why is power gate state set to true when
> dpm is disabled?
> 
> Alex
> 
> >
> > Change-Id: I569a5aa216b5e7d64a2b504f2ff98cc83ca802d5
> > Signed-off-by: Evan Quan 
> > ---
> >  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 17
> > +
> >  1 file changed, 17 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > index a124b81..cb0589e 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > @@ -777,6 +777,21 @@ static int
> vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
> > return 0;
> >  }
> >
> > +static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr) {
> > +   struct vega12_hwmgr *data =
> > +   (struct vega12_hwmgr *)(hwmgr->backend);
> > +
> > +   data->uvd_power_gated = true;
> > +   data->vce_power_gated = true;
> > +
> > +   if (data->smu_features[GNLD_DPM_UVD].enabled)
> > +   data->uvd_power_gated = false;
> > +
> > +   if (data->smu_features[GNLD_DPM_VCE].enabled)
> > +   data->vce_power_gated = false; }
> > +
> >  static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)  {
> > struct vega12_hwmgr *data =
> > @@ -801,6 +816,8 @@ static int vega12_enable_all_smu_features(struct
> pp_hwmgr *hwmgr)
> > }
> > }
> >
> > +   vega12_init_powergate_state(hwmgr);
> > +
> > return 0;
> >  }
> >
> > --
> > 2.7.4
> >
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Re: [PATCH 2/5] dma-buf: remove kmap_atomic interface

[Christian König]

Am 20.06.2018 um 08:10 schrieb Sumit Semwal:

Hi Christian,
On Tue, 19 Jun 2018 at 20:17, Christian König  wrote:

Am 18.06.2018 um 10:18 schrieb Daniel Vetter:

On Fri, Jun 01, 2018 at 02:00:17PM +0200, Christian König wrote:

Neither used nor correctly implemented anywhere. Just completely remove
the interface.

Signed-off-by: Christian König 

I wonder whether we can nuke the normal kmap stuff too ... everyone seems
to want/use the vmap stuff for kernel-internal mapping needs.

Anyway, this looks good.

Hope am not too late (was out of office for some time) - this looks ok
to me, please feel free to add my
Acked-by: Sumit Semwal 


No, you're not to late. I was actually holding back a bit because of 
missing Ack's.


Thanks for the response,
Christian.




---
   drivers/dma-buf/dma-buf.c  | 44 
--
   drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c  |  2 -
   drivers/gpu/drm/armada/armada_gem.c|  2 -
   drivers/gpu/drm/drm_prime.c| 26 -
   drivers/gpu/drm/i915/i915_gem_dmabuf.c | 11 --
   drivers/gpu/drm/i915/selftests/mock_dmabuf.c   |  2 -
   drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c  |  2 -
   drivers/gpu/drm/tegra/gem.c| 14 ---
   drivers/gpu/drm/udl/udl_dmabuf.c   | 17 -
   drivers/gpu/drm/vmwgfx/vmwgfx_prime.c  | 13 ---
   .../media/common/videobuf2/videobuf2-dma-contig.c  |  1 -
   drivers/media/common/videobuf2/videobuf2-dma-sg.c  |  1 -
   drivers/media/common/videobuf2/videobuf2-vmalloc.c |  1 -
   drivers/staging/android/ion/ion.c  |  2 -
   drivers/tee/tee_shm.c  |  6 ---
   include/drm/drm_prime.h|  4 --
   include/linux/dma-buf.h|  4 --
   17 files changed, 152 deletions(-)

diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index e99a8d19991b..e4c657d9fad7 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -405,7 +405,6 @@ struct dma_buf *dma_buf_export(const struct 
dma_buf_export_info *exp_info)
|| !exp_info->ops->map_dma_buf
|| !exp_info->ops->unmap_dma_buf
|| !exp_info->ops->release
-  || !exp_info->ops->map_atomic
|| !exp_info->ops->map
|| !exp_info->ops->mmap)) {
  return ERR_PTR(-EINVAL);
@@ -687,14 +686,6 @@ EXPORT_SYMBOL_GPL(dma_buf_unmap_attachment);
*  void \*dma_buf_kmap(struct dma_buf \*, unsigned long);
*  void dma_buf_kunmap(struct dma_buf \*, unsigned long, void \*);
*
- *   There are also atomic variants of these interfaces. Like for kmap they
- *   facilitate non-blocking fast-paths. Neither the importer nor the exporter
- *   (in the callback) is allowed to block when using these.
- *
- *   Interfaces::
- *  void \*dma_buf_kmap_atomic(struct dma_buf \*, unsigned long);
- *  void dma_buf_kunmap_atomic(struct dma_buf \*, unsigned long, void \*);
- *
*   For importers all the restrictions of using kmap apply, like the limited
*   supply of kmap_atomic slots. Hence an importer shall only hold onto at
*   max 2 atomic dma_buf kmaps at the same time (in any given process 
context).

This is also about atomic kmap ...

And the subsequent language around "Note that these calls need to always
succeed." is also not true, might be good to update that stating that kmap
is optional (like we say already for vmap).

With those docs nits addressed:

Reviewed-by: Daniel Vetter 

I've fixed up patch #1 and #2 and added your Reviewed-by tag.

Since I finally had time to install dim do you have any objections that
I now run "dim push drm-misc-next" with those two applied?

Regards,
Christian.


@@ -859,41 +850,6 @@ int dma_buf_end_cpu_access(struct dma_buf *dmabuf,
   }
   EXPORT_SYMBOL_GPL(dma_buf_end_cpu_access);

-/**
- * dma_buf_kmap_atomic - Map a page of the buffer object into kernel address
- * space. The same restrictions as for kmap_atomic and friends apply.
- * @dmabuf: [in]buffer to map page from.
- * @page_num:   [in]page in PAGE_SIZE units to map.
- *
- * This call must always succeed, any necessary preparations that might fail
- * need to be done in begin_cpu_access.
- */
-void *dma_buf_kmap_atomic(struct dma_buf *dmabuf, unsigned long page_num)
-{
-WARN_ON(!dmabuf);
-
-return dmabuf->ops->map_atomic(dmabuf, page_num);
-}
-EXPORT_SYMBOL_GPL(dma_buf_kmap_atomic);
-
-/**
- * dma_buf_kunmap_atomic - Unmap a page obtained by dma_buf_kmap_atomic.
- * @dmabuf: [in]buffer to unmap page from.
- * @page_num:   [in]page in PAGE_SIZE units to unmap.
- * @vaddr:  [in]kernel space pointer obtained from dma_buf_kmap_atomic.
- *
- * This call must always succeed.
- */
-void dma_buf_kunmap_atomic(struct dma_buf *dmabuf, unsigned long 

RE: [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on power state change

[Quan, Evan]

Hi Rex,

Yes, per discussed, we may need another patch to consider how to set the 
PHM_PlatformCaps_UMDPState flag.
But for now, I will keep the patch as it is.

Regards,
Evan
From: Zhu, Rex
Sent: Tuesday, June 19, 2018 11:43 PM
To: Quan, Evan ; Alex Deucher 
Cc: amd-gfx list 
Subject: Re: [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on 
power state change

Hi Evan,
did we need to check the following flags on vega12？will driver set those flags 
when user select the umd_pstate?
PHM_PlatformCaps_UMDPState/PHM_PlatformCaps_PState.
Best Regards
Rex

获取 Outlook for Android


From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Alex Deucher mailto:alexdeuc...@gmail.com>>
Sent: Tuesday, June 19, 2018 11:16:44 PM
To: Quan, Evan
Cc: amd-gfx list
Subject: Re: [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on 
power state change

On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan 
mailto:evan.q...@amd.com>> wrote:
> The clocks hard/soft min/max clock levels will be adjusted
> correspondingly.


Also note that this add the apply_clocks_adjust_rules callback which
is used to validate the clock settings on a power state change.  One
other comment below.

>
> Change-Id: I2c4b6cd6756d40a28933f0c26b9e1a3d5078bab8
> Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 162 
> +
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h |   2 +
>  2 files changed, 164 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index a227ace..26bdfff 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1950,6 +1950,166 @@ static int vega12_print_clock_levels(struct pp_hwmgr 
> *hwmgr,
> return size;
>  }
>
> +static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
> +{
> +   struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
> +   struct vega12_single_dpm_table *dpm_table;
> +   bool vblank_too_short = false;
> +   bool disable_mclk_switching;
> +   uint32_t i, latency;
> +
> +   disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
> + 
> !hwmgr->display_config->multi_monitor_in_sync) ||
> + vblank_too_short;
> +   latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
> +
> +   /* gfxclk */
> +   dpm_table = &(data->dpm_table.gfx_table);
> +   dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
> +   dpm_table->dpm_state.soft_max_level = 
> dpm_table->dpm_levels[dpm_table->count - 1].value;
> +   dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
> +   dpm_table->dpm_state.hard_max_level = 
> dpm_table->dpm_levels[dpm_table->count - 1].value;
> +
> +   if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
> +   if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
> +   dpm_table->dpm_state.soft_min_level = 
> dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
> +   dpm_table->dpm_state.soft_max_level = 
> dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
> +   }
> +
> +   if (hwmgr->dpm_level == 
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
> +   dpm_table->dpm_state.soft_min_level = 
> dpm_table->dpm_levels[0].value;
> +   dpm_table->dpm_state.soft_max_level = 
> dpm_table->dpm_levels[0].value;
> +   }
> +
> +   if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
> +   dpm_table->dpm_state.soft_min_level = 
> dpm_table->dpm_levels[dpm_table->count - 1].value;
> +   dpm_table->dpm_state.soft_max_level = 
> dpm_table->dpm_levels[dpm_table->count - 1].value;
> +   }
> +   }
> +
> +   /* memclk */
> +   dpm_table = &(data->dpm_table.mem_table);
> +   dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
> +   dpm_table->dpm_state.soft_max_level = 
> dpm_table->dpm_levels[dpm_table->count - 1].value;
> +   dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
> +   dpm_table->dpm_state.hard_max_level = 
> dpm_table->dpm_levels[dpm_table->count - 1].value;
> +
> +   if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
> +   if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
> +   dpm_table->dpm_state.soft_min_level = 
> dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
> +   dpm_table->dpm_state.soft_max_level = 
> dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
> +   }
> +
> +   if (hwmgr->dpm_level == 
> 

RE: [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on power state change

[Quan, Evan]

Hi Alex,

Comment inline.

> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Tuesday, June 19, 2018 11:17 PM
> To: Quan, Evan 
> Cc: amd-gfx list 
> Subject: Re: [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on
> power state change
> 
> On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan  wrote:
> > The clocks hard/soft min/max clock levels will be adjusted
> > correspondingly.
> 
> 
> Also note that this add the apply_clocks_adjust_rules callback which is used
> to validate the clock settings on a power state change.  One other comment
> below.
Yes, this is for the apply_clocks_adjust_rules callback. I updated the patch 
description as below

drm/amd/powerplay: apply clocks adjust rules on power state change

This add the apply_clocks_adjust_rules callback which is used
to validate the clock settings on a power state change.
> >
> > Change-Id: I2c4b6cd6756d40a28933f0c26b9e1a3d5078bab8
> > Signed-off-by: Evan Quan 
> > ---
> >  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 162
> +
> >  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h |   2 +
> >  2 files changed, 164 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > index a227ace..26bdfff 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > @@ -1950,6 +1950,166 @@ static int vega12_print_clock_levels(struct
> pp_hwmgr *hwmgr,
> > return size;
> >  }
> >
> > +static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) {
> > +   struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr-
> >backend);
> > +   struct vega12_single_dpm_table *dpm_table;
> > +   bool vblank_too_short = false;
> > +   bool disable_mclk_switching;
> > +   uint32_t i, latency;
> > +
> > +   disable_mclk_switching = ((1 < hwmgr->display_config->num_display)
> &&
> > + 
> > !hwmgr->display_config->multi_monitor_in_sync) ||
> > + vblank_too_short;
> > +   latency =
> > + hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
> > +
> > +   /* gfxclk */
> > +   dpm_table = &(data->dpm_table.gfx_table);
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[dpm_table->count - 1].value;
> > +   dpm_table->dpm_state.hard_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.hard_max_level =
> > + dpm_table->dpm_levels[dpm_table->count - 1].value;
> > +
> > +   if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
> > +   if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
> > +   }
> > +
> > +   if (hwmgr->dpm_level ==
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[0].value;
> > +   }
> > +
> > +   if (hwmgr->dpm_level ==
> AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[dpm_table->count - 1].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[dpm_table->count - 1].value;
> > +   }
> > +   }
> > +
> > +   /* memclk */
> > +   dpm_table = &(data->dpm_table.mem_table);
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[dpm_table->count - 1].value;
> > +   dpm_table->dpm_state.hard_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.hard_max_level =
> > + dpm_table->dpm_levels[dpm_table->count - 1].value;
> > +
> > +   if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
> > +   if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
> > +   }
> > +
> > +   if (hwmgr->dpm_level ==
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
> > +   dpm_table->dpm_state.soft_min_level = dpm_table-
> >dpm_levels[0].value;
> > +   dpm_table->dpm_state.soft_max_level = dpm_table-
> >dpm_levels[0].value;
> > +

[PATCH 2/2] drm/amd/powerplay: drop unnecessary uclk hard min setting

[Evan Quan]

We don't need to set uclk hard min here because this will
be set with other clocks on power state change.

Change-Id: I05d28f881f5cff5108b9dea36e95a917d58c123a
Signed-off-by: Evan Quan 
Acked-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index df91dde..8e2efa6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1399,7 +1399,6 @@ static int 
vega12_notify_smc_display_config_after_ps_adjustment(
(struct vega12_hwmgr *)(hwmgr->backend);
struct PP_Clocks min_clocks = {0};
struct pp_display_clock_request clock_req;
-   uint32_t clk_request;
 
if ((hwmgr->display_config->num_display > 1) &&
!hwmgr->display_config->multi_monitor_in_sync)
@@ -1427,15 +1426,6 @@ static int 
vega12_notify_smc_display_config_after_ps_adjustment(
}
}
 
-   if (data->smu_features[GNLD_DPM_UCLK].enabled) {
-   clk_request = (PPCLK_UCLK << 16) | (min_clocks.memoryClock) / 
100;
-   PP_ASSERT_WITH_CODE(
-   smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_SetHardMinByFreq, clk_request) == 0,
-   
"[PhwVega12_NotifySMCDisplayConfigAfterPowerStateAdjustment] Attempt to set 
UCLK HardMin Failed!",
-   return -1);
-   data->dpm_table.mem_table.dpm_state.hard_min_level = 
min_clocks.memoryClock;
-   }
-
return 0;
 }
 
-- 
2.7.4

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[PATCH 1/2] drm/amd/powerplay: correct smc display config for multi monitor

[Evan Quan]

Need to take into account multi-head with synced displays.

Change-Id: I2ad53f47ce1dff0fa8f6ae944986567443cca04e
Signed-off-by: Evan Quan 
Acked-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 28b172e..df91dde 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1401,7 +1401,8 @@ static int 
vega12_notify_smc_display_config_after_ps_adjustment(
struct pp_display_clock_request clock_req;
uint32_t clk_request;
 
-   if (hwmgr->display_config->num_display > 1)
+   if ((hwmgr->display_config->num_display > 1) &&
+   !hwmgr->display_config->multi_monitor_in_sync)
vega12_notify_smc_display_change(hwmgr, false);
else
vega12_notify_smc_display_change(hwmgr, true);
-- 
2.7.4

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Re: [PATCH 2/5] dma-buf: remove kmap_atomic interface

[Sumit Semwal]

Hi Christian,
On Tue, 19 Jun 2018 at 20:17, Christian König  wrote:
>
> Am 18.06.2018 um 10:18 schrieb Daniel Vetter:
> > On Fri, Jun 01, 2018 at 02:00:17PM +0200, Christian König wrote:
> >> Neither used nor correctly implemented anywhere. Just completely remove
> >> the interface.
> >>
> >> Signed-off-by: Christian König 
> > I wonder whether we can nuke the normal kmap stuff too ... everyone seems
> > to want/use the vmap stuff for kernel-internal mapping needs.
> >
> > Anyway, this looks good.
Hope am not too late (was out of office for some time) - this looks ok
to me, please feel free to add my
Acked-by: Sumit Semwal 

> >> ---
> >>   drivers/dma-buf/dma-buf.c  | 44 
> >> --
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c  |  2 -
> >>   drivers/gpu/drm/armada/armada_gem.c|  2 -
> >>   drivers/gpu/drm/drm_prime.c| 26 -
> >>   drivers/gpu/drm/i915/i915_gem_dmabuf.c | 11 --
> >>   drivers/gpu/drm/i915/selftests/mock_dmabuf.c   |  2 -
> >>   drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c  |  2 -
> >>   drivers/gpu/drm/tegra/gem.c| 14 ---
> >>   drivers/gpu/drm/udl/udl_dmabuf.c   | 17 -
> >>   drivers/gpu/drm/vmwgfx/vmwgfx_prime.c  | 13 ---
> >>   .../media/common/videobuf2/videobuf2-dma-contig.c  |  1 -
> >>   drivers/media/common/videobuf2/videobuf2-dma-sg.c  |  1 -
> >>   drivers/media/common/videobuf2/videobuf2-vmalloc.c |  1 -
> >>   drivers/staging/android/ion/ion.c  |  2 -
> >>   drivers/tee/tee_shm.c  |  6 ---
> >>   include/drm/drm_prime.h|  4 --
> >>   include/linux/dma-buf.h|  4 --
> >>   17 files changed, 152 deletions(-)
> >>
> >> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
> >> index e99a8d19991b..e4c657d9fad7 100644
> >> --- a/drivers/dma-buf/dma-buf.c
> >> +++ b/drivers/dma-buf/dma-buf.c
> >> @@ -405,7 +405,6 @@ struct dma_buf *dma_buf_export(const struct 
> >> dma_buf_export_info *exp_info)
> >>|| !exp_info->ops->map_dma_buf
> >>|| !exp_info->ops->unmap_dma_buf
> >>|| !exp_info->ops->release
> >> -  || !exp_info->ops->map_atomic
> >>|| !exp_info->ops->map
> >>|| !exp_info->ops->mmap)) {
> >>  return ERR_PTR(-EINVAL);
> >> @@ -687,14 +686,6 @@ EXPORT_SYMBOL_GPL(dma_buf_unmap_attachment);
> >>*  void \*dma_buf_kmap(struct dma_buf \*, unsigned long);
> >>*  void dma_buf_kunmap(struct dma_buf \*, unsigned long, void \*);
> >>*
> >> - *   There are also atomic variants of these interfaces. Like for kmap 
> >> they
> >> - *   facilitate non-blocking fast-paths. Neither the importer nor the 
> >> exporter
> >> - *   (in the callback) is allowed to block when using these.
> >> - *
> >> - *   Interfaces::
> >> - *  void \*dma_buf_kmap_atomic(struct dma_buf \*, unsigned long);
> >> - *  void dma_buf_kunmap_atomic(struct dma_buf \*, unsigned long, void 
> >> \*);
> >> - *
> >>*   For importers all the restrictions of using kmap apply, like the 
> >> limited
> >>*   supply of kmap_atomic slots. Hence an importer shall only hold onto 
> >> at
> >>*   max 2 atomic dma_buf kmaps at the same time (in any given process 
> >> context).
> > This is also about atomic kmap ...
> >
> > And the subsequent language around "Note that these calls need to always
> > succeed." is also not true, might be good to update that stating that kmap
> > is optional (like we say already for vmap).
> >
> > With those docs nits addressed:
> >
> > Reviewed-by: Daniel Vetter 
>
> I've fixed up patch #1 and #2 and added your Reviewed-by tag.
>
> Since I finally had time to install dim do you have any objections that
> I now run "dim push drm-misc-next" with those two applied?
>
> Regards,
> Christian.
>
> >
> >> @@ -859,41 +850,6 @@ int dma_buf_end_cpu_access(struct dma_buf *dmabuf,
> >>   }
> >>   EXPORT_SYMBOL_GPL(dma_buf_end_cpu_access);
> >>
> >> -/**
> >> - * dma_buf_kmap_atomic - Map a page of the buffer object into kernel 
> >> address
> >> - * space. The same restrictions as for kmap_atomic and friends apply.
> >> - * @dmabuf: [in]buffer to map page from.
> >> - * @page_num:   [in]page in PAGE_SIZE units to map.
> >> - *
> >> - * This call must always succeed, any necessary preparations that might 
> >> fail
> >> - * need to be done in begin_cpu_access.
> >> - */
> >> -void *dma_buf_kmap_atomic(struct dma_buf *dmabuf, unsigned long page_num)
> >> -{
> >> -WARN_ON(!dmabuf);
> >> -
> >> -return dmabuf->ops->map_atomic(dmabuf, page_num);
> >> -}
> >> -EXPORT_SYMBOL_GPL(dma_buf_kmap_atomic);
> >> -
> >> -/**
> >> - * dma_buf_kunmap_atomic - Unmap a page obtained by dma_buf_kmap_atomic.
> >> - * @dmabuf: 

[PATCH] drm/amd/powerplay: initialize uvd/vce powergate status v2

[Evan Quan]

On UVD/VCE dpm disabled, the powergate status should be
set as true. So that we will not try to gate them(enable dpm
for now).

v2: added check for uvd/vce powergate status before gating

Change-Id: I569a5aa216b5e7d64a2b504f2ff98cc83ca802d5
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 23 ++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 45c8f2d..28b172e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -777,6 +777,21 @@ static int vega12_set_allowed_featuresmask(struct pp_hwmgr 
*hwmgr)
return 0;
 }
 
+static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
+{
+   struct vega12_hwmgr *data =
+   (struct vega12_hwmgr *)(hwmgr->backend);
+
+   data->uvd_power_gated = true;
+   data->vce_power_gated = true;
+
+   if (data->smu_features[GNLD_DPM_UVD].enabled)
+   data->uvd_power_gated = false;
+
+   if (data->smu_features[GNLD_DPM_VCE].enabled)
+   data->vce_power_gated = false;
+}
+
 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 {
struct vega12_hwmgr *data =
@@ -801,6 +816,8 @@ static int vega12_enable_all_smu_features(struct pp_hwmgr 
*hwmgr)
}
}
 
+   vega12_init_powergate_state(hwmgr);
+
return 0;
 }
 
@@ -1985,6 +2002,9 @@ static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, 
bool bgate)
 {
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 
+   if (data->vce_power_gated == bgate)
+   return 0;
+
data->vce_power_gated = bgate;
vega12_enable_disable_vce_dpm(hwmgr, !bgate);
 }
@@ -1993,6 +2013,9 @@ static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, 
bool bgate)
 {
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 
+   if (data->uvd_power_gated == bgate)
+   return 0;
+
data->uvd_power_gated = bgate;
vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
 }
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/2] drm/amd/pp: Unify the shared struct between pp and display

[Rex Zhu]

1. move shared struct dm_pp_wm_sets_with_clock_ranges_soc15 to
  dm_pp_interface.h.
2. delete the same struct define in powerplay, use the struct
   display defined.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/display/dc/dm_services_types.h | 49 +-
 drivers/gpu/drm/amd/include/dm_pp_interface.h  | 79 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c   | 28 
 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h   |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c |  2 +-
 7 files changed, 65 insertions(+), 99 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h 
b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index 2b83f92..7a187f8 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -28,6 +28,7 @@
 
 #include "os_types.h"
 #include "dc_types.h"
+#include "dm_pp_interface.h"
 
 struct pp_smu_funcs_rv;
 
@@ -123,54 +124,6 @@ struct dm_pp_single_disp_config {
struct dc_link_settings link_settings; /* DP only */
 };
 
-#define MAX_WM_SETS 4
-
-enum dm_pp_wm_set_id {
-   WM_SET_A = 0,
-   WM_SET_B,
-   WM_SET_C,
-   WM_SET_D,
-   WM_SET_INVALID = 0x,
-};
-
-struct dm_pp_clock_range_for_wm_set {
-   enum dm_pp_wm_set_id wm_set_id;
-   uint32_t wm_min_eng_clk_in_khz;
-   uint32_t wm_max_eng_clk_in_khz;
-   uint32_t wm_min_mem_clk_in_khz;
-   uint32_t wm_max_mem_clk_in_khz;
-};
-
-struct dm_pp_wm_sets_with_clock_ranges {
-   uint32_t num_wm_sets;
-   struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS];
-};
-
-struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
-   enum dm_pp_wm_set_id wm_set_id;
-   uint32_t wm_min_dcfclk_clk_in_khz;
-   uint32_t wm_max_dcfclk_clk_in_khz;
-   uint32_t wm_min_mem_clk_in_khz;
-   uint32_t wm_max_mem_clk_in_khz;
-};
-
-struct dm_pp_clock_range_for_mcif_wm_set_soc15 {
-   enum dm_pp_wm_set_id wm_set_id;
-   uint32_t wm_min_socclk_clk_in_khz;
-   uint32_t wm_max_socclk_clk_in_khz;
-   uint32_t wm_min_mem_clk_in_khz;
-   uint32_t wm_max_mem_clk_in_khz;
-};
-
-struct dm_pp_wm_sets_with_clock_ranges_soc15 {
-   uint32_t num_wm_dmif_sets;
-   uint32_t num_wm_mcif_sets;
-   struct dm_pp_clock_range_for_dmif_wm_set_soc15
-   wm_dmif_clocks_ranges[MAX_WM_SETS];
-   struct dm_pp_clock_range_for_mcif_wm_set_soc15
-   wm_mcif_clocks_ranges[MAX_WM_SETS];
-};
-
 #define MAX_DISPLAY_CONFIGS 6
 
 struct dm_pp_display_configuration {
diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h 
b/drivers/gpu/drm/amd/include/dm_pp_interface.h
index 7852952..e0089f1 100644
--- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -189,39 +189,52 @@ struct pp_display_clock_request {
uint32_t clock_freq_in_khz;
 };
 
-#define PP_MAX_WM_SETS 4
-
-enum pp_wm_set_id {
-   DC_WM_SET_A = 0,
-   DC_WM_SET_B,
-   DC_WM_SET_C,
-   DC_WM_SET_D,
-   DC_WM_SET_INVALID = 0x,
-};
-
-struct pp_wm_set_with_dmif_clock_range_soc15 {
-   enum pp_wm_set_id wm_set_id;
-   uint32_t wm_min_dcefclk_in_khz;
-   uint32_t wm_max_dcefclk_in_khz;
-   uint32_t wm_min_memclk_in_khz;
-   uint32_t wm_max_memclk_in_khz;
-};
-
-struct pp_wm_set_with_mcif_clock_range_soc15 {
-   enum pp_wm_set_id wm_set_id;
-   uint32_t wm_min_socclk_in_khz;
-   uint32_t wm_max_socclk_in_khz;
-   uint32_t wm_min_memclk_in_khz;
-   uint32_t wm_max_memclk_in_khz;
-};
-
-struct pp_wm_sets_with_clock_ranges_soc15 {
-   uint32_t num_wm_sets_dmif;
-   uint32_t num_wm_sets_mcif;
-   struct pp_wm_set_with_dmif_clock_range_soc15
-   wm_sets_dmif[PP_MAX_WM_SETS];
-   struct pp_wm_set_with_mcif_clock_range_soc15
-   wm_sets_mcif[PP_MAX_WM_SETS];
+#define MAX_WM_SETS 4
+
+enum dm_pp_wm_set_id {
+   WM_SET_A = 0,
+   WM_SET_B,
+   WM_SET_C,
+   WM_SET_D,
+   WM_SET_INVALID = 0x,
+};
+
+struct dm_pp_clock_range_for_wm_set {
+   enum dm_pp_wm_set_id wm_set_id;
+   uint32_t wm_min_eng_clk_in_khz;
+   uint32_t wm_max_eng_clk_in_khz;
+   uint32_t wm_min_mem_clk_in_khz;
+   uint32_t wm_max_mem_clk_in_khz;
+};
+
+struct dm_pp_wm_sets_with_clock_ranges {
+   uint32_t num_wm_sets;
+   struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS];
+};
+
+struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
+   enum dm_pp_wm_set_id wm_set_id;
+   uint32_t wm_min_dcfclk_clk_in_khz;
+   uint32_t wm_max_dcfclk_clk_in_khz;
+   uint32_t wm_min_mem_clk_in_khz;
+   uint32_t wm_max_mem_clk_in_khz;
+};
+
+struct dm_pp_clock_range_for_mcif_wm_set_soc15 {
+   enum dm_pp_wm_set_id wm_set_id;
+   uint32_t wm_min_socclk_clk_in_khz;
+