Re: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
>Maybe other clients should also not disable gfx off feature if this flag is
>not set.
For disable gfx off feature, we just need to check adev->gfx.bin_off, it mean
the gfx off feature is enabled.
Best Regards
Rex
From: Quan, Evan
Sent: Monday, July 30, 2018 12:32 PM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
>This flag should only be set by gfx ip after gfx cg/pg feature enabled.
>Other clients can't enable gfx off feature before this flag is set.
Maybe other clients should also not disable gfx off feature if this flag is not
set.
Regards,
Evan
From: Zhu, Rex
Sent: Monday, July 30, 2018 11:46:00 AM
To: Quan, Evan; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
>"adev->gfx.bready_for_off" used for ?
This flag should only be set by gfx ip after gfx cg/pg feature enabled.
Other clients can't enable gfx off feature before this flag is set.
>"adev->gfx.bready_for_off == 0"
For disable gfx off feature, we don't need to care this flag.
Best Regards
Rex
From: Quan, Evan
Sent: Monday, July 30, 2018 11:12 AM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
+ if (adev->gfx.bready_for_off && !adev->gfx.bin_off
+ && !adev->gfx.disable_gfx_off_request) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.bin_off = true;
+ } else if (!enable && adev->gfx.bin_off) {
What is "adev->gfx.bready_for_off" used for ? Do we need to consider
"adev->gfx.bready_for_off == 0" case here?
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false))
+ adev->gfx.bin_off = false;
+ }
Regards,
Evan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:35:47 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
This funciton as the entry of gfx off ctrl feature.
we arbitrat gfx off feature enable/disable in this
function.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 52 ++
3 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5b7bb58..318961d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -988,6 +988,11 @@ struct amdgpu_gfx {
/* NGG */
struct amdgpu_ngg ngg;
+ /* gfx off */
+ boolbready_for_off;
+ boolbin_off;
+ struct mutexgfx_off_ctrl_mutex;
+ uint32_tdisable_gfx_off_request;
/* pipe reservation */
struct mutexpipe_reserve_mutex;
DECLARE_BITMAP (pipe_reserve_bitmap,
AMDGPU_MAX_COMPUTE_QUEUES);
@@ -1815,6 +1820,8 @@ void amdgpu_device_program_register_sequence(struct
amdgpu_device *adev,
const u32 array_size);
bool amdgpu_device_is_px(struct drm_device *dev);
+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev,
+ enum amd_ip_block_type client, bool enable);
/* atpx handler */
#if defined(CONFIG_VGA_SWITCHEROO)
void amdgpu_register_atpx_handler(void);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 745f760..b40ce6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2367,6 +2367,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(&adev->gfx.gpu_clock_mutex);
mutex_init(&adev->srbm_mutex);
mutex_init(&adev->gfx.pipe_reserve_mutex);
+ mutex_init(&adev->gfx.gfx_off_ctrl_mutex);
mutex_init(&adev->grbm_idx_mutex);
mutex_init(&adev->mn_lock);
mutex_init(&adev->virt.vf_errors.lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 239bf2a..68fe9c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -340,3 +340,55 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device
*adev)
&ring->mqd_gpu_addr,
&ring->mqd_ptr);
}
+
+/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
+ *
+ * @adev: amdgpu_device pointer
+ * @enum amd_ip_block_type gfx ip decide when to set ready for gfx off feature
+ *
Re: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
>This flag should only be set by gfx ip after gfx cg/pg feature enabled.
>Other clients can't enable gfx off feature before this flag is set.
Maybe other clients should also not disable gfx off feature if this flag is not
set.
Regards,
Evan
From: Zhu, Rex
Sent: Monday, July 30, 2018 11:46:00 AM
To: Quan, Evan; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
>"adev->gfx.bready_for_off" used for ?
This flag should only be set by gfx ip after gfx cg/pg feature enabled.
Other clients can't enable gfx off feature before this flag is set.
>"adev->gfx.bready_for_off == 0"
For disable gfx off feature, we don't need to care this flag.
Best Regards
Rex
From: Quan, Evan
Sent: Monday, July 30, 2018 11:12 AM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
+ if (adev->gfx.bready_for_off && !adev->gfx.bin_off
+ && !adev->gfx.disable_gfx_off_request) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.bin_off = true;
+ } else if (!enable && adev->gfx.bin_off) {
What is "adev->gfx.bready_for_off" used for ? Do we need to consider
"adev->gfx.bready_for_off == 0" case here?
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false))
+ adev->gfx.bin_off = false;
+ }
Regards,
Evan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:35:47 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
This funciton as the entry of gfx off ctrl feature.
we arbitrat gfx off feature enable/disable in this
function.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 52 ++
3 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5b7bb58..318961d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -988,6 +988,11 @@ struct amdgpu_gfx {
/* NGG */
struct amdgpu_ngg ngg;
+ /* gfx off */
+ boolbready_for_off;
+ boolbin_off;
+ struct mutexgfx_off_ctrl_mutex;
+ uint32_tdisable_gfx_off_request;
/* pipe reservation */
struct mutexpipe_reserve_mutex;
DECLARE_BITMAP (pipe_reserve_bitmap,
AMDGPU_MAX_COMPUTE_QUEUES);
@@ -1815,6 +1820,8 @@ void amdgpu_device_program_register_sequence(struct
amdgpu_device *adev,
const u32 array_size);
bool amdgpu_device_is_px(struct drm_device *dev);
+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev,
+ enum amd_ip_block_type client, bool enable);
/* atpx handler */
#if defined(CONFIG_VGA_SWITCHEROO)
void amdgpu_register_atpx_handler(void);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 745f760..b40ce6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2367,6 +2367,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(&adev->gfx.gpu_clock_mutex);
mutex_init(&adev->srbm_mutex);
mutex_init(&adev->gfx.pipe_reserve_mutex);
+ mutex_init(&adev->gfx.gfx_off_ctrl_mutex);
mutex_init(&adev->grbm_idx_mutex);
mutex_init(&adev->mn_lock);
mutex_init(&adev->virt.vf_errors.lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 239bf2a..68fe9c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -340,3 +340,55 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device
*adev)
&ring->mqd_gpu_addr,
&ring->mqd_ptr);
}
+
+/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
+ *
+ * @adev: amdgpu_device pointer
+ * @enum amd_ip_block_type gfx ip decide when to set ready for gfx off feature
+ * other clients send disable gfx off feature request
+ * @bool enable
+ *
+ * if gfx ip is ready for power off gfx ip, and no other clients's request for
+ * disable gfx off feature, driver will call smu to enable gfx off immediately.
+ * otherwise, driver will wait until the clients cancel the requests.
+ */
+
+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, enum amd_ip_block_type
client, bool enable)
+{
+ if (!(ad
Re: [PATCH 2/4] drm/amdgpu: Put enable gfx off feature to a delay thread
OK, I see. Then it's better to unlock the gfx_off_ctrl_mutex in
amdgpu_gfx_off_ctrl() before calling schedule_delayed_work().
Regards,
Evan
From: Zhu, Rex
Sent: Monday, July 30, 2018 11:52:41 AM
To: Quan, Evan; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/4] drm/amdgpu: Put enable gfx off feature to a delay
thread
>I think for disable gfxoff case, you need to use
>cancle_delayed_work_sync((&adev->gfx.delay_gfx_off_enable). E.g.
This makes code a bit complex.
we don't need to cancel the delay work.
In delay work thread, we also need to get the mutex. and check the request
count value.
if Other clients have new disable requests before the delay work ran, the count
will be added by 1.
so in the delay thread, gfx off will not be enabled.
Best Regards
Rex
From: Quan, Evan
Sent: Monday, July 30, 2018 10:26 AM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/4] drm/amdgpu: Put enable gfx off feature to a delay
thread
- if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
- adev->gfx.bin_off = true;
+ schedule_delayed_work(&adev->gfx.delay_gfx_off_enable,
GFX_OFF_DELAY_ENABLE);
} else if (!enable && adev->gfx.bin_off) {
if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false))
adev->gfx.bin_off = false;
I think for disable gfxoff case, you need to use
cancle_delayed_work_sync((&adev->gfx.delay_gfx_off_enable). E.g.
if (!cancle_delayed_work_sync((&adev->gfx.delay_gfx_off_enable) &&
!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false))
adev->gfx.bin_off = false;
Regards,
Evan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:35:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 2/4] drm/amdgpu: Put enable gfx off feature to a delay thread
delay to enable gfx off feature to avoid gfx on/off frequently
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 6 --
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 318961d..b59ac02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -993,6 +993,7 @@ struct amdgpu_gfx {
boolbin_off;
struct mutexgfx_off_ctrl_mutex;
uint32_tdisable_gfx_off_request;
+ struct delayed_work delay_gfx_off_enable;
/* pipe reservation */
struct mutexpipe_reserve_mutex;
DECLARE_BITMAP (pipe_reserve_bitmap,
AMDGPU_MAX_COMPUTE_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b40ce6f..9f8e267 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1925,6 +1925,20 @@ static void
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
DRM_ERROR("ib ring test failed (%d).\n", r);
}
+static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
+{
+ struct amdgpu_device *adev =
+ container_of(work, struct amdgpu_device,
gfx.delay_gfx_off_enable.work);
+
+ mutex_lock(&adev->gfx.gfx_off_ctrl_mutex);
+ if (adev->gfx.bready_for_off && !adev->gfx.bin_off
+ && adev->gfx.disable_gfx_off_request) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.bin_off = true;
+ }
+ mutex_unlock(&adev->gfx.gfx_off_ctrl_mutex);
+}
+
/**
* amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
*
@@ -2394,6 +2408,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
INIT_DELAYED_WORK(&adev->late_init_work,
amdgpu_device_ip_late_init_func_handler);
+ INIT_DELAYED_WORK(&adev->gfx.delay_gfx_off_enable,
+ amdgpu_device_delay_enable_gfx_off);
adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true :
false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 68fe9c8..1ea1e8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -26,6 +26,9 @@
#include "amdgpu.h"
#include "amdgpu_gfx.h"
+/* 0.5 second timeout */
+#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(500)
+
/*
* GPU scratch registers helpers function.
*/
@@ -384,8 +387,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device
Re: [PATCH 2/4] drm/amdgpu: Put enable gfx off feature to a delay thread
>I think for disable gfxoff case, you need to use
>cancle_delayed_work_sync((&adev->gfx.delay_gfx_off_enable). E.g.
This makes code a bit complex.
we don't need to cancel the delay work.
In delay work thread, we also need to get the mutex. and check the request
count value.
if Other clients have new disable requests before the delay work ran, the count
will be added by 1.
so in the delay thread, gfx off will not be enabled.
Best Regards
Rex
From: Quan, Evan
Sent: Monday, July 30, 2018 10:26 AM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/4] drm/amdgpu: Put enable gfx off feature to a delay
thread
- if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
- adev->gfx.bin_off = true;
+ schedule_delayed_work(&adev->gfx.delay_gfx_off_enable,
GFX_OFF_DELAY_ENABLE);
} else if (!enable && adev->gfx.bin_off) {
if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false))
adev->gfx.bin_off = false;
I think for disable gfxoff case, you need to use
cancle_delayed_work_sync((&adev->gfx.delay_gfx_off_enable). E.g.
if (!cancle_delayed_work_sync((&adev->gfx.delay_gfx_off_enable) &&
!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false))
adev->gfx.bin_off = false;
Regards,
Evan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:35:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 2/4] drm/amdgpu: Put enable gfx off feature to a delay thread
delay to enable gfx off feature to avoid gfx on/off frequently
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 6 --
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 318961d..b59ac02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -993,6 +993,7 @@ struct amdgpu_gfx {
boolbin_off;
struct mutexgfx_off_ctrl_mutex;
uint32_tdisable_gfx_off_request;
+ struct delayed_work delay_gfx_off_enable;
/* pipe reservation */
struct mutexpipe_reserve_mutex;
DECLARE_BITMAP (pipe_reserve_bitmap,
AMDGPU_MAX_COMPUTE_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b40ce6f..9f8e267 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1925,6 +1925,20 @@ static void
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
DRM_ERROR("ib ring test failed (%d).\n", r);
}
+static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
+{
+ struct amdgpu_device *adev =
+ container_of(work, struct amdgpu_device,
gfx.delay_gfx_off_enable.work);
+
+ mutex_lock(&adev->gfx.gfx_off_ctrl_mutex);
+ if (adev->gfx.bready_for_off && !adev->gfx.bin_off
+ && adev->gfx.disable_gfx_off_request) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.bin_off = true;
+ }
+ mutex_unlock(&adev->gfx.gfx_off_ctrl_mutex);
+}
+
/**
* amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
*
@@ -2394,6 +2408,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
INIT_DELAYED_WORK(&adev->late_init_work,
amdgpu_device_ip_late_init_func_handler);
+ INIT_DELAYED_WORK(&adev->gfx.delay_gfx_off_enable,
+ amdgpu_device_delay_enable_gfx_off);
adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true :
false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 68fe9c8..1ea1e8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -26,6 +26,9 @@
#include "amdgpu.h"
#include "amdgpu_gfx.h"
+/* 0.5 second timeout */
+#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(500)
+
/*
* GPU scratch registers helpers function.
*/
@@ -384,8 +387,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, enum
amd_ip_block_type clie
*/
if (adev->gfx.bready_for_off && !adev->gfx.bin_off
&& !adev->gfx.disable_gfx_off_request) {
- if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
- adev->gfx.bin_off = true;
+ schedule_delayed_work(&adev->gf
Re: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
>"adev->gfx.bready_for_off" used for ?
This flag should only be set by gfx ip after gfx cg/pg feature enabled.
Other clients can't enable gfx off feature before this flag is set.
>"adev->gfx.bready_for_off == 0"
For disable gfx off feature, we don't need to care this flag.
Best Regards
Rex
From: Quan, Evan
Sent: Monday, July 30, 2018 11:12 AM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
+ if (adev->gfx.bready_for_off && !adev->gfx.bin_off
+ && !adev->gfx.disable_gfx_off_request) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.bin_off = true;
+ } else if (!enable && adev->gfx.bin_off) {
What is "adev->gfx.bready_for_off" used for ? Do we need to consider
"adev->gfx.bready_for_off == 0" case here?
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false))
+ adev->gfx.bin_off = false;
+ }
Regards,
Evan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:35:47 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
This funciton as the entry of gfx off ctrl feature.
we arbitrat gfx off feature enable/disable in this
function.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 52 ++
3 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5b7bb58..318961d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -988,6 +988,11 @@ struct amdgpu_gfx {
/* NGG */
struct amdgpu_ngg ngg;
+ /* gfx off */
+ boolbready_for_off;
+ boolbin_off;
+ struct mutexgfx_off_ctrl_mutex;
+ uint32_tdisable_gfx_off_request;
/* pipe reservation */
struct mutexpipe_reserve_mutex;
DECLARE_BITMAP (pipe_reserve_bitmap,
AMDGPU_MAX_COMPUTE_QUEUES);
@@ -1815,6 +1820,8 @@ void amdgpu_device_program_register_sequence(struct
amdgpu_device *adev,
const u32 array_size);
bool amdgpu_device_is_px(struct drm_device *dev);
+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev,
+ enum amd_ip_block_type client, bool enable);
/* atpx handler */
#if defined(CONFIG_VGA_SWITCHEROO)
void amdgpu_register_atpx_handler(void);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 745f760..b40ce6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2367,6 +2367,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(&adev->gfx.gpu_clock_mutex);
mutex_init(&adev->srbm_mutex);
mutex_init(&adev->gfx.pipe_reserve_mutex);
+ mutex_init(&adev->gfx.gfx_off_ctrl_mutex);
mutex_init(&adev->grbm_idx_mutex);
mutex_init(&adev->mn_lock);
mutex_init(&adev->virt.vf_errors.lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 239bf2a..68fe9c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -340,3 +340,55 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device
*adev)
&ring->mqd_gpu_addr,
&ring->mqd_ptr);
}
+
+/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
+ *
+ * @adev: amdgpu_device pointer
+ * @enum amd_ip_block_type gfx ip decide when to set ready for gfx off feature
+ * other clients send disable gfx off feature request
+ * @bool enable
+ *
+ * if gfx ip is ready for power off gfx ip, and no other clients's request for
+ * disable gfx off feature, driver will call smu to enable gfx off immediately.
+ * otherwise, driver will wait until the clients cancel the requests.
+ */
+
+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, enum amd_ip_block_type
client, bool enable)
+{
+ if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
+ return; /* gfx off feature is not supported or disabled by user
via module parameter */
+
+ if (!adev->powerplay.pp_funcs->set_powergating_by_smu)
+ return; /* currently gfx off feature need smu support*/
+
+ mutex_lock(&adev->gfx.gfx_off_ctrl_mutex);
+ if (client == AMD_IP_BLOCK_TYPE_GFX) {
+ adev->gfx.bready_for_off = enable ? true : false; /*
Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12
> It means user was told the gfx is on but actually it may switches to gfxoff
> already.
Correct.
So if the gfx is off, user should disable gfx off feature before they
read/write the registers via mmio.
if gfx is on, that is not mean the gfx off feature is disabled. it doesn't
mean it is safe to visit the registers through mmio.
Best Regards
Rex
From: Quan, Evan
Sent: Monday, July 30, 2018 9:31 AM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on
Rv/Vega12
Since the gfxoff is always in dynamic switch, i do not think the status
reported to user is reliable. It means user was told the gfx is on but actually
it may switches to gfxoff already.
Regards,
Evan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:42:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12
As gfx off is supported on Rv/Vega12, so this check is
helpful and necessary when visit gfx regesiter via mmio.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 +++
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 26d130a..da1be82 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
return false;
}
+static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+ enum amd_ip_block_type client)
+{
+ if (client == AMD_IP_BLOCK_TYPE_GFX)
+ return smu10_is_gfx_on(hwmgr);
+ else /* for other ip, to do */
+ return true;
+}
+
static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
{
struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr
*)(hwmgr->backend);
@@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr,
bool bgate)
.smus_notify_pwe = smu10_smus_notify_pwe,
.display_clock_voltage_request = smu10_display_clock_voltage_request,
.powergate_gfx = smu10_gfx_off_control,
+ .is_hw_ip_on = smu10_is_hw_ip_on,
};
int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 0789d64..ee44300 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -45,7 +45,7 @@
#include "ppinterrupt.h"
#include "pp_overdriver.h"
#include "pp_thermal.h"
-
+#include "soc15_common.h"
static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask);
@@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct
pp_hwmgr *hwmgr,
return 0;
}
+/* GFX HW Power Status can be queried from bits [1:0] of MP1_SMN_EXT_SCRATCH0
+ * 2'b00 GFX is OFF
+ * 2'b01 Transitioning out of GFXOFF state
+ * 2'b10 GFX is ON
+ * 2'b11 Transitioning into GFXOFF state
+*/
+
+static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr)
+{
+ uint32_t tmp;
+ struct amdgpu_device *adev = hwmgr->adev;
+
+ tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
+ if (tmp == 1 || tmp == 2)
+ return true;
+ else
+ return false;
+}
+
+static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+ enum amd_ip_block_type client)
+{
+ if (client == AMD_IP_BLOCK_TYPE_GFX)
+ return vega12_is_gfx_on(hwmgr);
+ else /* for other ip, to do */
+ return true;
+}
+
static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
{
struct vega12_hwmgr *data =
@@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr,
bool enable)
.register_irq_handlers = smu9_register_irq_handlers,
.start_thermal_controller = vega12_start_thermal_controller,
.powergate_gfx = vega12_gfx_off_control,
+ .is_hw_ip_on = vega12_is_hw_ip_on,
};
int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
--
1.9.1
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Re: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
+ if (adev->gfx.bready_for_off && !adev->gfx.bin_off
+ && !adev->gfx.disable_gfx_off_request) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.bin_off = true;
+ } else if (!enable && adev->gfx.bin_off) {
What is "adev->gfx.bready_for_off" used for ? Do we need to consider
"adev->gfx.bready_for_off == 0" case here?
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false))
+ adev->gfx.bin_off = false;
+ }
Regards,
Evan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:35:47 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
This funciton as the entry of gfx off ctrl feature.
we arbitrat gfx off feature enable/disable in this
function.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 52 ++
3 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5b7bb58..318961d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -988,6 +988,11 @@ struct amdgpu_gfx {
/* NGG */
struct amdgpu_ngg ngg;
+ /* gfx off */
+ boolbready_for_off;
+ boolbin_off;
+ struct mutexgfx_off_ctrl_mutex;
+ uint32_tdisable_gfx_off_request;
/* pipe reservation */
struct mutexpipe_reserve_mutex;
DECLARE_BITMAP (pipe_reserve_bitmap,
AMDGPU_MAX_COMPUTE_QUEUES);
@@ -1815,6 +1820,8 @@ void amdgpu_device_program_register_sequence(struct
amdgpu_device *adev,
const u32 array_size);
bool amdgpu_device_is_px(struct drm_device *dev);
+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev,
+ enum amd_ip_block_type client, bool enable);
/* atpx handler */
#if defined(CONFIG_VGA_SWITCHEROO)
void amdgpu_register_atpx_handler(void);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 745f760..b40ce6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2367,6 +2367,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(&adev->gfx.gpu_clock_mutex);
mutex_init(&adev->srbm_mutex);
mutex_init(&adev->gfx.pipe_reserve_mutex);
+ mutex_init(&adev->gfx.gfx_off_ctrl_mutex);
mutex_init(&adev->grbm_idx_mutex);
mutex_init(&adev->mn_lock);
mutex_init(&adev->virt.vf_errors.lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 239bf2a..68fe9c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -340,3 +340,55 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device
*adev)
&ring->mqd_gpu_addr,
&ring->mqd_ptr);
}
+
+/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
+ *
+ * @adev: amdgpu_device pointer
+ * @enum amd_ip_block_type gfx ip decide when to set ready for gfx off feature
+ * other clients send disable gfx off feature request
+ * @bool enable
+ *
+ * if gfx ip is ready for power off gfx ip, and no other clients's request for
+ * disable gfx off feature, driver will call smu to enable gfx off immediately.
+ * otherwise, driver will wait until the clients cancel the requests.
+ */
+
+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, enum amd_ip_block_type
client, bool enable)
+{
+ if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
+ return; /* gfx off feature is not supported or disabled by user
via module parameter */
+
+ if (!adev->powerplay.pp_funcs->set_powergating_by_smu)
+ return; /* currently gfx off feature need smu support*/
+
+ mutex_lock(&adev->gfx.gfx_off_ctrl_mutex);
+ if (client == AMD_IP_BLOCK_TYPE_GFX) {
+ adev->gfx.bready_for_off = enable ? true : false; /*true, gfx
ip is ready to enable gfx off feature */
+ } else {
+ if (!enable) /* false : reveive one disable gfx off requests
from other clients*/
+ adev->gfx.disable_gfx_off_request++;
+ else if (adev->gfx.disable_gfx_off_request > 0)
+ adev->gfx.disable_gfx_off_request--;
+ }
+
+/* *
+ * we can enable gfx off feature when meet the following conditions:
+ * 1. gfx off feature is supported by hw
+ * 2. gfx ip is read
Re: [PATCH] drm/amdgpu: add new amdgpu_vm_bo_trace_cs() function
On Mon, Jul 30, 2018 at 12:30:40AM +0800, Grodzovsky, Andrey wrote:
> When VM fault happens it helps verify a that a BO for the faulted VA wasn't
> omitted from the BO list for the CS.
>
Good to know. Thanks, Andrey.
Ray
> Andrey
>
>
> From: amd-gfx on behalf of Huang Rui
>
> Sent: 29 July 2018 08:16:30
> To: Christian K?nig
> Cc: Grodzovsky, Andrey; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: add new amdgpu_vm_bo_trace_cs() function
>
> On Fri, Jul 27, 2018 at 04:57:43PM +0200, Christian K?nig wrote:
> > This allows us to trace all VM ranges which should be valid inside a CS.
> >
> > Signed-off-by: Christian K?nig
>
> Reviewed-by: Huang Rui
>
> A bit curious, what kind of situation that we need trace all VM ranges
> during the command submission?
>
> Thanks,
> Ray
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 2 ++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 5 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 30
> > ++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 1 +
> > 4 files changed, 38 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > index 8a49c3b97bd4..871401cd9997 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > @@ -1220,6 +1220,7 @@ static void amdgpu_cs_post_dependencies(struct
> > amdgpu_cs_parser *p)
> > static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> > union drm_amdgpu_cs *cs)
> > {
> > + struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
> > struct amdgpu_ring *ring = p->ring;
> > struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
> > enum drm_sched_priority priority;
> > @@ -1272,6 +1273,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser
> > *p,
> > amdgpu_job_free_resources(job);
> >
> > trace_amdgpu_cs_ioctl(job);
> > + amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
> > priority = job->base.s_priority;
> > drm_sched_entity_push_job(&job->base, entity);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> > index 11f262f15200..7206a0025b17 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> > @@ -314,6 +314,11 @@ DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_mapping,
> > TP_ARGS(mapping)
> > );
> >
> > +DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_cs,
> > + TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
> > + TP_ARGS(mapping)
> > +);
> > +
> > TRACE_EVENT(amdgpu_vm_set_ptes,
> > TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
> >uint32_t incr, uint64_t flags),
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > index 5d7d7900ccab..7aedf3184e36 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > @@ -2343,6 +2343,36 @@ struct amdgpu_bo_va_mapping
> > *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
> > return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
> > }
> >
> > +/**
> > + * amdgpu_vm_bo_trace_cs - trace all reserved mappings
> > + *
> > + * @vm: the requested vm
> > + * @ticket: CS ticket
> > + *
> > + * Trace all mappings of BOs reserved during a command submission.
> > + */
> > +void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx
> > *ticket)
> > +{
> > + struct amdgpu_bo_va_mapping *mapping;
> > +
> > + if (!trace_amdgpu_vm_bo_cs_enabled())
> > + return;
> > +
> > + for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
> > + mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
> > + struct amdgpu_bo *bo;
> > +
> > + if (!mapping->bo_va || !mapping->bo_va->base.bo)
> > + continue;
> > +
> > + bo = mapping->bo_va->base.bo;
> > + if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
> > + continue;
> > +
> > + trace_amdgpu_vm_bo_cs(mapping);
> > + }
> > +}
> > +
> > /**
> > * amdgpu_vm_bo_rmv - remove a bo to a specific vm
> > *
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> > index d416f895233d..67a15d439ac0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> > @@ -318,6 +318,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device
> > *adev,
> > uint64_t saddr, uint64_t size);
> > struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm
> > *vm,
> >uint64_t addr);
> > +void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm,
Re: [PATCH 3/4] drm/amdgpu: gfx ip ctrl gfx off via amdgpu_gfx_off_ctrl
Reviewed-by: Evan Quan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:35:49 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 3/4] drm/amdgpu: gfx ip ctrl gfx off via amdgpu_gfx_off_ctrl
use amdgpu_gfx_off_ctrl function so driver can arbitrate
whether the gfx ip can be power off or power on.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9f8e267..d861bfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1828,8 +1828,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device
*adev)
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
- if (adev->powerplay.pp_funcs->set_powergating_by_smu)
- amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false);
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_GFX, false);
r = adev->ip_blocks[i].version->funcs->hw_fini((void
*)adev);
/* XXX handle errors */
if (r) {
@@ -2013,8 +2012,7 @@ static int amdgpu_device_ip_suspend_phase2(struct
amdgpu_device *adev)
}
/* call smu to disable gfx off feature first when suspend */
- if (adev->powerplay.pp_funcs->set_powergating_by_smu)
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX,
false);
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_GFX, false);
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.valid)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ef00d14..c3d8030 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3783,13 +3783,11 @@ static int gfx_v9_0_set_powergating_state(void *handle,
gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
/* set gfx off through smu */
- if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
- amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true);
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_GFX, true);
break;
case CHIP_VEGA12:
/* set gfx off through smu */
- if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
- amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true);
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_GFX, true);
break;
default:
break;
--
1.9.1
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Re: [PATCH 4/4] drm/amdgpu: Disable gfx off if VCN is busy
Reviewed-by: Evan Quan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:35:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 4/4] drm/amdgpu: Disable gfx off if VCN is busy
this patch is a workaround for the gpu hang
at video end time if play video with gfx off enabled.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 798648a..d68039f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -214,6 +214,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct
*work)
fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg);
if (fences == 0) {
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_VCN, true);
if (adev->pm.dpm_enabled)
amdgpu_dpm_enable_uvd(adev, false);
else
@@ -230,6 +231,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
if (set_clocks) {
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_VCN, false);
if (adev->pm.dpm_enabled)
amdgpu_dpm_enable_uvd(adev, true);
else
--
1.9.1
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Re: [PATCH 2/4] drm/amdgpu: Put enable gfx off feature to a delay thread
- if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
- adev->gfx.bin_off = true;
+ schedule_delayed_work(&adev->gfx.delay_gfx_off_enable,
GFX_OFF_DELAY_ENABLE);
} else if (!enable && adev->gfx.bin_off) {
if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false))
adev->gfx.bin_off = false;
I think for disable gfxoff case, you need to use
cancle_delayed_work_sync((&adev->gfx.delay_gfx_off_enable). E.g.
if (!cancle_delayed_work_sync((&adev->gfx.delay_gfx_off_enable) &&
!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false))
adev->gfx.bin_off = false;
Regards,
Evan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:35:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 2/4] drm/amdgpu: Put enable gfx off feature to a delay thread
delay to enable gfx off feature to avoid gfx on/off frequently
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 6 --
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 318961d..b59ac02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -993,6 +993,7 @@ struct amdgpu_gfx {
boolbin_off;
struct mutexgfx_off_ctrl_mutex;
uint32_tdisable_gfx_off_request;
+ struct delayed_work delay_gfx_off_enable;
/* pipe reservation */
struct mutexpipe_reserve_mutex;
DECLARE_BITMAP (pipe_reserve_bitmap,
AMDGPU_MAX_COMPUTE_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b40ce6f..9f8e267 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1925,6 +1925,20 @@ static void
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
DRM_ERROR("ib ring test failed (%d).\n", r);
}
+static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
+{
+ struct amdgpu_device *adev =
+ container_of(work, struct amdgpu_device,
gfx.delay_gfx_off_enable.work);
+
+ mutex_lock(&adev->gfx.gfx_off_ctrl_mutex);
+ if (adev->gfx.bready_for_off && !adev->gfx.bin_off
+ && adev->gfx.disable_gfx_off_request) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.bin_off = true;
+ }
+ mutex_unlock(&adev->gfx.gfx_off_ctrl_mutex);
+}
+
/**
* amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
*
@@ -2394,6 +2408,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
INIT_DELAYED_WORK(&adev->late_init_work,
amdgpu_device_ip_late_init_func_handler);
+ INIT_DELAYED_WORK(&adev->gfx.delay_gfx_off_enable,
+ amdgpu_device_delay_enable_gfx_off);
adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true :
false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 68fe9c8..1ea1e8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -26,6 +26,9 @@
#include "amdgpu.h"
#include "amdgpu_gfx.h"
+/* 0.5 second timeout */
+#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(500)
+
/*
* GPU scratch registers helpers function.
*/
@@ -384,8 +387,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, enum
amd_ip_block_type clie
*/
if (adev->gfx.bready_for_off && !adev->gfx.bin_off
&& !adev->gfx.disable_gfx_off_request) {
- if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
- adev->gfx.bin_off = true;
+ schedule_delayed_work(&adev->gfx.delay_gfx_off_enable,
GFX_OFF_DELAY_ENABLE);
} else if (!enable && adev->gfx.bin_off) {
if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false))
adev->gfx.bin_off = false;
--
1.9.1
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RE: [PATCH] drm/amdgpu: add new amdgpu_vm_bo_trace_cs() function
Reviewed-by: Chunming Zhou
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Christian K?nig
Sent: Friday, July 27, 2018 10:58 PM
To: amd-gfx@lists.freedesktop.org; Grodzovsky, Andrey
Subject: [PATCH] drm/amdgpu: add new amdgpu_vm_bo_trace_cs() function
This allows us to trace all VM ranges which should be valid inside a CS.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 30 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 1 +
4 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 8a49c3b97bd4..871401cd9997 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1220,6 +1220,7 @@ static void amdgpu_cs_post_dependencies(struct
amdgpu_cs_parser *p) static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
union drm_amdgpu_cs *cs)
{
+ struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
struct amdgpu_ring *ring = p->ring;
struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
enum drm_sched_priority priority;
@@ -1272,6 +1273,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
amdgpu_job_free_resources(job);
trace_amdgpu_cs_ioctl(job);
+ amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
priority = job->base.s_priority;
drm_sched_entity_push_job(&job->base, entity);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 11f262f15200..7206a0025b17 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -314,6 +314,11 @@ DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_mapping,
TP_ARGS(mapping)
);
+DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_cs,
+ TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
+ TP_ARGS(mapping)
+);
+
TRACE_EVENT(amdgpu_vm_set_ptes,
TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
uint32_t incr, uint64_t flags),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 5d7d7900ccab..7aedf3184e36 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2343,6 +2343,36 @@ struct amdgpu_bo_va_mapping
*amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
return amdgpu_vm_it_iter_first(&vm->va, addr, addr); }
+/**
+ * amdgpu_vm_bo_trace_cs - trace all reserved mappings
+ *
+ * @vm: the requested vm
+ * @ticket: CS ticket
+ *
+ * Trace all mappings of BOs reserved during a command submission.
+ */
+void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx
+*ticket) {
+ struct amdgpu_bo_va_mapping *mapping;
+
+ if (!trace_amdgpu_vm_bo_cs_enabled())
+ return;
+
+ for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
+mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
+ struct amdgpu_bo *bo;
+
+ if (!mapping->bo_va || !mapping->bo_va->base.bo)
+ continue;
+
+ bo = mapping->bo_va->base.bo;
+ if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
+ continue;
+
+ trace_amdgpu_vm_bo_cs(mapping);
+ }
+}
+
/**
* amdgpu_vm_bo_rmv - remove a bo to a specific vm
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index d416f895233d..67a15d439ac0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -318,6 +318,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
uint64_t saddr, uint64_t size);
struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
uint64_t addr);
+void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx
+*ticket);
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va);
void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
--
2.14.1
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RE: [PATCH] drm/amdgpu: add proper error handling to amdgpu_bo_list_get
Reviewed-by: Chunming Zhou
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Christian K?nig
Sent: Friday, July 27, 2018 9:39 PM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: add proper error handling to amdgpu_bo_list_get
Otherwise we silently don't use a BO list when the handle is invalid.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 28 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 11 ---
3 files changed, 20 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 13aaa118aca4..4cd20e722d70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -713,8 +713,8 @@ struct amdgpu_bo_list {
struct amdgpu_bo_list_entry *array;
};
-struct amdgpu_bo_list *
-amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
+int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id,
+ struct amdgpu_bo_list **result);
void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
struct list_head *validated);
void amdgpu_bo_list_put(struct amdgpu_bo_list *list); diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index 7679c068c89a..944868e47119 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -180,27 +180,20 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
return r;
}
-struct amdgpu_bo_list *
-amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id)
+int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id,
+ struct amdgpu_bo_list **result)
{
- struct amdgpu_bo_list *result;
-
rcu_read_lock();
- result = idr_find(&fpriv->bo_list_handles, id);
+ *result = idr_find(&fpriv->bo_list_handles, id);
- if (result) {
- if (kref_get_unless_zero(&result->refcount)) {
- rcu_read_unlock();
- mutex_lock(&result->lock);
- } else {
- rcu_read_unlock();
- result = NULL;
- }
- } else {
+ if (*result && kref_get_unless_zero(&(*result)->refcount)) {
rcu_read_unlock();
+ mutex_lock(&(*result)->lock);
+ return 0;
}
- return result;
+ rcu_read_unlock();
+ return -ENOENT;
}
void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, @@ -335,9 +328,8 @@
int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
break;
case AMDGPU_BO_LIST_OP_UPDATE:
- r = -ENOENT;
- list = amdgpu_bo_list_get(fpriv, handle);
- if (!list)
+ r = amdgpu_bo_list_get(fpriv, handle, &list);
+ if (r)
goto error_free;
r = amdgpu_bo_list_set(adev, filp, list, info, diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 533b2e7656c0..8a49c3b97bd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -572,11 +572,16 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser
*p,
INIT_LIST_HEAD(&p->validated);
/* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES
is present */
- if (!p->bo_list)
- p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
- else
+ if (p->bo_list) {
mutex_lock(&p->bo_list->lock);
+ } else if (cs->in.bo_list_handle) {
+ r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
+ &p->bo_list);
+ if (r)
+ return r;
+ }
+
if (p->bo_list) {
amdgpu_bo_list_get_list(p->bo_list, &p->validated);
if (p->bo_list->first_userptr != p->bo_list->num_entries)
--
2.14.1
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Re: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12
Since the gfxoff is always in dynamic switch, i do not think the status
reported to user is reliable. It means user was told the gfx is on but actually
it may switches to gfxoff already.
Regards,
Evan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:42:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12
As gfx off is supported on Rv/Vega12, so this check is
helpful and necessary when visit gfx regesiter via mmio.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 +++
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 26d130a..da1be82 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
return false;
}
+static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+ enum amd_ip_block_type client)
+{
+ if (client == AMD_IP_BLOCK_TYPE_GFX)
+ return smu10_is_gfx_on(hwmgr);
+ else /* for other ip, to do */
+ return true;
+}
+
static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
{
struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr
*)(hwmgr->backend);
@@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr,
bool bgate)
.smus_notify_pwe = smu10_smus_notify_pwe,
.display_clock_voltage_request = smu10_display_clock_voltage_request,
.powergate_gfx = smu10_gfx_off_control,
+ .is_hw_ip_on = smu10_is_hw_ip_on,
};
int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 0789d64..ee44300 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -45,7 +45,7 @@
#include "ppinterrupt.h"
#include "pp_overdriver.h"
#include "pp_thermal.h"
-
+#include "soc15_common.h"
static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask);
@@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct
pp_hwmgr *hwmgr,
return 0;
}
+/* GFX HW Power Status can be queried from bits [1:0] of MP1_SMN_EXT_SCRATCH0
+ * 2'b00 GFX is OFF
+ * 2'b01 Transitioning out of GFXOFF state
+ * 2'b10 GFX is ON
+ * 2'b11 Transitioning into GFXOFF state
+*/
+
+static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr)
+{
+ uint32_t tmp;
+ struct amdgpu_device *adev = hwmgr->adev;
+
+ tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
+ if (tmp == 1 || tmp == 2)
+ return true;
+ else
+ return false;
+}
+
+static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+ enum amd_ip_block_type client)
+{
+ if (client == AMD_IP_BLOCK_TYPE_GFX)
+ return vega12_is_gfx_on(hwmgr);
+ else /* for other ip, to do */
+ return true;
+}
+
static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
{
struct vega12_hwmgr *data =
@@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr,
bool enable)
.register_irq_handlers = smu9_register_irq_handlers,
.start_thermal_controller = vega12_start_thermal_controller,
.powergate_gfx = vega12_gfx_off_control,
+ .is_hw_ip_on = vega12_is_hw_ip_on,
};
int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
--
1.9.1
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Re: [PATCH 1/3] drm/amd/pp: Delete duplicated interface in hwmgr_func
Reviewed-by: Evan Quan
From: amd-gfx on behalf of Rex Zhu
Sent: Sunday, July 29, 2018 7:42:25 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 1/3] drm/amd/pp: Delete duplicated interface in hwmgr_func
gfx off support in smu can be via powergate_gfx interface.
so remove the gfx_off_control interface.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 1 -
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index a63e006..26d130a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1185,7 +1185,6 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr,
bool bgate)
.dynamic_state_management_disable = smu10_disable_dpm_tasks,
.powergate_mmhub = smu10_powergate_mmhub,
.smus_notify_pwe = smu10_smus_notify_pwe,
- .gfx_off_control = smu10_gfx_off_control,
.display_clock_voltage_request = smu10_display_clock_voltage_request,
.powergate_gfx = smu10_gfx_off_control,
};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 7e58a0d..88f4517 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -298,7 +298,6 @@ struct pp_hwmgr_func {
int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock);
int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct
amd_pp_simple_clock_info *clocks);
- int (*gfx_off_control)(struct pp_hwmgr *hwmgr, bool enable);
int (*power_off_asic)(struct pp_hwmgr *hwmgr);
int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type
type, uint32_t mask);
int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type
type, char *buf);
--
1.9.1
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Re: [PATCH] drm/amdgpu: add new amdgpu_vm_bo_trace_cs() function
When VM fault happens it helps verify a that a BO for the faulted VA wasn't
omitted from the BO list for the CS.
Andrey
From: amd-gfx on behalf of Huang Rui
Sent: 29 July 2018 08:16:30
To: Christian König
Cc: Grodzovsky, Andrey; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: add new amdgpu_vm_bo_trace_cs() function
On Fri, Jul 27, 2018 at 04:57:43PM +0200, Christian König wrote:
> This allows us to trace all VM ranges which should be valid inside a CS.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
A bit curious, what kind of situation that we need trace all VM ranges
during the command submission?
Thanks,
Ray
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 5 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 30 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 1 +
> 4 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 8a49c3b97bd4..871401cd9997 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -1220,6 +1220,7 @@ static void amdgpu_cs_post_dependencies(struct
> amdgpu_cs_parser *p)
> static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> union drm_amdgpu_cs *cs)
> {
> + struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
> struct amdgpu_ring *ring = p->ring;
> struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
> enum drm_sched_priority priority;
> @@ -1272,6 +1273,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> amdgpu_job_free_resources(job);
>
> trace_amdgpu_cs_ioctl(job);
> + amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
> priority = job->base.s_priority;
> drm_sched_entity_push_job(&job->base, entity);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> index 11f262f15200..7206a0025b17 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> @@ -314,6 +314,11 @@ DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_mapping,
> TP_ARGS(mapping)
> );
>
> +DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_cs,
> + TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
> + TP_ARGS(mapping)
> +);
> +
> TRACE_EVENT(amdgpu_vm_set_ptes,
> TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
>uint32_t incr, uint64_t flags),
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 5d7d7900ccab..7aedf3184e36 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2343,6 +2343,36 @@ struct amdgpu_bo_va_mapping
> *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
> return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
> }
>
> +/**
> + * amdgpu_vm_bo_trace_cs - trace all reserved mappings
> + *
> + * @vm: the requested vm
> + * @ticket: CS ticket
> + *
> + * Trace all mappings of BOs reserved during a command submission.
> + */
> +void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx
> *ticket)
> +{
> + struct amdgpu_bo_va_mapping *mapping;
> +
> + if (!trace_amdgpu_vm_bo_cs_enabled())
> + return;
> +
> + for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
> + mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
> + struct amdgpu_bo *bo;
> +
> + if (!mapping->bo_va || !mapping->bo_va->base.bo)
> + continue;
> +
> + bo = mapping->bo_va->base.bo;
> + if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
> + continue;
> +
> + trace_amdgpu_vm_bo_cs(mapping);
> + }
> +}
> +
> /**
> * amdgpu_vm_bo_rmv - remove a bo to a specific vm
> *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index d416f895233d..67a15d439ac0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -318,6 +318,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device
> *adev,
> uint64_t saddr, uint64_t size);
> struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm
> *vm,
>uint64_t addr);
> +void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx
> *ticket);
> void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
> struct amdgpu_bo_va *bo_va);
> void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
> --
> 2.14.1
>
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Re: [Linux-v4.18-rc6] modpost-errors when compiling with clang-7 and CONFIG_DRM_AMDGPU=m
Do you need further informations? No, that is a known issue. Regards, Christian. Am 29.07.2018 um 15:52 schrieb Sedat Dilek: Hi, when compiling with clang-7 and CONFIG_DRM_AMDGPU=m I see the following... if [ "" = "-pg" ]; then if [ arch/x86/boot/compressed/misc.o != "scripts/mod/empty.o" ]; then ./scripts/recordmcount "arch/x86/boot/compressed/misc.o"; fi; fi; ERROR: "__addsf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__subdf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__gedf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__fixunssfsi" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__floatunsisf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__unordsf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__gesf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__mulsf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__truncdfsf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__ltsf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__muldf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__eqsf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__floatsisf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__ledf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__gtsf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__fixdfsi" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__floatunsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__nesf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__adddf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__extendsfdf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__fixunsdfsi" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__lesf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__ltdf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__floatsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__subsf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__gtdf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__fixsfsi" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divsf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__floatdidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! make[4]: *** [scripts/Makefile.modpost:92: __modpost] Error 1 make[3]: *** [Makefile:1208: modules] Error 2 make[3]: *** Waiting for unfinished jobs For now I have disabled CONFIG_DRM_AMDGPU=n. Do you need further informations? Kind regards, - Sedat - ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/scheduler: only kill entity if last user is killed
On Thu, Jul 26, 2018 at 01:45:54PM +0200, Christian König wrote:
> Note which task is using the entity and only kill it if the last user of
> the entity is killed. This should prevent problems when entities are leaked to
> child processes.
>
> Signed-off-by: Christian König
I am not very familiar with scheduler yet. From code logic, it looks fine for
me.
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/scheduler/gpu_scheduler.c | 6 +-
> include/drm/gpu_scheduler.h | 1 +
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler.c
> b/drivers/gpu/drm/scheduler/gpu_scheduler.c
> index 3f2fc5e8242a..f563e4fbb4b6 100644
> --- a/drivers/gpu/drm/scheduler/gpu_scheduler.c
> +++ b/drivers/gpu/drm/scheduler/gpu_scheduler.c
> @@ -275,6 +275,7 @@ static void drm_sched_entity_kill_jobs_cb(struct
> dma_fence *f,
> long drm_sched_entity_flush(struct drm_sched_entity *entity, long timeout)
> {
> struct drm_gpu_scheduler *sched;
> + struct task_struct *last_user;
> long ret = timeout;
>
> sched = entity->rq->sched;
> @@ -295,7 +296,9 @@ long drm_sched_entity_flush(struct drm_sched_entity
> *entity, long timeout)
>
>
> /* For killed process disable any more IBs enqueue right now */
> - if ((current->flags & PF_EXITING) && (current->exit_code == SIGKILL))
> + last_user = cmpxchg(&entity->last_user, current->group_leader, NULL);
> + if ((!last_user || last_user == current->group_leader) &&
> + (current->flags & PF_EXITING) && (current->exit_code == SIGKILL))
> drm_sched_entity_set_rq(entity, NULL);
>
> return ret;
> @@ -541,6 +544,7 @@ void drm_sched_entity_push_job(struct drm_sched_job
> *sched_job,
>
> trace_drm_sched_job(sched_job, entity);
>
> + WRITE_ONCE(entity->last_user, current->group_leader);
> first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node);
>
> /* first job wakes up scheduler */
> diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
> index 091b9afcd184..64016446a103 100644
> --- a/include/drm/gpu_scheduler.h
> +++ b/include/drm/gpu_scheduler.h
> @@ -85,6 +85,7 @@ struct drm_sched_entity {
> struct dma_fence_cb cb;
> atomic_t*guilty;
> struct dma_fence*last_scheduled;
> + struct task_struct *last_user;
> };
>
> /**
> --
> 2.14.1
>
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Re: [PATCH] drm/amdgpu: add new amdgpu_vm_bo_trace_cs() function
On Fri, Jul 27, 2018 at 04:57:43PM +0200, Christian König wrote:
> This allows us to trace all VM ranges which should be valid inside a CS.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
A bit curious, what kind of situation that we need trace all VM ranges
during the command submission?
Thanks,
Ray
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 5 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 30 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 1 +
> 4 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 8a49c3b97bd4..871401cd9997 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -1220,6 +1220,7 @@ static void amdgpu_cs_post_dependencies(struct
> amdgpu_cs_parser *p)
> static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> union drm_amdgpu_cs *cs)
> {
> + struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
> struct amdgpu_ring *ring = p->ring;
> struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
> enum drm_sched_priority priority;
> @@ -1272,6 +1273,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> amdgpu_job_free_resources(job);
>
> trace_amdgpu_cs_ioctl(job);
> + amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
> priority = job->base.s_priority;
> drm_sched_entity_push_job(&job->base, entity);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> index 11f262f15200..7206a0025b17 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> @@ -314,6 +314,11 @@ DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_mapping,
> TP_ARGS(mapping)
> );
>
> +DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_cs,
> + TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
> + TP_ARGS(mapping)
> +);
> +
> TRACE_EVENT(amdgpu_vm_set_ptes,
> TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
>uint32_t incr, uint64_t flags),
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 5d7d7900ccab..7aedf3184e36 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2343,6 +2343,36 @@ struct amdgpu_bo_va_mapping
> *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
> return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
> }
>
> +/**
> + * amdgpu_vm_bo_trace_cs - trace all reserved mappings
> + *
> + * @vm: the requested vm
> + * @ticket: CS ticket
> + *
> + * Trace all mappings of BOs reserved during a command submission.
> + */
> +void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx
> *ticket)
> +{
> + struct amdgpu_bo_va_mapping *mapping;
> +
> + if (!trace_amdgpu_vm_bo_cs_enabled())
> + return;
> +
> + for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
> + mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
> + struct amdgpu_bo *bo;
> +
> + if (!mapping->bo_va || !mapping->bo_va->base.bo)
> + continue;
> +
> + bo = mapping->bo_va->base.bo;
> + if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
> + continue;
> +
> + trace_amdgpu_vm_bo_cs(mapping);
> + }
> +}
> +
> /**
> * amdgpu_vm_bo_rmv - remove a bo to a specific vm
> *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index d416f895233d..67a15d439ac0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -318,6 +318,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device
> *adev,
> uint64_t saddr, uint64_t size);
> struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm
> *vm,
>uint64_t addr);
> +void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx
> *ticket);
> void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
> struct amdgpu_bo_va *bo_va);
> void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
> --
> 2.14.1
>
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Re: [PATCH] drm/amdgpu: add proper error handling to amdgpu_bo_list_get
On Fri, Jul 27, 2018 at 03:39:01PM +0200, Christian König wrote:
> Otherwise we silently don't use a BO list when the handle is invalid.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 28 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 11 ---
> 3 files changed, 20 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 13aaa118aca4..4cd20e722d70 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -713,8 +713,8 @@ struct amdgpu_bo_list {
> struct amdgpu_bo_list_entry *array;
> };
>
> -struct amdgpu_bo_list *
> -amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
> +int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id,
> +struct amdgpu_bo_list **result);
> void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
>struct list_head *validated);
> void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> index 7679c068c89a..944868e47119 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> @@ -180,27 +180,20 @@ static int amdgpu_bo_list_set(struct amdgpu_device
> *adev,
> return r;
> }
>
> -struct amdgpu_bo_list *
> -amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id)
> +int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id,
> +struct amdgpu_bo_list **result)
> {
> - struct amdgpu_bo_list *result;
> -
> rcu_read_lock();
> - result = idr_find(&fpriv->bo_list_handles, id);
> + *result = idr_find(&fpriv->bo_list_handles, id);
>
> - if (result) {
> - if (kref_get_unless_zero(&result->refcount)) {
> - rcu_read_unlock();
> - mutex_lock(&result->lock);
> - } else {
> - rcu_read_unlock();
> - result = NULL;
> - }
> - } else {
> + if (*result && kref_get_unless_zero(&(*result)->refcount)) {
> rcu_read_unlock();
> + mutex_lock(&(*result)->lock);
> + return 0;
> }
>
> - return result;
> + rcu_read_unlock();
> + return -ENOENT;
> }
>
> void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
> @@ -335,9 +328,8 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void
> *data,
> break;
>
> case AMDGPU_BO_LIST_OP_UPDATE:
> - r = -ENOENT;
> - list = amdgpu_bo_list_get(fpriv, handle);
> - if (!list)
> + r = amdgpu_bo_list_get(fpriv, handle, &list);
> + if (r)
> goto error_free;
>
> r = amdgpu_bo_list_set(adev, filp, list, info,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 533b2e7656c0..8a49c3b97bd4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -572,11 +572,16 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser
> *p,
> INIT_LIST_HEAD(&p->validated);
>
> /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES
> is present */
> - if (!p->bo_list)
> - p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
> - else
> + if (p->bo_list) {
> mutex_lock(&p->bo_list->lock);
>
> + } else if (cs->in.bo_list_handle) {
> + r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
> +&p->bo_list);
> + if (r)
> + return r;
> + }
> +
> if (p->bo_list) {
> amdgpu_bo_list_get_list(p->bo_list, &p->validated);
> if (p->bo_list->first_userptr != p->bo_list->num_entries)
> --
> 2.14.1
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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[PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12
As gfx off is supported on Rv/Vega12, so this check is
helpful and necessary when visit gfx regesiter via mmio.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 +++
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 26d130a..da1be82 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
return false;
}
+static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+ enum amd_ip_block_type client)
+{
+ if (client == AMD_IP_BLOCK_TYPE_GFX)
+ return smu10_is_gfx_on(hwmgr);
+ else /* for other ip, to do */
+ return true;
+}
+
static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
{
struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
@@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr,
bool bgate)
.smus_notify_pwe = smu10_smus_notify_pwe,
.display_clock_voltage_request = smu10_display_clock_voltage_request,
.powergate_gfx = smu10_gfx_off_control,
+ .is_hw_ip_on = smu10_is_hw_ip_on,
};
int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 0789d64..ee44300 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -45,7 +45,7 @@
#include "ppinterrupt.h"
#include "pp_overdriver.h"
#include "pp_thermal.h"
-
+#include "soc15_common.h"
static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask);
@@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct
pp_hwmgr *hwmgr,
return 0;
}
+/* GFX HW Power Status can be queried from bits [1:0] of MP1_SMN_EXT_SCRATCH0
+ * 2'b00 GFX is OFF
+ * 2'b01 Transitioning out of GFXOFF state
+ * 2'b10 GFX is ON
+ * 2'b11 Transitioning into GFXOFF state
+*/
+
+static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr)
+{
+ uint32_t tmp;
+ struct amdgpu_device *adev = hwmgr->adev;
+
+ tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
+ if (tmp == 1 || tmp == 2)
+ return true;
+ else
+ return false;
+}
+
+static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr,
+ enum amd_ip_block_type client)
+{
+ if (client == AMD_IP_BLOCK_TYPE_GFX)
+ return vega12_is_gfx_on(hwmgr);
+ else /* for other ip, to do */
+ return true;
+}
+
static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
{
struct vega12_hwmgr *data =
@@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr,
bool enable)
.register_irq_handlers = smu9_register_irq_handlers,
.start_thermal_controller = vega12_start_thermal_controller,
.powergate_gfx = vega12_gfx_off_control,
+ .is_hw_ip_on = vega12_is_hw_ip_on,
};
int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
--
1.9.1
___
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[PATCH 1/3] drm/amd/pp: Delete duplicated interface in hwmgr_func
gfx off support in smu can be via powergate_gfx interface.
so remove the gfx_off_control interface.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 1 -
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index a63e006..26d130a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1185,7 +1185,6 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr,
bool bgate)
.dynamic_state_management_disable = smu10_disable_dpm_tasks,
.powergate_mmhub = smu10_powergate_mmhub,
.smus_notify_pwe = smu10_smus_notify_pwe,
- .gfx_off_control = smu10_gfx_off_control,
.display_clock_voltage_request = smu10_display_clock_voltage_request,
.powergate_gfx = smu10_gfx_off_control,
};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 7e58a0d..88f4517 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -298,7 +298,6 @@ struct pp_hwmgr_func {
int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock);
int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct
amd_pp_simple_clock_info *clocks);
- int (*gfx_off_control)(struct pp_hwmgr *hwmgr, bool enable);
int (*power_off_asic)(struct pp_hwmgr *hwmgr);
int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type
type, uint32_t mask);
int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type
type, char *buf);
--
1.9.1
___
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[PATCH 2/3] drm/amd/pp: Export interface to help check hw power state
As more hw ip pg feature have been enabled(especial gfx off),
so need to check the hw power state before read/write registers
through mmio.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 21 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 6a41b81..3b5b2de 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -269,6 +269,7 @@ struct amd_pm_funcs {
int (*get_display_mode_validation_clocks)(void *handle,
struct amd_pp_simple_clock_info *clocks);
int (*notify_smu_enable_pwe)(void *handle);
+ bool (*is_hw_ip_on)(void *handle, enum amd_ip_block_type client);
};
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index da4ebff..c50164e 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1243,6 +1243,26 @@ static int pp_notify_smu_enable_pwe(void *handle)
return 0;
}
+static bool pp_is_hw_ip_on(void *handle, enum amd_ip_block_type client)
+{
+ struct pp_hwmgr *hwmgr = handle;
+ bool ret;
+
+ if (!hwmgr || !hwmgr->pm_en)
+ return true;
+
+ if (hwmgr->hwmgr_func->is_hw_ip_on == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return true;
+ }
+
+ mutex_lock(&hwmgr->smu_lock);
+ ret = hwmgr->hwmgr_func->is_hw_ip_on(hwmgr, client);
+ mutex_unlock(&hwmgr->smu_lock);
+
+ return ret;
+}
+
static const struct amd_pm_funcs pp_dpm_funcs = {
.load_firmware = pp_dpm_load_fw,
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1274,6 +1294,7 @@ static int pp_notify_smu_enable_pwe(void *handle)
.odn_edit_dpm_table = pp_odn_edit_dpm_table,
.set_power_limit = pp_set_power_limit,
.get_power_limit = pp_get_power_limit,
+ .is_hw_ip_on = pp_is_hw_ip_on,
/* export to DC */
.get_sclk = pp_dpm_get_sclk,
.get_mclk = pp_dpm_get_mclk,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 88f4517..3aca3a3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -328,6 +328,7 @@ struct pp_hwmgr_func {
int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
+ bool (*is_hw_ip_on)(struct pp_hwmgr *hwmgr, enum amd_ip_block_type
client);
};
struct pp_table_func {
--
1.9.1
___
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[PATCH 4/4] drm/amdgpu: Disable gfx off if VCN is busy
this patch is a workaround for the gpu hang
at video end time if play video with gfx off enabled.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 798648a..d68039f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -214,6 +214,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct
*work)
fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg);
if (fences == 0) {
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_VCN, true);
if (adev->pm.dpm_enabled)
amdgpu_dpm_enable_uvd(adev, false);
else
@@ -230,6 +231,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
if (set_clocks) {
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_VCN, false);
if (adev->pm.dpm_enabled)
amdgpu_dpm_enable_uvd(adev, true);
else
--
1.9.1
___
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[PATCH 3/4] drm/amdgpu: gfx ip ctrl gfx off via amdgpu_gfx_off_ctrl
use amdgpu_gfx_off_ctrl function so driver can arbitrate
whether the gfx ip can be power off or power on.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9f8e267..d861bfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1828,8 +1828,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device
*adev)
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
- if (adev->powerplay.pp_funcs->set_powergating_by_smu)
- amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false);
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_GFX, false);
r = adev->ip_blocks[i].version->funcs->hw_fini((void
*)adev);
/* XXX handle errors */
if (r) {
@@ -2013,8 +2012,7 @@ static int amdgpu_device_ip_suspend_phase2(struct
amdgpu_device *adev)
}
/* call smu to disable gfx off feature first when suspend */
- if (adev->powerplay.pp_funcs->set_powergating_by_smu)
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX,
false);
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_GFX, false);
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.valid)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ef00d14..c3d8030 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3783,13 +3783,11 @@ static int gfx_v9_0_set_powergating_state(void *handle,
gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
/* set gfx off through smu */
- if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
- amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true);
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_GFX, true);
break;
case CHIP_VEGA12:
/* set gfx off through smu */
- if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
- amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true);
+ amdgpu_gfx_off_ctrl(adev, AMD_IP_BLOCK_TYPE_GFX, true);
break;
default:
break;
--
1.9.1
___
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[PATCH 2/4] drm/amdgpu: Put enable gfx off feature to a delay thread
delay to enable gfx off feature to avoid gfx on/off frequently
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 6 --
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 318961d..b59ac02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -993,6 +993,7 @@ struct amdgpu_gfx {
boolbin_off;
struct mutexgfx_off_ctrl_mutex;
uint32_tdisable_gfx_off_request;
+ struct delayed_work delay_gfx_off_enable;
/* pipe reservation */
struct mutexpipe_reserve_mutex;
DECLARE_BITMAP (pipe_reserve_bitmap,
AMDGPU_MAX_COMPUTE_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b40ce6f..9f8e267 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1925,6 +1925,20 @@ static void
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
DRM_ERROR("ib ring test failed (%d).\n", r);
}
+static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
+{
+ struct amdgpu_device *adev =
+ container_of(work, struct amdgpu_device,
gfx.delay_gfx_off_enable.work);
+
+ mutex_lock(&adev->gfx.gfx_off_ctrl_mutex);
+ if (adev->gfx.bready_for_off && !adev->gfx.bin_off
+ && adev->gfx.disable_gfx_off_request) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.bin_off = true;
+ }
+ mutex_unlock(&adev->gfx.gfx_off_ctrl_mutex);
+}
+
/**
* amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
*
@@ -2394,6 +2408,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
INIT_DELAYED_WORK(&adev->late_init_work,
amdgpu_device_ip_late_init_func_handler);
+ INIT_DELAYED_WORK(&adev->gfx.delay_gfx_off_enable,
+ amdgpu_device_delay_enable_gfx_off);
adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true :
false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 68fe9c8..1ea1e8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -26,6 +26,9 @@
#include "amdgpu.h"
#include "amdgpu_gfx.h"
+/* 0.5 second timeout */
+#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(500)
+
/*
* GPU scratch registers helpers function.
*/
@@ -384,8 +387,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, enum
amd_ip_block_type clie
*/
if (adev->gfx.bready_for_off && !adev->gfx.bin_off
&& !adev->gfx.disable_gfx_off_request) {
- if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
- adev->gfx.bin_off = true;
+ schedule_delayed_work(&adev->gfx.delay_gfx_off_enable,
GFX_OFF_DELAY_ENABLE);
} else if (!enable && adev->gfx.bin_off) {
if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false))
adev->gfx.bin_off = false;
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/4] drm/amdgpu: Add amdgpu_gfx_off_ctrl function
This funciton as the entry of gfx off ctrl feature.
we arbitrat gfx off feature enable/disable in this
function.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 52 ++
3 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5b7bb58..318961d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -988,6 +988,11 @@ struct amdgpu_gfx {
/* NGG */
struct amdgpu_ngg ngg;
+ /* gfx off */
+ boolbready_for_off;
+ boolbin_off;
+ struct mutexgfx_off_ctrl_mutex;
+ uint32_tdisable_gfx_off_request;
/* pipe reservation */
struct mutexpipe_reserve_mutex;
DECLARE_BITMAP (pipe_reserve_bitmap,
AMDGPU_MAX_COMPUTE_QUEUES);
@@ -1815,6 +1820,8 @@ void amdgpu_device_program_register_sequence(struct
amdgpu_device *adev,
const u32 array_size);
bool amdgpu_device_is_px(struct drm_device *dev);
+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev,
+ enum amd_ip_block_type client, bool enable);
/* atpx handler */
#if defined(CONFIG_VGA_SWITCHEROO)
void amdgpu_register_atpx_handler(void);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 745f760..b40ce6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2367,6 +2367,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(&adev->gfx.gpu_clock_mutex);
mutex_init(&adev->srbm_mutex);
mutex_init(&adev->gfx.pipe_reserve_mutex);
+ mutex_init(&adev->gfx.gfx_off_ctrl_mutex);
mutex_init(&adev->grbm_idx_mutex);
mutex_init(&adev->mn_lock);
mutex_init(&adev->virt.vf_errors.lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 239bf2a..68fe9c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -340,3 +340,55 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device
*adev)
&ring->mqd_gpu_addr,
&ring->mqd_ptr);
}
+
+/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
+ *
+ * @adev: amdgpu_device pointer
+ * @enum amd_ip_block_type gfx ip decide when to set ready for gfx off feature
+ * other clients send disable gfx off feature request
+ * @bool enable
+ *
+ * if gfx ip is ready for power off gfx ip, and no other clients's request for
+ * disable gfx off feature, driver will call smu to enable gfx off immediately.
+ * otherwise, driver will wait until the clients cancel the requests.
+ */
+
+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, enum amd_ip_block_type
client, bool enable)
+{
+ if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK))
+ return; /* gfx off feature is not supported or disabled by user
via module parameter */
+
+ if (!adev->powerplay.pp_funcs->set_powergating_by_smu)
+ return; /* currently gfx off feature need smu support*/
+
+ mutex_lock(&adev->gfx.gfx_off_ctrl_mutex);
+ if (client == AMD_IP_BLOCK_TYPE_GFX) {
+ adev->gfx.bready_for_off = enable ? true : false; /*true, gfx
ip is ready to enable gfx off feature */
+ } else {
+ if (!enable) /* false : reveive one disable gfx off requests
from other clients*/
+ adev->gfx.disable_gfx_off_request++;
+ else if (adev->gfx.disable_gfx_off_request > 0)
+ adev->gfx.disable_gfx_off_request--;
+ }
+
+/* *
+ * we can enable gfx off feature when meet the following conditions:
+ * 1. gfx off feature is supported by hw
+ * 2. gfx ip is ready to enable gfx off feature
+ * 3. no other clients have requests to disable gfx off
+ * 4. gfx off feature is not enabled
+ * For disable gfx off feature
+ * 1. gfx off feature is supported by hw
+ * 2. receive disable gfx off requests
+ * 3. gfx off feature is enabled
+ */
+ if (adev->gfx.bready_for_off && !adev->gfx.bin_off
+ && !adev->gfx.disable_gfx_off_request) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.bin_off = true;
+ } else if (!enable && adev->gfx.bin_off) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, false))
+ adev->gfx.bin_off = false;
+ }
+ mutex_unlock(&adev->gfx.gfx_off_ctrl_mutex);
+}
--
1.9.1
___
[PATCH 5/5] drm/amgpu/acp: Implement set_powergating_state for acp
so driver can powergate acp block after asic initialized
to save power.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index b5b66c3..297a549 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -514,6 +514,12 @@ static int acp_set_clockgating_state(void *handle,
static int acp_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ bool enable = state == AMD_PG_STATE_GATE ? true : false;
+
+ if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
enable);
+
return 0;
}
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/5] drm/amdgpu/acp: Powrgate acp via smu
Call smu to power gate/ungate acp instand of only
powr down acp tiles in acp block.
when smu power gate acp:
smu will turn off clock, power down acp tiles,check and
enter in ULV state.
when smu ungate acp:
smu will exit ulv, turn on clocks, power on acp tiles.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 134 ++--
1 file changed, 22 insertions(+), 112 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index bab8fab..b5b66c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -116,136 +116,47 @@ static int acp_sw_fini(void *handle)
return 0;
}
-/* power off a tile/block within ACP */
-static int acp_suspend_tile(void *cgs_dev, int tile)
-{
- u32 val = 0;
- u32 count = 0;
-
- if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) {
- pr_err("Invalid ACP tile : %d to suspend\n", tile);
- return -1;
- }
-
- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile);
- val &= ACP_TILE_ON_MASK;
-
- if (val == 0x0) {
- val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
- val = val | (1 << tile);
- cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
- cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG,
- 0x500 + tile);
-
- count = ACP_TIMEOUT_LOOP;
- while (true) {
- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0
- + tile);
- val = val & ACP_TILE_ON_MASK;
- if (val == ACP_TILE_OFF_MASK)
- break;
- if (--count == 0) {
- pr_err("Timeout reading ACP PGFSM status\n");
- return -ETIMEDOUT;
- }
- udelay(100);
- }
-
- val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
-
- val |= ACP_TILE_OFF_RETAIN_REG_MASK;
- cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
- }
- return 0;
-}
-
-/* power on a tile/block within ACP */
-static int acp_resume_tile(void *cgs_dev, int tile)
-{
- u32 val = 0;
- u32 count = 0;
-
- if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) {
- pr_err("Invalid ACP tile to resume\n");
- return -1;
- }
-
- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile);
- val = val & ACP_TILE_ON_MASK;
-
- if (val != 0x0) {
- cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG,
- 0x600 + tile);
- count = ACP_TIMEOUT_LOOP;
- while (true) {
- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0
- + tile);
- val = val & ACP_TILE_ON_MASK;
- if (val == 0x0)
- break;
- if (--count == 0) {
- pr_err("Timeout reading ACP PGFSM status\n");
- return -ETIMEDOUT;
- }
- udelay(100);
- }
- val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
- if (tile == ACP_TILE_P1)
- val = val & (ACP_TILE_P1_MASK);
- else if (tile == ACP_TILE_P2)
- val = val & (ACP_TILE_P2_MASK);
-
- cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
- }
- return 0;
-}
-
struct acp_pm_domain {
- void *cgs_dev;
+ void *adev;
struct generic_pm_domain gpd;
};
static int acp_poweroff(struct generic_pm_domain *genpd)
{
- int i, ret;
struct acp_pm_domain *apd;
+ struct amdgpu_device *adev;
apd = container_of(genpd, struct acp_pm_domain, gpd);
if (apd != NULL) {
- /* Donot return abruptly if any of power tile fails to suspend.
-* Log it and continue powering off other tile
-*/
- for (i = 4; i >= 0 ; i--) {
- ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i);
- if (ret)
- pr_err("ACP tile %d tile suspend failed\n", i);
- }
+ adev = apd->adev;
+ /* call smu to POWER GATE ACP block
+* smu will
+* 1. turn off the acp clock
+* 2. power off the acp tiles
+* 3. check and enter ulv state
+*/
+ if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+ amdgpu_d
[PATCH 3/5] drm/amd/amdgpu: Enabling Power Gating for Stoney platform
From: Vijendar Mukunda
Removed condition checks to skip the power gating feature for
stoney platform.
Signed-off-by: Vijendar Mukunda
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 53 -
1 file changed, 25 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index d4d1738..bab8fab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -301,20 +301,19 @@ static int acp_hw_init(void *handle)
acp_base = adev->rmmio_base;
- if (adev->asic_type != CHIP_STONEY) {
- adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain),
GFP_KERNEL);
- if (adev->acp.acp_genpd == NULL)
- return -ENOMEM;
- adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
- adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
- adev->acp.acp_genpd->gpd.power_on = acp_poweron;
+ adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
+ if (adev->acp.acp_genpd == NULL)
+ return -ENOMEM;
+ adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
+ adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
+ adev->acp.acp_genpd->gpd.power_on = acp_poweron;
- adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device;
- pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
- }
+ adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device;
+
+ pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
GFP_KERNEL);
@@ -431,17 +430,17 @@ static int acp_hw_init(void *handle)
if (r)
return r;
- if (adev->asic_type != CHIP_STONEY) {
- for (i = 0; i < ACP_DEVS ; i++) {
- dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
- r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
- if (r) {
- dev_err(dev, "Failed to add dev to genpd\n");
- return r;
- }
+
+ for (i = 0; i < ACP_DEVS ; i++) {
+ dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
+ r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
+ if (r) {
+ dev_err(dev, "Failed to add dev to genpd\n");
+ return r;
}
}
+
/* Assert Soft reset of ACP */
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
@@ -499,7 +498,7 @@ static int acp_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* return early if no ACP */
- if (!adev->acp.acp_cell) {
+ if (!adev->acp.acp_genpd) {
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
false);
return 0;
}
@@ -540,19 +539,17 @@ static int acp_hw_fini(void *handle)
udelay(100);
}
- if (adev->acp.acp_genpd) {
- for (i = 0; i < ACP_DEVS ; i++) {
- dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
- ret = pm_genpd_remove_device(dev);
- /* If removal fails, dont giveup and try rest */
- if (ret)
- dev_err(dev, "remove dev from genpd failed\n");
- }
- kfree(adev->acp.acp_genpd);
+ for (i = 0; i < ACP_DEVS ; i++) {
+ dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
+ ret = pm_genpd_remove_device(dev);
+ /* If removal fails, dont giveup and try rest */
+ if (ret)
+ dev_err(dev, "remove dev from genpd failed\n");
}
mfd_remove_devices(adev->acp.parent);
kfree(adev->acp.acp_res);
+ kfree(adev->acp.acp_genpd);
kfree(adev->acp.acp_cell);
return 0;
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/5] drm/amd/pp: Add ACP PG support in SMU
when ACP block not enabled, we power off
acp block to save power.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c| 18 ++
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 21 -
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h| 1 +
3 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 7a646f9..da4ebff 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1181,6 +1181,21 @@ static int pp_dpm_powergate_gfx(void *handle, bool gate)
return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
}
+static void pp_dpm_powergate_acp(void *handle, bool gate)
+{
+ struct pp_hwmgr *hwmgr = handle;
+
+ if (!hwmgr || !hwmgr->pm_en)
+ return;
+
+ if (hwmgr->hwmgr_func->powergate_acp == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return;
+ }
+
+ hwmgr->hwmgr_func->powergate_acp(hwmgr, gate);
+}
+
static int pp_set_powergating_by_smu(void *handle,
uint32_t block_type, bool gate)
{
@@ -1200,6 +1215,9 @@ static int pp_set_powergating_by_smu(void *handle,
case AMD_IP_BLOCK_TYPE_GFX:
ret = pp_dpm_powergate_gfx(handle, gate);
break;
+ case AMD_IP_BLOCK_TYPE_ACP:
+ pp_dpm_powergate_acp(handle, gate);
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index 0adfc53..b863704 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -664,8 +664,13 @@ static void smu8_init_power_gate_state(struct pp_hwmgr
*hwmgr)
data->uvd_power_gated = false;
data->vce_power_gated = false;
data->samu_power_gated = false;
+#ifdef CONFIG_DRM_AMD_ACP
data->acp_power_gated = false;
- data->pgacpinit = true;
+#else
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF);
+ data->acp_power_gated = true;
+#endif
+
}
static void smu8_init_sclk_threshold(struct pp_hwmgr *hwmgr)
@@ -1886,6 +1891,19 @@ static int smu8_enable_disable_vce_dpm(struct pp_hwmgr
*hwmgr, bool enable)
}
+static void smu8_dpm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate)
+{
+ struct smu8_hwmgr *data = hwmgr->backend;
+
+ if (data->acp_power_gated == bgate)
+ return;
+
+ if (bgate)
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF);
+ else
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerON);
+}
+
static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
{
struct smu8_hwmgr *data = hwmgr->backend;
@@ -1951,6 +1969,7 @@ static void smu8_dpm_powergate_vce(struct pp_hwmgr
*hwmgr, bool bgate)
.powerdown_uvd = smu8_dpm_powerdown_uvd,
.powergate_uvd = smu8_dpm_powergate_uvd,
.powergate_vce = smu8_dpm_powergate_vce,
+ .powergate_acp = smu8_dpm_powergate_acp,
.get_mclk = smu8_dpm_get_mclk,
.get_sclk = smu8_dpm_get_sclk,
.patch_boot_state = smu8_dpm_patch_boot_state,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index d3d9626..7e58a0d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -247,6 +247,7 @@ struct pp_hwmgr_func {
int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
+ void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
int (*power_state_set)(struct pp_hwmgr *hwmgr,
--
1.9.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/5] drm/amdgpu: Power down acp if board uses AZ (v2)
From: Rex Zhu
if board uses AZ rather than ACP, we power down acp
through smu to save power.
v2: handle S3/S4 and hw_fini (Alex)
Signed-off-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 71efcf3..d4d1738 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -289,10 +289,12 @@ static int acp_hw_init(void *handle)
r = amd_acp_hw_init(adev->acp.cgs_device,
ip_block->version->major, ip_block->version->minor);
/* -ENODEV means board uses AZ rather than ACP */
- if (r == -ENODEV)
+ if (r == -ENODEV) {
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
true);
return 0;
- else if (r)
+ } else if (r) {
return r;
+ }
if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
return -EINVAL;
@@ -497,8 +499,10 @@ static int acp_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* return early if no ACP */
- if (!adev->acp.acp_cell)
+ if (!adev->acp.acp_cell) {
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
false);
return 0;
+ }
/* Assert Soft reset of ACP */
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
@@ -556,11 +560,21 @@ static int acp_hw_fini(void *handle)
static int acp_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ /* power up on suspend */
+ if (!adev->acp.acp_cell)
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
false);
return 0;
}
static int acp_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ /* power down again on resume */
+ if (!adev->acp.acp_cell)
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
true);
return 0;
}
--
1.9.1
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