Re: [PATCH 1/2] drm/amdgpu: Moved fault hash table to amdgpu vm
I think I'm missing something. I thought the whole discussion we were having about tracking current and future locations of page tables was about swapping out page tables that are managed by HMM. We currently do swap out page tables that don't have fence on them and that are not managed by HMM. And pipelining that is not a problem today. You're raising some potential problems that I think must be about swapping out page tables that don't have fences on them (otherwise they wouldn't be evicted) and that are managed by HMM. If there is no fence on the page table, no engine that can't handle page faults can depend on the page tables. So we can discard the contents and set the parent page directory entry to invalid. Setting the parent PDE needs to be synchronous so that the GPU doesn't try to access a page table that is no longer there. No pipelining, no problem. Then you came back with an argument "what about engines that don't support page faults". Those engines can't use memory mapped by HMM anyway. And they can't be evicted while they have a fence on them that indicates active usage by such an engine. You seem to see some problems that require not pipelining page table evictions. I still don't understand what the problem is. I think we should have a phone call to sort this out. A few more comments inline, but I think we're misunderstanding each other ... > 5. The new system memory location of the page table is noted in its BO. You mean in the parent page table? You can just invalidate the entry in the parent page table and let it fault. >>> I'm repeating myself, but exactly that is what won't work. >>> >>> See we still have engines which can't handle page faults which uses >>> the same VM at the same time. This means that we can't just fault in >>> page tables. >> And I don't understand why that is a problem. Those clients rely on >> fences to keep their BOs resident, including the page tables. Are you >> planning to change that? > > No, but how do you want to swap out page tables when there is a fence added? I don't. That's my point. If the page table has fences on it, it can't be swapped out. So there is no problem. > > Or do you want to stop adding fences to page tables for engines with > recoverable faults? Yes, that was my assumption, coming from a KFD perspective where with HMM we want to get away from our eviction fences that enforce BO residency, including page tables. Right now signaling an eviction fence means stopping user mode queues. We want to stop doing that. If page tables get evicted, that's fine as long as those virtual addresses aren't accessed. Once an access happens, the page table needs to be restored or recreated. Once that's done, the retrying hardware block will get a successful translation and continue executing. > > I think that is completely unrealistic considering the performance > penalty of faults. I agree that evicting a page table that's in active use is bad. For amdgpu_cs you can prevent that with a fence, no problem. But a fence is not a good way to prevent that for KFD, because it forces us to keep using our eviction fence and preempting user mode queues on evictions. You see, the eviction fence does not prevent the page table from being evicted, but it forces us to preempt all our queues when an eviction happens. That is a worse performance penalty than dealing with a page fault because the page fault is much more selective. A page fault can interrupt a compute shader at wave granularity. An preemption interrupts compute shaders with process granularity and at much longer time scales. For KFD I would try to find a better way to avoid evictions of page tables, maybe by bumping them up in the LRU at appropriate times. But even without any such improvements, page faults are still better for KFD than the current eviction-fence-based approach. Regards, Felix > > At least for currently available hardware we should limit page faults to > be used in as few cases as possible, e.g. SVM and userptr. > > Regards, > Christian. From: Koenig, Christian Sent: Wednesday, September 12, 2018 11:59 AM To: Kuehling, Felix; Zeng, Oak; Oak Zeng; amd-gfx@lists.freedesktop.org; Yang, Philip Subject: Re: [PATCH 1/2] drm/amdgpu: Moved fault hash table to amdgpu vm Am 12.09.2018 um 17:29 schrieb Felix Kuehling: > On 2018-09-12 02:56 AM, Christian König wrote: >> Am 12.09.2018 um 00:00 schrieb Felix Kuehling: >>> On 2018-09-11 03:19 AM, Christian König wrote: Hi Felix, let me try to explain the problem on an example: 1. We have a running job which needs recoverable page faults for accessing the process address space. 2. We run into memory pressure on VRAM and start to evict things. 3. A page tables of the running job is picked up for eviction. 4. We schedule a copy command to move the content of the page table to system memory. >>> I
Re: [PATCH 1/8] drm/amdgpu: add some VM PD/PT iterators v2
On 09/12/2018 04:54 PM, Christian König wrote:
Both a leaf as well as dfs iterator to walk over all the PDs/PTs. v2:
update comments and fix for_each_amdgpu_vm_pt_dfs_safe Signed-off-by:
Christian König
Reviewed-by: Junwei Zhang
--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 224
+ 1 file changed, 224 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index
136b00412dc8..787a200cf796 100644 ---
a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -355,6 +355,230 @@ static
struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
return list_first_entry(>va, struct amdgpu_vm_pt,
base.bo_list); } +/** + * amdgpu_vm_pt_cursor - state for
for_each_amdgpu_vm_pt + */ +struct amdgpu_vm_pt_cursor { + uint64_t
pfn; + struct amdgpu_vm_pt *parent; + struct amdgpu_vm_pt *entry; +
unsigned level; +}; + +/** + * amdgpu_vm_pt_start - start PD/PT walk +
* + * @adev: amdgpu_device pointer + * @vm: amdgpu_vm structure + *
@start: start address of the walk + * @cursor: state to initialize + *
+ * Initialize a amdgpu_vm_pt_cursor to start a walk. + */ +static
void amdgpu_vm_pt_start(struct amdgpu_device *adev, + struct amdgpu_vm
*vm, uint64_t start, + struct amdgpu_vm_pt_cursor *cursor) +{ +
cursor->pfn = start; + cursor->parent = NULL; + cursor->entry =
>root; + cursor->level = adev->vm_manager.root_level; +} + +/** +
* amdgpu_vm_pt_descendant - go to child node + * + * @adev:
amdgpu_device pointer + * @cursor: current state + * + * Walk to the
child node of the current node. + * Returns: + * True if the walk was
possible, false otherwise. + */ +static bool
amdgpu_vm_pt_descendant(struct amdgpu_device *adev, + struct
amdgpu_vm_pt_cursor *cursor) +{ + unsigned num_entries, shift, idx; +
+ if (!cursor->entry->entries) + return false; + +
BUG_ON(!cursor->entry->base.bo); + num_entries =
amdgpu_vm_num_entries(adev, cursor->level); + shift =
amdgpu_vm_level_shift(adev, cursor->level); + + ++cursor->level; + idx
= (cursor->pfn >> shift) % num_entries; + cursor->parent =
cursor->entry; + cursor->entry = >entry->entries[idx]; +
return true; +} + +/** + * amdgpu_vm_pt_sibling - go to sibling node +
* + * @adev: amdgpu_device pointer + * @cursor: current state + * + *
Walk to the sibling node of the current node. + * Returns: + * True if
the walk was possible, false otherwise. + */ +static bool
amdgpu_vm_pt_sibling(struct amdgpu_device *adev, + struct
amdgpu_vm_pt_cursor *cursor) +{ + unsigned shift, num_entries; + + /*
Root doesn't have a sibling */ + if (!cursor->parent) + return false;
+ + /* Go to our parents and see if we got a sibling */ + shift =
amdgpu_vm_level_shift(adev, cursor->level - 1); + num_entries =
amdgpu_vm_num_entries(adev, cursor->level - 1); + + if (cursor->entry
== >parent->entries[num_entries - 1]) + return false; + +
cursor->pfn += 1ULL << shift; + cursor->pfn &= ~((1ULL << shift) - 1);
+ ++cursor->entry; + return true; +} + +/** + * amdgpu_vm_pt_ancestor
- go to parent node + * + * @cursor: current state + * + * Walk to the
parent node of the current node. + * Returns: + * True if the walk was
possible, false otherwise. + */ +static bool
amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor) +{ + if
(!cursor->parent) + return false; + + --cursor->level; + cursor->entry
= cursor->parent; + cursor->parent =
amdgpu_vm_pt_parent(cursor->parent); + return true; +} + +/** + *
amdgpu_vm_pt_next - get next PD/PT in hieratchy + * + * @adev:
amdgpu_device pointer + * @cursor: current state + * + * Walk the
PD/PT tree to the next node. + */ +static void
amdgpu_vm_pt_next(struct amdgpu_device *adev, + struct
amdgpu_vm_pt_cursor *cursor) +{ + /* First try a newborn child */ + if
(amdgpu_vm_pt_descendant(adev, cursor)) + return; + + /* If that
didn't worked try to find a sibling */ + while
(!amdgpu_vm_pt_sibling(adev, cursor)) { + /* No sibling, go to our
parents and grandparents */ + if (!amdgpu_vm_pt_ancestor(cursor)) { +
cursor->pfn = ~0ll; + return; + } + } +} + +/** + *
amdgpu_vm_pt_first_leaf - get first leaf PD/PT + * + * @adev:
amdgpu_device pointer + * @vm: amdgpu_vm structure + * @start: start
addr of the walk + * @cursor: state to initialize + * + * Start a walk
and go directly to the leaf node. + */ +static void
amdgpu_vm_pt_first_leaf(struct amdgpu_device *adev, + struct amdgpu_vm
*vm, uint64_t start, + struct amdgpu_vm_pt_cursor *cursor) +{ +
amdgpu_vm_pt_start(adev, vm, start, cursor); + while
(amdgpu_vm_pt_descendant(adev, cursor)); +} + +/** + *
amdgpu_vm_pt_next_leaf - get next leaf PD/PT + * + * @adev:
amdgpu_device pointer + * @cursor: current state + * + * Walk the
PD/PT tree to the next leaf node. + */ +static void
amdgpu_vm_pt_next_leaf(struct amdgpu_device *adev, + struct
amdgpu_vm_pt_cursor *cursor) +{ + amdgpu_vm_pt_next(adev, cursor); +
while (amdgpu_vm_pt_descendant(adev, cursor)); +}
Re: [PATCH 4/8] drm/amdgpu: use the DFS iterator in amdgpu_vm_invalidate_pds v2
On 09/12/2018 04:54 PM, Christian König wrote:
Less code and easier to maintain.
v2: rename the function as well
Signed-off-by: Christian König
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 32
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a0a30416a490..c0c97b1425fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1370,37 +1370,22 @@ static void amdgpu_vm_update_pde(struct
amdgpu_pte_update_params *params,
}
/*
- * amdgpu_vm_invalidate_level - mark all PD levels as invalid
+ * amdgpu_vm_invalidate_pds - mark all PDs as invalid
*
* @adev: amdgpu_device pointer
* @vm: related vm
- * @parent: parent PD
- * @level: VMPT level
*
* Mark all PD level as invalid after an error.
*/
-static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- struct amdgpu_vm_pt *parent,
- unsigned level)
+static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
+struct amdgpu_vm *vm)
{
- unsigned pt_idx, num_entries;
-
- /*
-* Recurse into the subdirectories. This recursion is harmless because
-* we only have a maximum of 5 layers.
-*/
- num_entries = amdgpu_vm_num_entries(adev, level);
- for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) {
- struct amdgpu_vm_pt *entry = >entries[pt_idx];
-
- if (!entry->base.bo)
- continue;
+ struct amdgpu_vm_pt_cursor cursor;
+ struct amdgpu_vm_pt *entry;
- if (!entry->base.moved)
+ for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry)
+ if (entry->base.bo && !entry->base.moved)
amdgpu_vm_bo_relocated(>base);
- amdgpu_vm_invalidate_level(adev, vm, entry, level + 1);
- }
}
/*
@@ -1497,8 +1482,7 @@ int amdgpu_vm_update_directories(struct amdgpu_device
*adev,
return 0;
error:
- amdgpu_vm_invalidate_level(adev, vm, >root,
- adev->vm_manager.root_level);
+ amdgpu_vm_invalidate_pds(adev, vm);
amdgpu_job_free(job);
return r;
}
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/3] [RFC]drm: add syncobj timeline support v4
On 2018年09月12日 19:05, Christian König wrote:
Am 12.09.2018 um 12:20 schrieb zhoucm1:
[SNIP]
Drop the term semaphore here, better use syncobj.
This is from VK_KHR_timeline_semaphore extension describe, not my
invention, I just quote it. In kernel side, we call syncobj, in UMD,
they still call semaphore.
Yeah, but we don't care about close source UMD names in the kernel and'
the open source UMD calls it syncobj as well.
[SNIP]
+static void drm_syncobj_find_signal_pt_for_wait_pt(struct
drm_syncobj *syncobj,
+ struct drm_syncobj_wait_pt *wait_pt)
+{
That whole approach still looks horrible complicated to me.
It's already very close to what you said before.
Especially the separation of signal and wait pt is completely
unnecessary as far as I can see.
When a wait pt is requested we just need to search for the signal
point which it will trigger.
Yeah, I tried this, but when I implement cpu wait ioctl on specific
point, we need a advanced wait pt fence, otherwise, we could still
need old syncobj cb.
Why? I mean you just need to call drm_syncobj_find_fence() and when
that one returns NULL you use wait_event_*() to wait for a signal
point >= your wait point to appear and try again.
e.g. when there are 3 syncobjs(A,B,C) to wait, all syncobjABC have no
fence yet, as you said, during drm_syncobj_find_fence(A) is working on
wait_event, syncobjB and syncobjC could already be signaled, then we
don't know which one is first signaled, which is need when wait ioctl
returns.
Back to my implementation, it already fixes all your concerns before,
and can be able to easily used in wait_ioctl. When you feel that is
complicated, I guess that is because we merged all logic to that and
much clean up in one patch. In fact, it already is very simple,
timeline_init/fini, create signal/wait_pt, find signal_pt for wait_pt,
garbage collection, just them.
Thanks,
David Zhou
Regards,
Christian.
Thanks,
David Zhou
Regards,
Christian.
+ struct drm_syncobj_timeline *timeline =
>syncobj_timeline;
+ struct drm_syncobj_signal_pt *signal_pt;
+ int ret;
+
+ if (wait_pt->signal_pt_fence) {
+ return;
+ } else if ((syncobj->type == DRM_SYNCOBJ_TYPE_TIMELINE) &&
+ (wait_pt->value <= timeline->timeline)) {
+ dma_fence_signal(_pt->base.base);
+ rb_erase(_pt->node,
+ >wait_pt_tree);
+ RB_CLEAR_NODE(_pt->node);
+ dma_fence_put(_pt->base.base);
+ return;
+ }
+
+ list_for_each_entry(signal_pt, >signal_pt_list,
list) {
+ if (wait_pt->value < signal_pt->value)
+ continue;
+ if ((syncobj->type == DRM_SYNCOBJ_TYPE_NORMAL) &&
+ (wait_pt->value != signal_pt->value))
+ continue;
+ wait_pt->signal_pt_fence =
dma_fence_get(_pt->base->base);
+ ret = dma_fence_add_callback(wait_pt->signal_pt_fence,
+ _pt->wait_cb,
+ wait_pt_func);
+ if (ret == -ENOENT) {
+ dma_fence_signal(_pt->base.base);
+ dma_fence_put(wait_pt->signal_pt_fence);
+ wait_pt->signal_pt_fence = NULL;
+ rb_erase(_pt->node,
+ >wait_pt_tree);
+ RB_CLEAR_NODE(_pt->node);
+ dma_fence_put(_pt->base.base);
+ } else if (ret < 0) {
+ dma_fence_put(wait_pt->signal_pt_fence);
+ DRM_ERROR("add callback error!");
+ } else {
+ /* after adding callback, remove from rb tree */
+ rb_erase(_pt->node,
+ >wait_pt_tree);
+ RB_CLEAR_NODE(_pt->node);
+ }
+ return;
+ }
+ /* signaled pt was released */
+ if (!wait_pt->signal_pt_fence && (wait_pt->value <=
+ timeline->signal_point)) {
+ dma_fence_signal(_pt->base.base);
+ rb_erase(_pt->node,
+ >wait_pt_tree);
+ RB_CLEAR_NODE(_pt->node);
+ dma_fence_put(_pt->base.base);
+ }
}
-void drm_syncobj_add_callback(struct drm_syncobj *syncobj,
- struct drm_syncobj_cb *cb,
- drm_syncobj_func_t func)
+static int drm_syncobj_timeline_create_signal_pt(struct
drm_syncobj *syncobj,
+ struct dma_fence *fence,
+ u64 point)
{
+ struct drm_syncobj_signal_pt *signal_pt =
+ kzalloc(sizeof(struct drm_syncobj_signal_pt), GFP_KERNEL);
+ struct drm_syncobj_signal_pt *tail_pt;
+ struct dma_fence **fences;
+ struct rb_node *node;
+ struct drm_syncobj_wait_pt *tail_wait_pt = NULL;
+ int num_fences = 0;
+ int ret = 0, i;
+
+ if (!signal_pt)
+ return -ENOMEM;
+ if (syncobj->syncobj_timeline.signal_point >= point) {
+ DRM_WARN("A later signal is ready!");
+ goto out;
+ }
+ if (!fence)
+ goto out;
+
+ fences = kmalloc_array(sizeof(void *), 2, GFP_KERNEL);
+ if (!fences)
+ goto out;
+ fences[num_fences++] =
Re: [PATCH 2/6] drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10
On 2018-09-12 09:55 PM, Alex Deucher wrote:
> On Wed, Sep 12, 2018 at 9:45 PM Felix Kuehling wrote:
>> From: Emily Deng
>>
>> Correct the format
>>
>> For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
>> same setting with host driver, or it will happen conflicts.
>>
>> Signed-off-by: Emily Deng
>> Acked-by: Alex Deucher
>> Signed-off-by: Felix Kuehling
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 9 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 +++
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
>> 3 files changed, 37 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index afa9e77..e60de88 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -420,6 +420,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
>> AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xE8,
>> AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9,
>>
>> + /* For vega10 sriov, the sdma doorbell must be fixed as follow
>> +* to keep the same setting with host driver, or it will
>> +* happen conflicts
>> +*/
>> + AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0= 0xF0,
>> + AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
>> + AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1= 0xF2,
>> + AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
>> +
>> /* Interrupt handler */
>> AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy
>> interrupt ring buffer */
>> AMDGPU_DOORBELL64_IH_RING1= 0xF5, /* For page
>> migration request log */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> index bf0b012..7a165a9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> @@ -181,14 +181,25 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device
>> *adev)
>> * process in case of 64-bit doorbells so we
>> * can use each doorbell assignment twice.
>> */
>> - gpu_resources.sdma_doorbell[0][i] =
>> - AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
>> - gpu_resources.sdma_doorbell[0][i+1] =
>> - AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i
>> >> 1);
>> - gpu_resources.sdma_doorbell[1][i] =
>> - AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
>> - gpu_resources.sdma_doorbell[1][i+1] =
>> - AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i
>> >> 1);
>> + if (adev->asic_type == CHIP_VEGA10) {
>> + gpu_resources.sdma_doorbell[0][i] =
>> +
>> AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
>> + gpu_resources.sdma_doorbell[0][i+1] =
>> +
>> AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
>> + gpu_resources.sdma_doorbell[1][i] =
>> +
>> AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
>> + gpu_resources.sdma_doorbell[1][i+1] =
>> +
>> AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
>> + } else {
>> + gpu_resources.sdma_doorbell[0][i] =
>> + AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i
>> >> 1);
>> + gpu_resources.sdma_doorbell[0][i+1] =
>> + AMDGPU_DOORBELL64_sDMA_ENGINE0 +
>> 0x200 + (i >> 1);
>> + gpu_resources.sdma_doorbell[1][i] =
>> + AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i
>> >> 1);
>> + gpu_resources.sdma_doorbell[1][i+1] =
>> + AMDGPU_DOORBELL64_sDMA_ENGINE1 +
>> 0x200 + (i >> 1);
>> + }
> It would probably make more sense to reverse the conditions here so we
> retain the old behavior for all previous non-vega20 asics rather than
> just vega10. E.g.,
>
> if (vega20) {
> // use new doorbell mapping
> } else {
> // use the old doorbell mapping
> }
>
> Same thing below.
This code is only applicable to GFXv9 and later GPUs with 64-bit
doorbells. It does not apply to GFXv8 and older GPUs anyway. The new
enum names AMDGPU_VEGA10_DOORBELL64_... also imply that we preserve the
old behaviour on Vega10 only. I think the assumption is that future GPUs
will also need bigger doorbell assignments.
Do any of the other GFXv9 GPUs
Re: [PATCH 2/6] drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10
On Wed, Sep 12, 2018 at 9:45 PM Felix Kuehling wrote:
>
> From: Emily Deng
>
> Correct the format
>
> For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
> same setting with host driver, or it will happen conflicts.
>
> Signed-off-by: Emily Deng
> Acked-by: Alex Deucher
> Signed-off-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 9 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 +++
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
> 3 files changed, 37 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index afa9e77..e60de88 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -420,6 +420,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
> AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xE8,
> AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9,
>
> + /* For vega10 sriov, the sdma doorbell must be fixed as follow
> +* to keep the same setting with host driver, or it will
> +* happen conflicts
> +*/
> + AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0= 0xF0,
> + AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
> + AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1= 0xF2,
> + AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
> +
> /* Interrupt handler */
> AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy
> interrupt ring buffer */
> AMDGPU_DOORBELL64_IH_RING1= 0xF5, /* For page
> migration request log */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index bf0b012..7a165a9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -181,14 +181,25 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device
> *adev)
> * process in case of 64-bit doorbells so we
> * can use each doorbell assignment twice.
> */
> - gpu_resources.sdma_doorbell[0][i] =
> - AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
> - gpu_resources.sdma_doorbell[0][i+1] =
> - AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i
> >> 1);
> - gpu_resources.sdma_doorbell[1][i] =
> - AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
> - gpu_resources.sdma_doorbell[1][i+1] =
> - AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i
> >> 1);
> + if (adev->asic_type == CHIP_VEGA10) {
> + gpu_resources.sdma_doorbell[0][i] =
> + AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0
> + (i >> 1);
> + gpu_resources.sdma_doorbell[0][i+1] =
> + AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0
> + 0x200 + (i >> 1);
> + gpu_resources.sdma_doorbell[1][i] =
> + AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1
> + (i >> 1);
> + gpu_resources.sdma_doorbell[1][i+1] =
> + AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1
> + 0x200 + (i >> 1);
> + } else {
> + gpu_resources.sdma_doorbell[0][i] =
> + AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i
> >> 1);
> + gpu_resources.sdma_doorbell[0][i+1] =
> + AMDGPU_DOORBELL64_sDMA_ENGINE0 +
> 0x200 + (i >> 1);
> + gpu_resources.sdma_doorbell[1][i] =
> + AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i
> >> 1);
> + gpu_resources.sdma_doorbell[1][i+1] =
> + AMDGPU_DOORBELL64_sDMA_ENGINE1 +
> 0x200 + (i >> 1);
> + }
It would probably make more sense to reverse the conditions here so we
retain the old behavior for all previous non-vega20 asics rather than
just vega10. E.g.,
if (vega20) {
// use new doorbell mapping
} else {
// use the old doorbell mapping
}
Same thing below.
Alex
> }
> /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
> * SDMA, IH and VCN. So don't use them for the CP.
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index df13840..6265361 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -1299,9 +1299,15 @@ static int sdma_v4_0_sw_init(void *handle)
> DRM_INFO("use_doorbell being
[PATCH 3/6] drm/amdkfd: Make the number of SDMA queues variable
From: Shaoyun Liu
Vega20 supports 8 SDMA queues per engine
Signed-off-by: Shaoyun Liu
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 13 -
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 6 --
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 1 -
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 +
4 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 2e844d3..1327816 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -53,6 +53,7 @@ static const struct kfd_device_info kaveri_device_info = {
.needs_iommu_device = true,
.needs_pci_atomics = false,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
static const struct kfd_device_info carrizo_device_info = {
@@ -69,6 +70,7 @@ static const struct kfd_device_info carrizo_device_info = {
.needs_iommu_device = true,
.needs_pci_atomics = false,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
static const struct kfd_device_info raven_device_info = {
@@ -84,6 +86,7 @@ static const struct kfd_device_info raven_device_info = {
.needs_iommu_device = true,
.needs_pci_atomics = true,
.num_sdma_engines = 1,
+ .num_sdma_queues_per_engine = 2,
};
#endif
@@ -101,6 +104,7 @@ static const struct kfd_device_info hawaii_device_info = {
.needs_iommu_device = false,
.needs_pci_atomics = false,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
static const struct kfd_device_info tonga_device_info = {
@@ -116,6 +120,7 @@ static const struct kfd_device_info tonga_device_info = {
.needs_iommu_device = false,
.needs_pci_atomics = true,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
static const struct kfd_device_info fiji_device_info = {
@@ -131,6 +136,7 @@ static const struct kfd_device_info fiji_device_info = {
.needs_iommu_device = false,
.needs_pci_atomics = true,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
static const struct kfd_device_info fiji_vf_device_info = {
@@ -146,6 +152,7 @@ static const struct kfd_device_info fiji_vf_device_info = {
.needs_iommu_device = false,
.needs_pci_atomics = false,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
@@ -162,6 +169,7 @@ static const struct kfd_device_info polaris10_device_info =
{
.needs_iommu_device = false,
.needs_pci_atomics = true,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
static const struct kfd_device_info polaris10_vf_device_info = {
@@ -177,6 +185,7 @@ static const struct kfd_device_info
polaris10_vf_device_info = {
.needs_iommu_device = false,
.needs_pci_atomics = false,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
static const struct kfd_device_info polaris11_device_info = {
@@ -192,6 +201,7 @@ static const struct kfd_device_info polaris11_device_info =
{
.needs_iommu_device = false,
.needs_pci_atomics = true,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
static const struct kfd_device_info vega10_device_info = {
@@ -207,6 +217,7 @@ static const struct kfd_device_info vega10_device_info = {
.needs_iommu_device = false,
.needs_pci_atomics = false,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
static const struct kfd_device_info vega10_vf_device_info = {
@@ -222,9 +233,9 @@ static const struct kfd_device_info vega10_vf_device_info =
{
.needs_iommu_device = false,
.needs_pci_atomics = false,
.num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 2,
};
-
struct kfd_deviceid {
unsigned short did;
const struct kfd_device_info *device_info;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 409..77d56ef 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -109,7 +109,7 @@ static unsigned int get_num_sdma_engines(struct
device_queue_manager *dqm)
unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
{
return dqm->dev->device_info->num_sdma_engines
- * KFD_SDMA_QUEUES_PER_ENGINE;
+ * dqm->dev->device_info->num_sdma_queues_per_engine;
}
void program_sh_mem_settings(struct device_queue_manager *dqm,
@@ -1843,7 +1843,9 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data)
}
for (pipe = 0; pipe < get_num_sdma_engines(dqm); pipe++) {
-
[PATCH 5/6] drm/amdgpu: Add vega20 support on kfd probe
From: Shaoyun Liu Add Vega20 support in amdgpu_amdkfd_device_probe. Signed-off-by: Shaoyun Liu Acked-by: Alex Deucher Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 7a165a9..c733a8f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -79,6 +79,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions(); break; case CHIP_VEGA10: + case CHIP_VEGA20: case CHIP_RAVEN: kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions(); break; -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/6] drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10
From: Emily Deng
Correct the format
For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
same setting with host driver, or it will happen conflicts.
Signed-off-by: Emily Deng
Acked-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 9 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 27 +++
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
3 files changed, 37 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index afa9e77..e60de88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -420,6 +420,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xE8,
AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9,
+ /* For vega10 sriov, the sdma doorbell must be fixed as follow
+* to keep the same setting with host driver, or it will
+* happen conflicts
+*/
+ AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0= 0xF0,
+ AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
+ AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1= 0xF2,
+ AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
+
/* Interrupt handler */
AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy
interrupt ring buffer */
AMDGPU_DOORBELL64_IH_RING1= 0xF5, /* For page
migration request log */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index bf0b012..7a165a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -181,14 +181,25 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
* process in case of 64-bit doorbells so we
* can use each doorbell assignment twice.
*/
- gpu_resources.sdma_doorbell[0][i] =
- AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
- gpu_resources.sdma_doorbell[0][i+1] =
- AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >>
1);
- gpu_resources.sdma_doorbell[1][i] =
- AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
- gpu_resources.sdma_doorbell[1][i+1] =
- AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >>
1);
+ if (adev->asic_type == CHIP_VEGA10) {
+ gpu_resources.sdma_doorbell[0][i] =
+ AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 +
(i >> 1);
+ gpu_resources.sdma_doorbell[0][i+1] =
+ AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 +
0x200 + (i >> 1);
+ gpu_resources.sdma_doorbell[1][i] =
+ AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 +
(i >> 1);
+ gpu_resources.sdma_doorbell[1][i+1] =
+ AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 +
0x200 + (i >> 1);
+ } else {
+ gpu_resources.sdma_doorbell[0][i] =
+ AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >>
1);
+ gpu_resources.sdma_doorbell[0][i+1] =
+ AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200
+ (i >> 1);
+ gpu_resources.sdma_doorbell[1][i] =
+ AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >>
1);
+ gpu_resources.sdma_doorbell[1][i+1] =
+ AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200
+ (i >> 1);
+ }
}
/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
* SDMA, IH and VCN. So don't use them for the CP.
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index df13840..6265361 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1299,9 +1299,15 @@ static int sdma_v4_0_sw_init(void *handle)
DRM_INFO("use_doorbell being set to: [%s]\n",
ring->use_doorbell?"true":"false");
- ring->doorbell_index = (i == 0) ?
- (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
- : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD
offset
+ if (adev->asic_type == CHIP_VEGA10)
+ ring->doorbell_index = (i == 0) ?
+ (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1)
//get DWORD offset
+
[PATCH 4/6] drm/amd: Interface change to support 64 bit page_table_base
From: Shaoyun Liu
amdgpu_gpuvm_get_process_page_dir should return the page table address
in the format expected by the pm4_map_process packet for all ASIC
generations.
Signed-off-by: Shaoyun Liu
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 ++--
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 11 ++-
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c | 3 +--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 4 ++--
9 files changed, 28 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index db93c92..a4e38b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -173,7 +173,7 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device
*adev,
struct amdgpu_vm *vm);
void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm);
void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm);
-uint32_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
+uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
struct kgd_dev *kgd, uint64_t va, uint64_t size,
void *vm, struct kgd_mem **mem,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index b2e45c8..244d983 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -142,7 +142,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum
kgd_engine_type type);
static void set_scratch_backing_va(struct kgd_dev *kgd,
uint64_t va, uint32_t vmid);
static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
- uint32_t page_table_base);
+ uint64_t page_table_base);
static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd);
@@ -874,7 +874,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum
kgd_engine_type type)
}
static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
- uint32_t page_table_base)
+ uint64_t page_table_base)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
@@ -882,7 +882,8 @@ static void set_vm_context_page_table_base(struct kgd_dev
*kgd, uint32_t vmid,
pr_err("trying to set page table base for wrong VMID\n");
return;
}
- WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
+ WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
+ lower_32_bits(page_table_base));
}
static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index dd94b70..9f14991 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -98,7 +98,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum
kgd_engine_type type);
static void set_scratch_backing_va(struct kgd_dev *kgd,
uint64_t va, uint32_t vmid);
static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
- uint32_t page_table_base);
+ uint64_t page_table_base);
static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
@@ -833,7 +833,7 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum
kgd_engine_type type)
}
static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
- uint32_t page_table_base)
+ uint64_t page_table_base)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
@@ -841,7 +841,8 @@ static void set_vm_context_page_table_base(struct kgd_dev
*kgd, uint32_t vmid,
pr_err("trying to set page table base for wrong VMID\n");
return;
}
- WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
+ WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
+ lower_32_bits(page_table_base));
}
static int invalidate_tlbs(struct
[PATCH 0/6] Initial Vega20 support for KFD
This patch series is based on amd-staging-drm-next + the patch series "KFD upstreaming September 2018". Emily Deng (1): drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10 Shaoyun Liu (5): drm/amdgpu: Doorbell assignment for 8 sdma user queue per engine drm/amdkfd: Make the number of SDMA queues variable drm/amd: Interface change to support 64 bit page_table_base drm/amdgpu: Add vega20 support on kfd probe drm/amdkfd: Vega20 bring up on amdkfd side drivers/gpu/drm/amd/amdgpu/amdgpu.h| 23 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 50 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 7 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 7 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 7 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 +++- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 -- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_device.c| 33 ++ .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 18 +--- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 1 - drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c| 1 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 + drivers/gpu/drm/amd/include/kgd_kfd_interface.h| 10 ++--- 20 files changed, 136 insertions(+), 54 deletions(-) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 6/6] drm/amdkfd: Vega20 bring up on amdkfd side
From: Shaoyun Liu
Add Vega20 device IDs, device info and enable it in KFD.
Signed-off-by: Shaoyun Liu
Acked-by: Alex Deucher
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c| 22 ++
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c| 1 +
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 +
8 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index ee49960..e3ef7d9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -642,6 +642,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);
break;
case CHIP_VEGA10:
+ case CHIP_VEGA20:
pcache_info = vega10_cache_info;
num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 1327816..89eec81 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -236,6 +236,22 @@ static const struct kfd_device_info vega10_vf_device_info
= {
.num_sdma_queues_per_engine = 2,
};
+static const struct kfd_device_info vega20_device_info = {
+ .asic_family = CHIP_VEGA20,
+ .max_pasid_bits = 16,
+ .max_no_of_hqd = 24,
+ .doorbell_size = 8,
+ .ih_ring_entry_size = 8 * sizeof(uint32_t),
+ .event_interrupt_class = _interrupt_class_v9,
+ .num_of_watch_points = 4,
+ .mqd_size_aligned = MQD_SIZE_ALIGNED,
+ .supports_cwsr = true,
+ .needs_iommu_device = false,
+ .needs_pci_atomics = true,
+ .num_sdma_engines = 2,
+ .num_sdma_queues_per_engine = 8,
+};
+
struct kfd_deviceid {
unsigned short did;
const struct kfd_device_info *device_info;
@@ -323,6 +339,12 @@ static const struct kfd_deviceid supported_devices[] = {
{ 0x6868, _device_info },/* Vega10 */
{ 0x686C, _vf_device_info }, /* Vega10 vf*/
{ 0x687F, _device_info },/* Vega10 */
+ { 0x66a0, _device_info },/* Vega20 */
+ { 0x66a1, _device_info },/* Vega20 */
+ { 0x66a2, _device_info },/* Vega20 */
+ { 0x66a3, _device_info },/* Vega20 */
+ { 0x66a7, _device_info },/* Vega20 */
+ { 0x66af, _device_info } /* Vega20 */
};
static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index afa2167..d6af31c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1733,6 +1733,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev)
break;
case CHIP_VEGA10:
+ case CHIP_VEGA20:
case CHIP_RAVEN:
device_queue_manager_init_v9(>asic_ops);
break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 97d5423..3d66cec 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -400,6 +400,7 @@ int kfd_init_apertures(struct kfd_process *process)
kfd_init_apertures_vi(pdd, id);
break;
case CHIP_VEGA10:
+ case CHIP_VEGA20:
case CHIP_RAVEN:
kfd_init_apertures_v9(pdd, id);
break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 9f84b4d..6c31f73 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -322,6 +322,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
break;
case CHIP_VEGA10:
+ case CHIP_VEGA20:
case CHIP_RAVEN:
kernel_queue_init_v9(>ops_asic_specific);
break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index 3bc25ab..e33019a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -39,6 +39,7 @@ struct mqd_manager *mqd_manager_init(enum KFD_MQD_TYPE type,
[PATCH 1/6] drm/amdgpu: Doorbell assignment for 8 sdma user queue per engine
From: Shaoyun Liu
Change doorbell assignments to allow routing doorbells for 8 user
mode SDMA queues per engine.
Signed-off-by: Shaoyun Liu
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 14 -
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 38 +++--
drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 6 ++--
3 files changed, 33 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e992e0f..afa9e77 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -409,16 +409,16 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
/*
-* Other graphics doorbells can be allocated here: from 0x8c to 0xef
+* Other graphics doorbells can be allocated here: from 0x8c to 0xdf
* Graphics voltage island aperture 1
-* default non-graphics QWORD index is 0xF0 - 0xFF inclusive
+* default non-graphics QWORD index is 0xe0 - 0xFF inclusive
*/
- /* sDMA engines */
- AMDGPU_DOORBELL64_sDMA_ENGINE0= 0xF0,
- AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
- AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xF2,
- AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
+ /* sDMA engines reserved from 0xe0 -oxef */
+ AMDGPU_DOORBELL64_sDMA_ENGINE0= 0xE0,
+ AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xE1,
+ AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xE8,
+ AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9,
/* Interrupt handler */
AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy
interrupt ring buffer */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index d7f08e3..bf0b012 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -126,7 +126,7 @@ static void amdgpu_doorbell_get_kfd_info(struct
amdgpu_device *adev,
void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
{
- int i;
+ int i, n;
int last_valid_bit;
if (adev->kfd) {
struct kgd2kfd_shared_resources gpu_resources = {
@@ -165,7 +165,15 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
_resources.doorbell_physical_address,
_resources.doorbell_aperture_size,
_resources.doorbell_start_offset);
- if (adev->asic_type >= CHIP_VEGA10) {
+
+ if (adev->asic_type < CHIP_VEGA10) {
+ kgd2kfd->device_init(adev->kfd, _resources);
+ return;
+ }
+
+ n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;
+
+ for (i = 0; i < n; i += 2) {
/* On SOC15 the BIF is involved in routing
* doorbells using the low 12 bits of the
* address. Communicate the assignments to
@@ -173,20 +181,20 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
* process in case of 64-bit doorbells so we
* can use each doorbell assignment twice.
*/
- gpu_resources.sdma_doorbell[0][0] =
- AMDGPU_DOORBELL64_sDMA_ENGINE0;
- gpu_resources.sdma_doorbell[0][1] =
- AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200;
- gpu_resources.sdma_doorbell[1][0] =
- AMDGPU_DOORBELL64_sDMA_ENGINE1;
- gpu_resources.sdma_doorbell[1][1] =
- AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200;
- /* Doorbells 0x0f0-0ff and 0x2f0-2ff are reserved for
-* SDMA, IH and VCN. So don't use them for the CP.
-*/
- gpu_resources.reserved_doorbell_mask = 0x1f0;
- gpu_resources.reserved_doorbell_val = 0x0f0;
+ gpu_resources.sdma_doorbell[0][i] =
+ AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
+ gpu_resources.sdma_doorbell[0][i+1] =
+ AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >>
1);
+ gpu_resources.sdma_doorbell[1][i] =
+ AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
+ gpu_resources.sdma_doorbell[1][i+1] =
+ AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >>
1);
}
+ /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
+* SDMA, IH and VCN. So don't use
[PATCH 4/9] drm/amdkfd: reflect atomic support in IO link properties
From: Eric Huang
Add the flags of properties according to Asic type and pcie
capabilities.
Signed-off-by: Eric Huang
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 12 +-
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 37 +--
3 files changed, 39 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 29ac74f4..aa7cb88 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -366,6 +366,10 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
return NULL;
}
+ kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
+ if (!kfd)
+ return NULL;
+
/* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
* 32 and 64-bit requests are possible and must be
* supported.
@@ -377,12 +381,10 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
dev_info(kfd_device,
"skipped device %x:%x, PCI rejects atomics\n",
pdev->vendor, pdev->device);
+ kfree(kfd);
return NULL;
- }
-
- kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
- if (!kfd)
- return NULL;
+ } else if (!ret)
+ kfd->pci_atomic_requested = true;
kfd->kgd = kgd;
kfd->device_info = device_info;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 87e788c..73a46c7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -254,6 +254,8 @@ struct kfd_dev {
bool cwsr_enabled;
const void *cwsr_isa;
unsigned int cwsr_isa_size;
+
+ bool pci_atomic_requested;
};
/* KGD2KFD callbacks */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 80f5db4..7db629c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1125,17 +1125,40 @@ static void kfd_fill_mem_clk_max_info(struct
kfd_topology_device *dev)
static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
{
- struct kfd_iolink_properties *link;
+ struct kfd_iolink_properties *link, *cpu_link;
+ struct kfd_topology_device *cpu_dev;
+ uint32_t cap;
+ uint32_t cpu_flag = CRAT_IOLINK_FLAGS_ENABLED;
+ uint32_t flag = CRAT_IOLINK_FLAGS_ENABLED;
if (!dev || !dev->gpu)
return;
- /* GPU only creates direck links so apply flags setting to all */
- if (dev->gpu->device_info->asic_family == CHIP_HAWAII)
- list_for_each_entry(link, >io_link_props, list)
- link->flags = CRAT_IOLINK_FLAGS_ENABLED |
- CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
- CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
+ pcie_capability_read_dword(dev->gpu->pdev,
+ PCI_EXP_DEVCAP2, );
+
+ if (!(cap & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
+PCI_EXP_DEVCAP2_ATOMIC_COMP64)))
+ cpu_flag |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
+ CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
+
+ if (!dev->gpu->pci_atomic_requested ||
+ dev->gpu->device_info->asic_family == CHIP_HAWAII)
+ flag |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
+ CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
+
+ /* GPU only creates direct links so apply flags setting to all */
+ list_for_each_entry(link, >io_link_props, list) {
+ link->flags = flag;
+ cpu_dev = kfd_topology_device_by_proximity_domain(
+ link->node_to);
+ if (cpu_dev) {
+ list_for_each_entry(cpu_link,
+ _dev->io_link_props, list)
+ if (cpu_link->node_to == link->node_from)
+ cpu_link->flags = cpu_flag;
+ }
+ }
}
int kfd_topology_add_device(struct kfd_dev *gpu)
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 9/9] drm/amdgpu: remove unnecessary forward declaration
struct vi_sdma_mqd is defined in vi_structs.h.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index f58a8a3..dd94b70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -45,8 +45,6 @@ enum hqd_dequeue_request_type {
RESET_WAVES
};
-struct vi_sdma_mqd;
-
/*
* Register access functions
*/
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 8/9] drm/amdkfd: Add wavefront context save state retrieval ioctl
From: Jay Cornwall
Wavefront context save data is of interest to userspace clients for
debugging static wavefront state. The MQD contains two parameters
required to parse the control stack and the control stack itself
is kept in the MQD from gfx9 onwards.
Add an ioctl to fetch the context save area and control stack offsets
and to copy the control stack to a userspace address if it is kept in
the MQD.
Signed-off-by: Jay Cornwall
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 21
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 37 ++
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 8 +
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 8 +
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c| 23 ++
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c| 23 ++
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +++
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 22 +
include/uapi/linux/kfd_ioctl.h | 13 +++-
9 files changed, 159 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 297b36c..7f0b115 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -447,6 +447,24 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, struct
kfd_process *p,
return retval;
}
+static int kfd_ioctl_get_queue_wave_state(struct file *filep,
+ struct kfd_process *p, void *data)
+{
+ struct kfd_ioctl_get_queue_wave_state_args *args = data;
+ int r;
+
+ mutex_lock(>mutex);
+
+ r = pqm_get_wave_state(>pqm, args->queue_id,
+ (void __user *)args->ctl_stack_address,
+ >ctl_stack_used_size,
+ >save_area_used_size);
+
+ mutex_unlock(>mutex);
+
+ return r;
+}
+
static int kfd_ioctl_set_memory_policy(struct file *filep,
struct kfd_process *p, void *data)
{
@@ -1615,6 +1633,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK,
kfd_ioctl_set_cu_mask, 0),
+ AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE,
+ kfd_ioctl_get_queue_wave_state, 0)
+
};
#define AMDKFD_CORE_IOCTL_COUNTARRAY_SIZE(amdkfd_ioctls)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index ec0d62a..409 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1528,6 +1528,41 @@ static int process_termination_nocpsch(struct
device_queue_manager *dqm,
return retval;
}
+static int get_wave_state(struct device_queue_manager *dqm,
+ struct queue *q,
+ void __user *ctl_stack,
+ u32 *ctl_stack_used_size,
+ u32 *save_area_used_size)
+{
+ struct mqd_manager *mqd;
+ int r;
+
+ dqm_lock(dqm);
+
+ if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
+ q->properties.is_active || !q->device->cwsr_enabled) {
+ r = -EINVAL;
+ goto dqm_unlock;
+ }
+
+ mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
+ if (!mqd) {
+ r = -ENOMEM;
+ goto dqm_unlock;
+ }
+
+ if (!mqd->get_wave_state) {
+ r = -EINVAL;
+ goto dqm_unlock;
+ }
+
+ r = mqd->get_wave_state(mqd, q->mqd, ctl_stack, ctl_stack_used_size,
+ save_area_used_size);
+
+dqm_unlock:
+ dqm_unlock(dqm);
+ return r;
+}
static int process_termination_cpsch(struct device_queue_manager *dqm,
struct qcm_process_device *qpd)
@@ -1649,6 +1684,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev)
dqm->ops.process_termination = process_termination_cpsch;
dqm->ops.evict_process_queues = evict_process_queues_cpsch;
dqm->ops.restore_process_queues = restore_process_queues_cpsch;
+ dqm->ops.get_wave_state = get_wave_state;
break;
case KFD_SCHED_POLICY_NO_HWS:
/* initialize dqm for no cp scheduling */
@@ -1668,6 +1704,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev)
dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
dqm->ops.restore_process_queues =
restore_process_queues_nocpsch;
+ dqm->ops.get_wave_state = get_wave_state;
break;
default:
[PATCH 5/9] drm/amdkfd: KFD doesn't support TONGA SRIOV
From: Emily Deng
KFD module doesn't support TONGA SRIOV, if init KFD module in TONGA SRIOV
environment, it will let compute ring IB test fail.
Signed-off-by: Emily Deng
Reviewed-by: Shaoyun.liu
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index aa7cb88..26eff41 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -118,21 +118,6 @@ static const struct kfd_device_info tonga_device_info = {
.num_sdma_engines = 2,
};
-static const struct kfd_device_info tonga_vf_device_info = {
- .asic_family = CHIP_TONGA,
- .max_pasid_bits = 16,
- .max_no_of_hqd = 24,
- .doorbell_size = 4,
- .ih_ring_entry_size = 4 * sizeof(uint32_t),
- .event_interrupt_class = _interrupt_class_cik,
- .num_of_watch_points = 4,
- .mqd_size_aligned = MQD_SIZE_ALIGNED,
- .supports_cwsr = false,
- .needs_iommu_device = false,
- .needs_pci_atomics = false,
- .num_sdma_engines = 2,
-};
-
static const struct kfd_device_info fiji_device_info = {
.asic_family = CHIP_FIJI,
.max_pasid_bits = 16,
@@ -293,7 +278,6 @@ static const struct kfd_deviceid supported_devices[] = {
{ 0x6928, _device_info }, /* Tonga */
{ 0x6929, _device_info }, /* Tonga */
{ 0x692B, _device_info }, /* Tonga */
- { 0x692F, _vf_device_info }, /* Tonga vf */
{ 0x6938, _device_info }, /* Tonga */
{ 0x6939, _device_info }, /* Tonga */
{ 0x7300, _device_info }, /* Fiji */
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 6/9] drm/amdgpu: Enable BAD_OPCODE intr for gfx8
From: Harish Kasiviswanathan This enables KFD_EVENT_TYPE_HW_EXCEPTION notifications to user mode in response to bad opcodes in a CP queue. Signed-off-by: Harish Kasiviswanathan Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index ea7c18c..f58a8a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -282,7 +282,8 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) lock_srbm(kgd, mec, pipe, 0, 0); - WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK); + WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | + CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); unlock_srbm(kgd); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/9] drm/amdgpu: Fix SDMA HQD destroy error on gfx_v7
From: Amber Lin
A wrong register bit was examinated for checking SDMA status so it reports
false failures. This typo only appears on gfx_v7. gfx_v8 checks the correct
bit.
Signed-off-by: Amber Lin
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 6f0b526..b2e45c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -686,7 +686,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void
*mqd,
while (true) {
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
- if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
+ if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
break;
if (time_after(jiffies, end_jiffies))
return -ETIME;
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 7/9] drm/amdkfd: Report SDMA firmware version in the topology
Also save the version in struct kfd_dev so we only need to query
it once.
Signed-off-by: Philip Yang
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 6 +++---
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 26eff41..2e844d3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -405,6 +405,10 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
{
unsigned int size;
+ kfd->mec_fw_version = kfd->kfd2kgd->get_fw_version(kfd->kgd,
+ KGD_ENGINE_MEC1);
+ kfd->sdma_fw_version = kfd->kfd2kgd->get_fw_version(kfd->kgd,
+ KGD_ENGINE_SDMA1);
kfd->shared_resources = *gpu_resources;
kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 73a46c7..c4f7a52 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -247,6 +247,10 @@ struct kfd_dev {
/* Debug manager */
struct kfd_dbgmgr *dbgmgr;
+ /* Firmware versions */
+ uint16_t mec_fw_version;
+ uint16_t sdma_fw_version;
+
/* Maximum process number mapped to HW scheduler */
unsigned int max_proc_per_quantum;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 7db629c..02b12e4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -480,11 +480,11 @@ static ssize_t node_show(struct kobject *kobj, struct
attribute *attr,
(unsigned long long int) 0);
sysfs_show_32bit_prop(buffer, "fw_version",
- dev->gpu->kfd2kgd->get_fw_version(
- dev->gpu->kgd,
- KGD_ENGINE_MEC1));
+ dev->gpu->mec_fw_version);
sysfs_show_32bit_prop(buffer, "capability",
dev->node_props.capability);
+ sysfs_show_32bit_prop(buffer, "sdma_fw_version",
+ dev->gpu->sdma_fw_version);
}
return sysfs_show_32bit_prop(buffer, "max_engine_clk_ccompute",
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/9] drm/amdkfd: Change the control stack MTYPE from UC to NC on GFX9
From: Yong Zhao
CWSR fails on Raven if the control stack is MTYPE_UC, which is used
for regular GART mappings. As a workaround we map it using MTYPE_NC.
The MEC firmware expects the control stack at one page offset from the
start of the MQD so it is part of the MQD allocation on GFXv9. AMDGPU
added a memory allocation flag just for this purpose.
Signed-off-by: Yong Zhao
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 2 +-
5 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 8bee9a0..d7f08e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -253,7 +253,7 @@ void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
void **mem_obj, uint64_t *gpu_addr,
- void **cpu_ptr)
+ void **cpu_ptr, bool mqd_gfx9)
{
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
struct amdgpu_bo *bo = NULL;
@@ -268,6 +268,10 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
+
+ if (mqd_gfx9)
+ bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;
+
r = amdgpu_bo_create(adev, , );
if (r) {
dev_err(adev->dev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 2a1da3f..db93c92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -136,7 +136,7 @@ void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd);
/* Shared API */
int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
void **mem_obj, uint64_t *gpu_addr,
- void **cpu_ptr);
+ void **cpu_ptr, bool mqd_gfx9);
void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
void get_local_mem_info(struct kgd_dev *kgd,
struct kfd_local_mem_info *mem_info);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 1b04871..29ac74f4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -457,7 +457,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
if (kfd->kfd2kgd->init_gtt_mem_allocation(
kfd->kgd, size, >gtt_mem,
- >gtt_start_gpu_addr, >gtt_start_cpu_ptr)){
+ >gtt_start_gpu_addr, >gtt_start_cpu_ptr,
+ false)) {
dev_err(kfd_device, "Could not allocate %d bytes\n", size);
goto out;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index f5fc367..0cedb37 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -88,7 +88,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd,
ALIGN(sizeof(struct v9_mqd), PAGE_SIZE),
&((*mqd_mem_obj)->gtt_mem),
&((*mqd_mem_obj)->gpu_addr),
- (void *)&((*mqd_mem_obj)->cpu_ptr));
+ (void *)&((*mqd_mem_obj)->cpu_ptr), true);
} else
retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct v9_mqd),
mqd_mem_obj);
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 31c52c1..4ef0a50 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -320,7 +320,7 @@ struct tile_config {
struct kfd2kgd_calls {
int (*init_gtt_mem_allocation)(struct kgd_dev *kgd, size_t size,
void **mem_obj, uint64_t *gpu_addr,
- void **cpu_ptr);
+ void **cpu_ptr, bool mqd_gfx9);
void (*free_gtt_mem)(struct kgd_dev *kgd, void *mem_obj);
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/9] drm/amdkfd: Fix ATS capablity was not reported correctly on some APUs
From: Yong Zhao
Because CRAT_CU_FLAGS_IOMMU_PRESENT was not set in some BIOS crat, we
need to workaround this.
For future compatibility, we also overwrite the bit in capability according
to the value of needs_iommu_device.
Signed-off-by: Yong Zhao
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_iommu.c| 13 -
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 21 -
3 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
index 7a61f38..0149475 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
@@ -62,9 +62,20 @@ int kfd_iommu_device_init(struct kfd_dev *kfd)
struct amd_iommu_device_info iommu_info;
unsigned int pasid_limit;
int err;
+ struct kfd_topology_device *top_dev;
- if (!kfd->device_info->needs_iommu_device)
+ top_dev = kfd_topology_device_by_id(kfd->id);
+
+ /*
+* Overwrite ATS capability according to needs_iommu_device to fix
+* potential missing corresponding bit in CRAT of BIOS.
+*/
+ if (!kfd->device_info->needs_iommu_device) {
+ top_dev->node_props.capability &= ~HSA_CAP_ATS_PRESENT;
return 0;
+ }
+
+ top_dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
iommu_info.flags = 0;
err = amd_iommu_device_info(kfd->pdev, _info);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 355f79d..87e788c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -778,6 +778,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu);
int kfd_topology_remove_device(struct kfd_dev *gpu);
struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
uint32_t proximity_domain);
+struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id);
struct kfd_dev *kfd_device_by_id(uint32_t gpu_id);
struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev);
int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index bc95d4df..80f5db4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -63,22 +63,33 @@ struct kfd_topology_device
*kfd_topology_device_by_proximity_domain(
return device;
}
-struct kfd_dev *kfd_device_by_id(uint32_t gpu_id)
+struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id)
{
- struct kfd_topology_device *top_dev;
- struct kfd_dev *device = NULL;
+ struct kfd_topology_device *top_dev = NULL;
+ struct kfd_topology_device *ret = NULL;
down_read(_lock);
list_for_each_entry(top_dev, _device_list, list)
if (top_dev->gpu_id == gpu_id) {
- device = top_dev->gpu;
+ ret = top_dev;
break;
}
up_read(_lock);
- return device;
+ return ret;
+}
+
+struct kfd_dev *kfd_device_by_id(uint32_t gpu_id)
+{
+ struct kfd_topology_device *top_dev;
+
+ top_dev = kfd_topology_device_by_id(gpu_id);
+ if (!top_dev)
+ return NULL;
+
+ return top_dev->gpu;
}
struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev)
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Add braces to initialize task_info subojects
On Wed, Sep 12, 2018 at 1:24 PM Richard Smith wrote:
>
> On Wed, Sep 12, 2018 at 10:38 AM Nick Desaulniers
> wrote:
>>
>> On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
>> wrote:
>> >
>> > Clang warns if there are missing braces around a subobject
>> > initializer.
>> >
>> > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
>> > around initialization of subobject [-Wmissing-braces]
>> > struct amdgpu_task_info task_info = { 0 };
>> > ^
>> > {}
>> > 1 warning generated.
>> >
>> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:262:41: warning: suggest braces
>> > around initialization of subobject [-Wmissing-braces]
>> > struct amdgpu_task_info task_info = { 0 };
>> > ^
>> > {}
>> > 1 warning generated.
>> >
>> > Reported-by: Nick Desaulniers
>> > Signed-off-by: Nathan Chancellor
>> > ---
>> > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
>> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
>> > 2 files changed, 2 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> > b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> > index 9333109b210d..968cc1b8cdff 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> > @@ -1444,7 +1444,7 @@ static int gmc_v8_0_process_interrupt(struct
>> > amdgpu_device *adev,
>> > gmc_v8_0_set_fault_enable_default(adev, false);
>> >
>> > if (printk_ratelimit()) {
>> > - struct amdgpu_task_info task_info = { 0 };
>> > + struct amdgpu_task_info task_info = { { 0 } };
>>
>> Hi Nathan,
>> Thanks for this patch. I discussed this syntax with our language
>> lawyers. Turns out, this is not quite correct, as you're now saying
>> "initialize the first subobject to zero, but not the rest of the
>> object." -Wmissing-field-initializers would highlight this, but it's
>> not part of -Wall. It would be more correct to zero initialize the
>> full struct, including all of its subobjects with `= {};`.
>
>
> Sorry, I think I've caused some confusion here.
>
> Elements with an omitted initializer get implicitly zero-initialized. In C++,
> it's idiomatic to write `= {}` to perform aggregate zero-initialization, but
> in C, that's invalid because at least one initializer is syntactically
> required within the braces. As a result, `= {0}` is an idiomatic way to
> perform zero-initialization of an aggregate in C.
That doesn't seem to be the case:
https://godbolt.org/z/TZzfo6 shouldn't Clang warn in the case of bar()?
> Clang intends to suppress the -Wmissing-braces in that case; if the warning
> is still being produced in a recent version of Clang, that's a bug. However,
> the warning suppression was added between Clang 5 and Clang 6, so it's very
> plausible that the compiler being used here is simply older than the warning
> fix.
>
> (Long story short: the change here seems fine, but should be unnecessary as
> of Clang 6.)
The warning was identified from clang-8 ToT synced yesterday.
--
Thanks,
~Nick Desaulniers
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/8] drm/amdgpu: add some VM PD/PT iterators v2
The series is Reviewed-by: Felix Kuehling
On 2018-09-12 04:54 AM, Christian König wrote:
> Both a leaf as well as dfs iterator to walk over all the PDs/PTs.
>
> v2: update comments and fix for_each_amdgpu_vm_pt_dfs_safe
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 224
> +
> 1 file changed, 224 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 136b00412dc8..787a200cf796 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -355,6 +355,230 @@ static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct
> amdgpu_vm_pt *pt)
> return list_first_entry(>va, struct amdgpu_vm_pt, base.bo_list);
> }
>
> +/**
> + * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
> + */
> +struct amdgpu_vm_pt_cursor {
> + uint64_t pfn;
> + struct amdgpu_vm_pt *parent;
> + struct amdgpu_vm_pt *entry;
> + unsigned level;
> +};
> +
> +/**
> + * amdgpu_vm_pt_start - start PD/PT walk
> + *
> + * @adev: amdgpu_device pointer
> + * @vm: amdgpu_vm structure
> + * @start: start address of the walk
> + * @cursor: state to initialize
> + *
> + * Initialize a amdgpu_vm_pt_cursor to start a walk.
> + */
> +static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
> +struct amdgpu_vm *vm, uint64_t start,
> +struct amdgpu_vm_pt_cursor *cursor)
> +{
> + cursor->pfn = start;
> + cursor->parent = NULL;
> + cursor->entry = >root;
> + cursor->level = adev->vm_manager.root_level;
> +}
> +
> +/**
> + * amdgpu_vm_pt_descendant - go to child node
> + *
> + * @adev: amdgpu_device pointer
> + * @cursor: current state
> + *
> + * Walk to the child node of the current node.
> + * Returns:
> + * True if the walk was possible, false otherwise.
> + */
> +static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
> + struct amdgpu_vm_pt_cursor *cursor)
> +{
> + unsigned num_entries, shift, idx;
> +
> + if (!cursor->entry->entries)
> + return false;
> +
> + BUG_ON(!cursor->entry->base.bo);
> + num_entries = amdgpu_vm_num_entries(adev, cursor->level);
> + shift = amdgpu_vm_level_shift(adev, cursor->level);
> +
> + ++cursor->level;
> + idx = (cursor->pfn >> shift) % num_entries;
> + cursor->parent = cursor->entry;
> + cursor->entry = >entry->entries[idx];
> + return true;
> +}
> +
> +/**
> + * amdgpu_vm_pt_sibling - go to sibling node
> + *
> + * @adev: amdgpu_device pointer
> + * @cursor: current state
> + *
> + * Walk to the sibling node of the current node.
> + * Returns:
> + * True if the walk was possible, false otherwise.
> + */
> +static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
> + struct amdgpu_vm_pt_cursor *cursor)
> +{
> + unsigned shift, num_entries;
> +
> + /* Root doesn't have a sibling */
> + if (!cursor->parent)
> + return false;
> +
> + /* Go to our parents and see if we got a sibling */
> + shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
> + num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
> +
> + if (cursor->entry == >parent->entries[num_entries - 1])
> + return false;
> +
> + cursor->pfn += 1ULL << shift;
> + cursor->pfn &= ~((1ULL << shift) - 1);
> + ++cursor->entry;
> + return true;
> +}
> +
> +/**
> + * amdgpu_vm_pt_ancestor - go to parent node
> + *
> + * @cursor: current state
> + *
> + * Walk to the parent node of the current node.
> + * Returns:
> + * True if the walk was possible, false otherwise.
> + */
> +static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
> +{
> + if (!cursor->parent)
> + return false;
> +
> + --cursor->level;
> + cursor->entry = cursor->parent;
> + cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
> + return true;
> +}
> +
> +/**
> + * amdgpu_vm_pt_next - get next PD/PT in hieratchy
> + *
> + * @adev: amdgpu_device pointer
> + * @cursor: current state
> + *
> + * Walk the PD/PT tree to the next node.
> + */
> +static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
> + struct amdgpu_vm_pt_cursor *cursor)
> +{
> + /* First try a newborn child */
> + if (amdgpu_vm_pt_descendant(adev, cursor))
> + return;
> +
> + /* If that didn't worked try to find a sibling */
> + while (!amdgpu_vm_pt_sibling(adev, cursor)) {
> + /* No sibling, go to our parents and grandparents */
> + if (!amdgpu_vm_pt_ancestor(cursor)) {
> + cursor->pfn = ~0ll;
> + return;
> + }
> + }
> +}
> +
> +/**
> + * amdgpu_vm_pt_first_leaf - get first leaf PD/PT
> + *
> + * @adev: amdgpu_device pointer
> + * @vm: amdgpu_vm structure
> + * @start: start addr of the
Re: [PATCH 2/2] drm/amdgpu: use a single linked list for amdgpu_vm_bo_base
Is the small reduction in memory footprint (8 bytes per page table on a
64-bit kernel) really worth the trouble of open-coding a single-linked
list implementation? I guess this change makes a bigger difference for
2-level page tables than it does for 4-level, because the amdgpu_vm_pt
array is allocated at the page directory level and includes page tables
that don't even exist yet and may never exist. The amount of memory you
save is the same as the size of the page directory.
I wonder if the overhead could be reduced more effectively by allocating
struct amdgpu_vm_pt with the page table, rather than with the page
directory. Then the amdgpu_vm_pt.entries array would be an array of
pointers instead. It could be an array[0] at the end of the structure
since the number of entries is know then the page directory is
allocated. The BO could also be embedded in the amdgpu_vm_pt structure
so it doesn't need to be a separate allocation from the amdgpu_vm_pt.
Acked-by: Felix Kuehling
Regards,
Felix
On 2018-09-12 04:55 AM, Christian König wrote:
> Instead of the double linked list. Gets the size of amdgpu_vm_pt down to
> 64 bytes again.
>
> We could even reduce it down to 32 bytes, but that would require some
> rather extreme hacks.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 38
> --
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
> 4 files changed, 29 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index de990bdcdd6c..e6909252aefa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -448,7 +448,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
> return -ENOMEM;
> drm_gem_private_object_init(adev->ddev, >gem_base, size);
> INIT_LIST_HEAD(>shadow_list);
> - INIT_LIST_HEAD(>va);
> + bo->vm_bo = NULL;
> bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
> bp->domain;
> bo->allowed_domains = bo->preferred_domains;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> index 907fdf46d895..64337ff2ad63 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> @@ -89,8 +89,8 @@ struct amdgpu_bo {
> void*metadata;
> u32 metadata_size;
> unsignedprime_shared_count;
> - /* list of all virtual address to which this bo is associated to */
> - struct list_headva;
> + /* per VM structure for page tables and with virtual addresses */
> + struct amdgpu_vm_bo_base*vm_bo;
> /* Constant after initialization */
> struct drm_gem_object gem_base;
> struct amdgpu_bo*parent;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index cb6a5114128e..fb6b16273c54 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -309,12 +309,13 @@ static void amdgpu_vm_bo_base_init(struct
> amdgpu_vm_bo_base *base,
> {
> base->vm = vm;
> base->bo = bo;
> - INIT_LIST_HEAD(>bo_list);
> + base->next = NULL;
> INIT_LIST_HEAD(>vm_status);
>
> if (!bo)
> return;
> - list_add_tail(>bo_list, >va);
> + base->next = bo->vm_bo;
> + bo->vm_bo = base;
>
> if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
> return;
> @@ -352,7 +353,7 @@ static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct
> amdgpu_vm_pt *pt)
> if (!parent)
> return NULL;
>
> - return list_first_entry(>va, struct amdgpu_vm_pt, base.bo_list);
> + return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
> }
>
> /**
> @@ -954,7 +955,7 @@ static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
> for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) {
>
> if (entry->base.bo) {
> - list_del(>base.bo_list);
> + entry->base.bo->vm_bo = NULL;
> list_del(>base.vm_status);
> amdgpu_bo_unref(>base.bo->shadow);
> amdgpu_bo_unref(>base.bo);
> @@ -1162,12 +1163,13 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct
> amdgpu_job *job, bool need_
> struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
> struct amdgpu_bo *bo)
> {
> - struct amdgpu_bo_va *bo_va;
> + struct amdgpu_vm_bo_base *base;
>
> - list_for_each_entry(bo_va, >va, base.bo_list) {
> - if (bo_va->base.vm ==
Re: BUG: *ERROR* No EDID read
Hey, I had some time to bisect again tonight and it seems 018d82e5f02ef3583411bcaa4e00c69786f46f19 got back in again through: # first bad commit: [d98c71dadc2d0debdb80beb5a478baf1e6f98758] Merge drm-upstream/drm-next into drm-misc-next / Daniel On Wed, 29 Aug 2018 at 16:02, Daniel Andersson wrote: > > Hey again, > > This is an issue for me yet again on 4.19-rc1: > > [5.743354] [drm:dc_link_detect [amdgpu]] *ERROR* No EDID read. > > / Daniel > > dmesg with drm.debug=0x4: > > [0.00] Linux version 4.19.0-rc1-ARCH (engy@sleipnir) (gcc > version 8.2.0 (GCC)) #1 SMP PREEMPT Tue Aug 28 10:36:50 CEST 2018 > [0.00] Command line: BOOT_IMAGE=/vmlinuz-linuxtest > root=UUID=27247597-a354-42f3-8040-caff9592a297 rw quiet drm.debug=0x4 > [0.00] KERNEL supported cpus: > [0.00] AMD AuthenticAMD > [0.00] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating > point registers' > [0.00] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' > [0.00] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers' > [0.00] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256 > [0.00] x86/fpu: Enabled xstate features 0x7, context size is > 832 bytes, using 'compacted' format. > [0.00] BIOS-provided physical RAM map: > [0.00] BIOS-e820: [mem 0x-0x0009] usable > [0.00] BIOS-e820: [mem 0x000a-0x000f] reserved > [0.00] BIOS-e820: [mem 0x0010-0x09de] usable > [0.00] BIOS-e820: [mem 0x09df-0x09ff] reserved > [0.00] BIOS-e820: [mem 0x0a00-0xb75f] usable > [0.00] BIOS-e820: [mem 0xb760-0xb8b4afff] reserved > [0.00] BIOS-e820: [mem 0xb8b4b000-0xb8f2cfff] usable > [0.00] BIOS-e820: [mem 0xb8f2d000-0xb902dfff] ACPI NVS > [0.00] BIOS-e820: [mem 0xb902e000-0xb9cf6fff] reserved > [0.00] BIOS-e820: [mem 0xb9cf7000-0xb9e16fff] type 20 > [0.00] BIOS-e820: [mem 0xb9e17000-0xbbff] usable > [0.00] BIOS-e820: [mem 0xbc00-0xbfff] reserved > [0.00] BIOS-e820: [mem 0xed00-0xed07] reserved > [0.00] BIOS-e820: [mem 0xed0f-0xed0f0fff] reserved > [0.00] BIOS-e820: [mem 0xef60-0xef67] reserved > [0.00] BIOS-e820: [mem 0xef6f-0xef6f0fff] reserved > [0.00] BIOS-e820: [mem 0xfea0-0xfec00fff] reserved > [0.00] BIOS-e820: [mem 0xfec1-0xfec10fff] reserved > [0.00] BIOS-e820: [mem 0xfec3-0xfec30fff] reserved > [0.00] BIOS-e820: [mem 0xfed0-0xfed00fff] reserved > [0.00] BIOS-e820: [mem 0xfed4-0xfed44fff] reserved > [0.00] BIOS-e820: [mem 0xfed8-0xfed8] reserved > [0.00] BIOS-e820: [mem 0xfedc-0xfedc0fff] reserved > [0.00] BIOS-e820: [mem 0xfedc2000-0xfedc] reserved > [0.00] BIOS-e820: [mem 0xfedd4000-0xfedd5fff] reserved > [0.00] BIOS-e820: [mem 0xfee0-0xfeef] reserved > [0.00] BIOS-e820: [mem 0xff00-0x] reserved > [0.00] BIOS-e820: [mem 0x0001-0x00083f2f] usable > [0.00] BIOS-e820: [mem 0x00083f30-0x00083fff] reserved > [0.00] NX (Execute Disable) protection: active > [0.00] efi: EFI v2.60 by American Megatrends > [0.00] efi: ACPI 2.0=0xb8f2d000 ACPI=0xb8f2d000 > SMBIOS=0xb9c66000 SMBIOS 3.0=0xb9c65000 ESRT=0xb5ebef98 > [0.00] SMBIOS 3.0.0 present. > [0.00] DMI: To Be Filled By O.E.M. To Be Filled By O.E.M./X399 > Taichi, BIOS P2.00 11/21/2017 > [0.00] tsc: Fast TSC calibration failed > [0.00] e820: update [mem 0x-0x0fff] usable ==> reserved > [0.00] e820: remove [mem 0x000a-0x000f] usable > [0.00] last_pfn = 0x83f300 max_arch_pfn = 0x4 > [0.00] MTRR default type: uncachable > [0.00] MTRR fixed ranges enabled: > [0.00] 0-9 write-back > [0.00] A-B write-through > [0.00] C-D uncachable > [0.00] E-F write-protect > [0.00] MTRR variable ranges enabled: > [0.00] 0 base mask 8000 write-back > [0.00] 1 base 8000 mask C000 write-back > [0.00] 2 base BC00 mask FC00 uncachable > [0.00] 3 disabled > [0.00] 4 disabled > [0.00] 5 disabled > [0.00] 6 disabled > [0.00] 7 disabled > [0.00] TOM2: 00084000 aka 33792M > [
[PATCH] drm/amdgpu: use HMM mirror callback to replace mmu notifier (v2)
Replace our MMU notifier with hmm_mirror_ops.sync_cpu_device_pagetables
callback. Enable CONFIG_HMM and CONFIG_HMM_MIRROR as a dependency in
DRM_AMDGPU_USERPTR Kconfig.
It supports both KFD userptr and gfx userptr paths.
This depends on several HMM patchset from Jérôme Glisse queued for
upstream. See
http://172.27.226.38/root/kernel_amd/commits/hmm-dev-v01 (for AMD intranet)
Change-Id: Ie62c3c5e3c5b8521ab3b438d1eff2aa2a003835e
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/Kconfig | 6 +--
drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 78 +
drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 41 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 50 -
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 7 +++
6 files changed, 178 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig
b/drivers/gpu/drm/amd/amdgpu/Kconfig
index 9221e54..960a633 100644
--- a/drivers/gpu/drm/amd/amdgpu/Kconfig
+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
@@ -26,10 +26,10 @@ config DRM_AMDGPU_CIK
config DRM_AMDGPU_USERPTR
bool "Always enable userptr write support"
depends on DRM_AMDGPU
- select MMU_NOTIFIER
+ select HMM_MIRROR
help
- This option selects CONFIG_MMU_NOTIFIER if it isn't already
- selected to enabled full userptr support.
+ This option selects CONFIG_HMM and CONFIG_HMM_MIRROR if it
+ isn't already selected to enabled full userptr support.
config DRM_AMDGPU_GART_DEBUGFS
bool "Allow GART access through debugfs"
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 138cb78..ee691e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -172,6 +172,7 @@ amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
+amdgpu-$(CONFIG_HMM) += amdgpu_hmm.o
include $(FULL_AMD_PATH)/powerplay/Makefile
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
new file mode 100644
index 000..6c506f6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "amdgpu.h"
+#include "amdgpu_mn.h"
+
+static void amdgpu_hmm_release(struct hmm_mirror *mirror)
+{
+ pr_debug("mirror=%p\n", mirror);
+ amdgpu_hmm_mn_release(mirror);
+}
+
+static int amdgpu_hmm_sync_cpu_device_pagetables(struct hmm_mirror *mirror,
+ const struct hmm_update *update)
+{
+ struct hmm *hmm;
+ struct mm_struct *mm;
+ unsigned long start;
+ unsigned long end;
+
+ start = update->start;
+ end = update->end;
+
+ pr_debug("mirror %p start %lx end %lx\n", mirror, start, end);
+
+ hmm = mirror->hmm;
+ mm = *(struct mm_struct **)hmm;
+
+ return amdgpu_mn_invalidate_range(mirror, mm, start, end,
+ update->blockable);
+}
+
+static struct hmm_mirror_ops amdgpu_hmm_mirror_ops = {
+ .sync_cpu_device_pagetables = amdgpu_hmm_sync_cpu_device_pagetables,
+ .release = amdgpu_hmm_release
+};
+
+int amdgpu_hmm_register(struct hmm_mirror *mirror, struct mm_struct *mm)
+{
+ pr_debug("mirror=%p\n", mirror);
+
+ mirror->ops = _hmm_mirror_ops;
+
+ return hmm_mirror_register(mirror, mm);
+}
+
+void amdgpu_hmm_unregister(struct hmm_mirror *mirror)
+{
+ pr_debug("mirror=%p\n", mirror);
+
+
Re: [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc
On Wed, Sep 12, 2018 at 4:44 PM Harry Wentland wrote:
>
>
>
> On 2018-09-12 04:10 PM, Alex Deucher wrote:
> > On Wed, Sep 12, 2018 at 3:29 PM Alex Deucher wrote:
> >>
> >> From: Bhawanpreet Lakha
> >>
> >> Add Raven2 definitions in the dc code
> >>
> >> Signed-off-by: Bhawanpreet Lakha
> >> Reviewed-by: Harry Wentland
> >> Reviewed-by: Huang Rui
> >> Acked-by: Alex Deucher >> Signed-off-by: Alex Deucher
> >> ---
> >> .../amd/display/dc/bios/command_table_helper2.c| 5 +++
> >> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +
> >> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +
> >
> > Some of the clock source changes look suspect. See comments below.
> >
> > Alex
> >
> >> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36
> >> +-
> >> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 +++
> >> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 +++
> >> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +++
> >> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 +
> >> drivers/gpu/drm/amd/display/include/dal_types.h| 3 ++
> >> 9 files changed, 78 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >> index bbbcef566c55..65b006ad372e 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >> @@ -61,6 +61,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> >> return true;
> >> #endif
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> + *h = dal_cmd_tbl_helper_dce112_get_table2();
> >> + return true;
> >> +#endif
> >> case DCE_VERSION_12_0:
> >> *h = dal_cmd_tbl_helper_dce112_get_table2();
> >> return true;
> >> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> index d981755d1e4d..721dd13d2ed2 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> @@ -88,6 +88,10 @@ enum dce_version resource_parse_asic_id(struct
> >> hw_asic_id asic_id)
> >> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> >> case FAMILY_RV:
> >> dc_version = DCN_VERSION_1_0;
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
> >> + dc_version = DCN_VERSION_1_01;
> >> +#endif
> >> break;
> >> #endif
> >> default:
> >> @@ -138,6 +142,9 @@ struct resource_pool *dc_create_resource_pool(
> >>
> >> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> >> case DCN_VERSION_1_0:
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> +#endif
> >> res_pool = dcn10_create_resource_pool(
> >> num_virtual_links, dc);
> >> break;
> >> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> >> b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> >> index 5a9f3601ffb6..ae3c44aff1c8 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> >> @@ -601,6 +601,9 @@ static uint32_t dce110_get_pix_clk_dividers(
> >> case DCN_VERSION_1_0:
> >> #endif
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> +#endif
> >> dce112_get_pix_clk_dividers_helper(clk_src,
> >> pll_settings, pix_clk_params);
> >> break;
> >> @@ -907,6 +910,10 @@ static bool dce110_program_pix_clk(
> >> case DCN_VERSION_1_0:
> >> #endif
> >>
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + case DCN_VERSION_1_01:
> >> +#endif
> >> +
> >> if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
> >> bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
> >>
> >> pll_settings->use_external_clk;
> >> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> >> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> >> index 1b519f8f044f..65a596ffa02a 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> >> @@ -152,7 +152,10 @@ enum dcn10_clk_src_array_id {
> >> DCN10_CLK_SRC_PLL1,
> >> DCN10_CLK_SRC_PLL2,
> >> DCN10_CLK_SRC_PLL3,
> >> - DCN10_CLK_SRC_TOTAL
> >> + DCN10_CLK_SRC_TOTAL,
> >> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> >> + DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
> >> +#endif
> >
> > This change looks suspect.
>
> +Hersen who did some
[PATCH] drm/amd/display: Fix pflip IRQ status after gpu reset.
Problem: After GPU reset pflip completion IRQ is disabled and hence any subsequent mode set or plane update leads to hang. Fix: Unless acrtc->otg_inst is initialized to -1 during display block initializtion then durng resume from GPU reset amdgpu_irq_gpu_reset_resume_helper will override CRTC 0 pflip IRQ value with whatever value was on every other unused CRTC because dm_irq_state will do irq_source = dal_irq_type + acrtc->otg_inst where acrtc->otg_inst will be 0 for every unused CRTC. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5103eba..75c4b80 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3351,6 +3351,7 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, acrtc->crtc_id = crtc_index; acrtc->base.enabled = false; + acrtc->otg_inst = -1; dm->adev->mode_info.crtcs[crtc_index] = acrtc; drm_crtc_enable_color_mgmt(>base, MAX_COLOR_LUT_ENTRIES, -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc
On 2018-09-12 04:10 PM, Alex Deucher wrote:
> On Wed, Sep 12, 2018 at 3:29 PM Alex Deucher wrote:
>>
>> From: Bhawanpreet Lakha
>>
>> Add Raven2 definitions in the dc code
>>
>> Signed-off-by: Bhawanpreet Lakha
>> Reviewed-by: Harry Wentland
>> Reviewed-by: Huang Rui
>> Acked-by: Alex Deucher > Signed-off-by: Alex Deucher
>> ---
>> .../amd/display/dc/bios/command_table_helper2.c| 5 +++
>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +
>> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +
>
> Some of the clock source changes look suspect. See comments below.
>
> Alex
>
>> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36
>> +-
>> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 +++
>> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 +++
>> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +++
>> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 +
>> drivers/gpu/drm/amd/display/include/dal_types.h| 3 ++
>> 9 files changed, 78 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> index bbbcef566c55..65b006ad372e 100644
>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> @@ -61,6 +61,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>> return true;
>> #endif
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> + *h = dal_cmd_tbl_helper_dce112_get_table2();
>> + return true;
>> +#endif
>> case DCE_VERSION_12_0:
>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>> return true;
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> index d981755d1e4d..721dd13d2ed2 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> @@ -88,6 +88,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id
>> asic_id)
>> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>> case FAMILY_RV:
>> dc_version = DCN_VERSION_1_0;
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
>> + dc_version = DCN_VERSION_1_01;
>> +#endif
>> break;
>> #endif
>> default:
>> @@ -138,6 +142,9 @@ struct resource_pool *dc_create_resource_pool(
>>
>> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>> case DCN_VERSION_1_0:
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> +#endif
>> res_pool = dcn10_create_resource_pool(
>> num_virtual_links, dc);
>> break;
>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> index 5a9f3601ffb6..ae3c44aff1c8 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>> @@ -601,6 +601,9 @@ static uint32_t dce110_get_pix_clk_dividers(
>> case DCN_VERSION_1_0:
>> #endif
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> +#endif
>> dce112_get_pix_clk_dividers_helper(clk_src,
>> pll_settings, pix_clk_params);
>> break;
>> @@ -907,6 +910,10 @@ static bool dce110_program_pix_clk(
>> case DCN_VERSION_1_0:
>> #endif
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + case DCN_VERSION_1_01:
>> +#endif
>> +
>> if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
>> bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
>>
>> pll_settings->use_external_clk;
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>> index 1b519f8f044f..65a596ffa02a 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>> @@ -152,7 +152,10 @@ enum dcn10_clk_src_array_id {
>> DCN10_CLK_SRC_PLL1,
>> DCN10_CLK_SRC_PLL2,
>> DCN10_CLK_SRC_PLL3,
>> - DCN10_CLK_SRC_TOTAL
>> + DCN10_CLK_SRC_TOTAL,
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> + DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
>> +#endif
>
> This change looks suspect.
+Hersen who did some of the original work.
AFAIK DCN 10.1 has one less PLL.
We can drop all the DCN1_01 ifdefs to help simplify this code a bit.
Or do you mean something else here?
Harry
>
> Alex
>
>> };
>>
>> /* begin *
>> @@ -1163,6 +1166,10 @@ static bool construct(
>> /*
Re: [PATCH] drm/amdgpu: Add braces to initialize task_info subojects
On Wed, Sep 12, 2018 at 10:38 AM Nick Desaulniers
wrote:
> On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
> wrote:
> >
> > Clang warns if there are missing braces around a subobject
> > initializer.
> >
> > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
> > around initialization of subobject [-Wmissing-braces]
> > struct amdgpu_task_info task_info = { 0 };
> > ^
> > {}
> > 1 warning generated.
> >
> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:262:41: warning: suggest braces
> > around initialization of subobject [-Wmissing-braces]
> > struct amdgpu_task_info task_info = { 0 };
> > ^
> > {}
> > 1 warning generated.
> >
> > Reported-by: Nick Desaulniers
> > Signed-off-by: Nathan Chancellor
> > ---
> > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
> > 2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > index 9333109b210d..968cc1b8cdff 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > @@ -1444,7 +1444,7 @@ static int gmc_v8_0_process_interrupt(struct
> amdgpu_device *adev,
> > gmc_v8_0_set_fault_enable_default(adev, false);
> >
> > if (printk_ratelimit()) {
> > - struct amdgpu_task_info task_info = { 0 };
> > + struct amdgpu_task_info task_info = { { 0 } };
>
> Hi Nathan,
> Thanks for this patch. I discussed this syntax with our language
> lawyers. Turns out, this is not quite correct, as you're now saying
> "initialize the first subobject to zero, but not the rest of the
> object." -Wmissing-field-initializers would highlight this, but it's
> not part of -Wall. It would be more correct to zero initialize the
> full struct, including all of its subobjects with `= {};`.
>
Sorry, I think I've caused some confusion here.
Elements with an omitted initializer get implicitly zero-initialized. In
C++, it's idiomatic to write `= {}` to perform aggregate
zero-initialization, but in C, that's invalid because at least one
initializer is syntactically required within the braces. As a result, `=
{0}` is an idiomatic way to perform zero-initialization of an aggregate in
C. Clang intends to suppress the -Wmissing-braces in that case; if the
warning is still being produced in a recent version of Clang, that's a bug.
However, the warning suppression was added between Clang 5 and Clang 6, so
it's very plausible that the compiler being used here is simply older than
the warning fix.
(Long story short: the change here seems fine, but should be unnecessary as
of Clang 6.)
> > amdgpu_vm_get_task_info(adev, entry->pasid, _info);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > index 72f8018fa2a8..a781a5027212 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > @@ -259,7 +259,7 @@ static int gmc_v9_0_process_interrupt(struct
> amdgpu_device *adev,
> > }
> >
> > if (printk_ratelimit()) {
> > - struct amdgpu_task_info task_info = { 0 };
> > + struct amdgpu_task_info task_info = { { 0 } };
> >
> > amdgpu_vm_get_task_info(adev, entry->pasid, _info);
> >
> > --
> > 2.18.0
> >
>
>
> --
> Thanks,
> ~Nick Desaulniers
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Add braces to initialize task_info subojects
On Wed, Sep 12, 2018 at 01:24:34PM -0700, Richard Smith wrote:
> On Wed, Sep 12, 2018 at 10:38 AM Nick Desaulniers
> wrote:
>
> > On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
> > wrote:
> > >
> > > Clang warns if there are missing braces around a subobject
> > > initializer.
> > >
> > > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
> > > around initialization of subobject [-Wmissing-braces]
> > > struct amdgpu_task_info task_info = { 0 };
> > > ^
> > > {}
> > > 1 warning generated.
> > >
> > > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:262:41: warning: suggest braces
> > > around initialization of subobject [-Wmissing-braces]
> > > struct amdgpu_task_info task_info = { 0 };
> > > ^
> > > {}
> > > 1 warning generated.
> > >
> > > Reported-by: Nick Desaulniers
> > > Signed-off-by: Nathan Chancellor
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
> > > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
> > > 2 files changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > index 9333109b210d..968cc1b8cdff 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > @@ -1444,7 +1444,7 @@ static int gmc_v8_0_process_interrupt(struct
> > amdgpu_device *adev,
> > > gmc_v8_0_set_fault_enable_default(adev, false);
> > >
> > > if (printk_ratelimit()) {
> > > - struct amdgpu_task_info task_info = { 0 };
> > > + struct amdgpu_task_info task_info = { { 0 } };
> >
> > Hi Nathan,
> > Thanks for this patch. I discussed this syntax with our language
> > lawyers. Turns out, this is not quite correct, as you're now saying
> > "initialize the first subobject to zero, but not the rest of the
> > object." -Wmissing-field-initializers would highlight this, but it's
> > not part of -Wall. It would be more correct to zero initialize the
> > full struct, including all of its subobjects with `= {};`.
> >
>
> Sorry, I think I've caused some confusion here.
>
> Elements with an omitted initializer get implicitly zero-initialized. In
> C++, it's idiomatic to write `= {}` to perform aggregate
> zero-initialization, but in C, that's invalid because at least one
> initializer is syntactically required within the braces. As a result, `=
> {0}` is an idiomatic way to perform zero-initialization of an aggregate in
> C. Clang intends to suppress the -Wmissing-braces in that case; if the
> warning is still being produced in a recent version of Clang, that's a bug.
> However, the warning suppression was added between Clang 5 and Clang 6, so
> it's very plausible that the compiler being used here is simply older than
> the warning fix.
>
> (Long story short: the change here seems fine, but should be unnecessary as
> of Clang 6.)
>
Interesting...
nathan@flashbox ~/kernels/next (master >) $ clang --version | head -n1
clang version 6.0.1 (tags/RELEASE_601/final)
I guess the v2 I sent is unnecessary then. I'll leave it up to the
maintainers to decide which one they want to take.
Thanks!
Nathan
>
> > > amdgpu_vm_get_task_info(adev, entry->pasid, _info);
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > index 72f8018fa2a8..a781a5027212 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > @@ -259,7 +259,7 @@ static int gmc_v9_0_process_interrupt(struct
> > amdgpu_device *adev,
> > > }
> > >
> > > if (printk_ratelimit()) {
> > > - struct amdgpu_task_info task_info = { 0 };
> > > + struct amdgpu_task_info task_info = { { 0 } };
> > >
> > > amdgpu_vm_get_task_info(adev, entry->pasid, _info);
> > >
> > > --
> > > 2.18.0
> > >
> >
> >
> > --
> > Thanks,
> > ~Nick Desaulniers
> >
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: reserve GDS resources statically
From: Marek Olšák
I've chosen to do it like this because it's easy and allows an arbitrary
number of processes.
Signed-off-by: Marek Olšák
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 10 --
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 3 -
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 19 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 24 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 6 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 7 --
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 3 -
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 21
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 6 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h| 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 61 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 8 --
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 125 +---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 123 +--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 124 ++-
include/uapi/drm/amdgpu_drm.h | 15 +--
19 files changed, 109 insertions(+), 519 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index b80243d3972e..7264a4930b88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -71,23 +71,20 @@ int amdgpu_bo_list_create(struct amdgpu_device *adev,
struct drm_file *filp,
/ sizeof(struct amdgpu_bo_list_entry))
return -EINVAL;
size = sizeof(struct amdgpu_bo_list);
size += num_entries * sizeof(struct amdgpu_bo_list_entry);
list = kvmalloc(size, GFP_KERNEL);
if (!list)
return -ENOMEM;
kref_init(>refcount);
- list->gds_obj = adev->gds.gds_gfx_bo;
- list->gws_obj = adev->gds.gws_gfx_bo;
- list->oa_obj = adev->gds.oa_gfx_bo;
array = amdgpu_bo_list_array_entry(list, 0);
memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry));
for (i = 0; i < num_entries; ++i) {
struct amdgpu_bo_list_entry *entry;
struct drm_gem_object *gobj;
struct amdgpu_bo *bo;
struct mm_struct *usermm;
@@ -111,27 +108,20 @@ int amdgpu_bo_list_create(struct amdgpu_device *adev,
struct drm_file *filp,
} else {
entry = [last_entry++];
}
entry->robj = bo;
entry->priority = min(info[i].bo_priority,
AMDGPU_BO_LIST_MAX_PRIORITY);
entry->tv.bo = >robj->tbo;
entry->tv.shared = !entry->robj->prime_shared_count;
- if (entry->robj->preferred_domains == AMDGPU_GEM_DOMAIN_GDS)
- list->gds_obj = entry->robj;
- if (entry->robj->preferred_domains == AMDGPU_GEM_DOMAIN_GWS)
- list->gws_obj = entry->robj;
- if (entry->robj->preferred_domains == AMDGPU_GEM_DOMAIN_OA)
- list->oa_obj = entry->robj;
-
total_size += amdgpu_bo_size(entry->robj);
trace_amdgpu_bo_list_set(list, entry->robj);
}
list->first_userptr = first_userptr;
list->num_entries = num_entries;
trace_amdgpu_cs_bo_status(list->num_entries, total_size);
*result = list;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
index 61b089768e1c..30f12a60aa28 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
@@ -36,23 +36,20 @@ struct amdgpu_bo_list_entry {
struct ttm_validate_buffer tv;
struct amdgpu_bo_va *bo_va;
uint32_tpriority;
struct page **user_pages;
int user_invalidated;
};
struct amdgpu_bo_list {
struct rcu_head rhead;
struct kref refcount;
- struct amdgpu_bo *gds_obj;
- struct amdgpu_bo *gws_obj;
- struct amdgpu_bo *oa_obj;
unsigned first_userptr;
unsigned num_entries;
};
int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id,
struct amdgpu_bo_list **result);
void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
struct list_head *validated);
void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 1081fd00b059..88b58facf29e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
Re: [PATCH 1/2] drm/amdgpu: remove amdgpu_bo_list_entry.robj
On 2018-09-12 04:55 AM, Christian König wrote:
> We can get that just by casting tv.bo.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 42 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 58
> -
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +-
> 4 files changed, 58 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> index b80243d3972e..14d2982a47cc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> @@ -49,8 +49,11 @@ static void amdgpu_bo_list_free(struct kref *ref)
> refcount);
> struct amdgpu_bo_list_entry *e;
>
> - amdgpu_bo_list_for_each_entry(e, list)
> - amdgpu_bo_unref(>robj);
> + amdgpu_bo_list_for_each_entry(e, list) {
> + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
> +
> + amdgpu_bo_unref();
> + }
>
> call_rcu(>rhead, amdgpu_bo_list_free_rcu);
> }
> @@ -112,21 +115,20 @@ int amdgpu_bo_list_create(struct amdgpu_device *adev,
> struct drm_file *filp,
> entry = [last_entry++];
> }
>
> - entry->robj = bo;
> entry->priority = min(info[i].bo_priority,
> AMDGPU_BO_LIST_MAX_PRIORITY);
> - entry->tv.bo = >robj->tbo;
> - entry->tv.shared = !entry->robj->prime_shared_count;
> -
> - if (entry->robj->preferred_domains == AMDGPU_GEM_DOMAIN_GDS)
> - list->gds_obj = entry->robj;
> - if (entry->robj->preferred_domains == AMDGPU_GEM_DOMAIN_GWS)
> - list->gws_obj = entry->robj;
> - if (entry->robj->preferred_domains == AMDGPU_GEM_DOMAIN_OA)
> - list->oa_obj = entry->robj;
> -
> - total_size += amdgpu_bo_size(entry->robj);
> - trace_amdgpu_bo_list_set(list, entry->robj);
> + entry->tv.bo = >tbo;
> + entry->tv.shared = !bo->prime_shared_count;
You're no longer initializing entry->priority here. Is that intentional?
Regards,
Felix
> +
> + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_GDS)
> + list->gds_obj = bo;
> + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_GWS)
> + list->gws_obj = bo;
> + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_OA)
> + list->oa_obj = bo;
> +
> + total_size += amdgpu_bo_size(bo);
> + trace_amdgpu_bo_list_set(list, bo);
> }
>
> list->first_userptr = first_userptr;
> @@ -138,8 +140,11 @@ int amdgpu_bo_list_create(struct amdgpu_device *adev,
> struct drm_file *filp,
> return 0;
>
> error_free:
> - while (i--)
> - amdgpu_bo_unref([i].robj);
> + while (i--) {
> + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo);
> +
> + amdgpu_bo_unref();
> + }
> kvfree(list);
> return r;
>
> @@ -191,9 +196,10 @@ void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
>* with the same priority, i.e. it must be stable.
>*/
> amdgpu_bo_list_for_each_entry(e, list) {
> + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
> unsigned priority = e->priority;
>
> - if (!e->robj->parent)
> + if (!bo->parent)
> list_add_tail(>tv.head, [priority]);
>
> e->user_pages = NULL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
> index 61b089768e1c..7c5f5d1601e6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
> @@ -32,7 +32,6 @@ struct amdgpu_bo_va;
> struct amdgpu_fpriv;
>
> struct amdgpu_bo_list_entry {
> - struct amdgpu_bo*robj;
> struct ttm_validate_buffer tv;
> struct amdgpu_bo_va *bo_va;
> uint32_tpriority;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index c5cc648a1b4e..2e488c6f9562 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -39,6 +39,7 @@ static int amdgpu_cs_user_fence_chunk(struct
> amdgpu_cs_parser *p,
> uint32_t *offset)
> {
> struct drm_gem_object *gobj;
> + struct amdgpu_bo *bo;
> unsigned long size;
> int r;
>
> @@ -46,21 +47,21 @@ static int amdgpu_cs_user_fence_chunk(struct
> amdgpu_cs_parser *p,
> if (gobj == NULL)
> return -EINVAL;
>
> - p->uf_entry.robj =
Re: [PATCH xf86-video-ati] Fix uninitialized use of local variable pitch in radeon_setup_kernel_mem
On Wed, Sep 5, 2018 at 12:24 PM Michel Dänzer wrote:
>
> From: Michel Dänzer
>
> Fixes server reset.
>
> Pointed out by clang:
>
> ../../src/radeon_kms.c:2721:9: warning: variable 'pitch' is used
> uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
> if (!info->front_buffer) {
> ^~~
> ../../src/radeon_kms.c:2765:27: note: uninitialized use occurs here
> pScrn->displayWidth = pitch / cpp;
> ^
> ../../src/radeon_kms.c:2721:5: note: remove the 'if' if its condition is
> always true
> if (!info->front_buffer) {
> ^
> ../../src/radeon_kms.c:2680:14: note: initialize the variable 'pitch' to
> silence this warning
> int pitch;
> ^
> = 0
>
> Signed-off-by: Michel Dänzer
Reviewed-by: Alex Deucher
> ---
> src/radeon_kms.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/src/radeon_kms.c b/src/radeon_kms.c
> index a24776811..ae69f3353 100644
> --- a/src/radeon_kms.c
> +++ b/src/radeon_kms.c
> @@ -2760,10 +2760,11 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
> if (tiling_flags)
> radeon_bo_set_tiling(info->front_buffer->bo.radeon,
> tiling_flags, pitch);
> }
> -}
>
> -pScrn->displayWidth = pitch / cpp;
> + pScrn->displayWidth = pitch / cpp;
> +}
>
> +pitch = pScrn->displayWidth * cpp;
> xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n",
>pitch * pScrn->virtualY / 1024);
> radeon_kms_update_vram_limit(pScrn, pitch * pScrn->virtualY);
> --
> 2.19.0.rc1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amd: Properly initialize all subobjects in structures
Clang warns if there are missing braces around a subobject
initializer. Adding these braces only initializes the first
subobject; an empty set of braces initializes the structure
and all of its subobjects.
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
around initialization of subobject [-Wmissing-braces]
struct amdgpu_task_info task_info = { 0 };
^
{}
1 warning generated.
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:262:41: warning: suggest braces
around initialization of subobject [-Wmissing-braces]
struct amdgpu_task_info task_info = { 0 };
^
{}
1 warning generated.
The warnings above are the only ones of this type in drm/amd but do
this conversion for all instances of this idiom for consistency (also
used by several other locations in the kernel tree).
Reported-by: Nick Desaulniers
Signed-off-by: Nathan Chancellor
---
v1 -> v2:
* Use empty braces for initialization as suggested by Nick
* Convert all users of the sets of braces + 0 idiom to single set of
empty braces as suggested by Alex
If this patchset is too large or incorrectly done, please let me know.
Seemed like a logical thing to do in one patch but I'm happy to break it
down.
Thanks,
Nathan
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 2 +-
.../gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cik.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/si_dpm.c | 4 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 8 +--
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 8 +--
.../gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 2 +-
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +-
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +++
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 14 ++---
.../gpu/drm/amd/display/dc/bios/bios_parser.c | 4 +-
.../drm/amd/display/dc/bios/bios_parser2.c| 10 ++--
.../amd/display/dc/bios/bios_parser_common.c | 2 +-
.../drm/amd/display/dc/bios/command_table.c | 22
.../drm/amd/display/dc/bios/command_table2.c | 12 ++---
.../gpu/drm/amd/display/dc/calcs/dce_calcs.c | 4 +-
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 10 ++--
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +--
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 25 +
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 4 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 52 +--
.../drm/amd/display/dc/core/dc_link_hwss.c| 2 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 12 ++---
.../gpu/drm/amd/display/dc/dce/dce_audio.c| 2 +-
.../drm/amd/display/dc/dce/dce_clock_source.c | 12 ++---
.../gpu/drm/amd/display/dc/dce/dce_clocks.c | 14 ++---
.../drm/amd/display/dc/dce/dce_link_encoder.c | 16 +++---
.../amd/display/dc/dce/dce_stream_encoder.c | 8 +--
.../drm/amd/display/dc/dce/dce_transform.c| 2 +-
.../amd/display/dc/dce100/dce100_resource.c | 2 +-
.../display/dc/dce110/dce110_hw_sequencer.c | 22
.../amd/display/dc/dce110/dce110_resource.c | 6 +--
.../display/dc/dce110/dce110_transform_v.c| 6 +--
.../amd/display/dc/dce112/dce112_resource.c | 10 ++--
.../amd/display/dc/dce120/dce120_resource.c | 6 +--
.../drm/amd/display/dc/dce80/dce80_resource.c | 6 +--
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 22
.../amd/display/dc/dcn10/dcn10_link_encoder.c | 16 +++---
.../display/dc/dcn10/dcn10_stream_encoder.c | 8 +--
.../gpu/drm/amd/display/dc/i2caux/i2caux.c| 6 +--
drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h | 2 +-
.../amd/display/modules/freesync/freesync.c | 6 +--
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 2 +-
.../gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 2 +-
.../gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 +-
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 10 ++--
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 2 +-
.../gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 2 +-
.../drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 +-
.../amd/powerplay/smumgr/polaris10_smumgr.c | 10 ++--
.../drm/amd/powerplay/smumgr/smu7_smumgr.c| 6 +--
.../drm/amd/powerplay/smumgr/smu8_smumgr.c| 4 +-
.../drm/amd/powerplay/smumgr/vega10_smumgr.c
Re: [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc
On Wed, Sep 12, 2018 at 3:29 PM Alex Deucher wrote:
>
> From: Bhawanpreet Lakha
>
> Add Raven2 definitions in the dc code
>
> Signed-off-by: Bhawanpreet Lakha
> Reviewed-by: Harry Wentland
> Reviewed-by: Huang Rui
> Acked-by: Alex Deucher Signed-off-by: Alex Deucher
> ---
> .../amd/display/dc/bios/command_table_helper2.c| 5 +++
> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +
> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +
Some of the clock source changes look suspect. See comments below.
Alex
> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36
> +-
> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 +++
> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 +++
> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +++
> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 +
> drivers/gpu/drm/amd/display/include/dal_types.h| 3 ++
> 9 files changed, 78 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> index bbbcef566c55..65b006ad372e 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> @@ -61,6 +61,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> return true;
> #endif
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> + *h = dal_cmd_tbl_helper_dce112_get_table2();
> + return true;
> +#endif
> case DCE_VERSION_12_0:
> *h = dal_cmd_tbl_helper_dce112_get_table2();
> return true;
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index d981755d1e4d..721dd13d2ed2 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -88,6 +88,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id
> asic_id)
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> case FAMILY_RV:
> dc_version = DCN_VERSION_1_0;
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
> + dc_version = DCN_VERSION_1_01;
> +#endif
> break;
> #endif
> default:
> @@ -138,6 +142,9 @@ struct resource_pool *dc_create_resource_pool(
>
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> case DCN_VERSION_1_0:
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> +#endif
> res_pool = dcn10_create_resource_pool(
> num_virtual_links, dc);
> break;
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> index 5a9f3601ffb6..ae3c44aff1c8 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> @@ -601,6 +601,9 @@ static uint32_t dce110_get_pix_clk_dividers(
> case DCN_VERSION_1_0:
> #endif
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> +#endif
> dce112_get_pix_clk_dividers_helper(clk_src,
> pll_settings, pix_clk_params);
> break;
> @@ -907,6 +910,10 @@ static bool dce110_program_pix_clk(
> case DCN_VERSION_1_0:
> #endif
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + case DCN_VERSION_1_01:
> +#endif
> +
> if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
> bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
>
> pll_settings->use_external_clk;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> index 1b519f8f044f..65a596ffa02a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> @@ -152,7 +152,10 @@ enum dcn10_clk_src_array_id {
> DCN10_CLK_SRC_PLL1,
> DCN10_CLK_SRC_PLL2,
> DCN10_CLK_SRC_PLL3,
> - DCN10_CLK_SRC_TOTAL
> + DCN10_CLK_SRC_TOTAL,
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
> +#endif
This change looks suspect.
Alex
> };
>
> /* begin *
> @@ -1163,6 +1166,10 @@ static bool construct(
> /* max pipe num for ASIC before check pipe fuses */
> pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
> + if (dc->ctx->dce_version == DCN_VERSION_1_01)
> + pool->base.pipe_count = 3;
> +#endif
> dc->caps.max_video_width = 3840;
> dc->caps.max_downscale_ratio = 200;
>
Re: [PATCH] drm/amdgpu: Add braces to initialize task_info subojects
On Wed, Sep 12, 2018 at 02:44:34PM -0400, Alex Deucher wrote:
> On Wed, Sep 12, 2018 at 2:40 PM Nathan Chancellor
> wrote:
> >
> > On Wed, Sep 12, 2018 at 10:38:30AM -0700, Nick Desaulniers wrote:
> > > On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
> > > wrote:
> > > >
> > > > Clang warns if there are missing braces around a subobject
> > > > initializer.
> > > >
> > > > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
> > > > around initialization of subobject [-Wmissing-braces]
> > > > struct amdgpu_task_info task_info = { 0 };
> > > > ^
> > > > {}
> > > > 1 warning generated.
> > > >
> > > > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:262:41: warning: suggest braces
> > > > around initialization of subobject [-Wmissing-braces]
> > > > struct amdgpu_task_info task_info = { 0 };
> > > > ^
> > > > {}
> > > > 1 warning generated.
> > > >
> > > > Reported-by: Nick Desaulniers
> > > > Signed-off-by: Nathan Chancellor
> > > > ---
> > > > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
> > > > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
> > > > 2 files changed, 2 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > > b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > > index 9333109b210d..968cc1b8cdff 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > > @@ -1444,7 +1444,7 @@ static int gmc_v8_0_process_interrupt(struct
> > > > amdgpu_device *adev,
> > > > gmc_v8_0_set_fault_enable_default(adev, false);
> > > >
> > > > if (printk_ratelimit()) {
> > > > - struct amdgpu_task_info task_info = { 0 };
> > > > + struct amdgpu_task_info task_info = { { 0 } };
> > >
> > > Hi Nathan,
> > > Thanks for this patch. I discussed this syntax with our language
> > > lawyers. Turns out, this is not quite correct, as you're now saying
> > > "initialize the first subobject to zero, but not the rest of the
> > > object." -Wmissing-field-initializers would highlight this, but it's
> > > not part of -Wall. It would be more correct to zero initialize the
> > > full struct, including all of its subobjects with `= {};`.
> > >
> >
> > Good point, I was debating on which one was correct. There are several
> > places in this driver that use the multiple brace + 0 idiom, which is
> > why I used this form. I will spin up a v2 with your suggestion, thank
> > you for the review!
>
> Feel free to fix up the others as well. The others were only changed
> due to the same warning you sent the patch for.
>
> Alex
>
Hi Alex,
Thank you for the information, I will do that in v2.
Thanks,
Nathan
> >
> > Nathan
> >
> > > >
> > > > amdgpu_vm_get_task_info(adev, entry->pasid, _info);
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > > index 72f8018fa2a8..a781a5027212 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > > @@ -259,7 +259,7 @@ static int gmc_v9_0_process_interrupt(struct
> > > > amdgpu_device *adev,
> > > > }
> > > >
> > > > if (printk_ratelimit()) {
> > > > - struct amdgpu_task_info task_info = { 0 };
> > > > + struct amdgpu_task_info task_info = { { 0 } };
> > > >
> > > > amdgpu_vm_get_task_info(adev, entry->pasid, _info);
> > > >
> > > > --
> > > > 2.18.0
> > > >
> > >
> > >
> > > --
> > > Thanks,
> > > ~Nick Desaulniers
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/ttm: once more fix ttm_bo_bulk_move_lru_tail
On Wed, Sep 12, 2018 at 3:25 PM Christian König
wrote:
>
> While cutting the lists we sometimes accidentally added a list_head from
> the stack to the LRUs, effectively corrupting the list.
>
> Remove the list cutting and use explicit list manipulation instead.
>
> Signed-off-by: Christian König
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/ttm/ttm_bo.c | 51
> ++--
> 1 file changed, 30 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
> index 138c98902033..b2a33bf1ef10 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo.c
> @@ -247,23 +247,18 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object
> *bo,
> }
> EXPORT_SYMBOL(ttm_bo_move_to_lru_tail);
>
> -static void ttm_bo_bulk_move_helper(struct ttm_lru_bulk_move_pos *pos,
> - struct list_head *lru, bool is_swap)
> +static void ttm_list_move_bulk_tail(struct list_head *list,
> + struct list_head *first,
> + struct list_head *last)
> {
> - struct list_head *list;
> - LIST_HEAD(entries);
> - LIST_HEAD(before);
> + first->prev->next = last->next;
> + last->next->prev = first->prev;
>
> - reservation_object_assert_held(pos->last->resv);
> - list = is_swap ? >last->swap : >last->lru;
> - list_cut_position(, lru, list);
> + list->prev->next = first;
> + first->prev = list->prev;
>
> - reservation_object_assert_held(pos->first->resv);
> - list = is_swap ? pos->first->swap.prev : pos->first->lru.prev;
> - list_cut_position(, , list);
> -
> - list_splice(, lru);
> - list_splice_tail(, lru);
> + last->next = list;
> + list->prev = last;
> }
>
> void ttm_bo_bulk_move_lru_tail(struct ttm_lru_bulk_move *bulk)
> @@ -271,23 +266,33 @@ void ttm_bo_bulk_move_lru_tail(struct ttm_lru_bulk_move
> *bulk)
> unsigned i;
>
> for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
> + struct ttm_lru_bulk_move_pos *pos = >tt[i];
> struct ttm_mem_type_manager *man;
>
> - if (!bulk->tt[i].first)
> + if (!pos->first)
> continue;
>
> - man = >tt[i].first->bdev->man[TTM_PL_TT];
> - ttm_bo_bulk_move_helper(>tt[i], >lru[i], false);
> + reservation_object_assert_held(pos->first->resv);
> + reservation_object_assert_held(pos->last->resv);
> +
> + man = >first->bdev->man[TTM_PL_TT];
> + ttm_list_move_bulk_tail(>lru[i], >first->lru,
> + >last->lru);
> }
>
> for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
> + struct ttm_lru_bulk_move_pos *pos = >vram[i];
> struct ttm_mem_type_manager *man;
>
> - if (!bulk->vram[i].first)
> + if (!pos->first)
> continue;
>
> - man = >vram[i].first->bdev->man[TTM_PL_VRAM];
> - ttm_bo_bulk_move_helper(>vram[i], >lru[i], false);
> + reservation_object_assert_held(pos->first->resv);
> + reservation_object_assert_held(pos->last->resv);
> +
> + man = >first->bdev->man[TTM_PL_VRAM];
> + ttm_list_move_bulk_tail(>lru[i], >first->lru,
> + >last->lru);
> }
>
> for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
> @@ -297,8 +302,12 @@ void ttm_bo_bulk_move_lru_tail(struct ttm_lru_bulk_move
> *bulk)
> if (!pos->first)
> continue;
>
> + reservation_object_assert_held(pos->first->resv);
> + reservation_object_assert_held(pos->last->resv);
> +
> lru = >first->bdev->glob->swap_lru[i];
> - ttm_bo_bulk_move_helper(>swap[i], lru, true);
> + ttm_list_move_bulk_tail(lru, >first->swap,
> + >last->swap);
> }
> }
> EXPORT_SYMBOL(ttm_bo_bulk_move_lru_tail);
> --
> 2.14.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 16/16] drm/amdgpu: set CG flags for raven2 (v2)
From: Huang Rui Raven2 does not enable all of the CG flags that raven1 does. v2: rebase (Alex) Signed-off-by: Huang Rui Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 57 +- 1 file changed, 37 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 0a935604ec9e..f5a44d1fe5da 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -714,26 +714,43 @@ static int soc15_common_early_init(void *handle) adev->external_rev_id = adev->rev_id + 0x28; break; case CHIP_RAVEN: - adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | - AMD_CG_SUPPORT_GFX_MGLS | - AMD_CG_SUPPORT_GFX_RLC_LS | - AMD_CG_SUPPORT_GFX_CP_LS | - AMD_CG_SUPPORT_GFX_3D_CGCG | - AMD_CG_SUPPORT_GFX_3D_CGLS | - AMD_CG_SUPPORT_GFX_CGCG | - AMD_CG_SUPPORT_GFX_CGLS | - AMD_CG_SUPPORT_BIF_MGCG | - AMD_CG_SUPPORT_BIF_LS | - AMD_CG_SUPPORT_HDP_MGCG | - AMD_CG_SUPPORT_HDP_LS | - AMD_CG_SUPPORT_DRM_MGCG | - AMD_CG_SUPPORT_DRM_LS | - AMD_CG_SUPPORT_ROM_MGCG | - AMD_CG_SUPPORT_MC_MGCG | - AMD_CG_SUPPORT_MC_LS | - AMD_CG_SUPPORT_SDMA_MGCG | - AMD_CG_SUPPORT_SDMA_LS | - AMD_CG_SUPPORT_VCN_MGCG; + if (adev->rev_id >= 0x8) + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_BIF_LS | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_ROM_MGCG | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_VCN_MGCG; + else + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_BIF_MGCG | + AMD_CG_SUPPORT_BIF_LS | + AMD_CG_SUPPORT_HDP_MGCG | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_DRM_MGCG | + AMD_CG_SUPPORT_DRM_LS | + AMD_CG_SUPPORT_ROM_MGCG | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_SDMA_MGCG | + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_VCN_MGCG; adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 10/16] drm/amdgpu: fix the VM fault while write at the top of the invisible vram
From: Huang Rui Raven2 has a HW issue that it is unable to use the vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the workaround that increase system aperture high address to get rid of the VM fault and hardware hang. Signed-off-by: Huang Rui Reviewed-by: Alex Deucher Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 15 +-- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 15 +-- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index ffd0ec9586d1..65f58ebcf835 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -73,8 +73,19 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) /* Program the system aperture low logical page number. */ WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18); - WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, -max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18); + + if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8) + /* +* Raven2 has a HW issue that it is unable to use the vram which +* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the +* workaround that increase system aperture high address (add 1) +* to get rid of the VM fault and hardware hang. +*/ + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, +(max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18) + 0x1); + else + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, +max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18); /* Set default page address. */ value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index b121eb6a0ad4..2a126c6950c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -91,8 +91,19 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) /* Program the system aperture low logical page number. */ WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18); - WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, -max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18); + + if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8) + /* +* Raven2 has a HW issue that it is unable to use the vram which +* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the +* workaround that increase system aperture high address (add 1) +* to get rid of the VM fault and hardware hang. +*/ + WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, +(max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18) + 0x1); + else + WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, +max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18); /* Set default page address. */ value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/16] drm/amd/powerplay: round up the Mhz convertion (v2)
From: Evan Quan
Since the clock value there may be like 2 10Khz.
v2: rebase (Alex)
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 26d130a91725..5b55c709fb1c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -211,12 +211,18 @@ static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr,
const void *input)
return 0;
}
+static inline uint32_t convert_10k_to_mhz(uint32_t clock)
+{
+ return (clock + 99) / 100;
+}
+
static int smu10_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
{
struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
- if (smu10_data->need_min_deep_sleep_dcefclk &&
smu10_data->deep_sleep_dcefclk != clock/100) {
- smu10_data->deep_sleep_dcefclk = clock/100;
+ if (smu10_data->need_min_deep_sleep_dcefclk &&
+ smu10_data->deep_sleep_dcefclk != convert_10k_to_mhz(clock)) {
+ smu10_data->deep_sleep_dcefclk = convert_10k_to_mhz(clock);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepDcefclk,
smu10_data->deep_sleep_dcefclk);
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc
From: Bhawanpreet Lakha
Add Raven2 definitions in the dc code
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
Reviewed-by: Huang Rui
Acked-by: Alex Deucher
---
.../amd/display/dc/bios/command_table_helper2.c| 5 +++
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 +-
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 +++
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 +++
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +++
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 +
drivers/gpu/drm/amd/display/include/dal_types.h| 3 ++
9 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index bbbcef566c55..65b006ad372e 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -61,6 +61,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
return true;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+ *h = dal_cmd_tbl_helper_dce112_get_table2();
+ return true;
+#endif
case DCE_VERSION_12_0:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index d981755d1e4d..721dd13d2ed2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -88,6 +88,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id
asic_id)
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case FAMILY_RV:
dc_version = DCN_VERSION_1_0;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
+ dc_version = DCN_VERSION_1_01;
+#endif
break;
#endif
default:
@@ -138,6 +142,9 @@ struct resource_pool *dc_create_resource_pool(
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0:
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+#endif
res_pool = dcn10_create_resource_pool(
num_virtual_links, dc);
break;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 5a9f3601ffb6..ae3c44aff1c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -601,6 +601,9 @@ static uint32_t dce110_get_pix_clk_dividers(
case DCN_VERSION_1_0:
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+#endif
dce112_get_pix_clk_dividers_helper(clk_src,
pll_settings, pix_clk_params);
break;
@@ -907,6 +910,10 @@ static bool dce110_program_pix_clk(
case DCN_VERSION_1_0:
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+#endif
+
if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
pll_settings->use_external_clk;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 1b519f8f044f..65a596ffa02a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -152,7 +152,10 @@ enum dcn10_clk_src_array_id {
DCN10_CLK_SRC_PLL1,
DCN10_CLK_SRC_PLL2,
DCN10_CLK_SRC_PLL3,
- DCN10_CLK_SRC_TOTAL
+ DCN10_CLK_SRC_TOTAL,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
+#endif
};
/* begin *
@@ -1163,6 +1166,10 @@ static bool construct(
/* max pipe num for ASIC before check pipe fuses */
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (dc->ctx->dce_version == DCN_VERSION_1_01)
+ pool->base.pipe_count = 3;
+#endif
dc->caps.max_video_width = 3840;
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
@@ -1194,13 +1201,28 @@ static bool construct(
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL2,
_src_regs[2], false);
+
+#ifdef CONFIG_DRM_AMD_DC_DCN1_01
+ if (dc->ctx->dce_version == DCN_VERSION_1_0) {
+ pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
[PATCH 15/16] drm/amd/powerplay: disable raven2 force dpm level support (v2)
From: Evan Quan
It's not supported yet.
v2: rebase (Alex)
Signed-off-by: Evan Quan
Reviewed-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 5b55c709fb1c..9808bd48b386 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -551,12 +551,18 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr
*hwmgr,
enum amd_dpm_forced_level level)
{
struct smu10_hwmgr *data = hwmgr->backend;
+ struct amdgpu_device *adev = hwmgr->adev;
if (hwmgr->smu_version < 0x1E3700) {
pr_info("smu firmware version too old, can not set dpm
level\n");
return 0;
}
+ /* Disable UMDPSTATE support on rv2 temporarily */
+ if ((adev->asic_type == CHIP_RAVEN) &&
+ (adev->rev_id >= 8))
+ return 0;
+
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/16] drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2 compatible
From: Evan Quan
Check the raven2 version number as well.
Signed-off-by: Evan Quan
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
index bb07d43f3874..6f961dec2088 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
@@ -177,7 +177,8 @@ static int smu10_verify_smc_interface(struct pp_hwmgr
*hwmgr)
PPSMC_MSG_GetDriverIfVersion);
smc_driver_if_version = smu10_read_arg_from_smc(hwmgr);
- if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION) {
+ if ((smc_driver_if_version != SMU10_DRIVER_IF_VERSION) &&
+ (smc_driver_if_version != SMU10_DRIVER_IF_VERSION + 1)) {
pr_err("Attempt to read SMC IF Version Number Failed!\n");
return -EINVAL;
}
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 02/16] drm/amdgpu: set external rev id for raven2
It's different from raven1. Signed-off-by: Huang Rui Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 794cfe4a52d1..0a935604ec9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -742,7 +742,10 @@ static int soc15_common_early_init(void *handle) AMD_PG_SUPPORT_CP | AMD_PG_SUPPORT_RLC_SMU_HS; - adev->external_rev_id = 0x1; + if (adev->rev_id >= 0x8) + adev->external_rev_id = adev->rev_id + 0x81; + else + adev->external_rev_id = 0x1; break; case CHIP_PICASSO: adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS | -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/16] drm/amdgpu: add raven2 vcn firmware support
From: Feifei Xu
Specify raven2 vcn firmware on amdgpu_vce_sw_init.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 93ffba2cbec4..a74498ce87ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -43,9 +43,11 @@
/* Firmware Names */
#define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
#define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
+#define FIRMWARE_RAVEN2"amdgpu/raven2_vcn.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN);
MODULE_FIRMWARE(FIRMWARE_PICASSO);
+MODULE_FIRMWARE(FIRMWARE_RAVEN2);
static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
@@ -61,7 +63,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_RAVEN:
- fw_name = FIRMWARE_RAVEN;
+if (adev->rev_id >= 8)
+ fw_name = FIRMWARE_RAVEN2;
+ else
+ fw_name = FIRMWARE_RAVEN;
break;
case CHIP_PICASSO:
fw_name = FIRMWARE_PICASSO;
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 03/16] drm/amdgpu: add raven2 to gpu_info firmware
From: Feifei Xu
Add gpu_info firmware for raven2.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 39fe66810d53..762dc5f886cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -63,6 +63,7 @@ MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
#define AMDGPU_RESUME_MS 2000
@@ -1334,7 +1335,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
chip_name = "vega12";
break;
case CHIP_RAVEN:
- chip_name = "raven";
+ if (adev->rev_id >= 8)
+ chip_name = "raven2";
+ else
+ chip_name = "raven";
break;
case CHIP_PICASSO:
chip_name = "picasso";
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 05/16] drm/amdgpu: add psp support for raven2
From: Likun Gao
Modified for using raven2_asd.bin to replace raven_asd.bin for raven2
Signed-off-by: Likun Gao
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 73a1ca833292..4edeb0496a12 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -36,6 +36,7 @@
MODULE_FIRMWARE("amdgpu/raven_asd.bin");
MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
+MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
static int
psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type
*type)
@@ -112,7 +113,10 @@ static int psp_v10_0_init_microcode(struct psp_context
*psp)
switch (adev->asic_type) {
case CHIP_RAVEN:
- chip_name = "raven";
+ if (adev->rev_id >= 0x8)
+ chip_name = "raven2";
+ else
+ chip_name = "raven";
break;
case CHIP_PICASSO:
chip_name = "picasso";
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 01/16] drm/amdgpu: move get_rev_id at first before load gpu_info firmware
From: Huang Rui
Rev id is used for identifying Raven2 series of chips. So we would better to
initialize it at first.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index e338ad6d0d20..794cfe4a52d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -479,6 +479,11 @@ static const struct amdgpu_ip_block_version
vega10_common_ip_block =
.funcs = _common_ip_funcs,
};
+static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
+{
+ return adev->nbio_funcs->get_rev_id(adev);
+}
+
int soc15_set_ip_blocks(struct amdgpu_device *adev)
{
/* Set IP register base before any HW register access */
@@ -507,6 +512,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
adev->df_funcs = _v3_6_funcs;
else
adev->df_funcs = _v1_7_funcs;
+
+ adev->rev_id = soc15_get_rev_id(adev);
adev->nbio_funcs->detect_hw_virt(adev);
if (amdgpu_sriov_vf(adev))
@@ -581,11 +588,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
return 0;
}
-static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
-{
- return adev->nbio_funcs->get_rev_id(adev);
-}
-
static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring
*ring)
{
adev->nbio_funcs->hdp_flush(adev, ring);
@@ -642,7 +644,6 @@ static int soc15_common_early_init(void *handle)
adev->asic_funcs = _asic_funcs;
- adev->rev_id = soc15_get_rev_id(adev);
adev->external_rev_id = 0xFF;
switch (adev->asic_type) {
case CHIP_VEGA10:
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/16] drm/amdgpu/gfx9: add raven2 golden setting
From: Feifei Xu
Golden register settings from the hw team.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 ++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7b9e1c274c59..4991ae00a4ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -187,6 +187,29 @@ static const struct soc15_reg_golden
golden_settings_gc_9_1_rv1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x0800)
};
+static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
+{
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7f, 0x0400),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7f,
0x0a00),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0f, 0x0880),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8f, 0x0880),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8f, 0x0880),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x77ff, 0x26013041),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0x77ff,
0x26013041),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8f, 0x0880),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x,
0x0404),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0f,
0x0880),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0f,
0x0880),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0f,
0x0880),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0f,
0x0880),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0f,
0x0880),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0x,
0x),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0x,
0x0010),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x0100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8f, 0x0880),
+};
+
static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0x, 0x),
@@ -255,6 +278,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
#define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x2442
#define PICASSO_GB_ADDR_CONFIG_GOLDEN 0x2442
+#define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -294,6 +318,17 @@ static void gfx_v9_0_init_golden_registers(struct
amdgpu_device *adev)
ARRAY_SIZE(golden_settings_gc_9_0_vg20));
break;
case CHIP_RAVEN:
+ soc15_program_register_sequence(adev, golden_settings_gc_9_1,
+
ARRAY_SIZE(golden_settings_gc_9_1));
+ if (adev->rev_id >= 8)
+ soc15_program_register_sequence(adev,
+
golden_settings_gc_9_1_rv2,
+
ARRAY_SIZE(golden_settings_gc_9_1_rv2));
+ else
+ soc15_program_register_sequence(adev,
+
golden_settings_gc_9_1_rv1,
+
ARRAY_SIZE(golden_settings_gc_9_1_rv1));
+ break;
case CHIP_PICASSO:
soc15_program_register_sequence(adev,
golden_settings_gc_9_1,
@@ -1288,7 +1323,10 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device
*adev)
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
- gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
+ if (adev->rev_id >= 8)
+ gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
+ else
+ gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
break;
case CHIP_PICASSO:
adev->gfx.config.max_hw_contexts = 8;
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/16] drm/amdgpu/sdma4: Add raven2 golden setting
From: Feifei Xu
Golden register settings from the hw team.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 7ef140aaca3c..75be0b9ed2c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -185,6 +185,12 @@ static const struct soc15_reg_golden
golden_settings_sdma_rv1[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ,
0x0018773f, 0x0002)
};
+static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
+{
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f,
0x3001),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ,
0x0018773f, 0x3001)
+};
+
static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
u32 instance, u32 offset)
{
@@ -225,11 +231,16 @@ static void sdma_v4_0_init_golden_registers(struct
amdgpu_device *adev)
case CHIP_RAVEN:
case CHIP_PICASSO:
soc15_program_register_sequence(adev,
-golden_settings_sdma_4_1,
-
ARRAY_SIZE(golden_settings_sdma_4_1));
- soc15_program_register_sequence(adev,
-golden_settings_sdma_rv1,
-
ARRAY_SIZE(golden_settings_sdma_rv1));
+ golden_settings_sdma_4_1,
+
ARRAY_SIZE(golden_settings_sdma_4_1));
+ if (adev->rev_id >= 8)
+ soc15_program_register_sequence(adev,
+
golden_settings_sdma_rv2,
+
ARRAY_SIZE(golden_settings_sdma_rv2));
+ else
+ soc15_program_register_sequence(adev,
+
golden_settings_sdma_rv1,
+
ARRAY_SIZE(golden_settings_sdma_rv1));
break;
default:
break;
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/16] drm/amdgpu/gfx9: add support for raven2 gfx firmware
From: Feifei Xu
use raven2 gfx firmware.
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ad20747bace8..7b9e1c274c59 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -87,6 +87,13 @@ MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
+MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
+MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
+MODULE_FIRMWARE("amdgpu/raven2_me.bin");
+MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
+MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
+MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
+
static const struct soc15_reg_golden golden_settings_gc_9_0[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00f, 0x0400),
@@ -573,7 +580,10 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device
*adev)
chip_name = "vega20";
break;
case CHIP_RAVEN:
- chip_name = "raven";
+ if (adev->rev_id >= 8)
+ chip_name = "raven2";
+ else
+ chip_name = "raven";
break;
case CHIP_PICASSO:
chip_name = "picasso";
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/16] drm/amd/display: Add DC config flag for Raven2 (v2)
From: Bhawanpreet Lakha Add DRM_AMD_DC_DCN1_01 config flag for Raven2 v2: Make DC select DRM_AMD_DC_DCN1_01 (Alex) Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Reviewed-by: Huang Rui Acked-by: Alex Deucher --- drivers/gpu/drm/amd/display/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index ed654a76c76a..13a6ce9c8e94 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -5,6 +5,7 @@ config DRM_AMD_DC bool "AMD DC - Enable new display engine" default y select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) + select DRM_AMD_DC_DCN1_01 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) help Choose this option if you want to use the new display engine support for AMDGPU. This adds required support for Vega and @@ -15,6 +16,11 @@ config DRM_AMD_DC_DCN1_0 help RV family support for display engine +config DRM_AMD_DC_DCN1_01 + def_bool n + help + RV2 family for display engine + config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/16] Add support for Raven2
Raven2 is a new Raven APU. Alex Deucher (1): drm/amdgpu: set external rev id for raven2 Bhawanpreet Lakha (2): drm/amd/display: Add Raven2 definitions in dc drm/amd/display: Add DC config flag for Raven2 (v2) Evan Quan (3): drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2 compatible drm/amd/powerplay: round up the Mhz convertion (v2) drm/amd/powerplay: disable raven2 force dpm level support (v2) Feifei Xu (6): drm/amdgpu: add raven2 to gpu_info firmware drm/amdgpu: add raven2 vcn firmware support drm/amdgpu/sdma4: specify raven2 firmware. drm/amdgpu/sdma4: Add raven2 golden setting drm/amdgpu/gfx9: add support for raven2 gfx firmware drm/amdgpu/gfx9: add raven2 golden setting Huang Rui (3): drm/amdgpu: move get_rev_id at first before load gpu_info firmware drm/amdgpu: fix the VM fault while write at the top of the invisible vram drm/amdgpu: set CG flags for raven2 (v2) Likun Gao (1): drm/amdgpu: add psp support for raven2 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c| 7 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 52 ++- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 15 - drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c| 15 - drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 27 ++-- drivers/gpu/drm/amd/amdgpu/soc15.c | 75 ++ drivers/gpu/drm/amd/display/Kconfig| 6 ++ .../amd/display/dc/bios/command_table_helper2.c| 5 ++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 ++ .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 ++ .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 ++- drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 ++ drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 ++ drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 ++ drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 ++ drivers/gpu/drm/amd/display/include/dal_types.h| 3 + drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 16 - .../gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c| 3 +- 20 files changed, 261 insertions(+), 46 deletions(-) -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/ttm: once more fix ttm_bo_bulk_move_lru_tail
While cutting the lists we sometimes accidentally added a list_head from
the stack to the LRUs, effectively corrupting the list.
Remove the list cutting and use explicit list manipulation instead.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 51 ++--
1 file changed, 30 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 138c98902033..b2a33bf1ef10 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -247,23 +247,18 @@ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo,
}
EXPORT_SYMBOL(ttm_bo_move_to_lru_tail);
-static void ttm_bo_bulk_move_helper(struct ttm_lru_bulk_move_pos *pos,
- struct list_head *lru, bool is_swap)
+static void ttm_list_move_bulk_tail(struct list_head *list,
+ struct list_head *first,
+ struct list_head *last)
{
- struct list_head *list;
- LIST_HEAD(entries);
- LIST_HEAD(before);
+ first->prev->next = last->next;
+ last->next->prev = first->prev;
- reservation_object_assert_held(pos->last->resv);
- list = is_swap ? >last->swap : >last->lru;
- list_cut_position(, lru, list);
+ list->prev->next = first;
+ first->prev = list->prev;
- reservation_object_assert_held(pos->first->resv);
- list = is_swap ? pos->first->swap.prev : pos->first->lru.prev;
- list_cut_position(, , list);
-
- list_splice(, lru);
- list_splice_tail(, lru);
+ last->next = list;
+ list->prev = last;
}
void ttm_bo_bulk_move_lru_tail(struct ttm_lru_bulk_move *bulk)
@@ -271,23 +266,33 @@ void ttm_bo_bulk_move_lru_tail(struct ttm_lru_bulk_move
*bulk)
unsigned i;
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
+ struct ttm_lru_bulk_move_pos *pos = >tt[i];
struct ttm_mem_type_manager *man;
- if (!bulk->tt[i].first)
+ if (!pos->first)
continue;
- man = >tt[i].first->bdev->man[TTM_PL_TT];
- ttm_bo_bulk_move_helper(>tt[i], >lru[i], false);
+ reservation_object_assert_held(pos->first->resv);
+ reservation_object_assert_held(pos->last->resv);
+
+ man = >first->bdev->man[TTM_PL_TT];
+ ttm_list_move_bulk_tail(>lru[i], >first->lru,
+ >last->lru);
}
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
+ struct ttm_lru_bulk_move_pos *pos = >vram[i];
struct ttm_mem_type_manager *man;
- if (!bulk->vram[i].first)
+ if (!pos->first)
continue;
- man = >vram[i].first->bdev->man[TTM_PL_VRAM];
- ttm_bo_bulk_move_helper(>vram[i], >lru[i], false);
+ reservation_object_assert_held(pos->first->resv);
+ reservation_object_assert_held(pos->last->resv);
+
+ man = >first->bdev->man[TTM_PL_VRAM];
+ ttm_list_move_bulk_tail(>lru[i], >first->lru,
+ >last->lru);
}
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
@@ -297,8 +302,12 @@ void ttm_bo_bulk_move_lru_tail(struct ttm_lru_bulk_move
*bulk)
if (!pos->first)
continue;
+ reservation_object_assert_held(pos->first->resv);
+ reservation_object_assert_held(pos->last->resv);
+
lru = >first->bdev->glob->swap_lru[i];
- ttm_bo_bulk_move_helper(>swap[i], lru, true);
+ ttm_list_move_bulk_tail(lru, >first->swap,
+ >last->swap);
}
}
EXPORT_SYMBOL(ttm_bo_bulk_move_lru_tail);
--
2.14.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: use HMM mirror callback to replace mmu notifier
Yes, at least Jeromes original patch for amdgpu already did this.
Christian.
Am 12.09.2018 um 20:58 schrieb Felix Kuehling:
Should we add HMM as a dependency in the Kconfig? At least for KFD
functionality we depend on userptrs.
Regards,
Felix
On 2018-09-12 03:15 AM, Christian König wrote:
Am 11.09.2018 um 21:31 schrieb Philip Yang:
Replace our MMU notifier with hmm_mirror_ops.sync_cpu_device_pagetables
callback if kernel configured
HMM. Kenel configured without HMM still uses
our own MMU notifier.
Please drop that and always use the HMM path.
When a kernel doesn't support HMM we should not support userptr either.
Christian.
It supports both KFD userptr and gfx userptr paths.
This depends on several HMM patchset from Jérôme Glisse queued for
upstream. See
http://172.27.226.38/root/kernel_amd/commits/hmm-dev-v01 (for AMD
intranet)
Change-Id: Ie62c3c5e3c5b8521ab3b438d1eff2aa2a003835e
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 77
+
drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 41 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 49 -
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 6 +++
5 files changed, 173 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 138cb78..ee691e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -172,6 +172,7 @@ amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
+amdgpu-$(CONFIG_HMM) += amdgpu_hmm.o
include $(FULL_AMD_PATH)/powerplay/Makefile
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
new file mode 100644
index 000..a502c11
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person
obtaining a
+ * copy of this software and associated documentation files (the
"Software"),
+ * to deal in the Software without restriction, including without
limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom
the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "amdgpu.h"
+#include "amdgpu_mn.h"
+
+static void amdgpu_hmm_release(struct hmm_mirror *mirror)
+{
+ pr_debug("mirror=%p\n", mirror);
+}
+
+static int amdgpu_hmm_sync_cpu_device_pagetables(struct hmm_mirror
*mirror,
+ const struct hmm_update *update)
+{
+ struct hmm *hmm;
+ struct mm_struct *mm;
+ unsigned long start;
+ unsigned long end;
+
+ start = update->start;
+ end = update->end;
+
+ pr_debug("mirror %p start %lx end %lx\n", mirror, start, end);
+
+ hmm = mirror->hmm;
+ mm = *(struct mm_struct **)hmm;
+
+ return amdgpu_mn_invalidate_range(mirror, mm, start, end,
+ update->blockable);
+}
+
+static struct hmm_mirror_ops amdgpu_hmm_mirror_ops = {
+ .sync_cpu_device_pagetables =
amdgpu_hmm_sync_cpu_device_pagetables,
+ .release = amdgpu_hmm_release
+};
+
+int amdgpu_hmm_register(struct hmm_mirror *mirror, struct mm_struct
*mm)
+{
+ pr_debug("mirror=%p\n", mirror);
+
+ mirror->ops = _hmm_mirror_ops;
+
+ return hmm_mirror_register(mirror, mm);
+}
+
+void amdgpu_hmm_unregister(struct hmm_mirror *mirror)
+{
+ pr_debug("mirror=%p\n", mirror);
+
+ hmm_mirror_unregister(mirror);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
new file mode 100644
index 000..a21a5f6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person
obtaining a
+ * copy of this software and associated documentation files (the
Re: [PATCH] drm/amdgpu: use HMM mirror callback to replace mmu notifier
Should we add HMM as a dependency in the Kconfig? At least for KFD
functionality we depend on userptrs.
Regards,
Felix
On 2018-09-12 03:15 AM, Christian König wrote:
> Am 11.09.2018 um 21:31 schrieb Philip Yang:
>> Replace our MMU notifier with hmm_mirror_ops.sync_cpu_device_pagetables
>> callback if kernel configured
>
>> HMM. Kenel configured without HMM still uses
>> our own MMU notifier.
>
> Please drop that and always use the HMM path.
>
> When a kernel doesn't support HMM we should not support userptr either.
>
> Christian.
>
>>
>> It supports both KFD userptr and gfx userptr paths.
>>
>> This depends on several HMM patchset from Jérôme Glisse queued for
>> upstream. See
>> http://172.27.226.38/root/kernel_amd/commits/hmm-dev-v01 (for AMD
>> intranet)
>>
>> Change-Id: Ie62c3c5e3c5b8521ab3b438d1eff2aa2a003835e
>> Signed-off-by: Philip Yang
>> ---
>> drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 77
>> +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 41 ++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 49 -
>> drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 6 +++
>> 5 files changed, 173 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
>> b/drivers/gpu/drm/amd/amdgpu/Makefile
>> index 138cb78..ee691e8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
>> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
>> @@ -172,6 +172,7 @@ amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
>> amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
>> amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
>> amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
>> +amdgpu-$(CONFIG_HMM) += amdgpu_hmm.o
>> include $(FULL_AMD_PATH)/powerplay/Makefile
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
>> new file mode 100644
>> index 000..a502c11
>> --- /dev/null
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
>> @@ -0,0 +1,77 @@
>> +/*
>> + * Copyright 2018 Advanced Micro Devices, Inc.
>> + *
>> + * Permission is hereby granted, free of charge, to any person
>> obtaining a
>> + * copy of this software and associated documentation files (the
>> "Software"),
>> + * to deal in the Software without restriction, including without
>> limitation
>> + * the rights to use, copy, modify, merge, publish, distribute,
>> sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom
>> the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
>> EVENT SHALL
>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>> DAMAGES OR
>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>> OTHERWISE,
>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>> USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include "amdgpu.h"
>> +#include "amdgpu_mn.h"
>> +
>> +static void amdgpu_hmm_release(struct hmm_mirror *mirror)
>> +{
>> + pr_debug("mirror=%p\n", mirror);
>> +}
>> +
>> +static int amdgpu_hmm_sync_cpu_device_pagetables(struct hmm_mirror
>> *mirror,
>> + const struct hmm_update *update)
>> +{
>> + struct hmm *hmm;
>> + struct mm_struct *mm;
>> + unsigned long start;
>> + unsigned long end;
>> +
>> + start = update->start;
>> + end = update->end;
>> +
>> + pr_debug("mirror %p start %lx end %lx\n", mirror, start, end);
>> +
>> + hmm = mirror->hmm;
>> + mm = *(struct mm_struct **)hmm;
>> +
>> + return amdgpu_mn_invalidate_range(mirror, mm, start, end,
>> + update->blockable);
>> +}
>> +
>> +static struct hmm_mirror_ops amdgpu_hmm_mirror_ops = {
>> + .sync_cpu_device_pagetables =
>> amdgpu_hmm_sync_cpu_device_pagetables,
>> + .release = amdgpu_hmm_release
>> +};
>> +
>> +int amdgpu_hmm_register(struct hmm_mirror *mirror, struct mm_struct
>> *mm)
>> +{
>> + pr_debug("mirror=%p\n", mirror);
>> +
>> + mirror->ops = _hmm_mirror_ops;
>> +
>> + return hmm_mirror_register(mirror, mm);
>> +}
>> +
>> +void amdgpu_hmm_unregister(struct hmm_mirror *mirror)
>> +{
>> + pr_debug("mirror=%p\n", mirror);
>> +
>> + hmm_mirror_unregister(mirror);
>> +}
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
>> new file mode 100644
>> index
[PATCH 21/21] drm/amdgpu: use IP presence to free uvd and vce handles
Rather than checking the asic type, check whether the UVD
or VCE IP blocks exist. This way we don't have to update
the check with new asics that use VCN.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 489eea8dd53c..030b998a1b9f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -974,10 +974,10 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
pm_runtime_get_sync(dev->dev);
- if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) {
+ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
amdgpu_uvd_free_handles(adev, file_priv);
+ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
amdgpu_vce_free_handles(adev, file_priv);
- }
amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/21] drm/amdgpu: add picasso support for sdma_v4
From: Likun Gao
Add sdma support to picasso
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index ee0213edca8e..ca8a26178e2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -48,6 +48,7 @@ MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
+MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x00F8L
#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC00L
@@ -221,6 +222,7 @@ static void sdma_v4_0_init_golden_registers(struct
amdgpu_device *adev)
ARRAY_SIZE(golden_settings_sdma1_4_2));
break;
case CHIP_RAVEN:
+ case CHIP_PICASSO:
soc15_program_register_sequence(adev,
golden_settings_sdma_4_1,
ARRAY_SIZE(golden_settings_sdma_4_1));
@@ -269,6 +271,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device
*adev)
case CHIP_RAVEN:
chip_name = "raven";
break;
+ case CHIP_PICASSO:
+ chip_name = "picasso";
+ break;
default:
BUG();
}
@@ -849,6 +854,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_RAVEN:
+ case CHIP_PICASSO:
sdma_v4_1_init_power_gating(adev);
sdma_v4_1_update_power_gating(adev, true);
break;
@@ -1256,7 +1262,7 @@ static int sdma_v4_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (adev->asic_type == CHIP_RAVEN)
+ if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO)
adev->sdma.num_instances = 1;
else
adev->sdma.num_instances = 2;
@@ -1599,6 +1605,7 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
case CHIP_VEGA12:
case CHIP_VEGA20:
case CHIP_RAVEN:
+ case CHIP_PICASSO:
sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
sdma_v4_0_update_medium_grain_light_sleep(adev,
@@ -1617,6 +1624,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
switch (adev->asic_type) {
case CHIP_RAVEN:
+ case CHIP_PICASSO:
sdma_v4_1_update_power_gating(adev,
state == AMD_PG_STATE_GATE ? true : false);
break;
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 19/21] drm/amdgpu: add new raven series device
From: Huang Rui
This patch is to add new pci device for raven series.
Signed-off-by: Huang Rui
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index b5c2ccb585b4..b575728ead07 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -874,6 +874,8 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
/* Raven */
{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
+ /* Picasso */
+ {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PICASSO|AMD_IS_APU},
{0, 0, 0}
};
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 16/21] drm/amdgpu: enable mmhub power gating
From: Kenneth Feng
Remove some functions due to the design change.
All the mmhub power gating sequence is moved to
smu fw.Driver sends the message to enable mmhub
powergating.We can also skip the fw version check
since the old fw version is in a very early stage
and we don't use that fw for release.
Signed-off-by: Kenneth Feng
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 220
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 1 -
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
4 files changed, 1 insertion(+), 223 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 55b11afec16e..0ad1586c293f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1098,7 +1098,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device
*adev)
switch (adev->asic_type) {
case CHIP_RAVEN:
case CHIP_PICASSO:
- mmhub_v1_0_initialize_power_gating(adev);
mmhub_v1_0_update_power_gating(adev, true);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 1797304cb40b..b121eb6a0ad4 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -261,236 +261,16 @@ static void mmhub_v1_0_program_invalidation(struct
amdgpu_device *adev)
}
}
-struct pctl_data {
- uint32_t index;
- uint32_t data;
-};
-
-static const struct pctl_data pctl0_data[] = {
- {0x0, 0x7a640},
- {0x9, 0x2a64a},
- {0xd, 0x2a680},
- {0x11, 0x6a684},
- {0x19, 0xea68e},
- {0x29, 0xa69e},
- {0x2b, 0x0010a6c0},
- {0x3d, 0x83a707},
- {0xc2, 0x8a7a4},
- {0xcc, 0x1a7b8},
- {0xcf, 0xfa7cc},
- {0xe0, 0x17a7dd},
- {0xf9, 0xa7dc},
- {0xfb, 0x12a7f5},
- {0x10f, 0xa808},
- {0x111, 0x12a810},
- {0x125, 0x7a82c}
-};
-#define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data))
-
-#define PCTL0_RENG_EXEC_END_PTR 0x12d
-#define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640
-#define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
-
-static const struct pctl_data pctl1_data[] = {
- {0x0, 0x39a000},
- {0x3b, 0x44a040},
- {0x81, 0x2a08d},
- {0x85, 0x6ba094},
- {0xf2, 0x18a100},
- {0x10c, 0x4a132},
- {0x112, 0xca141},
- {0x120, 0x2fa158},
- {0x151, 0x17a1d0},
- {0x16a, 0x1a1e9},
- {0x16d, 0x13a1ec},
- {0x182, 0x7a201},
- {0x18b, 0x3a20a},
- {0x190, 0x7a580},
- {0x199, 0xa590},
- {0x19b, 0x4a594},
- {0x1a1, 0x1a59c},
- {0x1a4, 0x7a82c},
- {0x1ad, 0xfa7cc},
- {0x1be, 0x17a7dd},
- {0x1d7, 0x12a810},
- {0x1eb, 0x4000a7e1},
- {0x1ec, 0x5000a7f5},
- {0x1ed, 0x4000a7e2},
- {0x1ee, 0x5000a7dc},
- {0x1ef, 0x4000a7e3},
- {0x1f0, 0x5000a7f6},
- {0x1f1, 0x5000a7e4}
-};
-#define PCTL1_DATA_LEN (ARRAY_SIZE(pctl1_data))
-
-#define PCTL1_RENG_EXEC_END_PTR 0x1f1
-#define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000
-#define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d
-#define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE 0xa580
-#define PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT 0xa59d
-#define PCTL1_STCTRL_REG_SAVE_RANGE2_BASE 0xa82c
-#define PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT 0xa833
-
-static void mmhub_v1_0_power_gating_write_save_ranges(struct amdgpu_device
*adev)
-{
- uint32_t tmp = 0;
-
- /* PCTL0_STCTRL_REGISTER_SAVE_RANGE0 */
- tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
- STCTRL_REGISTER_SAVE_BASE,
- PCTL0_STCTRL_REG_SAVE_RANGE0_BASE);
- tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
- STCTRL_REGISTER_SAVE_LIMIT,
- PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT);
- WREG32_SOC15(MMHUB, 0, mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0, tmp);
-
- /* PCTL1_STCTRL_REGISTER_SAVE_RANGE0 */
- tmp = 0;
- tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
- STCTRL_REGISTER_SAVE_BASE,
- PCTL1_STCTRL_REG_SAVE_RANGE0_BASE);
- tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
- STCTRL_REGISTER_SAVE_LIMIT,
- PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT);
- WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0, tmp);
-
- /* PCTL1_STCTRL_REGISTER_SAVE_RANGE1 */
- tmp = 0;
- tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
- STCTRL_REGISTER_SAVE_BASE,
- PCTL1_STCTRL_REG_SAVE_RANGE1_BASE);
- tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
- STCTRL_REGISTER_SAVE_LIMIT,
-
[PATCH 20/21] drm/amdgpu: enable gfxoff in non-sriov and stutter mode by default
From: Kenneth Feng
enable gfxoff in non-sriov and stutter mode by default
Signed-off-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 25e7e1cccaa1..39fe66810d53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1492,6 +1492,8 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
}
adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
+ if (amdgpu_sriov_vf(adev))
+ adev->powerplay.pp_feature &= ~PP_GFXOFF_MASK;
for (i = 0; i < adev->num_ip_blocks; i++) {
if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index b575728ead07..33e1856fb8cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -114,8 +114,8 @@ uint amdgpu_pg_mask = 0x;
uint amdgpu_sdma_phase_quantum = 32;
char *amdgpu_disable_cu = NULL;
char *amdgpu_virtual_display = NULL;
-/* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/
-uint amdgpu_pp_feature_mask = 0xfffd3fff;
+/* OverDrive(bit 14) disabled by default*/
+uint amdgpu_pp_feature_mask = 0xbfff;
int amdgpu_ngg = 0;
int amdgpu_prim_buf_per_se = 0;
int amdgpu_pos_buf_per_se = 0;
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 18/21] drm/amdgpu: add ip blocks for picasso (v2)
From: Huang Rui Add PCO IPs. V2: enable VCN as well Signed-off-by: Huang Rui Signed-off-by: Likun Gao Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 7837f0cc75b2..e338ad6d0d20 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -556,6 +556,24 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _v4_0_ip_block); amdgpu_device_ip_block_add(adev, _v1_0_ip_block); break; + case CHIP_PICASSO: + amdgpu_device_ip_block_add(adev, _common_ip_block); + amdgpu_device_ip_block_add(adev, _v9_0_ip_block); + amdgpu_device_ip_block_add(adev, _ih_ip_block); + amdgpu_device_ip_block_add(adev, _v10_0_ip_block); + amdgpu_device_ip_block_add(adev, _smu_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) + amdgpu_device_ip_block_add(adev, _virtual_ip_block); +#if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) + amdgpu_device_ip_block_add(adev, _ip_block); +#else +# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." +#endif + amdgpu_device_ip_block_add(adev, _v9_0_ip_block); + amdgpu_device_ip_block_add(adev, _v4_0_ip_block); + amdgpu_device_ip_block_add(adev, _v1_0_ip_block); + break; default: return -EINVAL; } -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/21] drm/amdgpu: add picasso support for gfx_v9_0
From: Likun Gao
Add gfx support to picasso
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 +++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3594704a6f9b..ad20747bace8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -80,6 +80,13 @@ MODULE_FIRMWARE("amdgpu/raven_mec.bin");
MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
+MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
+MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
+MODULE_FIRMWARE("amdgpu/picasso_me.bin");
+MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
+MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
+MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
+
static const struct soc15_reg_golden golden_settings_gc_9_0[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00f, 0x0400),
@@ -240,6 +247,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
#define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x2442
+#define PICASSO_GB_ADDR_CONFIG_GOLDEN 0x2442
static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -279,6 +287,7 @@ static void gfx_v9_0_init_golden_registers(struct
amdgpu_device *adev)
ARRAY_SIZE(golden_settings_gc_9_0_vg20));
break;
case CHIP_RAVEN:
+ case CHIP_PICASSO:
soc15_program_register_sequence(adev,
golden_settings_gc_9_1,
ARRAY_SIZE(golden_settings_gc_9_1));
@@ -566,6 +575,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device
*adev)
case CHIP_RAVEN:
chip_name = "raven";
break;
+ case CHIP_PICASSO:
+ chip_name = "picasso";
+ break;
default:
BUG();
}
@@ -1019,7 +1031,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
}
- if (adev->asic_type == CHIP_RAVEN) {
+ if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) {
/* TODO: double check the cp_table_size for RV */
adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 *
1024); /* JT + GDS */
r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
@@ -1268,6 +1280,14 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device
*adev)
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
break;
+ case CHIP_PICASSO:
+ adev->gfx.config.max_hw_contexts = 8;
+ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+ gb_addr_config = PICASSO_GB_ADDR_CONFIG_GOLDEN;
+ break;
default:
BUG();
break;
@@ -1546,6 +1566,7 @@ static int gfx_v9_0_sw_init(void *handle)
case CHIP_VEGA12:
case CHIP_VEGA20:
case CHIP_RAVEN:
+ case CHIP_PICASSO:
adev->gfx.mec.num_mec = 2;
break;
default:
@@ -1707,7 +1728,7 @@ static int gfx_v9_0_sw_fini(void *handle)
amdgpu_bo_free_kernel(>gfx.rlc.clear_state_obj,
>gfx.rlc.clear_state_gpu_addr,
(void **)>gfx.rlc.cs_ptr);
- if (adev->asic_type == CHIP_RAVEN) {
+ if ((adev->asic_type == CHIP_RAVEN) || (adev->asic_type ==
CHIP_PICASSO)) {
amdgpu_bo_free_kernel(>gfx.rlc.cp_table_obj,
>gfx.rlc.cp_table_gpu_addr,
(void **)>gfx.rlc.cp_table_ptr);
@@ -2373,7 +2394,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
return r;
}
- if (adev->asic_type == CHIP_RAVEN) {
+ if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) {
if (amdgpu_lbpw != 0)
gfx_v9_0_enable_lbpw(adev, true);
else
@@ -3777,6 +3798,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
switch (adev->asic_type) {
case CHIP_RAVEN:
+ case CHIP_PICASSO:
if (!enable) {
amdgpu_gfx_off_ctrl(adev, false);
[PATCH 14/21] drm/amdgpu: Add pg support for gfxoff for PCO
From: Kenneth Feng Add pg support for gfxoff. Signed-off-by: Kenneth Feng Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index d3b73afcb871..2539fa7b9594 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -740,7 +740,10 @@ static int soc15_common_early_init(void *handle) AMD_CG_SUPPORT_SDMA_MGCG | AMD_CG_SUPPORT_SDMA_LS; - adev->pg_flags = 0; + if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) + adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | + AMD_PG_SUPPORT_CP | + AMD_PG_SUPPORT_RLC_SMU_HS; adev->external_rev_id = adev->rev_id + 0x41; break; -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/21] drm/amdgpu: add picasso for amdgpu kms
From: Likun Gao
Add picasso for amdgpu kms
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 29ac3873eeb0..489eea8dd53c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -974,7 +974,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
pm_runtime_get_sync(dev->dev);
- if (adev->asic_type != CHIP_RAVEN) {
+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) {
amdgpu_uvd_free_handles(adev, file_priv);
amdgpu_vce_free_handles(adev, file_priv);
}
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 15/21] drm/amdgpu: Enable SDMA power gating for PCO
From: Kenneth Feng Enable SDMA power gating Signed-off-by: Kenneth Feng Acked-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 2539fa7b9594..b205a4a5c3d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -740,6 +740,8 @@ static int soc15_common_early_init(void *handle) AMD_CG_SUPPORT_SDMA_MGCG | AMD_CG_SUPPORT_SDMA_LS; + adev->pg_flags = AMD_PG_SUPPORT_SDMA; + if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_CP | -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 17/21] drm/amdgpu: enable vcn powergating for PCO
From: Kenneth Feng enable vcn pg Signed-off-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 53159f1d7a39..7837f0cc75b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -740,7 +740,9 @@ static int soc15_common_early_init(void *handle) AMD_CG_SUPPORT_SDMA_MGCG | AMD_CG_SUPPORT_SDMA_LS; - adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_MMHUB; + adev->pg_flags = AMD_PG_SUPPORT_SDMA | + AMD_PG_SUPPORT_MMHUB | + AMD_PG_SUPPORT_VCN; if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 06/21] drm/amdgpu: initilize picasso psp firmwares support
From: Likun Gao
Same as raven for now.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index bd397d2916fb..611c06d3600a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -56,6 +56,7 @@ static int psp_sw_init(void *handle)
psp_v3_1_set_psp_funcs(psp);
break;
case CHIP_RAVEN:
+ case CHIP_PICASSO:
psp_v10_0_set_psp_funcs(psp);
break;
case CHIP_VEGA20:
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 02be34e72ed9..73a1ca833292 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -35,6 +35,7 @@
#include "sdma0/sdma0_4_1_offset.h"
MODULE_FIRMWARE("amdgpu/raven_asd.bin");
+MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
static int
psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type
*type)
@@ -113,6 +114,9 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
case CHIP_RAVEN:
chip_name = "raven";
break;
+ case CHIP_PICASSO:
+ chip_name = "picasso";
+ break;
default: BUG();
}
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 10/21] drm/amdgpu: add picasso support for gmc
From: Likun Gao
Same as raven.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index b1c848937e42..55b11afec16e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -846,6 +846,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
adev->gmc.gart_size = 512ULL << 20;
break;
case CHIP_RAVEN: /* DCE SG support */
+ case CHIP_PICASSO: /* DCE SG support */
adev->gmc.gart_size = 1024ULL << 20;
break;
}
@@ -934,6 +935,7 @@ static int gmc_v9_0_sw_init(void *handle)
adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
switch (adev->asic_type) {
case CHIP_RAVEN:
+ case CHIP_PICASSO:
if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
} else {
@@ -1060,6 +1062,7 @@ static void gmc_v9_0_init_golden_registers(struct
amdgpu_device *adev)
case CHIP_VEGA12:
break;
case CHIP_RAVEN:
+ case CHIP_PICASSO:
soc15_program_register_sequence(adev,
golden_settings_athub_1_0_0,
ARRAY_SIZE(golden_settings_athub_1_0_0));
@@ -1094,6 +1097,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device
*adev)
switch (adev->asic_type) {
case CHIP_RAVEN:
+ case CHIP_PICASSO:
mmhub_v1_0_initialize_power_gating(adev);
mmhub_v1_0_update_power_gating(adev, true);
break;
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 03/21] drm/amdgpu: add picasso support for vm
From: Likun Gao
Add vm support for picasso.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index be1659fedf94..cea7991dd471 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2776,7 +2776,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
AMDGPU_VM_USE_CPU_FOR_COMPUTE);
- if (adev->asic_type == CHIP_RAVEN)
+ if (adev->asic_type == CHIP_RAVEN || adev->asic_type ==
CHIP_PICASSO)
vm->pte_support_ats = true;
} else {
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
@@ -2868,7 +2868,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
*/
int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
unsigned int pasid)
{
- bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
+ bool pte_support_ats = (adev->asic_type == CHIP_RAVEN ||
adev->asic_type == CHIP_PICASSO);
int r;
r = amdgpu_bo_reserve(vm->root.base.bo, true);
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/21] drm/amdgpu: add picasso support for vcn
From: Likun Gao Add vcn support for picasso. Signed-off-by: Likun Gao Reviewed-by: Alex Deucher Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 76e59a6e8311..93ffba2cbec4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -42,8 +42,10 @@ /* Firmware Names */ #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" +#define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" MODULE_FIRMWARE(FIRMWARE_RAVEN); +MODULE_FIRMWARE(FIRMWARE_PICASSO); static void amdgpu_vcn_idle_work_handler(struct work_struct *work); @@ -61,6 +63,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) case CHIP_RAVEN: fw_name = FIRMWARE_RAVEN; break; + case CHIP_PICASSO: + fw_name = FIRMWARE_PICASSO; + break; default: return -EINVAL; } -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/21] drm/amd/display/dm: add picasso support
From: Likun Gao
Add support for picasso to the display manager.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 82c2e8260571..25e7e1cccaa1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2177,6 +2177,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type
asic_type)
case CHIP_VEGA20:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
+ case CHIP_PICASSO:
#endif
return amdgpu_dc != 0;
#endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5103eba75cb3..e74a9258c03d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1124,7 +1124,8 @@ static int dce110_register_irq_handlers(struct
amdgpu_device *adev)
if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 ||
adev->asic_type == CHIP_VEGA20 ||
- adev->asic_type == CHIP_RAVEN)
+ adev->asic_type == CHIP_RAVEN ||
+ adev->asic_type == CHIP_PICASSO)
client_id = SOC15_IH_CLIENTID_DCE;
int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -1543,6 +1544,7 @@ static int amdgpu_dm_initialize_drm_device(struct
amdgpu_device *adev)
break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
+ case CHIP_PICASSO:
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail;
@@ -1773,6 +1775,7 @@ static int dm_early_init(void *handle)
break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
+ case CHIP_PICASSO:
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4;
@@ -2021,7 +2024,8 @@ static int fill_plane_attributes_from_fb(struct
amdgpu_device *adev,
if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 ||
adev->asic_type == CHIP_VEGA20 ||
- adev->asic_type == CHIP_RAVEN) {
+ adev->asic_type == CHIP_RAVEN ||
+ adev->asic_type == CHIP_PICASSO) {
/* Fill GFX9 params */
plane_state->tiling_info.gfx9.num_pipes =
adev->gfx.config.gb_addr_config_fields.num_pipes;
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/21] Add Picasso support
This patch set adds support for Picasso. Picasso is a new APU similar to raven. Alex Deucher (1): drm/amdgpu: use IP presence to free uvd and vce handles Huang Rui (2): drm/amdgpu: add ip blocks for picasso (v2) drm/amdgpu: add new raven series device Kenneth Feng (5): drm/amdgpu: Add pg support for gfxoff for PCO drm/amdgpu: Enable SDMA power gating for PCO drm/amdgpu: enable mmhub power gating drm/amdgpu: enable vcn powergating for PCO drm/amdgpu: enable gfxoff in non-sriov and stutter mode by default Likun Gao (13): drm/amdgpu: add picasso to asic_type enum drm/amdgpu: add soc15 support for picasso drm/amdgpu: add picasso support for vm drm/amd/display/dm: add picasso support drm/amdgpu: Add support of powerplay for picasso drm/amdgpu: initilize picasso psp firmwares support drm/amdgpu: add picasso ucode loading method drm/amdgpu: add picasso support for vcn drm/amdgpu: add clockgating support for picasso drm/amdgpu: add picasso support for gmc drm/amdgpu: add picasso support for gfx_v9_0 drm/amdgpu: add picasso support for sdma_v4 drm/amdgpu: add picasso for amdgpu kms drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c| 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 ++- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c| 231 + drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h| 1 - drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 4 + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 46 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 1 + .../gpu/drm/amd/powerplay/hwmgr/processpptables.c | 8 +- include/drm/amd_asic_type.h| 1 + 18 files changed, 133 insertions(+), 244 deletions(-) -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 01/21] drm/amdgpu: add picasso to asic_type enum
From: Likun Gao
Add picasso to amd_asic_type enum and amdgpu_asic_name[].
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
include/drm/amd_asic_type.h| 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d4855d1ef51f..e8083ec3fbc2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -89,6 +89,7 @@ static const char *amdgpu_asic_name[] = {
"VEGA12",
"VEGA20",
"RAVEN",
+ "PICASSO",
"LAST",
};
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
index dd63d08cc54e..5644fc679d6f 100644
--- a/include/drm/amd_asic_type.h
+++ b/include/drm/amd_asic_type.h
@@ -49,6 +49,7 @@ enum amd_asic_type {
CHIP_VEGA12,
CHIP_VEGA20,
CHIP_RAVEN,
+ CHIP_PICASSO,
CHIP_LAST,
};
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/21] drm/amdgpu: add clockgating support for picasso
From: Likun Gao
Treat it the same as raven for now.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 0e09549d1db8..1797304cb40b 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -621,7 +621,7 @@ static void
mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
- if (adev->asic_type != CHIP_RAVEN) {
+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) {
def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
} else
@@ -637,7 +637,7 @@ static void
mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
- if (adev->asic_type != CHIP_RAVEN)
+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type !=
CHIP_PICASSO)
data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
@@ -654,7 +654,7 @@ static void
mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
- if (adev->asic_type != CHIP_RAVEN)
+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type !=
CHIP_PICASSO)
data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
@@ -667,13 +667,13 @@ static void
mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
if (def1 != data1) {
- if (adev->asic_type != CHIP_RAVEN)
+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type !=
CHIP_PICASSO)
WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
else
WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
}
- if (adev->asic_type != CHIP_RAVEN && def2 != data2)
+ if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO &&
def2 != data2)
WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
}
@@ -737,6 +737,7 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
case CHIP_VEGA12:
case CHIP_VEGA20:
case CHIP_RAVEN:
+ case CHIP_PICASSO:
mmhub_v1_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
athub_update_medium_grain_clock_gating(adev,
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 02/21] drm/amdgpu: add soc15 support for picasso
From: Likun Gao
Add the IP blocks, clock and powergating flags, and common clockgating support.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/soc15.c | 21 +
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e8083ec3fbc2..82c2e8260571 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -62,6 +62,7 @@
MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
#define AMDGPU_RESUME_MS 2000
@@ -1335,6 +1336,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
case CHIP_RAVEN:
chip_name = "raven";
break;
+ case CHIP_PICASSO:
+ chip_name = "picasso";
+ break;
}
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
@@ -1460,7 +1464,8 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
case CHIP_VEGA12:
case CHIP_VEGA20:
case CHIP_RAVEN:
- if (adev->asic_type == CHIP_RAVEN)
+ case CHIP_PICASSO:
+ if ((adev->asic_type == CHIP_RAVEN) || (adev->asic_type ==
CHIP_PICASSO))
adev->family = AMDGPU_FAMILY_RV;
else
adev->family = AMDGPU_FAMILY_AI;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index fc0cb7d38c9f..d3b73afcb871 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -486,6 +486,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_RAVEN:
+ case CHIP_PICASSO:
vega10_reg_base_init(adev);
break;
case CHIP_VEGA20:
@@ -724,6 +725,25 @@ static int soc15_common_early_init(void *handle)
adev->external_rev_id = 0x1;
break;
+ case CHIP_PICASSO:
+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
+ AMD_CG_SUPPORT_GFX_CP_LS |
+ AMD_CG_SUPPORT_GFX_3D_CGCG |
+ AMD_CG_SUPPORT_GFX_3D_CGLS |
+ AMD_CG_SUPPORT_GFX_CGCG |
+ AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_BIF_LS |
+ AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_ROM_MGCG |
+ AMD_CG_SUPPORT_MC_MGCG |
+ AMD_CG_SUPPORT_MC_LS |
+ AMD_CG_SUPPORT_SDMA_MGCG |
+ AMD_CG_SUPPORT_SDMA_LS;
+
+ adev->pg_flags = 0;
+
+ adev->external_rev_id = adev->rev_id + 0x41;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
@@ -924,6 +944,7 @@ static int soc15_common_set_clockgating_state(void *handle,
state == AMD_CG_STATE_GATE ? true : false);
break;
case CHIP_RAVEN:
+ case CHIP_PICASSO:
adev->nbio_funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
adev->nbio_funcs->update_medium_grain_light_sleep(adev,
--
2.13.6
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/21] drm/amdgpu: add picasso ucode loading method
From: Likun Gao Same as raven. Signed-off-by: Likun Gao Reviewed-by: Alex Deucher Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index a942fd28dae8..8a9b6258c2e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -303,6 +303,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) return AMDGPU_FW_LOAD_SMU; case CHIP_VEGA10: case CHIP_RAVEN: + case CHIP_PICASSO: case CHIP_VEGA12: case CHIP_VEGA20: if (!load_type) -- 2.13.6 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Add braces to initialize task_info subojects
On Wed, Sep 12, 2018 at 2:40 PM Nathan Chancellor
wrote:
>
> On Wed, Sep 12, 2018 at 10:38:30AM -0700, Nick Desaulniers wrote:
> > On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
> > wrote:
> > >
> > > Clang warns if there are missing braces around a subobject
> > > initializer.
> > >
> > > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
> > > around initialization of subobject [-Wmissing-braces]
> > > struct amdgpu_task_info task_info = { 0 };
> > > ^
> > > {}
> > > 1 warning generated.
> > >
> > > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:262:41: warning: suggest braces
> > > around initialization of subobject [-Wmissing-braces]
> > > struct amdgpu_task_info task_info = { 0 };
> > > ^
> > > {}
> > > 1 warning generated.
> > >
> > > Reported-by: Nick Desaulniers
> > > Signed-off-by: Nathan Chancellor
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
> > > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
> > > 2 files changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > index 9333109b210d..968cc1b8cdff 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > > @@ -1444,7 +1444,7 @@ static int gmc_v8_0_process_interrupt(struct
> > > amdgpu_device *adev,
> > > gmc_v8_0_set_fault_enable_default(adev, false);
> > >
> > > if (printk_ratelimit()) {
> > > - struct amdgpu_task_info task_info = { 0 };
> > > + struct amdgpu_task_info task_info = { { 0 } };
> >
> > Hi Nathan,
> > Thanks for this patch. I discussed this syntax with our language
> > lawyers. Turns out, this is not quite correct, as you're now saying
> > "initialize the first subobject to zero, but not the rest of the
> > object." -Wmissing-field-initializers would highlight this, but it's
> > not part of -Wall. It would be more correct to zero initialize the
> > full struct, including all of its subobjects with `= {};`.
> >
>
> Good point, I was debating on which one was correct. There are several
> places in this driver that use the multiple brace + 0 idiom, which is
> why I used this form. I will spin up a v2 with your suggestion, thank
> you for the review!
Feel free to fix up the others as well. The others were only changed
due to the same warning you sent the patch for.
Alex
>
> Nathan
>
> > >
> > > amdgpu_vm_get_task_info(adev, entry->pasid, _info);
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > index 72f8018fa2a8..a781a5027212 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > > @@ -259,7 +259,7 @@ static int gmc_v9_0_process_interrupt(struct
> > > amdgpu_device *adev,
> > > }
> > >
> > > if (printk_ratelimit()) {
> > > - struct amdgpu_task_info task_info = { 0 };
> > > + struct amdgpu_task_info task_info = { { 0 } };
> > >
> > > amdgpu_vm_get_task_info(adev, entry->pasid, _info);
> > >
> > > --
> > > 2.18.0
> > >
> >
> >
> > --
> > Thanks,
> > ~Nick Desaulniers
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Add braces to initialize task_info subojects
On Wed, Sep 12, 2018 at 10:38:30AM -0700, Nick Desaulniers wrote:
> On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
> wrote:
> >
> > Clang warns if there are missing braces around a subobject
> > initializer.
> >
> > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
> > around initialization of subobject [-Wmissing-braces]
> > struct amdgpu_task_info task_info = { 0 };
> > ^
> > {}
> > 1 warning generated.
> >
> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:262:41: warning: suggest braces
> > around initialization of subobject [-Wmissing-braces]
> > struct amdgpu_task_info task_info = { 0 };
> > ^
> > {}
> > 1 warning generated.
> >
> > Reported-by: Nick Desaulniers
> > Signed-off-by: Nathan Chancellor
> > ---
> > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
> > 2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > index 9333109b210d..968cc1b8cdff 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > @@ -1444,7 +1444,7 @@ static int gmc_v8_0_process_interrupt(struct
> > amdgpu_device *adev,
> > gmc_v8_0_set_fault_enable_default(adev, false);
> >
> > if (printk_ratelimit()) {
> > - struct amdgpu_task_info task_info = { 0 };
> > + struct amdgpu_task_info task_info = { { 0 } };
>
> Hi Nathan,
> Thanks for this patch. I discussed this syntax with our language
> lawyers. Turns out, this is not quite correct, as you're now saying
> "initialize the first subobject to zero, but not the rest of the
> object." -Wmissing-field-initializers would highlight this, but it's
> not part of -Wall. It would be more correct to zero initialize the
> full struct, including all of its subobjects with `= {};`.
>
Good point, I was debating on which one was correct. There are several
places in this driver that use the multiple brace + 0 idiom, which is
why I used this form. I will spin up a v2 with your suggestion, thank
you for the review!
Nathan
> >
> > amdgpu_vm_get_task_info(adev, entry->pasid, _info);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > index 72f8018fa2a8..a781a5027212 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > @@ -259,7 +259,7 @@ static int gmc_v9_0_process_interrupt(struct
> > amdgpu_device *adev,
> > }
> >
> > if (printk_ratelimit()) {
> > - struct amdgpu_task_info task_info = { 0 };
> > + struct amdgpu_task_info task_info = { { 0 } };
> >
> > amdgpu_vm_get_task_info(adev, entry->pasid, _info);
> >
> > --
> > 2.18.0
> >
>
>
> --
> Thanks,
> ~Nick Desaulniers
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Add braces to initialize task_info subojects
On Tue, Sep 11, 2018 at 5:26 PM Nathan Chancellor
wrote:
>
> Clang warns if there are missing braces around a subobject
> initializer.
>
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:1447:41: warning: suggest braces
> around initialization of subobject [-Wmissing-braces]
> struct amdgpu_task_info task_info = { 0 };
> ^
> {}
> 1 warning generated.
>
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:262:41: warning: suggest braces
> around initialization of subobject [-Wmissing-braces]
> struct amdgpu_task_info task_info = { 0 };
> ^
> {}
> 1 warning generated.
>
> Reported-by: Nick Desaulniers
> Signed-off-by: Nathan Chancellor
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 9333109b210d..968cc1b8cdff 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1444,7 +1444,7 @@ static int gmc_v8_0_process_interrupt(struct
> amdgpu_device *adev,
> gmc_v8_0_set_fault_enable_default(adev, false);
>
> if (printk_ratelimit()) {
> - struct amdgpu_task_info task_info = { 0 };
> + struct amdgpu_task_info task_info = { { 0 } };
Hi Nathan,
Thanks for this patch. I discussed this syntax with our language
lawyers. Turns out, this is not quite correct, as you're now saying
"initialize the first subobject to zero, but not the rest of the
object." -Wmissing-field-initializers would highlight this, but it's
not part of -Wall. It would be more correct to zero initialize the
full struct, including all of its subobjects with `= {};`.
>
> amdgpu_vm_get_task_info(adev, entry->pasid, _info);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 72f8018fa2a8..a781a5027212 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -259,7 +259,7 @@ static int gmc_v9_0_process_interrupt(struct
> amdgpu_device *adev,
> }
>
> if (printk_ratelimit()) {
> - struct amdgpu_task_info task_info = { 0 };
> + struct amdgpu_task_info task_info = { { 0 } };
>
> amdgpu_vm_get_task_info(adev, entry->pasid, _info);
>
> --
> 2.18.0
>
--
Thanks,
~Nick Desaulniers
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2 05/17] compat_ioctl: move more drivers to generic_compat_ioctl_ptrarg
On Wed, Sep 12, 2018 at 05:08:52PM +0200, Arnd Bergmann wrote: > The .ioctl and .compat_ioctl file operations have the same prototype so > they can both point to the same function, which works great almost all > the time when all the commands are compatible. > > One exception is the s390 architecture, where a compat pointer is only > 31 bit wide, and converting it into a 64-bit pointer requires calling > compat_ptr(). Most drivers here will ever run in s390, but since we now > have a generic helper for it, it's easy enough to use it consistently. > > I double-checked all these drivers to ensure that all ioctl arguments > are used as pointers or are ignored, but are not interpreted as integer > values. > > Signed-off-by: Arnd Bergmann Acked-by: Greg Kroah-Hartman ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH xf86-video-amdgpu 0/6] xf86-video-amdgpu integration for DRM variable refresh rate API
On 09/12/2018 12:22 PM, Michel Dänzer wrote: On 2018-09-12 2:48 p.m., Kazlauskas, Nicholas wrote: On 09/12/2018 04:13 AM, Michel Dänzer wrote: On 2018-09-11 6:18 p.m., Nicholas Kazlauskas wrote: These patches are part of a proposed new interface for supporting variable refresh rate via DRM properties. https://patchwork.freedesktop.org/series/49486/ When notified of a window that is FreeSync capable via X these patches help track when the window is fullscreen to manage the variable_refresh property on the CRTC. I'm afraid the Xorg driver support will have to be more or less redone from scratch for upstreaming: Whether or not a client wants variable refresh rate enabled can be tracked via the window property mechanism supported by the core X11 protocol, no need for a protocol extension. That should also allow simpler tracking of when variable refresh rate can actually be enabled: It can be enabled while a window is flipping, and its corresponding property allows it. This should be straightforward with the Present extension, because that also explicitly marks the end of a window flipping (via an "unflip"). DRI2 is trickier; it's probably okay not to support variable refresh rate with that, at least initially. I can look into this after the upcoming Xorg driver 18.1 releases. Or I can give guidance if one of you wants to look into it. I can a look into this. I agree that the extension method is less than ideal - in being vendor specific mostly. It does have the nice property that it remains independent of the application's render backend, though. Not sure what you mean by that. Surely a window property is just as independent. :) I was mostly referring to being independent from the backend specific code in the DDX driver - DRI2/DRI3/present etc. This change turns the notification from being a callback into polling. I imagine you're suggesting specifying a window property hint like _NET_WM_BYPASS_COMPOSITOR - maybe a define new one like _NET_WM_VARIABLE_REFRESH (even though the two are closely related in terms of fullscreen behavior). Then in each backend the property could probably be checked before the present as appropriate. Right. (Not sure the _NET_WM prefix is appropriate, as it's nothing to do with the window manager, but that's a detail) I guess an application could operate independently from the window manager with variable refresh enabled but it's not certainly a common use case. I suppose this would probably need additional documentation patches for the extended window manager standards. _NET_VARIABLE_REFRESH is probably fine as a name. This patch series already has the problem you're describing about DRI2 where there's not a nice explicit end notification for flipping - it's only disabled when the window no longer covers the CRTC or the window is destroyed (which is the case for most applications but likely not all). Right. I think it's better to just not bother with DRI2, at least until there's a specific scenario where variable refresh is really needed with DRI2. Nicholas Kazlauskas ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH xf86-video-amdgpu 0/6] xf86-video-amdgpu integration for DRM variable refresh rate API
On 2018-09-12 2:48 p.m., Kazlauskas, Nicholas wrote: > On 09/12/2018 04:13 AM, Michel Dänzer wrote: >> On 2018-09-11 6:18 p.m., Nicholas Kazlauskas wrote: >>> These patches are part of a proposed new interface for supporting >>> variable refresh rate via DRM properties. >>> >>> https://patchwork.freedesktop.org/series/49486/ >>> >>> When notified of a window that is FreeSync capable via X these >>> patches help track when the window is fullscreen to manage the >>> variable_refresh property on the CRTC. >> >> I'm afraid the Xorg driver support will have to be more or less redone >> from scratch for upstreaming: >> >> Whether or not a client wants variable refresh rate enabled can be >> tracked via the window property mechanism supported by the core X11 >> protocol, no need for a protocol extension. >> >> That should also allow simpler tracking of when variable refresh rate >> can actually be enabled: It can be enabled while a window is flipping, >> and its corresponding property allows it. This should be straightforward >> with the Present extension, because that also explicitly marks the end >> of a window flipping (via an "unflip"). DRI2 is trickier; it's probably >> okay not to support variable refresh rate with that, at least initially. >> >> >> I can look into this after the upcoming Xorg driver 18.1 releases. Or I >> can give guidance if one of you wants to look into it. > > I can a look into this. I agree that the extension method is less than > ideal - in being vendor specific mostly. It does have the nice property > that it remains independent of the application's render backend, though. Not sure what you mean by that. Surely a window property is just as independent. :) > I imagine you're suggesting specifying a window property hint like > _NET_WM_BYPASS_COMPOSITOR - maybe a define new one like > _NET_WM_VARIABLE_REFRESH (even though the two are closely related in > terms of fullscreen behavior). Then in each backend the property could > probably be checked before the present as appropriate. Right. (Not sure the _NET_WM prefix is appropriate, as it's nothing to do with the window manager, but that's a detail) > This patch series already has the problem you're describing about DRI2 > where there's not a nice explicit end notification for flipping - it's > only disabled when the window no longer covers the CRTC or the window is > destroyed (which is the case for most applications but likely not all). Right. I think it's better to just not bother with DRI2, at least until there's a specific scenario where variable refresh is really needed with DRI2. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Initialize fences array entries in amdgpu_sa_bo_next_hole
Am 12.09.2018 um 18:10 schrieb Michel Dänzer: From: Michel Dänzer The entries were only initialized once in amdgpu_sa_bo_new. If a fence wasn't signalled yet in the first amdgpu_sa_bo_next_hole call, but then got signalled before a later amdgpu_sa_bo_next_hole call, it could destroy the fence but leave its pointer in the array, resulting in use-after-free in amdgpu_sa_bo_new. Signed-off-by: Michel Dänzer Good catch, patch is Reviewed-by: Christian König . --- I think this should fix an issue hit by today's piglit run: Sep 12 13:31:41 kaveri kernel: [ 2776.375043] refcount_t: increment on 0; use-after-free. Sep 12 13:31:41 kaveri kernel: [ 2776.375076] WARNING: CPU: 14 PID: 14012 at lib/refcount.c:153 refcount_inc_checked+0x26/0x30 Sep 12 13:31:41 kaveri kernel: [ 2776.375079] Modules linked in: fuse(E) lz4(E) lz4_compress(E) cpufreq_powersave(E) cpufreq_userspace(E) cpufreq_conservative(E) amdgpu(OE) chash(OE) gpu_sched(OE) binfmt_misc(E) nls_ascii(E) nls_cp437(E) vfat(E) fat(E) edac_mce_amd(E) radeon(OE) kvm(E) irqbypass(E) ttm(OE) crct10dif_pclmul(E) crc32_pclmul(E) snd_hda_codec_realtek(E) ghash_clmulni_intel(E) wmi_bmof(E) pcbc(E) snd_hda_codec_generic(E) snd_hda_codec_hdmi(E) drm_kms_helper(OE) aesni_intel(E) snd_hda_intel(E) aes_x86_64(E) snd_hda_codec(E) crypto_simd(E) r8169(E) snd_hda_core(E) cryptd(E) efi_pstore(E) drm(OE) glue_helper(E) sg(E) snd_hwdep(E) libphy(E) i2c_algo_bit(E) snd_pcm(E) fb_sys_fops(E) syscopyarea(E) sysfillrect(E) snd_timer(E) sysimgblt(E) efivars(E) pcspkr(E) snd(E) ccp(E) soundcore(E) sp5100_tco(E) rng_core(E) i2c_piix4(E) Sep 12 13:31:41 kaveri kernel: [ 2776.375237] k10temp(E) wmi(E) button(E) pcc_cpufreq(E) acpi_cpufreq(E) tcp_bbr(E) sch_fq(E) sunrpc(E) nct6775(E) hwmon_vid(E) efivarfs(E) ip_tables(E) x_tables(E) autofs4(E) ext4(E) crc32c_generic(E) crc16(E) mbcache(E) jbd2(E) fscrypto(E) dm_mod(E) raid10(E) raid1(E) raid0(E) multipath(E) linear(E) md_mod(E) sd_mod(E) evdev(E) hid_generic(E) usbhid(E) hid(E) ahci(E) libahci(E) libata(E) xhci_pci(E) xhci_hcd(E) crc32c_intel(E) usbcore(E) scsi_mod(E) gpio_amdpt(E) gpio_generic(E) Sep 12 13:31:41 kaveri kernel: [ 2776.375355] CPU: 14 PID: 14012 Comm: arb_shader:cs0 Tainted: G OE 4.19.0-rc1+ #112 Sep 12 13:31:41 kaveri kernel: [ 2776.375359] Hardware name: Micro-Star International Co., Ltd. MS-7A34/B350 TOMAHAWK (MS-7A34), BIOS 1.80 09/13/2017 Sep 12 13:31:41 kaveri kernel: [ 2776.375364] RIP: 0010:refcount_inc_checked+0x26/0x30 Sep 12 13:31:41 kaveri kernel: [ 2776.375369] Code: 00 00 00 00 e8 ab fe ff ff 84 c0 74 01 c3 80 3d f3 35 b3 01 00 75 f6 48 c7 c7 a0 c5 fe 9f c6 05 e3 35 b3 01 01 e8 85 7f 58 ff <0f> 0b c3 0f 1f 80 00 00 00 00 41 56 41 55 41 54 41 89 fc 55 48 bd Sep 12 13:31:41 kaveri kernel: [ 2776.375372] RSP: 0018:8803de50f070 EFLAGS: 00010286 Sep 12 13:31:41 kaveri kernel: [ 2776.375379] RAX: RBX: 8803de50f278 RCX: 9e65c7f0 Sep 12 13:31:41 kaveri kernel: [ 2776.375383] RDX: RSI: 0008 RDI: 8803ee19e9c0 Sep 12 13:31:41 kaveri kernel: [ 2776.375386] RBP: 88020c8453e0 R08: ed007dc33d39 R09: ed007dc33d38 Sep 12 13:31:41 kaveri kernel: [ 2776.375390] R10: ed007dc33d38 R11: 8803ee19e9c7 R12: 0003 Sep 12 13:31:41 kaveri kernel: [ 2776.375393] R13: dc00 R14: 0002 R15: 8803de50f330 Sep 12 13:31:41 kaveri kernel: [ 2776.375397] FS: 7f2901924700() GS:8803ee18() knlGS: Sep 12 13:31:41 kaveri kernel: [ 2776.375401] CS: 0010 DS: ES: CR0: 80050033 Sep 12 13:31:41 kaveri kernel: [ 2776.375404] CR2: 55b1f3c5e000 CR3: 0003e5ca CR4: 003406e0 Sep 12 13:31:41 kaveri kernel: [ 2776.375407] Call Trace: Sep 12 13:31:41 kaveri kernel: [ 2776.375494] amdgpu_sa_bo_new+0x630/0xf40 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375581] ? amdgpu_sa_bo_manager_fini+0x260/0x260 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375672] ? amdgpu_job_alloc+0x3d/0x310 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375762] ? amdgpu_job_alloc_with_ib+0x24/0xe0 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375838] ? amdgpu_vm_bo_update_mapping+0x2b5/0xb40 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375914] ? amdgpu_vm_bo_update+0x938/0x1c60 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375989] ? amdgpu_vm_handle_moved+0x206/0x2c0 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.376063] ? amdgpu_cs_ioctl+0x27ee/0x4a80 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.376083] ? drm_ioctl_kernel+0x197/0x220 [drm] Sep 12 13:31:41 kaveri kernel: [ 2776.376101] ? drm_ioctl+0x40e/0x860 [drm] Sep 12 13:31:41 kaveri kernel: [ 2776.376171] ? amdgpu_drm_ioctl+0xcc/0x1b0 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.376176] ? do_vfs_ioctl+0x193/0xf70 Sep 12 13:31:41 kaveri kernel: [ 2776.376179] ? ksys_ioctl+0x60/0x90 Sep 12 13:31:41 kaveri kernel: [ 2776.376182] ?
[PATCH] drm/amdgpu: Initialize fences array entries in amdgpu_sa_bo_next_hole
From: Michel Dänzer The entries were only initialized once in amdgpu_sa_bo_new. If a fence wasn't signalled yet in the first amdgpu_sa_bo_next_hole call, but then got signalled before a later amdgpu_sa_bo_next_hole call, it could destroy the fence but leave its pointer in the array, resulting in use-after-free in amdgpu_sa_bo_new. Signed-off-by: Michel Dänzer --- I think this should fix an issue hit by today's piglit run: Sep 12 13:31:41 kaveri kernel: [ 2776.375043] refcount_t: increment on 0; use-after-free. Sep 12 13:31:41 kaveri kernel: [ 2776.375076] WARNING: CPU: 14 PID: 14012 at lib/refcount.c:153 refcount_inc_checked+0x26/0x30 Sep 12 13:31:41 kaveri kernel: [ 2776.375079] Modules linked in: fuse(E) lz4(E) lz4_compress(E) cpufreq_powersave(E) cpufreq_userspace(E) cpufreq_conservative(E) amdgpu(OE) chash(OE) gpu_sched(OE) binfmt_misc(E) nls_ascii(E) nls_cp437(E) vfat(E) fat(E) edac_mce_amd(E) radeon(OE) kvm(E) irqbypass(E) ttm(OE) crct10dif_pclmul(E) crc32_pclmul(E) snd_hda_codec_realtek(E) ghash_clmulni_intel(E) wmi_bmof(E) pcbc(E) snd_hda_codec_generic(E) snd_hda_codec_hdmi(E) drm_kms_helper(OE) aesni_intel(E) snd_hda_intel(E) aes_x86_64(E) snd_hda_codec(E) crypto_simd(E) r8169(E) snd_hda_core(E) cryptd(E) efi_pstore(E) drm(OE) glue_helper(E) sg(E) snd_hwdep(E) libphy(E) i2c_algo_bit(E) snd_pcm(E) fb_sys_fops(E) syscopyarea(E) sysfillrect(E) snd_timer(E) sysimgblt(E) efivars(E) pcspkr(E) snd(E) ccp(E) soundcore(E) sp5100_tco(E) rng_core(E) i2c_piix4(E) Sep 12 13:31:41 kaveri kernel: [ 2776.375237] k10temp(E) wmi(E) button(E) pcc_cpufreq(E) acpi_cpufreq(E) tcp_bbr(E) sch_fq(E) sunrpc(E) nct6775(E) hwmon_vid(E) efivarfs(E) ip_tables(E) x_tables(E) autofs4(E) ext4(E) crc32c_generic(E) crc16(E) mbcache(E) jbd2(E) fscrypto(E) dm_mod(E) raid10(E) raid1(E) raid0(E) multipath(E) linear(E) md_mod(E) sd_mod(E) evdev(E) hid_generic(E) usbhid(E) hid(E) ahci(E) libahci(E) libata(E) xhci_pci(E) xhci_hcd(E) crc32c_intel(E) usbcore(E) scsi_mod(E) gpio_amdpt(E) gpio_generic(E) Sep 12 13:31:41 kaveri kernel: [ 2776.375355] CPU: 14 PID: 14012 Comm: arb_shader:cs0 Tainted: G OE 4.19.0-rc1+ #112 Sep 12 13:31:41 kaveri kernel: [ 2776.375359] Hardware name: Micro-Star International Co., Ltd. MS-7A34/B350 TOMAHAWK (MS-7A34), BIOS 1.80 09/13/2017 Sep 12 13:31:41 kaveri kernel: [ 2776.375364] RIP: 0010:refcount_inc_checked+0x26/0x30 Sep 12 13:31:41 kaveri kernel: [ 2776.375369] Code: 00 00 00 00 e8 ab fe ff ff 84 c0 74 01 c3 80 3d f3 35 b3 01 00 75 f6 48 c7 c7 a0 c5 fe 9f c6 05 e3 35 b3 01 01 e8 85 7f 58 ff <0f> 0b c3 0f 1f 80 00 00 00 00 41 56 41 55 41 54 41 89 fc 55 48 bd Sep 12 13:31:41 kaveri kernel: [ 2776.375372] RSP: 0018:8803de50f070 EFLAGS: 00010286 Sep 12 13:31:41 kaveri kernel: [ 2776.375379] RAX: RBX: 8803de50f278 RCX: 9e65c7f0 Sep 12 13:31:41 kaveri kernel: [ 2776.375383] RDX: RSI: 0008 RDI: 8803ee19e9c0 Sep 12 13:31:41 kaveri kernel: [ 2776.375386] RBP: 88020c8453e0 R08: ed007dc33d39 R09: ed007dc33d38 Sep 12 13:31:41 kaveri kernel: [ 2776.375390] R10: ed007dc33d38 R11: 8803ee19e9c7 R12: 0003 Sep 12 13:31:41 kaveri kernel: [ 2776.375393] R13: dc00 R14: 0002 R15: 8803de50f330 Sep 12 13:31:41 kaveri kernel: [ 2776.375397] FS: 7f2901924700() GS:8803ee18() knlGS: Sep 12 13:31:41 kaveri kernel: [ 2776.375401] CS: 0010 DS: ES: CR0: 80050033 Sep 12 13:31:41 kaveri kernel: [ 2776.375404] CR2: 55b1f3c5e000 CR3: 0003e5ca CR4: 003406e0 Sep 12 13:31:41 kaveri kernel: [ 2776.375407] Call Trace: Sep 12 13:31:41 kaveri kernel: [ 2776.375494] amdgpu_sa_bo_new+0x630/0xf40 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375581] ? amdgpu_sa_bo_manager_fini+0x260/0x260 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375672] ? amdgpu_job_alloc+0x3d/0x310 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375762] ? amdgpu_job_alloc_with_ib+0x24/0xe0 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375838] ? amdgpu_vm_bo_update_mapping+0x2b5/0xb40 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375914] ? amdgpu_vm_bo_update+0x938/0x1c60 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.375989] ? amdgpu_vm_handle_moved+0x206/0x2c0 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.376063] ? amdgpu_cs_ioctl+0x27ee/0x4a80 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.376083] ? drm_ioctl_kernel+0x197/0x220 [drm] Sep 12 13:31:41 kaveri kernel: [ 2776.376101] ? drm_ioctl+0x40e/0x860 [drm] Sep 12 13:31:41 kaveri kernel: [ 2776.376171] ? amdgpu_drm_ioctl+0xcc/0x1b0 [amdgpu] Sep 12 13:31:41 kaveri kernel: [ 2776.376176] ? do_vfs_ioctl+0x193/0xf70 Sep 12 13:31:41 kaveri kernel: [ 2776.376179] ? ksys_ioctl+0x60/0x90 Sep 12 13:31:41 kaveri kernel: [ 2776.376182] ? __x64_sys_ioctl+0x6f/0xb0 Sep 12 13:31:41 kaveri kernel: [ 2776.376186] ? do_syscall_64+0xa5/0x3e0 Sep 12 13:31:41
Re: [PATCH v2 05/17] compat_ioctl: move more drivers to generic_compat_ioctl_ptrarg
Em Wed, 12 Sep 2018 17:08:52 +0200
Arnd Bergmann escreveu:
> The .ioctl and .compat_ioctl file operations have the same prototype so
> they can both point to the same function, which works great almost all
> the time when all the commands are compatible.
>
> One exception is the s390 architecture, where a compat pointer is only
> 31 bit wide, and converting it into a 64-bit pointer requires calling
> compat_ptr(). Most drivers here will ever run in s390, but since we now
> have a generic helper for it, it's easy enough to use it consistently.
>
> I double-checked all these drivers to ensure that all ioctl arguments
> are used as pointers or are ignored, but are not interpreted as integer
> values.
>
> Signed-off-by: Arnd Bergmann
> ---
> drivers/media/rc/lirc_dev.c | 4 +---
> diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c
> index f862f1b7f996..077209f414ed 100644
> --- a/drivers/media/rc/lirc_dev.c
> +++ b/drivers/media/rc/lirc_dev.c
> @@ -730,9 +730,7 @@ static const struct file_operations lirc_fops = {
> .owner = THIS_MODULE,
> .write = ir_lirc_transmit_ir,
> .unlocked_ioctl = ir_lirc_ioctl,
> -#ifdef CONFIG_COMPAT
> - .compat_ioctl = ir_lirc_ioctl,
> -#endif
> + .compat_ioctl = generic_compat_ioctl_ptrarg,
> .read = ir_lirc_read,
> .poll = ir_lirc_poll,
> .open = ir_lirc_open,
Adding an infrared remote controller to a s390 mainframe sounds fun :-)
I suspect that one could implement it on a s390 platform
using gpio-ir-recv and/or gpio-ir-tx drivers. Perhaps one possible
practical usage would be to let the mainframe to send remote
controller codes to adjust the air conditioning system ;-)
From lirc driver's PoV, there's nothing that really prevents one to
do that and use lirc API, and the driver is generic enough to work
on any hardware platform.
I didn't check the implementation of generic_compat_ioctl_ptrarg(),
but assuming it is ok,
Acked-by: Mauro Carvalho Chehab
Thanks,
Mauro
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amdgpu: Moved fault hash table to amdgpu vm
Am 12.09.2018 um 17:29 schrieb Felix Kuehling: On 2018-09-12 02:56 AM, Christian König wrote: Am 12.09.2018 um 00:00 schrieb Felix Kuehling: On 2018-09-11 03:19 AM, Christian König wrote: Hi Felix, let me try to explain the problem on an example: 1. We have a running job which needs recoverable page faults for accessing the process address space. 2. We run into memory pressure on VRAM and start to evict things. 3. A page tables of the running job is picked up for eviction. 4. We schedule a copy command to move the content of the page table to system memory. I think we should change this. If you evict a page table, you don't need to preserve its contents. You should be able to restore the page table contents from scratch when you handle the page fault that restores it. Yeah, already implemented. You actually don't need the page fault for that. 5. The new system memory location of the page table is noted in its BO. You mean in the parent page table? You can just invalidate the entry in the parent page table and let it fault. I'm repeating myself, but exactly that is what won't work. See we still have engines which can't handle page faults which uses the same VM at the same time. This means that we can't just fault in page tables. And I don't understand why that is a problem. Those clients rely on fences to keep their BOs resident, including the page tables. Are you planning to change that? No, but how do you want to swap out page tables when there is a fence added? Or do you want to stop adding fences to page tables for engines with recoverable faults? I think that is completely unrealistic considering the performance penalty of faults. At least for currently available hardware we should limit page faults to be used in as few cases as possible, e.g. SVM and userptr. Regards, Christian. Regards, Felix What we could do is to separate the address space into a low and a high range where we have different handling for both. I've already prototyped this and prepared mostly everything necessary for that, but that is still not 100% completed. Regards, Christian. 6. We get a fault from the job and swap in the page from the process address space. No. Then you need to keep updating page tables that are swapped out. Instead just discard them and rebuild on fault. 7. Now we need to enter the new page address into the page table -> *BAM* The problem is now that we don't know the address of the page table because the current location was replaced with the future location in step #5. You solve that problem by discarding page tables that are swapped out. Then there is no future location. We could now argue that we could update the page tables on the fly for the evicted page and never wait for the current job to finish, but this won't work because not all engines can handle that. Engines that can't handle page faults will depend on fences to keep their page tables resident, like we do today. So they won't have this problem. Regards, Felix I will circumvent this problem for now by blocking the eviction before step #5. The issue with that is that this pipelining is responsible for nearly 20% of the fps in some testcases. I hope that it won't be that bad when I limit disabling the pipelining to only page tables, but it is certainly possible that we will get pushback on this. If that happens we probably need to add some flags to limit this workaround even more to only the root PD and all the PDs/PTs which are involved in recoverable faults. Regards, Christian. Am 10.09.2018 um 21:10 schrieb Felix Kuehling: I'm not sure why you need to distinguish current and future state when dealing with page faults. When you get a page fault, you know that the GPU is trying to access memory right now, in the present. So you're always working with the current state. When the CPU page table changes, you get an MMU notifier that allows you to invalidate the corresponding GPU PTEs. If you have a valid GPU PTE, it always represents the current states and is in sync with the CPU page table. If the GPU page table is ever outdated, it should have an invalid entry in that place. If SDMA is used to update the GPU PTEs, there is a delay. The MMU notifier is synchronous, so it shouldn't be a problem. You just wait for the SDMA job to complete before returning. When updating PTEs with new valid addresses, it's asynchronous. But the GPU will continue retrying on the invalid entry until SDMA finishes. So it's also implicitly synchronized on the GPU side. Regards, Felix On 2018-09-10 05:42 AM, Christian König wrote: Hi Felix & Oak, over the weekend I had the idea that we could just use the shadow BOs to have the current state in a page fault. They are GTT BOs and CPU accessible anyway. Regards, Christian. Am 08.09.2018 um 09:34 schrieb Christian König: Hi Felix, But why do you want to update page tables when there is no more user mode context that cares about them? Is this just to
Re: [PATCH v2 05/17] compat_ioctl: move more drivers to generic_compat_ioctl_ptrarg
On Wed, Sep 12, 2018 at 05:08:52PM +0200, Arnd Bergmann wrote:
> The .ioctl and .compat_ioctl file operations have the same prototype so
> they can both point to the same function, which works great almost all
> the time when all the commands are compatible.
>
> One exception is the s390 architecture, where a compat pointer is only
> 31 bit wide, and converting it into a 64-bit pointer requires calling
> compat_ptr(). Most drivers here will ever run in s390, but since we now
> have a generic helper for it, it's easy enough to use it consistently.
>
> I double-checked all these drivers to ensure that all ioctl arguments
> are used as pointers or are ignored, but are not interpreted as integer
> values.
>
> Signed-off-by: Arnd Bergmann
> drivers/android/binder.c| 2 +-
> drivers/crypto/qat/qat_common/adf_ctl_drv.c | 2 +-
> drivers/dma-buf/dma-buf.c | 4 +---
> drivers/dma-buf/sw_sync.c | 2 +-
> drivers/dma-buf/sync_file.c | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_chardev.c| 2 +-
> drivers/hid/hidraw.c| 4 +---
> drivers/iio/industrialio-core.c | 2 +-
> drivers/infiniband/core/uverbs_main.c | 4 ++--
> drivers/media/rc/lirc_dev.c | 4 +---
> drivers/mfd/cros_ec_dev.c | 4 +---
> drivers/misc/vmw_vmci/vmci_host.c | 2 +-
> drivers/nvdimm/bus.c| 4 ++--
> drivers/nvme/host/core.c| 2 +-
> drivers/pci/switch/switchtec.c | 2 +-
> drivers/platform/x86/wmi.c | 2 +-
> drivers/rpmsg/rpmsg_char.c | 4 ++--
> drivers/sbus/char/display7seg.c | 2 +-
> drivers/sbus/char/envctrl.c | 4 +---
> drivers/scsi/3w-.c | 4 +---
> drivers/scsi/cxlflash/main.c| 2 +-
> drivers/scsi/esas2r/esas2r_main.c | 2 +-
> drivers/scsi/pmcraid.c | 4 +---
> drivers/staging/android/ion/ion.c | 4 +---
> drivers/staging/vme/devices/vme_user.c | 2 +-
> drivers/tee/tee_core.c | 2 +-
> drivers/usb/class/cdc-wdm.c | 2 +-
> drivers/usb/class/usbtmc.c | 4 +---
> drivers/video/fbdev/ps3fb.c | 2 +-
> drivers/virt/fsl_hypervisor.c | 2 +-
> fs/btrfs/super.c| 2 +-
> fs/ceph/dir.c | 2 +-
> fs/ceph/file.c | 2 +-
> fs/fuse/dev.c | 2 +-
> fs/notify/fanotify/fanotify_user.c | 2 +-
> fs/userfaultfd.c| 2 +-
> net/rfkill/core.c | 2 +-
> 37 files changed, 40 insertions(+), 58 deletions(-)
> diff --git a/drivers/infiniband/core/uverbs_main.c
> b/drivers/infiniband/core/uverbs_main.c
> index 823beca448e1..f4755c1c9cfa 100644
> +++ b/drivers/infiniband/core/uverbs_main.c
> @@ -930,7 +930,7 @@ static const struct file_operations uverbs_fops = {
> .release = ib_uverbs_close,
> .llseek = no_llseek,
> .unlocked_ioctl = ib_uverbs_ioctl,
> - .compat_ioctl = ib_uverbs_ioctl,
> + .compat_ioctl = generic_compat_ioctl_ptrarg,
> };
>
> static const struct file_operations uverbs_mmap_fops = {
> @@ -941,7 +941,7 @@ static const struct file_operations uverbs_mmap_fops = {
> .release = ib_uverbs_close,
> .llseek = no_llseek,
> .unlocked_ioctl = ib_uverbs_ioctl,
> - .compat_ioctl = ib_uverbs_ioctl,
> + .compat_ioctl = generic_compat_ioctl_ptrarg,
> };
>
> static struct ib_client uverbs_client = {
For uverbs:
Acked-by: Jason Gunthorpe
It is very strange, this patch did not appear in the RDMA patchworks,
I almost missed it :|
Jason
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2 05/17] compat_ioctl: move more drivers to generic_compat_ioctl_ptrarg
On Wed, Sep 12, 2018 at 5:08 PM, Arnd Bergmann wrote:
> The .ioctl and .compat_ioctl file operations have the same prototype so
> they can both point to the same function, which works great almost all
> the time when all the commands are compatible.
>
> One exception is the s390 architecture, where a compat pointer is only
> 31 bit wide, and converting it into a 64-bit pointer requires calling
> compat_ptr(). Most drivers here will ever run in s390, but since we now
> have a generic helper for it, it's easy enough to use it consistently.
>
> I double-checked all these drivers to ensure that all ioctl arguments
> are used as pointers or are ignored, but are not interpreted as integer
> values.
>
> Signed-off-by: Arnd Bergmann
Acked-by: Daniel Vetter
At least for the drm and dma-buf bits.
-Daniel
> ---
> drivers/android/binder.c| 2 +-
> drivers/crypto/qat/qat_common/adf_ctl_drv.c | 2 +-
> drivers/dma-buf/dma-buf.c | 4 +---
> drivers/dma-buf/sw_sync.c | 2 +-
> drivers/dma-buf/sync_file.c | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_chardev.c| 2 +-
> drivers/hid/hidraw.c| 4 +---
> drivers/iio/industrialio-core.c | 2 +-
> drivers/infiniband/core/uverbs_main.c | 4 ++--
> drivers/media/rc/lirc_dev.c | 4 +---
> drivers/mfd/cros_ec_dev.c | 4 +---
> drivers/misc/vmw_vmci/vmci_host.c | 2 +-
> drivers/nvdimm/bus.c| 4 ++--
> drivers/nvme/host/core.c| 2 +-
> drivers/pci/switch/switchtec.c | 2 +-
> drivers/platform/x86/wmi.c | 2 +-
> drivers/rpmsg/rpmsg_char.c | 4 ++--
> drivers/sbus/char/display7seg.c | 2 +-
> drivers/sbus/char/envctrl.c | 4 +---
> drivers/scsi/3w-.c | 4 +---
> drivers/scsi/cxlflash/main.c| 2 +-
> drivers/scsi/esas2r/esas2r_main.c | 2 +-
> drivers/scsi/pmcraid.c | 4 +---
> drivers/staging/android/ion/ion.c | 4 +---
> drivers/staging/vme/devices/vme_user.c | 2 +-
> drivers/tee/tee_core.c | 2 +-
> drivers/usb/class/cdc-wdm.c | 2 +-
> drivers/usb/class/usbtmc.c | 4 +---
> drivers/video/fbdev/ps3fb.c | 2 +-
> drivers/virt/fsl_hypervisor.c | 2 +-
> fs/btrfs/super.c| 2 +-
> fs/ceph/dir.c | 2 +-
> fs/ceph/file.c | 2 +-
> fs/fuse/dev.c | 2 +-
> fs/notify/fanotify/fanotify_user.c | 2 +-
> fs/userfaultfd.c| 2 +-
> net/rfkill/core.c | 2 +-
> 37 files changed, 40 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/android/binder.c b/drivers/android/binder.c
> index d58763b6b009..d2464f5759f8 100644
> --- a/drivers/android/binder.c
> +++ b/drivers/android/binder.c
> @@ -5576,7 +5576,7 @@ static const struct file_operations binder_fops = {
> .owner = THIS_MODULE,
> .poll = binder_poll,
> .unlocked_ioctl = binder_ioctl,
> - .compat_ioctl = binder_ioctl,
> + .compat_ioctl = generic_compat_ioctl_ptrarg,
> .mmap = binder_mmap,
> .open = binder_open,
> .flush = binder_flush,
> diff --git a/drivers/crypto/qat/qat_common/adf_ctl_drv.c
> b/drivers/crypto/qat/qat_common/adf_ctl_drv.c
> index abc7a7f64d64..8ff77a70addc 100644
> --- a/drivers/crypto/qat/qat_common/adf_ctl_drv.c
> +++ b/drivers/crypto/qat/qat_common/adf_ctl_drv.c
> @@ -68,7 +68,7 @@ static long adf_ctl_ioctl(struct file *fp, unsigned int
> cmd, unsigned long arg);
> static const struct file_operations adf_ctl_ops = {
> .owner = THIS_MODULE,
> .unlocked_ioctl = adf_ctl_ioctl,
> - .compat_ioctl = adf_ctl_ioctl,
> + .compat_ioctl = generic_compat_ioctl_ptrarg,
> };
>
> struct adf_ctl_drv_info {
> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
> index 13884474d158..a6d7dc4cf7e9 100644
> --- a/drivers/dma-buf/dma-buf.c
> +++ b/drivers/dma-buf/dma-buf.c
> @@ -325,9 +325,7 @@ static const struct file_operations dma_buf_fops = {
> .llseek = dma_buf_llseek,
> .poll = dma_buf_poll,
> .unlocked_ioctl = dma_buf_ioctl,
> -#ifdef CONFIG_COMPAT
> - .compat_ioctl = dma_buf_ioctl,
> -#endif
> + .compat_ioctl = generic_compat_ioctl_ptrarg,
> };
>
> /*
> diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c
> index 53c1d6d36a64..bc810506d487 100644
> --- a/drivers/dma-buf/sw_sync.c
> +++ b/drivers/dma-buf/sw_sync.c
> @@ -419,5 +419,5 @@ const struct file_operations sw_sync_debugfs_fops = {
> .open = sw_sync_debugfs_open,
> .release= sw_sync_debugfs_release,
> .unlocked_ioctl = sw_sync_ioctl,
>
Re: [PATCH v2 0/3] Add DMCU fw loading on raven
Series is: Reviewed-by: Alex Deucher From: amd-gfx on behalf of David Francis Sent: Wednesday, September 12, 2018 10:34:42 AM To: amd-gfx@lists.freedesktop.org Cc: Francis, David Subject: [PATCH v2 0/3] Add DMCU fw loading on raven v2: measure intv offset in bytes instead of words David Francis (3): drm/amd: Add ucode DMCU support drm/amd: Add PSP DMCU support drm/amd: Add DM DMCU support drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 21 - drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 10 ++ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c| 6 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 91 ++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 + 5 files changed, 127 insertions(+), 3 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[pull] amdgpu drm-fixes-4.19
Hi Dave, A few fixes for 4.19: - Fix a small memory leak - SR-IOV reset fix - Fix locking in MMU-notifier error path - Updated SDMA golden settings to fix a PRT hang The following changes since commit 67c6ed7cf9ebe53815f15bfdeb49ad91801c2235: Merge tag 'drm-intel-fixes-2018-09-05' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes (2018-09-07 11:07:03 +1000) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-fixes-4.19 for you to fetch changes up to 0165de983272d1fae0809ed9db47c46a412279bc: drm/amdgpu: fix error handling in amdgpu_cs_user_fence_chunk (2018-09-11 16:35:00 -0500) Christian König (2): drm/amdgpu: fix amdgpu_mn_unlock() in the CS error path drm/amdgpu: fix error handling in amdgpu_cs_user_fence_chunk Emily Deng (1): drm/amdgpu: move PSP init prior to IH in gpu reset Tao Zhou (1): drm/amdgpu: Fix SDMA hang in prt mode v2 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 25 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 7 +-- 3 files changed, 22 insertions(+), 12 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amdgpu: Moved fault hash table to amdgpu vm
On 2018-09-12 02:56 AM, Christian König wrote: > Am 12.09.2018 um 00:00 schrieb Felix Kuehling: >> On 2018-09-11 03:19 AM, Christian König wrote: >>> Hi Felix, >>> >>> let me try to explain the problem on an example: >>> >>> 1. We have a running job which needs recoverable page faults for >>> accessing the process address space. >>> 2. We run into memory pressure on VRAM and start to evict things. >>> 3. A page tables of the running job is picked up for eviction. >>> 4. We schedule a copy command to move the content of the page table to >>> system memory. >> I think we should change this. If you evict a page table, you don't need >> to preserve its contents. You should be able to restore the page table >> contents from scratch when you handle the page fault that restores it. > > Yeah, already implemented. You actually don't need the page fault for > that. > >>> 5. The new system memory location of the page table is noted in its BO. >> You mean in the parent page table? You can just invalidate the entry in >> the parent page table and let it fault. > > I'm repeating myself, but exactly that is what won't work. > > See we still have engines which can't handle page faults which uses > the same VM at the same time. This means that we can't just fault in > page tables. And I don't understand why that is a problem. Those clients rely on fences to keep their BOs resident, including the page tables. Are you planning to change that? Regards, Felix > > What we could do is to separate the address space into a low and a > high range where we have different handling for both. > > I've already prototyped this and prepared mostly everything necessary > for that, but that is still not 100% completed. > > Regards, > Christian. > >>> 6. We get a fault from the job and swap in the page from the process >>> address space. >> No. Then you need to keep updating page tables that are swapped out. >> Instead just discard them and rebuild on fault. >> >>> 7. Now we need to enter the new page address into the page table -> >>> *BAM* >>> >>> The problem is now that we don't know the address of the page table >>> because the current location was replaced with the future location in >>> step #5. >> You solve that problem by discarding page tables that are swapped out. >> Then there is no future location. >> >>> We could now argue that we could update the page tables on the fly for >>> the evicted page and never wait for the current job to finish, but >>> this won't work because not all engines can handle that. >> Engines that can't handle page faults will depend on fences to keep >> their page tables resident, like we do today. So they won't have this >> problem. >> >> Regards, >> Felix >> >>> I will circumvent this problem for now by blocking the eviction before >>> step #5. The issue with that is that this pipelining is responsible >>> for nearly 20% of the fps in some testcases. >>> >>> I hope that it won't be that bad when I limit disabling the pipelining >>> to only page tables, but it is certainly possible that we will get >>> pushback on this. >>> >>> If that happens we probably need to add some flags to limit this >>> workaround even more to only the root PD and all the PDs/PTs which are >>> involved in recoverable faults. >>> >>> Regards, >>> Christian. >>> >>> Am 10.09.2018 um 21:10 schrieb Felix Kuehling: I'm not sure why you need to distinguish current and future state when dealing with page faults. When you get a page fault, you know that the GPU is trying to access memory right now, in the present. So you're always working with the current state. When the CPU page table changes, you get an MMU notifier that allows you to invalidate the corresponding GPU PTEs. If you have a valid GPU PTE, it always represents the current states and is in sync with the CPU page table. If the GPU page table is ever outdated, it should have an invalid entry in that place. If SDMA is used to update the GPU PTEs, there is a delay. The MMU notifier is synchronous, so it shouldn't be a problem. You just wait for the SDMA job to complete before returning. When updating PTEs with new valid addresses, it's asynchronous. But the GPU will continue retrying on the invalid entry until SDMA finishes. So it's also implicitly synchronized on the GPU side. Regards, Felix On 2018-09-10 05:42 AM, Christian König wrote: > Hi Felix & Oak, > > over the weekend I had the idea that we could just use the shadow BOs > to have the current state in a page fault. They are GTT BOs and CPU > accessible anyway. > > Regards, > Christian. > > Am 08.09.2018 um 09:34 schrieb Christian König: >> Hi Felix, >> >>> But why do you want to update page tables when there is no more >>> user >>> mode context that cares about them? Is this just to allow pending >>> work >>> to
[PATCH v2 05/17] compat_ioctl: move more drivers to generic_compat_ioctl_ptrarg
The .ioctl and .compat_ioctl file operations have the same prototype so
they can both point to the same function, which works great almost all
the time when all the commands are compatible.
One exception is the s390 architecture, where a compat pointer is only
31 bit wide, and converting it into a 64-bit pointer requires calling
compat_ptr(). Most drivers here will ever run in s390, but since we now
have a generic helper for it, it's easy enough to use it consistently.
I double-checked all these drivers to ensure that all ioctl arguments
are used as pointers or are ignored, but are not interpreted as integer
values.
Signed-off-by: Arnd Bergmann
---
drivers/android/binder.c| 2 +-
drivers/crypto/qat/qat_common/adf_ctl_drv.c | 2 +-
drivers/dma-buf/dma-buf.c | 4 +---
drivers/dma-buf/sw_sync.c | 2 +-
drivers/dma-buf/sync_file.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c| 2 +-
drivers/hid/hidraw.c| 4 +---
drivers/iio/industrialio-core.c | 2 +-
drivers/infiniband/core/uverbs_main.c | 4 ++--
drivers/media/rc/lirc_dev.c | 4 +---
drivers/mfd/cros_ec_dev.c | 4 +---
drivers/misc/vmw_vmci/vmci_host.c | 2 +-
drivers/nvdimm/bus.c| 4 ++--
drivers/nvme/host/core.c| 2 +-
drivers/pci/switch/switchtec.c | 2 +-
drivers/platform/x86/wmi.c | 2 +-
drivers/rpmsg/rpmsg_char.c | 4 ++--
drivers/sbus/char/display7seg.c | 2 +-
drivers/sbus/char/envctrl.c | 4 +---
drivers/scsi/3w-.c | 4 +---
drivers/scsi/cxlflash/main.c| 2 +-
drivers/scsi/esas2r/esas2r_main.c | 2 +-
drivers/scsi/pmcraid.c | 4 +---
drivers/staging/android/ion/ion.c | 4 +---
drivers/staging/vme/devices/vme_user.c | 2 +-
drivers/tee/tee_core.c | 2 +-
drivers/usb/class/cdc-wdm.c | 2 +-
drivers/usb/class/usbtmc.c | 4 +---
drivers/video/fbdev/ps3fb.c | 2 +-
drivers/virt/fsl_hypervisor.c | 2 +-
fs/btrfs/super.c| 2 +-
fs/ceph/dir.c | 2 +-
fs/ceph/file.c | 2 +-
fs/fuse/dev.c | 2 +-
fs/notify/fanotify/fanotify_user.c | 2 +-
fs/userfaultfd.c| 2 +-
net/rfkill/core.c | 2 +-
37 files changed, 40 insertions(+), 58 deletions(-)
diff --git a/drivers/android/binder.c b/drivers/android/binder.c
index d58763b6b009..d2464f5759f8 100644
--- a/drivers/android/binder.c
+++ b/drivers/android/binder.c
@@ -5576,7 +5576,7 @@ static const struct file_operations binder_fops = {
.owner = THIS_MODULE,
.poll = binder_poll,
.unlocked_ioctl = binder_ioctl,
- .compat_ioctl = binder_ioctl,
+ .compat_ioctl = generic_compat_ioctl_ptrarg,
.mmap = binder_mmap,
.open = binder_open,
.flush = binder_flush,
diff --git a/drivers/crypto/qat/qat_common/adf_ctl_drv.c
b/drivers/crypto/qat/qat_common/adf_ctl_drv.c
index abc7a7f64d64..8ff77a70addc 100644
--- a/drivers/crypto/qat/qat_common/adf_ctl_drv.c
+++ b/drivers/crypto/qat/qat_common/adf_ctl_drv.c
@@ -68,7 +68,7 @@ static long adf_ctl_ioctl(struct file *fp, unsigned int cmd,
unsigned long arg);
static const struct file_operations adf_ctl_ops = {
.owner = THIS_MODULE,
.unlocked_ioctl = adf_ctl_ioctl,
- .compat_ioctl = adf_ctl_ioctl,
+ .compat_ioctl = generic_compat_ioctl_ptrarg,
};
struct adf_ctl_drv_info {
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index 13884474d158..a6d7dc4cf7e9 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -325,9 +325,7 @@ static const struct file_operations dma_buf_fops = {
.llseek = dma_buf_llseek,
.poll = dma_buf_poll,
.unlocked_ioctl = dma_buf_ioctl,
-#ifdef CONFIG_COMPAT
- .compat_ioctl = dma_buf_ioctl,
-#endif
+ .compat_ioctl = generic_compat_ioctl_ptrarg,
};
/*
diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c
index 53c1d6d36a64..bc810506d487 100644
--- a/drivers/dma-buf/sw_sync.c
+++ b/drivers/dma-buf/sw_sync.c
@@ -419,5 +419,5 @@ const struct file_operations sw_sync_debugfs_fops = {
.open = sw_sync_debugfs_open,
.release= sw_sync_debugfs_release,
.unlocked_ioctl = sw_sync_ioctl,
- .compat_ioctl = sw_sync_ioctl,
+ .compat_ioctl = generic_compat_ioctl_ptrarg,
};
diff --git a/drivers/dma-buf/sync_file.c b/drivers/dma-buf/sync_file.c
index 35dd06479867..1c64ed60c658 100644
--- a/drivers/dma-buf/sync_file.c
+++ b/drivers/dma-buf/sync_file.c
@@ -488,5 +488,5 @@ static const struct file_operations
Re: [PATCH] drm/amdgpu: use HMM mirror callback to replace mmu notifier
Am 12.09.2018 um 16:56 schrieb Philip Yang:
On 2018-09-12 03:15 AM, Christian König wrote:
Am 11.09.2018 um 21:31 schrieb Philip Yang:
Replace our MMU notifier with hmm_mirror_ops.sync_cpu_device_pagetables
callback if kernel configured
HMM. Kenel configured without HMM still uses
our own MMU notifier.
Please drop that and always use the HMM path.
When a kernel doesn't support HMM we should not support userptr either.
Christian.
I'd like to always use HMM path, but this patch needs support old
kernel w/o HMM.
Currently userptr works w/o HMM support, do I miss something or
misunderstand?
We don't need to support older kernel w/o HMM for upstream.
Support for older kernels is something purely done on release branches.
Regards,
Christian.
Regards,
Philip
It supports both KFD userptr and gfx userptr paths.
This depends on several HMM patchset from Jérôme Glisse queued for
upstream. See
http://172.27.226.38/root/kernel_amd/commits/hmm-dev-v01 (for AMD
intranet)
Change-Id: Ie62c3c5e3c5b8521ab3b438d1eff2aa2a003835e
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 77
+
drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 41 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 49 -
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 6 +++
5 files changed, 173 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 138cb78..ee691e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -172,6 +172,7 @@ amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
+amdgpu-$(CONFIG_HMM) += amdgpu_hmm.o
include $(FULL_AMD_PATH)/powerplay/Makefile
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
new file mode 100644
index 000..a502c11
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person
obtaining a
+ * copy of this software and associated documentation files (the
"Software"),
+ * to deal in the Software without restriction, including without
limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
sublicense,
+ * and/or sell copies of the Software, and to permit persons to
whom the
+ * Software is furnished to do so, subject to the following
conditions:
+ *
+ * The above copyright notice and this permission notice shall be
included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "amdgpu.h"
+#include "amdgpu_mn.h"
+
+static void amdgpu_hmm_release(struct hmm_mirror *mirror)
+{
+ pr_debug("mirror=%p\n", mirror);
+}
+
+static int amdgpu_hmm_sync_cpu_device_pagetables(struct hmm_mirror
*mirror,
+ const struct hmm_update *update)
+{
+ struct hmm *hmm;
+ struct mm_struct *mm;
+ unsigned long start;
+ unsigned long end;
+
+ start = update->start;
+ end = update->end;
+
+ pr_debug("mirror %p start %lx end %lx\n", mirror, start, end);
+
+ hmm = mirror->hmm;
+ mm = *(struct mm_struct **)hmm;
+
+ return amdgpu_mn_invalidate_range(mirror, mm, start, end,
+ update->blockable);
+}
+
+static struct hmm_mirror_ops amdgpu_hmm_mirror_ops = {
+ .sync_cpu_device_pagetables =
amdgpu_hmm_sync_cpu_device_pagetables,
+ .release = amdgpu_hmm_release
+};
+
+int amdgpu_hmm_register(struct hmm_mirror *mirror, struct mm_struct
*mm)
+{
+ pr_debug("mirror=%p\n", mirror);
+
+ mirror->ops = _hmm_mirror_ops;
+
+ return hmm_mirror_register(mirror, mm);
+}
+
+void amdgpu_hmm_unregister(struct hmm_mirror *mirror)
+{
+ pr_debug("mirror=%p\n", mirror);
+
+ hmm_mirror_unregister(mirror);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
new file mode 100644
index 000..a21a5f6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2018 Advanced Micro
Re: [PATCH] drm/amdgpu: use HMM mirror callback to replace mmu notifier
On 2018-09-12 03:15 AM, Christian König wrote:
Am 11.09.2018 um 21:31 schrieb Philip Yang:
Replace our MMU notifier with hmm_mirror_ops.sync_cpu_device_pagetables
callback if kernel configured
HMM. Kenel configured without HMM still uses
our own MMU notifier.
Please drop that and always use the HMM path.
When a kernel doesn't support HMM we should not support userptr either.
Christian.
I'd like to always use HMM path, but this patch needs support old kernel
w/o HMM.
Currently userptr works w/o HMM support, do I miss something or
misunderstand?
Regards,
Philip
It supports both KFD userptr and gfx userptr paths.
This depends on several HMM patchset from Jérôme Glisse queued for
upstream. See
http://172.27.226.38/root/kernel_amd/commits/hmm-dev-v01 (for AMD
intranet)
Change-Id: Ie62c3c5e3c5b8521ab3b438d1eff2aa2a003835e
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 77
+
drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 41 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 49 -
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 6 +++
5 files changed, 173 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 138cb78..ee691e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -172,6 +172,7 @@ amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
+amdgpu-$(CONFIG_HMM) += amdgpu_hmm.o
include $(FULL_AMD_PATH)/powerplay/Makefile
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
new file mode 100644
index 000..a502c11
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person
obtaining a
+ * copy of this software and associated documentation files (the
"Software"),
+ * to deal in the Software without restriction, including without
limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom
the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "amdgpu.h"
+#include "amdgpu_mn.h"
+
+static void amdgpu_hmm_release(struct hmm_mirror *mirror)
+{
+ pr_debug("mirror=%p\n", mirror);
+}
+
+static int amdgpu_hmm_sync_cpu_device_pagetables(struct hmm_mirror
*mirror,
+ const struct hmm_update *update)
+{
+ struct hmm *hmm;
+ struct mm_struct *mm;
+ unsigned long start;
+ unsigned long end;
+
+ start = update->start;
+ end = update->end;
+
+ pr_debug("mirror %p start %lx end %lx\n", mirror, start, end);
+
+ hmm = mirror->hmm;
+ mm = *(struct mm_struct **)hmm;
+
+ return amdgpu_mn_invalidate_range(mirror, mm, start, end,
+ update->blockable);
+}
+
+static struct hmm_mirror_ops amdgpu_hmm_mirror_ops = {
+ .sync_cpu_device_pagetables =
amdgpu_hmm_sync_cpu_device_pagetables,
+ .release = amdgpu_hmm_release
+};
+
+int amdgpu_hmm_register(struct hmm_mirror *mirror, struct mm_struct
*mm)
+{
+ pr_debug("mirror=%p\n", mirror);
+
+ mirror->ops = _hmm_mirror_ops;
+
+ return hmm_mirror_register(mirror, mm);
+}
+
+void amdgpu_hmm_unregister(struct hmm_mirror *mirror)
+{
+ pr_debug("mirror=%p\n", mirror);
+
+ hmm_mirror_unregister(mirror);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
new file mode 100644
index 000..a21a5f6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person
obtaining a
+ * copy of this software and associated documentation files (the
"Software"),
+ * to deal in the Software
[PATCH v2 2/3] drm/amd: Add PSP DMCU support
DMCU (Display Microcontroller Unit) is a GPU chip involved in eDP features like Adaptive Backlight Modulation and Panel Self Refresh. PSP is already equipped to handle DMCU firmware loading, all that is needed is to translate between the new DMCU ucode ID and the equivalent psp_gfx_fw_type. Signed-off-by: David Francis --- drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 02be34e72ed9..240dc8c85867 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -91,6 +91,12 @@ psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type * case AMDGPU_UCODE_ID_VCN: *type = GFX_FW_TYPE_VCN; break; + case AMDGPU_UCODE_ID_DMCU_ERAM: + *type = GFX_FW_TYPE_DMCU_ERAM; + break; + case AMDGPU_UCODE_ID_DMCU_INTV: + *type = GFX_FW_TYPE_DMCU_ISR; + break; case AMDGPU_UCODE_ID_MAXIMUM: default: return -EINVAL; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2 3/3] drm/amd: Add DM DMCU support
DMCU (Display Microcontroller Unit) is a GPU chip involved in
eDP features like Adaptive Backlight Modulation and Panel Self
Refresh.
DC is already fully equipped to initialize DMCU as long as the
firmware is loaded.
At the moment only the raven firmware is available.
A single .bin file is loaded by the kernel's loading mechanism
and split into two ucodes according to the header.
DMCU is optional, so if the firmware is not found, no error or
warning is raised.
Signed-off-by: David Francis
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 91 ++-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +
2 files changed, 92 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5103eba75cb3..7cb753e1d026 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -30,6 +30,7 @@
#include "vid.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
+#include "amdgpu_ucode.h"
#include "atom.h"
#include "amdgpu_dm.h"
#include "amdgpu_pm.h"
@@ -50,6 +51,7 @@
#include
#include
#include
+#include
#include
#include
@@ -71,6 +73,9 @@
#include "modules/inc/mod_freesync.h"
+#define FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcue.bin"
+MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
+
/* basic init/fini API */
static int amdgpu_dm_init(struct amdgpu_device *adev);
static void amdgpu_dm_fini(struct amdgpu_device *adev);
@@ -514,13 +519,97 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
return;
}
-static int dm_sw_init(void *handle)
+static int load_dmcu_fw(struct amdgpu_device *adev)
{
+ const char *fw_name_dmcu;
+ int r;
+ const struct dmcu_firmware_header_v1_0 *hdr;
+
+ switch(adev->asic_type) {
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+ case CHIP_TONGA:
+ case CHIP_FIJI:
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ case CHIP_POLARIS11:
+ case CHIP_POLARIS10:
+ case CHIP_POLARIS12:
+ case CHIP_VEGAM:
+ case CHIP_VEGA10:
+ case CHIP_VEGA12:
+ case CHIP_VEGA20:
+ return 0;
+ case CHIP_RAVEN:
+ fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
+ break;
+ default:
+ DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
+ return -1;
+ }
+
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU
loading\n");
+ return 0;
+ }
+
+ r = request_firmware_direct(>dm.fw_dmcu, fw_name_dmcu, adev->dev);
+ if (r == -ENOENT) {
+ /* DMCU firmware is not necessary, so don't raise a fuss if
it's missing */
+ DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
+ adev->dm.fw_dmcu = NULL;
+ return 0;
+ }
+ if (r) {
+ dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
+ fw_name_dmcu);
+ return r;
+ }
+
+ r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
+ if (r) {
+ dev_err(adev->dev, "amdgpu_dm: Can't validate firmware
\"%s\"\n",
+ fw_name_dmcu);
+ release_firmware(adev->dm.fw_dmcu);
+ adev->dm.fw_dmcu = NULL;
+ return r;
+ }
+
+ hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
+ adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id =
AMDGPU_UCODE_ID_DMCU_ERAM;
+ adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) -
le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
+
+ adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id =
AMDGPU_UCODE_ID_DMCU_INTV;
+ adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
+
+ DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
+
return 0;
}
+static int dm_sw_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ return load_dmcu_fw(adev);
+}
+
static int dm_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if(adev->dm.fw_dmcu) {
+ release_firmware(adev->dm.fw_dmcu);
+ adev->dm.fw_dmcu = NULL;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index c159584c04f7..9a57c654943a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++
[PATCH v2 1/3] drm/amd: Add ucode DMCU support
DMCU (Display Microcontroller Unit) is a GPU chip involved in
eDP features like Adaptive Backlight Modulation and Panel Self
Refresh.
DMCU has two pieces of firmware: the ERAM and the interrupt
vectors, which must be loaded seperately.
To this end, the DMCU firmware has a custom header and parsing
logic similar to MEC, to extract the two ucodes from a single
struct firmware.
Signed-off-by: David Francis
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 21 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 10 ++
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index a942fd28dae8..1fa8bc337859 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -322,6 +322,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device
*adev,
{
const struct common_firmware_header *header = NULL;
const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
+ const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
if (NULL == ucode->fw)
return 0;
@@ -333,8 +334,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device
*adev,
return 0;
header = (const struct common_firmware_header *)ucode->fw->data;
-
cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
+ dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
(ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
@@ -343,7 +344,9 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device
*adev,
ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
-ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
+ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
+ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
+ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) {
ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
@@ -365,6 +368,20 @@ static int amdgpu_ucode_init_single_fw(struct
amdgpu_device *adev,
le32_to_cpu(header->ucode_array_offset_bytes) +
le32_to_cpu(cp_hdr->jt_offset) *
4),
ucode->ucode_size);
+ } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {
+ ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
+ le32_to_cpu(dmcu_hdr->intv_size_bytes);
+
+ memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+
le32_to_cpu(header->ucode_array_offset_bytes)),
+ ucode->ucode_size);
+ } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {
+ ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
+
+ memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+
le32_to_cpu(header->ucode_array_offset_bytes) +
+
le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
+ ucode->ucode_size);
} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
ucode->ucode_size =
adev->gfx.rlc.save_restore_list_cntl_size_bytes;
memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index b358e7519987..8f3f1117728c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -157,6 +157,13 @@ struct gpu_info_firmware_header_v1_0 {
uint16_t version_minor; /* version */
};
+/* version_major=1, version_minor=0 */
+struct dmcu_firmware_header_v1_0 {
+ struct common_firmware_header header;
+ uint32_t intv_offset_bytes; /* interrupt vectors offset from end of
header, in bytes */
+ uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */
+};
+
/* header is fixed size */
union amdgpu_firmware_header {
struct common_firmware_header common;
@@ -170,6 +177,7 @@ union amdgpu_firmware_header {
struct sdma_firmware_header_v1_0 sdma;
struct sdma_firmware_header_v1_1 sdma_v1_1;
struct gpu_info_firmware_header_v1_0 gpu_info;
+ struct dmcu_firmware_header_v1_0 dmcu;
uint8_t raw[0x100];
};
@@ -196,6 +204,8 @@ enum AMDGPU_UCODE_ID {
AMDGPU_UCODE_ID_UVD1,
AMDGPU_UCODE_ID_VCE,
AMDGPU_UCODE_ID_VCN,
+
