Re: [PATCH 4/4] drm/amdgpu: Change the gfx/sdma init/fini sequence

[Vishwakarma, Pratik]

On 9/20/2018 3:37 PM, Rex Zhu wrote:

initialize gfx/sdma before dpm features enabled.
and disable dpm features before gfx/sdma fini.

Signed-off-by: Rex Zhu 
---
  drivers/gpu/drm/amd/amdgpu/cik.c  | 17 +
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +--
  drivers/gpu/drm/amd/amdgpu/si.c   | 13 +++--
  drivers/gpu/drm/amd/amdgpu/soc15.c|  8 
  drivers/gpu/drm/amd/amdgpu/vi.c   | 24 
  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 16 +---
  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   | 18 --
  7 files changed, 54 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 78ab939..f41f5f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2002,6 +2002,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _v7_2_ip_block);
+   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
if (amdgpu_dpm == -1)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
else
@@ -2014,8 +2016,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
  #endif
else
amdgpu_device_ip_block_add(adev, _v8_2_ip_block);
-   amdgpu_device_ip_block_add(adev, _v7_2_ip_block);
-   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
amdgpu_device_ip_block_add(adev, _v4_2_ip_block);
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
break;
@@ -2023,6 +2023,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _v7_3_ip_block);
+   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
if (amdgpu_dpm == -1)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
else
@@ -2035,8 +2037,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
  #endif
else
amdgpu_device_ip_block_add(adev, _v8_5_ip_block);
-   amdgpu_device_ip_block_add(adev, _v7_3_ip_block);
-   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
amdgpu_device_ip_block_add(adev, _v4_2_ip_block);
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
break;
@@ -2044,6 +2044,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _v7_1_ip_block);
+   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
@@ -2053,8 +2055,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
  #endif
else
amdgpu_device_ip_block_add(adev, _v8_1_ip_block);
-   amdgpu_device_ip_block_add(adev, _v7_1_ip_block);
-   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
+
amdgpu_device_ip_block_add(adev, _v4_2_ip_block);
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
break;
@@ -2063,6 +2064,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _v7_2_ip_block);
+   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
@@ -2072,8 +2075,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
  #endif
else
amdgpu_device_ip_block_add(adev, _v8_3_ip_block);
-   amdgpu_device_ip_block_add(adev, _v7_2_ip_block);
-   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
amdgpu_device_ip_block_add(adev, _v4_2_ip_block);
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);

[PATCH 7/9] drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega12

[Alex Deucher]

So we can query what features are enabled for debugging.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index de81abfbf4f1..9600e2f226e9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1317,7 +1317,11 @@ static int vega12_read_sensor(struct pp_hwmgr *hwmgr, 
int idx,
break;
case AMDGPU_PP_SENSOR_GPU_POWER:
ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
-
+   break;
+   case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
+   ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value);
+   if (!ret)
+   *size = 8;
break;
default:
ret = -EINVAL;
-- 
2.13.6

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[PATCH 1/9] drm/amdgpu/powerplay: add get_argument callback for vega20

[Alex Deucher]

For consistency with other vega parts.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 18 -
 .../gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c   |  5 +
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c   | 23 +-
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h   |  1 -
 4 files changed, 15 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index d45cbfe8e184..7825c6ad1452 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -461,7 +461,7 @@ static int vega20_get_number_of_dpm_level(struct pp_hwmgr 
*hwmgr,
"[GetNumOfDpmLevel] failed to get dpm levels!",
return ret);
 
-   vega20_read_arg_from_smc(hwmgr, num_of_levels);
+   *num_of_levels = smum_get_argument(hwmgr);
PP_ASSERT_WITH_CODE(*num_of_levels > 0,
"[GetNumOfDpmLevel] number of clk levels is invalid!",
return -EINVAL);
@@ -481,7 +481,7 @@ static int vega20_get_dpm_frequency_by_index(struct 
pp_hwmgr *hwmgr,
"[GetDpmFreqByIndex] failed to get dpm freq by index!",
return ret);
 
-   vega20_read_arg_from_smc(hwmgr, clk);
+   *clk = smum_get_argument(hwmgr);
PP_ASSERT_WITH_CODE(*clk,
"[GetDpmFreqByIndex] clk value is invalid!",
return -EINVAL);
@@ -1044,7 +1044,7 @@ static int vega20_od8_get_gfx_clock_base_voltage(
"[GetBaseVoltage] failed to get GFXCLK AVFS voltage 
from SMU!",
return ret);
 
-   vega20_read_arg_from_smc(hwmgr, voltage);
+   *voltage = smum_get_argument(hwmgr);
*voltage = *voltage / VOLTAGE_SCALE;
 
return 0;
@@ -1401,7 +1401,7 @@ static int vega20_get_max_sustainable_clock(struct 
pp_hwmgr *hwmgr,
(clock_select << 16))) == 0,
"[GetMaxSustainableClock] Failed to get max DC clock 
from SMC!",
return ret);
-   vega20_read_arg_from_smc(hwmgr, clock);
+   *clock = smum_get_argument(hwmgr);
 
/* if DC limit is zero, return AC limit */
if (*clock == 0) {
@@ -1410,7 +1410,7 @@ static int vega20_get_max_sustainable_clock(struct 
pp_hwmgr *hwmgr,
(clock_select << 16))) == 0,
"[GetMaxSustainableClock] failed to get max AC clock 
from SMC!",
return ret);
-   vega20_read_arg_from_smc(hwmgr, clock);
+   *clock = smum_get_argument(hwmgr);
}
 
return 0;
@@ -1770,14 +1770,14 @@ static int vega20_get_clock_ranges(struct pp_hwmgr 
*hwmgr,
PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) 
== 0,
"[GetClockRanges] Failed to get max clock from 
SMC!",
return ret);
-   vega20_read_arg_from_smc(hwmgr, clock);
+   *clock = smum_get_argument(hwmgr);
} else {
PP_ASSERT_WITH_CODE((ret = 
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_GetMinDpmFreq,
(clock_select << 16))) == 0,
"[GetClockRanges] Failed to get min clock from 
SMC!",
return ret);
-   vega20_read_arg_from_smc(hwmgr, clock);
+   *clock = smum_get_argument(hwmgr);
}
 
return 0;
@@ -1862,7 +1862,7 @@ static int vega20_get_current_gfx_clk_freq(struct 
pp_hwmgr *hwmgr, uint32_t *gfx
PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16))) == 0,
"[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK 
Frequency Failed!",
return ret);
-   vega20_read_arg_from_smc(hwmgr, _clk);
+   gfx_clk = smum_get_argument(hwmgr);
 
*gfx_freq = gfx_clk * 100;
 
@@ -1880,7 +1880,7 @@ static int vega20_get_current_mclk_freq(struct pp_hwmgr 
*hwmgr, uint32_t *mclk_f
PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16))) == 0,
"[GetCurrentMClkFreq] Attempt to get Current MCLK 
Frequency Failed!",
return ret);
-   vega20_read_arg_from_smc(hwmgr, _clk);
+   mem_clk = smum_get_argument(hwmgr);
 
*mclk_freq = mem_clk * 100;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c
index 2984ddd5428c..1c951a5d827d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c
@@ -37,10 +37,7 @@ static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, 
uint32_t *current_rpm)

[PATCH 5/9] drm/amdgpu: add new AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK sensor

[Alex Deucher]

For getting the 64 bit enabled smc feature mask from vega parts.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 448dee481a38..bd7404532029 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -113,6 +113,7 @@ enum amd_pp_sensors {
AMDGPU_PP_SENSOR_GPU_POWER,
AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
+   AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
 };
 
 enum amd_pp_task {
-- 
2.13.6

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[PATCH 9/9] drm/amdgpu: print smc feature mask in debugfs amdgpu_pm_info

[Alex Deucher]

Print the enabled smc feature mask in amdgpu_pm_info for debugging.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 8c334fc808c2..18d989e0e362 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1976,6 +1976,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device 
*adev)
 {
uint32_t value;
+   uint64_t value64;
uint32_t query = 0;
int size;
 
@@ -2014,6 +2015,10 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, 
struct amdgpu_device *a
seq_printf(m, "GPU Load: %u %%\n", value);
seq_printf(m, "\n");
 
+   /* SMC feature mask */
+   if (!amdgpu_dpm_read_sensor(adev, 
AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *), ))
+   seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
+
/* UVD clocks */
if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void 
*), )) {
if (!value) {
-- 
2.13.6

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[PATCH 8/9] drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega20

[Alex Deucher]

So we can query what features are enabled for debugging.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 260e0e48dcd6..2a554f9edcda 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -1941,6 +1941,11 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, 
int idx,
*size = 16;
ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
break;
+   case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
+   ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
+   if (!ret)
+   *size = 8;
+   break;
default:
ret = -EINVAL;
break;
-- 
2.13.6

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[PATCH 2/9] drm/amdgpu/powerplay: Move vega10_enable_smc_features

[Alex Deucher]

to vega10_smumgr.c.  For consistency with other vega parts.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 11 +--
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |  2 --
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c |  1 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c   |  1 +
 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c   | 10 ++
 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h   |  2 ++
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index ca9be583fb62..f32951f8c688 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -39,6 +39,7 @@
 #include "soc15_common.h"
 #include "pppcielanes.h"
 #include "vega10_hwmgr.h"
+#include "vega10_smumgr.h"
 #include "vega10_processpptables.h"
 #include "vega10_pptable.h"
 #include "vega10_thermal.h"
@@ -4940,16 +4941,6 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.get_performance_level = vega10_get_performance_level,
 };
 
-int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
-   bool enable, uint32_t feature_mask)
-{
-   int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
-   PPSMC_MSG_DisableSmuFeatures;
-
-   return smum_send_msg_to_smc_with_parameter(hwmgr,
-   msg, feature_mask);
-}
-
 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
 {
hwmgr->hwmgr_func = _hwmgr_funcs;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 339820da9e6a..89870556de1b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -441,7 +441,5 @@ int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool 
bgate);
 int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
 int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate);
 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
-int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
-   bool enable, uint32_t feature_mask);
 
 #endif /* _VEGA10_HWMGR_H_ */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
index 22364875a943..2d88abf97e7b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
@@ -23,6 +23,7 @@
 
 #include "hwmgr.h"
 #include "vega10_hwmgr.h"
+#include "vega10_smumgr.h"
 #include "vega10_powertune.h"
 #include "vega10_ppsmc.h"
 #include "vega10_inc.h"
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index aa044c1955fe..407762b36901 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -23,6 +23,7 @@
 
 #include "vega10_thermal.h"
 #include "vega10_hwmgr.h"
+#include "vega10_smumgr.h"
 #include "vega10_ppsmc.h"
 #include "vega10_inc.h"
 #include "soc15_common.h"
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 5d19115f410c..8176d3371e70 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -88,6 +88,16 @@ static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
return 0;
 }
 
+int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
+  bool enable, uint32_t feature_mask)
+{
+   int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
+   PPSMC_MSG_DisableSmuFeatures;
+
+   return smum_send_msg_to_smc_with_parameter(hwmgr,
+   msg, feature_mask);
+}
+
 static int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
uint32_t *features_enabled)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
index 424e868bc768..630c0ae4c03d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
@@ -42,6 +42,8 @@ struct vega10_smumgr {
struct smu_table_arraysmu_tables;
 };
 
+int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
+  bool enable, uint32_t feature_mask);
 
 #endif
 
-- 
2.13.6

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[PATCH 3/9] drm/amdgpu/powerplay: add smu smc_table_manager callback for vega12

[Alex Deucher]

For consistency with other asics.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c |  8 
 .../gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c   | 22 ++
 .../gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h   |  4 
 3 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 0789d64246ca..de81abfbf4f1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -745,8 +745,8 @@ static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
 
memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
 
-   result = vega12_copy_table_to_smc(hwmgr,
-   (uint8_t *)pp_table, TABLE_PPTABLE);
+   result = smum_smc_table_manager(hwmgr,
+   (uint8_t *)pp_table, TABLE_PPTABLE, 
false);
PP_ASSERT_WITH_CODE(!result,
"Failed to upload PPtable!", return result);
 
@@ -2103,8 +2103,8 @@ static int 
vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
 
if ((data->water_marks_bitmap & WaterMarksExist) &&
!(data->water_marks_bitmap & WaterMarksLoaded)) {
-   result = vega12_copy_table_to_smc(hwmgr,
-   (uint8_t *)wm_table, TABLE_WATERMARKS);
+   result = smum_smc_table_manager(hwmgr,
+   (uint8_t *)wm_table, 
TABLE_WATERMARKS, false);
PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return 
EINVAL);
data->water_marks_bitmap |= WaterMarksLoaded;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
index 7f0e2109f40d..ddb801517667 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
@@ -37,8 +37,8 @@
  * @param   hwmgrthe address of the HW manager
  * @param   table_idthe driver's table ID to copy from
  */
-int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
-   uint8_t *table, int16_t table_id)
+static int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ uint8_t *table, int16_t table_id)
 {
struct vega12_smumgr *priv =
(struct vega12_smumgr *)(hwmgr->smu_backend);
@@ -75,8 +75,8 @@ int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
  * @param   hwmgrthe address of the HW manager
  * @param   table_idthe table to copy from
  */
-int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr,
-   uint8_t *table, int16_t table_id)
+static int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr,
+   uint8_t *table, int16_t table_id)
 {
struct vega12_smumgr *priv =
(struct vega12_smumgr *)(hwmgr->smu_backend);
@@ -351,6 +351,19 @@ static int vega12_start_smu(struct pp_hwmgr *hwmgr)
return 0;
 }
 
+static int vega12_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
+   uint16_t table_id, bool rw)
+{
+   int ret;
+
+   if (rw)
+   ret = vega12_copy_table_from_smc(hwmgr, table, table_id);
+   else
+   ret = vega12_copy_table_to_smc(hwmgr, table, table_id);
+
+   return ret;
+}
+
 const struct pp_smumgr_func vega12_smu_funcs = {
.smu_init = _smu_init,
.smu_fini = _smu_fini,
@@ -362,4 +375,5 @@ const struct pp_smumgr_func vega12_smu_funcs = {
.upload_pptable_settings = NULL,
.is_dpm_running = vega12_is_dpm_running,
.get_argument = smu9_get_argument,
+   .smc_table_manager = vega12_smc_table_manager,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h
index b285cbc04019..aeec965ce81f 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h
@@ -48,10 +48,6 @@ struct vega12_smumgr {
 #define SMU_FEATURES_HIGH_MASK   0x
 #define SMU_FEATURES_HIGH_SHIFT  32
 
-int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
-   uint8_t *table, int16_t table_id);
-int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr,
-   uint8_t *table, int16_t table_id);
 int vega12_enable_smc_features(struct pp_hwmgr *hwmgr,
bool enable, uint64_t feature_mask);
 int vega12_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
-- 
2.13.6

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[PATCH 4/9] drm/amdgpu/powerplay: add smu smc_table_manager callback for vega20

[Alex Deucher]

For consistency with other asics.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 32 +++---
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c   | 22 ---
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h   |  4 ---
 3 files changed, 34 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 7825c6ad1452..260e0e48dcd6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -743,8 +743,8 @@ static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
 
memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
 
-   result = vega20_copy_table_to_smc(hwmgr,
-   (uint8_t *)pp_table, TABLE_PPTABLE);
+   result = smum_smc_table_manager(hwmgr,
+   (uint8_t *)pp_table, TABLE_PPTABLE, 
false);
PP_ASSERT_WITH_CODE(!result,
"[InitSMCTable] Failed to upload PPtable!",
return result);
@@ -1067,7 +1067,7 @@ static int vega20_od8_initialize_default_settings(
vega20_od8_set_feature_id(hwmgr);
 
/* Set default values */
-   ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)od_table, 
TABLE_OVERDRIVE);
+   ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, 
TABLE_OVERDRIVE, true);
PP_ASSERT_WITH_CODE(!ret,
"Failed to export over drive table!",
return ret);
@@ -1195,7 +1195,7 @@ static int vega20_od8_initialize_default_settings(
}
}
 
-   ret = vega20_copy_table_to_smc(hwmgr, (uint8_t *)od_table, 
TABLE_OVERDRIVE);
+   ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, 
TABLE_OVERDRIVE, false);
PP_ASSERT_WITH_CODE(!ret,
"Failed to import over drive table!",
return ret);
@@ -1214,7 +1214,7 @@ static int vega20_od8_set_settings(
struct vega20_od8_single_setting *od8_settings =
data->od8_settings.od8_settings_array;
 
-   ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)(_table), 
TABLE_OVERDRIVE);
+   ret = smum_smc_table_manager(hwmgr, (uint8_t *)(_table), 
TABLE_OVERDRIVE, true);
PP_ASSERT_WITH_CODE(!ret,
"Failed to export over drive table!",
return ret);
@@ -1271,7 +1271,7 @@ static int vega20_od8_set_settings(
break;
}
 
-   ret = vega20_copy_table_to_smc(hwmgr, (uint8_t *)(_table), 
TABLE_OVERDRIVE);
+   ret = smum_smc_table_manager(hwmgr, (uint8_t *)(_table), 
TABLE_OVERDRIVE, false);
PP_ASSERT_WITH_CODE(!ret,
"Failed to import over drive table!",
return ret);
@@ -1841,7 +1841,7 @@ static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
int ret = 0;
SmuMetrics_t metrics_table;
 
-   ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)_table, 
TABLE_SMU_METRICS);
+   ret = smum_smc_table_manager(hwmgr, (uint8_t *)_table, 
TABLE_SMU_METRICS, true);
PP_ASSERT_WITH_CODE(!ret,
"Failed to export SMU METRICS table!",
return ret);
@@ -1893,7 +1893,7 @@ static int vega20_get_current_activity_percent(struct 
pp_hwmgr *hwmgr,
int ret = 0;
SmuMetrics_t metrics_table;
 
-   ret = vega20_copy_table_from_smc(hwmgr, (uint8_t *)_table, 
TABLE_SMU_METRICS);
+   ret = smum_smc_table_manager(hwmgr, (uint8_t *)_table, 
TABLE_SMU_METRICS, true);
PP_ASSERT_WITH_CODE(!ret,
"Failed to export SMU METRICS table!",
return ret);
@@ -2612,18 +2612,18 @@ static int vega20_odn_edit_dpm_table(struct pp_hwmgr 
*hwmgr,
data->gfxclk_overdrive = false;
data->memclk_overdrive = false;
 
-   ret = vega20_copy_table_from_smc(hwmgr,
-   (uint8_t *)od_table,
-   TABLE_OVERDRIVE);
+   ret = smum_smc_table_manager(hwmgr,
+(uint8_t *)od_table,
+TABLE_OVERDRIVE, true);
PP_ASSERT_WITH_CODE(!ret,
"Failed to export overdrive table!",
return ret);
break;
 
case PP_OD_COMMIT_DPM_TABLE:
-   ret = vega20_copy_table_to_smc(hwmgr,
-   (uint8_t *)od_table,
-   TABLE_OVERDRIVE);
+   ret = smum_smc_table_manager(hwmgr,
+(uint8_t *)od_table,
+TABLE_OVERDRIVE, false);
PP_ASSERT_WITH_CODE(!ret,

[PATCH 6/9] drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega10

[Alex Deucher]

So we can query what features are enabled for debugging.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c   | 5 +
 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 8 
 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h | 2 ++
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index f32951f8c688..419a1d77d661 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3714,6 +3714,11 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, 
int idx,

SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
*((uint32_t *)value) = 
(uint32_t)convert_to_vddc((uint8_t)val_vid);
return 0;
+   case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
+   ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value);
+   if (!ret)
+   *size = 8;
+   break;
default:
ret = -EINVAL;
break;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 8176d3371e70..c81acc3192ad 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -98,8 +98,8 @@ int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
msg, feature_mask);
 }
 
-static int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
-   uint32_t *features_enabled)
+int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
+   uint64_t *features_enabled)
 {
if (features_enabled == NULL)
return -EINVAL;
@@ -112,9 +112,9 @@ static int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
 
 static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
 {
-   uint32_t features_enabled = 0;
+   uint64_t features_enabled = 0;
 
-   vega10_get_smc_features(hwmgr, _enabled);
+   vega10_get_enabled_smc_features(hwmgr, _enabled);
 
if (features_enabled & SMC_DPM_FEATURES)
return true;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
index 630c0ae4c03d..bad760f22624 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
@@ -44,6 +44,8 @@ struct vega10_smumgr {
 
 int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
   bool enable, uint32_t feature_mask);
+int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
+   uint64_t *features_enabled);
 
 #endif
 
-- 
2.13.6

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Re: [PATCH v2 1/6] drm/dp_mst: Introduce drm_dp_mst_connector_atomic_check()

[Harry Wentland]

On 2018-09-19 07:08 PM, Lyude Paul wrote:
> Currently the way that we prevent userspace from performing new modesets
> on MST connectors that have just been destroyed is rather broken.
> There's nothing in the actual DRM DP MST topology helpers that checks
> whether or not a connector still exists, instead each DRM driver does
> this on it's own, usually by returning NULL from the best_encoder
> callback which in turn, causes the atomic commit to fail.
> 
> However, this is wrong in a rather subtle way. If ->best_encoder()
> returns NULL, this makes ALL modesets involving the connector fail. This
> includes modesets from userspace that would shut off the CRTCs being
> used by the connector. Since this results in blocking any changes to a
> connector's DPMS prop, it has the sideaffect of preventing legacy
> modesetting users from ever disabling a CRTC that was previously enabled
> for use in an MST topology. An example of this, where X tries to
> change the DPMS property of an MST connector that was just detached from
> the system:
> 
> [ 2908.320131] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] 
> [CONNECTOR:82:DP-6]
> [ 2908.320148] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] 
> [CONNECTOR:82:DP-6] status updated from connected to disconnected
> [ 2908.320166] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] 
> [CONNECTOR:82:DP-6] disconnected
> [ 2908.320193] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 111 (1)
> [ 2908.320230] [drm:drm_sysfs_hotplug_event [drm]] generating hotplug event
> ...
> [ 2908.638539] [drm:drm_ioctl [drm]] pid=12928, dev=0xe201, auth=1, 
> DRM_IOCTL_MODE_SETPROPERTY
> [ 2908.638546] [drm:drm_atomic_state_init [drm]] Allocated atomic state 
> 7155ba49
> [ 2908.638553] [drm:drm_mode_object_get [drm]] OBJ ID: 114 (1)
> [ 2908.638560] [drm:drm_mode_object_get [drm]] OBJ ID: 108 (1)
> [ 2908.638568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:41:head-0] 
> 97a6396e state to 7155ba49
> [ 2908.638575] [drm:drm_atomic_add_affected_connectors [drm]] Adding all 
> current connectors for [CRTC:41:head-0] to 7155ba49
> [ 2908.638582] [drm:drm_mode_object_get [drm]] OBJ ID: 82 (3)
> [ 2908.638589] [drm:drm_mode_object_get [drm]] OBJ ID: 82 (4)
> [ 2908.638596] [drm:drm_atomic_get_connector_state [drm]] Added 
> [CONNECTOR:82:DP-6] 87427144 state to 7155ba49
> [ 2908.638603] [drm:drm_atomic_check_only [drm]] checking 7155ba49
> [ 2908.638609] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] 
> [CRTC:41:head-0] active changed
> [ 2908.638613] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] 
> Updating routing for [CONNECTOR:82:DP-6]
> [ 2908.638616] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] No 
> suitable encoder found for [CONNECTOR:82:DP-6]
> [ 2908.638623] [drm:drm_atomic_check_only [drm]] atomic driver check for 
> 7155ba49 failed: -22
> [ 2908.638630] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic 
> state 7155ba49
> [ 2908.638637] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 82 (4)
> [ 2908.638643] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 82 (3)
> [ 2908.638650] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 114 (2)
> [ 2908.638656] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 108 (2)
> [ 2908.638663] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 
> 7155ba49
> [ 2908.638669] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 82 (2)
> [ 2908.638676] [drm:drm_ioctl [drm]] pid=12928, ret = -22
> 
> While this doesn't usually result in any errors that would be obvious to
> the user, it does result in us leaving display resources on. This in
> turn leads to unwanted sideaffects like inactive GPUs being left on
> (usually from the resulting leaked runtime PM ref).
> 
> So, provide an easier way of doing this that doesn't require breaking
> ->best_encoder(): add a common drm_dp_mst_connector_atomic_check()
> function that DRM drivers can call in order to have CRTC enabling
> commits fail automatically if the MST port driving the connector no
> longer exists. We'll also be able to expand upon this later as well once
> we add MST fallback retraining support.
> 
> Changes since v1:
> - Use list_for_each_entry_safe in drm_dp_mst_connector_still_exists() -
>   Julia Lawall
> 
> Signed-off-by: Lyude Paul 
> Cc: Julia Lawall 
> Cc: sta...@vger.kernel.org

Whoops, missed the v2 earlier. It's still
Acked-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 76 +++
>  include/drm/drm_dp_mst_helper.h   |  3 ++
>  2 files changed, 79 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 7780567aa669..58b9554711c7 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -3129,6 +3129,82 @@ static const struct drm_private_state_funcs 
> mst_state_funcs = 

Re: [PATCH 6/6] drm/amdgpu/dm/mst: Use drm_dp_mst_connector_atomic_check()

[Harry Wentland]

On 2018-09-18 07:06 PM, Lyude Paul wrote:
> Hook this into amdgpu's atomic check for their connectors so they never
> get modesets on no-longer-present MST connectors. We'll also expand on
> this later once we add DP MST fallback retraining support.
> 
> As well, turns out that the only atomic DRM driver without the
> ->best_encoder() bug is amdgpu. Congrats AMD!
> 
> Signed-off-by: Lyude Paul 

Reviewed-by: Harry Wentland 

Harry

> ---
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c  | 12 
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 9a300732ba37..d011a39f17b2 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -294,10 +294,22 @@ static struct drm_encoder *dm_mst_best_encoder(struct 
> drm_connector *connector)
>   return _dm_connector->mst_encoder->base;
>  }
>  
> +static int
> +amdgpu_dm_mst_connector_atomic_check(struct drm_connector *connector,
> +  struct drm_connector_state *new_cstate)
> +{
> + struct amdgpu_dm_connector *aconnector =
> + to_amdgpu_dm_connector(connector);
> +
> + return drm_dp_mst_connector_atomic_check(connector, new_cstate,
> +  >mst_mgr);
> +}
> +
>  static const struct drm_connector_helper_funcs 
> dm_dp_mst_connector_helper_funcs = {
>   .get_modes = dm_dp_mst_get_modes,
>   .mode_valid = amdgpu_dm_connector_mode_valid,
>   .best_encoder = dm_mst_best_encoder,
> + .atomic_check = amdgpu_dm_mst_connector_atomic_check,
>  };
>  
>  static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
> 
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Re: [PATCH 1/6] drm/dp_mst: Introduce drm_dp_mst_connector_atomic_check()

[Harry Wentland]

On 2018-09-18 07:06 PM, Lyude Paul wrote:
> Currently the way that we prevent userspace from performing new modesets
> on MST connectors that have just been destroyed is rather broken.
> There's nothing in the actual DRM DP MST topology helpers that checks
> whether or not a connector still exists, instead each DRM driver does
> this on it's own, usually by returning NULL from the best_encoder
> callback which in turn, causes the atomic commit to fail.
> 
> However, this is wrong in a rather subtle way. If ->best_encoder()
> returns NULL, this makes ALL modesets involving the connector fail. This
> includes modesets from userspace that would shut off the CRTCs being
> used by the connector. Since this results in blocking any changes to a
> connector's DPMS prop, it has the sideaffect of preventing legacy
> modesetting users from ever disabling a CRTC that was previously enabled
> for use in an MST topology. An example of this, where X tries to
> change the DPMS property of an MST connector that was just detached from
> the system:
> 
> [ 2908.320131] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] 
> [CONNECTOR:82:DP-6]
> [ 2908.320148] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] 
> [CONNECTOR:82:DP-6] status updated from connected to disconnected
> [ 2908.320166] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] 
> [CONNECTOR:82:DP-6] disconnected
> [ 2908.320193] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 111 (1)
> [ 2908.320230] [drm:drm_sysfs_hotplug_event [drm]] generating hotplug event
> ...
> [ 2908.638539] [drm:drm_ioctl [drm]] pid=12928, dev=0xe201, auth=1, 
> DRM_IOCTL_MODE_SETPROPERTY
> [ 2908.638546] [drm:drm_atomic_state_init [drm]] Allocated atomic state 
> 7155ba49
> [ 2908.638553] [drm:drm_mode_object_get [drm]] OBJ ID: 114 (1)
> [ 2908.638560] [drm:drm_mode_object_get [drm]] OBJ ID: 108 (1)
> [ 2908.638568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:41:head-0] 
> 97a6396e state to 7155ba49
> [ 2908.638575] [drm:drm_atomic_add_affected_connectors [drm]] Adding all 
> current connectors for [CRTC:41:head-0] to 7155ba49
> [ 2908.638582] [drm:drm_mode_object_get [drm]] OBJ ID: 82 (3)
> [ 2908.638589] [drm:drm_mode_object_get [drm]] OBJ ID: 82 (4)
> [ 2908.638596] [drm:drm_atomic_get_connector_state [drm]] Added 
> [CONNECTOR:82:DP-6] 87427144 state to 7155ba49
> [ 2908.638603] [drm:drm_atomic_check_only [drm]] checking 7155ba49
> [ 2908.638609] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] 
> [CRTC:41:head-0] active changed
> [ 2908.638613] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] 
> Updating routing for [CONNECTOR:82:DP-6]
> [ 2908.638616] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] No 
> suitable encoder found for [CONNECTOR:82:DP-6]
> [ 2908.638623] [drm:drm_atomic_check_only [drm]] atomic driver check for 
> 7155ba49 failed: -22
> [ 2908.638630] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic 
> state 7155ba49
> [ 2908.638637] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 82 (4)
> [ 2908.638643] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 82 (3)
> [ 2908.638650] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 114 (2)
> [ 2908.638656] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 108 (2)
> [ 2908.638663] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 
> 7155ba49
> [ 2908.638669] [drm:drm_mode_object_put.part.2 [drm]] OBJ ID: 82 (2)
> [ 2908.638676] [drm:drm_ioctl [drm]] pid=12928, ret = -22
> 
> While this doesn't usually result in any errors that would be obvious to
> the user, it does result in us leaving display resources on. This in
> turn leads to unwanted sideaffects like inactive GPUs being left on
> (usually from the resulting leaked runtime PM ref).
> 
> So, provide an easier way of doing this that doesn't require breaking
> ->best_encoder(): add a common drm_dp_mst_connector_atomic_check()
> function that DRM drivers can call in order to have CRTC enabling
> commits fail automatically if the MST port driving the connector no
> longer exists. We'll also be able to expand upon this later as well once
> we add MST fallback retraining support.
> 
> Signed-off-by: Lyude Paul 
> Cc: sta...@vger.kernel.org

This does seem like a saner way to handle the case when the MST connector is 
gone. As this doesn't currently seem to affect amdgpu directly and I therefore 
might miss something I'll leave the RB to someone else, but you have my
Acked-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 76 +++
>  include/drm/drm_dp_mst_helper.h   |  3 ++
>  2 files changed, 79 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 7780567aa669..0162d4bf2549 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -3129,6 +3129,82 @@ static 

Re: Regression on gfx8 with ring init

[Andrey Grodzovsky]

What's the status with this error and the suggested patch to fix it ? It 
impacts GPU reset on Polaris11.


Do we want to investigate why the original patch breaks it or just 
disable with the proposed patch ?



P.S Suspend resume also stopped working on latest branch - will bisect 
it later today or tomorrow.



Andrey


On 09/18/2018 11:00 AM, Christian König wrote:

Tom,

can you try if the following makes it working again?

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

index b6160de70d12..d65f5ba92fc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -937,6 +937,10 @@ static int gfx_v8_0_ring_test_ib(struct 
amdgpu_ring *ring, long timeout)

    return r;
 }

+static int gfx_v8_0_kiq_ring_test_ib(struct amdgpu_ring *ring, long 
timeout)

+{
+   return 0;
+}

 static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
 {
@@ -7174,7 +7178,7 @@ static const struct amdgpu_ring_funcs 
gfx_v8_0_ring_funcs_kiq = {

    .emit_ib = gfx_v8_0_ring_emit_ib_compute,
    .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
    .test_ring = gfx_v8_0_ring_test_ring,
-   .test_ib = gfx_v8_0_ring_test_ib,
+   .test_ib = gfx_v8_0_kiq_ring_test_ib,
    .insert_nop = amdgpu_ring_insert_nop,
    .pad_ib = amdgpu_ring_generic_pad_ib,
    .emit_rreg = gfx_v8_0_ring_emit_rreg,


Thanks,
Christian.

Am 18.09.2018 um 16:41 schrieb Christian König:

CRTC and GFX interrupts seem to be working perfectly fine.

The problem here looks like only EOP interrupts from the Compute 
queue are not correctly handled.


Most likely a bug somewhere in gfx_v8_0_eop_irq().

Christian.

Am 18.09.2018 um 16:36 schrieb Deucher, Alexander:


FWIW, a number of consumer Raven boards have bad IVRS tables 
(windows doesn't use interrupt remapping so they are sometimes wrong 
and probably not validated.  There are a number of workaround to 
manually override the IVRS tables to make interrupts work.  I think 
specifying pci=noacpi is also a possible workaround.



Alex


*From:* amd-gfx  on behalf of 
Christian König 

*Sent:* Tuesday, September 18, 2018 10:31:16 AM
*To:* StDenis, Tom; amd-gfx mailing list; Zhou, David(ChunMing)
*Subject:* Re: Regression on gfx8 with ring init
Well looks like interrupt processing is working perfectly fine.

But looking at the error message once more I see that this actually
affects ring number 9 and not the GFX ring.

Can you fix amdgpu_ib_ring_tests() to print ring->name instead of the
number?

That must be some of the compute rings.

Thanks,
Christian.

Am 18.09.2018 um 16:20 schrieb Tom St Denis:
> On 2018-09-18 10:13 a.m., Christian König wrote:
>> Mhm, there is no more failed IB-test in there isn't it?
>
> oh sorry I thought you wanted to test HEAD~ ... Attached is a log 
from

> the tip of drm-next
>
> Tom
>
>>
>> Christian.
>>
>> Am 18.09.2018 um 16:09 schrieb Tom St Denis:
>>> Disabling IOMMU in the BIOS resulted in a correct boot up...
>>>
>>> Here's the log.
>>>
>>> Tom
>>>
>>> On 2018-09-18 9:58 a.m., Tom St Denis wrote:
 Odd I couldn't even boot my system with the dGPU as primary after
 rebuilding the kernel.  It got hung up in the IOMMU driver (loads
 of AMD-Vi IOMMU errors) which I wasn't able to capture because it
 panic'ed before loading the network stack.

 Bizarre.

 I'll keep trying.

 Tom

 On 2018-09-18 9:35 a.m., Christian König wrote:
> Am 18.09.2018 um 15:32 schrieb Tom St Denis:
>> On 2018-09-18 9:30 a.m., Christian König wrote:
>>> Great, not sure if that is a good or a bad news.
>>>
>>> Anyway going to revert the change for now. Does anybody
>>> volunteer to figure out why interrupts sometimes doesn't work
>>> correctly on Raven?
>>
>> What does "doesn't work correctly?"  My workstation is a Raven1
>> (Ryzen 2400G) and other than the TTM bulk move issue has been
>> perfectly stable (through suspend/resumes too I might add).
>>
>> Anything I could test with my devel raven?
>
> The problem seems to be that on some boards IH handling doesn't
> work as it should.
>
> Can you try to disable the onboard graphics and try again?
>
> If that still doesn't work there is a DRM_DEBUG in
> amdgpu_ih_process(), make that a DRM_ERROR and send me the
> resulting dmesg of loading amdgpu (but don't start any UMD).
>
> Thanks,
> Christian.
>
>>
>>
>> Tom
>>
>>>
>>> Christian.
>>>
>>> Am 18.09.2018 um 15:27 schrieb Tom St Denis:
 This commit:

 [root@raven linux]# git bisect good
 9b0df0937a852d299fbe42a5939c9a8a4cc83c55 is the first bad 
commit

 commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55
 Author: Christian König 
 Date:   Tue Sep 18 10:38:09 2018 +0200

   

Re: [PATCH v2] drm/amdgpu:No action when VCN PG state is unchanged

[Christian König]

Am 20.09.2018 um 18:24 schrieb James Zhu:



On 2018-09-20 11:49 AM, Alex Deucher wrote:

On Thu, Sep 20, 2018 at 11:27 AM James Zhu  wrote:



On 2018-09-20 11:14 AM, Alex Deucher wrote:

On Thu, Sep 13, 2018 at 4:56 PM James Zhu  wrote:

When VCN PG state is unchanged, it is unnecessary to reset power
gate state

Signed-off-by: James Zhu 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1 +
   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 12 ++--
   2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

index 0b0b863..d2219ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -69,6 +69,7 @@ struct amdgpu_vcn {
  struct amdgpu_ring  ring_jpeg;
  struct amdgpu_irq_src   irq;
  unsigned    num_enc_rings;
+   enum amd_powergating_state cur_state;

Does the default value (0) at init time properly reflect the default
powergating state?  If so,
Acked-by: Alex Deucher 

Yes, the below code shows it will be set to 0 during driver load stage.

Yes, I understand that.  Is 0 (AMD_PG_STATE_GATE) what we want as the
default though?  The first time the code runs are we going to do the
right thing or is the code going to return early?  IIRC, the hw
default is ungated.

cur_state is used for tracking driver SW PG state, not HW  PG state.
I though no matter what HW  PG state is after device powers up, when 
first vcn ring is scheduled to run,
begin_use->set_powergating_state->vcn_v1_0_start->ungate 
power/clock->Boot_VCPU  will be tried.


For DPG mode, the ungate power/clock , boot VCPU will not actually be 
activated during start setup stage, and

only be activated during ring run stage.


Mhm, I wonder if it wouldn't be better to have that functionality one 
layer up.


E.g. in amdgpu_device_ip_set_powergating_state so that it applies to all 
IP blocks in the same way.


But on the other hand the correct solution looks good to me as well, so 
feel free to add my Acked-by as well.


Christian.



James

Alex

int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)

  adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);

struct amdgpu_device {

  struct amdgpu_vcn    vcn;

Best Regards!
James zhu

   };

   int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

index 2664bb2..2cde0b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1633,12 +1633,20 @@ static int 
vcn_v1_0_set_powergating_state(void *handle,

   * revisit this when there is a cleaner line between
   * the smc and the hw blocks
   */
+   int ret;
  struct amdgpu_device *adev = (struct amdgpu_device 
*)handle;


+   if(state == adev->vcn.cur_state)
+   return 0;
+
  if (state == AMD_PG_STATE_GATE)
-   return vcn_v1_0_stop(adev);
+   ret = vcn_v1_0_stop(adev);
  else
-   return vcn_v1_0_start(adev);
+   ret = vcn_v1_0_start(adev);
+
+   if(!ret)
+   adev->vcn.cur_state = state;
+   return ret;
   }

   static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
--
2.7.4

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Re: [PATCH v2] drm/amdgpu:No action when VCN PG state is unchanged

[James Zhu]

On 2018-09-20 11:49 AM, Alex Deucher wrote:

On Thu, Sep 20, 2018 at 11:27 AM James Zhu  wrote:



On 2018-09-20 11:14 AM, Alex Deucher wrote:

On Thu, Sep 13, 2018 at 4:56 PM James Zhu  wrote:

When VCN PG state is unchanged, it is unnecessary to reset power
gate state

Signed-off-by: James Zhu 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1 +
   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 12 ++--
   2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 0b0b863..d2219ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -69,6 +69,7 @@ struct amdgpu_vcn {
  struct amdgpu_ring  ring_jpeg;
  struct amdgpu_irq_src   irq;
  unsignednum_enc_rings;
+   enum amd_powergating_state cur_state;

Does the default value (0) at init time properly reflect the default
powergating state?  If so,
Acked-by: Alex Deucher 

Yes, the below code shows it will be set to 0 during driver load stage.

Yes, I understand that.  Is 0 (AMD_PG_STATE_GATE) what we want as the
default though?  The first time the code runs are we going to do the
right thing or is the code going to return early?  IIRC, the hw
default is ungated.

cur_state is used for tracking driver SW PG state, not HW  PG state.
I though no matter what HW  PG state is after device powers up, when 
first vcn ring is scheduled to run,
begin_use->set_powergating_state->vcn_v1_0_start->ungate 
power/clock->Boot_VCPU  will be tried.


For DPG mode, the ungate power/clock , boot VCPU will not actually be 
activated during start setup stage, and

only be activated during ring run stage.

James

Alex

int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)

  adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);

struct amdgpu_device {

  struct amdgpu_vcnvcn;

Best Regards!
James zhu

   };

   int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2664bb2..2cde0b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1633,12 +1633,20 @@ static int vcn_v1_0_set_powergating_state(void *handle,
   * revisit this when there is a cleaner line between
   * the smc and the hw blocks
   */
+   int ret;
  struct amdgpu_device *adev = (struct amdgpu_device *)handle;

+   if(state == adev->vcn.cur_state)
+   return 0;
+
  if (state == AMD_PG_STATE_GATE)
-   return vcn_v1_0_stop(adev);
+   ret = vcn_v1_0_stop(adev);
  else
-   return vcn_v1_0_start(adev);
+   ret = vcn_v1_0_start(adev);
+
+   if(!ret)
+   adev->vcn.cur_state = state;
+   return ret;
   }

   static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
--
2.7.4

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[pull] amdgpu drm-fixes-4.19

[Alex Deucher]

Hi Dave,

A few fixes for 4.19:
- Add a new polaris pci id
- KFD fixes for raven and gfx7

The following changes since commit 8ca4fff974ad5288d38298f15bf218f2eac2d5e7:

  Merge tag 'drm-intel-fixes-2018-09-19' of 
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes (2018-09-20 10:01:53 
+1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.19

for you to fetch changes up to 44d8cc6f1a905e4bb1d4221a898abb0d7e9d100a:

  drm/amdkfd: Fix ATS capablity was not reported correctly on some APUs 
(2018-09-20 10:25:23 -0500)


Alex Deucher (1):
  drm/amdgpu: add new polaris pci id

Amber Lin (1):
  drm/amdgpu: Fix SDMA HQD destroy error on gfx_v7

Yong Zhao (2):
  drm/amdkfd: Change the control stack MTYPE from UC to NC on GFX9
  drm/amdkfd: Fix ATS capablity was not reported correctly on some APUs

 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|  6 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c   | 14 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_device.c   |  3 ++-
 drivers/gpu/drm/amd/amdkfd/kfd_iommu.c| 13 -
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c   |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 21 -
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h   |  2 +-
 11 files changed, 49 insertions(+), 18 deletions(-)
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Re: [PATCH v2] drm/amdgpu:No action when VCN PG state is unchanged

[Alex Deucher]

On Thu, Sep 20, 2018 at 11:27 AM James Zhu  wrote:
>
>
>
> On 2018-09-20 11:14 AM, Alex Deucher wrote:
> > On Thu, Sep 13, 2018 at 4:56 PM James Zhu  wrote:
> >> When VCN PG state is unchanged, it is unnecessary to reset power
> >> gate state
> >>
> >> Signed-off-by: James Zhu 
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1 +
> >>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 12 ++--
> >>   2 files changed, 11 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> >> index 0b0b863..d2219ab 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> >> @@ -69,6 +69,7 @@ struct amdgpu_vcn {
> >>  struct amdgpu_ring  ring_jpeg;
> >>  struct amdgpu_irq_src   irq;
> >>  unsignednum_enc_rings;
> >> +   enum amd_powergating_state cur_state;
> > Does the default value (0) at init time properly reflect the default
> > powergating state?  If so,
> > Acked-by: Alex Deucher 
> Yes, the below code shows it will be set to 0 during driver load stage.

Yes, I understand that.  Is 0 (AMD_PG_STATE_GATE) what we want as the
default though?  The first time the code runs are we going to do the
right thing or is the code going to return early?  IIRC, the hw
default is ungated.

Alex

>
> int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
> 
>  adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
>
> struct amdgpu_device {
> 
>  struct amdgpu_vcnvcn;
>
> Best Regards!
> James zhu
> >>   };
> >>
> >>   int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
> >> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> >> index 2664bb2..2cde0b4 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> >> @@ -1633,12 +1633,20 @@ static int vcn_v1_0_set_powergating_state(void 
> >> *handle,
> >>   * revisit this when there is a cleaner line between
> >>   * the smc and the hw blocks
> >>   */
> >> +   int ret;
> >>  struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> +   if(state == adev->vcn.cur_state)
> >> +   return 0;
> >> +
> >>  if (state == AMD_PG_STATE_GATE)
> >> -   return vcn_v1_0_stop(adev);
> >> +   ret = vcn_v1_0_stop(adev);
> >>  else
> >> -   return vcn_v1_0_start(adev);
> >> +   ret = vcn_v1_0_start(adev);
> >> +
> >> +   if(!ret)
> >> +   adev->vcn.cur_state = state;
> >> +   return ret;
> >>   }
> >>
> >>   static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
> >> --
> >> 2.7.4
> >>
> >> ___
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Re: [PATCH 1/3] drm/amd/pp: Avoid divide-by-zero in smu7_fan_ctrl_set_fan_speed_rpm

[Deucher, Alexander]

From: Zhu, Rex
Sent: Thursday, September 20, 2018 10:43 AM
To: Deucher, Alexander; amd-gfx@lists.freedesktop.org; Quan, Evan
Subject: RE: [PATCH 1/3] drm/amd/pp: Avoid divide-by-zero in 
smu7_fan_ctrl_set_fan_speed_rpm


Hi Alex and Evan,



For the fan control via sysfs,  I think we need to clarify the use case.



We support manual/auto fan control mode.



User can set the mode through pwm_enable. 1 mean manual. 2 mean auto

User can set fan speed via pwm1 and fan1_input.



For pwm1, user set the percentage value (0% - 100%)

And can get the pwm1’s range via sysfs: pwm1_min, pwm1_max. the range is [0, 
255]. In driver, we transfer to [0% - 100%]



For fan1_input, user set the fan’s resolution per minute

No way for user to get the range. On Tonga, the range is (0, 6000]. Not support 
zero-rpm on tonga.



Do we need to add new sysfs to expose the RPM range or just print the range in 
dmesg if user’s setting is out of range?



Yes, expose the rpm limits via fan1_min and max.  See:

https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface

for more info on standard sysfs interfaces for hwmon.


Another question is:



Currently, the default fan control mode is auto.

When user change the fan speed via pwm1 or fan1_input, we switch to manual mode 
automatically.



So if user want to change back to auto fan control mode, they need to echo 2 to 
pwm_enable.



I think we should reject any changes unless the user selects manual (1) first.


Best Regards

Rex





From: Deucher, Alexander
Sent: Thursday, September 20, 2018 9:52 PM
To: Zhu, Rex ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/amd/pp: Avoid divide-by-zero in 
smu7_fan_ctrl_set_fan_speed_rpm



Series is:

Reviewed-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>



From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Rex Zhu mailto:rex@amd.com>>
Sent: Thursday, September 20, 2018 3:14:25 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 1/3] drm/amd/pp: Avoid divide-by-zero in 
smu7_fan_ctrl_set_fan_speed_rpm



The minRPM speed maybe equal to zero. so need to check
input RPM not equal to 0, otherwise cause divide-by-zero driver crash.

Signed-off-by: Rex Zhu mailto:rex@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index 44527755..d61a9b4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -260,6 +260,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, 
uint32_t speed)
 if (hwmgr->thermal_controller.fanInfo.bNoFan ||
 (hwmgr->thermal_controller.fanInfo.
 ucTachometerPulsesPerRevolution == 0) ||
+   speed == 0 ||
 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
 (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
 return 0;
--
1.9.1

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Re: [PATCH v2] drm/amdgpu:No action when VCN PG state is unchanged

[James Zhu]

On 2018-09-20 11:14 AM, Alex Deucher wrote:

On Thu, Sep 13, 2018 at 4:56 PM James Zhu  wrote:

When VCN PG state is unchanged, it is unnecessary to reset power
gate state

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1 +
  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 12 ++--
  2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 0b0b863..d2219ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -69,6 +69,7 @@ struct amdgpu_vcn {
 struct amdgpu_ring  ring_jpeg;
 struct amdgpu_irq_src   irq;
 unsignednum_enc_rings;
+   enum amd_powergating_state cur_state;

Does the default value (0) at init time properly reflect the default
powergating state?  If so,
Acked-by: Alex Deucher 

Yes, the below code shows it will be set to 0 during driver load stage.

int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)

    adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);

struct amdgpu_device {

    struct amdgpu_vcn        vcn;

Best Regards!
James zhu

  };

  int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2664bb2..2cde0b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1633,12 +1633,20 @@ static int vcn_v1_0_set_powergating_state(void *handle,
  * revisit this when there is a cleaner line between
  * the smc and the hw blocks
  */
+   int ret;
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;

+   if(state == adev->vcn.cur_state)
+   return 0;
+
 if (state == AMD_PG_STATE_GATE)
-   return vcn_v1_0_stop(adev);
+   ret = vcn_v1_0_stop(adev);
 else
-   return vcn_v1_0_start(adev);
+   ret = vcn_v1_0_start(adev);
+
+   if(!ret)
+   adev->vcn.cur_state = state;
+   return ret;
  }

  static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
--
2.7.4

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Re: [PATCH v2] drm/amdgpu:No action when VCN PG state is unchanged

[Alex Deucher]

On Thu, Sep 13, 2018 at 4:56 PM James Zhu  wrote:
>
> When VCN PG state is unchanged, it is unnecessary to reset power
> gate state
>
> Signed-off-by: James Zhu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 12 ++--
>  2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 0b0b863..d2219ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -69,6 +69,7 @@ struct amdgpu_vcn {
> struct amdgpu_ring  ring_jpeg;
> struct amdgpu_irq_src   irq;
> unsignednum_enc_rings;
> +   enum amd_powergating_state cur_state;

Does the default value (0) at init time properly reflect the default
powergating state?  If so,
Acked-by: Alex Deucher 

>  };
>
>  int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 2664bb2..2cde0b4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -1633,12 +1633,20 @@ static int vcn_v1_0_set_powergating_state(void 
> *handle,
>  * revisit this when there is a cleaner line between
>  * the smc and the hw blocks
>  */
> +   int ret;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> +   if(state == adev->vcn.cur_state)
> +   return 0;
> +
> if (state == AMD_PG_STATE_GATE)
> -   return vcn_v1_0_stop(adev);
> +   ret = vcn_v1_0_stop(adev);
> else
> -   return vcn_v1_0_start(adev);
> +   ret = vcn_v1_0_start(adev);
> +
> +   if(!ret)
> +   adev->vcn.cur_state = state;
> +   return ret;
>  }
>
>  static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
> --
> 2.7.4
>
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[pull] amdgpu/kfd, radeon, ttm, scheduler drm-next-4.20

[Alex Deucher]

Hi Dave,

This is a new pull for drm-next on top of last weeks with the following
changes:
- Fixed 64 bit divide
- Fixed vram type on vega20
- Misc vega20 fixes
- Misc DC fixes
- Fix GDS/GWS/OA domain handling

Previous changes from last week:
amdgpu/kfd:
- Picasso (new APU) support
- Raven2 (new APU) support
- Vega20 enablement
- ACP powergating improvements
- Add ABGR/XBGR display support
- VCN JPEG engine support
- Initial xGMI support
- Use load balancing for engine scheduling
- Lots of new documentation
- Rework and clean up i2c and aux handling in DC
- Add DP YCbCr 4:2:0 support in DC
- Add DMCU firmware loading for Raven (used for ABM and PSR)
- New debugfs features in DC
- LVDS support in DC
- Implement wave kill for gfx/compute (light weight reset for shaders)
- Use AGP aperture to avoid gart mappings when possible
- GPUVM performance improvements
- Bulk moves for more efficient GPUVM LRU handling
- Merge amdgpu and amdkfd into one module
- Enable gfxoff and stutter mode on Raven
- Misc cleanups

Scheduler:
- Load balancing support
- Bug fixes

ttm:
- Bulk move functionality
- Bug fixes

radeon:
- Misc cleanups

The following changes since commit 0957dc7097a3f462f6cedb45cf9b9785cc29e5bb:

  drm/amdgpu: revert "stop using gart_start as offset for the GTT domain" 
(2018-09-14 10:05:42 -0500)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.20

for you to fetch changes up to 846311ae68f3c78365ebf3dff505c99e7da861cf:

  drm/amdgpu: Exclude MM engines for vega20 virtual device (2018-09-19 22:32:29 
-0500)


A. Wilcox (1):
  drm/amdgpu: use processed values for counting

Charlene Liu (1):
  drm/amd/display: Fix 3D stereo issues.

Chiawen Huang (2):
  drm/amd/display: add aux i2c event log.
  drm/amd/display: add query HPD interface.

Christian König (15):
  drm/amdgpu: add amdgpu_vm_entries_mask v2
  drm/amdgpu: fix parameter documentation for amdgpu_vm_free_pts
  drm/amdgpu: add GDS, GWS and OA debugfs files
  drm/amdgpu: stop crashing on GDS/GWS/OA eviction
  drm/amdgpu: don't allocate zero sized kernel BOs
  drm/amdgpu: drop size check
  drm/amdgpu: remove fence fallback
  drm/amdgpu: stop pipelining VM PDs/PTs moves
  drm/amdgpu: always enable shadow BOs v2
  drm/amdgpu: shadow BOs don't need any alignment
  drm/amdgpu: always recover VRAM during GPU recovery
  drm/amdgpu: fix shadow BO restoring
  drm/amdgpu: fix up GDS/GWS/OA shifting
  drm/amdgpu: initialize GDS/GWS/OA domains even when they are zero sized
  drm/amdgpu: move reserving GDS/GWS/OA into common code

Dmytro Laktyushkin (1):
  drm/amd/display: stop using switch for different CS revisions

Evan Quan (3):
  drm/amd/powerplay: update OD feature judgement
  drm/amd/powerplay: update OD to take voltage value instead of offset
  drm/amd/powerplay: retrieve the updated clock table after OD

Frank Min (2):
  drm/amdgpu: add vega20 sriov capability detection
  drm/amdgpu: Exclude MM engines for vega20 virtual device

Hawking Zhang (2):
  drm/amdgpu: update vram_info structure in atomfirmware.h
  drm/amdgpu: fix unknown vram mem type for vega20

Leo Li (2):
  drm/amd/display: Drop amdgpu_display_manager.dal member
  drm/amd/display: Drop amdgpu_dm_prev_state struct

Mathieu Malaterre (1):
  drm/radeon: change function signature to pass full range

Tom St Denis (1):
  drm/amd/amdgpu: Avoid fault when allocating an empty buffer object

Tony Cheng (1):
  drm/amd/display: dc 3.1.66

 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c   |  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 119 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  |  56 
 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h|   7 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c|  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  14 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  81 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |   1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 125 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  37 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  |  28 --
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  32 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  35 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  15 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c |   6 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |   2 -
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |  11 -
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c   |   6 +-
 

Re: amdgpu fails compilation with CONFIG_FORTIFY_SOURCE

[Harry Wentland]

Thanks for the fix.

We've moved to logging functionality more closely aligned with the rest of DRM 
and dropped logger.c a while back.

Harry

On 2018-09-05 02:43 PM, Ján Kosterec wrote:
> amdgpu driver fails compilation when compiling with CONFIG_FORTIFY_SOURCE 
> kernel option:
>
> In function ‘memmove’,
> inlined from ‘append_entry’ at 
> drivers/gpu/drm/amd/amdgpu/../display/dc/basics/logger.c:258:2,
> inlined from ‘dm_logger_append_va.part.5’ at 
> drivers/gpu/drm/amd/amdgpu/../display/dc/basics/logger.c:349:4:
> ./include/linux/string.h:356:4: error: call to ‘__read_overflow2’ declared 
> with attribute error: detected read beyond size of object passed as 2nd 
> parameter
> __read_overflow2();
> ^~
>
> I have attached a patch which resolves this problem.
> Regards,
> Jan
>
>
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RE: [PATCH 1/3] drm/amd/pp: Avoid divide-by-zero in smu7_fan_ctrl_set_fan_speed_rpm

[Zhu, Rex]

Hi Alex and Evan,

For the fan control via sysfs,  I think we need to clarify the use case.

We support manual/auto fan control mode.

User can set the mode through pwm_enable. 1 mean manual. 2 mean auto
User can set fan speed via pwm1 and fan1_input.

For pwm1, user set the percentage value (0% - 100%)
And can get the pwm1's range via sysfs: pwm1_min, pwm1_max. the range is [0, 
255]. In driver, we transfer to [0% - 100%]

For fan1_input, user set the fan's resolution per minute
No way for user to get the range. On Tonga, the range is (0, 6000]. Not support 
zero-rpm on tonga.

Do we need to add new sysfs to expose the RPM range or just print the range in 
dmesg if user's setting is out of range?

Another question is:

Currently, the default fan control mode is auto.
When user change the fan speed via pwm1 or fan1_input, we switch to manual mode 
automatically.

So if user want to change back to auto fan control mode, they need to echo 2 to 
pwm_enable.

Best Regards
Rex


From: Deucher, Alexander
Sent: Thursday, September 20, 2018 9:52 PM
To: Zhu, Rex ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/amd/pp: Avoid divide-by-zero in 
smu7_fan_ctrl_set_fan_speed_rpm


Series is:

Reviewed-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>


From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Rex Zhu mailto:rex@amd.com>>
Sent: Thursday, September 20, 2018 3:14:25 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 1/3] drm/amd/pp: Avoid divide-by-zero in 
smu7_fan_ctrl_set_fan_speed_rpm

The minRPM speed maybe equal to zero. so need to check
input RPM not equal to 0, otherwise cause divide-by-zero driver crash.

Signed-off-by: Rex Zhu mailto:rex@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index 44527755..d61a9b4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -260,6 +260,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, 
uint32_t speed)
 if (hwmgr->thermal_controller.fanInfo.bNoFan ||
 (hwmgr->thermal_controller.fanInfo.
 ucTachometerPulsesPerRevolution == 0) ||
+   speed == 0 ||
 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
 (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
 return 0;
--
1.9.1

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Re: [PATCH v2] drm/amdgpu:No action when VCN PG state is unchanged

[Zhu, James]

Ping


Alex and Christian,


Could you give a review on this updated patch?


Thanks & Best Regards!


James Zhu



From: James Zhu 
Sent: Thursday, September 13, 2018 4:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James
Subject: [PATCH v2] drm/amdgpu:No action when VCN PG state is unchanged

When VCN PG state is unchanged, it is unnecessary to reset power
gate state

Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 12 ++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 0b0b863..d2219ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -69,6 +69,7 @@ struct amdgpu_vcn {
 struct amdgpu_ring  ring_jpeg;
 struct amdgpu_irq_src   irq;
 unsignednum_enc_rings;
+   enum amd_powergating_state cur_state;
 };

 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2664bb2..2cde0b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1633,12 +1633,20 @@ static int vcn_v1_0_set_powergating_state(void *handle,
  * revisit this when there is a cleaner line between
  * the smc and the hw blocks
  */
+   int ret;
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;

+   if(state == adev->vcn.cur_state)
+   return 0;
+
 if (state == AMD_PG_STATE_GATE)
-   return vcn_v1_0_stop(adev);
+   ret = vcn_v1_0_stop(adev);
 else
-   return vcn_v1_0_start(adev);
+   ret = vcn_v1_0_start(adev);
+
+   if(!ret)
+   adev->vcn.cur_state = state;
+   return ret;
 }

 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
--
2.7.4

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Re: [PATCH 1/4] drm/amdgpu: Halt rlc/cp in rlc_safe_mode

[Deucher, Alexander]

Series is:

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Thursday, September 20, 2018 6:07:28 AM
To: amd-gfx@lists.freedesktop.org; Zhou, Hang
Cc: Zhu, Rex
Subject: [PATCH 1/4] drm/amdgpu: Halt rlc/cp in rlc_safe_mode

before halt rlc/cp, need to
1. enter rlc safe mode
2. wait rlc/cp idle

Signed-off-by: Hang Zhou 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 86 ---
 1 file changed, 59 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 05b5bba..93d7fe5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5080,6 +5080,55 @@ static int gfx_v8_0_kcq_disable(struct amdgpu_device 
*adev)
 return r;
 }

+static bool gfx_v8_0_is_idle(void *handle)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
+   || RREG32(mmGRBM_STATUS2) != 0x8)
+   return false;
+   else
+   return true;
+}
+
+static bool gfx_v8_0_rlc_is_idle(void *handle)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   if (RREG32(mmGRBM_STATUS2) != 0x8)
+   return false;
+   else
+   return true;
+}
+
+static int gfx_v8_0_wait_for_rlc_idle(void *handle)
+{
+   unsigned int i;
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   for (i = 0; i < adev->usec_timeout; i++) {
+   if (gfx_v8_0_rlc_is_idle(handle))
+   return 0;
+
+   udelay(1);
+   }
+   return -ETIMEDOUT;
+}
+
+static int gfx_v8_0_wait_for_idle(void *handle)
+{
+   unsigned int i;
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   for (i = 0; i < adev->usec_timeout; i++) {
+   if (gfx_v8_0_is_idle(handle))
+   return 0;
+
+   udelay(1);
+   }
+   return -ETIMEDOUT;
+}
+
 static int gfx_v8_0_hw_fini(void *handle)
 {
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -5098,9 +5147,16 @@ static int gfx_v8_0_hw_fini(void *handle)
 pr_debug("For SRIOV client, shouldn't do anything.\n");
 return 0;
 }
-   gfx_v8_0_cp_enable(adev, false);
-   gfx_v8_0_rlc_stop(adev);
-
+   adev->gfx.rlc.funcs->enter_safe_mode(adev);
+   if (!gfx_v8_0_wait_for_idle(adev))
+   gfx_v8_0_cp_enable(adev, false);
+   else
+   pr_err("cp is busy, skip halt cp\n");
+   if (!gfx_v8_0_wait_for_rlc_idle(adev))
+   gfx_v8_0_rlc_stop(adev);
+   else
+   pr_err("rlc is busy, skip halt rlc\n");
+   adev->gfx.rlc.funcs->exit_safe_mode(adev);
 return 0;
 }

@@ -5121,30 +5177,6 @@ static int gfx_v8_0_resume(void *handle)
 return r;
 }

-static bool gfx_v8_0_is_idle(void *handle)
-{
-   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-   if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
-   return false;
-   else
-   return true;
-}
-
-static int gfx_v8_0_wait_for_idle(void *handle)
-{
-   unsigned i;
-   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-   for (i = 0; i < adev->usec_timeout; i++) {
-   if (gfx_v8_0_is_idle(handle))
-   return 0;
-
-   udelay(1);
-   }
-   return -ETIMEDOUT;
-}
-
 static bool gfx_v8_0_check_soft_reset(void *handle)
 {
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
1.9.1

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Re: [PATCH 1/3] drm/amd/pp: Avoid divide-by-zero in smu7_fan_ctrl_set_fan_speed_rpm

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Thursday, September 20, 2018 3:14:25 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 1/3] drm/amd/pp: Avoid divide-by-zero in 
smu7_fan_ctrl_set_fan_speed_rpm

The minRPM speed maybe equal to zero. so need to check
input RPM not equal to 0, otherwise cause divide-by-zero driver crash.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index 44527755..d61a9b4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -260,6 +260,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, 
uint32_t speed)
 if (hwmgr->thermal_controller.fanInfo.bNoFan ||
 (hwmgr->thermal_controller.fanInfo.
 ucTachometerPulsesPerRevolution == 0) ||
+   speed == 0 ||
 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
 (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
 return 0;
--
1.9.1

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Re: [PATCH 3/6] drm: add support of syncobj timeline point wait v2

[Christian König]

Am 20.09.2018 um 13:03 schrieb Chunming Zhou:

points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.

Signed-off-by: Chunming Zhou 
---
  drivers/gpu/drm/drm_internal.h |  2 +
  drivers/gpu/drm/drm_ioctl.c|  2 +
  drivers/gpu/drm/drm_syncobj.c  | 99 +-
  include/uapi/drm/drm.h | 14 +
  4 files changed, 103 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 0c4eb4a9ab31..566d44e3c782 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -183,6 +183,8 @@ int drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, 
void *data,
   struct drm_file *file_private);
  int drm_syncobj_wait_ioctl(struct drm_device *dev, void *data,
   struct drm_file *file_private);
+int drm_syncobj_timeline_wait_ioctl(struct drm_device *dev, void *data,
+   struct drm_file *file_private);
  int drm_syncobj_reset_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_private);
  int drm_syncobj_signal_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 6b4a633b4240..c0891614f516 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -669,6 +669,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_WAIT, drm_syncobj_wait_ioctl,
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
+   DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT, 
drm_syncobj_timeline_wait_ioctl,
+ DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_RESET, drm_syncobj_reset_ioctl,
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_SIGNAL, drm_syncobj_signal_ioctl,
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 67472bd77c83..a43de0e4616c 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -126,13 +126,14 @@ static void drm_syncobj_add_callback_locked(struct 
drm_syncobj *syncobj,
  }
  
  static int drm_syncobj_fence_get_or_add_callback(struct drm_syncobj *syncobj,

+u64 point,
 struct dma_fence **fence,
 struct drm_syncobj_cb *cb,
 drm_syncobj_func_t func)
  {
int ret;
  
-	ret = drm_syncobj_search_fence(syncobj, 0, 0, fence);

+   ret = drm_syncobj_search_fence(syncobj, point, 0, fence);
if (!ret)
return 1;
  
@@ -143,7 +144,7 @@ static int drm_syncobj_fence_get_or_add_callback(struct drm_syncobj *syncobj,

 */
if (!list_empty(>signal_pt_list)) {
spin_unlock(>lock);
-   drm_syncobj_search_fence(syncobj, 0, 0, fence);
+   drm_syncobj_search_fence(syncobj, point, 0, fence);
if (*fence)
return 1;
spin_lock(>lock);
@@ -358,7 +359,9 @@ void drm_syncobj_replace_fence(struct drm_syncobj *syncobj,
spin_lock(>lock);
list_for_each_entry_safe(cur, tmp, >cb_list, node) {
list_del_init(>node);
+   spin_unlock(>lock);
cur->func(syncobj, cur);
+   spin_lock(>lock);


That looks fishy to me. Why do we need to unlock and who guarantees that 
tmp is still valid when we grab the lock again?


Apart from that can't see anything obvious wrong, but I certainly need 
to take a closer look.


Christian.


}
spin_unlock(>lock);
}
@@ -856,6 +859,7 @@ struct syncobj_wait_entry {
struct dma_fence *fence;
struct dma_fence_cb fence_cb;
struct drm_syncobj_cb syncobj_cb;
+   u64point;
  };
  
  static void syncobj_wait_fence_func(struct dma_fence *fence,

@@ -873,12 +877,13 @@ static void syncobj_wait_syncobj_func(struct drm_syncobj 
*syncobj,
struct syncobj_wait_entry *wait =
container_of(cb, struct syncobj_wait_entry, syncobj_cb);
  
-	drm_syncobj_search_fence(syncobj, 0, 0, >fence);

+   drm_syncobj_search_fence(syncobj, wait->point, 0, >fence);
  
  	wake_up_process(wait->task);

  }
  
  static signed long drm_syncobj_array_wait_timeout(struct drm_syncobj **syncobjs,

+ void __user *user_points,
  uint32_t count,
  uint32_t flags,
  signed long timeout,
@@ -886,13 +891,27 @@ static signed 

Re: [PATCH 2/6] drm: add syncobj timeline support v8

[Christian König]

Am 20.09.2018 um 13:03 schrieb Chunming Zhou:

This patch is for VK_KHR_timeline_semaphore extension, semaphore is called 
syncobj in kernel side:
This extension introduces a new type of syncobj that has an integer payload
identifying a point in a timeline. Such timeline syncobjs support the
following operations:
* CPU query - A host operation that allows querying the payload of the
  timeline syncobj.
* CPU wait - A host operation that allows a blocking wait for a
  timeline syncobj to reach a specified value.
* Device wait - A device operation that allows waiting for a
  timeline syncobj to reach a specified value.
* Device signal - A device operation that allows advancing the
  timeline syncobj to a specified value.

v1:
Since it's a timeline, that means the front time point(PT) always is signaled 
before the late PT.
a. signal PT design:
Signal PT fence N depends on PT[N-1] fence and signal opertion fence, when 
PT[N] fence is signaled,
the timeline will increase to value of PT[N].
b. wait PT design:
Wait PT fence is signaled by reaching timeline point value, when timeline is 
increasing, will compare
wait PTs value with new timeline value, if PT value is lower than timeline 
value, then wait PT will be
signaled, otherwise keep in list. syncobj wait operation can wait on any point 
of timeline,
so need a RB tree to order them. And wait PT could ahead of signal PT, we need 
a sumission fence to
perform that.

v2:
1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian)
2. move unexposed denitions to .c file. (Daniel Vetter)
3. split up the change to drm_syncobj_find_fence() in a separate patch. 
(Christian)
4. split up the change to drm_syncobj_replace_fence() in a separate patch.
5. drop the submission_fence implementation and instead use wait_event() for 
that. (Christian)
6. WARN_ON(point != 0) for NORMAL type syncobj case. (Daniel Vetter)

v3:
1. replace normal syncobj with timeline implemenation. (Vetter and Christian)
 a. normal syncobj signal op will create a signal PT to tail of signal pt 
list.
 b. normal syncobj wait op will create a wait pt with last signal point, 
and this wait PT is only signaled by related signal point PT.
2. many bug fix and clean up
3. stub fence moving is moved to other patch.

v4：
1. fix RB tree loop with while(node=rb_first(...)). (Christian)
2. fix syncobj lifecycle. (Christian)
3. only enable_signaling when there is wait_pt. (Christian)
4. fix timeline path issues.
5. write a timeline test in libdrm

v5: (Christian)
1. semaphore is called syncobj in kernel side.
2. don't need 'timeline' characters in some function name.
3. keep syncobj cb.

v6: (Christian)
1. merge syncobj_timeline to syncobj structure.
2. simplify some check sentences.
3. some misc change.
4. fix CTS failed issue.

v7: (Christian)
1. error handling when creating signal pt.
2. remove timeline naming in func.
3. export flags in find_fence.
4. allow reset timeline.

v8:
1. use wait_event_interruptible without timeout
2. rename _TYPE_INDIVIDUAL to _TYPE_BINARY

individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore*
timeline syncobj is tested by ./amdgpu_test -s 9

Signed-off-by: Chunming Zhou 
Cc: Christian Konig 
Cc: Dave Airlie 
Cc: Daniel Rakos 
Cc: Daniel Vetter 


A few more function comments would be nice to have, but that can also 
come later.


Reviewed-by: Christian König  for now.

Thanks for the hard work,
Christian.


---
  drivers/gpu/drm/drm_syncobj.c  | 287 ++---
  drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +-
  include/drm/drm_syncobj.h  |  65 ++---
  include/uapi/drm/drm.h |   1 +
  4 files changed, 281 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index f796c9fc3858..67472bd77c83 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -56,6 +56,9 @@
  #include "drm_internal.h"
  #include 
  
+/* merge normal syncobj to timeline syncobj, the point interval is 1 */

+#define DRM_SYNCOBJ_BINARY_POINT 1
+
  struct drm_syncobj_stub_fence {
struct dma_fence base;
spinlock_t lock;
@@ -82,6 +85,11 @@ static const struct dma_fence_ops drm_syncobj_stub_fence_ops 
= {
.release = drm_syncobj_stub_fence_release,
  };
  
+struct drm_syncobj_signal_pt {

+   struct dma_fence_array *base;
+   u64value;
+   struct list_head list;
+};
  
  /**

   * drm_syncobj_find - lookup and reference a sync object.
@@ -124,8 +132,8 @@ static int drm_syncobj_fence_get_or_add_callback(struct 
drm_syncobj *syncobj,
  {
int ret;
  
-	*fence = drm_syncobj_fence_get(syncobj);

-   if (*fence)
+   ret = drm_syncobj_search_fence(syncobj, 0, 0, fence);
+   if (!ret)
return 1;
  
  	spin_lock(>lock);

@@ -133,10 +141,12 @@ static int drm_syncobj_fence_get_or_add_callback(struct 
drm_syncobj *syncobj,
 * have the lock, try one more 

[PATCH 4/6] drm: add timeline syncobj payload query ioctl

[Chunming Zhou]

user mode can query timeline payload.

Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/drm_internal.h |  2 ++
 drivers/gpu/drm/drm_ioctl.c|  2 ++
 drivers/gpu/drm/drm_syncobj.c  | 53 ++
 include/uapi/drm/drm.h | 11 +++
 4 files changed, 68 insertions(+)

diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 566d44e3c782..9c4826411a3c 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -189,6 +189,8 @@ int drm_syncobj_reset_ioctl(struct drm_device *dev, void 
*data,
struct drm_file *file_private);
 int drm_syncobj_signal_ioctl(struct drm_device *dev, void *data,
 struct drm_file *file_private);
+int drm_syncobj_query_ioctl(struct drm_device *dev, void *data,
+   struct drm_file *file_private);
 
 /* drm_framebuffer.c */
 void drm_framebuffer_print_info(struct drm_printer *p, unsigned int indent,
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index c0891614f516..c3c0617e6372 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -675,6 +675,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_SIGNAL, drm_syncobj_signal_ioctl,
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
+   DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_QUERY, drm_syncobj_query_ioctl,
+ DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_CRTC_GET_SEQUENCE, drm_crtc_get_sequence_ioctl, 
DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_CRTC_QUEUE_SEQUENCE, 
drm_crtc_queue_sequence_ioctl, DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_LEASE, drm_mode_create_lease_ioctl, 
DRM_MASTER|DRM_UNLOCKED),
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index a43de0e4616c..e998fc319f9f 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -1289,3 +1289,56 @@ drm_syncobj_signal_ioctl(struct drm_device *dev, void 
*data,
 
return ret;
 }
+
+static void drm_syncobj_timeline_query_payload(struct drm_syncobj *syncobj,
+  uint64_t *point)
+{
+   if (syncobj->type != DRM_SYNCOBJ_TYPE_TIMELINE) {
+   DRM_ERROR("Normal syncobj cann't be queried!");
+   *point = 0;
+   return;
+   }
+   *point = syncobj->signal_point;
+}
+
+int drm_syncobj_query_ioctl(struct drm_device *dev, void *data,
+   struct drm_file *file_private)
+{
+   struct drm_syncobj_timeline_query *args = data;
+   struct drm_syncobj **syncobjs;
+   uint64_t *points;
+   uint32_t i;
+   int ret;
+
+   if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+   return -ENODEV;
+
+   if (args->count_handles == 0)
+   return -EINVAL;
+
+   ret = drm_syncobj_array_find(file_private,
+u64_to_user_ptr(args->handles),
+args->count_handles,
+);
+   if (ret < 0)
+   return ret;
+
+
+   points = kmalloc_array(args->count_handles, sizeof(*points),
+  GFP_KERNEL);
+   if (points == NULL) {
+   ret = -ENOMEM;
+   goto out;
+   }
+   for (i = 0; i < args->count_handles; i++) {
+   drm_syncobj_timeline_query_payload(syncobjs[i], [i]);
+   copy_to_user(u64_to_user_ptr(args->points), points,
+sizeof(uint64_t) * args->count_handles);
+   }
+
+   kfree(points);
+out:
+   drm_syncobj_array_free(syncobjs, args->count_handles);
+
+   return ret;
+}
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 501e86d81f47..188b63f1975b 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -767,6 +767,15 @@ struct drm_syncobj_array {
__u32 pad;
 };
 
+struct drm_syncobj_timeline_query {
+   __u64 handles;
+   /* points are timeline syncobjs payloads returned by query ioctl */
+   __u64 points;
+   __u32 count_handles;
+   __u32 pad;
+};
+
+
 /* Query current scanout sequence number */
 struct drm_crtc_get_sequence {
__u32 crtc_id;  /* requested crtc_id */
@@ -924,6 +933,8 @@ extern "C" {
 #define DRM_IOCTL_MODE_REVOKE_LEASEDRM_IOWR(0xC9, struct 
drm_mode_revoke_lease)
 
 #define DRM_IOCTL_SYNCOBJ_TIMELINE_WAITDRM_IOWR(0xCA, struct 
drm_syncobj_timeline_wait)
+#define DRM_IOCTL_SYNCOBJ_QUERYDRM_IOWR(0xCB, struct 
drm_syncobj_timeline_query)
+
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x9f.
-- 
2.17.1

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[PATCH 6/6] drm/amdgpu: update version for timeline syncobj support in amdgpu

[Chunming Zhou]

Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6870909da926..58cba492ba55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -70,9 +70,10 @@
  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
  * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
  * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
+ * - 3.28.0 - Add syncobj timeline support to AMDGPU_CS.
  */
 #define KMS_DRIVER_MAJOR   3
-#define KMS_DRIVER_MINOR   27
+#define KMS_DRIVER_MINOR   28
 #define KMS_DRIVER_PATCHLEVEL  0
 
 int amdgpu_vram_limit = 0;
-- 
2.17.1

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[PATCH 3/6] drm: add support of syncobj timeline point wait v2

[Chunming Zhou]

points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.

Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/drm_internal.h |  2 +
 drivers/gpu/drm/drm_ioctl.c|  2 +
 drivers/gpu/drm/drm_syncobj.c  | 99 +-
 include/uapi/drm/drm.h | 14 +
 4 files changed, 103 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 0c4eb4a9ab31..566d44e3c782 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -183,6 +183,8 @@ int drm_syncobj_fd_to_handle_ioctl(struct drm_device *dev, 
void *data,
   struct drm_file *file_private);
 int drm_syncobj_wait_ioctl(struct drm_device *dev, void *data,
   struct drm_file *file_private);
+int drm_syncobj_timeline_wait_ioctl(struct drm_device *dev, void *data,
+   struct drm_file *file_private);
 int drm_syncobj_reset_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_private);
 int drm_syncobj_signal_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 6b4a633b4240..c0891614f516 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -669,6 +669,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_WAIT, drm_syncobj_wait_ioctl,
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
+   DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT, 
drm_syncobj_timeline_wait_ioctl,
+ DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_RESET, drm_syncobj_reset_ioctl,
  DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_SIGNAL, drm_syncobj_signal_ioctl,
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 67472bd77c83..a43de0e4616c 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -126,13 +126,14 @@ static void drm_syncobj_add_callback_locked(struct 
drm_syncobj *syncobj,
 }
 
 static int drm_syncobj_fence_get_or_add_callback(struct drm_syncobj *syncobj,
+u64 point,
 struct dma_fence **fence,
 struct drm_syncobj_cb *cb,
 drm_syncobj_func_t func)
 {
int ret;
 
-   ret = drm_syncobj_search_fence(syncobj, 0, 0, fence);
+   ret = drm_syncobj_search_fence(syncobj, point, 0, fence);
if (!ret)
return 1;
 
@@ -143,7 +144,7 @@ static int drm_syncobj_fence_get_or_add_callback(struct 
drm_syncobj *syncobj,
 */
if (!list_empty(>signal_pt_list)) {
spin_unlock(>lock);
-   drm_syncobj_search_fence(syncobj, 0, 0, fence);
+   drm_syncobj_search_fence(syncobj, point, 0, fence);
if (*fence)
return 1;
spin_lock(>lock);
@@ -358,7 +359,9 @@ void drm_syncobj_replace_fence(struct drm_syncobj *syncobj,
spin_lock(>lock);
list_for_each_entry_safe(cur, tmp, >cb_list, node) {
list_del_init(>node);
+   spin_unlock(>lock);
cur->func(syncobj, cur);
+   spin_lock(>lock);
}
spin_unlock(>lock);
}
@@ -856,6 +859,7 @@ struct syncobj_wait_entry {
struct dma_fence *fence;
struct dma_fence_cb fence_cb;
struct drm_syncobj_cb syncobj_cb;
+   u64point;
 };
 
 static void syncobj_wait_fence_func(struct dma_fence *fence,
@@ -873,12 +877,13 @@ static void syncobj_wait_syncobj_func(struct drm_syncobj 
*syncobj,
struct syncobj_wait_entry *wait =
container_of(cb, struct syncobj_wait_entry, syncobj_cb);
 
-   drm_syncobj_search_fence(syncobj, 0, 0, >fence);
+   drm_syncobj_search_fence(syncobj, wait->point, 0, >fence);
 
wake_up_process(wait->task);
 }
 
 static signed long drm_syncobj_array_wait_timeout(struct drm_syncobj 
**syncobjs,
+ void __user *user_points,
  uint32_t count,
  uint32_t flags,
  signed long timeout,
@@ -886,13 +891,27 @@ static signed long drm_syncobj_array_wait_timeout(struct 
drm_syncobj **syncobjs,
 {
struct syncobj_wait_entry *entries;
struct dma_fence *fence;
+   uint64_t *points;
signed long ret;
uint32_t signaled_count, i;
 
-   entries = kcalloc(count, sizeof(*entries), 

Re: [PATCH 1/6] drm: add flags to drm_syncobj_find_fence

[Christian König]

Am 20.09.2018 um 13:03 schrieb Chunming Zhou:

flags can be used by driver to decide whether need to block wait submission.

Signed-off-by: Chunming Zhou 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
  drivers/gpu/drm/drm_syncobj.c  | 4 ++--
  drivers/gpu/drm/v3d/v3d_gem.c  | 4 ++--
  drivers/gpu/drm/vc4/vc4_gem.c  | 2 +-
  include/drm/drm_syncobj.h  | 2 +-
  5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d9d2ede96490..412fac238575 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1102,7 +1102,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct 
amdgpu_cs_parser *p,
  {
int r;
struct dma_fence *fence;
-   r = drm_syncobj_find_fence(p->filp, handle, 0, );
+   r = drm_syncobj_find_fence(p->filp, handle, 0, 0, );
if (r)
return r;
  
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c

index e9ce623d049e..f796c9fc3858 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -235,7 +235,7 @@ static int drm_syncobj_assign_null_handle(struct 
drm_syncobj *syncobj)
   * dma_fence_put().
   */
  int drm_syncobj_find_fence(struct drm_file *file_private,
-  u32 handle, u64 point,
+  u32 handle, u64 point, u64 flags,
   struct dma_fence **fence)
  {
struct drm_syncobj *syncobj = drm_syncobj_find(file_private, handle);
@@ -506,7 +506,7 @@ static int drm_syncobj_export_sync_file(struct drm_file 
*file_private,
if (fd < 0)
return fd;
  
-	ret = drm_syncobj_find_fence(file_private, handle, 0, );

+   ret = drm_syncobj_find_fence(file_private, handle, 0, 0, );
if (ret)
goto err_put_fd;
  
diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c

index 70c54774400b..97477879d3d4 100644
--- a/drivers/gpu/drm/v3d/v3d_gem.c
+++ b/drivers/gpu/drm/v3d/v3d_gem.c
@@ -521,12 +521,12 @@ v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
kref_init(>refcount);
  
  	ret = drm_syncobj_find_fence(file_priv, args->in_sync_bcl,

-0, >bin.in_fence);
+0, 0, >bin.in_fence);
if (ret == -EINVAL)
goto fail;
  
  	ret = drm_syncobj_find_fence(file_priv, args->in_sync_rcl,

-0, >render.in_fence);
+0, 0, >render.in_fence);
if (ret == -EINVAL)
goto fail;
  
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c

index 5b22e996af6c..251198194c38 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -1173,7 +1173,7 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
  
  	if (args->in_sync) {

ret = drm_syncobj_find_fence(file_priv, args->in_sync,
-0, _fence);
+0, 0, _fence);
if (ret)
goto fail;
  
diff --git a/include/drm/drm_syncobj.h b/include/drm/drm_syncobj.h

index 425432b85a87..2eda44def639 100644
--- a/include/drm/drm_syncobj.h
+++ b/include/drm/drm_syncobj.h
@@ -134,7 +134,7 @@ struct drm_syncobj *drm_syncobj_find(struct drm_file 
*file_private,
  void drm_syncobj_replace_fence(struct drm_syncobj *syncobj, u64 point,
   struct dma_fence *fence);
  int drm_syncobj_find_fence(struct drm_file *file_private,
-  u32 handle, u64 point,
+  u32 handle, u64 point, u64 flags,
   struct dma_fence **fence);
  void drm_syncobj_free(struct kref *kref);
  int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,


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[PATCH 5/6] drm/amdgpu: add timeline support in amdgpu CS

[Chunming Zhou]

syncobj wait/signal operation is appending in command submission.

Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 114 +++--
 include/uapi/drm/amdgpu_drm.h  |  10 +++
 3 files changed, 104 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 447c4c7a36d6..6e4a3db56833 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -975,6 +975,11 @@ struct amdgpu_cs_chunk {
void*kdata;
 };
 
+struct amdgpu_cs_syncobj_post_dep {
+   struct drm_syncobj *post_dep_syncobj;
+   u64 point;
+};
+
 struct amdgpu_cs_parser {
struct amdgpu_device*adev;
struct drm_file *filp;
@@ -1003,9 +1008,8 @@ struct amdgpu_cs_parser {
 
/* user fence */
struct amdgpu_bo_list_entry uf_entry;
-
+   struct amdgpu_cs_syncobj_post_dep *post_dep_syncobjs;
unsigned num_post_dep_syncobjs;
-   struct drm_syncobj **post_dep_syncobjs;
 };
 
 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 412fac238575..0efe75bf2f03 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -204,6 +204,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser 
*p, union drm_amdgpu_cs
case AMDGPU_CHUNK_ID_DEPENDENCIES:
case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
+   case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
+   case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
break;
 
default:
@@ -783,7 +785,7 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser 
*parser, int error,
   >validated);
 
for (i = 0; i < parser->num_post_dep_syncobjs; i++)
-   drm_syncobj_put(parser->post_dep_syncobjs[i]);
+   drm_syncobj_put(parser->post_dep_syncobjs[i].post_dep_syncobj);
kfree(parser->post_dep_syncobjs);
 
dma_fence_put(parser->fence);
@@ -1098,11 +1100,13 @@ static int amdgpu_cs_process_fence_dep(struct 
amdgpu_cs_parser *p,
 }
 
 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
-uint32_t handle)
+uint32_t handle, u64 point,
+u64 flags)
 {
int r;
struct dma_fence *fence;
-   r = drm_syncobj_find_fence(p->filp, handle, 0, 0, );
+
+   r = drm_syncobj_find_fence(p->filp, handle, point, flags, );
if (r)
return r;
 
@@ -1113,48 +1117,91 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct 
amdgpu_cs_parser *p,
 }
 
 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
-   struct amdgpu_cs_chunk *chunk)
+   struct amdgpu_cs_chunk *chunk,
+   bool timeline)
 {
unsigned num_deps;
int i, r;
-   struct drm_amdgpu_cs_chunk_sem *deps;
 
-   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
-   num_deps = chunk->length_dw * 4 /
-   sizeof(struct drm_amdgpu_cs_chunk_sem);
+   if (!timeline) {
+   struct drm_amdgpu_cs_chunk_sem *deps;
 
-   for (i = 0; i < num_deps; ++i) {
-   r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
+   deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_sem);
+   for (i = 0; i < num_deps; ++i) {
+   r = amdgpu_syncobj_lookup_and_add_to_sync(p, 
deps[i].handle,
+ 0, 0);
if (r)
return r;
+   }
+   } else {
+   struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
+
+   syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj 
*)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_syncobj);
+   for (i = 0; i < num_deps; ++i) {
+   r = amdgpu_syncobj_lookup_and_add_to_sync(p, 
syncobj_deps[i].handle,
+ 
syncobj_deps[i].point,
+ 
syncobj_deps[i].flags);
+   if (r)
+   return r;
+   }
}
+
return 0;
 }
 
 static int amdgpu_cs_process_syncobj_out_dep(struct 

[PATCH 2/6] drm: add syncobj timeline support v8

[Chunming Zhou]

This patch is for VK_KHR_timeline_semaphore extension, semaphore is called 
syncobj in kernel side:
This extension introduces a new type of syncobj that has an integer payload
identifying a point in a timeline. Such timeline syncobjs support the
following operations:
   * CPU query - A host operation that allows querying the payload of the
 timeline syncobj.
   * CPU wait - A host operation that allows a blocking wait for a
 timeline syncobj to reach a specified value.
   * Device wait - A device operation that allows waiting for a
 timeline syncobj to reach a specified value.
   * Device signal - A device operation that allows advancing the
 timeline syncobj to a specified value.

v1:
Since it's a timeline, that means the front time point(PT) always is signaled 
before the late PT.
a. signal PT design:
Signal PT fence N depends on PT[N-1] fence and signal opertion fence, when 
PT[N] fence is signaled,
the timeline will increase to value of PT[N].
b. wait PT design:
Wait PT fence is signaled by reaching timeline point value, when timeline is 
increasing, will compare
wait PTs value with new timeline value, if PT value is lower than timeline 
value, then wait PT will be
signaled, otherwise keep in list. syncobj wait operation can wait on any point 
of timeline,
so need a RB tree to order them. And wait PT could ahead of signal PT, we need 
a sumission fence to
perform that.

v2:
1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian)
2. move unexposed denitions to .c file. (Daniel Vetter)
3. split up the change to drm_syncobj_find_fence() in a separate patch. 
(Christian)
4. split up the change to drm_syncobj_replace_fence() in a separate patch.
5. drop the submission_fence implementation and instead use wait_event() for 
that. (Christian)
6. WARN_ON(point != 0) for NORMAL type syncobj case. (Daniel Vetter)

v3:
1. replace normal syncobj with timeline implemenation. (Vetter and Christian)
a. normal syncobj signal op will create a signal PT to tail of signal pt 
list.
b. normal syncobj wait op will create a wait pt with last signal point, and 
this wait PT is only signaled by related signal point PT.
2. many bug fix and clean up
3. stub fence moving is moved to other patch.

v4：
1. fix RB tree loop with while(node=rb_first(...)). (Christian)
2. fix syncobj lifecycle. (Christian)
3. only enable_signaling when there is wait_pt. (Christian)
4. fix timeline path issues.
5. write a timeline test in libdrm

v5: (Christian)
1. semaphore is called syncobj in kernel side.
2. don't need 'timeline' characters in some function name.
3. keep syncobj cb.

v6: (Christian)
1. merge syncobj_timeline to syncobj structure.
2. simplify some check sentences.
3. some misc change.
4. fix CTS failed issue.

v7: (Christian)
1. error handling when creating signal pt.
2. remove timeline naming in func.
3. export flags in find_fence.
4. allow reset timeline.

v8:
1. use wait_event_interruptible without timeout
2. rename _TYPE_INDIVIDUAL to _TYPE_BINARY

individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore*
timeline syncobj is tested by ./amdgpu_test -s 9

Signed-off-by: Chunming Zhou 
Cc: Christian Konig 
Cc: Dave Airlie 
Cc: Daniel Rakos 
Cc: Daniel Vetter 
---
 drivers/gpu/drm/drm_syncobj.c  | 287 ++---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +-
 include/drm/drm_syncobj.h  |  65 ++---
 include/uapi/drm/drm.h |   1 +
 4 files changed, 281 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index f796c9fc3858..67472bd77c83 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -56,6 +56,9 @@
 #include "drm_internal.h"
 #include 
 
+/* merge normal syncobj to timeline syncobj, the point interval is 1 */
+#define DRM_SYNCOBJ_BINARY_POINT 1
+
 struct drm_syncobj_stub_fence {
struct dma_fence base;
spinlock_t lock;
@@ -82,6 +85,11 @@ static const struct dma_fence_ops drm_syncobj_stub_fence_ops 
= {
.release = drm_syncobj_stub_fence_release,
 };
 
+struct drm_syncobj_signal_pt {
+   struct dma_fence_array *base;
+   u64value;
+   struct list_head list;
+};
 
 /**
  * drm_syncobj_find - lookup and reference a sync object.
@@ -124,8 +132,8 @@ static int drm_syncobj_fence_get_or_add_callback(struct 
drm_syncobj *syncobj,
 {
int ret;
 
-   *fence = drm_syncobj_fence_get(syncobj);
-   if (*fence)
+   ret = drm_syncobj_search_fence(syncobj, 0, 0, fence);
+   if (!ret)
return 1;
 
spin_lock(>lock);
@@ -133,10 +141,12 @@ static int drm_syncobj_fence_get_or_add_callback(struct 
drm_syncobj *syncobj,
 * have the lock, try one more time just to be sure we don't add a
 * callback when a fence has already been set.
 */
-   if (syncobj->fence) {
-   *fence = dma_fence_get(rcu_dereference_protected(syncobj->fence,
-   

[PATCH 1/6] drm: add flags to drm_syncobj_find_fence

[Chunming Zhou]

flags can be used by driver to decide whether need to block wait submission.

Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
 drivers/gpu/drm/drm_syncobj.c  | 4 ++--
 drivers/gpu/drm/v3d/v3d_gem.c  | 4 ++--
 drivers/gpu/drm/vc4/vc4_gem.c  | 2 +-
 include/drm/drm_syncobj.h  | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d9d2ede96490..412fac238575 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1102,7 +1102,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct 
amdgpu_cs_parser *p,
 {
int r;
struct dma_fence *fence;
-   r = drm_syncobj_find_fence(p->filp, handle, 0, );
+   r = drm_syncobj_find_fence(p->filp, handle, 0, 0, );
if (r)
return r;
 
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index e9ce623d049e..f796c9fc3858 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -235,7 +235,7 @@ static int drm_syncobj_assign_null_handle(struct 
drm_syncobj *syncobj)
  * dma_fence_put().
  */
 int drm_syncobj_find_fence(struct drm_file *file_private,
-  u32 handle, u64 point,
+  u32 handle, u64 point, u64 flags,
   struct dma_fence **fence)
 {
struct drm_syncobj *syncobj = drm_syncobj_find(file_private, handle);
@@ -506,7 +506,7 @@ static int drm_syncobj_export_sync_file(struct drm_file 
*file_private,
if (fd < 0)
return fd;
 
-   ret = drm_syncobj_find_fence(file_private, handle, 0, );
+   ret = drm_syncobj_find_fence(file_private, handle, 0, 0, );
if (ret)
goto err_put_fd;
 
diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
index 70c54774400b..97477879d3d4 100644
--- a/drivers/gpu/drm/v3d/v3d_gem.c
+++ b/drivers/gpu/drm/v3d/v3d_gem.c
@@ -521,12 +521,12 @@ v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
kref_init(>refcount);
 
ret = drm_syncobj_find_fence(file_priv, args->in_sync_bcl,
-0, >bin.in_fence);
+0, 0, >bin.in_fence);
if (ret == -EINVAL)
goto fail;
 
ret = drm_syncobj_find_fence(file_priv, args->in_sync_rcl,
-0, >render.in_fence);
+0, 0, >render.in_fence);
if (ret == -EINVAL)
goto fail;
 
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
index 5b22e996af6c..251198194c38 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -1173,7 +1173,7 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
 
if (args->in_sync) {
ret = drm_syncobj_find_fence(file_priv, args->in_sync,
-0, _fence);
+0, 0, _fence);
if (ret)
goto fail;
 
diff --git a/include/drm/drm_syncobj.h b/include/drm/drm_syncobj.h
index 425432b85a87..2eda44def639 100644
--- a/include/drm/drm_syncobj.h
+++ b/include/drm/drm_syncobj.h
@@ -134,7 +134,7 @@ struct drm_syncobj *drm_syncobj_find(struct drm_file 
*file_private,
 void drm_syncobj_replace_fence(struct drm_syncobj *syncobj, u64 point,
   struct dma_fence *fence);
 int drm_syncobj_find_fence(struct drm_file *file_private,
-  u32 handle, u64 point,
+  u32 handle, u64 point, u64 flags,
   struct dma_fence **fence);
 void drm_syncobj_free(struct kref *kref);
 int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
-- 
2.17.1

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[PATCH 4/4] drm/amdgpu: Change the gfx/sdma init/fini sequence

[Rex Zhu]

initialize gfx/sdma before dpm features enabled.
and disable dpm features before gfx/sdma fini.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/cik.c  | 17 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +--
 drivers/gpu/drm/amd/amdgpu/si.c   | 13 +++--
 drivers/gpu/drm/amd/amdgpu/soc15.c|  8 
 drivers/gpu/drm/amd/amdgpu/vi.c   | 24 
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 16 +---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   | 18 --
 7 files changed, 54 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 78ab939..f41f5f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2002,6 +2002,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _v7_2_ip_block);
+   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
if (amdgpu_dpm == -1)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
else
@@ -2014,8 +2016,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
 #endif
else
amdgpu_device_ip_block_add(adev, _v8_2_ip_block);
-   amdgpu_device_ip_block_add(adev, _v7_2_ip_block);
-   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
amdgpu_device_ip_block_add(adev, _v4_2_ip_block);
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
break;
@@ -2023,6 +2023,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _v7_3_ip_block);
+   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
if (amdgpu_dpm == -1)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
else
@@ -2035,8 +2037,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
 #endif
else
amdgpu_device_ip_block_add(adev, _v8_5_ip_block);
-   amdgpu_device_ip_block_add(adev, _v7_3_ip_block);
-   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
amdgpu_device_ip_block_add(adev, _v4_2_ip_block);
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
break;
@@ -2044,6 +2044,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _v7_1_ip_block);
+   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
@@ -2053,8 +2055,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
 #endif
else
amdgpu_device_ip_block_add(adev, _v8_1_ip_block);
-   amdgpu_device_ip_block_add(adev, _v7_1_ip_block);
-   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
+
amdgpu_device_ip_block_add(adev, _v4_2_ip_block);
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
break;
@@ -2063,6 +2064,8 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v7_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _v7_2_ip_block);
+   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
@@ -2072,8 +2075,6 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
 #endif
else
amdgpu_device_ip_block_add(adev, _v8_3_ip_block);
-   amdgpu_device_ip_block_add(adev, _v7_2_ip_block);
-   amdgpu_device_ip_block_add(adev, _sdma_ip_block);
amdgpu_device_ip_block_add(adev, _v4_2_ip_block);
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
break;
diff --git 

[PATCH 3/4] drm/amd/pp: Disable dpm features on smu7/8 when suspend

[Rex Zhu]

Need to disable dpm features before halt rlc.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 14 +
 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 37 
 2 files changed, 33 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 04b7da0..3a6e348 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -5035,6 +5035,19 @@ static int smu7_get_performance_level(struct pp_hwmgr 
*hwmgr, const struct pp_hw
return 0;
 }
 
+static int smu7_power_off_asic(struct pp_hwmgr *hwmgr)
+{
+   struct smu7_hwmgr *data = hwmgr->backend;
+   int result;
+
+   result = smu7_disable_dpm_tasks(hwmgr);
+   PP_ASSERT_WITH_CODE((0 == result),
+   "[disable_dpm_tasks] Failed to disable DPM!",
+   );
+
+   return result;
+}
+
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = _hwmgr_backend_init,
.backend_fini = _hwmgr_backend_fini,
@@ -5092,6 +5105,7 @@ static int smu7_get_performance_level(struct pp_hwmgr 
*hwmgr, const struct pp_hw
.get_power_profile_mode = smu7_get_power_profile_mode,
.set_power_profile_mode = smu7_set_power_profile_mode,
.get_performance_level = smu7_get_performance_level,
+   .power_off_asic = smu7_power_off_asic,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index b863704..53cf787 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -880,7 +880,7 @@ static int smu8_set_power_state_tasks(struct pp_hwmgr 
*hwmgr, const void *input)
smu8_update_low_mem_pstate(hwmgr, input);
 
return 0;
-};
+}
 
 
 static int smu8_setup_asic_task(struct pp_hwmgr *hwmgr)
@@ -934,14 +934,6 @@ static void smu8_reset_cc6_data(struct pp_hwmgr *hwmgr)
hw_data->cc6_settings.cpu_pstate_disable = false;
 }
 
-static int smu8_power_off_asic(struct pp_hwmgr *hwmgr)
-{
-   smu8_power_up_display_clock_sys_pll(hwmgr);
-   smu8_clear_nb_dpm_flag(hwmgr);
-   smu8_reset_cc6_data(hwmgr);
-   return 0;
-};
-
 static void smu8_program_voting_clients(struct pp_hwmgr *hwmgr)
 {
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
@@ -1011,6 +1003,17 @@ static void smu8_reset_acp_boot_level(struct pp_hwmgr 
*hwmgr)
data->acp_boot_level = 0xff;
 }
 
+static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+{
+   smu8_program_voting_clients(hwmgr);
+   if (smu8_start_dpm(hwmgr))
+   return -EINVAL;
+   smu8_program_bootup_state(hwmgr);
+   smu8_reset_acp_boot_level(hwmgr);
+
+   return 0;
+}
+
 static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
smu8_disable_nb_dpm(hwmgr);
@@ -1020,18 +1023,16 @@ static int smu8_disable_dpm_tasks(struct pp_hwmgr 
*hwmgr)
return -EINVAL;
 
return 0;
-};
+}
 
-static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
+static int smu8_power_off_asic(struct pp_hwmgr *hwmgr)
 {
-   smu8_program_voting_clients(hwmgr);
-   if (smu8_start_dpm(hwmgr))
-   return -EINVAL;
-   smu8_program_bootup_state(hwmgr);
-   smu8_reset_acp_boot_level(hwmgr);
-
+   smu8_disable_dpm_tasks(hwmgr);
+   smu8_power_up_display_clock_sys_pll(hwmgr);
+   smu8_clear_nb_dpm_flag(hwmgr);
+   smu8_reset_cc6_data(hwmgr);
return 0;
-};
+}
 
 static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state  *prequest_ps,
-- 
1.9.1

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[PATCH 1/4] drm/amdgpu: Halt rlc/cp in rlc_safe_mode

[Rex Zhu]

before halt rlc/cp, need to
1. enter rlc safe mode
2. wait rlc/cp idle

Signed-off-by: Hang Zhou 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 86 ---
 1 file changed, 59 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 05b5bba..93d7fe5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5080,6 +5080,55 @@ static int gfx_v8_0_kcq_disable(struct amdgpu_device 
*adev)
return r;
 }
 
+static bool gfx_v8_0_is_idle(void *handle)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
+   || RREG32(mmGRBM_STATUS2) != 0x8)
+   return false;
+   else
+   return true;
+}
+
+static bool gfx_v8_0_rlc_is_idle(void *handle)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   if (RREG32(mmGRBM_STATUS2) != 0x8)
+   return false;
+   else
+   return true;
+}
+
+static int gfx_v8_0_wait_for_rlc_idle(void *handle)
+{
+   unsigned int i;
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   for (i = 0; i < adev->usec_timeout; i++) {
+   if (gfx_v8_0_rlc_is_idle(handle))
+   return 0;
+
+   udelay(1);
+   }
+   return -ETIMEDOUT;
+}
+
+static int gfx_v8_0_wait_for_idle(void *handle)
+{
+   unsigned int i;
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   for (i = 0; i < adev->usec_timeout; i++) {
+   if (gfx_v8_0_is_idle(handle))
+   return 0;
+
+   udelay(1);
+   }
+   return -ETIMEDOUT;
+}
+
 static int gfx_v8_0_hw_fini(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -5098,9 +5147,16 @@ static int gfx_v8_0_hw_fini(void *handle)
pr_debug("For SRIOV client, shouldn't do anything.\n");
return 0;
}
-   gfx_v8_0_cp_enable(adev, false);
-   gfx_v8_0_rlc_stop(adev);
-
+   adev->gfx.rlc.funcs->enter_safe_mode(adev);
+   if (!gfx_v8_0_wait_for_idle(adev))
+   gfx_v8_0_cp_enable(adev, false);
+   else
+   pr_err("cp is busy, skip halt cp\n");
+   if (!gfx_v8_0_wait_for_rlc_idle(adev))
+   gfx_v8_0_rlc_stop(adev);
+   else
+   pr_err("rlc is busy, skip halt rlc\n");
+   adev->gfx.rlc.funcs->exit_safe_mode(adev);
return 0;
 }
 
@@ -5121,30 +5177,6 @@ static int gfx_v8_0_resume(void *handle)
return r;
 }
 
-static bool gfx_v8_0_is_idle(void *handle)
-{
-   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-   if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
-   return false;
-   else
-   return true;
-}
-
-static int gfx_v8_0_wait_for_idle(void *handle)
-{
-   unsigned i;
-   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-   for (i = 0; i < adev->usec_timeout; i++) {
-   if (gfx_v8_0_is_idle(handle))
-   return 0;
-
-   udelay(1);
-   }
-   return -ETIMEDOUT;
-}
-
 static bool gfx_v8_0_check_soft_reset(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-- 
1.9.1

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[PATCH 2/4] drm/amdgpu: Remove redundant code in gfx_v8_0.c

[Rex Zhu]

the CG related registers have been programed in golden setting
PG register default value is 0.

Signed-off-by: Hang Zhou 
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 19 ---
 1 file changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 93d7fe5..3670f76 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4211,28 +4211,9 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device 
*adev)
u32 tmp;
 
gfx_v8_0_rlc_stop(adev);
-
-   /* disable CG */
-   tmp = RREG32(mmRLC_CGCG_CGLS_CTRL);
-   tmp &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
-RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
-   WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
-   if (adev->asic_type == CHIP_POLARIS11 ||
-   adev->asic_type == CHIP_POLARIS10 ||
-   adev->asic_type == CHIP_POLARIS12 ||
-   adev->asic_type == CHIP_VEGAM) {
-   tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);
-   tmp &= ~0x3;
-   WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);
-   }
-
-   /* disable PG */
-   WREG32(mmRLC_PG_CNTL, 0);
-
gfx_v8_0_rlc_reset(adev);
gfx_v8_0_init_pg(adev);
 
-
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
/* legacy rlc firmware loading */
r = gfx_v8_0_rlc_load_microcode(adev);
-- 
1.9.1

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Re: [PATCH 2/6] [RFC]drm: add syncobj timeline support v7

[Christian König]

Am 20.09.2018 um 11:45 schrieb Zhou, David(ChunMing):



-Original Message-
From: amd-gfx  On Behalf Of
Christian K?nig
Sent: Thursday, September 20, 2018 5:35 PM
To: Zhou, David(ChunMing) ; dri-
de...@lists.freedesktop.org
Cc: Dave Airlie ; Rakos, Daniel
; Daniel Vetter ; amd-
g...@lists.freedesktop.org
Subject: Re: [PATCH 2/6] [RFC]drm: add syncobj timeline support v7

The only thing I can still see is that you use wait_event_timeout() instead of
wait_event_interruptible().

Any particular reason for that?

I tried again after you said last thread, CTS always fail, and syncobj unit 
test fails as well.


Can you figure out why that happened? It sounds like an IOCTL is not 
correctly restarted after an signal.



Apart from that it now looks good to me.

Thanks, Can I get your RB on it?


No that the wait isn't interruptible is still a blocker.


Btw, I realize Vulkan spec names semaphore type as binary and timeline, so how 
about change _TYPE_INDIVIDUAL  to _TYPE_BINARY ?


Not a bad name either.

Christian.



Regards,
David Zhou

Christian.

Am 20.09.2018 um 11:29 schrieb Zhou, David(ChunMing):

Ping...


-Original Message-
From: amd-gfx  On Behalf Of
Chunming Zhou
Sent: Wednesday, September 19, 2018 5:18 PM
To: dri-de...@lists.freedesktop.org
Cc: Zhou, David(ChunMing) ; amd-
g...@lists.freedesktop.org; Rakos, Daniel ;
Daniel Vetter ; Dave Airlie ;
Koenig, Christian 
Subject: [PATCH 2/6] [RFC]drm: add syncobj timeline support v7

This patch is for VK_KHR_timeline_semaphore extension, semaphore is
called syncobj in kernel side:
This extension introduces a new type of syncobj that has an integer
payload identifying a point in a timeline. Such timeline syncobjs
support the following
operations:
 * CPU query - A host operation that allows querying the payload of the
   timeline syncobj.
 * CPU wait - A host operation that allows a blocking wait for a
   timeline syncobj to reach a specified value.
 * Device wait - A device operation that allows waiting for a
   timeline syncobj to reach a specified value.
 * Device signal - A device operation that allows advancing the
   timeline syncobj to a specified value.

v1:
Since it's a timeline, that means the front time point(PT) always is
signaled before the late PT.
a. signal PT design:
Signal PT fence N depends on PT[N-1] fence and signal opertion fence,
when PT[N] fence is signaled, the timeline will increase to value of PT[N].
b. wait PT design:
Wait PT fence is signaled by reaching timeline point value, when
timeline is increasing, will compare wait PTs value with new timeline
value, if PT value is lower than timeline value, then wait PT will be signaled,

otherwise keep in list.

syncobj wait operation can wait on any point of timeline, so need a
RB tree to order them. And wait PT could ahead of signal PT, we need
a sumission fence to perform that.

v2:
1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian) 2.
move unexposed denitions to .c file. (Daniel Vetter) 3. split up the
change to
drm_syncobj_find_fence() in a separate patch. (Christian) 4. split up
the change to drm_syncobj_replace_fence() in a separate patch.
5. drop the submission_fence implementation and instead use
wait_event() for that. (Christian) 6. WARN_ON(point != 0) for NORMAL

type syncobj case.

(Daniel Vetter)

v3:
1. replace normal syncobj with timeline implemenation. (Vetter and

Christian)

  a. normal syncobj signal op will create a signal PT to tail of signal pt 
list.
  b. normal syncobj wait op will create a wait pt with last signal
point, and this wait PT is only signaled by related signal point PT.
2. many bug fix and clean up
3. stub fence moving is moved to other patch.

v4：
1. fix RB tree loop with while(node=rb_first(...)). (Christian) 2.
fix syncobj lifecycle. (Christian) 3. only enable_signaling when
there is wait_pt. (Christian) 4. fix timeline path issues.
5. write a timeline test in libdrm

v5: (Christian)
1. semaphore is called syncobj in kernel side.
2. don't need 'timeline' characters in some function name.
3. keep syncobj cb.

v6: (Christian)
1. merge syncobj_timeline to syncobj structure.
2. simplify some check sentences.
3. some misc change.
4. fix CTS failed issue.

v7: (Christian)
1. error handling when creating signal pt.
2. remove timeline naming in func.
3. export flags in find_fence.
4. allow reset timeline.

individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore*
timeline syncobj is tested by ./amdgpu_test -s 9

Signed-off-by: Chunming Zhou 
Cc: Christian Konig 
Cc: Dave Airlie 
Cc: Daniel Rakos 
Cc: Daniel Vetter 
---
   drivers/gpu/drm/drm_syncobj.c  | 293 ++---
   drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +-
   include/drm/drm_syncobj.h  |  65 ++---
   include/uapi/drm/drm.h |   1 +
   4 files changed, 287 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/drm_syncobj.c
b/drivers/gpu/drm/drm_syncobj.c 

RE: [PATCH 2/6] [RFC]drm: add syncobj timeline support v7

[Zhou, David(ChunMing)]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Christian K?nig
> Sent: Thursday, September 20, 2018 5:35 PM
> To: Zhou, David(ChunMing) ; dri-
> de...@lists.freedesktop.org
> Cc: Dave Airlie ; Rakos, Daniel
> ; Daniel Vetter ; amd-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH 2/6] [RFC]drm: add syncobj timeline support v7
> 
> The only thing I can still see is that you use wait_event_timeout() instead of
> wait_event_interruptible().
> 
> Any particular reason for that?

I tried again after you said last thread, CTS always fail, and syncobj unit 
test fails as well.


> 
> Apart from that it now looks good to me.

Thanks, Can I get your RB on it?

Btw, I realize Vulkan spec names semaphore type as binary and timeline, so how 
about change _TYPE_INDIVIDUAL  to _TYPE_BINARY ?

Regards,
David Zhou
> 
> Christian.
> 
> Am 20.09.2018 um 11:29 schrieb Zhou, David(ChunMing):
> > Ping...
> >
> >> -Original Message-
> >> From: amd-gfx  On Behalf Of
> >> Chunming Zhou
> >> Sent: Wednesday, September 19, 2018 5:18 PM
> >> To: dri-de...@lists.freedesktop.org
> >> Cc: Zhou, David(ChunMing) ; amd-
> >> g...@lists.freedesktop.org; Rakos, Daniel ;
> >> Daniel Vetter ; Dave Airlie ;
> >> Koenig, Christian 
> >> Subject: [PATCH 2/6] [RFC]drm: add syncobj timeline support v7
> >>
> >> This patch is for VK_KHR_timeline_semaphore extension, semaphore is
> >> called syncobj in kernel side:
> >> This extension introduces a new type of syncobj that has an integer
> >> payload identifying a point in a timeline. Such timeline syncobjs
> >> support the following
> >> operations:
> >> * CPU query - A host operation that allows querying the payload of the
> >>   timeline syncobj.
> >> * CPU wait - A host operation that allows a blocking wait for a
> >>   timeline syncobj to reach a specified value.
> >> * Device wait - A device operation that allows waiting for a
> >>   timeline syncobj to reach a specified value.
> >> * Device signal - A device operation that allows advancing the
> >>   timeline syncobj to a specified value.
> >>
> >> v1:
> >> Since it's a timeline, that means the front time point(PT) always is
> >> signaled before the late PT.
> >> a. signal PT design:
> >> Signal PT fence N depends on PT[N-1] fence and signal opertion fence,
> >> when PT[N] fence is signaled, the timeline will increase to value of PT[N].
> >> b. wait PT design:
> >> Wait PT fence is signaled by reaching timeline point value, when
> >> timeline is increasing, will compare wait PTs value with new timeline
> >> value, if PT value is lower than timeline value, then wait PT will be 
> >> signaled,
> otherwise keep in list.
> >> syncobj wait operation can wait on any point of timeline, so need a
> >> RB tree to order them. And wait PT could ahead of signal PT, we need
> >> a sumission fence to perform that.
> >>
> >> v2:
> >> 1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian) 2.
> >> move unexposed denitions to .c file. (Daniel Vetter) 3. split up the
> >> change to
> >> drm_syncobj_find_fence() in a separate patch. (Christian) 4. split up
> >> the change to drm_syncobj_replace_fence() in a separate patch.
> >> 5. drop the submission_fence implementation and instead use
> >> wait_event() for that. (Christian) 6. WARN_ON(point != 0) for NORMAL
> type syncobj case.
> >> (Daniel Vetter)
> >>
> >> v3:
> >> 1. replace normal syncobj with timeline implemenation. (Vetter and
> Christian)
> >>  a. normal syncobj signal op will create a signal PT to tail of signal 
> >> pt list.
> >>  b. normal syncobj wait op will create a wait pt with last signal
> >> point, and this wait PT is only signaled by related signal point PT.
> >> 2. many bug fix and clean up
> >> 3. stub fence moving is moved to other patch.
> >>
> >> v4：
> >> 1. fix RB tree loop with while(node=rb_first(...)). (Christian) 2.
> >> fix syncobj lifecycle. (Christian) 3. only enable_signaling when
> >> there is wait_pt. (Christian) 4. fix timeline path issues.
> >> 5. write a timeline test in libdrm
> >>
> >> v5: (Christian)
> >> 1. semaphore is called syncobj in kernel side.
> >> 2. don't need 'timeline' characters in some function name.
> >> 3. keep syncobj cb.
> >>
> >> v6: (Christian)
> >> 1. merge syncobj_timeline to syncobj structure.
> >> 2. simplify some check sentences.
> >> 3. some misc change.
> >> 4. fix CTS failed issue.
> >>
> >> v7: (Christian)
> >> 1. error handling when creating signal pt.
> >> 2. remove timeline naming in func.
> >> 3. export flags in find_fence.
> >> 4. allow reset timeline.
> >>
> >> individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore*
> >> timeline syncobj is tested by ./amdgpu_test -s 9
> >>
> >> Signed-off-by: Chunming Zhou 
> >> Cc: Christian Konig 
> >> Cc: Dave Airlie 
> >> Cc: Daniel Rakos 
> >> Cc: Daniel Vetter 
> >> ---
> >>   drivers/gpu/drm/drm_syncobj.c  | 293 ++---
> >>   drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +-
> >>   

Re: [PATCH 2/6] [RFC]drm: add syncobj timeline support v7

[Christian König]

The only thing I can still see is that you use wait_event_timeout() 
instead of wait_event_interruptible().


Any particular reason for that?

Apart from that it now looks good to me.

Christian.

Am 20.09.2018 um 11:29 schrieb Zhou, David(ChunMing):

Ping...


-Original Message-
From: amd-gfx  On Behalf Of
Chunming Zhou
Sent: Wednesday, September 19, 2018 5:18 PM
To: dri-de...@lists.freedesktop.org
Cc: Zhou, David(ChunMing) ; amd-
g...@lists.freedesktop.org; Rakos, Daniel ; Daniel
Vetter ; Dave Airlie ; Koenig,
Christian 
Subject: [PATCH 2/6] [RFC]drm: add syncobj timeline support v7

This patch is for VK_KHR_timeline_semaphore extension, semaphore is
called syncobj in kernel side:
This extension introduces a new type of syncobj that has an integer payload
identifying a point in a timeline. Such timeline syncobjs support the following
operations:
* CPU query - A host operation that allows querying the payload of the
  timeline syncobj.
* CPU wait - A host operation that allows a blocking wait for a
  timeline syncobj to reach a specified value.
* Device wait - A device operation that allows waiting for a
  timeline syncobj to reach a specified value.
* Device signal - A device operation that allows advancing the
  timeline syncobj to a specified value.

v1:
Since it's a timeline, that means the front time point(PT) always is signaled
before the late PT.
a. signal PT design:
Signal PT fence N depends on PT[N-1] fence and signal opertion fence, when
PT[N] fence is signaled, the timeline will increase to value of PT[N].
b. wait PT design:
Wait PT fence is signaled by reaching timeline point value, when timeline is
increasing, will compare wait PTs value with new timeline value, if PT value is
lower than timeline value, then wait PT will be signaled, otherwise keep in 
list.
syncobj wait operation can wait on any point of timeline, so need a RB tree to
order them. And wait PT could ahead of signal PT, we need a sumission fence
to perform that.

v2:
1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian) 2.
move unexposed denitions to .c file. (Daniel Vetter) 3. split up the change to
drm_syncobj_find_fence() in a separate patch. (Christian) 4. split up the
change to drm_syncobj_replace_fence() in a separate patch.
5. drop the submission_fence implementation and instead use wait_event()
for that. (Christian) 6. WARN_ON(point != 0) for NORMAL type syncobj case.
(Daniel Vetter)

v3:
1. replace normal syncobj with timeline implemenation. (Vetter and Christian)
 a. normal syncobj signal op will create a signal PT to tail of signal pt 
list.
 b. normal syncobj wait op will create a wait pt with last signal point, 
and this
wait PT is only signaled by related signal point PT.
2. many bug fix and clean up
3. stub fence moving is moved to other patch.

v4：
1. fix RB tree loop with while(node=rb_first(...)). (Christian) 2. fix syncobj
lifecycle. (Christian) 3. only enable_signaling when there is wait_pt. 
(Christian)
4. fix timeline path issues.
5. write a timeline test in libdrm

v5: (Christian)
1. semaphore is called syncobj in kernel side.
2. don't need 'timeline' characters in some function name.
3. keep syncobj cb.

v6: (Christian)
1. merge syncobj_timeline to syncobj structure.
2. simplify some check sentences.
3. some misc change.
4. fix CTS failed issue.

v7: (Christian)
1. error handling when creating signal pt.
2. remove timeline naming in func.
3. export flags in find_fence.
4. allow reset timeline.

individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore* timeline
syncobj is tested by ./amdgpu_test -s 9

Signed-off-by: Chunming Zhou 
Cc: Christian Konig 
Cc: Dave Airlie 
Cc: Daniel Rakos 
Cc: Daniel Vetter 
---
  drivers/gpu/drm/drm_syncobj.c  | 293 ++---
  drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +-
  include/drm/drm_syncobj.h  |  65 ++---
  include/uapi/drm/drm.h |   1 +
  4 files changed, 287 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/drm_syncobj.c
b/drivers/gpu/drm/drm_syncobj.c index f796c9fc3858..95b60ac045c6 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -56,6 +56,9 @@
  #include "drm_internal.h"
  #include 

+/* merge normal syncobj to timeline syncobj, the point interval is 1 */
+#define DRM_SYNCOBJ_INDIVIDUAL_POINT 1
+
  struct drm_syncobj_stub_fence {
struct dma_fence base;
spinlock_t lock;
@@ -82,6 +85,11 @@ static const struct dma_fence_ops
drm_syncobj_stub_fence_ops = {
.release = drm_syncobj_stub_fence_release,  };

+struct drm_syncobj_signal_pt {
+   struct dma_fence_array *base;
+   u64value;
+   struct list_head list;
+};

  /**
   * drm_syncobj_find - lookup and reference a sync object.
@@ -124,8 +132,8 @@ static int
drm_syncobj_fence_get_or_add_callback(struct drm_syncobj *syncobj,  {
int ret;

-   *fence = drm_syncobj_fence_get(syncobj);
-   if 

RE: [PATCH 2/6] [RFC]drm: add syncobj timeline support v7

[Zhou, David(ChunMing)]

Ping...

> -Original Message-
> From: amd-gfx  On Behalf Of
> Chunming Zhou
> Sent: Wednesday, September 19, 2018 5:18 PM
> To: dri-de...@lists.freedesktop.org
> Cc: Zhou, David(ChunMing) ; amd-
> g...@lists.freedesktop.org; Rakos, Daniel ; Daniel
> Vetter ; Dave Airlie ; Koenig,
> Christian 
> Subject: [PATCH 2/6] [RFC]drm: add syncobj timeline support v7
> 
> This patch is for VK_KHR_timeline_semaphore extension, semaphore is
> called syncobj in kernel side:
> This extension introduces a new type of syncobj that has an integer payload
> identifying a point in a timeline. Such timeline syncobjs support the 
> following
> operations:
>* CPU query - A host operation that allows querying the payload of the
>  timeline syncobj.
>* CPU wait - A host operation that allows a blocking wait for a
>  timeline syncobj to reach a specified value.
>* Device wait - A device operation that allows waiting for a
>  timeline syncobj to reach a specified value.
>* Device signal - A device operation that allows advancing the
>  timeline syncobj to a specified value.
> 
> v1:
> Since it's a timeline, that means the front time point(PT) always is signaled
> before the late PT.
> a. signal PT design:
> Signal PT fence N depends on PT[N-1] fence and signal opertion fence, when
> PT[N] fence is signaled, the timeline will increase to value of PT[N].
> b. wait PT design:
> Wait PT fence is signaled by reaching timeline point value, when timeline is
> increasing, will compare wait PTs value with new timeline value, if PT value 
> is
> lower than timeline value, then wait PT will be signaled, otherwise keep in 
> list.
> syncobj wait operation can wait on any point of timeline, so need a RB tree to
> order them. And wait PT could ahead of signal PT, we need a sumission fence
> to perform that.
> 
> v2:
> 1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian) 2.
> move unexposed denitions to .c file. (Daniel Vetter) 3. split up the change to
> drm_syncobj_find_fence() in a separate patch. (Christian) 4. split up the
> change to drm_syncobj_replace_fence() in a separate patch.
> 5. drop the submission_fence implementation and instead use wait_event()
> for that. (Christian) 6. WARN_ON(point != 0) for NORMAL type syncobj case.
> (Daniel Vetter)
> 
> v3:
> 1. replace normal syncobj with timeline implemenation. (Vetter and Christian)
> a. normal syncobj signal op will create a signal PT to tail of signal pt 
> list.
> b. normal syncobj wait op will create a wait pt with last signal point, 
> and this
> wait PT is only signaled by related signal point PT.
> 2. many bug fix and clean up
> 3. stub fence moving is moved to other patch.
> 
> v4：
> 1. fix RB tree loop with while(node=rb_first(...)). (Christian) 2. fix syncobj
> lifecycle. (Christian) 3. only enable_signaling when there is wait_pt. 
> (Christian)
> 4. fix timeline path issues.
> 5. write a timeline test in libdrm
> 
> v5: (Christian)
> 1. semaphore is called syncobj in kernel side.
> 2. don't need 'timeline' characters in some function name.
> 3. keep syncobj cb.
> 
> v6: (Christian)
> 1. merge syncobj_timeline to syncobj structure.
> 2. simplify some check sentences.
> 3. some misc change.
> 4. fix CTS failed issue.
> 
> v7: (Christian)
> 1. error handling when creating signal pt.
> 2. remove timeline naming in func.
> 3. export flags in find_fence.
> 4. allow reset timeline.
> 
> individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore* timeline
> syncobj is tested by ./amdgpu_test -s 9
> 
> Signed-off-by: Chunming Zhou 
> Cc: Christian Konig 
> Cc: Dave Airlie 
> Cc: Daniel Rakos 
> Cc: Daniel Vetter 
> ---
>  drivers/gpu/drm/drm_syncobj.c  | 293 ++---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +-
>  include/drm/drm_syncobj.h  |  65 ++---
>  include/uapi/drm/drm.h |   1 +
>  4 files changed, 287 insertions(+), 74 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_syncobj.c
> b/drivers/gpu/drm/drm_syncobj.c index f796c9fc3858..95b60ac045c6 100644
> --- a/drivers/gpu/drm/drm_syncobj.c
> +++ b/drivers/gpu/drm/drm_syncobj.c
> @@ -56,6 +56,9 @@
>  #include "drm_internal.h"
>  #include 
> 
> +/* merge normal syncobj to timeline syncobj, the point interval is 1 */
> +#define DRM_SYNCOBJ_INDIVIDUAL_POINT 1
> +
>  struct drm_syncobj_stub_fence {
>   struct dma_fence base;
>   spinlock_t lock;
> @@ -82,6 +85,11 @@ static const struct dma_fence_ops
> drm_syncobj_stub_fence_ops = {
>   .release = drm_syncobj_stub_fence_release,  };
> 
> +struct drm_syncobj_signal_pt {
> + struct dma_fence_array *base;
> + u64value;
> + struct list_head list;
> +};
> 
>  /**
>   * drm_syncobj_find - lookup and reference a sync object.
> @@ -124,8 +132,8 @@ static int
> drm_syncobj_fence_get_or_add_callback(struct drm_syncobj *syncobj,  {
>   int ret;
> 
> - *fence = drm_syncobj_fence_get(syncobj);
> - if (*fence)
> + ret = 

Re: [PATCH 1/6] drm/dp_mst: Introduce drm_dp_mst_connector_atomic_check()

[Dan Carpenter]

Hi Lyude,

Thank you for the patch! Perhaps something to improve:

url:
https://github.com/0day-ci/linux/commits/Lyude-Paul/Fix-legacy-DPMS-changes-with-MST/20180919-203434
base:   git://anongit.freedesktop.org/drm-intel for-linux-next

smatch warnings:
drivers/gpu/drm/drm_dp_mst_topology.c:3144 drm_dp_mst_connector_still_exists() 
error: we previously assumed 'port' could be null (see line 3146)

# 
https://github.com/0day-ci/linux/commit/f8df31d5221b9a6da6698d4a37e622253bb17cdc
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout f8df31d5221b9a6da6698d4a37e622253bb17cdc
vim +/port +3144 drivers/gpu/drm/drm_dp_mst_topology.c

3f3353b7 Pandiyan, Dhinakaran 2017-04-20  3131  
f8df31d5 Lyude Paul   2018-09-18  3132  static bool
f8df31d5 Lyude Paul   2018-09-18  3133  
drm_dp_mst_connector_still_exists(struct drm_connector *connector,
f8df31d5 Lyude Paul   2018-09-18  3134  
  struct drm_dp_mst_topology_mgr *mgr,
f8df31d5 Lyude Paul   2018-09-18  3135  
  struct drm_dp_mst_branch *mstb)
f8df31d5 Lyude Paul   2018-09-18  3136  {
f8df31d5 Lyude Paul   2018-09-18  3137  struct drm_dp_mst_port 
*port;
f8df31d5 Lyude Paul   2018-09-18  3138  bool exists = false;
f8df31d5 Lyude Paul   2018-09-18  3139  
f8df31d5 Lyude Paul   2018-09-18  3140  mstb = 
drm_dp_get_validated_mstb_ref(mgr, mstb);
f8df31d5 Lyude Paul   2018-09-18  3141  if (!mstb)
f8df31d5 Lyude Paul   2018-09-18  3142  return false;
f8df31d5 Lyude Paul   2018-09-18  3143  
f8df31d5 Lyude Paul   2018-09-18 @3144  
list_for_each_entry(port, >ports, next) {

We need to use a different loop iterator, or possibly
list_for_each_entry_safe() because it looks like we're freeing
something.  Maybe it's cleanest to do both.

f8df31d5 Lyude Paul   2018-09-18  3145  port = 
drm_dp_get_validated_port_ref(mgr, port);
f8df31d5 Lyude Paul   2018-09-18 @3146  if (!port)
f8df31d5 Lyude Paul   2018-09-18  3147  
continue;
f8df31d5 Lyude Paul   2018-09-18  3148  
f8df31d5 Lyude Paul   2018-09-18  3149  exists = 
(port->connector == connector ||
f8df31d5 Lyude Paul   2018-09-18  3150
(port->mstb &&
f8df31d5 Lyude Paul   2018-09-18  3151 
drm_dp_mst_connector_still_exists(connector, mgr,
f8df31d5 Lyude Paul   2018-09-18  3152  
 port->mstb)));
f8df31d5 Lyude Paul   2018-09-18  3153  
f8df31d5 Lyude Paul   2018-09-18  3154  
drm_dp_put_port(port);
f8df31d5 Lyude Paul   2018-09-18  3155  if (exists)
f8df31d5 Lyude Paul   2018-09-18  3156  break;
f8df31d5 Lyude Paul   2018-09-18  3157  }
f8df31d5 Lyude Paul   2018-09-18  3158  
f8df31d5 Lyude Paul   2018-09-18  3159  
drm_dp_put_mst_branch_device(mstb);
f8df31d5 Lyude Paul   2018-09-18  3160  return exists;
f8df31d5 Lyude Paul   2018-09-18  3161  }
f8df31d5 Lyude Paul   2018-09-18  3162  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

It's important to pay attention to e-mails from "kbuild test robot"

[Michel Dänzer]

In particular if one's e-mail is in the To: field of the e-mail.

While there can be false positives, e.g. because a patch depends on
other patches, in general those e-mails point out valid issues in kernel
patches sent out for review. In that case, one should follow up with an
amended patch, or if the patch has already landed, an incremental fix-up
patch. If it isn't clear what the issue is, please ask.

This is a free service which can help improve the quality of our
patches, let's take advantage of it.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [PATCH] drm/amd/powerplay: enable fan RPM and pwm settings

[Zhu, Rex]

Please see in line.


Regards

Rex



From: amd-gfx  on behalf of Evan Quan 

Sent: Thursday, September 20, 2018 10:26 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Quan, Evan
Subject: [PATCH] drm/amd/powerplay: enable fan RPM and pwm settings

Manual fan RPM and pwm setting on vega20 are
available now.

Change-Id: Iad45a169d6984acc091c4efaf46973619fe43a29
Signed-off-by: Evan Quan 
Reviewed-by: Alex Deucher 
Reviewed-by: Rex Zhu 
---
 .../include/asic_reg/thm/thm_11_0_2_offset.h  |  12 ++
 .../include/asic_reg/thm/thm_11_0_2_sh_mask.h |  10 ++
 .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c|  27 
 .../drm/amd/powerplay/hwmgr/vega20_thermal.c  | 148 +-
 .../drm/amd/powerplay/hwmgr/vega20_thermal.h  |  11 +-
 5 files changed, 204 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
index 510ec3c70626..5ad10408660e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
@@ -26,6 +26,18 @@
 #define mmCG_MULT_THERMAL_STATUS   
0x005f
 #define mmCG_MULT_THERMAL_STATUS_BASE_IDX  
0

+#define mmCG_FDO_CTRL0 
0x0067
+#define mmCG_FDO_CTRL0_BASE_IDX
0
+
+#define mmCG_FDO_CTRL1 
0x0068
+#define mmCG_FDO_CTRL1_BASE_IDX
0
+
+#define mmCG_FDO_CTRL2 
0x0069
+#define mmCG_FDO_CTRL2_BASE_IDX
0
+
+#define mmCG_TACH_STATUS   
0x006b
+#define mmCG_TACH_STATUS_BASE_IDX  
0
+
 #define mmTHM_THERMAL_INT_ENA  
0x000a
 #define mmTHM_THERMAL_INT_ENA_BASE_IDX 
0
 #define mmTHM_THERMAL_INT_CTRL 
0x000b
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
index f69533fa6abf..ed1a2c869de5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
@@ -28,6 +28,16 @@
 #define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT
   0x9
 #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 
   0x01FFL
 #define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK  
   0x0003FE00L
+#define CG_FDO_CTRL2__TMIN__SHIFT  
   0x0
+#define CG_FDO_CTRL2__TMIN_MASK
   0x00FFL
+#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT  
   0xb
+#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK
   0x3800L
+#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT  
   0x0
+#define CG_FDO_CTRL1__FMAX_DUTY100_MASK
   0x00FFL
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT   
   0x0
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 
   0x00FFL
+#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 
   0x0
+#define CG_TACH_STATUS__TACH_PERIOD_MASK   
   0xL

 //THM_THERMAL_INT_ENA
 #define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 
   0x0
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 39069663ac3f..4a80b8101194 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -2284,6 +2284,25 @@ static uint32_t vega20_get_fan_control_mode(struct 
pp_hwmgr 

[PATCH 2/3] drm/amdgpu: Add fan RPM setting via sysfs

[Rex Zhu]

User can set fan's revolution per minute via
fan1_input.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h|  3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 28 +-
 drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 19 +
 4 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index ff24e1c..0258c6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -278,6 +278,9 @@ enum amdgpu_pcie_gen {
 #define amdgpu_dpm_get_fan_speed_rpm(adev, s) \

((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, 
(s))
 
+#define amdgpu_dpm_set_fan_speed_rpm(adev, s) \
+   
((adev)->powerplay.pp_funcs->set_fan_speed_rpm)((adev)->powerplay.pp_handle, 
(s))
+
 #define amdgpu_dpm_get_sclk(adev, l) \

((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 8c334fc..6a5b247 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1187,6 +1187,32 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device 
*dev,
return sprintf(buf, "%i\n", speed);
 }
 
+static ssize_t amdgpu_hwmon_set_fan1_input(struct device *dev,
+struct device_attribute *attr,
+const char *buf, size_t count)
+{
+   struct amdgpu_device *adev = dev_get_drvdata(dev);
+   int err;
+   u32 value;
+
+   /* Can't adjust fan when the card is off */
+   if  ((adev->flags & AMD_IS_PX) &&
+(adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+   return -EINVAL;
+
+   err = kstrtou32(buf, 10, );
+   if (err)
+   return err;
+
+   if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
+   err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
+   if (err)
+   return err;
+   }
+
+   return count;
+}
+
 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -1419,7 +1445,7 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device 
*dev,
 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, 
amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 
0);
 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 
0);
-static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, 
NULL, 0);
+static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO | S_IWUSR, 
amdgpu_hwmon_get_fan1_input, amdgpu_hwmon_set_fan1_input, 0);
 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 
0);
 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, 
NULL, 0);
 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 
0);
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 448dee4..d0fe993 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -227,6 +227,7 @@ struct amd_pm_funcs {
enum amd_dpm_forced_level (*get_performance_level)(void *handle);
enum amd_pm_state_type (*get_current_power_state)(void *handle);
int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
+   int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
int (*get_pp_table)(void *handle, char **table);
int (*set_pp_table)(void *handle, const char *buf, size_t size);
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index f486d50..60392cb 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -586,6 +586,24 @@ static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t 
*rpm)
return ret;
 }
 
+static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm)
+{
+   struct pp_hwmgr *hwmgr = handle;
+   int ret = 0;
+
+   if (!hwmgr || !hwmgr->pm_en)
+   return -EINVAL;
+
+   if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) {
+   pr_info("%s was not implemented.\n", __func__);
+   return 0;
+   }
+   mutex_lock(>smu_lock);
+   ret = hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm);
+   mutex_unlock(>smu_lock);
+   return ret;
+}
+
 static int pp_dpm_get_pp_num_states(void *handle,
struct 

[PATCH 3/3] drm/amd/pp: Fix fan's RPM setting not work on VI/Vega10

[Rex Zhu]

set the target rpm value to wrong register.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c   | 2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index d61a9b4..5bdc0df 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -273,7 +273,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, 
uint32_t speed)
tach_period = 60 * crystal_clock_freq * 1 / (8 * speed);
 
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-   CG_TACH_STATUS, TACH_PERIOD, tach_period);
+   CG_TACH_CTRL, TARGET_PERIOD, tach_period);
 
return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index aa044c1..c0711084 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -321,9 +321,9 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr 
*hwmgr, uint32_t speed)
if (!result) {
crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device 
*)hwmgr->adev);
tach_period = 60 * crystal_clock_freq * 1 / (8 * speed);
-   WREG32_SOC15(THM, 0, mmCG_TACH_STATUS,
-   REG_SET_FIELD(RREG32_SOC15(THM, 0, 
mmCG_TACH_STATUS),
-   CG_TACH_STATUS, TACH_PERIOD,
+   WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
+   REG_SET_FIELD(RREG32_SOC15(THM, 0, 
mmCG_TACH_CTRL),
+   CG_TACH_CTRL, TARGET_PERIOD,
tach_period));
}
return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
-- 
1.9.1

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[PATCH 1/3] drm/amd/pp: Avoid divide-by-zero in smu7_fan_ctrl_set_fan_speed_rpm

[Rex Zhu]

The minRPM speed maybe equal to zero. so need to check
input RPM not equal to 0, otherwise cause divide-by-zero driver crash.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
index 44527755..d61a9b4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c
@@ -260,6 +260,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, 
uint32_t speed)
if (hwmgr->thermal_controller.fanInfo.bNoFan ||
(hwmgr->thermal_controller.fanInfo.
ucTachometerPulsesPerRevolution == 0) ||
+   speed == 0 ||
(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
return 0;
-- 
1.9.1

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