Re: [PATCH 2/2] drm/amd/vega10: allow increased power limit
On Thu, Oct 4, 2018 at 3:17 AM Aleksandr Mezin
wrote:
>
> Allow setting the power limit to 150% of the default one, like
> Windows driver does.
Please see this patch:
https://patchwork.freedesktop.org/patch/255970/
This matches what the windows driver does.
Alex
>
> Signed-off-by: Aleksandr Mezin
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> index a6432f9a75b4..8218aa9189da 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> @@ -1342,7 +1342,8 @@ int vega10_enable_power_containment(struct pp_hwmgr
> *hwmgr)
>
> hwmgr->default_power_limit = hwmgr->power_limit =
> (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
> - hwmgr->max_power_limit = hwmgr->default_power_limit;
> + hwmgr->max_power_limit = hwmgr->default_power_limit +
> + hwmgr->default_power_limit / 2;
>
> if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
> if (data->smu_features[GNLD_PPT].supported)
> --
> 2.19.0
>
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Re: [PATCH] drm/amd/pp: enable power limit increase in OD mode
On Wed, Oct 10, 2018 at 7:25 PM Greathouse, Joseph
wrote:
>
> OverDrive mode allows users to increase the maximum SCLK and MCLK
> frequencies beyond the default on the GPU. However, this may not
> results in large performance gains if the GPU then runs into its TDP
> power limit. This patch adds the capability to increase the power
> limit of a GPU above its default maximum.
>
> This is only allowed when overdrive is enabled in the ppfeaturemask,
> since this is an overdrive feature. The TDPODLimit value from the
> VBIOS describes how how much higher the TDP should be allowed to go
> over its default, in percentage.
>
> Signed-off-by: Joseph Greathouse
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 75b56ae..5b0b6b6 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -958,6 +958,7 @@ static int pp_dpm_switch_power_profile(void *handle,
> static int pp_set_power_limit(void *handle, uint32_t limit)
> {
> struct pp_hwmgr *hwmgr = handle;
> + uint32_t max_power_limit = hwmgr->default_power_limit;
>
> if (!hwmgr || !hwmgr->pm_en)
> return -EINVAL;
> @@ -970,7 +971,12 @@ static int pp_set_power_limit(void *handle, uint32_t
> limit)
> if (limit == 0)
> limit = hwmgr->default_power_limit;
>
> - if (limit > hwmgr->default_power_limit)
> + if (hwmgr->od_enabled) {
> + max_power_limit *= (100 +
> hwmgr->platform_descriptor.TDPODLimit);
> + max_power_limit /= 100;
> + }
> +
> + if (limit > max_power_limit)
> return -EINVAL;
>
> mutex_lock(>smu_lock);
> @@ -989,8 +995,13 @@ static int pp_get_power_limit(void *handle, uint32_t
> *limit, bool default_limit)
>
> mutex_lock(>smu_lock);
>
> - if (default_limit)
> + if (default_limit) {
> *limit = hwmgr->default_power_limit;
> + if (hwmgr->od_enabled) {
> + *limit *= (100 +
> hwmgr->platform_descriptor.TDPODLimit);
> + *limit /= 100;
> + }
> + }
> else
> *limit = hwmgr->power_limit;
>
> --
> 2.7.4
>
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[pull] amdgpu, amdkfd, scheduler, radeon, ttm drm-next-4.20
Hi Dave, Fixes for 4.20. A little bigger than I'd like, but there are a lot of fixes for new asics that were introduced in 4.20 (Vega20, RV2, PCO). Highlights: - Add a new list.h helper for doing bulk updates. Used by ttm. - Fixes for display underflow on VI APUs at 4K with UVD running - Endian fixes for powerplay on vega - DC fixes for interlaced video - Vega20 powerplay fixes - RV/RV2/PCO powerplay fixes - Fix for spurious ACPI events on HG laptops - Fix a memory leak in DC on driver unload - Fixes for manual fan control mode switching - Suspend/resume robustness fixes - Fix display handling on RV2 - VCN fixes for DPG on PCO - Misc code cleanups and warning fixes The following changes since commit c530174b90fa3bcaa83d168b001b574bcb2da021: Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into drm-next (2018-10-04 11:31:05 +1000) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-next-4.20 for you to fetch changes up to df2fc43d09d3ee5ede82cab9299df5e78aa427b5: list: introduce list_bulk_move_tail helper (2018-10-10 15:20:54 -0500) Akshu Agrawal (1): drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVD Alex Deucher (5): drm/amdgpu/vega20: make power profile output more consistent drm/amdgpu/powerplay: endian fixes for vega10_processpptables.c drm/amdgpu/powerplay: endian fixes for vega12_processpptables.c drm/amdgpu/powerplay: endian fixes for vega20_processpptables.c drm/amdgpu/powerplay: factor out some pptable helpers Charlene Liu (2): drm/amd/display: fix 4K stereo screen flash issue drm/amd/display: fix Interlace video timing. Christian König (3): drm/amdgpu: fix AGP location with VRAM at 0x0 drm/amdgpu: fix incorrect use of amdgpu_irq_add_id in si_dma.c list: introduce list_bulk_move_tail helper Colin Ian King (1): drm/amdgpu/powerplay: fix missing break in switch statements Emily Deng (1): drm/amdgpu: Limit the max mc address to hole start Eric Yang (2): drm/amd/display: block DP YCbCr420 modes drm/amd/display: clean up encoding checks Eryk Brol (1): drm/amd/display: Add function to fetch clock requirements Evan Quan (8): drm/amd/powerplay/vega20: correct the hwmon interface ppt limit output drm/amd/powerplay/vega20: tell the correct gfx voltage V2 drm/amd/powerplay/vega20: enable fan RPM and pwm settings V2 drm/amdgpu: added vega20 LBPW support v2 drm/amdgpu: change Raven always on CUs to 4 drm/amdgpu: added AMD GPU instance counting V2 drm/amd/powerplay: helper interfaces for MGPU fan boost feature drm/amd/powerplay: enable MGPU fan boost feature on Vega20 Felix Kuehling (1): drm/amdkfd: Fix incorrect use of process->mm Hersen Wu (1): drm/amd/display: RV2 DP MST 2nd display within daisy chain not light up James Zhu (4): drm/amdgpu/vcn:Remove unused code drm/amdgpu/vcn:fix dpg pause mode hang issue drm/amdgpu/vcn:Replace value with defined macro drm/amdgpu/vcn:Correct VCN cache window definition Jun Lei (2): drm/amd/display: Add DC build_id to determine build type drm/amd/display: fix memory leak in resource pools Leo Li (1): drm/amd/display: Flatten irq handler data struct Lyude Paul (1): drm/amdgpu: Suppress keypresses from ACPI_VIDEO events Murton Liu (1): drm/amd/display: HLK Periodic Frame Notification test failed Nathan Chancellor (2): drm/amd/display: Use proper enums in process_channel_reply drm/scheduler: Simplify spsc_queue_count check in drm_sched_entity_select_rq Nicholas Kazlauskas (1): drm/amd/display: Raise dispclk value for dce_update_clocks Nick Alcock (1): drm/radeon: ratelimit bo warnings Nikola Cornij (1): drm/amd/display: Add a check-function for virtual signal type Pratik Vishwakarma (1): drm/amdgpu: skip IB tests for KIQ in general Rex Zhu (35): drm/amdgpu: Fix comments error in sdma_v4_1_update_power_gating drm/amd/pp: Fix fan's RPM setting not work on VI/Vega10 drm/amd/pp: Avoid divide-by-zero in fan_ctrl_set_fan_speed_rpm drm/amd/pp: Expose the smu support for SDMA PG cntl drm/amdgpu: Move out power up/down sdma out of smu drm/amd/pp: Remove uncessary extra vcn pg cntl in smu drm/amd/pp: Remove wrong code in fiji_start_smu drm/amdgpu: Refine uvd_v6/7_0_enc_get_destroy_msg drm/amdgpu: Add new AMDGPU_PP_SENSOR_MIN/MAX_FAN_RPM sensor drm/amd/pp: Implement AMDGPU_PP_SENSOR_MIN/MAX_FAN_RPM drm/amdgpu: Add fan RPM setting via sysfs drm/amdgpu: Disable sysfs pwm1 if not in manual fan control drm/amdgpu: Always enable fan sensors for read drm/amdgpu: Drop dead define in amdgpu.h drm/amd/pp: Fix memory leak on CI/AI drm/amdgpu: Move gfx flag in_suspend to adev drm/amd/pp: Refine
[PATCH] drm/amd/pp: enable power limit increase in OD mode
OverDrive mode allows users to increase the maximum SCLK and MCLK
frequencies beyond the default on the GPU. However, this may not
results in large performance gains if the GPU then runs into its TDP
power limit. This patch adds the capability to increase the power
limit of a GPU above its default maximum.
This is only allowed when overdrive is enabled in the ppfeaturemask,
since this is an overdrive feature. The TDPODLimit value from the
VBIOS describes how how much higher the TDP should be allowed to go
over its default, in percentage.
Signed-off-by: Joseph Greathouse
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 75b56ae..5b0b6b6 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -958,6 +958,7 @@ static int pp_dpm_switch_power_profile(void *handle,
static int pp_set_power_limit(void *handle, uint32_t limit)
{
struct pp_hwmgr *hwmgr = handle;
+ uint32_t max_power_limit = hwmgr->default_power_limit;
if (!hwmgr || !hwmgr->pm_en)
return -EINVAL;
@@ -970,7 +971,12 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
if (limit == 0)
limit = hwmgr->default_power_limit;
- if (limit > hwmgr->default_power_limit)
+ if (hwmgr->od_enabled) {
+ max_power_limit *= (100 +
hwmgr->platform_descriptor.TDPODLimit);
+ max_power_limit /= 100;
+ }
+
+ if (limit > max_power_limit)
return -EINVAL;
mutex_lock(>smu_lock);
@@ -989,8 +995,13 @@ static int pp_get_power_limit(void *handle, uint32_t
*limit, bool default_limit)
mutex_lock(>smu_lock);
- if (default_limit)
+ if (default_limit) {
*limit = hwmgr->default_power_limit;
+ if (hwmgr->od_enabled) {
+ *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
+ *limit /= 100;
+ }
+ }
else
*limit = hwmgr->power_limit;
--
2.7.4
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[PATCH 26/26] drm/amd/display: Disable 4k 60 HDMI on DCE11
From: David Francis
[Why]
Carrizo and Stoney have severe corruption when trying to power
4k 60 monitors over HDMI connectors that support 4k 60.
Carrizo and Stoney require retimers and redrivers to support 4k 60
over HDMI. This driver does not currently support these. Thus, 4k 60
HDMI (and all other modes requiring over 300MHz) should be disabled.
[How]
Reduce the dce11 HDMI pixel clock cap to 30kHz.
Signed-off-by: David Francis
Reviewed-by: Roman Li
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index c5714ebb9cea..1a90e1a38055 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -568,7 +568,7 @@ static struct input_pixel_processor *dce110_ipp_create(
static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
- .max_hdmi_pixel_clock = 594000,
+ .max_hdmi_pixel_clock = 30,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true
};
--
2.14.1
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[PATCH 25/26] drm/amd/display: Check if hubp function hooks exist before calling them
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f88c440c2826..345fc0302e4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -787,7 +787,7 @@ static bool dcn10_hw_wa_force_recovery(struct dc *dc)
>current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx != NULL) {
hubp = pipe_ctx->plane_res.hubp;
- if (hubp != NULL) {
+ if (hubp != NULL &&
hubp->funcs->hubp_get_underflow_status) {
if
(hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
/* one pipe underflow, we will reset
all the pipes*/
need_recover = true;
@@ -813,7 +813,7 @@ static bool dcn10_hw_wa_force_recovery(struct dc *dc)
if (pipe_ctx != NULL) {
hubp = pipe_ctx->plane_res.hubp;
/*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
- if (hubp != NULL)
+ if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
hubp->funcs->set_hubp_blank_en(hubp, true);
}
}
@@ -826,7 +826,7 @@ static bool dcn10_hw_wa_force_recovery(struct dc *dc)
if (pipe_ctx != NULL) {
hubp = pipe_ctx->plane_res.hubp;
/*DCHUBP_CNTL:HUBP_DISABLE=1*/
- if (hubp != NULL)
+ if (hubp != NULL && hubp->funcs->hubp_disable_control)
hubp->funcs->hubp_disable_control(hubp, true);
}
}
@@ -836,7 +836,7 @@ static bool dcn10_hw_wa_force_recovery(struct dc *dc)
if (pipe_ctx != NULL) {
hubp = pipe_ctx->plane_res.hubp;
/*DCHUBP_CNTL:HUBP_DISABLE=0*/
- if (hubp != NULL)
+ if (hubp != NULL && hubp->funcs->hubp_disable_control)
hubp->funcs->hubp_disable_control(hubp, true);
}
}
@@ -848,7 +848,7 @@ static bool dcn10_hw_wa_force_recovery(struct dc *dc)
if (pipe_ctx != NULL) {
hubp = pipe_ctx->plane_res.hubp;
/*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
- if (hubp != NULL)
+ if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
hubp->funcs->set_hubp_blank_en(hubp, true);
}
}
--
2.14.1
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[PATCH 24/26] drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part3
From: Fatemeh Darbehani
[Why]
In DCN we want direct DAL to SMU calls, with as little as
possible interference by pplib. The reason for each pp_smu interface
mapping to 1 SMU message is so we can have the sequencing of different
SMU message in dal and shared across different OS. This will also
simplify debugging as DAL owns this interaction and there's no
confusion about division of ownership.
[How]
Separate the set_hard_min_fclk_by_freq message from the
SMU messages that are sent as part of pp_rv_set_display_requirement.
directly notify min dcfclk to smu part 2
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 22 +-
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 6 ++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
index 6f329d1e8fd3..771bc86bc972 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
@@ -196,6 +196,24 @@ static void notify_hard_min_dcfclk_to_smu(
pp_smu->set_hard_min_dcfclk_by_freq(_smu->pp_smu, min_dcf_clk_mhz);
}
+static void notify_hard_min_fclk_to_smu(
+ struct pp_smu_funcs_rv *pp_smu, int min_f_clk_khz)
+{
+ int min_f_clk_mhz; //minimum required F clock in mhz
+
+ /*
+* if function pointer not set up, this message is
+* sent as part of pplib_apply_display_requirements.
+* So just return.
+*/
+ if (!pp_smu || !pp_smu->set_hard_min_fclk_by_freq)
+ return;
+
+ min_f_clk_mhz = min_f_clk_khz / 1000;
+
+ pp_smu->set_hard_min_fclk_by_freq(_smu->pp_smu, min_f_clk_mhz);
+}
+
static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
struct dc_state *context,
bool safe_to_lower)
@@ -250,7 +268,8 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
clock_voltage_req.clocks_in_khz = new_clocks->fclk_khz;
smu_req.hard_min_fclk_khz = new_clocks->fclk_khz;
- dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx,
_voltage_req);
+ notify_hard_min_fclk_to_smu(pp_smu, new_clocks->fclk_khz);
+
send_request_to_lower = true;
}
@@ -279,6 +298,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc,
new_clocks);
notify_hard_min_dcfclk_to_smu(pp_smu,
clock_voltage_req.clocks_in_khz);
+
if (pp_smu->set_display_requirement)
pp_smu->set_display_requirement(_smu->pp_smu,
_req);
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index e95502942e8c..285b6806a0ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -103,6 +103,12 @@ struct pp_smu_funcs_rv {
void (*set_display_count)(struct pp_smu *pp, int count);
/* which SMU message? are reader and writer WM separate SMU msg? */
+ /*
+* PPSMC_MSG_SetDriverDramAddrHigh
+* PPSMC_MSG_SetDriverDramAddrLow
+* PPSMC_MSG_TransferTableDram2Smu
+*
+* */
void (*set_wm_ranges)(struct pp_smu *pp,
struct pp_smu_wm_range_sets *ranges);
--
2.14.1
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[PATCH 23/26] drm/amd/display: Remove stream_res tg null check in commit planes
From: SivapiriyanKumarasamy [Why] TG in pipe_ctx stream resource is not null where used in commit_planes_do_stream_update since it is assigned the same time the stream is set in pipe_ctx - when the pipe is acquired. This null check produced a static code analysis warning and should be removed to avoid similar unnecessary checks in the future. [How] Remove the null check. Signed-off-by: SivapiriyanKumarasamy Reviewed-by: Krunoslav Kovac Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/core/dc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 99db82802c62..b83d1321d021 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1425,7 +1425,6 @@ static void commit_planes_do_stream_update(struct dc *dc, stream_update->adjust->v_total_max); if (stream_update->periodic_fn_vsync_delta && - pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt) pipe_ctx->stream_res.tg->funcs->program_vline_interrupt( pipe_ctx->stream_res.tg, _ctx->stream->timing, -- 2.14.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 19/26] drm/amd/display: dc 3.2.02
From: SivapiriyanKumarasamy Signed-off-by: SivapiriyanKumarasamy Reviewed-by: Harry Wentland Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7ce5f6e74b16..7c01f01a47ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.01" +#define DC_VER "3.2.02" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- 2.14.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 22/26] drm/amd/display: Fix incorrect end slope of EETF
From: SivapiriyanKumarasamy Force the E2 to dc_fixpt_one when E1 exceeds that value. This is the correct thing to do to avoid corruption. Signed-off-by: SivapiriyanKumarasamy Reviewed-by: Krunoslav Kovac Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c index 2e215c9e5445..bba518684243 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c @@ -789,7 +789,8 @@ static void hermite_spline_eetf(struct fixed31_32 input_x, // (t^3 - 2t^2 + t) * (1-ks) E2 = dc_fixpt_add(E2, dc_fixpt_mul(temp2, dc_fixpt_add(t, dc_fixpt_sub(t3, temp1; - } + } else + E2 = dc_fixpt_one; temp1 = dc_fixpt_sub(dc_fixpt_one, E2); temp2 = dc_fixpt_mul(temp1, temp1); -- 2.14.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 21/26] drm/amd/display: rename cstate_pstate_watermarks_st1
cstate_pstate_watermarks_st1 -> cstate_pstate_watermarks_st
Signed-off-by: vikrant mhaske
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index da89c2edb07c..06df02ddff6a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -31,7 +31,7 @@
#include "dml/display_mode_structs.h"
struct dchub_init_data;
-struct cstate_pstate_watermarks_st {
+struct cstate_pstate_watermarks_st1 {
uint32_t cstate_exit_ns;
uint32_t cstate_enter_plus_exit_ns;
uint32_t pstate_change_ns;
@@ -40,7 +40,7 @@ struct cstate_pstate_watermarks_st {
struct dcn_watermarks {
uint32_t pte_meta_urgent_ns;
uint32_t urgent_ns;
- struct cstate_pstate_watermarks_st cstate_pstate;
+ struct cstate_pstate_watermarks_st1 cstate_pstate;
};
struct dcn_watermark_set {
--
2.14.1
___
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[PATCH 20/26] drm/amd/display: explicit uint64_t casting
explicitly cast uint64_t in div64_u64_rem()
Signed-off-by: vikrant mhaske
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
index 39ee8eba3c31..d1656c9d50df 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
@@ -126,7 +126,7 @@ static inline struct bw_fixed bw_div(const struct bw_fixed
arg1, const struct bw
static inline struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct
bw_fixed arg2)
{
struct bw_fixed res;
- div64_u64_rem(arg1.value, arg2.value, );
+ div64_u64_rem(arg1.value, arg2.value, (uint64_t *));
return res;
}
--
2.14.1
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[PATCH 18/26] drm/amd/display: add dccg block
From: Dmytro Laktyushkin
This adds the hw block as well as hooks up dppclk dto
programming
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h | 7 +++-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 -
drivers/gpu/drm/amd/display/dc/inc/core_types.h| 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 44 ++
4 files changed, 58 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
index 2668d5645daa..046077797416 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
@@ -27,7 +27,8 @@
#ifndef _DCE_CLK_MGR_H_
#define _DCE_CLK_MGR_H_
-#include "../inc/hw/clk_mgr.h"
+#include "clk_mgr.h"
+#include "dccg.h"
#define MEMORY_TYPE_MULTIPLIER_CZ 4
@@ -79,6 +80,8 @@ struct dce_clk_mgr {
const struct clk_mgr_shift *clk_mgr_shift;
const struct clk_mgr_mask *clk_mgr_mask;
+ struct dccg *dccg;
+
struct state_dependent_clocks
max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
int dentist_vco_freq_khz;
@@ -160,6 +163,6 @@ struct clk_mgr *dce112_clk_mgr_create(
struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx);
-void dce_clk_mgr_destroy(struct clk_mgr **dccg);
+void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);
#endif /* _DCE_CLK_MGR_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 5c4a4f68b8a0..f88c440c2826 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -45,6 +45,7 @@
#include "dcn10_hubbub.h"
#include "dcn10_cm_common.h"
#include "dc_link_dp.h"
+#include "dccg.h"
#define DC_LOGGER_INIT(logger)
@@ -2059,7 +2060,13 @@ void update_dchubp_dpp(
should_divided_by_2,
true);
- dc->res_pool->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
+ if (dc->res_pool->dccg)
+ dc->res_pool->dccg->funcs->update_dpp_dto(
+ dc->res_pool->dccg,
+ dpp->inst,
+ pipe_ctx->plane_res.bw.calc.dppclk_khz);
+ else
+ dc->res_pool->clk_mgr->clks.dppclk_khz =
should_divided_by_2 ?
dc->res_pool->clk_mgr->clks.dispclk_khz / 2 :
dc->res_pool->clk_mgr->clks.dispclk_khz;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 6d0f5d885f7e..e3ee96afa60e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -170,6 +170,7 @@ struct resource_pool {
struct audio_support audio_support;
struct clk_mgr *clk_mgr;
+ struct dccg *dccg;
struct irq_service *irqs;
struct abm *abm;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
new file mode 100644
index ..95a56d012626
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_DCCG_H__
+#define __DAL_DCCG_H__
+
+#include "dc_types.h"
+
+struct dccg {
+ struct dc_context *ctx;
+ const struct dccg_funcs *funcs;
+
+ int ref_dppclk;
+};
+
+struct dccg_funcs {
+ void
[PATCH 16/26] drm/amd/display: rename dccg to clk_mgr
From: Dmytro Laktyushkin
In preparation for adding the actual dccg block since the
current implementation of dccg is mor eof a clock manager
than a hw block
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce/Makefile| 2 +-
.../display/dc/dce/{dce_dccg.c => dce_clk_mgr.c} | 350 ++---
.../display/dc/dce/{dce_dccg.h => dce_clk_mgr.h} | 58 ++--
.../amd/display/dc/dce100/dce100_hw_sequencer.c| 4 +-
.../drm/amd/display/dc/dce100/dce100_resource.c| 16 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c| 4 +-
.../drm/amd/display/dc/dce110/dce110_resource.c| 16 +-
.../drm/amd/display/dc/dce112/dce112_resource.c| 16 +-
.../drm/amd/display/dc/dce120/dce120_resource.c| 10 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 24 +-
drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 2 +-
.../dc/dcn10/{dcn10_dccg.c => dcn10_clk_mgr.c} | 131
.../dc/dcn10/{dcn10_dccg.h => dcn10_clk_mgr.h} | 10 +-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 18 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 28 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h| 6 +-
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 +-
.../amd/display/dc/inc/hw/{dccg.h => clk_mgr.h}| 16 +-
19 files changed, 357 insertions(+), 358 deletions(-)
rename drivers/gpu/drm/amd/display/dc/dce/{dce_dccg.c => dce_clk_mgr.c} (68%)
rename drivers/gpu/drm/amd/display/dc/dce/{dce_dccg.h => dce_clk_mgr.h} (78%)
rename drivers/gpu/drm/amd/display/dc/dcn10/{dcn10_dccg.c => dcn10_clk_mgr.c}
(69%)
rename drivers/gpu/drm/amd/display/dc/dcn10/{dcn10_dccg.h => dcn10_clk_mgr.h}
(87%)
rename drivers/gpu/drm/amd/display/dc/inc/hw/{dccg.h => clk_mgr.h} (83%)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index b16650c6f477..a5eb80aa3dd9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2071,7 +2071,7 @@ void dc_resource_state_construct(
const struct dc *dc,
struct dc_state *dst_ctx)
{
- dst_ctx->dccg = dc->res_pool->dccg;
+ dst_ctx->dccg = dc->res_pool->clk_mgr;
}
enum dc_status dc_validate_global_state(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile
b/drivers/gpu/drm/amd/display/dc/dce/Makefile
index f4ce7f502094..6d7b64a743ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile
@@ -28,7 +28,7 @@
DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
-dce_dccg.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \
+dce_clk_mgr.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \
dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dccg.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
similarity index 68%
rename from drivers/gpu/drm/amd/display/dc/dce/dce_dccg.c
rename to drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
index f87d70eeceae..9a28a04417d1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
@@ -23,27 +23,27 @@
*
*/
-#include "dce_dccg.h"
+#include "dce_clk_mgr.h"
#include "reg_helper.h"
#include "dmcu.h"
#include "core_types.h"
#include "dal_asic_id.h"
-#define TO_DCE_DCCG(clocks)\
- container_of(clocks, struct dce_dccg, base)
+#define TO_DCE_CLK_MGR(clocks)\
+ container_of(clocks, struct dce_clk_mgr, base)
#define REG(reg) \
- (dccg_dce->regs->reg)
+ (clk_mgr_dce->regs->reg)
#undef FN
#define FN(reg_name, field_name) \
- dccg_dce->dccg_shift->field_name, dccg_dce->dccg_mask->field_name
+ clk_mgr_dce->clk_mgr_shift->field_name,
clk_mgr_dce->clk_mgr_mask->field_name
#define CTX \
- dccg_dce->base.ctx
+ clk_mgr_dce->base.ctx
#define DC_LOGGER \
- dccg->ctx->logger
+ clk_mgr->ctx->logger
/* Max clock values for each state indexed by "enum clocks_state": */
static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
@@ -128,12 +128,12 @@ static int dentist_get_divider_from_did(int did)
(should not be case with CIK) then SW should program all rates
generated according to average value (case as with previous ASICs)
*/
-static int dccg_adjust_dp_ref_freq_for_ss(struct dce_dccg *dccg_dce, int
dp_ref_clk_khz)
+static int clk_mgr_adjust_dp_ref_freq_for_ss(struct dce_clk_mgr *clk_mgr_dce,
int dp_ref_clk_khz)
{
- if (dccg_dce->ss_on_dprefclk && dccg_dce->dprefclk_ss_divider != 0) {
+ if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider !=
0) {
[PATCH 17/26] drm/amd/display: implement PERF_TRACE on Linux
From: David Francis
[Why]
A quick-and-dirty way of getting performance data for the amdgpu
driver would make performance improvements easier
[How]
The PERF_TRACE functionality is a tic-toc style debug method.
Put PERF_TRACE calls on either side of the code you want to test.
PERF_TRACE requires access to struct dc_context. PERF_TRACE()
will pick up the CTX macro, and PERF_TRACE_CTX(struct dc_context)
allows you to pass the context explicitly.
The last 20 results can be read through the debugfs entry
amdgpu_perf_trace. Each result contains the time in ns and
number of GPU read/writes since the result before it.
In my experimentation, each PERF_TRACE() call uses at most 700ns
Signed-off-by: David Francis
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 74 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h | 2 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 21 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 36 +++
drivers/gpu/drm/amd/display/dc/dc_types.h | 22 +++
.../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 4 +-
drivers/gpu/drm/amd/display/dc/dm_services.h | 13 ++--
8 files changed, 165 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 492230c41b4a..252bfe330c1e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -471,8 +471,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
}
#if defined(CONFIG_DEBUG_FS)
- if (dtn_debugfs_init(adev))
- DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
+ if (amdgpu_dm_debugfs_init(adev))
+ DRM_ERROR("amdgpu: failed to initialize dm debugfs entries.\n");
#endif
DRM_DEBUG_DRIVER("KMS initialized.\n");
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 0ef4a40d2247..6b73c0e6bf67 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -782,7 +782,63 @@ static ssize_t dtn_log_write(
return size;
}
-int dtn_debugfs_init(struct amdgpu_device *adev)
+static ssize_t perf_trace_read(struct file *f, char __user *buf,
+size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ struct perf_trace *trace = adev->dm.dc->ctx->perf_trace;
+ struct perf_trace_entry *entry;
+ char *rd_buf = NULL;
+ char *rd_buf_pos = NULL;
+ const uint32_t line_buf_size = 200;
+ const uint32_t rd_buf_size = line_buf_size * trace->num_entries;
+ int r;
+ int result = 0;
+ int i;
+
+ if (*pos & 3 || size & 3)
+ return -EINVAL;
+
+ rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
+ if (!rd_buf)
+ return -EINVAL;
+ rd_buf_pos = rd_buf;
+
+ rd_buf_pos += snprintf(rd_buf_pos, rd_buf_size, "PERF_TRACE:\n");
+
+ for (i = 0; i < trace->num_entries; i++) {
+ entry = >entries[(trace->next_entry + i) %
trace->num_entries];
+
+ if (strcmp(entry->func_name, ""))
+ rd_buf_pos += snprintf(rd_buf_pos, line_buf_size,
"%s:%d Reads:%d\t Writes:%d\t ns:%lld\n",
+ entry->func_name,
+ entry->line_number,
+ entry->read_count,
+ entry->write_count,
+ entry->time_delta);
+ }
+
+ while (size) {
+ if (*pos >= rd_buf_size)
+ break;
+
+ r = put_user((*(rd_buf + result)), buf);
+ if (r) {
+ kfree(rd_buf);
+ return r;
+ }
+
+ buf += 1;
+ size -= 1;
+ *pos += 1;
+ result += 1;
+ }
+
+ kfree(rd_buf);
+ return result;
+}
+
+int amdgpu_dm_debugfs_init(struct amdgpu_device *adev)
{
static const struct file_operations dtn_log_fops = {
.owner = THIS_MODULE,
@@ -791,6 +847,12 @@ int dtn_debugfs_init(struct amdgpu_device *adev)
.llseek = default_llseek
};
+ static const struct file_operations perf_trace_fops = {
+ .owner = THIS_MODULE,
+ .read = perf_trace_read,
+ .llseek = default_llseek
+ };
+
struct drm_minor *minor = adev->ddev->primary;
struct dentry *root = minor->debugfs_root;
@@ -801,5 +863,15 @@ int dtn_debugfs_init(struct amdgpu_device *adev)
adev,
[PATCH 12/26] drm/amd/display: fix report display count logic
From: Eric Yang
[Why]
Previous logic to update display count in commit_planes_do_stream_update
doesn't cover all cases.
[How]
Update display count as part of clock updates. Count virtual stream
as active to work around headless situation.
Signed-off-by: Eric Yang
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 35 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c | 47 +--
2 files changed, 45 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 20dd062d7a33..a8d8358058ff 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1365,35 +1365,6 @@ static struct dc_stream_status *stream_get_status(
static const enum surface_update_type update_surface_trace_level =
UPDATE_TYPE_FULL;
-static void notify_display_count_to_smu(
- struct dc *dc,
- struct dc_state *context)
-{
- int i, display_count;
- struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
-
- /*
-* if function pointer not set up, this message is
-* sent as part of pplib_apply_display_requirements.
-* So just return.
-*/
- if (!pp_smu || !pp_smu->set_display_count)
- return;
-
- display_count = 0;
- for (i = 0; i < context->stream_count; i++) {
- const struct dc_stream_state *stream = context->streams[i];
-
- /* only notify active stream */
- if (stream->dpms_off)
- continue;
-
- display_count++;
- }
-
- pp_smu->set_display_count(_smu->pp_smu, display_count);
-}
-
static void commit_planes_do_stream_update(struct dc *dc,
struct dc_stream_state *stream,
struct dc_stream_update *stream_update,
@@ -1444,15 +1415,13 @@ static void commit_planes_do_stream_update(struct dc
*dc,
if (stream_update->dpms_off) {
if (*stream_update->dpms_off) {
core_link_disable_stream(pipe_ctx,
KEEP_ACQUIRED_RESOURCE);
- notify_display_count_to_smu(dc,
dc->current_state);
+ dc->hwss.optimize_bandwidth(dc,
dc->current_state);
} else {
- notify_display_count_to_smu(dc,
dc->current_state);
+ dc->hwss.prepare_bandwidth(dc,
dc->current_state);
core_link_enable_stream(dc->current_state, pipe_ctx);
}
}
-
-
if (stream_update->abm_level &&
pipe_ctx->stream_res.abm) {
if (pipe_ctx->stream_res.tg->funcs->is_blanked)
{
// if otg funcs defined check if
blanked before programming
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
index abfe82f02fd8..0a9f944c961d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
@@ -139,6 +139,29 @@ static void dcn1_ramp_up_dispclk_with_dpp(struct dccg
*dccg, struct dc_clocks *n
dccg->clks.max_supported_dppclk_khz =
new_clocks->max_supported_dppclk_khz;
}
+static int get_active_display_cnt(
+ struct dc *dc,
+ struct dc_state *context)
+{
+ int i, display_count;
+
+ display_count = 0;
+ for (i = 0; i < context->stream_count; i++) {
+ const struct dc_stream_state *stream = context->streams[i];
+
+ /*
+* Only notify active stream or virtual stream.
+* Need to notify virtual stream to work around
+* headless case. HPD does not fire when system is in
+* S0i2.
+*/
+ if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
+ display_count++;
+ }
+
+ return display_count;
+}
+
static void dcn1_update_clocks(struct dccg *dccg,
struct dc_state *context,
bool safe_to_lower)
@@ -152,11 +175,27 @@ static void dcn1_update_clocks(struct dccg *dccg,
struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
bool send_request_to_increase = false;
bool send_request_to_lower = false;
+ int display_count;
+
+ bool enter_display_off = false;
+
+ display_count = get_active_display_cnt(dc, context);
+
+ if (display_count == 0)
+ enter_display_off = true;
- if (new_clocks->phyclk_khz)
- smu_req.display_count = 1;
- else
-
[PATCH 15/26] drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part2
From: Fatemeh Darbehani
[Why]
In DCN we want direct DAL to SMU calls, with as little as possible
interference by pplib. The reason for each pp_smu interface mapping to
1 SMU message is so we can have the sequencing of different SMU message
in dal and shared across different OS. This will also simplify
debugging as DAL owns this interaction and there's no confusion about
division of ownership.
[How]
Part 2: Separate set_min_deep_sleep_dcfclk message from the SMU
messages that are sent as part of dm_pp_apply_clock_for_voltage_request.
Directly notify min dcfclk to smu
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c | 28 +--
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h| 6 ++---
2 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
index 5159a7ea966a..5ffc36753668 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
@@ -178,6 +178,24 @@ static void notify_deep_sleep_dcfclk_to_smu(
pp_smu->set_min_deep_sleep_dcfclk(_smu->pp_smu,
min_dcef_deep_sleep_clk_mhz);
}
+static void notify_hard_min_dcfclk_to_smu(
+ struct pp_smu_funcs_rv *pp_smu, int min_dcf_clk_khz)
+{
+ int min_dcf_clk_mhz; //minimum required DCF clock in mhz
+
+ /*
+* if function pointer not set up, this message is
+* sent as part of pplib_apply_display_requirements.
+* So just return.
+*/
+ if (!pp_smu || !pp_smu->set_hard_min_dcfclk_by_freq)
+ return;
+
+ min_dcf_clk_mhz = min_dcf_clk_khz / 1000;
+
+ pp_smu->set_hard_min_dcfclk_by_freq(_smu->pp_smu, min_dcf_clk_mhz);
+}
+
static void dcn1_update_clocks(struct dccg *dccg,
struct dc_state *context,
bool safe_to_lower)
@@ -225,6 +243,7 @@ static void dcn1_update_clocks(struct dccg *dccg,
send_request_to_lower = true;
}
+ // F Clock
if (should_set_clock(safe_to_lower, new_clocks->fclk_khz,
dccg->clks.fclk_khz)) {
dccg->clks.fclk_khz = new_clocks->fclk_khz;
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_FCLK;
@@ -235,6 +254,7 @@ static void dcn1_update_clocks(struct dccg *dccg,
send_request_to_lower = true;
}
+ //DCF Clock
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz,
dccg->clks.dcfclk_khz)) {
dccg->clks.dcfclk_khz = new_clocks->dcfclk_khz;
smu_req.hard_min_dcefclk_khz = new_clocks->dcfclk_khz;
@@ -257,7 +277,9 @@ static void dcn1_update_clocks(struct dccg *dccg,
/*use dcfclk to request voltage*/
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc,
new_clocks);
- dm_pp_apply_clock_for_voltage_request(dccg->ctx,
_voltage_req);
+
+ notify_hard_min_dcfclk_to_smu(pp_smu,
clock_voltage_req.clocks_in_khz);
+
if (pp_smu->set_display_requirement)
pp_smu->set_display_requirement(_smu->pp_smu,
_req);
@@ -279,7 +301,9 @@ static void dcn1_update_clocks(struct dccg *dccg,
/*use dcfclk to request voltage*/
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc,
new_clocks);
- dm_pp_apply_clock_for_voltage_request(dccg->ctx,
_voltage_req);
+
+ notify_hard_min_dcfclk_to_smu(pp_smu,
clock_voltage_req.clocks_in_khz);
+
if (pp_smu->set_display_requirement)
pp_smu->set_display_requirement(_smu->pp_smu,
_req);
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index f2ea8452d48f..e95502942e8c 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -109,7 +109,7 @@ struct pp_smu_funcs_rv {
/* PPSMC_MSG_SetHardMinDcfclkByFreq
* fixed clock at requested freq, either from FCH bypass or DFS
*/
- void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int khz);
+ void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
/* PPSMC_MSG_SetMinDeepSleepDcfclk
* when DF is in cstate, dcf clock is further divided down
@@ -120,12 +120,12 @@ struct pp_smu_funcs_rv {
/* PPSMC_MSG_SetHardMinFclkByFreq
* FCLK will vary with DPM, but never below requested hard min
*/
- void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int khz);
+ void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
/* PPSMC_MSG_SetHardMinSocclkByFreq
* Needed for DWB support
[PATCH 13/26] drm/amd/display: Add link encoder dp_ycbcr420_supported feature flag
From: Eric Bernstein
[Why]
Need separate feature flag for DP 4:2:0 support, since existing
flag is used for HDMI
[How]
Added dp_ycbcr420_supported to struct encoder_feature_support
Signed-off-by: Eric Bernstein
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 8 +---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 3 ++-
7 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bbfffaf15ccb..492230c41b4a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3780,12 +3780,12 @@ void amdgpu_dm_connector_init_helper(struct
amdgpu_display_manager *dm,
case DRM_MODE_CONNECTOR_HDMIA:
aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
aconnector->base.ycbcr_420_allowed =
- link->link_enc->features.ycbcr420_supported ? true :
false;
+ link->link_enc->features.hdmi_ycbcr420_supported ? true
: false;
break;
case DRM_MODE_CONNECTOR_DisplayPort:
aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
aconnector->base.ycbcr_420_allowed =
- link->link_enc->features.ycbcr420_supported ? true :
false;
+ link->link_enc->features.dp_ycbcr420_supported ? true :
false;
break;
case DRM_MODE_CONNECTOR_DVID:
aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 366bc8c2c643..3e18ea84b1f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -645,7 +645,7 @@ static bool dce110_link_encoder_validate_hdmi_output(
return false;
/* DCE11 HW does not support 420 */
- if (!enc110->base.features.ycbcr420_supported &&
+ if (!enc110->base.features.hdmi_ycbcr420_supported &&
crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index b3d00d7e51fa..e73b1392bed9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -551,7 +551,8 @@ static struct transform *dce112_transform_create(
static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 60,
- .ycbcr420_supported = true,
+ .hdmi_ycbcr420_supported = true,
+ .dp_ycbcr420_supported = false,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 512a22d9fea8..a69e89f779de 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -607,7 +607,8 @@ static struct audio *create_audio(
static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 60,
- .ycbcr420_supported = true,
+ .hdmi_ycbcr420_supported = true,
+ .dp_ycbcr420_supported = false,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index ba6a8686062f..477ab916 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -589,7 +589,7 @@ static bool dcn10_link_encoder_validate_hdmi_output(
return false;
/* DCE11 HW does not support 420 */
- if (!enc10->base.features.ycbcr420_supported &&
+ if (!enc10->base.features.hdmi_ycbcr420_supported &&
crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
return false;
@@ -606,8 +606,10 @@
[PATCH 14/26] drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part1
From: Fatemeh Darbehani
[Why]
In DCN we want direct DAL to SMU calls, with as little as possible
interference by pplib. The reason for each pp_smu interface mapping
to 1 SMU message is so we can have the sequencing of different SMU
message in dal and shared across different OS. This will also simplify
debugging as DAL owns this interaction and there's no confusion about
division of ownership.
[How]
Part 1: Separate set_min_deep_Sleep_dcfclk message from the SMU
messages that are sent as part of dcn10_pplib_apply_display_requirements.
Notify deep sleep dcfclk to smu directly
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
index 0a9f944c961d..5159a7ea966a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
@@ -162,6 +162,22 @@ static int get_active_display_cnt(
return display_count;
}
+static void notify_deep_sleep_dcfclk_to_smu(
+ struct pp_smu_funcs_rv *pp_smu, int min_dcef_deep_sleep_clk_khz)
+{
+ int min_dcef_deep_sleep_clk_mhz; //minimum required DCEF Deep Sleep
clock in mhz
+ /*
+* if function pointer not set up, this message is
+* sent as part of pplib_apply_display_requirements.
+* So just return.
+*/
+ if (!pp_smu || !pp_smu->set_min_deep_sleep_dcfclk)
+ return;
+
+ min_dcef_deep_sleep_clk_mhz = (min_dcef_deep_sleep_clk_khz + 999) /
1000; //Round up
+ pp_smu->set_min_deep_sleep_dcfclk(_smu->pp_smu,
min_dcef_deep_sleep_clk_mhz);
+}
+
static void dcn1_update_clocks(struct dccg *dccg,
struct dc_state *context,
bool safe_to_lower)
@@ -244,6 +260,8 @@ static void dcn1_update_clocks(struct dccg *dccg,
dm_pp_apply_clock_for_voltage_request(dccg->ctx,
_voltage_req);
if (pp_smu->set_display_requirement)
pp_smu->set_display_requirement(_smu->pp_smu,
_req);
+
+ notify_deep_sleep_dcfclk_to_smu(pp_smu,
dccg->clks.dcfclk_deep_sleep_khz);
dcn1_pplib_apply_display_requirements(dc, context);
}
@@ -264,6 +282,8 @@ static void dcn1_update_clocks(struct dccg *dccg,
dm_pp_apply_clock_for_voltage_request(dccg->ctx,
_voltage_req);
if (pp_smu->set_display_requirement)
pp_smu->set_display_requirement(_smu->pp_smu,
_req);
+
+ notify_deep_sleep_dcfclk_to_smu(pp_smu,
dccg->clks.dcfclk_deep_sleep_khz);
dcn1_pplib_apply_display_requirements(dc, context);
}
--
2.14.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/26] drm/amd/display: expose hwseq functions and add registers
From: Nevenko Stupar
Make these functions non static and define registers for future use
is_lower_pipe_tree_visible();
is_upper_pipe_tree_visible();
is_pipe_tree_visible();
dcn10_program_pte_vm();
set_hdr_multiplier();
update_dchubp_dpp()
find_top_pipe_for_stream()
Signed-off-by: Nevenko Stupar
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h| 2 -
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 50 ++
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +++---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 20 +
4 files changed, 77 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index d321e1c053e4..7ce5f6e74b16 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -249,8 +249,6 @@ struct dc_debug_options {
bool disable_dmcu;
bool disable_psr;
bool force_abm_enable;
- bool disable_hbup_pg;
- bool disable_dpp_pg;
bool disable_stereo_support;
bool vsr_support;
bool performance_trace;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 64dc75378541..7d977870131c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -233,6 +233,16 @@ struct dce_hwseq_registers {
uint32_t DOMAIN5_PG_CONFIG;
uint32_t DOMAIN6_PG_CONFIG;
uint32_t DOMAIN7_PG_CONFIG;
+ uint32_t DOMAIN8_PG_CONFIG;
+ uint32_t DOMAIN9_PG_CONFIG;
+ uint32_t DOMAIN10_PG_CONFIG;
+ uint32_t DOMAIN11_PG_CONFIG;
+ uint32_t DOMAIN16_PG_CONFIG;
+ uint32_t DOMAIN17_PG_CONFIG;
+ uint32_t DOMAIN18_PG_CONFIG;
+ uint32_t DOMAIN19_PG_CONFIG;
+ uint32_t DOMAIN20_PG_CONFIG;
+ uint32_t DOMAIN21_PG_CONFIG;
uint32_t DOMAIN0_PG_STATUS;
uint32_t DOMAIN1_PG_STATUS;
uint32_t DOMAIN2_PG_STATUS;
@@ -241,6 +251,16 @@ struct dce_hwseq_registers {
uint32_t DOMAIN5_PG_STATUS;
uint32_t DOMAIN6_PG_STATUS;
uint32_t DOMAIN7_PG_STATUS;
+ uint32_t DOMAIN8_PG_STATUS;
+ uint32_t DOMAIN9_PG_STATUS;
+ uint32_t DOMAIN10_PG_STATUS;
+ uint32_t DOMAIN11_PG_STATUS;
+ uint32_t DOMAIN16_PG_STATUS;
+ uint32_t DOMAIN17_PG_STATUS;
+ uint32_t DOMAIN18_PG_STATUS;
+ uint32_t DOMAIN19_PG_STATUS;
+ uint32_t DOMAIN20_PG_STATUS;
+ uint32_t DOMAIN21_PG_STATUS;
uint32_t DIO_MEM_PWR_CTRL;
uint32_t DCCG_GATE_DISABLE_CNTL;
uint32_t DCCG_GATE_DISABLE_CNTL2;
@@ -489,6 +509,26 @@ struct dce_hwseq_registers {
type DOMAIN6_POWER_GATE; \
type DOMAIN7_POWER_FORCEON; \
type DOMAIN7_POWER_GATE; \
+ type DOMAIN8_POWER_FORCEON; \
+ type DOMAIN8_POWER_GATE; \
+ type DOMAIN9_POWER_FORCEON; \
+ type DOMAIN9_POWER_GATE; \
+ type DOMAIN10_POWER_FORCEON; \
+ type DOMAIN10_POWER_GATE; \
+ type DOMAIN11_POWER_FORCEON; \
+ type DOMAIN11_POWER_GATE; \
+ type DOMAIN16_POWER_FORCEON; \
+ type DOMAIN16_POWER_GATE; \
+ type DOMAIN17_POWER_FORCEON; \
+ type DOMAIN17_POWER_GATE; \
+ type DOMAIN18_POWER_FORCEON; \
+ type DOMAIN18_POWER_GATE; \
+ type DOMAIN19_POWER_FORCEON; \
+ type DOMAIN19_POWER_GATE; \
+ type DOMAIN20_POWER_FORCEON; \
+ type DOMAIN20_POWER_GATE; \
+ type DOMAIN21_POWER_FORCEON; \
+ type DOMAIN21_POWER_GATE; \
type DOMAIN0_PGFSM_PWR_STATUS; \
type DOMAIN1_PGFSM_PWR_STATUS; \
type DOMAIN2_PGFSM_PWR_STATUS; \
@@ -497,6 +537,16 @@ struct dce_hwseq_registers {
type DOMAIN5_PGFSM_PWR_STATUS; \
type DOMAIN6_PGFSM_PWR_STATUS; \
type DOMAIN7_PGFSM_PWR_STATUS; \
+ type DOMAIN8_PGFSM_PWR_STATUS; \
+ type DOMAIN9_PGFSM_PWR_STATUS; \
+ type DOMAIN10_PGFSM_PWR_STATUS; \
+ type DOMAIN11_PGFSM_PWR_STATUS; \
+ type DOMAIN16_PGFSM_PWR_STATUS; \
+ type DOMAIN17_PGFSM_PWR_STATUS; \
+ type DOMAIN18_PGFSM_PWR_STATUS; \
+ type DOMAIN19_PGFSM_PWR_STATUS; \
+ type DOMAIN20_PGFSM_PWR_STATUS; \
+ type DOMAIN21_PGFSM_PWR_STATUS; \
type DCFCLK_GATE_DIS; \
type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
type VGA_TEST_ENABLE; \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 637524128176..d1f8c8e0b4c3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1603,7 +1603,7 @@ static void mmhub_read_vm_context0_settings(struct
dcn10_hubp *hubp1,
}
-static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
+void
[PATCH 10/26] drm/amd/display: initialize dc_transfer_func->ctx
From: David Francis [Why] dc_transfer_func structs were being passed around with a null pointer, waiting for unsuspecting programmers to dereference it. [How] Initialize it Signed-off-by: David Francis Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 1 + drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 2ac848a106ba..e113439aaa86 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -106,6 +106,7 @@ static void construct(struct dc_stream_state *stream, stream->out_transfer_func = dc_create_transfer_func(); stream->out_transfer_func->type = TF_TYPE_BYPASS; + stream->out_transfer_func->ctx = stream->ctx; } static void destruct(struct dc_stream_state *stream) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 8fb3aefd195c..c60c9b4c3075 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -44,6 +44,7 @@ static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state plane_state->in_transfer_func = dc_create_transfer_func(); plane_state->in_transfer_func->type = TF_TYPE_BYPASS; + plane_state->in_transfer_func->ctx = ctx; } static void destruct(struct dc_plane_state *plane_state) -- 2.14.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/26] drm/amd/display: Build ColorSpace and Transfer Function
From: SivapiriyanKumarasamy
[Why]
Need to build correct regamma curve to make use of display native
parameters for HDR and more closely match content range to
display.
[How]
Enable freesync hdr curve building after reading display capabilities
and receiving setsourcecontentinfo call. This will do both EOTF and
EETF based on the content.
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c| 2 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 2 +-
.../drm/amd/display/modules/color/color_gamma.c| 175 -
.../drm/amd/display/modules/color/color_gamma.h| 11 +-
4 files changed, 186 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index be19e6861189..216e48cec716 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -164,7 +164,7 @@ int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc)
*/
stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
ret = mod_color_calculate_regamma_params(stream->out_transfer_func,
-gamma, true, adev->asic_type
<= CHIP_RAVEN);
+gamma, true, adev->asic_type
<= CHIP_RAVEN, NULL);
dc_gamma_release();
if (!ret) {
stream->out_transfer_func->type = old_type;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 5d95a997fd9f..97c059934feb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -268,7 +268,7 @@ bool cm_helper_translate_curve_to_hw_format(
memset(lut_params, 0, sizeof(struct pwl_params));
memset(seg_distr, 0, sizeof(seg_distr));
- if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
+ if (output_tf->tf == TRANSFER_FUNCTION_PQ || output_tf->tf ==
TRANSFER_FUNCTION_GAMMA22) {
/* 32 segments
* segments are from 2^-25 to 2^7
*/
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index cdcefd087487..2e215c9e5445 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -306,6 +306,18 @@ static struct fixed31_32 translate_from_linear_space(
a1);
}
+static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg)
+{
+ struct fixed31_32 gamma = dc_fixpt_from_fraction(22, 10);
+
+ return translate_from_linear_space(arg,
+ dc_fixpt_zero,
+ dc_fixpt_zero,
+ dc_fixpt_zero,
+ dc_fixpt_zero,
+ gamma);
+}
+
static struct fixed31_32 translate_to_linear_space(
struct fixed31_32 arg,
struct fixed31_32 a0,
@@ -709,6 +721,160 @@ static void build_regamma(struct pwl_float_data_ex
*rgb_regamma,
}
}
+static void hermite_spline_eetf(struct fixed31_32 input_x,
+ struct fixed31_32 max_display,
+ struct fixed31_32 min_display,
+ struct fixed31_32 max_content,
+ struct fixed31_32 *out_x)
+{
+ struct fixed31_32 min_lum_pq;
+ struct fixed31_32 max_lum_pq;
+ struct fixed31_32 max_content_pq;
+ struct fixed31_32 ks;
+ struct fixed31_32 E1;
+ struct fixed31_32 E2;
+ struct fixed31_32 E3;
+ struct fixed31_32 t;
+ struct fixed31_32 t2;
+ struct fixed31_32 t3;
+ struct fixed31_32 two;
+ struct fixed31_32 three;
+ struct fixed31_32 temp1;
+ struct fixed31_32 temp2;
+ struct fixed31_32 a = dc_fixpt_from_fraction(15, 10);
+ struct fixed31_32 b = dc_fixpt_from_fraction(5, 10);
+ struct fixed31_32 epsilon = dc_fixpt_from_fraction(1, 100); //
dc_fixpt_epsilon is a bit too small
+
+ if (dc_fixpt_eq(max_content, dc_fixpt_zero)) {
+ *out_x = dc_fixpt_zero;
+ return;
+ }
+
+ compute_pq(input_x, );
+ compute_pq(dc_fixpt_div(min_display, max_content), _lum_pq);
+ compute_pq(dc_fixpt_div(max_display, max_content), _lum_pq);
+ compute_pq(dc_fixpt_one, _content_pq); // always 1? DAL2 code is
weird
+ a = dc_fixpt_div(dc_fixpt_add(dc_fixpt_one, b), max_content_pq); //
(1+b)/maxContent
+ ks = dc_fixpt_sub(dc_fixpt_mul(a, max_lum_pq), b); // a * max_lum_pq - b
+
+ if (dc_fixpt_lt(E1, ks))
+ E2 = E1;
+ else if (dc_fixpt_le(ks, E1) && dc_fixpt_le(E1, dc_fixpt_one)) {
+
[PATCH 08/26] drm/amd/display: split dccg clock manager into asic folders
From: Dmytro Laktyushkin
Currently dccg contains code related to every dcn revision in
a single file.
This change splits out the dcn parts of code into correct folders
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce/Makefile| 2 +-
.../display/dc/dce/{dce_clocks.c => dce_dccg.c}| 282 +
.../display/dc/dce/{dce_clocks.h => dce_dccg.h}| 48 +++-
.../drm/amd/display/dc/dce100/dce100_resource.c| 2 +-
.../drm/amd/display/dc/dce110/dce110_resource.c| 2 +-
.../drm/amd/display/dc/dce112/dce112_resource.c| 2 +-
.../drm/amd/display/dc/dce120/dce120_resource.c| 2 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c | 278
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.h | 37 +++
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h| 2 +-
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 +-
.../display/dc/inc/hw/{display_clock.h => dccg.h} | 6 +-
15 files changed, 374 insertions(+), 297 deletions(-)
rename drivers/gpu/drm/amd/display/dc/dce/{dce_clocks.c => dce_dccg.c} (74%)
rename drivers/gpu/drm/amd/display/dc/dce/{dce_clocks.h => dce_dccg.h} (74%)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dccg.h
rename drivers/gpu/drm/amd/display/dc/inc/hw/{display_clock.h => dccg.h} (94%)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile
b/drivers/gpu/drm/amd/display/dc/dce/Makefile
index 8f7f0e8b341f..f4ce7f502094 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile
@@ -28,7 +28,7 @@
DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
-dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \
+dce_dccg.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \
dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_dccg.c
similarity index 74%
rename from drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
rename to drivers/gpu/drm/amd/display/dc/dce/dce_dccg.c
index a98020d1b59f..f87d70eeceae 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dccg.c
@@ -23,10 +23,9 @@
*
*/
+#include "dce_dccg.h"
+
#include "reg_helper.h"
-#include "bios_parser_interface.h"
-#include "dc.h"
-#include "dce_clocks.h"
#include "dmcu.h"
#include "core_types.h"
#include "dal_asic_id.h"
@@ -95,28 +94,6 @@ static const struct state_dependent_clocks
dce120_max_clks_by_state[] = {
/*ClocksStatePerformance*/
{ .display_clk_khz = 1133000, .pixel_clk_khz = 60 } };
-/* Starting DID for each range */
-enum dentist_base_divider_id {
- DENTIST_BASE_DID_1 = 0x08,
- DENTIST_BASE_DID_2 = 0x40,
- DENTIST_BASE_DID_3 = 0x60,
- DENTIST_BASE_DID_4 = 0x7e,
- DENTIST_MAX_DID = 0x7f
-};
-
-/* Starting point and step size for each divider range.*/
-enum dentist_divider_range {
- DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */
- DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */
- DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */
- DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */
- DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
- DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */
- DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
- DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */
- DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
-};
-
static int dentist_get_divider_from_did(int did)
{
if (did < DENTIST_BASE_DID_1)
@@ -192,7 +169,7 @@ static int dce_get_dp_ref_freq_khz(struct dccg *dccg)
return dccg_adjust_dp_ref_freq_for_ss(dccg_dce, dp_ref_clk_khz);
}
-static int dce12_get_dp_ref_freq_khz(struct dccg *dccg)
+int dce12_get_dp_ref_freq_khz(struct dccg *dccg)
{
struct dce_dccg *dccg_dce = TO_DCE_DCCG(dccg);
@@ -305,9 +282,7 @@ static int dce_set_clock(
return actual_clock;
}
-static int dce112_set_clock(
- struct dccg *dccg,
- int requested_clk_khz)
+int dce112_set_clock(struct dccg *dccg, int requested_clk_khz)
{
struct dce_dccg *dccg_dce = TO_DCE_DCCG(dccg);
struct bp_set_dce_clock_parameters dce_clk_params;
@@ -416,7 +391,7 @@ static void dce_clock_read_integrated_info(struct dce_dccg
*dccg_dce)
dccg_dce->dfs_bypass_enabled = true;
}
-static void dce_clock_read_ss_info(struct dce_dccg *dccg_dce)
+void dce_clock_read_ss_info(struct dce_dccg *dccg_dce)
{
struct dc_bios
[PATCH 09/26] drm/amd/display: Add support for Freesync 2 HDR and Content to Display Mapping
From: SivapiriyanKumarasamy
[Why]
Freesync 2 HDR and support for HDR content
outside the range of the HDR display
require implementation on Dal 3 to better match
Dal2.
[How]
Add support for Freesync HDR and mapping
of source content to display ranges for better
representation of HDR content.
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c| 2 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 2 +-
.../drm/amd/display/modules/color/color_gamma.c| 175 -
.../drm/amd/display/modules/color/color_gamma.h| 11 +-
4 files changed, 186 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index be19e6861189..216e48cec716 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -164,7 +164,7 @@ int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc)
*/
stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
ret = mod_color_calculate_regamma_params(stream->out_transfer_func,
-gamma, true, adev->asic_type
<= CHIP_RAVEN);
+gamma, true, adev->asic_type
<= CHIP_RAVEN, NULL);
dc_gamma_release();
if (!ret) {
stream->out_transfer_func->type = old_type;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 5d95a997fd9f..97c059934feb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -268,7 +268,7 @@ bool cm_helper_translate_curve_to_hw_format(
memset(lut_params, 0, sizeof(struct pwl_params));
memset(seg_distr, 0, sizeof(seg_distr));
- if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
+ if (output_tf->tf == TRANSFER_FUNCTION_PQ || output_tf->tf ==
TRANSFER_FUNCTION_GAMMA22) {
/* 32 segments
* segments are from 2^-25 to 2^7
*/
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index cdcefd087487..2e215c9e5445 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -306,6 +306,18 @@ static struct fixed31_32 translate_from_linear_space(
a1);
}
+static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg)
+{
+ struct fixed31_32 gamma = dc_fixpt_from_fraction(22, 10);
+
+ return translate_from_linear_space(arg,
+ dc_fixpt_zero,
+ dc_fixpt_zero,
+ dc_fixpt_zero,
+ dc_fixpt_zero,
+ gamma);
+}
+
static struct fixed31_32 translate_to_linear_space(
struct fixed31_32 arg,
struct fixed31_32 a0,
@@ -709,6 +721,160 @@ static void build_regamma(struct pwl_float_data_ex
*rgb_regamma,
}
}
+static void hermite_spline_eetf(struct fixed31_32 input_x,
+ struct fixed31_32 max_display,
+ struct fixed31_32 min_display,
+ struct fixed31_32 max_content,
+ struct fixed31_32 *out_x)
+{
+ struct fixed31_32 min_lum_pq;
+ struct fixed31_32 max_lum_pq;
+ struct fixed31_32 max_content_pq;
+ struct fixed31_32 ks;
+ struct fixed31_32 E1;
+ struct fixed31_32 E2;
+ struct fixed31_32 E3;
+ struct fixed31_32 t;
+ struct fixed31_32 t2;
+ struct fixed31_32 t3;
+ struct fixed31_32 two;
+ struct fixed31_32 three;
+ struct fixed31_32 temp1;
+ struct fixed31_32 temp2;
+ struct fixed31_32 a = dc_fixpt_from_fraction(15, 10);
+ struct fixed31_32 b = dc_fixpt_from_fraction(5, 10);
+ struct fixed31_32 epsilon = dc_fixpt_from_fraction(1, 100); //
dc_fixpt_epsilon is a bit too small
+
+ if (dc_fixpt_eq(max_content, dc_fixpt_zero)) {
+ *out_x = dc_fixpt_zero;
+ return;
+ }
+
+ compute_pq(input_x, );
+ compute_pq(dc_fixpt_div(min_display, max_content), _lum_pq);
+ compute_pq(dc_fixpt_div(max_display, max_content), _lum_pq);
+ compute_pq(dc_fixpt_one, _content_pq); // always 1? DAL2 code is
weird
+ a = dc_fixpt_div(dc_fixpt_add(dc_fixpt_one, b), max_content_pq); //
(1+b)/maxContent
+ ks = dc_fixpt_sub(dc_fixpt_mul(a, max_lum_pq), b); // a * max_lum_pq - b
+
+ if (dc_fixpt_lt(E1, ks))
+ E2 = E1;
+ else if (dc_fixpt_le(ks, E1) && dc_fixpt_le(E1, dc_fixpt_one)) {
+ if (dc_fixpt_lt(epsilon,
[PATCH 07/26] drm/amd/display: clean up base dccg struct
From: Dmytro Laktyushkin
Move things not accessed outside dccg block into dce specific
struct
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c| 49 +-
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h| 8
.../drm/amd/display/dc/dce100/dce100_resource.c| 7
.../drm/amd/display/dc/dce110/dce110_resource.c| 8
.../drm/amd/display/dc/dce112/dce112_resource.c| 8
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 15 ---
.../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 9
7 files changed, 37 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 4d5a37b37919..a98020d1b59f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -244,7 +244,7 @@ static enum dm_pp_clocks_state
dce_get_required_clocks_state(
* lowest RequiredState with the lowest state that satisfies
* all required clocks
*/
- for (i = dccg->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
+ for (i = dccg_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW;
i--)
if (context->bw.dce.dispclk_khz >
dccg_dce->max_clks_by_state[i].display_clk_khz
|| max_pix_clk >
@@ -252,13 +252,13 @@ static enum dm_pp_clocks_state
dce_get_required_clocks_state(
break;
low_req_clk = i + 1;
- if (low_req_clk > dccg->max_clks_state) {
+ if (low_req_clk > dccg_dce->max_clks_state) {
/* set max clock state for high phyclock, invalid on exceeding
display clock */
- if
(dccg_dce->max_clks_by_state[dccg->max_clks_state].display_clk_khz
+ if
(dccg_dce->max_clks_by_state[dccg_dce->max_clks_state].display_clk_khz
< context->bw.dce.dispclk_khz)
low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
else
- low_req_clk = dccg->max_clks_state;
+ low_req_clk = dccg_dce->max_clks_state;
}
return low_req_clk;
@@ -298,7 +298,7 @@ static int dce_set_clock(
/* from power down, we need mark the clock state as ClocksStateNominal
* from HWReset, so when resume we will call pplib voltage regulator.*/
if (requested_clk_khz == 0)
- dccg->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
+ dccg_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
@@ -333,7 +333,7 @@ static int dce112_set_clock(
/* from power down, we need mark the clock state as ClocksStateNominal
* from HWReset, so when resume we will call pplib voltage regulator.*/
if (requested_clk_khz == 0)
- dccg->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
+ dccg_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
/*Program DP ref Clock*/
/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
@@ -839,9 +839,9 @@ static void dce_update_clocks(struct dccg *dccg,
struct dc_state *context,
bool safe_to_lower)
{
+ struct dce_dccg *dccg_dce = TO_DCE_DCCG(dccg);
struct dm_pp_power_level_change_request level_change_req;
int unpatched_disp_clk = context->bw.dce.dispclk_khz;
- struct dce_dccg *dccg_dce = TO_DCE_DCCG(dccg);
/*TODO: W/A for dal3 linux, investigate why this works */
if (!dccg_dce->dfs_bypass_active)
@@ -849,10 +849,10 @@ static void dce_update_clocks(struct dccg *dccg,
level_change_req.power_level = dce_get_required_clocks_state(dccg,
context);
/* get max clock state from PPLIB */
- if ((level_change_req.power_level < dccg->cur_min_clks_state &&
safe_to_lower)
- || level_change_req.power_level >
dccg->cur_min_clks_state) {
+ if ((level_change_req.power_level < dccg_dce->cur_min_clks_state &&
safe_to_lower)
+ || level_change_req.power_level >
dccg_dce->cur_min_clks_state) {
if (dm_pp_apply_power_level_change_request(dccg->ctx,
_change_req))
- dccg->cur_min_clks_state = level_change_req.power_level;
+ dccg_dce->cur_min_clks_state =
level_change_req.power_level;
}
if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz,
dccg->clks.dispclk_khz)) {
@@ -868,14 +868,15 @@ static void dce11_update_clocks(struct dccg *dccg,
struct dc_state *context,
bool safe_to_lower)
{
+ struct dce_dccg *dccg_dce = TO_DCE_DCCG(dccg);
struct dm_pp_power_level_change_request
[PATCH 06/26] drm/amd/display: Freesync does not engage on some displays
From: Harmanprit Tatla
[Why]
Current render margin time is not sufficient to compute exit frame
time for most monitors.
[How]
Declared render margin in FPS to compute a exit frame rate that is
4 FPS above the minimum FPS required to engage FreeSync.
Also did code clean-up to remove redundancies.
Signed-off-by: Harmanprit Tatla
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/modules/freesync/freesync.c| 37 ++
1 file changed, 9 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 4018c7180d00..620a171620ee 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -37,6 +37,8 @@
#define RENDER_TIMES_MAX_COUNT 10
/* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */
#define BTR_EXIT_MARGIN 2000
+/*Threshold to exit fixed refresh rate*/
+#define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 4
/* Number of consecutive frames to check before entering/exiting fixed
refresh*/
#define FIXED_REFRESH_ENTER_FRAME_COUNT 5
#define FIXED_REFRESH_EXIT_FRAME_COUNT 5
@@ -257,40 +259,14 @@ static void apply_below_the_range(struct core_freesync
*core_freesync,
if (in_out_vrr->btr.btr_active) {
in_out_vrr->btr.frame_counter = 0;
in_out_vrr->btr.btr_active = false;
-
- /* Exit Fixed Refresh mode */
- } else if (in_out_vrr->fixed.fixed_active) {
-
- in_out_vrr->fixed.frame_counter++;
-
- if (in_out_vrr->fixed.frame_counter >
- FIXED_REFRESH_EXIT_FRAME_COUNT) {
- in_out_vrr->fixed.frame_counter = 0;
- in_out_vrr->fixed.fixed_active = false;
- }
}
} else if (last_render_time_in_us > max_render_time_in_us) {
/* Enter Below the Range */
- if (!in_out_vrr->btr.btr_active &&
- in_out_vrr->btr.btr_enabled) {
- in_out_vrr->btr.btr_active = true;
-
- /* Enter Fixed Refresh mode */
- } else if (!in_out_vrr->fixed.fixed_active &&
- !in_out_vrr->btr.btr_enabled) {
- in_out_vrr->fixed.frame_counter++;
-
- if (in_out_vrr->fixed.frame_counter >
- FIXED_REFRESH_ENTER_FRAME_COUNT) {
- in_out_vrr->fixed.frame_counter = 0;
- in_out_vrr->fixed.fixed_active = true;
- }
- }
+ in_out_vrr->btr.btr_active = true;
}
/* BTR set to "not active" so disengage */
if (!in_out_vrr->btr.btr_active) {
- in_out_vrr->btr.btr_active = false;
in_out_vrr->btr.inserted_duration_in_us = 0;
in_out_vrr->btr.frames_to_insert = 0;
in_out_vrr->btr.frame_counter = 0;
@@ -375,7 +351,12 @@ static void apply_fixed_refresh(struct core_freesync
*core_freesync,
bool update = false;
unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
- if (last_render_time_in_us + BTR_EXIT_MARGIN < max_render_time_in_us) {
+ //Compute the exit refresh rate and exit frame duration
+ unsigned int exit_refresh_rate_in_milli_hz =
((10/max_render_time_in_us)
+ + (1000*FIXED_REFRESH_EXIT_MARGIN_IN_HZ));
+ unsigned int exit_frame_duration_in_us =
10/exit_refresh_rate_in_milli_hz;
+
+ if (last_render_time_in_us < exit_frame_duration_in_us) {
/* Exit Fixed Refresh mode */
if (in_out_vrr->fixed.fixed_active) {
in_out_vrr->fixed.frame_counter++;
--
2.14.1
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[PATCH 05/26] drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead
From: Dmytro Laktyushkin
This is done to keep things more readable, avoids a true/false flag
in dc interface layer.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++---
.../amd/display/dc/dce100/dce100_hw_sequencer.c| 15 +++--
.../amd/display/dc/dce100/dce100_hw_sequencer.h| 5 ++-
.../amd/display/dc/dce110/dce110_hw_sequencer.c| 30 -
.../amd/display/dc/dce110/dce110_hw_sequencer.h| 9 +++--
.../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 3 +-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 39 +++---
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 8 +++--
8 files changed, 79 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2bbc39de10cc..20dd062d7a33 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -941,7 +941,7 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
if (!dcb->funcs->is_accelerated_mode(dcb))
dc->hwss.enable_accelerated_mode(dc, context);
- dc->hwss.set_bandwidth(dc, context, false);
+ dc->hwss.prepare_bandwidth(dc, context);
/* re-program planes for existing stream, in case we need to
* free up plane resource for later use
@@ -1010,7 +1010,7 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
/* pplib is notified if disp_num changed */
- dc->hwss.set_bandwidth(dc, context, true);
+ dc->hwss.optimize_bandwidth(dc, context);
dc_release_state(dc->current_state);
@@ -1059,7 +1059,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
dc->optimized_required = false;
- dc->hwss.set_bandwidth(dc, context, true);
+ dc->hwss.optimize_bandwidth(dc, context);
return true;
}
@@ -1479,7 +1479,7 @@ static void commit_planes_for_stream(struct dc *dc,
struct pipe_ctx *top_pipe_to_program = NULL;
if (update_type == UPDATE_TYPE_FULL) {
- dc->hwss.set_bandwidth(dc, context, false);
+ dc->hwss.prepare_bandwidth(dc, context);
context_clock_trace(dc, context);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
index 2725eac4baab..5055026e553f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
@@ -105,22 +105,16 @@ bool dce100_enable_display_power_gating(
return false;
}
-void dce100_set_bandwidth(
+void dce100_prepare_bandwidth(
struct dc *dc,
- struct dc_state *context,
- bool decrease_allowed)
+ struct dc_state *context)
{
- int dispclk_khz = context->bw.dce.dispclk_khz;
-
- context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
-
dce110_set_safe_displaymarks(>res_ctx, dc->res_pool);
dc->res_pool->dccg->funcs->update_clocks(
dc->res_pool->dccg,
context,
- decrease_allowed);
- context->bw.dce.dispclk_khz = dispclk_khz;
+ false);
}
/**/
@@ -130,6 +124,7 @@ void dce100_hw_sequencer_construct(struct dc *dc)
dce110_hw_sequencer_construct(dc);
dc->hwss.enable_display_power_gating =
dce100_enable_display_power_gating;
- dc->hwss.set_bandwidth = dce100_set_bandwidth;
+ dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
+ dc->hwss.optimize_bandwidth = dce100_prepare_bandwidth;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
index c6ec0ed6ec3d..acd418515346 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
@@ -33,10 +33,9 @@ struct dc_state;
void dce100_hw_sequencer_construct(struct dc *dc);
-void dce100_set_bandwidth(
+void dce100_prepare_bandwidth(
struct dc *dc,
- struct dc_state *context,
- bool decrease_allowed);
+ struct dc_state *context);
bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
struct dc_bios *dcb,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 0d25dcf6408a..bd3ce10f6309 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
[PATCH 04/26] drm/amd/display: move pplib/smu notification to dccg block
From: Dmytro Laktyushkin
This is done to clear up the clock programming sequence
since the only time we need to notify pplib is after
clock update.
This also renames the clk block to dccg, at the moment
this block contains both clock management and dccg
functionality.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 -
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 21 +-
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc.h| 5 -
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c| 659 +
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h| 6 +-
.../amd/display/dc/dce100/dce100_hw_sequencer.c| 60 +-
.../drm/amd/display/dc/dce100/dce100_resource.c| 4 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c| 212 +--
.../amd/display/dc/dce110/dce110_hw_sequencer.h| 10 +-
.../drm/amd/display/dc/dce110/dce110_resource.c| 8 +-
.../drm/amd/display/dc/dce112/dce112_resource.c| 14 +-
.../drm/amd/display/dc/dce120/dce120_resource.c| 9 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 51 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h| 2 +-
.../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 13 +-
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 -
drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 -
20 files changed, 475 insertions(+), 623 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7c491c91465f..2bbc39de10cc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -957,8 +957,6 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
}
/* Program hardware */
- dc->hwss.ready_shared_resources(dc, context);
-
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = >res_ctx.pipe_ctx[i];
dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
@@ -1020,8 +1018,6 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
dc_retain_state(dc->current_state);
- dc->hwss.optimize_shared_resources(dc);
-
return result;
}
@@ -1448,12 +1444,8 @@ static void commit_planes_do_stream_update(struct dc *dc,
if (stream_update->dpms_off) {
if (*stream_update->dpms_off) {
core_link_disable_stream(pipe_ctx,
KEEP_ACQUIRED_RESOURCE);
-
dc->hwss.pplib_apply_display_requirements(
- dc, dc->current_state);
notify_display_count_to_smu(dc,
dc->current_state);
} else {
-
dc->hwss.pplib_apply_display_requirements(
- dc, dc->current_state);
notify_display_count_to_smu(dc,
dc->current_state);
core_link_enable_stream(dc->current_state, pipe_ctx);
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fb04a4ad141f..f4936f7c5545 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1357,28 +1357,13 @@ static enum dc_status enable_link_dp(
struct dc_link *link = stream->sink->link;
struct dc_link_settings link_settings = {0};
enum dp_panel_mode panel_mode;
- enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
/* get link settings for video mode timing */
decide_link_settings(stream, _settings);
- /* raise clock state for HBR3 if required. Confirmed with HW DCE/DPCS
-* logic for HBR3 still needs Nominal (0.8V) on VDDC rail
-*/
- if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
- max_link_rate = LINK_RATE_HIGH3;
-
- if (link_settings.link_rate == max_link_rate) {
- struct dc_clocks clocks = state->bw.dcn.clk;
-
- /* dce/dcn compat, do not update dispclk */
- clocks.dispclk_khz = 0;
- /* 27mhz = 2700hz= 27000khz */
- clocks.phyclk_khz = link_settings.link_rate * 27000;
-
- state->dis_clk->funcs->update_clocks(
- state->dis_clk, , false);
- }
+ pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
+ link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
+
[PATCH 03/26] drm/amd/display: handle max_vstartup larger than vblank_end
From: Dmytro Laktyushkin
When vstartup is larger than vblank end we need to set v_fp2
to allow for this early start
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 54626682bab2..47f80e0e8be8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -274,10 +274,12 @@ void optc1_program_timing(
* program the reg for interrupt postition.
*/
vertical_line_start = asic_blank_end -
optc->dlg_otg_param.vstartup_start + 1;
- if (vertical_line_start < 0) {
- ASSERT(0);
+ v_fp2 = 0;
+ if (vertical_line_start < 0)
+ v_fp2 = -vertical_line_start;
+ if (vertical_line_start < 0)
vertical_line_start = 0;
- }
+
REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
OTG_VERTICAL_INTERRUPT2_LINE_START,
vertical_line_start);
@@ -296,9 +298,6 @@ void optc1_program_timing(
if (patched_crtc_timing.flags.INTERLACE == 1)
field_num = 1;
}
- v_fp2 = 0;
- if (optc->dlg_otg_param.vstartup_start > asic_blank_end)
- v_fp2 = optc->dlg_otg_param.vstartup_start > asic_blank_end;
/* Interlace */
if (patched_crtc_timing.flags.INTERLACE == 1) {
--
2.14.1
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[PATCH 01/26] drm/amd/display: fix bug of accessing invalid memory
From: Su Sung Chung
[Why]
A loop inside of build_evenly_distributed_points function that traverse through
the array of points become an infinite loop when m_GammaUpdates does not
get assigned to any value.
[How]
In DMColor, clear m_gammaIsValid bit just before writting all Zeromem for
m_GammaUpdates, to prevent calling build_evenly_distributed_points
before m_GammaUpdates gets assigned to some value.
Signed-off-by: Su Sung Chung
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 15427f4fc990..cdcefd087487 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1069,10 +1069,14 @@ static void build_evenly_distributed_points(
struct dividers dividers)
{
struct gamma_pixel *p = points;
- struct gamma_pixel *p_last = p + numberof_points - 1;
+ struct gamma_pixel *p_last;
uint32_t i = 0;
+ // This function should not gets called with 0 as a parameter
+ ASSERT(numberof_points > 0);
+ p_last = p + numberof_points - 1;
+
do {
struct fixed31_32 value = dc_fixpt_from_fraction(i,
numberof_points - 1);
@@ -1083,7 +1087,7 @@ static void build_evenly_distributed_points(
++p;
++i;
- } while (i != numberof_points);
+ } while (i < numberof_points);
p->r = dc_fixpt_div(p_last->r, dividers.divider1);
p->g = dc_fixpt_div(p_last->g, dividers.divider1);
--
2.14.1
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[PATCH 02/26] drm/amd/display: dc 3.2.01
From: Fatemeh Darbehani Signed-off-by: Fatemeh Darbehani Reviewed-by: Steven Chiu Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 199527171100..4a05f86aba12 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.68" +#define DC_VER "3.2.01" #define MAX_SURFACES 3 #define MAX_STREAMS 6 -- 2.14.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/26] DC Patches 10 Oct, 2018
Summary of Changes
*Refactor dce clocks
*Implement PERF_TRACE on linux
*Refactor dc to smu interface
Bhawanpreet Lakha (2):
drm/amd/display: explicit uint64_t casting
drm/amd/display: rename cstate_pstate_watermarks_st1
Charlene Liu (1):
drm/amd/display: Check if hubp function hooks exist before calling
them
David Francis (3):
drm/amd/display: initialize dc_transfer_func->ctx
drm/amd/display: implement PERF_TRACE on Linux
drm/amd/display: Disable 4k 60 HDMI on DCE11
Dmytro Laktyushkin (7):
drm/amd/display: handle max_vstartup larger than vblank_end
drm/amd/display: move pplib/smu notification to dccg block
drm/amd/display: remove safe_to_lower flag from dc, use 2 functions
instead
drm/amd/display: clean up base dccg struct
drm/amd/display: split dccg clock manager into asic folders
drm/amd/display: rename dccg to clk_mgr
drm/amd/display: add dccg block
Eric Bernstein (1):
drm/amd/display: Add link encoder dp_ycbcr420_supported feature flag
Eric Yang (1):
drm/amd/display: fix report display count logic
Fatemeh Darbehani (4):
drm/amd/display: dc 3.2.01
drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h -
part1
drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h -
part2
drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h -
part3
Harmanprit Tatla (1):
drm/amd/display: Freesync does not engage on some displays
Nevenko Stupar (1):
drm/amd/display: expose hwseq functions and add registers
SivapiriyanKumarasamy (4):
drm/amd/display: Add support for Freesync 2 HDR and Content to Display
Mapping
drm/amd/display: dc 3.2.02
drm/amd/display: Fix incorrect end slope of EETF
drm/amd/display: Remove stream_res tg null check in commit planes
Su Sung Chung (1):
drm/amd/display: fix bug of accessing invalid memory
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c| 2 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 74 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h | 2 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 21 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 88 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 21 +-
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_stream.c| 1 +
drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 1 +
drivers/gpu/drm/amd/display/dc/dc.h| 9 +-
drivers/gpu/drm/amd/display/dc/dc_types.h | 22 +
drivers/gpu/drm/amd/display/dc/dce/Makefile| 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 879 +++
.../display/dc/dce/{dce_clocks.h => dce_clk_mgr.h} | 105 ++-
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c| 947 -
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 50 ++
.../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +-
.../amd/display/dc/dce100/dce100_hw_sequencer.c| 73 +-
.../amd/display/dc/dce100/dce100_hw_sequencer.h| 5 +-
.../drm/amd/display/dc/dce100/dce100_resource.c| 25 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c| 230 +
.../amd/display/dc/dce110/dce110_hw_sequencer.h| 11 +-
.../drm/amd/display/dc/dce110/dce110_resource.c| 32 +-
.../drm/amd/display/dc/dce112/dce112_resource.c| 39 +-
.../drm/amd/display/dc/dce120/dce120_resource.c| 20 +-
.../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 3 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 41 +-
drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 2 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 380 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h | 37 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 6 +-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 133 ++-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 20 +
.../drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 8 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 31 +-
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 12 +-
drivers/gpu/drm/amd/display/dc/dm_services.h | 13 +-
drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h| 5 +-
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 +-
.../dc/inc/hw/{display_clock.h => clk_mgr.h} | 34 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 44 +
.../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 3 +-
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +-
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 13 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 -
.../drm/amd/display/modules/color/color_gamma.c| 184 +++-
.../drm/amd/display/modules/color/color_gamma.h| 11 +-
.../drm/amd/display/modules/freesync/freesync.c
[PATCH 15/18] drm/amdgpu/vcn:Remove SPG mode unused steps during vcn start
Remove Sitatic Power Gate mode unused steps during vcn start Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 30 ++ 1 file changed, 2 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index afb174f..93e2a40 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -784,24 +784,6 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, ~UVD_MASTINT_EN__VCPU_EN_MASK); - /* stall UMC and register bus before resetting VCPU */ - WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), - UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, - ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); - mdelay(1); - - /* put LMI, VCPU, RBC etc... into reset */ - WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, - UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | - UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | - UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | - UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | - UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | - UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | - UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | - UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); - mdelay(5); - /* initialize VCN memory controller */ tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp| @@ -844,14 +826,8 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3); - /* take all subblocks out of reset, except VCPU */ - WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, - UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); - mdelay(5); - /* enable VCPU clock */ - WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, - UVD_VCPU_CNTL__CLK_EN_MASK); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); /* enable UMC */ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, @@ -891,8 +867,7 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) } /* enable master interrupt */ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), - (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), - ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); + UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); /* enable system interrupt for JRBC, TODO: move to set interrupt*/ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), @@ -908,7 +883,6 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); - tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/18] drm/amdgpu/vcn:Remove DPG mode unused steps during vcn start
Remove Dynamic Power Gate mode unused steps during VCN start Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 28 +--- 1 file changed, 1 insertion(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index afc7a1d..5740cca 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -981,22 +981,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); - /* stall UMC and register bus before resetting VCPU */ - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, - UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); - - /* put LMI, VCPU, RBC etc... into reset */ - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, - UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | - UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | - UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | - UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | - UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | - UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | - UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | - UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, - 0x, 0); - /* initialize VCN memory controller */ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | @@ -1039,14 +1023,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0x, 0); WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0x, 0); - /* take all subblocks out of reset, except VCPU */ - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, - UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0x, 0); - - /* enable VCPU clock */ - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, - UVD_VCPU_CNTL__CLK_EN_MASK, 0x, 0); - /* enable UMC */ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, 0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); @@ -1056,8 +1032,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) /* enable master interrupt */ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, - (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), - (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0); + UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); vcn_v1_0_clock_gating_dpg_mode(adev, 1); /* setup mmUVD_LMI_CTRL */ @@ -1085,7 +1060,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); - tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/18] drm/amdgpu/vcn:Update SPG mode VCN memory control
Update Static Power Gate mode VCN memory control Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 624a255..73301a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -787,13 +787,12 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) mdelay(5); /* initialize VCN memory controller */ - WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, - (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | - UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | - UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | - UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | - UVD_LMI_CTRL__REQ_MODE_MASK | - 0x0010L); + tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); + WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp| + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK| + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); #ifdef __BIG_ENDIAN /* swap (8 in 32) RB and IB */ -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 02/18] drm/amdgpu/vcn:Update latest UVD_MPC register for VCN
Update latest UVD_MPC register for VCN. Use defined macro to replace value for readability. Signed-off-by: James Zhu Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 52 +++ 1 file changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index e928241..5608d21 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -785,12 +785,27 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) #endif WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040); - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0); - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040); - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0); - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0); - WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88); + tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); + tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; + tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; + WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); + + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, + ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | + (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | + (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | + (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); + + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, + ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | + (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | + (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | + (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); + + WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, + ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | + (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | + (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); /* take all subblocks out of reset, except VCPU */ WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, @@ -981,12 +996,25 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) #endif WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0x, 0); - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040, 0x, 0); - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0, 0x, 0); - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040, 0x, 0); - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0, 0x, 0); - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_ALU, 0, 0x, 0); - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 0x88, 0x, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL, + 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0x, 0); + + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, + ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | +(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | +(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | +(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0x, 0); + + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, + ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | +(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | +(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | +(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0x, 0); + + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, + ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | +(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | +(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0x, 0); vcn_v1_0_mc_resume_dpg_mode(adev); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/18] VCN start/stop clean up
Clean up current VCN start/stop function, and update with latest firmware/hardware implemention. James Zhu (18): drm/amdgpu/vcn:Add new register offset/mask for VCN drm/amdgpu/vcn:Update latest UVD_MPC register for VCN drm/amdgpu/vcn:Update latest spg mode stop for VCN drm/amdgpu/vcn:Add ring W/R PTR check for VCN DPG mode stop drm/amdgpu/vcn:Reduce unnecessary local variable drm/amdgpu/vcn:Update DPG mode VCN memory control drm/amdgpu/vcn:Update DPG mode VCN global tiling registers drm/amdgpu/vcn:Add DPG mode Register XX check drm/amdgpu/vcn:Remove DPG mode unused steps during vcn start drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode start drm/amdgpu/vcn:Update SPG mode VCN memory control drm/amdgpu/vcn:Update SPG mode VCN global tiling drm/amdgpu/vcn:Move SPG mode mc resume after MPC control drm/amdgpu/vcn:Add SPG mode Register XX check drm/amdgpu/vcn:Remove SPG mode unused steps during vcn start drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode drm/amdgpu/vcn:Set VCPU busy after gate power during vcn SPG start drm/amdgpu/vcn:Update SPG mode UVD status clear drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 288 - .../drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 14 + .../drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 18 ++ 3 files changed, 201 insertions(+), 119 deletions(-) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/18] drm/amdgpu/vcn:Update DPG mode VCN global tiling registers
Update Dynamic Power Gate mode VCN global tiling registers Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 0f3597c..de57e6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -371,16 +371,27 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 0x, 0); + /* VCN global tiling registers */ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config, 0x, 0); WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config, 0x, 0); WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config, 0x, 0); - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, - adev->gfx.config.gb_addr_config, 0x, 0); - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, - adev->gfx.config.gb_addr_config, 0x, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0x, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0x, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0x, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0x, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0x, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0x, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0x, 0); } /** -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/18] drm/amdgpu/vcn:Add ring W/R PTR check for VCN DPG mode stop
Add ring write/read pointer check for VCN dynamic power gate mode
stop,to make sure that no job is left in ring before turn off DPG mode.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 029ed6d..a609486 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1171,6 +1171,16 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device
*adev)
UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
+ if (ret_code) {
+ int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFF;
+ /* wait for read ptr to be equal to write ptr */
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0x,
ret_code);
+
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
+ UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
+ }
+
/* disable dynamic power gating mode */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
--
2.7.4
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[PATCH 08/18] drm/amdgpu/vcn:Add DPG mode Register XX check
Add Dynamic Power Gate mode Register XX check Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index de57e6d..afc7a1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -37,6 +37,11 @@ #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" +#define mmUVD_RBC_XX_IB_REG_CHECK 0x05ab +#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1 +#define mmUVD_REG_XX_MASK 0x05ac +#define mmUVD_REG_XX_MASK_BASE_IDX 1 + static int vcn_v1_0_stop(struct amdgpu_device *adev); static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); @@ -1031,6 +1036,9 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) vcn_v1_0_mc_resume_dpg_mode(adev); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0x, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0x, 0); + /* take all subblocks out of reset, except VCPU */ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0x, 0); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 10/18] drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode start
Apply new UMC enable for VNC Dynamic Power Gate mode start Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 5740cca..624a255 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1023,13 +1023,14 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0x, 0); WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0x, 0); - /* enable UMC */ - WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, - 0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); - /* boot up the VCPU */ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0x, 0); + /* enable UMC */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, + 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, + 0x, 0); + /* enable master interrupt */ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 17/18] drm/amdgpu/vcn:Set VCPU busy after gate power during vcn SPG start
Set VCPU busy after gate power during vcn Static Power Gate start Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 153f23a..d8fe14d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -777,6 +777,10 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) lmi_swap_cntl = 0; vcn_1_0_disable_static_power_gating(adev); + + tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; + WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); + /* disable clock gating */ vcn_v1_0_disable_clock_gating(adev); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/18] drm/amdgpu/vcn:Move SPG mode mc resume after MPC control
Move Static Power Gate mode mc resume after MPC control Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 29f711b..3275eaf 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -780,8 +780,6 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) /* disable clock gating */ vcn_v1_0_disable_clock_gating(adev); - vcn_v1_0_mc_resume_spg_mode(adev); - /* disable interupt */ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, ~UVD_MASTINT_EN__VCPU_EN_MASK); @@ -840,6 +838,8 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); + vcn_v1_0_mc_resume_spg_mode(adev); + /* take all subblocks out of reset, except VCPU */ WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 16/18] drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode
Apply new UMC enable for VNC Dynamic Power Gate mode
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 93e2a40..153f23a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -829,13 +829,18 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device
*adev)
/* enable VCPU clock */
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
+ /* boot up the VCPU */
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
+ ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+
/* enable UMC */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
- /* boot up the VCPU */
- WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
- mdelay(10);
+ tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
for (i = 0; i < 10; ++i) {
uint32_t status;
--
2.7.4
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[PATCH 06/18] drm/amdgpu/vcn:Update DPG mode VCN memory control
Update Dynamic Power Gate mode VCN memory control Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index e597116..0f3597c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -983,11 +983,13 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) /* initialize VCN memory controller */ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, - (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | + (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | UVD_LMI_CTRL__REQ_MODE_MASK | + UVD_LMI_CTRL__CRC_RESET_MASK | + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 0x0010L, 0x, 0); #ifdef __BIG_ENDIAN @@ -1041,13 +1043,14 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) vcn_v1_0_clock_gating_dpg_mode(adev, 1); /* setup mmUVD_LMI_CTRL */ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, - (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | - UVD_LMI_CTRL__CRC_RESET_MASK | - UVD_LMI_CTRL__MASK_MC_URGENT_MASK | - UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | - UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | - (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | - 0x0010L), 0x, 1); + (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__REQ_MODE_MASK | + UVD_LMI_CTRL__CRC_RESET_MASK | + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | + 0x0010L, 0x, 1); tmp = adev->gfx.config.gb_addr_config; /* setup VCN global tiling registers */ -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/18] drm/amdgpu/vcn:Update SPG mode VCN global tiling
Update Static Power Gate mode VCN global tiling Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 73301a9..29f711b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -325,6 +325,24 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) adev->gfx.config.gb_addr_config); WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); } static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 05/18] drm/amdgpu/vcn:Reduce unnecessary local variable
Reduce unnecessary local variable.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index a609486..e597116 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -938,7 +938,7 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device
*adev)
static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring = >vcn.ring_dec;
- uint32_t rb_bufsz, tmp, reg_data;
+ uint32_t rb_bufsz, tmp;
uint32_t lmi_swap_cntl;
/* disable byte swapping */
@@ -947,19 +947,19 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device
*adev)
vcn_1_0_enable_static_power_gating(adev);
/* enable dynamic power gating mode */
- reg_data = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
- reg_data |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
- reg_data |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
- WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data);
+ tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
+ tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
+ tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
+ WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
/* enable clock gating */
vcn_v1_0_clock_gating_dpg_mode(adev, 0);
/* enable VCPU clock */
- reg_data = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
- reg_data |= UVD_VCPU_CNTL__CLK_EN_MASK;
- reg_data |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, reg_data, 0x, 0);
+ tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
+ tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
+ tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
+ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0x, 0);
/* disable interupt */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
--
2.7.4
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[PATCH 18/18] drm/amdgpu/vcn:Update SPG mode UVD status clear
Update Static Power Gate mode UVD status clear Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index d8fe14d..bc64706 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -883,9 +883,9 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); - /* clear the bit 4 of VCN_STATUS */ - WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, - ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); + /* clear the busy bit of UVD_STATUS */ + tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; + WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); /* force RBC into idle state */ rb_bufsz = order_base_2(ring->ring_size); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/18] drm/amdgpu/vcn:Add SPG mode Register XX check
Add Static Power Gate mode Register XX check Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 3275eaf..afb174f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -840,6 +840,10 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) vcn_v1_0_mc_resume_spg_mode(adev); + WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10); + WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, + RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3); + /* take all subblocks out of reset, except VCPU */ WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 03/18] drm/amdgpu/vcn:Update latest spg mode stop for VCN
Update latest static power gate mode stop function for VCN
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 41 ++-
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 5608d21..029ed6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1123,28 +1123,39 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
*/
static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
{
- /* force RBC into idle state */
- WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
+ int ret_code, tmp;
- /* Stall UMC and register bus before resetting VCPU */
- WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
- UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
- mdelay(1);
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7,
ret_code);
+
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
/* put VCPU into reset */
- WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
- UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
- mdelay(5);
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+ UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
+ ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
/* disable VCPU clock */
- WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__CLK_EN_MASK);
- /* Unstall UMC and register bus */
- WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+ /* reset LMI UMC/LMI */
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+ UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
+ ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
+
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+ UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
+ ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
- WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
+ WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
vcn_v1_0_enable_clock_gating(adev);
vcn_1_0_enable_static_power_gating(adev);
--
2.7.4
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[PATCH 01/18] drm/amdgpu/vcn:Add new register offset/mask for VCN
Add new register offset/mask for VCN to support latest VCN implementation. Signed-off-by: James Zhu --- .../gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 14 ++ .../gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 18 ++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h index 4b7da58..442ca7c 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h @@ -82,6 +82,18 @@ #define mmUVD_LCM_CGC_CNTRL 0x0123 #define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 +#define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x0184 +#define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x0185 +#define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x0186 +#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_MIF_CURR_ADDR_CONFIG 0x0192 +#define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_MIF_REF_ADDR_CONFIG 0x0193 +#define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x01c5 +#define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1 // addressBlock: uvd_uvdnpdec // base address: 0x2 @@ -327,6 +339,8 @@ #define mmUVD_LMI_VM_CTRL_BASE_IDX 1 #define mmUVD_LMI_SWAP_CNTL 0x056d #define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1 +#define mmUVD_MPC_CNTL 0x0577 +#define mmUVD_MPC_CNTL_BASE_IDX 1 #define mmUVD_MPC_SET_MUXA0 0x0579 #define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 #define mmUVD_MPC_SET_MUXA1 0x057a diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h index 26382f5..63457f9 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h @@ -985,6 +985,7 @@ #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x0001L #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x0002L #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x0004L @@ -993,6 +994,7 @@ #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x0100L #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x0600L #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800L +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FEL //UVD_MASTINT_EN #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 #define UVD_MASTINT_EN__VCPU_EN__SHIFT
Re: [PATCH -next] drm/amdgpu: remove set but not used variable 'header'
On Wed, Sep 26, 2018 at 11:01 AM YueHaibing wrote:
>
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c: In function 'amdgpu_ucode_init_bo':
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:431:39: warning:
> variable 'header' set but not used [-Wunused-but-set-variable]
>
> Signed-off-by: YueHaibing
Applied. Thanks,
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> index 1fa8bc3..afd5cf3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
> @@ -428,7 +428,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
> uint64_t fw_offset = 0;
> int i, err;
> struct amdgpu_firmware_info *ucode = NULL;
> - const struct common_firmware_header *header = NULL;
>
> if (!adev->firmware.fw_size) {
> dev_warn(adev->dev, "No ip firmware need to load\n");
> @@ -465,7 +464,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
> for (i = 0; i < adev->firmware.max_ucodes; i++) {
> ucode = >firmware.ucode[i];
> if (ucode->fw) {
> - header = (const struct common_firmware_header
> *)ucode->fw->data;
> amdgpu_ucode_init_single_fw(adev, ucode,
> adev->firmware.fw_buf_mc + fw_offset,
> adev->firmware.fw_buf_ptr
> + fw_offset);
> if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
>
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Re: [PATCH -next] drm/amdgpu: remove set but not used variable 'ring' in psp_v11_0_ring_stop
On Mon, Oct 1, 2018 at 3:26 AM YueHaibing wrote:
>
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c: In function 'psp_v11_0_ring_stop':
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c:309:19: warning:
> variable 'ring' set but not used [-Wunused-but-set-variable]
>
> Signed-off-by: YueHaibing
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> index 9217af0..3f3fac2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> @@ -306,11 +306,8 @@ static int psp_v11_0_ring_stop(struct psp_context *psp,
> enum psp_ring_type ring_type)
> {
> int ret = 0;
> - struct psp_ring *ring;
> struct amdgpu_device *adev = psp->adev;
>
> - ring = >km_ring;
> -
> /* Write the ring destroy command to C2PMSG_64 */
> WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
> GFX_CTRL_CMD_ID_DESTROY_RINGS);
>
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Re: [PATCH -next] drm/amdkfd: Remove set but not used variable 'preempt_all_queues'
On Tue, Oct 9, 2018 at 3:37 AM YueHaibing wrote:
>
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c: In function
> 'destroy_queue_cpsch':
> drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:1366:7: warning:
> variable 'preempt_all_queues' set but not used [-Wunused-but-set-variable]
>
> It never used since introduct in
> commit 992839ad64f2 ("drm/amdkfd: Add static user-mode queues support")
>
> Signed-off-by: YueHaibing
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index 4f22e74..06d38b7 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -1363,9 +1363,6 @@ static int destroy_queue_cpsch(struct
> device_queue_manager *dqm,
> {
> int retval;
> struct mqd_manager *mqd_mgr;
> - bool preempt_all_queues;
> -
> - preempt_all_queues = false;
>
> retval = 0;
>
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Re: [PATCH][drm-next] drm/amdgpu/powerplay: fix missing break in switch statements
On Tue, Oct 9, 2018 at 6:44 AM Huang Rui wrote:
>
> On Mon, Oct 08, 2018 at 05:22:28PM +0100, Colin King wrote:
> > From: Colin Ian King
> >
> > There are several switch statements that are missing break statements.
> > Add missing breaks to handle any fall-throughs corner cases.
> >
> > Detected by CoverityScan, CID#1457175 ("Missing break in switch")
> >
> > Fixes: 18aafc59b106 ("drm/amd/powerplay: implement fw related smu interface
> > for iceland.")
> > Signed-off-by: Colin Ian King
>
> Acked-by: Huang Rui
>
Applied. thanks!
Alex
> > ---
> > drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 2 ++
> > drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c| 2 ++
> > drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 ++
> > drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 2 ++
> > drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 2 ++
> > 5 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> > index 18643e06bc6f..669bd0c2a16c 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> > @@ -2269,11 +2269,13 @@ static uint32_t ci_get_offsetof(uint32_t type,
> > uint32_t member)
> > case DRAM_LOG_BUFF_SIZE:
> > return offsetof(SMU7_SoftRegisters,
> > DRAM_LOG_BUFF_SIZE);
> > }
> > + break;
> > case SMU_Discrete_DpmTable:
> > switch (member) {
> > case LowSclkInterruptThreshold:
> > return offsetof(SMU7_Discrete_DpmTable,
> > LowSclkInterruptT);
> > }
> > + break;
> > }
> > pr_debug("can't get the offset of type %x member %x\n", type, member);
> > return 0;
> > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > index ec14798e87b6..bddd6d09f887 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> > @@ -2331,6 +2331,7 @@ static uint32_t fiji_get_offsetof(uint32_t type,
> > uint32_t member)
> > case DRAM_LOG_BUFF_SIZE:
> > return offsetof(SMU73_SoftRegisters,
> > DRAM_LOG_BUFF_SIZE);
> > }
> > + break;
> > case SMU_Discrete_DpmTable:
> > switch (member) {
> > case UvdBootLevel:
> > @@ -2340,6 +2341,7 @@ static uint32_t fiji_get_offsetof(uint32_t type,
> > uint32_t member)
> > case LowSclkInterruptThreshold:
> > return offsetof(SMU73_Discrete_DpmTable,
> > LowSclkInterruptThreshold);
> > }
> > + break;
> > }
> > pr_warn("can't get the offset of type %x member %x\n", type, member);
> > return 0;
> > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > index 73aa368a454e..2d4c7f167b88 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> > @@ -2237,11 +2237,13 @@ static uint32_t iceland_get_offsetof(uint32_t type,
> > uint32_t member)
> > case DRAM_LOG_BUFF_SIZE:
> > return offsetof(SMU71_SoftRegisters,
> > DRAM_LOG_BUFF_SIZE);
> > }
> > + break;
> > case SMU_Discrete_DpmTable:
> > switch (member) {
> > case LowSclkInterruptThreshold:
> > return offsetof(SMU71_Discrete_DpmTable,
> > LowSclkInterruptThreshold);
> > }
> > + break;
> > }
> > pr_warn("can't get the offset of type %x member %x\n", type, member);
> > return 0;
> > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > index ae8378ed32ee..a2ba5b012866 100644
> > --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> > @@ -2619,6 +2619,7 @@ static uint32_t tonga_get_offsetof(uint32_t type,
> > uint32_t member)
> > case DRAM_LOG_BUFF_SIZE:
> > return offsetof(SMU72_SoftRegisters,
> > DRAM_LOG_BUFF_SIZE);
> > }
> > + break;
> > case SMU_Discrete_DpmTable:
> > switch (member) {
> > case UvdBootLevel:
> > @@ -2628,6 +2629,7 @@ static uint32_t tonga_get_offsetof(uint32_t type,
> > uint32_t member)
> > case LowSclkInterruptThreshold:
> > return offsetof(SMU72_Discrete_DpmTable,
> > LowSclkInterruptThreshold);
> > }
> > + break;
> > }
> > pr_warn("can't get the offset of type %x member %x\n", type, member);
> > return 0;
> >
Re: [PATCH] drm/amdgpu: Suppress keypresses from ACPI_VIDEO events
On Fri, Sep 21, 2018 at 8:44 PM Lyude Paul wrote:
>
> Currently we return NOTIFY_DONE for any event which we don't think is
> ours. However, many laptops will send more then just an ATIF event and
> will also send an ACPI_VIDEO_NOTIFY_PROBE event as well. Since we don't
> check for this, we return NOTIFY_DONE which causes a keypress for the
> ACPI event to be propogated to userspace. This is the equivalent of
> someone pressing the display key on a laptop every time there's a
> hotplug event.
>
> So, check for ACPI_VIDEO_NOTIFY_PROBE events and suppress keypresses
> from them.
>
> Signed-off-by: Lyude Paul
> Cc: sta...@vger.kernel.org
Applied. Thanks! Sorry for the delay.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 17 -
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index 353993218f21..f008804f0b97 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -358,7 +358,9 @@ static int amdgpu_atif_get_sbios_requests(struct
> amdgpu_atif *atif,
> *
> * Checks the acpi event and if it matches an atif event,
> * handles it.
> - * Returns NOTIFY code
> + *
> + * Returns:
> + * NOTIFY_BAD or NOTIFY_DONE, depending on the event.
> */
> static int amdgpu_atif_handler(struct amdgpu_device *adev,
>struct acpi_bus_event *event)
> @@ -372,11 +374,16 @@ static int amdgpu_atif_handler(struct amdgpu_device
> *adev,
> if (strcmp(event->device_class, ACPI_VIDEO_CLASS) != 0)
> return NOTIFY_DONE;
>
> + /* Is this actually our event? */
> if (!atif ||
> !atif->notification_cfg.enabled ||
> - event->type != atif->notification_cfg.command_code)
> - /* Not our event */
> - return NOTIFY_DONE;
> + event->type != atif->notification_cfg.command_code) {
> + /* These events will generate keypresses otherwise */
> + if (event->type == ACPI_VIDEO_NOTIFY_PROBE)
> + return NOTIFY_BAD;
> + else
> + return NOTIFY_DONE;
> + }
>
> if (atif->functions.sbios_requests) {
> struct atif_sbios_requests req;
> @@ -385,7 +392,7 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
> count = amdgpu_atif_get_sbios_requests(atif, );
>
> if (count <= 0)
> - return NOTIFY_DONE;
> + return NOTIFY_BAD;
>
> DRM_DEBUG_DRIVER("ATIF: %d pending SBIOS requests\n", count);
>
> --
> 2.17.1
>
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Re: [PATCH 3/3] drm/amdgpu: Remove wrong fw loading type warning
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Rex Zhu
Sent: Wednesday, October 10, 2018 9:28:15 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH 3/3] drm/amdgpu: Remove wrong fw loading type warning
Remove the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 971549f..d91f378 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,8 +297,6 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
- pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
case CHIP_RAVEN:
--
1.9.1
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Re: [PATCH 2/2] drm/amd/powerplay: hint when power profile setting is not supported
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Evan Quan
Sent: Wednesday, October 10, 2018 4:13:15 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH 2/2] drm/amd/powerplay: hint when power profile setting is not
supported
Give user some hints when the power profile setting is not supported.
Change-Id: Iba2b938d02a039ccdee32f9aca185f79fd818796
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 6bc8e9c08b0c..343d7f506bb4 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -897,9 +897,14 @@ static int pp_set_power_profile_mode(void *handle, long
*input, uint32_t size)
pr_info("%s was not implemented.\n", __func__);
return ret;
}
+
+ if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+ pr_info("power profile setting is for manual dpm mode only.\n");
+ return ret;
+ }
+
mutex_lock(>smu_lock);
- if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
- ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input,
size);
+ ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
mutex_unlock(>smu_lock);
return ret;
}
--
2.19.1
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Re: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
I think it's useful to keep around for bringup and early in the asic lifecycle.
Alex
From: Zhu, Rex
Sent: Tuesday, October 9, 2018 11:39:49 PM
To: Deucher, Alexander; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Ok.
BTW, Maybe we can remove the module parameter amdgpu_fw_load_type suppor .
It is only used for bring up/debug.
Best Regards
Rex
From: Deucher, Alexander
Sent: Wednesday, October 10, 2018 3:31 AM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Maybe just drop the warning altogether? We only support SMU loading on VI at
this point. Otherwise, we'll need to update this if we ever add a new fw
loading type.
Alex
From: amd-gfx on behalf of Rex Zhu
Sent: Tuesday, October 9, 2018 11:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH v2 4/5] drm/amdgpu: Fix unnecessary warning in dmesg
Fix the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
v2: fix typo
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 971549f..01d794d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,7 +297,7 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
+ if (load_type == AMDGPU_FW_LOAD_DIRECT || load_type ==
AMDGPU_FW_LOAD_PSP)
pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
--
1.9.1
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amdgpu ac adaptor bug
I just bisected the kernel and i have found the commit that caused the bug: https://github.com/torvalds/linux/commit/320b164abb32db876866a4ff8c2cb710524ac6ea ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 3/5] drm/amdgpu: Extract the function of fw loading out of powerplay
Sounds good to me.
Alex
From: amd-gfx on behalf of Zhu, Rex
Sent: Tuesday, October 9, 2018 9:44 PM
To: Alex Deucher
Cc: amd-gfx list
Subject: RE: [PATCH 3/5] drm/amdgpu: Extract the function of fw loading out of
powerplay
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, October 10, 2018 3:28 AM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 3/5] drm/amdgpu: Extract the function of fw loading out
> of powerplay
>
> On Tue, Oct 9, 2018 at 8:45 AM Rex Zhu wrote:
> >
> > So there is no dependence between gfx/sdma/smu.
> > and for Vi, after IH hw_init, driver load all the smu/gfx/sdma fw. for
> > AI, fw loading is controlled by PSP, after psp hw init, we call the
> > function to check smu fw version.
> >
> > Signed-off-by: Rex Zhu
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 30
> ++
> > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11
> > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 --
> > drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 20 ---
> > drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
> > drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 8 ++
> > drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5
> > 7 files changed, 32 insertions(+), 51 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 4787571..a6766b3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -1525,6 +1525,24 @@ static int amdgpu_device_ip_early_init(struct
> amdgpu_device *adev)
> > return 0;
> > }
> >
> > +static int amdgpu_device_fw_loading(struct amdgpu_device *adev,
> > +uint32_t index) {
> > + int r = 0;
> > +
> > + if ((adev->asic_type < CHIP_VEGA10
> > +&& (adev->ip_blocks[index].version->type ==
> AMD_IP_BLOCK_TYPE_IH))
> > +|| (adev->asic_type >= CHIP_VEGA10
> > +&& (adev->ip_blocks[index].version->type ==
> > + AMD_IP_BLOCK_TYPE_PSP))) {
>
> This seems kind of fragile. If we change the order again at some point, it
> will
> break. How about we check whether hw_init/resume is done or not on the
> blocks we care about or move the checks into the callers and only call when
> we need it?
Hi Alex,
How about split hw_init to hw_init_phase1 and hw_init_phase2 as resume?
We loaded fw(call psp_hw_init and start_smu) between phase1 and phase2.
Regards
Rex
> > + if (adev->powerplay.pp_funcs->load_firmware) {
> > + r = adev->powerplay.pp_funcs->load_firmware(adev-
> >powerplay.pp_handle);
> > + if (r) {
> > + pr_err("firmware loading failed\n");
> > + return r;
> > + }
> > + }
> > + }
> > + return 0;
> > +}
> > /**
> > * amdgpu_device_ip_init - run init for hardware IPs
> > *
> > @@ -1595,6 +1613,9 @@ static int amdgpu_device_ip_init(struct
> amdgpu_device *adev)
> > return r;
> > }
> > adev->ip_blocks[i].status.hw = true;
> > + r = amdgpu_device_fw_loading(adev, i);
> > + if (r)
> > + return r;
> > }
> >
> > amdgpu_xgmi_add_device(adev);
> > @@ -2030,6 +2051,9 @@ static int
> amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
> > DRM_INFO("RE-INIT: %s %s\n",
> > block->version->funcs->name,
> r?"failed":"succeeded");
> > if (r)
> > return r;
> > + r = amdgpu_device_fw_loading(adev, i);
> > + if (r)
> > + return r;
> > }
> > }
> >
> > @@ -2098,6 +2122,9 @@ static int
> amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
> >
> > adev->ip_blocks[i].version->funcs->name, r);
> > return r;
> > }
> > + r = amdgpu_device_fw_loading(adev, i);
> > + if (r)
> > + return r;
> > }
> > }
> >
> > @@ -2134,6 +2161,9 @@ static int
> amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
> > adev->ip_blocks[i].version->funcs->name,
> > r);
> > return r;
> > }
> > + r = amdgpu_device_fw_loading(adev, i);
> > + if (r)
> > + return r;
> > }
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > index 8439f9a..3d0f277 100644
> > ---
Re: [PATCH] drm/amdgpu: Limit the max mc address to hole start
Good question, I asked the same one :)
One problem seems to be a firmware bug in the VCE firmware which seems
to write to the wrong location in this case.
Another one is probably a coding error in the SDMA handling.
Christian.
Am 10.10.2018 um 16:32 schrieb Liu, Shaoyun:
Just curious , why the gart range form 0x to 0x1FFF
will cause the engine hang ?
Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: Wednesday, October 10, 2018 3:31 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu: Limit the max mc address to hole start
Use "AMDGPU_GMC_HOLE_START - 1"
For the vram_start is 0 case, the gart range will be from 0x to
0x1FFF, which will cause the engine hang.
So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 9a5b252..84aae69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -146,6 +146,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc) {
const uint64_t four_gb = 0x1ULL;
u64 size_af, size_bf;
+ /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
+ u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START -
+1);
mc->gart_size += adev->pm.smu_prv_buffer_size;
@@ -153,7 +155,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
* the GART base on a 4GB boundary as well.
*/
size_bf = mc->fb_start;
- size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->fb_end + 1, four_gb);
+ size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
if (mc->gart_size > max(size_bf, size_af)) {
dev_warn(adev->dev, "limiting GART\n"); @@ -164,7 +166,7 @@
void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
(size_af < mc->gart_size))
mc->gart_start = 0;
else
- mc->gart_start = mc->mc_mask - mc->gart_size + 1;
+ mc->gart_start = max_mc_address - mc->gart_size + 1;
mc->gart_start &= ~(four_gb - 1);
mc->gart_end = mc->gart_start + mc->gart_size - 1;
--
2.7.4
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RE: [PATCH] drm/amdgpu: Limit the max mc address to hole start
Just curious , why the gart range form 0x to 0x1FFF
will cause the engine hang ?
Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: Wednesday, October 10, 2018 3:31 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu: Limit the max mc address to hole start
Use "AMDGPU_GMC_HOLE_START - 1"
For the vram_start is 0 case, the gart range will be from 0x to
0x1FFF, which will cause the engine hang.
So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 9a5b252..84aae69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -146,6 +146,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc) {
const uint64_t four_gb = 0x1ULL;
u64 size_af, size_bf;
+ /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
+ u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START -
+1);
mc->gart_size += adev->pm.smu_prv_buffer_size;
@@ -153,7 +155,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
* the GART base on a 4GB boundary as well.
*/
size_bf = mc->fb_start;
- size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->fb_end + 1, four_gb);
+ size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
if (mc->gart_size > max(size_bf, size_af)) {
dev_warn(adev->dev, "limiting GART\n"); @@ -164,7 +166,7 @@
void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
(size_af < mc->gart_size))
mc->gart_start = 0;
else
- mc->gart_start = mc->mc_mask - mc->gart_size + 1;
+ mc->gart_start = max_mc_address - mc->gart_size + 1;
mc->gart_start &= ~(four_gb - 1);
mc->gart_end = mc->gart_start + mc->gart_size - 1;
--
2.7.4
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Re: [PATCH libdrm v2 2/2] amdgpu/test: Fix deadlock tests for AI and RV v2
Sorry for late response, just back from vacation.
Indeed I do have commit rights, I am back now and will finalize
this work soon.
Thanks for the reviews.
Andrey
On 10/03/2018 02:22 PM, Marek Olšák wrote:
Yes, Andrey has commit rights.
Marek
On Wed, Oct 3, 2018 at 10:34 AM Christian König
wrote:
Thanks for keeping working on this.
Series is Reviewed-by: Christian König as well.
Do you now have commit rights?
Christian.
Am 02.10.2018 um 22:47 schrieb Marek Olšák:
For the series:
Reviewed-by: Marek Olšák
Marek
On Fri, Sep 28, 2018 at 10:46 AM Andrey Grodzovsky
wrote:
Seems like AI and RV requires uncashed memory mapping to be able
to pickup value written to memory by CPU after the WAIT_REG_MEM
command was already launched.
.
Enable the test for AI and RV.
v2:
Update commit description.
Signed-off-by: Andrey Grodzovsky
---
tests/amdgpu/deadlock_tests.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index 304482d..292ec4e 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -80,6 +80,8 @@ static uint32_t minor_version;
static pthread_t stress_thread;
static uint32_t *ptr;
+int use_uc_mtype = 0;
+
static void amdgpu_deadlock_helper(unsigned ip_type);
static void amdgpu_deadlock_gfx(void);
static void amdgpu_deadlock_compute(void);
@@ -92,13 +94,14 @@ CU_BOOL suite_deadlock_tests_enable(void)
_version, _handle))
return CU_FALSE;
- if (device_handle->info.family_id == AMDGPU_FAMILY_AI ||
- device_handle->info.family_id == AMDGPU_FAMILY_SI ||
- device_handle->info.family_id == AMDGPU_FAMILY_RV) {
+ if (device_handle->info.family_id == AMDGPU_FAMILY_SI) {
printf("\n\nCurrently hangs the CP on this ASIC, deadlock suite
disabled\n");
enable = CU_FALSE;
}
+ if (device_handle->info.family_id >= AMDGPU_FAMILY_AI)
+ use_uc_mtype = 1;
+
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
@@ -183,8 +186,8 @@ static void amdgpu_deadlock_helper(unsigned ip_type)
r = amdgpu_cs_ctx_create(device_handle, _handle);
CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0,
+ r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ?
AMDGPU_VM_MTYPE_UC : 0,
_result_handle,
_result_cpu,
_result_mc_address,
_handle);
CU_ASSERT_EQUAL(r, 0);
--
2.7.4
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Re: [PATCH v2 2/3] drm: Add variable refresh property to DRM CRTC
On 10/10/2018 03:14 AM, Pekka Paalanen wrote: On Fri, 5 Oct 2018 12:21:20 -0400 "Kazlauskas, Nicholas" wrote: On 10/05/2018 04:10 AM, Pekka Paalanen wrote: Hi, I have a somewhat of my own view on what would be involved with VRR, and I'd like to hear what you think of it. Comments inline. On Tue, 25 Sep 2018 09:51:37 -0400 "Kazlauskas, Nicholas" wrote: On 09/24/2018 04:26 PM, Ville Syrjälä wrote: On Mon, Sep 24, 2018 at 03:06:02PM -0400, Kazlauskas, Nicholas wrote: On 09/24/2018 02:38 PM, Ville Syrjälä wrote: On Mon, Sep 24, 2018 at 02:15:36PM -0400, Nicholas Kazlauskas wrote: Variable refresh rate algorithms have typically been enabled only when the display is covered by a single source of content. This patch introduces a new default CRTC property that helps hint to the driver when the CRTC composition is suitable for variable refresh rate algorithms. Userspace can set this property dynamically as the composition changes. Whether the variable refresh rate algorithms are active will still depend on the CRTC being suitable and the connector being capable and enabled by the user for variable refresh rate support. It is worth noting that while the property is atomic it isn't filtered from legacy userspace queries. This allows for Xorg userspace drivers to implement support in non-atomic setups. Signed-off-by: Nicholas Kazlauskas ... Whenever I mentioned variable refresh "features", what I really meant was operating in one of two modes: (1) Letting the driver and hardware adjust refresh automatically based on the flip rate on a CRTC from a single application (2) Setting a fixed frame duration based on the flip rate on a CRTC from a single application I wonder if that's too much magic in the kernel... what would be wrong with simply flipping ASAP when VRR is active? How will userspace be able to predict coming flip opportunities if the kernel does so much magic? The kernel driver doesn't need to do much more than let the hardware know the variable refresh range. The "magic" is performed by hardware. Most games would like to render as fast as possible to deliver a more responsive and smoother image to the user. Many of these are also resource intensive and won't always be able to render at the fixed refresh rate of the panel (especially for higher refresh rates like 144Hz). The user will experience stuttering if the game takes too long to render and misses the vblank window for the flip. Dynamic VRR adjustment can resolve this problem. The hardware can lower the refresh rate and increase the vblank window in response to this so the user doesn't experience stuttering (or latency). Userspace shouldn't predict anything. ... The reasoning for the split is because not all content is suitable for variable refresh. Desktop environments, web browsers, etc only typically flip when needed - which will result in display flickering. Flickering? What do you mean? This is a property of how panels work. The luminance for a panel will vary based on how long the vrefresh is. Since the vrefresh length is changing as part of VRR you're more likely to notice the difference in luminance the bigger the difference is. The difference will be largest when switching from the min vrefresh to the max vrefresh duration. Large differences can occur for applications that render on demand like a web browser (and why you wouldn't want VRR enabled for those). The hardware would continuously wait for a flip that isn't coming. Then if the user moves their cursor or the page updates it's going to happen "randomly" in that window and the hardware will adjust to that. Hi Nicholas, it seems I have very much mis-guessed what VRR aims to achieve, and the effect on luminance sounds horrible. It really depends on the panel characteristics - like the VRR range and panel brightness. Some panels can be particularly unpleasant but others are fine. People have worked for years to make display timings more explicit, giving better control and predictability over them. It sounds like VRR is not an improvement that allows new smarter software to take control of timings even better. Instead, VRR seems to be a step backwards, introducing more uncertainty into the timings. The expectation of a fixed unknown refresh rate must be built into software for the software to work reasonably while VRR is active. > From your comments I understood that the VRR hardware still very much depends on a consistent refresh rate, except the hardware (not the software!) can additionally slew the refresh rate over time. Abrupt changes in frame timings must still be prevented, but I wasn't quite sure if you meant the hardware will do that or if the software must do that, since you are worried about on-demand updating applications causing flickering. Hence, VRR looks like a band-aid for old and simple applications that use brute force (more fps, maximize the work load) in an attempt to make things smoother and to reduce latency.
[PATCH 2/3] drm/amdgpu: Load fw between hw_init/resume_phase1 and phase2
Extract the function of fw loading out of powerplay.
Do fw loading between hw_init/resuem_phase1 and phase2
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 61 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 ---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 20 ---
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 8 +--
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5 --
7 files changed, 62 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 372574a..1e4dd09 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1570,6 +1570,47 @@ static int amdgpu_device_ip_hw_init_phase2(struct
amdgpu_device *adev)
return 0;
}
+static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
+{
+ int r = 0;
+ int i;
+
+ if (adev->asic_type >= CHIP_VEGA10) {
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_PSP) {
+ if (adev->in_gpu_reset || adev->in_suspend) {
+ if (amdgpu_sriov_vf(adev) &&
adev->in_gpu_reset)
+ break; /* sriov gpu reset, psp
need to do hw_init before IH because of hw limit */
+ r =
adev->ip_blocks[i].version->funcs->resume(adev);
+ if (r) {
+ DRM_ERROR("resume of IP block
<%s> failed %d\n",
+
adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ } else {
+ r =
adev->ip_blocks[i].version->funcs->hw_init(adev);
+ if (r) {
+ DRM_ERROR("hw_init of IP block
<%s> failed %d\n",
+
adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ }
+ adev->ip_blocks[i].status.hw = true;
+ }
+ }
+ }
+
+ if (adev->powerplay.pp_funcs->load_firmware) {
+ r =
adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+ if (r) {
+ pr_err("firmware loading failed\n");
+ return r;
+ }
+ }
+
+ return 0;
+}
+
/**
* amdgpu_device_ip_init - run init for hardware IPs
*
@@ -1634,6 +1675,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
if (r)
return r;
+ r = amdgpu_device_fw_loading(adev);
+ if (r)
+ return r;
+
r = amdgpu_device_ip_hw_init_phase2(adev);
if (r)
return r;
@@ -2167,7 +2212,8 @@ static int amdgpu_device_ip_resume_phase2(struct
amdgpu_device *adev)
continue;
if (adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_COMMON ||
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
- adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
continue;
r = adev->ip_blocks[i].version->funcs->resume(adev);
if (r) {
@@ -2199,6 +2245,11 @@ static int amdgpu_device_ip_resume(struct amdgpu_device
*adev)
r = amdgpu_device_ip_resume_phase1(adev);
if (r)
return r;
+
+ r = amdgpu_device_fw_loading(adev);
+ if (r)
+ return r;
+
r = amdgpu_device_ip_resume_phase2(adev);
return r;
@@ -3149,6 +3200,10 @@ static int amdgpu_device_reset(struct amdgpu_device
*adev)
if (r)
goto out;
+ r = amdgpu_device_fw_loading(adev);
+ if (r)
+ return r;
+
r = amdgpu_device_ip_resume_phase2(adev);
if (r)
goto out;
@@ -3205,6 +3260,10 @@ static int amdgpu_device_reset_sriov(struct
amdgpu_device *adev,
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
[PATCH 3/3] drm/amdgpu: Remove wrong fw loading type warning
Remove the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 971549f..d91f378 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -297,8 +297,6 @@ enum amdgpu_firmware_load_type
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
- pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
case CHIP_RAVEN:
--
1.9.1
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[PATCH 1/3] drm/amdgpu: split ip hw_init into 2 phases
We need to do some IPs earlier to deal with ordering issues
similar to how resume is split into two phases.
Do fw loading via smu/psp between the two phases.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 66 --
1 file changed, 53 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 680df05..372574a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1525,6 +1525,51 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
return 0;
}
+static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
+{
+ int i, r;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (!adev->ip_blocks[i].status.sw)
+ continue;
+ if (adev->ip_blocks[i].status.hw)
+ continue;
+ if (adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_COMMON ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
+ r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+ if (r) {
+ DRM_ERROR("hw_init of IP block <%s> failed
%d\n",
+
adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ adev->ip_blocks[i].status.hw = true;
+ }
+ }
+
+ return 0;
+}
+
+static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
+{
+ int i, r;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (!adev->ip_blocks[i].status.sw)
+ continue;
+ if (adev->ip_blocks[i].status.hw)
+ continue;
+ r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+ if (r) {
+ DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ adev->ip_blocks[i].status.hw = true;
+ }
+
+ return 0;
+}
+
/**
* amdgpu_device_ip_init - run init for hardware IPs
*
@@ -1584,19 +1629,14 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init
complete*/
if (r)
return r;
- for (i = 0; i < adev->num_ip_blocks; i++) {
- if (!adev->ip_blocks[i].status.sw)
- continue;
- if (adev->ip_blocks[i].status.hw)
- continue;
- r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
- if (r) {
- DRM_ERROR("hw_init of IP block <%s> failed %d\n",
- adev->ip_blocks[i].version->funcs->name, r);
- return r;
- }
- adev->ip_blocks[i].status.hw = true;
- }
+
+ r = amdgpu_device_ip_hw_init_phase1(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_device_ip_hw_init_phase2(adev);
+ if (r)
+ return r;
amdgpu_xgmi_add_device(adev);
amdgpu_amdkfd_device_init(adev);
--
1.9.1
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Re: [PATCH 2/5] drm/amdgpu/rlc: gfx_v6 change the method to call rlc function
Am 10.10.2018 um 13:42 schrieb likun Gao:
From: Likun Gao
Use struct pointer to call rlc function.
When you do this please do the next step as well and separate our the
RLC functions into another file.
Otherwise I don't see the point in actually doing the change.
Christian.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index d76eb27..9b5523d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2403,7 +2403,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
if (r) {
dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
r);
- gfx_v6_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return r;
}
@@ -2428,7 +2428,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
(void **)>gfx.rlc.cs_ptr);
if (r) {
dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
- gfx_v6_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return r;
}
@@ -2549,8 +2549,8 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
if (!adev->gfx.rlc_fw)
return -EINVAL;
- gfx_v6_0_rlc_stop(adev);
- gfx_v6_0_rlc_reset(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_reset(adev);
gfx_v6_0_init_pg(adev);
gfx_v6_0_init_cg(adev);
@@ -2578,7 +2578,7 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
WREG32(mmRLC_UCODE_ADDR, 0);
gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
- gfx_v6_0_rlc_start(adev);
+ adev->gfx.rlc.funcs->rlc_start(adev);
return 0;
}
@@ -3075,6 +3075,15 @@ static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs
= {
.select_me_pipe_q = _v6_0_select_me_pipe_q
};
+static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {
+ .rlc_init = gfx_v6_0_rlc_init,
+ .rlc_fini = gfx_v6_0_rlc_fini,
+ .rlc_resume = gfx_v6_0_rlc_resume,
+ .rlc_stop = gfx_v6_0_rlc_stop,
+ .rlc_reset = gfx_v6_0_rlc_reset,
+ .rlc_start = gfx_v6_0_rlc_start
+};
+
static int gfx_v6_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -3082,6 +3091,7 @@ static int gfx_v6_0_early_init(void *handle)
adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
adev->gfx.funcs = _v6_0_gfx_funcs;
+ adev->gfx.rlc.funcs = _v6_0_rlc_funcs;
gfx_v6_0_set_ring_funcs(adev);
gfx_v6_0_set_irq_funcs(adev);
@@ -3114,7 +3124,7 @@ static int gfx_v6_0_sw_init(void *handle)
return r;
}
- r = gfx_v6_0_rlc_init(adev);
+ r = adev->gfx.rlc.funcs->rlc_init(adev);
if (r) {
DRM_ERROR("Failed to init rlc BOs!\n");
return r;
@@ -3165,7 +3175,7 @@ static int gfx_v6_0_sw_fini(void *handle)
for (i = 0; i < adev->gfx.num_compute_rings; i++)
amdgpu_ring_fini(>gfx.compute_ring[i]);
- gfx_v6_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return 0;
}
@@ -3177,7 +3187,7 @@ static int gfx_v6_0_hw_init(void *handle)
gfx_v6_0_constants_init(adev);
- r = gfx_v6_0_rlc_resume(adev);
+ r = adev->gfx.rlc.funcs->rlc_resume(adev);
if (r)
return r;
@@ -3195,7 +3205,7 @@ static int gfx_v6_0_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gfx_v6_0_cp_enable(adev, false);
- gfx_v6_0_rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
gfx_v6_0_fini_pg(adev);
return 0;
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Re: [PATCH 1/5] drm/amdgpu/rlc: unify rlc function into structure
Am 10.10.2018 um 13:42 schrieb likun Gao:
From: Likun Gao
Put function rlc_init,rlc_fini,rlc_resume,rlc_stop,rlc_start into structure
amdgpu_rlc_funcs.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index b61b5c1..bb7b1ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -41,6 +41,12 @@
struct amdgpu_rlc_funcs {
void (*enter_safe_mode)(struct amdgpu_device *adev);
void (*exit_safe_mode)(struct amdgpu_device *adev);
+ int (*rlc_init)(struct amdgpu_device *adev);
+ void (*rlc_fini)(struct amdgpu_device *adev);
+ int (*rlc_resume)(struct amdgpu_device *adev);
+ void (*rlc_stop)(struct amdgpu_device *adev);
+ void (*rlc_reset)(struct amdgpu_device *adev);
+ void (*rlc_start)(struct amdgpu_device *adev);
Please drop the rlc_ prefix to all those members. The structure name
already denotes it as rlc functions.
Christian.
};
struct amdgpu_rlc {
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[PATCH 3/5] drm/amdgpu/rlc: gfx_v7 change the method to call rlc function
From: Likun Gao
Use struct pointer to call rlc function.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 0e72bc0..8826f59 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3314,7 +3314,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
(void **)>gfx.rlc.sr_ptr);
if (r) {
dev_warn(adev->dev, "(%d) create, pin or map of RLC sr
bo failed\n", r);
- gfx_v7_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return r;
}
@@ -3337,7 +3337,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
(void **)>gfx.rlc.cs_ptr);
if (r) {
dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
- gfx_v7_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return r;
}
@@ -3357,7 +3357,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
(void
**)>gfx.rlc.cp_table_ptr);
if (r) {
dev_warn(adev->dev, "(%d) create RLC cp table bo
failed\n", r);
- gfx_v7_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return r;
}
@@ -3545,13 +3545,13 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device
*adev)
adev->gfx.rlc_feature_version = le32_to_cpu(
hdr->ucode_feature_version);
- gfx_v7_0_rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
/* disable CG */
tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffc;
WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
- gfx_v7_0_rlc_reset(adev);
+ adev->gfx.rlc.funcs->rlc_reset(adev);
gfx_v7_0_init_pg(adev);
@@ -3582,7 +3582,7 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
if (adev->asic_type == CHIP_BONAIRE)
WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
- gfx_v7_0_rlc_start(adev);
+ adev->gfx.rlc.funcs->rlc_start(adev);
return 0;
}
@@ -4289,7 +4289,13 @@ static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs
= {
static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
.enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
- .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
+ .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode,
+ .rlc_init = gfx_v7_0_rlc_init,
+ .rlc_fini = gfx_v7_0_rlc_fini,
+ .rlc_resume = gfx_v7_0_rlc_resume,
+ .rlc_stop = gfx_v7_0_rlc_stop,
+ .rlc_reset = gfx_v7_0_rlc_reset,
+ .rlc_start = gfx_v7_0_rlc_start
};
static int gfx_v7_0_early_init(void *handle)
@@ -4540,7 +4546,7 @@ static int gfx_v7_0_sw_init(void *handle)
return r;
}
- r = gfx_v7_0_rlc_init(adev);
+ r = adev->gfx.rlc.funcs->rlc_init(adev);
if (r) {
DRM_ERROR("Failed to init rlc BOs!\n");
return r;
@@ -4604,7 +4610,7 @@ static int gfx_v7_0_sw_fini(void *handle)
amdgpu_ring_fini(>gfx.compute_ring[i]);
gfx_v7_0_cp_compute_fini(adev);
- gfx_v7_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
gfx_v7_0_mec_fini(adev);
amdgpu_bo_free_kernel(>gfx.rlc.clear_state_obj,
>gfx.rlc.clear_state_gpu_addr,
@@ -4627,7 +4633,7 @@ static int gfx_v7_0_hw_init(void *handle)
gfx_v7_0_constants_init(adev);
/* init rlc */
- r = gfx_v7_0_rlc_resume(adev);
+ r = adev->gfx.rlc.funcs->rlc_resume(adev);
if (r)
return r;
@@ -4645,7 +4651,7 @@ static int gfx_v7_0_hw_fini(void *handle)
amdgpu_irq_put(adev, >gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, >gfx.priv_inst_irq, 0);
gfx_v7_0_cp_enable(adev, false);
- gfx_v7_0_rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
gfx_v7_0_fini_pg(adev);
return 0;
@@ -4730,7 +4736,7 @@ static int gfx_v7_0_soft_reset(void *handle)
gfx_v7_0_update_cg(adev, false);
/* stop the rlc */
- gfx_v7_0_rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
/* Disable GFX parsing/prefetching */
WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
--
2.7.4
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[PATCH 5/5] drm/amdgpu/rlc: gfx_v9 change the method to call rlc function
From: Likun Gao
Use struct pointer to call rlc function.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d6b5069..16798f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1152,7 +1152,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
if (r) {
dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
r);
- gfx_v9_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return r;
}
/* set up the cs buffer */
@@ -1174,7 +1174,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
if (r) {
dev_err(adev->dev,
"(%d) failed to create cp table bo\n", r);
- gfx_v9_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return r;
}
@@ -1738,7 +1738,7 @@ static int gfx_v9_0_sw_init(void *handle)
return r;
}
- r = gfx_v9_0_rlc_init(adev);
+ r = adev->gfx.rlc.funcs->rlc_init(adev);
if (r) {
DRM_ERROR("Failed to init rlc BOs!\n");
return r;
@@ -2488,12 +2488,12 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device
*adev)
return 0;
}
- gfx_v9_0_rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
/* disable CG */
WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
- gfx_v9_0_rlc_reset(adev);
+ adev->gfx.rlc.funcs->rlc_reset(adev);
gfx_v9_0_init_pg(adev);
@@ -2512,7 +2512,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
gfx_v9_0_enable_lbpw(adev, false);
}
- gfx_v9_0_rlc_start(adev);
+ adev->gfx.rlc.funcs->rlc_start(adev);
return 0;
}
@@ -3343,7 +3343,7 @@ static int gfx_v9_0_hw_init(void *handle)
if (r)
return r;
- r = gfx_v9_0_rlc_resume(adev);
+ r = adev->gfx.rlc.funcs->rlc_resume(adev);
if (r)
return r;
@@ -3423,7 +3423,7 @@ static int gfx_v9_0_hw_fini(void *handle)
}
gfx_v9_0_cp_enable(adev, false);
- gfx_v9_0_rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
gfx_v9_0_csb_vram_unpin(adev);
@@ -3498,7 +3498,7 @@ static int gfx_v9_0_soft_reset(void *handle)
if (grbm_soft_reset) {
/* stop the rlc */
- gfx_v9_0_rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
/* Disable GFX parsing/prefetching */
gfx_v9_0_cp_gfx_enable(adev, false);
@@ -3654,7 +3654,7 @@ static void gfx_v9_0_exit_rlc_safe_mode(struct
amdgpu_device *adev)
static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
bool enable)
{
- gfx_v9_0_enter_rlc_safe_mode(adev);
+ adev->gfx.rlc.funcs->enter_safe_mode(adev);
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
@@ -3665,7 +3665,7 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct
amdgpu_device *adev,
gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
}
- gfx_v9_0_exit_rlc_safe_mode(adev);
+ adev->gfx.rlc.funcs->exit_safe_mode(adev);
}
static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
@@ -3881,7 +3881,13 @@ static int gfx_v9_0_update_gfx_clock_gating(struct
amdgpu_device *adev,
static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
.enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
- .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
+ .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode,
+ .rlc_init = gfx_v9_0_rlc_init,
+ .rlc_fini = gfx_v9_0_rlc_fini,
+ .rlc_resume = gfx_v9_0_rlc_resume,
+ .rlc_stop = gfx_v9_0_rlc_stop,
+ .rlc_reset = gfx_v9_0_rlc_reset,
+ .rlc_start = gfx_v9_0_rlc_start
};
static int gfx_v9_0_set_powergating_state(void *handle,
--
2.7.4
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[PATCH 4/5] drm/amdgpu/rlc: gfx_v8 change the method to call rlc function
From: Likun Gao
Use struct pointer to call rlc function.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 8439f9a..7735545 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1391,7 +1391,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
(void **)>gfx.rlc.cs_ptr);
if (r) {
dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
- gfx_v8_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return r;
}
@@ -2088,7 +2088,7 @@ static int gfx_v8_0_sw_init(void *handle)
return r;
}
- r = gfx_v8_0_rlc_init(adev);
+ r = adev->gfx.rlc.funcs->rlc_init(adev);
if (r) {
DRM_ERROR("Failed to init rlc BOs!\n");
return r;
@@ -2181,7 +2181,7 @@ static int gfx_v8_0_sw_fini(void *handle)
amdgpu_gfx_kiq_fini(adev);
gfx_v8_0_mec_fini(adev);
- gfx_v8_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
amdgpu_bo_free_kernel(>gfx.rlc.clear_state_obj,
>gfx.rlc.clear_state_gpu_addr,
(void **)>gfx.rlc.cs_ptr);
@@ -4177,8 +4177,8 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
{
int r;
- gfx_v8_0_rlc_stop(adev);
- gfx_v8_0_rlc_reset(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_reset(adev);
gfx_v8_0_init_pg(adev);
if (adev->powerplay.pp_funcs->load_firmware) {
@@ -4189,7 +4189,7 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
}
}
- gfx_v8_0_rlc_start(adev);
+ adev->gfx.rlc.funcs->rlc_start(adev);
return 0;
}
@@ -4876,7 +4876,7 @@ static int gfx_v8_0_hw_init(void *handle)
gfx_v8_0_init_golden_registers(adev);
gfx_v8_0_constants_init(adev);
- r = gfx_v8_0_rlc_resume(adev);
+ r = adev->gfx.rlc.funcs->rlc_resume(adev);
if (r)
return r;
@@ -4988,7 +4988,7 @@ static int gfx_v8_0_hw_fini(void *handle)
else
pr_err("cp is busy, skip halt cp\n");
if (!gfx_v8_0_wait_for_rlc_idle(adev))
- gfx_v8_0_rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
else
pr_err("rlc is busy, skip halt rlc\n");
adev->gfx.rlc.funcs->exit_safe_mode(adev);
@@ -5080,7 +5080,7 @@ static int gfx_v8_0_pre_soft_reset(void *handle)
srbm_soft_reset = adev->gfx.srbm_soft_reset;
/* stop the rlc */
- gfx_v8_0_rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
@@ -5206,7 +5206,7 @@ static int gfx_v8_0_post_soft_reset(void *handle)
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
gfx_v8_0_cp_gfx_resume(adev);
- gfx_v8_0_rlc_start(adev);
+ adev->gfx.rlc.funcs->rlc_start(adev);
return 0;
}
@@ -5663,7 +5663,13 @@ static void iceland_exit_rlc_safe_mode(struct
amdgpu_device *adev)
static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
.enter_safe_mode = iceland_enter_rlc_safe_mode,
- .exit_safe_mode = iceland_exit_rlc_safe_mode
+ .exit_safe_mode = iceland_exit_rlc_safe_mode,
+ .rlc_init = gfx_v8_0_rlc_init,
+ .rlc_fini = gfx_v8_0_rlc_fini,
+ .rlc_resume = gfx_v8_0_rlc_resume,
+ .rlc_stop = gfx_v8_0_rlc_stop,
+ .rlc_reset = gfx_v8_0_rlc_reset,
+ .rlc_start = gfx_v8_0_rlc_start
};
static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device
*adev,
--
2.7.4
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[PATCH 2/5] drm/amdgpu/rlc: gfx_v6 change the method to call rlc function
From: Likun Gao
Use struct pointer to call rlc function.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index d76eb27..9b5523d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2403,7 +2403,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
if (r) {
dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
r);
- gfx_v6_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return r;
}
@@ -2428,7 +2428,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
(void **)>gfx.rlc.cs_ptr);
if (r) {
dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
- gfx_v6_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return r;
}
@@ -2549,8 +2549,8 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
if (!adev->gfx.rlc_fw)
return -EINVAL;
- gfx_v6_0_rlc_stop(adev);
- gfx_v6_0_rlc_reset(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_reset(adev);
gfx_v6_0_init_pg(adev);
gfx_v6_0_init_cg(adev);
@@ -2578,7 +2578,7 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
WREG32(mmRLC_UCODE_ADDR, 0);
gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
- gfx_v6_0_rlc_start(adev);
+ adev->gfx.rlc.funcs->rlc_start(adev);
return 0;
}
@@ -3075,6 +3075,15 @@ static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs
= {
.select_me_pipe_q = _v6_0_select_me_pipe_q
};
+static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {
+ .rlc_init = gfx_v6_0_rlc_init,
+ .rlc_fini = gfx_v6_0_rlc_fini,
+ .rlc_resume = gfx_v6_0_rlc_resume,
+ .rlc_stop = gfx_v6_0_rlc_stop,
+ .rlc_reset = gfx_v6_0_rlc_reset,
+ .rlc_start = gfx_v6_0_rlc_start
+};
+
static int gfx_v6_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -3082,6 +3091,7 @@ static int gfx_v6_0_early_init(void *handle)
adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
adev->gfx.funcs = _v6_0_gfx_funcs;
+ adev->gfx.rlc.funcs = _v6_0_rlc_funcs;
gfx_v6_0_set_ring_funcs(adev);
gfx_v6_0_set_irq_funcs(adev);
@@ -3114,7 +3124,7 @@ static int gfx_v6_0_sw_init(void *handle)
return r;
}
- r = gfx_v6_0_rlc_init(adev);
+ r = adev->gfx.rlc.funcs->rlc_init(adev);
if (r) {
DRM_ERROR("Failed to init rlc BOs!\n");
return r;
@@ -3165,7 +3175,7 @@ static int gfx_v6_0_sw_fini(void *handle)
for (i = 0; i < adev->gfx.num_compute_rings; i++)
amdgpu_ring_fini(>gfx.compute_ring[i]);
- gfx_v6_0_rlc_fini(adev);
+ adev->gfx.rlc.funcs->rlc_fini(adev);
return 0;
}
@@ -3177,7 +3187,7 @@ static int gfx_v6_0_hw_init(void *handle)
gfx_v6_0_constants_init(adev);
- r = gfx_v6_0_rlc_resume(adev);
+ r = adev->gfx.rlc.funcs->rlc_resume(adev);
if (r)
return r;
@@ -3195,7 +3205,7 @@ static int gfx_v6_0_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gfx_v6_0_cp_enable(adev, false);
- gfx_v6_0_rlc_stop(adev);
+ adev->gfx.rlc.funcs->rlc_stop(adev);
gfx_v6_0_fini_pg(adev);
return 0;
--
2.7.4
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[PATCH 1/5] drm/amdgpu/rlc: unify rlc function into structure
From: Likun Gao
Put function rlc_init,rlc_fini,rlc_resume,rlc_stop,rlc_start into structure
amdgpu_rlc_funcs.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index b61b5c1..bb7b1ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -41,6 +41,12 @@
struct amdgpu_rlc_funcs {
void (*enter_safe_mode)(struct amdgpu_device *adev);
void (*exit_safe_mode)(struct amdgpu_device *adev);
+ int (*rlc_init)(struct amdgpu_device *adev);
+ void (*rlc_fini)(struct amdgpu_device *adev);
+ int (*rlc_resume)(struct amdgpu_device *adev);
+ void (*rlc_stop)(struct amdgpu_device *adev);
+ void (*rlc_reset)(struct amdgpu_device *adev);
+ void (*rlc_start)(struct amdgpu_device *adev);
};
struct amdgpu_rlc {
--
2.7.4
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[PATCH 0/5] RLC kernel code update for unified RLC function
From: Likun Gao Hi all, Code modified about RLC will be operated to improve the resuability of RLC's code, and this process will operated with two steps: STEP1(completed): - Unify RLC's function into the structure amdgpu_rlc_funcs and use structure pointer to call RLC functions. - The modified of the step have completed, and the related code change have patched in the following patches. Please help to review. STEP2(underway): - Will modified the code to unify the RLC function for each version of GFX to improve the resuability of RLC's function code. Regards, Likun Likun Gao (5): drm/amdgpu/rlc: unify rlc function into structure drm/amdgpu/rlc: gfx_v6 change the method to call rlc function drm/amdgpu/rlc: gfx_v7 change the method to call rlc function drm/amdgpu/rlc: gfx_v8 change the method to call rlc function drm/amdgpu/rlc: gfx_v9 change the method to call rlc function drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 ++ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 28 +++- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 30 ++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 28 +--- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 ++ 5 files changed, 78 insertions(+), 44 deletions(-) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amd/powerplay: translate power_profile mode to pplib workload type
Correctly translate the power profile specified by user to workload
type accepted by SMU fw.
Change-Id: I4de525d6a84a80c2fcfc1a6de2a465a7a07868a4
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 42 +--
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 958af7b48827..b4dbbb7c334c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -3175,6 +3175,34 @@ static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
return result;
}
+static int conv_power_profile_to_pplib_workload(int power_profile)
+{
+ int pplib_workload = 0;
+
+ switch (power_profile) {
+ case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
+ pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_POWERSAVING:
+ pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_VIDEO:
+ pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_VR:
+ pplib_workload = WORKLOAD_PPLIB_VR_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_COMPUTE:
+ pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_CUSTOM:
+ pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
+ break;
+ }
+
+ return pplib_workload;
+}
+
static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
{
DpmActivityMonitorCoeffInt_t activity_monitor;
@@ -3210,7 +3238,7 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr
*hwmgr, char *buf)
for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
- workload_type = i + 1;
+ workload_type = conv_power_profile_to_pplib_workload(i);
result = vega20_get_activity_monitor_coeff(hwmgr,
(uint8_t *)(_monitor), workload_type);
PP_ASSERT_WITH_CODE(!result,
@@ -3283,10 +3311,15 @@ static int vega20_get_power_profile_mode(struct
pp_hwmgr *hwmgr, char *buf)
static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input,
uint32_t size)
{
DpmActivityMonitorCoeffInt_t activity_monitor;
- int result = 0;
+ int workload_type, result = 0;
hwmgr->power_profile_mode = input[size];
+ if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
+ pr_err("Invalid power profile mode %d\n",
hwmgr->power_profile_mode);
+ return -EINVAL;
+ }
+
if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
if (size < 10)
return -EINVAL;
@@ -3353,8 +3386,11 @@ static int vega20_set_power_profile_mode(struct pp_hwmgr
*hwmgr, long *input, ui
return result);
}
+ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ workload_type =
+ conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
- 1 << hwmgr->power_profile_mode);
+ 1 << workload_type);
return 0;
}
--
2.19.1
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[PATCH 2/2] drm/amd/powerplay: hint when power profile setting is not supported
Give user some hints when the power profile setting is not supported.
Change-Id: Iba2b938d02a039ccdee32f9aca185f79fd818796
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 6bc8e9c08b0c..343d7f506bb4 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -897,9 +897,14 @@ static int pp_set_power_profile_mode(void *handle, long
*input, uint32_t size)
pr_info("%s was not implemented.\n", __func__);
return ret;
}
+
+ if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+ pr_info("power profile setting is for manual dpm mode only.\n");
+ return ret;
+ }
+
mutex_lock(>smu_lock);
- if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
- ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input,
size);
+ ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
mutex_unlock(>smu_lock);
return ret;
}
--
2.19.1
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RE: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Thanks Sigil
Hi Christian
Looks we can enable/disable ctx-switch for SDMA at will, no dependency or
conflict on SRIOV
/Monk
-Original Message-
From: Ma, Sigil
Sent: Wednesday, October 10, 2018 3:25 PM
To: Liu, Monk ; Koenig, Christian ;
Huang, Ray ; Min, Frank
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Hi Monk,
AUTO_CTXSW_ENABLE is not relevant to worldswitch preemption. it only applies
for ring buffer preemption. SDMA will do worldswitch whatever AUTO_CTXSW_ENABLE
is 1 or 0.
-Original Message-
From: Liu, Monk
Sent: Wednesday, October 10, 2018 2:54 PM
To: Koenig, Christian ; Huang, Ray
; Min, Frank ; Ma, Sigil
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Oh, that mean I remember it reversed way, according to code looks we need to
enable ctx_switch to support WORLD SWITCH for SDMA engine
But better let Sigil confirm it ...
Hi @Ma, Sigil can you confirm it ? what's the relationship between ctx_swich
and world swich for SDMA engines ?
Ctx_switch_enable() will set "SDMA0/1_CNTL's field: AUTO_CTXSW_ENABLE" to 1,
can you tell us what's it for and how it go with SRIOV world switch ?
Thanks
/Monk
-Original Message-
From: Koenig, Christian
Sent: Tuesday, October 9, 2018 9:03 PM
To: Liu, Monk ; Huang, Ray ; Min, Frank
; Ma, Sigil
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Hi Monk,
well that doesn't make much sense to me what you say here cause context
switching certainly is already enabled under SRIOV:
> - if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence
> doesn't need below to lines */
> - sdma_v4_0_ctx_switch_enable(adev, true);
> - sdma_v4_0_enable(adev, true);
> - }
The problem is that context switching as well as the gfx ring is enabled for
both SDMA0 and SDMA1 without initializing SDMA1.
That's most likely causing some unwanted consequences.
Christian.
Am 09.10.2018 um 13:45 schrieb Liu, Monk:
> Context switch is for preemption across different queues (gfx, rlc0/1,
> page) under bare-metal environment, For SRIOV we didn't need it and we didn't
> test it yet, so we just disable it to make life easier, besides since each VF
> share only 6 MS slice there is in fact no benefit to enable it for SRIOV ...
>
> + @Ma, Sigil to confirm
>
> Hi Sigil
>
> Do you think context switch could be enabled for SRIOV VF ?? I worry that the
> context switch have internal crush with preemption for world switch , thanks !
>
> /Monk
>
> -Original Message-
> From: Christian König
> Sent: Tuesday, October 9, 2018 6:57 PM
> To: Huang, Ray ; Liu, Monk ; Min,
> Frank
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
>
> Am 09.10.2018 um 11:17 schrieb Huang Rui:
>> On Mon, Oct 08, 2018 at 03:35:15PM +0200, Christian König wrote:
>>> [SNIP]
>>> - if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>>> - r = sdma_v4_0_load_microcode(adev);
>>> + /* start the gfx rings and rlc compute queues */
>>> + for (i = 0; i < adev->sdma.num_instances; i++)
>>> + sdma_v4_0_gfx_resume(adev, i);
>>> +
>>> + if (amdgpu_sriov_vf(adev)) {
>>> + sdma_v4_0_ctx_switch_enable(adev, true);
>>> + sdma_v4_0_enable(adev, true);
>>> + } else {
>>> + r = sdma_v4_0_rlc_resume(adev);
>>> if (r)
>>> return r;
>>> }
>> + Monk, Frank,
>>
>> I probably cannot judge here, under SRIOV, I saw you disable ctx
>> switch before. Do you have any concern if we enabled it here.
> The problem was that those calls where mixed into sdma_v4_0_gfx_resume() for
> the first SDMA instance.
>
> What was happening is that SDMA0 was initialized and while doing so enabled
> both SDMA0 and SDMA1. So SDMA1 was starting up before the ring buffer was
> even set.
>
> That this doesn't crashed was pure coincident and is most likely also the
> reason why we ran into problems when ring buffers weren't initialized.
>
> Regards,
> Christian.
>
>> Others, looks good for me. Christian, may we know which kind of jobs
>> will use sdma page queue(ring), you know, we just sdma gfx queue(ring)
>> before?
>>
>> Thanks,
>> Ray
>>
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Re: [PATCH] drm/amdgpu: Limit the max mc address to hole start
Am 10.10.2018 um 09:31 schrieb Emily Deng:
Use "AMDGPU_GMC_HOLE_START - 1"
For the vram_start is 0 case, the gart range will be from 0x
to 0x1FFF, which will cause the engine hang.
So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq
Signed-off-by: Emily Deng
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 9a5b252..84aae69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -146,6 +146,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
{
const uint64_t four_gb = 0x1ULL;
u64 size_af, size_bf;
+ /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
+ u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
mc->gart_size += adev->pm.smu_prv_buffer_size;
@@ -153,7 +155,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
* the GART base on a 4GB boundary as well.
*/
size_bf = mc->fb_start;
- size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->fb_end + 1, four_gb);
+ size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
if (mc->gart_size > max(size_bf, size_af)) {
dev_warn(adev->dev, "limiting GART\n");
@@ -164,7 +166,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
(size_af < mc->gart_size))
mc->gart_start = 0;
else
- mc->gart_start = mc->mc_mask - mc->gart_size + 1;
+ mc->gart_start = max_mc_address - mc->gart_size + 1;
mc->gart_start &= ~(four_gb - 1);
mc->gart_end = mc->gart_start + mc->gart_size - 1;
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[PATCH] drm/amdgpu: Limit the max mc address to hole start
Use "AMDGPU_GMC_HOLE_START - 1"
For the vram_start is 0 case, the gart range will be from 0x
to 0x1FFF, which will cause the engine hang.
So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 9a5b252..84aae69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -146,6 +146,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
{
const uint64_t four_gb = 0x1ULL;
u64 size_af, size_bf;
+ /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
+ u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
mc->gart_size += adev->pm.smu_prv_buffer_size;
@@ -153,7 +155,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
* the GART base on a 4GB boundary as well.
*/
size_bf = mc->fb_start;
- size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->fb_end + 1, four_gb);
+ size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
if (mc->gart_size > max(size_bf, size_af)) {
dev_warn(adev->dev, "limiting GART\n");
@@ -164,7 +166,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
(size_af < mc->gart_size))
mc->gart_start = 0;
else
- mc->gart_start = mc->mc_mask - mc->gart_size + 1;
+ mc->gart_start = max_mc_address - mc->gart_size + 1;
mc->gart_start &= ~(four_gb - 1);
mc->gart_end = mc->gart_start + mc->gart_size - 1;
--
2.7.4
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RE: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Hi Monk,
AUTO_CTXSW_ENABLE is not relevant to worldswitch preemption. it only applies
for ring buffer preemption. SDMA will do worldswitch whatever AUTO_CTXSW_ENABLE
is 1 or 0.
-Original Message-
From: Liu, Monk
Sent: Wednesday, October 10, 2018 2:54 PM
To: Koenig, Christian ; Huang, Ray
; Min, Frank ; Ma, Sigil
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Oh, that mean I remember it reversed way, according to code looks we need to
enable ctx_switch to support WORLD SWITCH for SDMA engine
But better let Sigil confirm it ...
Hi @Ma, Sigil can you confirm it ? what's the relationship between ctx_swich
and world swich for SDMA engines ?
Ctx_switch_enable() will set "SDMA0/1_CNTL's field: AUTO_CTXSW_ENABLE" to 1,
can you tell us what's it for and how it go with SRIOV world switch ?
Thanks
/Monk
-Original Message-
From: Koenig, Christian
Sent: Tuesday, October 9, 2018 9:03 PM
To: Liu, Monk ; Huang, Ray ; Min, Frank
; Ma, Sigil
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Hi Monk,
well that doesn't make much sense to me what you say here cause context
switching certainly is already enabled under SRIOV:
> - if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence
> doesn't need below to lines */
> - sdma_v4_0_ctx_switch_enable(adev, true);
> - sdma_v4_0_enable(adev, true);
> - }
The problem is that context switching as well as the gfx ring is enabled for
both SDMA0 and SDMA1 without initializing SDMA1.
That's most likely causing some unwanted consequences.
Christian.
Am 09.10.2018 um 13:45 schrieb Liu, Monk:
> Context switch is for preemption across different queues (gfx, rlc0/1,
> page) under bare-metal environment, For SRIOV we didn't need it and we didn't
> test it yet, so we just disable it to make life easier, besides since each VF
> share only 6 MS slice there is in fact no benefit to enable it for SRIOV ...
>
> + @Ma, Sigil to confirm
>
> Hi Sigil
>
> Do you think context switch could be enabled for SRIOV VF ?? I worry that the
> context switch have internal crush with preemption for world switch , thanks !
>
> /Monk
>
> -Original Message-
> From: Christian König
> Sent: Tuesday, October 9, 2018 6:57 PM
> To: Huang, Ray ; Liu, Monk ; Min,
> Frank
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
>
> Am 09.10.2018 um 11:17 schrieb Huang Rui:
>> On Mon, Oct 08, 2018 at 03:35:15PM +0200, Christian König wrote:
>>> [SNIP]
>>> - if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>>> - r = sdma_v4_0_load_microcode(adev);
>>> + /* start the gfx rings and rlc compute queues */
>>> + for (i = 0; i < adev->sdma.num_instances; i++)
>>> + sdma_v4_0_gfx_resume(adev, i);
>>> +
>>> + if (amdgpu_sriov_vf(adev)) {
>>> + sdma_v4_0_ctx_switch_enable(adev, true);
>>> + sdma_v4_0_enable(adev, true);
>>> + } else {
>>> + r = sdma_v4_0_rlc_resume(adev);
>>> if (r)
>>> return r;
>>> }
>> + Monk, Frank,
>>
>> I probably cannot judge here, under SRIOV, I saw you disable ctx
>> switch before. Do you have any concern if we enabled it here.
> The problem was that those calls where mixed into sdma_v4_0_gfx_resume() for
> the first SDMA instance.
>
> What was happening is that SDMA0 was initialized and while doing so enabled
> both SDMA0 and SDMA1. So SDMA1 was starting up before the ring buffer was
> even set.
>
> That this doesn't crashed was pure coincident and is most likely also the
> reason why we ran into problems when ring buffers weren't initialized.
>
> Regards,
> Christian.
>
>> Others, looks good for me. Christian, may we know which kind of jobs
>> will use sdma page queue(ring), you know, we just sdma gfx queue(ring)
>> before?
>>
>> Thanks,
>> Ray
>>
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Re: [PATCH v2 2/3] drm: Add variable refresh property to DRM CRTC
On Fri, 5 Oct 2018 12:21:20 -0400 "Kazlauskas, Nicholas" wrote: > On 10/05/2018 04:10 AM, Pekka Paalanen wrote: > > Hi, > > > > I have a somewhat of my own view on what would be involved with VRR, > > and I'd like to hear what you think of it. Comments inline. > > > > > > On Tue, 25 Sep 2018 09:51:37 -0400 > > "Kazlauskas, Nicholas" wrote: > > > >> On 09/24/2018 04:26 PM, Ville Syrjälä wrote: > >>> On Mon, Sep 24, 2018 at 03:06:02PM -0400, Kazlauskas, Nicholas wrote: > On 09/24/2018 02:38 PM, Ville Syrjälä wrote: > > On Mon, Sep 24, 2018 at 02:15:36PM -0400, Nicholas Kazlauskas wrote: > >> Variable refresh rate algorithms have typically been enabled only > >> when the display is covered by a single source of content. > >> > >> This patch introduces a new default CRTC property that helps > >> hint to the driver when the CRTC composition is suitable for variable > >> refresh rate algorithms. Userspace can set this property dynamically > >> as the composition changes. > >> > >> Whether the variable refresh rate algorithms are active will still > >> depend on the CRTC being suitable and the connector being capable > >> and enabled by the user for variable refresh rate support. > >> > >> It is worth noting that while the property is atomic it isn't filtered > >> from legacy userspace queries. This allows for Xorg userspace drivers > >> to implement support in non-atomic setups. > >> > >> Signed-off-by: Nicholas Kazlauskas ... > >> Whenever I mentioned variable refresh "features", what I really meant > >> was operating in one of two modes: > >> > >> (1) Letting the driver and hardware adjust refresh automatically based > >> on the flip rate on a CRTC from a single application > >> > >> (2) Setting a fixed frame duration based on the flip rate on a CRTC from > >> a single application > > > > I wonder if that's too much magic in the kernel... what would be wrong > > with simply flipping ASAP when VRR is active? > > > > How will userspace be able to predict coming flip opportunities if the > > kernel does so much magic? > > The kernel driver doesn't need to do much more than let the hardware > know the variable refresh range. The "magic" is performed by hardware. > > Most games would like to render as fast as possible to deliver a more > responsive and smoother image to the user. Many of these are also > resource intensive and won't always be able to render at the fixed > refresh rate of the panel (especially for higher refresh rates like > 144Hz). The user will experience stuttering if the game takes too long > to render and misses the vblank window for the flip. > > Dynamic VRR adjustment can resolve this problem. The hardware can lower > the refresh rate and increase the vblank window in response to this so > the user doesn't experience stuttering (or latency). > > Userspace shouldn't predict anything. ... > The reasoning for the split is because not all content is suitable for > variable refresh. Desktop environments, web browsers, etc only typically > flip when needed - which will result in display flickering. > > > > Flickering? What do you mean? > > This is a property of how panels work. > > The luminance for a panel will vary based on how long the vrefresh is. > Since the vrefresh length is changing as part of VRR you're more likely > to notice the difference in luminance the bigger the difference is. > > The difference will be largest when switching from the min vrefresh to > the max vrefresh duration. > > Large differences can occur for applications that render on demand like > a web browser (and why you wouldn't want VRR enabled for those). The > hardware would continuously wait for a flip that isn't coming. Then if > the user moves their cursor or the page updates it's going to happen > "randomly" in that window and the hardware will adjust to that. Hi Nicholas, it seems I have very much mis-guessed what VRR aims to achieve, and the effect on luminance sounds horrible. People have worked for years to make display timings more explicit, giving better control and predictability over them. It sounds like VRR is not an improvement that allows new smarter software to take control of timings even better. Instead, VRR seems to be a step backwards, introducing more uncertainty into the timings. The expectation of a fixed unknown refresh rate must be built into software for the software to work reasonably while VRR is active. From your comments I understood that the VRR hardware still very much depends on a consistent refresh rate, except the hardware (not the software!) can additionally slew the refresh rate over time. Abrupt changes in frame timings must still be prevented, but I wasn't quite sure if you meant the hardware will do that or if the software must do that, since you are worried about on-demand updating applications causing flickering. Hence, VRR
Re: [PATCH] drm/amdgpu: Limit the max mc address to hole start
Am 10.10.2018 um 08:45 schrieb Emily Deng:
Replace AMDGPU_VA_HOLE_START with AMDGPU_GMC_HOLE_START and add the comment.
For the vram_start is 0 case, the gart range will be from 0x
to 0x1FFF, which will cause the engine hang.
So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 9a5b252..bb05d9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -146,6 +146,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
{
const uint64_t four_gb = 0x1ULL;
u64 size_af, size_bf;
+ /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
+ u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START);
This needs to use "AMDGPU_GMC_HOLE_START - 1" because the mc_mask is the
inclusive address space end.
Alternative you could do min(adev->gmc.mc_mask + 1, ) and also
remove the "+ 1" in the calculations below. That would probably be even
cleaner.
With that fixed the patch is Reviewed-by: Christian König
.
Regards,
Christian.
mc->gart_size += adev->pm.smu_prv_buffer_size;
@@ -153,7 +155,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
* the GART base on a 4GB boundary as well.
*/
size_bf = mc->fb_start;
- size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->fb_end + 1, four_gb);
+ size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
if (mc->gart_size > max(size_bf, size_af)) {
dev_warn(adev->dev, "limiting GART\n");
@@ -164,7 +166,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
(size_af < mc->gart_size))
mc->gart_start = 0;
else
- mc->gart_start = mc->mc_mask - mc->gart_size + 1;
+ mc->gart_start = max_mc_address - mc->gart_size + 1;
mc->gart_start &= ~(four_gb - 1);
mc->gart_end = mc->gart_start + mc->gart_size - 1;
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Re: [PATCH 04/12] drm/amdgpu: move IV prescreening into the GMC code
Yeah, exactly my thinking.
Basically the long term goal is to move most of the reporting and
handling of faults into amdgpu_gmc.c. Otherwise we would duplicate a lot
of handling for future hw generations.
On the other hand if the approach with the second IH ring buffer works
as expected we most likely won't need the pre-screening anymore at all.
But that needs more work to be 100% sure.
Christian.
Am 10.10.2018 um 01:46 schrieb Felix Kuehling:
I realized that most of the code in gmc_v9_0_psescreen_iv is not
actually hardware-specific. If it was not prescreening, but using an
amdgpu_iv_entry that was already parsed, I think it could just be a
generic function for processing retry faults:
* looking up the VM of a fault
* storing retry faults in a per-VM fifo
* dropping faults that have already been seen
In other words, it's just a generic top half interrupt handler for retry
faults while the bottom half (worker thread) would use the per-VM FIFOs
to handle those pending retry faults.
Regards,
Felix
On 2018-09-26 09:53 AM, Christian König wrote:
The GMC/VM subsystem is causing the faults, so move the handling here as
well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 59 +
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 69 --
2 files changed, 59 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 729a2c230f91..f8d69ab85fc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -244,6 +244,62 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct
amdgpu_device *adev,
return 0;
}
+/**
+ * vega10_ih_prescreen_iv - prescreen an interrupt vector
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns true if the interrupt vector should be further processed.
+ */
+static bool gmc_v9_0_prescreen_iv(struct amdgpu_device *adev,
+ struct amdgpu_iv_entry *entry,
+ uint64_t addr)
+{
+ struct amdgpu_vm *vm;
+ u64 key;
+ int r;
+
+ /* No PASID, can't identify faulting process */
+ if (!entry->pasid)
+ return true;
+
+ /* Not a retry fault */
+ if (!(entry->src_data[1] & 0x80))
+ return true;
+
+ /* Track retry faults in per-VM fault FIFO. */
+ spin_lock(>vm_manager.pasid_lock);
+ vm = idr_find(>vm_manager.pasid_idr, entry->pasid);
+ if (!vm) {
+ /* VM not found, process it normally */
+ spin_unlock(>vm_manager.pasid_lock);
+ return true;
+ }
+
+ key = AMDGPU_VM_FAULT(entry->pasid, addr);
+ r = amdgpu_vm_add_fault(vm->fault_hash, key);
+
+ /* Hash table is full or the fault is already being processed,
+* ignore further page faults
+*/
+ if (r != 0) {
+ spin_unlock(>vm_manager.pasid_lock);
+ return false;
+ }
+ /* No locking required with single writer and single reader */
+ r = kfifo_put(>faults, key);
+ if (!r) {
+ /* FIFO is full. Ignore it until there is space */
+ amdgpu_vm_clear_fault(vm->fault_hash, key);
+ spin_unlock(>vm_manager.pasid_lock);
+ return false;
+ }
+
+ spin_unlock(>vm_manager.pasid_lock);
+ /* It's the first fault for this address, process it normally */
+ return true;
+}
+
static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
@@ -255,6 +311,9 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device
*adev,
addr = (u64)entry->src_data[0] << 12;
addr |= ((u64)entry->src_data[1] & 0xf) << 44;
+ if (!gmc_v9_0_prescreen_iv(adev, entry, addr))
+ return 1;
+
if (!amdgpu_sriov_vf(adev)) {
status = RREG32(hub->vm_l2_pro_fault_status);
WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 0f50bef87163..0f68a0cd1fbf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -228,76 +228,7 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
*/
static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev)
{
- u32 ring_index = adev->irq.ih.rptr >> 2;
- u32 dw0, dw3, dw4, dw5;
- u16 pasid;
- u64 addr, key;
- struct amdgpu_vm *vm;
- int r;
-
- dw0 = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
- dw3 = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
- dw4 = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]);
- dw5 = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]);
-
- /*
RE: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Oh, that mean I remember it reversed way, according to code looks we need to
enable ctx_switch to support WORLD SWITCH for SDMA engine
But better let Sigil confirm it ...
Hi @Ma, Sigil can you confirm it ? what's the relationship between ctx_swich
and world swich for SDMA engines ?
Ctx_switch_enable() will set "SDMA0/1_CNTL's field: AUTO_CTXSW_ENABLE" to 1,
can you tell us what's it for and how it go with SRIOV world switch ?
Thanks
/Monk
-Original Message-
From: Koenig, Christian
Sent: Tuesday, October 9, 2018 9:03 PM
To: Liu, Monk ; Huang, Ray ; Min, Frank
; Ma, Sigil
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
Hi Monk,
well that doesn't make much sense to me what you say here cause context
switching certainly is already enabled under SRIOV:
> - if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence
> doesn't need below to lines */
> - sdma_v4_0_ctx_switch_enable(adev, true);
> - sdma_v4_0_enable(adev, true);
> - }
The problem is that context switching as well as the gfx ring is enabled for
both SDMA0 and SDMA1 without initializing SDMA1.
That's most likely causing some unwanted consequences.
Christian.
Am 09.10.2018 um 13:45 schrieb Liu, Monk:
> Context switch is for preemption across different queues (gfx, rlc0/1,
> page) under bare-metal environment, For SRIOV we didn't need it and we didn't
> test it yet, so we just disable it to make life easier, besides since each VF
> share only 6 MS slice there is in fact no benefit to enable it for SRIOV ...
>
> + @Ma, Sigil to confirm
>
> Hi Sigil
>
> Do you think context switch could be enabled for SRIOV VF ?? I worry that the
> context switch have internal crush with preemption for world switch , thanks !
>
> /Monk
>
> -Original Message-
> From: Christian König
> Sent: Tuesday, October 9, 2018 6:57 PM
> To: Huang, Ray ; Liu, Monk ; Min,
> Frank
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/8] drm/amdgpu: fix sdma v4 startup under SRIOV
>
> Am 09.10.2018 um 11:17 schrieb Huang Rui:
>> On Mon, Oct 08, 2018 at 03:35:15PM +0200, Christian König wrote:
>>> [SNIP]
>>> - if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>>> - r = sdma_v4_0_load_microcode(adev);
>>> + /* start the gfx rings and rlc compute queues */
>>> + for (i = 0; i < adev->sdma.num_instances; i++)
>>> + sdma_v4_0_gfx_resume(adev, i);
>>> +
>>> + if (amdgpu_sriov_vf(adev)) {
>>> + sdma_v4_0_ctx_switch_enable(adev, true);
>>> + sdma_v4_0_enable(adev, true);
>>> + } else {
>>> + r = sdma_v4_0_rlc_resume(adev);
>>> if (r)
>>> return r;
>>> }
>> + Monk, Frank,
>>
>> I probably cannot judge here, under SRIOV, I saw you disable ctx
>> switch before. Do you have any concern if we enabled it here.
> The problem was that those calls where mixed into sdma_v4_0_gfx_resume() for
> the first SDMA instance.
>
> What was happening is that SDMA0 was initialized and while doing so enabled
> both SDMA0 and SDMA1. So SDMA1 was starting up before the ring buffer was
> even set.
>
> That this doesn't crashed was pure coincident and is most likely also the
> reason why we ran into problems when ring buffers weren't initialized.
>
> Regards,
> Christian.
>
>> Others, looks good for me. Christian, may we know which kind of jobs
>> will use sdma page queue(ring), you know, we just sdma gfx queue(ring)
>> before?
>>
>> Thanks,
>> Ray
>>
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[PATCH v2] drm/amdgpu: Limit the max mc address to hole start
Replace AMDGPU_VA_HOLE_START with AMDGPU_GMC_HOLE_START, and add the comment in
code.
For the vram_start is 0 case, the gart range will be from 0x
to 0x1FFF, which will cause the engine hang.
So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 9a5b252..bb05d9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -146,6 +146,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
{
const uint64_t four_gb = 0x1ULL;
u64 size_af, size_bf;
+ /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
+ u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START);
mc->gart_size += adev->pm.smu_prv_buffer_size;
@@ -153,7 +155,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
* the GART base on a 4GB boundary as well.
*/
size_bf = mc->fb_start;
- size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->fb_end + 1, four_gb);
+ size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
if (mc->gart_size > max(size_bf, size_af)) {
dev_warn(adev->dev, "limiting GART\n");
@@ -164,7 +166,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
(size_af < mc->gart_size))
mc->gart_start = 0;
else
- mc->gart_start = mc->mc_mask - mc->gart_size + 1;
+ mc->gart_start = max_mc_address - mc->gart_size + 1;
mc->gart_start &= ~(four_gb - 1);
mc->gart_end = mc->gart_start + mc->gart_size - 1;
--
2.7.4
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[PATCH] drm/amdgpu: Limit the max mc address to hole start
Replace AMDGPU_VA_HOLE_START with AMDGPU_GMC_HOLE_START and add the comment.
For the vram_start is 0 case, the gart range will be from 0x
to 0x1FFF, which will cause the engine hang.
So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 9a5b252..bb05d9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -146,6 +146,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
{
const uint64_t four_gb = 0x1ULL;
u64 size_af, size_bf;
+ /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
+ u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START);
mc->gart_size += adev->pm.smu_prv_buffer_size;
@@ -153,7 +155,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
* the GART base on a 4GB boundary as well.
*/
size_bf = mc->fb_start;
- size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->fb_end + 1, four_gb);
+ size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
if (mc->gart_size > max(size_bf, size_af)) {
dev_warn(adev->dev, "limiting GART\n");
@@ -164,7 +166,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
(size_af < mc->gart_size))
mc->gart_start = 0;
else
- mc->gart_start = mc->mc_mask - mc->gart_size + 1;
+ mc->gart_start = max_mc_address - mc->gart_size + 1;
mc->gart_start &= ~(four_gb - 1);
mc->gart_end = mc->gart_start + mc->gart_size - 1;
--
2.7.4
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