[PATCH v2 2/3] drm/amd/powerplay:add hwmgr callback to update nbpstate on Carrizo

[Guttula, Suresh]

Add hwmgr callback "update_nbdpm_pstate".This will use to access
"cz_nbdpm_pstate_enable_disable" function to enable/disable low
memory pstate.

Signed-off-by: suresh guttula 
---

v2: commit message edited to explain more details
 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 1 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h| 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index 53cf787..553a203 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1992,6 +1992,7 @@ static const struct pp_hwmgr_func smu8_hwmgr_funcs = {
.power_state_set = smu8_set_power_state_tasks,
.dynamic_state_management_disable = smu8_disable_dpm_tasks,
.notify_cac_buffer_info = smu8_notify_cac_buffer_info,
+   .update_nbdpm_pstate = smu8_nbdpm_pstate_enable_disable,
.get_thermal_temperature_range = smu8_get_thermal_temperature_range,
 };
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 07d180ce..fb0f96f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -317,6 +317,9 @@ struct pp_hwmgr_func {
uint32_t mc_addr_low,
uint32_t mc_addr_hi,
uint32_t size);
+   int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
+   bool enable,
+   bool lock);
int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
struct PP_TemperatureRange *range);
int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
-- 
2.7.4

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[PATCH v2 3/3] drm/amd:Enable/Disable NBPSTATE on On/OFF of UVD

[Guttula, Suresh]

We observe black lines (underflow) on display when playing a
4K video with UVD. On Disabling Low memory P state this issue is
not seen.
In this patch ,disabling low memory P state only when video
size >= 4k.
Multiple runs of power measurement shows no imapct

Signed-off-by: suresh guttula 
---
v2: Enable/disable low memory pstate logic added to
amdgpu_dpm_enable_uvd() instead of parser function
 
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c  | 17 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h |  2 ++
 3 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 7235cd0..66c0dbd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -33,6 +33,8 @@
 #include 
 #include 
 #include 
+#include "hwmgr.h"
+#define WIDTH_4K 3840
 
 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
 
@@ -1956,6 +1958,21 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, 
bool enable)
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, 
!enable);
mutex_unlock(&adev->pm.mutex);
}
+   /* enable/disable Low Memory PState for UVD (4k videos) */
+   if (adev->asic_type == CHIP_STONEY &&
+   adev->uvd.decode_image_width >= WIDTH_4K) {
+   struct pp_hwmgr *hwmgr;
+   struct pp_instance *pp_handle =
+   (struct pp_instance *)adev->powerplay.pp_handle;
+   if (pp_handle) {
+   hwmgr = pp_handle->hwmgr;
+   if (hwmgr && hwmgr->hwmgr_func &&
+   hwmgr->hwmgr_func->update_nbdpm_pstate)
+   hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
+   !enable,
+   true);
+   }
+   }
 }
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 69896f4..4e5d13e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -692,6 +692,8 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device 
*adev, uint32_t *msg,
buf_sizes[0x1] = dpb_size;
buf_sizes[0x2] = image_size;
buf_sizes[0x4] = min_ctx_size;
+   /* store image width to adjust nb memory pstate */
+   adev->uvd.decode_image_width = width;
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index a3ab1a4..5eb6328 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -65,6 +65,8 @@ struct amdgpu_uvd {
struct drm_sched_entity entity;
struct delayed_work idle_work;
unsignedharvest_config;
+   /* store image width to adjust nb memory state */
+   unsigneddecode_image_width;
 };
 
 int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
-- 
2.7.4

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[PATCH 1/3] Revert "drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVD"

[Guttula, Suresh]

From: "S, Shirish" 

This reverts commit dbd8299c32f6f413f6cfe322fe0308f3cfc577e8.

Reason for revert:
This patch sends  msg PPSMC_MSG_DisableLowMemoryPstate(0x002e)
in wrong of sequence to SMU which is before PPSMC_MSG_UVDPowerON (0x0008).
This leads to SMU failing to service the request as it is
dependent on UVD to be powered ON, since it accesses UVD
registers.

This msg should ideally be sent only when the UVD is about to decode
a 4k video.

Signed-off-by: Shirish S 
Signed-off-by: suresh guttula 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index fef111d..53cf787 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1228,17 +1228,14 @@ static int smu8_dpm_force_dpm_level(struct pp_hwmgr 
*hwmgr,
 
 static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
 {
-   if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
-   smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);
+   if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
-   }
return 0;
 }
 
 static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
 {
if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
-   smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);
return smum_send_msg_to_smc_with_parameter(
hwmgr,
PPSMC_MSG_UVDPowerON,
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: Fix oops when pp_funcs->switch_power_profile is unset

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Kuehling, 
Felix 
Sent: Thursday, November 15, 2018 4:56:51 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix; Joerg Roedel
Subject: [PATCH] drm/amdgpu: Fix oops when pp_funcs->switch_power_profile is 
unset

On Vega20 and other pre-production GPUs, powerplay is not enabled yet.
Check for NULL pointers before calling pp_funcs function pointers.

Also affects Kaveri.

CC: Joerg Roedel 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index a9c7597..1c1fed6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -503,8 +503,11 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, 
bool idle)
 {
 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

-   amdgpu_dpm_switch_power_profile(adev,
-   PP_SMC_POWER_PROFILE_COMPUTE, !idle);
+   if (adev->powerplay.pp_funcs &&
+   adev->powerplay.pp_funcs->switch_power_profile)
+   amdgpu_dpm_switch_power_profile(adev,
+   PP_SMC_POWER_PROFILE_COMPUTE,
+   !idle);
 }

 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
--
2.7.4

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[PATCH] drm/amdgpu: Fix oops when pp_funcs->switch_power_profile is unset

[Kuehling, Felix]

On Vega20 and other pre-production GPUs, powerplay is not enabled yet.
Check for NULL pointers before calling pp_funcs function pointers.

Also affects Kaveri.

CC: Joerg Roedel 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index a9c7597..1c1fed6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -503,8 +503,11 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, 
bool idle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 
-   amdgpu_dpm_switch_power_profile(adev,
-   PP_SMC_POWER_PROFILE_COMPUTE, !idle);
+   if (adev->powerplay.pp_funcs &&
+   adev->powerplay.pp_funcs->switch_power_profile)
+   amdgpu_dpm_switch_power_profile(adev,
+   PP_SMC_POWER_PROFILE_COMPUTE,
+   !idle);
 }
 
 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
-- 
2.7.4

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Re: [PATCH] drm/amd/powerplay: Ratelimit all "was not implemented" messages

[Alex Deucher]

On Thu, Nov 15, 2018 at 8:47 AM Joerg Roedel  wrote:
>
> From: Joerg Roedel 
>
> Running kfdtest on an AMD Carizzo flooded the kernel log
> with thousands of these "was not implemented" messages,
> making it impossible to see other messages there.
>
> Ratelimit the messages to prevent user-space from flooding
> the kernel log.
>
> Signed-off-by: Joerg Roedel 

Should we just make these debug only?  Applied.

Thanks,

Alex

> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 52 
> +--
>  1 file changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index d6aa1d414320..b68c2e0fef01 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -300,7 +300,7 @@ static int pp_set_clockgating_by_smu(void *handle, 
> uint32_t msg_id)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   pr_info_ratelimited("%s was not implemented.\n", __func__);
> return 0;
> }
>
> @@ -387,7 +387,7 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
> return 0;
>
> if (hwmgr->hwmgr_func->get_sclk == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   pr_info_ratelimited("%s was not implemented.\n", __func__);
> return 0;
> }
> mutex_lock(&hwmgr->smu_lock);
> @@ -405,7 +405,7 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
> return 0;
>
> if (hwmgr->hwmgr_func->get_mclk == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   pr_info_ratelimited("%s was not implemented.\n", __func__);
> return 0;
> }
> mutex_lock(&hwmgr->smu_lock);
> @@ -422,7 +422,7 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
> return;
>
> if (hwmgr->hwmgr_func->powergate_vce == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   pr_info_ratelimited("%s was not implemented.\n", __func__);
> return;
> }
> mutex_lock(&hwmgr->smu_lock);
> @@ -438,7 +438,7 @@ static void pp_dpm_powergate_uvd(void *handle, bool gate)
> return;
>
> if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   pr_info_ratelimited("%s was not implemented.\n", __func__);
> return;
> }
> mutex_lock(&hwmgr->smu_lock);
> @@ -505,7 +505,7 @@ static void pp_dpm_set_fan_control_mode(void *handle, 
> uint32_t mode)
> return;
>
> if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   pr_info_ratelimited("%s was not implemented.\n", __func__);
> return;
> }
> mutex_lock(&hwmgr->smu_lock);
> @@ -522,7 +522,7 @@ static uint32_t pp_dpm_get_fan_control_mode(void *handle)
> return 0;
>
> if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   pr_info_ratelimited("%s was not implemented.\n", __func__);
> return 0;
> }
> mutex_lock(&hwmgr->smu_lock);
> @@ -540,7 +540,7 @@ static int pp_dpm_set_fan_speed_percent(void *handle, 
> uint32_t percent)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   pr_info_ratelimited("%s was not implemented.\n", __func__);
> return 0;
> }
> mutex_lock(&hwmgr->smu_lock);
> @@ -558,7 +558,7 @@ static int pp_dpm_get_fan_speed_percent(void *handle, 
> uint32_t *speed)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   pr_info_ratelimited("%s was not implemented.\n", __func__);
> return 0;
> }
>
> @@ -594,7 +594,7 @@ static int pp_dpm_set_fan_speed_rpm(void *handle, 
> uint32_t rpm)
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) {
> -   pr_info("%s was not implemented.\n", __func__);
> +   pr_info_ratelimited("%s was not implemented.\n", __func__);
> return 0;
> }
> mutex_lock(&hwmgr->smu_lock);
> @@ -720,7 +720,7 @@ static int pp_dpm_force_clock_level(void *handle,
> return -EINVAL;
>
> if (hwmgr->hwmgr_func->force_clock_level == NULL) {
> -   pr_info("%s was not impl

RE: [PATCH] drm/amdgpu: Fix Kernel Oops triggered by kfdtest

[Kuehling, Felix]

Apologies. We already have a fix for this on our internal amd-kfd-staging 
branch, but it's missing from amd-staging-drm-next. I'll cherry-pick our fix to 
amd-staging-drm-next and nominate it for drm-fixes.

Regards,
  Felix

-Original Message-
From: amd-gfx  On Behalf Of Joerg Roedel
Sent: Thursday, November 15, 2018 9:46 AM
To: Zhu, Rex ; Quan, Evan ; Deucher, 
Alexander ; Koenig, Christian 
; Zhou, David(ChunMing) 
Cc: Joerg Roedel ; dri-de...@lists.freedesktop.org; 
amd-gfx@lists.freedesktop.org; linux-ker...@vger.kernel.org
Subject: [PATCH] drm/amdgpu: Fix Kernel Oops triggered by kfdtest

From: Joerg Roedel 

Running kfdtest on Kaveri triggers a kernel NULL-ptr dereference:

BUG: unable to handle kernel NULL pointer dereference at 

PGD 42c017067 P4D 42c017067 PUD 40f071067 PMD 0
Oops: 0010 [#1] SMP NOPTI
CPU: 0 PID: 13107 Comm: kfdtest Not tainted 4.20.0-rc2+ #11
Hardware name: Gigabyte Technology Co., Ltd. To be filled by 
O.E.M./F2A88XM-HD3, BIOS F6 05/28/2014
RIP: 0010:  (null)
Code: Bad RIP value.
RSP: 0018:c90001adbbf0 EFLAGS: 00010202
RAX: a0806240 RBX: 88842a0fbc00 RCX: 0002
RDX: 0001 RSI: 0004 RDI: 88842969
RBP: c90001adbbf8 R08: 2000 R09: 88842e542ec0
R10: 7feff778f008 R11: 7feff778f010 R12: 
R13: 88840f063a20 R14: 88842a0fbd20 R15: 0f43ff60
FS:  7feff7769740() GS:88842fa0() 
knlGS:
CS:  0010 DS:  ES:  CR0: 80050033
CR2: ffd6 CR3: 00040f122000 CR4: 000406f0
Call Trace:
 ? amdgpu_amdkfd_set_compute_idle+0x29/0x30 [amdgpu]
 register_process+0x140/0x150 [amdgpu]
 pqm_create_queue+0x395/0x560 [amdgpu]
 kfd_ioctl_create_queue+0x285/0x680 [amdgpu]
 kfd_ioctl+0x27f/0x450 [amdgpu]
 ? kfd_ioctl_destroy_queue+0x80/0x80 [amdgpu]
 do_vfs_ioctl+0x96/0x6a0
 ? __audit_syscall_entry+0xdd/0x130
 ? handle_mm_fault+0x11b/0x240
 ksys_ioctl+0x67/0x90
 __x64_sys_ioctl+0x1a/0x20
 do_syscall_64+0x61/0x190
 entry_SYSCALL_64_after_hwframe+0x44/0xa9

The reason is that the pp_funcs->switch_power_profile function pointer is not 
set for a Kaveri ASIC and thus the kernel calls a NULL pointer.

Add a check before calling the function to avoid that.

Signed-off-by: Joerg Roedel 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index f972cd156795..0ecedd30f2aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -337,8 +337,9 @@ enum amdgpu_pcie_gen {
(adev)->powerplay.pp_handle, request))
 
 #define amdgpu_dpm_switch_power_profile(adev, type, en) \
-   ((adev)->powerplay.pp_funcs->switch_power_profile(\
-   (adev)->powerplay.pp_handle, type, en))
+   if ((adev)->powerplay.pp_funcs->switch_power_profile != NULL) \
+   ((adev)->powerplay.pp_funcs->switch_power_profile(\
+   (adev)->powerplay.pp_handle, type, en))
 
 #define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
--
2.13.7

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Re: [PATCH v2 -next] drm/amdgpu: remove set but not used variable 'ring'

[Alex Deucher]

On Thu, Nov 15, 2018 at 11:12 AM YueHaibing  wrote:
>
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c: In function 'psp_v10_0_ring_stop':
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c:230:19: warning:
>  variable 'ring' set but not used [-Wunused-but-set-variable]
>
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c: In function 'psp_v3_1_ring_stop':
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c:359:19: warning:
>  variable ‘ring’ set but not used [-Wunused-but-set-variable]
>
> It not used since commit
> 4ef72453311a ("drm/amdgpu: added api for stopping psp ring (v2)")
>
> Signed-off-by: YueHaibing 
> Reviewed-by: Huang Rui 

Applied.  thanks!


> ---
> v2:also remove it in psp_v3_1_ring_stop
> ---
>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 ---
>  drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  | 3 ---
>  2 files changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 295c220..d78b430 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -240,12 +240,9 @@ static int psp_v10_0_ring_stop(struct psp_context *psp,
>enum psp_ring_type ring_type)
>  {
> int ret = 0;
> -   struct psp_ring *ring;
> unsigned int psp_ring_reg = 0;
> struct amdgpu_device *adev = psp->adev;
>
> -   ring = &psp->km_ring;
> -
> /* Write the ring destroy command to C2PMSG_64 */
> psp_ring_reg = 3 << 16;
> WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
> b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index e1ebf77..cc5e3ac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -356,12 +356,9 @@ static int psp_v3_1_ring_stop(struct psp_context *psp,
>   enum psp_ring_type ring_type)
>  {
> int ret = 0;
> -   struct psp_ring *ring;
> unsigned int psp_ring_reg = 0;
> struct amdgpu_device *adev = psp->adev;
>
> -   ring = &psp->km_ring;
> -
> /* Write the ring destroy command to C2PMSG_64 */
> psp_ring_reg = 3 << 16;
> WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
> --
> 2.7.0
>
>
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RE: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v3

[Russell, Kent]

Not a problem, I just saw the one missing patch when trying to rebase our KFD 
branch. I'll just put it on there instead. 

 Kent

-Original Message-
From: Kuehling, Felix 
Sent: Thursday, November 15, 2018 2:52 PM
To: Russell, Kent ; amd-gfx@lists.freedesktop.org
Cc: Russell, Kent ; Liu, Shaoyun 
Subject: RE: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same 
hive v3

Sorry, something is still missing here. The new variable vram_base_offset isn't 
used anywhere. We have some other changes in amd-kfd-staging to use that 
vram_base_offset that are probably missing on amd-staging-drm-next. This change 
won't have any effect as is.

Regards,
  Felix

-Original Message-
From: amd-gfx  On Behalf Of Russell, Kent
Sent: Thursday, November 15, 2018 2:23 PM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent ; Liu, Shaoyun 
Subject: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v3

From: Shaoyun Liu 

VM mapping will only fall back to P2P if XGMI mapping is not available

V2: Rebase onto 4.20
V3: Remove PCIe-related things

Change-Id: I7a854ab3d5c9958bd45d4fe439ea7e370a092e7a
Signed-off-by: Shaoyun Liu 
Reviewed-by: Felix Kuehling 
Reviewed-by: Huang Rui 
Reviewed-by: Christian König 
Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dad0e23..5aa60bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2011,6 +2011,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
uint64_t flags;
+   uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+   struct amdgpu_device *bo_adev;
int r;
 
if (clear || !bo) {
@@ -2029,9 +2031,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo->tbo.resv);
}
 
-   if (bo)
+   if (bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
-   else
+   bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id)
+   vram_base_offset = bo_adev->vm_manager.vram_base_offset;
+   else
+   return -EINVAL;
+   } else
flags = 0x0;
 
if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
-- 
2.7.4

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RE: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v3

[Kuehling, Felix]

Sorry, something is still missing here. The new variable vram_base_offset isn't 
used anywhere. We have some other changes in amd-kfd-staging to use that 
vram_base_offset that are probably missing on amd-staging-drm-next. This change 
won't have any effect as is.

Regards,
  Felix

-Original Message-
From: amd-gfx  On Behalf Of Russell, Kent
Sent: Thursday, November 15, 2018 2:23 PM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent ; Liu, Shaoyun 
Subject: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v3

From: Shaoyun Liu 

VM mapping will only fall back to P2P if XGMI mapping is not available

V2: Rebase onto 4.20
V3: Remove PCIe-related things

Change-Id: I7a854ab3d5c9958bd45d4fe439ea7e370a092e7a
Signed-off-by: Shaoyun Liu 
Reviewed-by: Felix Kuehling 
Reviewed-by: Huang Rui 
Reviewed-by: Christian König 
Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dad0e23..5aa60bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2011,6 +2011,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
uint64_t flags;
+   uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+   struct amdgpu_device *bo_adev;
int r;
 
if (clear || !bo) {
@@ -2029,9 +2031,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo->tbo.resv);
}
 
-   if (bo)
+   if (bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
-   else
+   bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id)
+   vram_base_offset = bo_adev->vm_manager.vram_base_offset;
+   else
+   return -EINVAL;
+   } else
flags = 0x0;
 
if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
-- 
2.7.4

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[PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v3

[Russell, Kent]

From: Shaoyun Liu 

VM mapping will only fall back to P2P if XGMI mapping is not available

V2: Rebase onto 4.20
V3: Remove PCIe-related things

Change-Id: I7a854ab3d5c9958bd45d4fe439ea7e370a092e7a
Signed-off-by: Shaoyun Liu 
Reviewed-by: Felix Kuehling 
Reviewed-by: Huang Rui 
Reviewed-by: Christian König 
Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dad0e23..5aa60bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2011,6 +2011,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
uint64_t flags;
+   uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+   struct amdgpu_device *bo_adev;
int r;
 
if (clear || !bo) {
@@ -2029,9 +2031,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo->tbo.resv);
}
 
-   if (bo)
+   if (bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
-   else
+   bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id)
+   vram_base_offset = bo_adev->vm_manager.vram_base_offset;
+   else
+   return -EINVAL;
+   } else
flags = 0x0;
 
if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
-- 
2.7.4

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[PATCH] drm/amdgpu: enable paging queue doorbell support v2

[Yang, Philip]

paging queues doorbell index use existing assignment sDMA_HI_PRI_ENGINE0/1
index, and increase SDMA_DOORBELL_RANGE size from 2 dwords to 4 dwords to
enable the new doorbell index.

v2: disable paging queue doorbell on Vega10 and Vega12 with SRIOV

Change-Id: I9adb965f16ee4089d261d9a22231337739184e49
Signed-off-by: Philip Yang 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 26 ++
 3 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 6f9c54978cc1..0eb42c29ecac 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -80,7 +80,7 @@ static void nbio_v6_1_sdma_doorbell_range(struct 
amdgpu_device *adev, int instan
 
if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
-   doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
+   doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
} else
doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index f8cee95d61cc..9342ee03d7d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -76,7 +76,7 @@ static void nbio_v7_4_sdma_doorbell_range(struct 
amdgpu_device *adev, int instan
 
if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
-   doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
+   doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
} else
doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index f4490cdd9804..1f19f15bb171 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device 
*adev, unsigned int i)
OFFSET, ring->doorbell_index);
WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
-   /* TODO: enable doorbell support */
-   /*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
- ring->doorbell_index);*/
 
-   sdma_v4_0_ring_set_wptr(ring);
+   /* paging queue doorbell index is already enabled at 
sdma_v4_0_gfx_resume */
+   sdma_v4_0_page_ring_set_wptr(ring);
 
/* set minor_ptr_update to 0 after wptr programed */
WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
@@ -1504,9 +1502,6 @@ static int sdma_v4_0_sw_init(void *handle)
ring->ring_obj = NULL;
ring->use_doorbell = true;
 
-   DRM_INFO("use_doorbell being set to: [%s]\n",
-   ring->use_doorbell?"true":"false");
-
if (adev->asic_type == CHIP_VEGA10)
ring->doorbell_index = (i == 0) ?
(AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1) 
//get DWORD offset
@@ -1516,6 +1511,8 @@ static int sdma_v4_0_sw_init(void *handle)
(AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get 
DWORD offset
: (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get 
DWORD offset
 
+   DRM_DEBUG("use_doorbell being set to: [%s] doorbell index %d\n",
+   ring->use_doorbell?"true":"false", 
ring->doorbell_index);
 
sprintf(ring->name, "sdma%d", i);
r = amdgpu_ring_init(adev, ring, 1024,
@@ -1529,7 +1526,20 @@ static int sdma_v4_0_sw_init(void *handle)
if (adev->sdma.has_page_queue) {
ring = &adev->sdma.instance[i].page;
ring->ring_obj = NULL;
-   ring->use_doorbell = false;
+   if (!amdgpu_sriov_vf(adev) || adev->asic_type == 
CHIP_VEGA20)
+   ring->use_doorbell = true;
+
+   if (adev->asic_type == CHIP_VEGA10)
+   ring->doorbell_index = (i == 0) ?
+   
(AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 << 1)
+   : 
(AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 << 1);
+   else
+   ring->doorbell_index = (i == 0) ?
+  

Re: [PATCH] drm/amdgpu: enable paging queue doorbell support

[Yang, Philip]

Thanks, I will disable paging queue doorbell on Vega10 and Vega12 with 
SRIOV.

Philip

On 2018-11-15 1:01 p.m., Kuehling, Felix wrote:
> You changed the doorbell routing in NBIO. I think that won't work for SR-IOV, 
> because it's not controlled by the guest OS there. We may need to disable 
> paging queue doorbell on Vega10 and Vega12 with SRIOV. For Vega20 we plan to 
> change the doorbell layout before it goes to production (Oak started working 
> on that). So on Vega20 we should be able to enable the doorbell for the 
> paging queue.
>
> Regards,
>Felix
>
> -Original Message-
> From: amd-gfx  On Behalf Of Yang, 
> Philip
> Sent: Thursday, November 15, 2018 12:54 PM
> To: Alex Deucher 
> Cc: amd-gfx list 
> Subject: Re: [PATCH] drm/amdgpu: enable paging queue doorbell support
>
> On 2018-11-15 11:43 a.m., Alex Deucher wrote:
>> On Thu, Nov 15, 2018 at 11:08 AM Yang, Philip  wrote:
>>> paging queues doorbell index use existing assignment
>>> sDMA_HI_PRI_ENGINE0/1 index, and increase SDMA_DOORBELL_RANGE size
>>> from 2 dwords to 4 dwords to enable the new doorbell index.
>>>
>>> Change-Id: I9adb965f16ee4089d261d9a22231337739184e49
>>> Signed-off-by: Philip Yang 
>> Is there a specific fw version requirement for this?  If so, we need
>> to add a check.  Also will this break SR-IOV due to the doorbell
>> mapping requirements for other OSes?  Have we resolved that yet?
>>
> Yes, new FW is required to enable paging queue, it's good idea to check FW 
> version when we enable paging queue later after new FW is checked in. paging 
> queue is not enabled yet.
> This change will not take effect until paging queue is enabled.
>
> This does not change doorbell mapping so it will not break SR-IOV. My 
> understanding is Doorbell mapping is good for vega10/12/20, but need update 
> for future chip.
>>> ---
>>>drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
>>>drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  2 +-
>>>drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 25 +
>>>3 files changed, 19 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>>> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>>> index 6f9c54978cc1..0eb42c29ecac 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>>> @@ -80,7 +80,7 @@ static void nbio_v6_1_sdma_doorbell_range(struct
>>> amdgpu_device *adev, int instan
>>>
>>>   if (use_doorbell) {
>>>   doorbell_range = REG_SET_FIELD(doorbell_range, 
>>> BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
>>> -   doorbell_range = REG_SET_FIELD(doorbell_range, 
>>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
>>> +   doorbell_range = REG_SET_FIELD(doorbell_range,
>>> + BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
>>>   } else
>>>   doorbell_range = REG_SET_FIELD(doorbell_range,
>>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>>> index f8cee95d61cc..9342ee03d7d4 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>>> @@ -76,7 +76,7 @@ static void nbio_v7_4_sdma_doorbell_range(struct
>>> amdgpu_device *adev, int instan
>>>
>>>   if (use_doorbell) {
>>>   doorbell_range = REG_SET_FIELD(doorbell_range, 
>>> BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
>>> -   doorbell_range = REG_SET_FIELD(doorbell_range, 
>>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
>>> +   doorbell_range = REG_SET_FIELD(doorbell_range,
>>> + BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
>>>   } else
>>>   doorbell_range = REG_SET_FIELD(doorbell_range,
>>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> index f4490cdd9804..96c9e83204b7 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> @@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device 
>>> *adev, unsigned int i)
>>>   OFFSET, ring->doorbell_index);
>>>   WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
>>>   WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
>>> -   /* TODO: enable doorbell support */
>>> -   /*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
>>> - ring->doorbell_index);*/
>>>
>>> -   sdma_v4_0_ring_set_wptr(ring);
>>> +   /* paging queue doorbell index is already enabled at 
>>> sdma_v4_0_gfx_resume */
>>> +   sdma_v4_0_page_ring_set_wptr(ring);
>>>
>>>   /* set minor_ptr_update to 0 after wptr programed */
>>>   WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); @@ -1504,9
>>> +1502,6 @@ static int sdma_v4_0_sw_init(void *handle)
>>> 

RE: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v2

[Kuehling, Felix]

Hmm, we should remove the PCIe portion of this change. We just added some extra 
checks there on amd-kfd-staging that should make it closer to upstreamable. For 
now, just handle the XGMI case, but return -EINVAL in the else-branch (for 
other remote VRAM cases).

Regards,
  Felix

From: Russell, Kent
Sent: Thursday, November 15, 2018 1:04 PM
To: Kuehling, Felix ; amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun 
Subject: Re: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same 
hive v2

It was merged to 4.19 on Sept 21. It got missed on the 4.20 rebase.

Kent

KENT RUSSELL
Sr. Software Engineer | Linux Compute Kernel
1 Commerce Valley Drive East
Markham, ON L3T 7X6
O +(1) 289-695-2122 | Ext 72122

From: Kuehling, Felix
Sent: Thursday, November 15, 2018 12:57:44 PM
To: Russell, Kent; 
amd-gfx@lists.freedesktop.org
Cc: Russell, Kent; Liu, Shaoyun
Subject: RE: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same 
hive v2

This change is not suitable for amd-staging-drm-next. PCIe P2P was not enabled 
on amd-staging-drm-next because it's not reliable yet. This change enables it 
even in situations that are not safe (including small BAR systems).

Why are you porting this change to amd-staging-drm-next? Does anyone depend on 
XGMI support on this branch?

Regards,
  Felix

-Original Message-
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Russell, Kent
Sent: Thursday, November 15, 2018 11:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent mailto:kent.russ...@amd.com>>; Liu, 
Shaoyun mailto:shaoyun@amd.com>>
Subject: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v2

From: Shaoyun Liu mailto:shaoyun@amd.com>>

VM mapping will only fall back to P2P if XGMI mapping is not available

V2: Rebase onto 4.20

Change-Id: I7a854ab3d5c9958bd45d4fe439ea7e370a092e7a
Signed-off-by: Shaoyun Liu mailto:shaoyun@amd.com>>
Reviewed-by: Felix Kuehling 
mailto:felix.kuehl...@amd.com>>
Reviewed-by: Huang Rui mailto:ray.hu...@amd.com>>
Reviewed-by: Christian König 
mailto:christian.koe...@amd.com>>
Signed-off-by: Kent Russell mailto:kent.russ...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dad0e23..576d168 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2011,6 +2011,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 struct drm_mm_node *nodes;
 struct dma_fence *exclusive, **last_update;
 uint64_t flags;
+   uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+   struct amdgpu_device *bo_adev;
 int r;

 if (clear || !bo) {
@@ -2029,9 +2031,19 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 exclusive = reservation_object_get_excl(bo->tbo.resv);
 }

-   if (bo)
+   if (bo) {
 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
-   else
+   bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (mem && mem->mem_type == TTM_PL_VRAM && adev != bo_adev) {
+   if (adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == 
bo_adev->gmc.xgmi.hive_id) {
+   vram_base_offset = 
bo_adev->vm_manager.vram_base_offset;
+   } else {
+   flags |= AMDGPU_PTE_SYSTEM;
+   vram_base_offset = bo_adev->gmc.aper_base;
+   }
+   }
+   } else
 flags = 0x0;

 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
--
2.7.4

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Re: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v2

[Russell, Kent]

It was merged to 4.19 on Sept 21. It got missed on the 4.20 rebase.

Kent

KENT RUSSELL
Sr. Software Engineer | Linux Compute Kernel
1 Commerce Valley Drive East
Markham, ON L3T 7X6
O +(1) 289-695-2122 | Ext 72122

From: Kuehling, Felix
Sent: Thursday, November 15, 2018 12:57:44 PM
To: Russell, Kent; amd-gfx@lists.freedesktop.org
Cc: Russell, Kent; Liu, Shaoyun
Subject: RE: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same 
hive v2

This change is not suitable for amd-staging-drm-next. PCIe P2P was not enabled 
on amd-staging-drm-next because it's not reliable yet. This change enables it 
even in situations that are not safe (including small BAR systems).

Why are you porting this change to amd-staging-drm-next? Does anyone depend on 
XGMI support on this branch?

Regards,
  Felix

-Original Message-
From: amd-gfx  On Behalf Of Russell, Kent
Sent: Thursday, November 15, 2018 11:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent ; Liu, Shaoyun 
Subject: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v2

From: Shaoyun Liu 

VM mapping will only fall back to P2P if XGMI mapping is not available

V2: Rebase onto 4.20

Change-Id: I7a854ab3d5c9958bd45d4fe439ea7e370a092e7a
Signed-off-by: Shaoyun Liu 
Reviewed-by: Felix Kuehling 
Reviewed-by: Huang Rui 
Reviewed-by: Christian König 
Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dad0e23..576d168 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2011,6 +2011,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 struct drm_mm_node *nodes;
 struct dma_fence *exclusive, **last_update;
 uint64_t flags;
+   uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+   struct amdgpu_device *bo_adev;
 int r;

 if (clear || !bo) {
@@ -2029,9 +2031,19 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 exclusive = reservation_object_get_excl(bo->tbo.resv);
 }

-   if (bo)
+   if (bo) {
 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
-   else
+   bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (mem && mem->mem_type == TTM_PL_VRAM && adev != bo_adev) {
+   if (adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == 
bo_adev->gmc.xgmi.hive_id) {
+   vram_base_offset = 
bo_adev->vm_manager.vram_base_offset;
+   } else {
+   flags |= AMDGPU_PTE_SYSTEM;
+   vram_base_offset = bo_adev->gmc.aper_base;
+   }
+   }
+   } else
 flags = 0x0;

 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
--
2.7.4

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RE: [PATCH] drm/amdgpu: enable paging queue doorbell support

[Kuehling, Felix]

You changed the doorbell routing in NBIO. I think that won't work for SR-IOV, 
because it's not controlled by the guest OS there. We may need to disable 
paging queue doorbell on Vega10 and Vega12 with SRIOV. For Vega20 we plan to 
change the doorbell layout before it goes to production (Oak started working on 
that). So on Vega20 we should be able to enable the doorbell for the paging 
queue.

Regards,
  Felix

-Original Message-
From: amd-gfx  On Behalf Of Yang, Philip
Sent: Thursday, November 15, 2018 12:54 PM
To: Alex Deucher 
Cc: amd-gfx list 
Subject: Re: [PATCH] drm/amdgpu: enable paging queue doorbell support

On 2018-11-15 11:43 a.m., Alex Deucher wrote:
> On Thu, Nov 15, 2018 at 11:08 AM Yang, Philip  wrote:
>> paging queues doorbell index use existing assignment 
>> sDMA_HI_PRI_ENGINE0/1 index, and increase SDMA_DOORBELL_RANGE size 
>> from 2 dwords to 4 dwords to enable the new doorbell index.
>>
>> Change-Id: I9adb965f16ee4089d261d9a22231337739184e49
>> Signed-off-by: Philip Yang 
> Is there a specific fw version requirement for this?  If so, we need 
> to add a check.  Also will this break SR-IOV due to the doorbell 
> mapping requirements for other OSes?  Have we resolved that yet?
>
Yes, new FW is required to enable paging queue, it's good idea to check FW 
version when we enable paging queue later after new FW is checked in. paging 
queue is not enabled yet.
This change will not take effect until paging queue is enabled.

This does not change doorbell mapping so it will not break SR-IOV. My 
understanding is Doorbell mapping is good for vega10/12/20, but need update for 
future chip.
>> ---
>>   drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
>>   drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  2 +-
>>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 25 +
>>   3 files changed, 19 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> index 6f9c54978cc1..0eb42c29ecac 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> @@ -80,7 +80,7 @@ static void nbio_v6_1_sdma_doorbell_range(struct 
>> amdgpu_device *adev, int instan
>>
>>  if (use_doorbell) {
>>  doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
>> -   doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
>> +   doorbell_range = REG_SET_FIELD(doorbell_range, 
>> + BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
>>  } else
>>  doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> index f8cee95d61cc..9342ee03d7d4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> @@ -76,7 +76,7 @@ static void nbio_v7_4_sdma_doorbell_range(struct 
>> amdgpu_device *adev, int instan
>>
>>  if (use_doorbell) {
>>  doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
>> -   doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
>> +   doorbell_range = REG_SET_FIELD(doorbell_range, 
>> + BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
>>  } else
>>  doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index f4490cdd9804..96c9e83204b7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device 
>> *adev, unsigned int i)
>>  OFFSET, ring->doorbell_index);
>>  WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
>>  WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
>> -   /* TODO: enable doorbell support */
>> -   /*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
>> - ring->doorbell_index);*/
>>
>> -   sdma_v4_0_ring_set_wptr(ring);
>> +   /* paging queue doorbell index is already enabled at 
>> sdma_v4_0_gfx_resume */
>> +   sdma_v4_0_page_ring_set_wptr(ring);
>>
>>  /* set minor_ptr_update to 0 after wptr programed */
>>  WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); @@ -1504,9 
>> +1502,6 @@ static int sdma_v4_0_sw_init(void *handle)
>>  ring->ring_obj = NULL;
>>  ring->use_doorbell = true;
>>
>> -   DRM_INFO("use_doorbell being set to: [%s]\n",
>> -   ring->use_doorbell?"true":"false");
>> -
>>  if (adev->asic_type == CHIP_VEGA10

RE: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v2

[Kuehling, Felix]

This change is not suitable for amd-staging-drm-next. PCIe P2P was not enabled 
on amd-staging-drm-next because it's not reliable yet. This change enables it 
even in situations that are not safe (including small BAR systems).

Why are you porting this change to amd-staging-drm-next? Does anyone depend on 
XGMI support on this branch?

Regards,
  Felix

-Original Message-
From: amd-gfx  On Behalf Of Russell, Kent
Sent: Thursday, November 15, 2018 11:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent ; Liu, Shaoyun 
Subject: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v2

From: Shaoyun Liu 

VM mapping will only fall back to P2P if XGMI mapping is not available

V2: Rebase onto 4.20

Change-Id: I7a854ab3d5c9958bd45d4fe439ea7e370a092e7a
Signed-off-by: Shaoyun Liu 
Reviewed-by: Felix Kuehling 
Reviewed-by: Huang Rui 
Reviewed-by: Christian König 
Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dad0e23..576d168 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2011,6 +2011,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
uint64_t flags;
+   uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+   struct amdgpu_device *bo_adev;
int r;
 
if (clear || !bo) {
@@ -2029,9 +2031,19 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo->tbo.resv);
}
 
-   if (bo)
+   if (bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
-   else
+   bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (mem && mem->mem_type == TTM_PL_VRAM && adev != bo_adev) {
+   if (adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == 
bo_adev->gmc.xgmi.hive_id) {
+   vram_base_offset = 
bo_adev->vm_manager.vram_base_offset;
+   } else {
+   flags |= AMDGPU_PTE_SYSTEM;
+   vram_base_offset = bo_adev->gmc.aper_base;
+   }
+   }
+   } else
flags = 0x0;
 
if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: enable paging queue doorbell support

[Yang, Philip]

On 2018-11-15 11:43 a.m., Alex Deucher wrote:
> On Thu, Nov 15, 2018 at 11:08 AM Yang, Philip  wrote:
>> paging queues doorbell index use existing assignment sDMA_HI_PRI_ENGINE0/1
>> index, and increase SDMA_DOORBELL_RANGE size from 2 dwords to 4 dwords to
>> enable the new doorbell index.
>>
>> Change-Id: I9adb965f16ee4089d261d9a22231337739184e49
>> Signed-off-by: Philip Yang 
> Is there a specific fw version requirement for this?  If so, we need
> to add a check.  Also will this break SR-IOV due to the doorbell
> mapping requirements for other OSes?  Have we resolved that yet?
>
Yes, new FW is required to enable paging queue, it's good idea to check 
FW version
when we enable paging queue later after new FW is checked in. paging 
queue is not enabled yet.
This change will not take effect until paging queue is enabled.

This does not change doorbell mapping so it will not break SR-IOV. My 
understanding is Doorbell
mapping is good for vega10/12/20, but need update for future chip.
>> ---
>>   drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
>>   drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  2 +-
>>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 25 +
>>   3 files changed, 19 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> index 6f9c54978cc1..0eb42c29ecac 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> @@ -80,7 +80,7 @@ static void nbio_v6_1_sdma_doorbell_range(struct 
>> amdgpu_device *adev, int instan
>>
>>  if (use_doorbell) {
>>  doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
>> -   doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
>> +   doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
>>  } else
>>  doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
>> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> index f8cee95d61cc..9342ee03d7d4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>> @@ -76,7 +76,7 @@ static void nbio_v7_4_sdma_doorbell_range(struct 
>> amdgpu_device *adev, int instan
>>
>>  if (use_doorbell) {
>>  doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
>> -   doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
>> +   doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
>>  } else
>>  doorbell_range = REG_SET_FIELD(doorbell_range, 
>> BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index f4490cdd9804..96c9e83204b7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device 
>> *adev, unsigned int i)
>>  OFFSET, ring->doorbell_index);
>>  WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
>>  WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
>> -   /* TODO: enable doorbell support */
>> -   /*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
>> - ring->doorbell_index);*/
>>
>> -   sdma_v4_0_ring_set_wptr(ring);
>> +   /* paging queue doorbell index is already enabled at 
>> sdma_v4_0_gfx_resume */
>> +   sdma_v4_0_page_ring_set_wptr(ring);
>>
>>  /* set minor_ptr_update to 0 after wptr programed */
>>  WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
>> @@ -1504,9 +1502,6 @@ static int sdma_v4_0_sw_init(void *handle)
>>  ring->ring_obj = NULL;
>>  ring->use_doorbell = true;
>>
>> -   DRM_INFO("use_doorbell being set to: [%s]\n",
>> -   ring->use_doorbell?"true":"false");
>> -
>>  if (adev->asic_type == CHIP_VEGA10)
>>  ring->doorbell_index = (i == 0) ?
>>  (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 
>> 1) //get DWORD offset
>> @@ -1516,6 +1511,8 @@ static int sdma_v4_0_sw_init(void *handle)
>>  (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get 
>> DWORD offset
>>  : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // 
>> get DWORD offset
>>
>> +   DRM_INFO("use_doorbell being set to: [%s] doorbell index 
>> %d\n",
>> +   ring->use_doorbell?"true":"false", 
>> ring->doorbell_index);
>>
> I think we can drop these 

Re: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v2

[Deucher, Alexander]

Reviewed-by: Alex  Deucher 


From: amd-gfx  on behalf of Russell, 
Kent 
Sent: Thursday, November 15, 2018 11:54:27 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent; Liu, Shaoyun
Subject: [PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v2

From: Shaoyun Liu 

VM mapping will only fall back to P2P if XGMI mapping is not available

V2: Rebase onto 4.20

Change-Id: I7a854ab3d5c9958bd45d4fe439ea7e370a092e7a
Signed-off-by: Shaoyun Liu 
Reviewed-by: Felix Kuehling 
Reviewed-by: Huang Rui 
Reviewed-by: Christian König 
Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dad0e23..576d168 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2011,6 +2011,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 struct drm_mm_node *nodes;
 struct dma_fence *exclusive, **last_update;
 uint64_t flags;
+   uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+   struct amdgpu_device *bo_adev;
 int r;

 if (clear || !bo) {
@@ -2029,9 +2031,19 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 exclusive = reservation_object_get_excl(bo->tbo.resv);
 }

-   if (bo)
+   if (bo) {
 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
-   else
+   bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (mem && mem->mem_type == TTM_PL_VRAM && adev != bo_adev) {
+   if (adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == 
bo_adev->gmc.xgmi.hive_id) {
+   vram_base_offset = 
bo_adev->vm_manager.vram_base_offset;
+   } else {
+   flags |= AMDGPU_PTE_SYSTEM;
+   vram_base_offset = bo_adev->gmc.aper_base;
+   }
+   }
+   } else
 flags = 0x0;

 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
--
2.7.4

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[PATCH] drm/amdgpu : Use XGMI mapping when devices on the same hive v2

[Russell, Kent]

From: Shaoyun Liu 

VM mapping will only fall back to P2P if XGMI mapping is not available

V2: Rebase onto 4.20

Change-Id: I7a854ab3d5c9958bd45d4fe439ea7e370a092e7a
Signed-off-by: Shaoyun Liu 
Reviewed-by: Felix Kuehling 
Reviewed-by: Huang Rui 
Reviewed-by: Christian König 
Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index dad0e23..576d168 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2011,6 +2011,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
uint64_t flags;
+   uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+   struct amdgpu_device *bo_adev;
int r;
 
if (clear || !bo) {
@@ -2029,9 +2031,19 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo->tbo.resv);
}
 
-   if (bo)
+   if (bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
-   else
+   bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (mem && mem->mem_type == TTM_PL_VRAM && adev != bo_adev) {
+   if (adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == 
bo_adev->gmc.xgmi.hive_id) {
+   vram_base_offset = 
bo_adev->vm_manager.vram_base_offset;
+   } else {
+   flags |= AMDGPU_PTE_SYSTEM;
+   vram_base_offset = bo_adev->gmc.aper_base;
+   }
+   }
+   } else
flags = 0x0;
 
if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: enable paging queue doorbell support

[Alex Deucher]

On Thu, Nov 15, 2018 at 11:08 AM Yang, Philip  wrote:
>
> paging queues doorbell index use existing assignment sDMA_HI_PRI_ENGINE0/1
> index, and increase SDMA_DOORBELL_RANGE size from 2 dwords to 4 dwords to
> enable the new doorbell index.
>
> Change-Id: I9adb965f16ee4089d261d9a22231337739184e49
> Signed-off-by: Philip Yang 

Is there a specific fw version requirement for this?  If so, we need
to add a check.  Also will this break SR-IOV due to the doorbell
mapping requirements for other OSes?  Have we resolved that yet?

> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  2 +-
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 25 +
>  3 files changed, 19 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index 6f9c54978cc1..0eb42c29ecac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -80,7 +80,7 @@ static void nbio_v6_1_sdma_doorbell_range(struct 
> amdgpu_device *adev, int instan
>
> if (use_doorbell) {
> doorbell_range = REG_SET_FIELD(doorbell_range, 
> BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
> -   doorbell_range = REG_SET_FIELD(doorbell_range, 
> BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
> +   doorbell_range = REG_SET_FIELD(doorbell_range, 
> BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
> } else
> doorbell_range = REG_SET_FIELD(doorbell_range, 
> BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index f8cee95d61cc..9342ee03d7d4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -76,7 +76,7 @@ static void nbio_v7_4_sdma_doorbell_range(struct 
> amdgpu_device *adev, int instan
>
> if (use_doorbell) {
> doorbell_range = REG_SET_FIELD(doorbell_range, 
> BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
> -   doorbell_range = REG_SET_FIELD(doorbell_range, 
> BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
> +   doorbell_range = REG_SET_FIELD(doorbell_range, 
> BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
> } else
> doorbell_range = REG_SET_FIELD(doorbell_range, 
> BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index f4490cdd9804..96c9e83204b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device 
> *adev, unsigned int i)
> OFFSET, ring->doorbell_index);
> WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
> WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
> -   /* TODO: enable doorbell support */
> -   /*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
> - ring->doorbell_index);*/
>
> -   sdma_v4_0_ring_set_wptr(ring);
> +   /* paging queue doorbell index is already enabled at 
> sdma_v4_0_gfx_resume */
> +   sdma_v4_0_page_ring_set_wptr(ring);
>
> /* set minor_ptr_update to 0 after wptr programed */
> WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
> @@ -1504,9 +1502,6 @@ static int sdma_v4_0_sw_init(void *handle)
> ring->ring_obj = NULL;
> ring->use_doorbell = true;
>
> -   DRM_INFO("use_doorbell being set to: [%s]\n",
> -   ring->use_doorbell?"true":"false");
> -
> if (adev->asic_type == CHIP_VEGA10)
> ring->doorbell_index = (i == 0) ?
> (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1) 
> //get DWORD offset
> @@ -1516,6 +1511,8 @@ static int sdma_v4_0_sw_init(void *handle)
> (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get 
> DWORD offset
> : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // 
> get DWORD offset
>
> +   DRM_INFO("use_doorbell being set to: [%s] doorbell index 
> %d\n",
> +   ring->use_doorbell?"true":"false", 
> ring->doorbell_index);
>

I think we can drop these messages in general.  Looks like leftover
debugging output.

> sprintf(ring->name, "sdma%d", i);
> r = amdgpu_ring_init(adev, ring, 1024,
> @@ -1529,7 +1526,19 @@ static int sdma_v4_0_sw_init(void *handle)
> if (adev->sdma.has_page_queue) {
> ring = &adev->sdma.instance[i].page;
> ring->ring_obj = NULL;
> -   ring->use_doorbell = false;
> +   ring->use_doorbell = true;
> +
> +   if (adev->asic_type == CHIP_VEGA10)
> +  

Re: [PATCH -next] drm/amdgpu: remove set but not used variable 'ring'

[YueHaibing]

On 2018/11/15 19:49, Huang, Ray wrote:
>> -Original Message-
>> From: YueHaibing [mailto:yuehaib...@huawei.com]
>> Sent: Thursday, November 15, 2018 6:52 PM
>> To: Deucher, Alexander ; Koenig, Christian
>> ; Zhou, David(ChunMing)
>> ; airl...@linux.ie; Liu, Shaoyun
>> ; Francis, David ; Huang,
>> Ray ; Xu, Feifei ; Gao, Likun
>> 
>> Cc: YueHaibing ; amd-gfx@lists.freedesktop.org;
>> dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; kernel-
>> janit...@vger.kernel.org
>> Subject: [PATCH -next] drm/amdgpu: remove set but not used variable 'ring'
>>
>> Fixes gcc '-Wunused-but-set-variable' warning:
>>
>> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c: In function
>> 'psp_v10_0_ring_stop':
>> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c:230:19: warning:
>>  variable 'ring' set but not used [-Wunused-but-set-variable]
>>
>> It not used since commit
>> 4ef72453311a ("drm/amdgpu: added api for stopping psp ring (v2)")
> 
> Thanks, please also remove the similar code in psp_v3_1. 
> With that updates, patch is Reviewed-by: Huang Rui 
> 

Ok, will send v2.

>>
>> Signed-off-by: YueHaibing 
>> ---
>>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 ---
>>  1 file changed, 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> index 295c220..d78b430 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> @@ -240,12 +240,9 @@ static int psp_v10_0_ring_stop(struct psp_context
>> *psp,
>> enum psp_ring_type ring_type)  {
>>  int ret = 0;
>> -struct psp_ring *ring;
>>  unsigned int psp_ring_reg = 0;
>>  struct amdgpu_device *adev = psp->adev;
>>
>> -ring = &psp->km_ring;
>> -
>>  /* Write the ring destroy command to C2PMSG_64 */
>>  psp_ring_reg = 3 << 16;
>>  WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
>>
>>
>>
>>
> 
> 
> .
> 

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[PATCH -next] drm/amdgpu: remove set but not used variable 'ring'

[YueHaibing]

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdgpu/psp_v10_0.c: In function 'psp_v10_0_ring_stop':
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c:230:19: warning:
 variable 'ring' set but not used [-Wunused-but-set-variable]

It not used since commit
4ef72453311a ("drm/amdgpu: added api for stopping psp ring (v2)")

Signed-off-by: YueHaibing 
---
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 295c220..d78b430 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -240,12 +240,9 @@ static int psp_v10_0_ring_stop(struct psp_context *psp,
   enum psp_ring_type ring_type)
 {
int ret = 0;
-   struct psp_ring *ring;
unsigned int psp_ring_reg = 0;
struct amdgpu_device *adev = psp->adev;
 
-   ring = &psp->km_ring;
-
/* Write the ring destroy command to C2PMSG_64 */
psp_ring_reg = 3 << 16;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);





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[PATCH v2 -next] drm/amdgpu: remove set but not used variable 'ring'

[YueHaibing]

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdgpu/psp_v10_0.c: In function 'psp_v10_0_ring_stop':
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c:230:19: warning:
 variable 'ring' set but not used [-Wunused-but-set-variable]

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c: In function 'psp_v3_1_ring_stop':
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c:359:19: warning:
 variable ‘ring’ set but not used [-Wunused-but-set-variable]

It not used since commit
4ef72453311a ("drm/amdgpu: added api for stopping psp ring (v2)")

Signed-off-by: YueHaibing 
Reviewed-by: Huang Rui 
---
v2:also remove it in psp_v3_1_ring_stop
---
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 ---
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 295c220..d78b430 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -240,12 +240,9 @@ static int psp_v10_0_ring_stop(struct psp_context *psp,
   enum psp_ring_type ring_type)
 {
int ret = 0;
-   struct psp_ring *ring;
unsigned int psp_ring_reg = 0;
struct amdgpu_device *adev = psp->adev;
 
-   ring = &psp->km_ring;
-
/* Write the ring destroy command to C2PMSG_64 */
psp_ring_reg = 3 << 16;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index e1ebf77..cc5e3ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -356,12 +356,9 @@ static int psp_v3_1_ring_stop(struct psp_context *psp,
  enum psp_ring_type ring_type)
 {
int ret = 0;
-   struct psp_ring *ring;
unsigned int psp_ring_reg = 0;
struct amdgpu_device *adev = psp->adev;
 
-   ring = &psp->km_ring;
-
/* Write the ring destroy command to C2PMSG_64 */
psp_ring_reg = 3 << 16;
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
-- 
2.7.0


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[PATCH] drm/amdgpu: enable paging queue doorbell support

[Yang, Philip]

paging queues doorbell index use existing assignment sDMA_HI_PRI_ENGINE0/1
index, and increase SDMA_DOORBELL_RANGE size from 2 dwords to 4 dwords to
enable the new doorbell index.

Change-Id: I9adb965f16ee4089d261d9a22231337739184e49
Signed-off-by: Philip Yang 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 25 +
 3 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 6f9c54978cc1..0eb42c29ecac 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -80,7 +80,7 @@ static void nbio_v6_1_sdma_doorbell_range(struct 
amdgpu_device *adev, int instan
 
if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
-   doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
+   doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
} else
doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index f8cee95d61cc..9342ee03d7d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -76,7 +76,7 @@ static void nbio_v7_4_sdma_doorbell_range(struct 
amdgpu_device *adev, int instan
 
if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
-   doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
+   doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 4);
} else
doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index f4490cdd9804..96c9e83204b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -925,11 +925,9 @@ static void sdma_v4_0_page_resume(struct amdgpu_device 
*adev, unsigned int i)
OFFSET, ring->doorbell_index);
WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
-   /* TODO: enable doorbell support */
-   /*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
- ring->doorbell_index);*/
 
-   sdma_v4_0_ring_set_wptr(ring);
+   /* paging queue doorbell index is already enabled at 
sdma_v4_0_gfx_resume */
+   sdma_v4_0_page_ring_set_wptr(ring);
 
/* set minor_ptr_update to 0 after wptr programed */
WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
@@ -1504,9 +1502,6 @@ static int sdma_v4_0_sw_init(void *handle)
ring->ring_obj = NULL;
ring->use_doorbell = true;
 
-   DRM_INFO("use_doorbell being set to: [%s]\n",
-   ring->use_doorbell?"true":"false");
-
if (adev->asic_type == CHIP_VEGA10)
ring->doorbell_index = (i == 0) ?
(AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1) 
//get DWORD offset
@@ -1516,6 +1511,8 @@ static int sdma_v4_0_sw_init(void *handle)
(AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get 
DWORD offset
: (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get 
DWORD offset
 
+   DRM_INFO("use_doorbell being set to: [%s] doorbell index %d\n",
+   ring->use_doorbell?"true":"false", 
ring->doorbell_index);
 
sprintf(ring->name, "sdma%d", i);
r = amdgpu_ring_init(adev, ring, 1024,
@@ -1529,7 +1526,19 @@ static int sdma_v4_0_sw_init(void *handle)
if (adev->sdma.has_page_queue) {
ring = &adev->sdma.instance[i].page;
ring->ring_obj = NULL;
-   ring->use_doorbell = false;
+   ring->use_doorbell = true;
+
+   if (adev->asic_type == CHIP_VEGA10)
+   ring->doorbell_index = (i == 0) ?
+   
(AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 << 1)
+   : 
(AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 << 1);
+   else
+   ring->doorbell_index = (i == 0) ?
+   
(AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 << 1)
+   : 
(AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 << 1)

[PATCH v3 2/2] drm/amd: Add abm level drm property

[David Francis]

Adaptive Backlight Management (ABM) is a feature
that reduces backlight level to save power, while
increasing pixel contrast and pixel luminance
to maintain readability and image quality.

ABM will adjust in response to the
pixel luminance of the displayed content.

ABM is made available as a drm property on eDP
monitors called "abm level", which ranges from 0 to 4.
When this property is set to 0, ABM is off.  Levels 1
to 4 represent different ranges of backlight reduction.
At higher levels both the backlight reduction and pixel
adjustment will be greater.

ABM requires DMCU firmware, which is currently available for
Raven ASICs only.  If the feature does not work, please
ensure your firmware is up to date.

v2:
Fix commit message, only attach property if DMCU loaded
v3:
Storre ABM level in crtc state to accommodate dc

Signed-off-by: David Francis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  5 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  2 ++
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 35 ---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  3 ++
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 11 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |  1 +
 6 files changed, 52 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 7d6a36bca9dd..ced8cefa223b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -637,6 +637,11 @@ int amdgpu_display_modeset_create_props(struct 
amdgpu_device *adev)
 "freesync_capable");
if (!adev->mode_info.freesync_capable_property)
return -ENOMEM;
+   adev->mode_info.abm_level_property =
+   drm_property_create_range(adev->ddev, 0,
+   "abm level", 0, 4);
+   if (!adev->mode_info.abm_level_property)
+   return -ENOMEM;
}
 
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 1627dd3413c7..2938635c0fc1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -342,6 +342,8 @@ struct amdgpu_mode_info {
struct drm_property *freesync_property;
/* it is used to know about display capability of freesync mode */
struct drm_property *freesync_capable_property;
+   /* Adaptive Backlight Modulation (power feature) */
+   struct drm_property *abm_level_property;
/* hardcoded DFP edid from BIOS */
struct edid *bios_hardcoded_edid;
int bios_hardcoded_edid_size;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f71febb4210d..090a602f3014 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2920,6 +2920,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
state->adjust = cur->adjust;
state->vrr_infopacket = cur->vrr_infopacket;
state->freesync_enabled = cur->freesync_enabled;
+   state->abm_level = cur->abm_level;
 
/* TODO Duplicate dc_stream after objects are stream object is 
flattened */
 
@@ -3038,6 +3039,9 @@ int amdgpu_dm_connector_atomic_set_property(struct 
drm_connector *connector,
} else if (property == adev->mode_info.freesync_capable_property) {
dm_new_state->freesync_capable = val;
ret = 0;
+   } else if (property == adev->mode_info.abm_level_property) {
+   dm_new_state->abm_level = val;
+   ret = 0;
}
 
return ret;
@@ -3086,7 +3090,11 @@ int amdgpu_dm_connector_atomic_get_property(struct 
drm_connector *connector,
} else if (property == adev->mode_info.freesync_capable_property) {
*val = dm_state->freesync_capable;
ret = 0;
+   } else if (property == adev->mode_info.abm_level_property) {
+   *val = dm_state->abm_level;
+   ret = 0;
}
+
return ret;
 }
 
@@ -3151,6 +3159,7 @@ amdgpu_dm_connector_atomic_duplicate_state(struct 
drm_connector *connector)
 
new_state->freesync_capable = state->freesync_capable;
new_state->freesync_enable = state->freesync_enable;
+   new_state->abm_level = state->abm_level;
 
return &new_state->base;
 }
@@ -3904,6 +3913,12 @@ void amdgpu_dm_connector_init_helper(struct 
amdgpu_display_manager *dm,
drm_object_attach_property(&aconnector->base.base,
adev->mode_info.freesync_capable_property, 0);
}
+
+   if (connector_type == DRM_MODE_CONNECTOR_eDP &&
+   dc_is_dmcu_initialized(adev->dm.dc)) {
+   drm_object_attach_property(&aconnector->base.base,
+   

[PATCH v3 1/2] drm/amd: Load DMCU IRAM

[David Francis]

DMCU IRAM must be loaded by the driver before DMCU
can function.

Move the IRAM code out of the shadows and into a new file
modules/power/power_helpers.c

The IRAM table contains the backlight curve and ABM parameters

Add this new file to the Makefiles

Call dmcu_load_iram in late init of DM

Move struct dmcu_version from dc.h to dmcu.h to allow
dmcu to be included on its own

Signed-off-by: David Francis 
---
 drivers/gpu/drm/amd/display/Makefile  |   3 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  21 ++
 drivers/gpu/drm/amd/display/dc/dc.h   |   8 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h  |   7 +
 .../drm/amd/display/modules/power/Makefile|  31 ++
 .../amd/display/modules/power/power_helpers.c | 326 ++
 .../amd/display/modules/power/power_helpers.h |  47 +++
 7 files changed, 435 insertions(+), 8 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/modules/power/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/modules/power/power_helpers.c
 create mode 100644 drivers/gpu/drm/amd/display/modules/power/power_helpers.h

diff --git a/drivers/gpu/drm/amd/display/Makefile 
b/drivers/gpu/drm/amd/display/Makefile
index c97dc9613325..cfde1568c79a 100644
--- a/drivers/gpu/drm/amd/display/Makefile
+++ b/drivers/gpu/drm/amd/display/Makefile
@@ -32,11 +32,12 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/inc
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/info_packet
+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/power
 
 #TODO: remove when Timing Sync feature is complete
 subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
 
-DAL_LIBS = amdgpu_dm dcmodules/freesync modules/color 
modules/info_packet
+DAL_LIBS = amdgpu_dm dcmodules/freesync modules/color 
modules/info_packet modules/power
 
 AMD_DAL = $(addsuffix /Makefile, $(addprefix 
$(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0c1a533eb531..f71febb4210d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -72,6 +72,7 @@
 #endif
 
 #include "modules/inc/mod_freesync.h"
+#include "modules/power/power_helpers.h"
 
 #define FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -643,6 +644,26 @@ static int dm_late_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+   struct dmcu_iram_parameters params;
+   unsigned int linear_lut[16];
+   int i;
+   struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
+   bool ret;
+
+   for (i = 0; i < 16; i++)
+   linear_lut[i] = 0x * i / 15;
+
+   params.set = 0;
+   params.backlight_ramping_start = 0x;
+   params.backlight_ramping_reduction = 0x;
+   params.backlight_lut_array_size = 16;
+   params.backlight_lut_array = linear_lut;
+
+   ret = dmcu_load_iram(dmcu, params);
+
+   if (!ret)
+   return -EINVAL;
+
return detect_mst_link_for_all_connectors(adev->ddev);
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 18865a76ea55..6b0988310138 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -36,6 +36,7 @@
 
 #include "inc/hw_sequencer.h"
 #include "inc/compressor.h"
+#include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
 #define DC_VER "3.2.06"
@@ -47,13 +48,6 @@
 
/***
  * Display Core Interfaces
  
**/
-struct dmcu_version {
-   unsigned int date;
-   unsigned int month;
-   unsigned int year;
-   unsigned int interface_version;
-};
-
 struct dc_versions {
const char *dc_ver;
struct dmcu_version dmcu_version;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
index 4550747fb61c..cb85eaa9857f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
@@ -32,6 +32,13 @@ enum dmcu_state {
DMCU_RUNNING = 1
 };
 
+struct dmcu_version {
+   unsigned int date;
+   unsigned int month;
+   unsigned int year;
+   unsigned int interface_version;
+};
+
 struct dmcu {
struct dc_context *ctx;
const struct dmcu_funcs *funcs;
diff --git a/drivers/gpu/drm/amd/display/modules/power/Makefile 
b/drivers/gpu/drm/amd/display/modules/power/Makefile
new file mode 100644
index ..87851f892a52
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/modules/power/Makefile
@@ -0,0 +1,31 @@
+#
+# Copyright 2017 Advanced Micro Devices, Inc.

[PATCH] drm/amdgpu: Fix Kernel Oops triggered by kfdtest

[Joerg Roedel]

From: Joerg Roedel 

Running kfdtest on Kaveri triggers a kernel NULL-ptr dereference:

BUG: unable to handle kernel NULL pointer dereference at 

PGD 42c017067 P4D 42c017067 PUD 40f071067 PMD 0
Oops: 0010 [#1] SMP NOPTI
CPU: 0 PID: 13107 Comm: kfdtest Not tainted 4.20.0-rc2+ #11
Hardware name: Gigabyte Technology Co., Ltd. To be filled by 
O.E.M./F2A88XM-HD3, BIOS F6 05/28/2014
RIP: 0010:  (null)
Code: Bad RIP value.
RSP: 0018:c90001adbbf0 EFLAGS: 00010202
RAX: a0806240 RBX: 88842a0fbc00 RCX: 0002
RDX: 0001 RSI: 0004 RDI: 88842969
RBP: c90001adbbf8 R08: 2000 R09: 88842e542ec0
R10: 7feff778f008 R11: 7feff778f010 R12: 
R13: 88840f063a20 R14: 88842a0fbd20 R15: 0f43ff60
FS:  7feff7769740() GS:88842fa0() 
knlGS:
CS:  0010 DS:  ES:  CR0: 80050033
CR2: ffd6 CR3: 00040f122000 CR4: 000406f0
Call Trace:
 ? amdgpu_amdkfd_set_compute_idle+0x29/0x30 [amdgpu]
 register_process+0x140/0x150 [amdgpu]
 pqm_create_queue+0x395/0x560 [amdgpu]
 kfd_ioctl_create_queue+0x285/0x680 [amdgpu]
 kfd_ioctl+0x27f/0x450 [amdgpu]
 ? kfd_ioctl_destroy_queue+0x80/0x80 [amdgpu]
 do_vfs_ioctl+0x96/0x6a0
 ? __audit_syscall_entry+0xdd/0x130
 ? handle_mm_fault+0x11b/0x240
 ksys_ioctl+0x67/0x90
 __x64_sys_ioctl+0x1a/0x20
 do_syscall_64+0x61/0x190
 entry_SYSCALL_64_after_hwframe+0x44/0xa9

The reason is that the pp_funcs->switch_power_profile
function pointer is not set for a Kaveri ASIC and thus the
kernel calls a NULL pointer.

Add a check before calling the function to avoid that.

Signed-off-by: Joerg Roedel 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index f972cd156795..0ecedd30f2aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -337,8 +337,9 @@ enum amdgpu_pcie_gen {
(adev)->powerplay.pp_handle, request))
 
 #define amdgpu_dpm_switch_power_profile(adev, type, en) \
-   ((adev)->powerplay.pp_funcs->switch_power_profile(\
-   (adev)->powerplay.pp_handle, type, en))
+   if ((adev)->powerplay.pp_funcs->switch_power_profile != NULL) \
+   ((adev)->powerplay.pp_funcs->switch_power_profile(\
+   (adev)->powerplay.pp_handle, type, en))
 
 #define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
-- 
2.13.7

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[PATCH] drm/amd/powerplay: Ratelimit all "was not implemented" messages

[Joerg Roedel]

From: Joerg Roedel 

Running kfdtest on an AMD Carizzo flooded the kernel log
with thousands of these "was not implemented" messages,
making it impossible to see other messages there.

Ratelimit the messages to prevent user-space from flooding
the kernel log.

Signed-off-by: Joerg Roedel 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 52 +--
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index d6aa1d414320..b68c2e0fef01 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -300,7 +300,7 @@ static int pp_set_clockgating_by_smu(void *handle, uint32_t 
msg_id)
return -EINVAL;
 
if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return 0;
}
 
@@ -387,7 +387,7 @@ static uint32_t pp_dpm_get_sclk(void *handle, bool low)
return 0;
 
if (hwmgr->hwmgr_func->get_sclk == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return 0;
}
mutex_lock(&hwmgr->smu_lock);
@@ -405,7 +405,7 @@ static uint32_t pp_dpm_get_mclk(void *handle, bool low)
return 0;
 
if (hwmgr->hwmgr_func->get_mclk == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return 0;
}
mutex_lock(&hwmgr->smu_lock);
@@ -422,7 +422,7 @@ static void pp_dpm_powergate_vce(void *handle, bool gate)
return;
 
if (hwmgr->hwmgr_func->powergate_vce == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return;
}
mutex_lock(&hwmgr->smu_lock);
@@ -438,7 +438,7 @@ static void pp_dpm_powergate_uvd(void *handle, bool gate)
return;
 
if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return;
}
mutex_lock(&hwmgr->smu_lock);
@@ -505,7 +505,7 @@ static void pp_dpm_set_fan_control_mode(void *handle, 
uint32_t mode)
return;
 
if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return;
}
mutex_lock(&hwmgr->smu_lock);
@@ -522,7 +522,7 @@ static uint32_t pp_dpm_get_fan_control_mode(void *handle)
return 0;
 
if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return 0;
}
mutex_lock(&hwmgr->smu_lock);
@@ -540,7 +540,7 @@ static int pp_dpm_set_fan_speed_percent(void *handle, 
uint32_t percent)
return -EINVAL;
 
if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return 0;
}
mutex_lock(&hwmgr->smu_lock);
@@ -558,7 +558,7 @@ static int pp_dpm_get_fan_speed_percent(void *handle, 
uint32_t *speed)
return -EINVAL;
 
if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return 0;
}
 
@@ -594,7 +594,7 @@ static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t 
rpm)
return -EINVAL;
 
if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return 0;
}
mutex_lock(&hwmgr->smu_lock);
@@ -720,7 +720,7 @@ static int pp_dpm_force_clock_level(void *handle,
return -EINVAL;
 
if (hwmgr->hwmgr_func->force_clock_level == NULL) {
-   pr_info("%s was not implemented.\n", __func__);
+   pr_info_ratelimited("%s was not implemented.\n", __func__);
return 0;
}
 
@@ -745,7 +745,7 @@ static int pp_dpm_print_clock_levels(void *handle,
return -EINVAL;
 
if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
-   pr_info("%s

RE: [PATCH -next] drm/amdgpu: remove set but not used variable 'ring'

[Huang, Ray]

> -Original Message-
> From: YueHaibing [mailto:yuehaib...@huawei.com]
> Sent: Thursday, November 15, 2018 6:52 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; airl...@linux.ie; Liu, Shaoyun
> ; Francis, David ; Huang,
> Ray ; Xu, Feifei ; Gao, Likun
> 
> Cc: YueHaibing ; amd-gfx@lists.freedesktop.org;
> dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; kernel-
> janit...@vger.kernel.org
> Subject: [PATCH -next] drm/amdgpu: remove set but not used variable 'ring'
> 
> Fixes gcc '-Wunused-but-set-variable' warning:
> 
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c: In function
> 'psp_v10_0_ring_stop':
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c:230:19: warning:
>  variable 'ring' set but not used [-Wunused-but-set-variable]
> 
> It not used since commit
> 4ef72453311a ("drm/amdgpu: added api for stopping psp ring (v2)")

Thanks, please also remove the similar code in psp_v3_1. 
With that updates, patch is Reviewed-by: Huang Rui 

> 
> Signed-off-by: YueHaibing 
> ---
>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 295c220..d78b430 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -240,12 +240,9 @@ static int psp_v10_0_ring_stop(struct psp_context
> *psp,
>  enum psp_ring_type ring_type)  {
>   int ret = 0;
> - struct psp_ring *ring;
>   unsigned int psp_ring_reg = 0;
>   struct amdgpu_device *adev = psp->adev;
> 
> - ring = &psp->km_ring;
> -
>   /* Write the ring destroy command to C2PMSG_64 */
>   psp_ring_reg = 3 << 16;
>   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
> 
> 
> 
> 

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