[PATCH] drm/amdgpu: add thick tile mode settings for Oland of gfx6

[Tao Zhou]

Adding thick tile mode for Oland to prevent UMD from getting mode value 0

Change-Id: Ic73265c89e075361452830d673dfd8af9c18ab53
Signed-off-by: Tao Zhou 
Tested-by: Hui.Deng 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 305276c7e4bf..c0cb244f58cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -782,6 +782,25 @@ static void gfx_v6_0_tiling_mode_table_init(struct 
amdgpu_device *adev)
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
+   tilemode[18] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+   ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+   PIPE_CONFIG(ADDR_SURF_P4_8x16);
+   tilemode[19] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+   ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
+   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+   NUM_BANKS(ADDR_SURF_16_BANK) |
+   TILE_SPLIT(split_equal_to_row_size);
+   tilemode[20] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+   ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+   NUM_BANKS(ADDR_SURF_16_BANK) |
+   TILE_SPLIT(split_equal_to_row_size);
tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-- 
2.17.1

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RE: [PATCH xf86-video-amdgpu] Fix hang when entering into dpms-off mode

[Liu, Aaron]

@Michel Dänzer,

I have reviewed your patch and verified it passed.

I couldn't merge this merge request to your master manually.
The log is below:
aaliu@lnx-aaliu:~/work/brahma/xf86-video-amdgpu-gitlab$ git push origin master
Username for 'https://gitlab.freedesktop.org': aaliu
Password for 'https://aa...@gitlab.freedesktop.org': 
remote: HTTP Basic: Access denied
remote: You must use a personal access token with 'api' scope for Git over HTTP.
remote: You can generate one at 
https://gitlab.freedesktop.org/profile/personal_access_tokens
fatal: Authentication failed for 
'https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu.git/'

BR,
Aaron Liu

> -Original Message-
> From: Michel Dänzer 
> Sent: Friday, March 01, 2019 12:36 AM
> To: Liu, Aaron 
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH xf86-video-amdgpu] Fix hang when entering into dpms-
> off mode
> 
> On 2019-02-28 1:05 p.m., Michel Dänzer wrote:
> > On 2019-02-28 3:52 a.m., Aaron Liu wrote:
> >>
> >> @@ -900,7 +900,12 @@ CARD32
> amdgpu_dri2_deferred_event(OsTimerPtr timer, CARD32 now, pointer data)
> >>delta_seq = delta_t * drmmode_crtc->dpms_last_fps;
> >>delta_seq /= 100;
> >>frame = (CARD64) drmmode_crtc->dpms_last_seq + delta_seq;
> >> -  if (event_info->drm_queue_seq)
> >> +  /*
> >> +   * If CRTC is in DPMS off state, it can't use vblank_handler.
> >> +   * Because drmmode_wait_vblank is not excuted in such as
> >> +   * amdgpu_dri2_schedule_swap/amdgpu_dri2_schedule_wait_msc.
> >> +   */
> >> +  if (event_info->drm_queue_seq && amdgpu_crtc_is_enabled(crtc))
> >>drmmode_crtc->drmmode->event_context.
> >>vblank_handler(pAMDGPUEnt->fd, frame, drm_now /
> 100,
> >>   drm_now % 100,
> >>
> >
> > This isn't a good solution I'm afraid, as it'll leave the struct
> > amdgpu_drm_queue_entry memory associated with
> > event_info->drm_queue_seq linked into the amdgpu_drm_queue list,
> which
> > would gradually slow down processing of that list.
> >
> >
> > I think I know what the issue is, I'll work on a fix in the afternoon.
> 
> Please test
> https://gitlab.freedesktop.org/xorg/driver/xf86-video-
> amdgpu/merge_requests/29
> .
> 
> 
> --
> Earthling Michel Dänzer   |  https://www.amd.com
> Libre software enthusiast | Mesa and X developer
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[PATCH] drm/amd/powerplay: fix semicolon code style issue

[Yang Wei]

From: Yang Wei 

Delete superfluous semicolons.

Signed-off-by: Yang Wei 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 8 
 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 9bc27f4..b12c828 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1304,7 +1304,7 @@ static int pp_notify_smu_enable_pwe(void *handle)
 
if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) {
pr_info_ratelimited("%s was not implemented.\n", __func__);
-   return -EINVAL;;
+   return -EINVAL;
}
 
mutex_lock(>smu_lock);
@@ -1341,7 +1341,7 @@ static int pp_set_min_deep_sleep_dcefclk(void *handle, 
uint32_t clock)
 
if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) {
pr_debug("%s was not implemented.\n", __func__);
-   return -EINVAL;;
+   return -EINVAL;
}
 
mutex_lock(>smu_lock);
@@ -1360,7 +1360,7 @@ static int pp_set_hard_min_dcefclk_by_freq(void *handle, 
uint32_t clock)
 
if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) {
pr_debug("%s was not implemented.\n", __func__);
-   return -EINVAL;;
+   return -EINVAL;
}
 
mutex_lock(>smu_lock);
@@ -1379,7 +1379,7 @@ static int pp_set_hard_min_fclk_by_freq(void *handle, 
uint32_t clock)
 
if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) {
pr_debug("%s was not implemented.\n", __func__);
-   return -EINVAL;;
+   return -EINVAL;
}
 
mutex_lock(>smu_lock);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 1f92a9f..ffa7d46 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -76,7 +76,7 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 {
struct amdgpu_device *adev = NULL;
-   int ret = -EINVAL;;
+   int ret = -EINVAL;
PHM_FUNC_CHECK(hwmgr);
adev = hwmgr->adev;
 
-- 
2.7.4


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amd-staging-drm-next - [drm] REG_WAIT timeout 1us * 80000 tries - dce_abm_set_pipe line:62

[Przemek Socha]

Hi all,

today I've spotted a warning during hibernation (S4) process while the machine 
was attempting to disable all HW and write hibernation image to disk just 
before "amdgpu :00:01.0: GPU pci config reset" and disabling EC interrupt.

Besides that everything works just fine. System hibernates and resumes 
correctly, so I have no idea if I should worry or not.

System is Lenovo G50-45 with a6-6310 APU and r4 Mullins.

>[14469.490249] [drm] REG_WAIT timeout 1us * 8 tries - dce_abm_set_pipe 
line:62
>[14469.490427] WARNING: CPU: 3 PID: 32028 at drivers/gpu/drm/amd/amdgpu/../
display/dc/dc_helper.c:277 generic_reg_wait.cold.3+0x2a/0x31 [amdgpu]
>[14469.490429] Modules linked in: rfcomm nf_tables ebtable_nat ip_set 
nfnetlink ebtable_filter ebtables ip6table_filter ip6_tables overlay squashfs 
loop bnep ipv6 ath3k >btusb btintel bluetooth ecdh_generic rtsx_usb_ms 
memstick rtsx_usb_sdmmc uvcvideo videobuf2_vmalloc videobuf2_memops 
videobuf2_v4l2 rtsx_usb videobuf2_common videodev media >ath9k kvm_amd 
ath9k_common ath9k_hw kvm irqbypass sdhci_pci cqhci sdhci crc32_pclmul 
ghash_clmulni_intel serio_raw mmc_core mac80211 amdgpu ath xhci_pci xhci_hcd 
cfg80211 >mfd_core chash gpu_sched ehci_pci ttm ehci_hcd sp5100_tco
>[14469.490488] CPU: 3 PID: 32028 Comm: kworker/u8:13 Not tainted 5.0.0-rc1+ 
#71
>[14469.490490] Hardware name: LENOVO 80E3/Lancer 5B2, BIOS A2CN45WW(V2.13) 
08/04/2016
>[14469.490499] Workqueue: events_unbound async_run_entry_fn
>[14469.490590] RIP: 0010:generic_reg_wait.cold.3+0x2a/0x31 [amdgpu]
>[14469.490595] Code: 44 8b 44 24 68 48 c7 c7 30 2f 43 c0 48 8b 4c 24 60 8b 54 
24 58 8b 74 24 04 e8 16 ed 37 ef 41 83 7c 24 20 01 0f 84 d6 a3 fe ff <0f> 0b e9 
cf a3 fe ff e8 4d c1 eb ff 48 c7 c7 00 a0 4b c0 e8 a1 77
>[14469.490598] RSP: 0018:9759425ff6e0 EFLAGS: 00010297
>[14469.490602] RAX: 0043 RBX: 00013881 RCX: 

>[14469.490605] RDX:  RSI: 0096 RDI: 
>
>[14469.490608] RBP: 1620 R08: 0004 R09: 
0001bb40
>[14469.490611] R10: 02e453506252 R11: 0043 R12: 
8d2552416100
>[14469.490613] R13:  R14: 0001 R15: 
0001
>[14469.490617] FS:  () GS:8d2557b8() knlGS:

>[14469.490620] CS:  0010 DS:  ES:  CR0: 80050033
>[14469.490623] CR2: 7efbb0564038 CR3: 000212b5e000 CR4: 
000406e0
>[14469.490625] Call Trace:
>[14469.490743]  dce_abm_set_pipe+0x47/0x2a8 [amdgpu]
>[14469.490855]  dce_abm_immediate_disable+0x15/0x208 [amdgpu]
>[14469.490949]  dc_link_set_abm_disable+0x31/0x40 [amdgpu]
>[14469.491045]  dce110_blank_stream+0x69/0x70 [amdgpu]
>[14469.491139]  core_link_disable_stream+0x3e/0x238 [amdgpu]
>[14469.491236]  dce110_reset_hw_ctx_wrap+0xbe/0x1e0 [amdgpu]
>[14469.491333]  dce110_apply_ctx_to_hw+0x46/0x768 [amdgpu]
>[14469.491428]  ? amdgpu_pm_compute_clocks.part.11+0x265/0x4d8 [amdgpu]
>[14469.491539]  ? dm_pp_apply_display_requirements+0x1dd/0x1f8 [amdgpu]
>[14469.491633]  dc_commit_state+0x35e/0x9f0 [amdgpu]
>[14469.491731]  ? dce110_timing_generator_get_position+0x71/0x160 [amdgpu]
>[14469.491842]  amdgpu_dm_atomic_commit_tail+0x4b4/0x1cf0 [amdgpu]
>[14469.491941]  ? dce110_timing_generator_get_crtc_scanoutpos+0x75/0x130 
[amdgpu]
>[14469.492031]  ? dc_stream_get_scanoutpos+0x70/0x90 [amdgpu]
>[14469.492140]  ? dm_crtc_get_scanoutpos+0x61/0xb0 [amdgpu]
>[14469.492234]  ? amdgpu_display_get_crtc_scanoutpos+0x80/0x168 [amdgpu]
>[14469.492330]  ? dce110_timing_generator_get_vblank_counter+0x26/0xa0 
[amdgpu]
>[14469.492340]  ? _raw_spin_unlock_irqrestore+0xf/0x28
>[14469.492346]  ? __wake_up_common_lock+0x84/0xb8
>[14469.492456]  ? amdgpu_dm_atomic_commit_tail+0x1cf0/0x1cf0 [amdgpu]
>[14469.492462]  ? preempt_count_add+0x74/0xa0
>[14469.492467]  ? _raw_spin_lock_irq+0xf/0x30
>[14469.492471]  ? _raw_spin_unlock_irq+0xe/0x20
>[14469.492478]  ? wait_for_completion_timeout+0x101/0x128
>[14469.492486]  ? drm_atomic_helper_setup_commit+0x4a7/0x660
>[14469.492493]  ? drm_atomic_helper_commit+0x107/0x418
>[14469.492499]  drm_atomic_helper_commit+0x107/0x418
>[14469.492507]  __drm_atomic_helper_disable_all.constprop.30+0x141/0x150
>[14469.492514]  drm_atomic_helper_suspend+0xe5/0x118
>[14469.492625]  dm_suspend+0x20/0xb8 [amdgpu]
>[14469.492716]  amdgpu_device_ip_suspend_phase1+0x94/0xc0 [amdgpu]
>[14469.492808]  amdgpu_device_suspend+0x2e8/0x490 [amdgpu]
>[14469.492817]  pci_pm_freeze+0x4c/0xc8
>[14469.492823]  ? pci_pm_poweroff+0xd0/0xd0
>[14469.492829]  dpm_run_callback+0x2a/0x120
>[14469.492837]  __device_suspend+0x200/0x7e8
>[14469.492844]  async_suspend+0x15/0x88
>[14469.492849]  async_run_entry_fn+0x32/0xd8
>[14469.492856]  process_one_work+0x1f4/0x428
>[14469.492863]  worker_thread+0x43/0x490
>[14469.492869]  ? process_one_work+0x428/0x428
>[14469.492873]  kthread+0x15d/0x180
>[14469.492878]  ? kthread_create_on_node+0x60/0x60
>[14469.492884]  

[PATCH xf86-video-amdgpu] Allow changing DCC parameters between flips

[Marek Olšák]

From: Marek Olšák 

---
 src/amdgpu_present.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/amdgpu_present.c b/src/amdgpu_present.c
index ce88bd8f..f4fc6ebd 100644
--- a/src/amdgpu_present.c
+++ b/src/amdgpu_present.c
@@ -271,26 +271,34 @@ amdgpu_present_check_flip(RRCrtcPtr crtc, WindowPtr 
window, PixmapPtr pixmap,
return FALSE;
 
if (info->drmmode.dri2_flipping)
return FALSE;
 
 #if XORG_VERSION_CURRENT <= XORG_VERSION_NUMERIC(1, 20, 99, 1, 0)
if (pixmap->devKind != screen_pixmap->devKind)
return FALSE;
 #endif
 
+   uint64_t tiling_info1 = amdgpu_pixmap_get_tiling_info(pixmap);
+   uint64_t tiling_info2 = amdgpu_pixmap_get_tiling_info(screen_pixmap);
+
/* The kernel driver doesn't handle flipping between BOs with different
-* tiling parameters correctly yet
+* tiling parameters correctly yet except DCC.
 */
-   if (amdgpu_pixmap_get_tiling_info(pixmap) !=
-   amdgpu_pixmap_get_tiling_info(screen_pixmap))
-   return FALSE;
+   if (info->family >= AMDGPU_FAMILY_AI) {
+   if (AMDGPU_TILING_GET(tiling_info1, SWIZZLE_MODE) !=
+   AMDGPU_TILING_GET(tiling_info2, SWIZZLE_MODE))
+   return FALSE;
+   } else {
+   if (tiling_info1 != tiling_info2)
+   return FALSE;
+   }
 
for (i = 0, num_crtcs_on = 0; i < config->num_crtc; i++) {
if (drmmode_crtc_can_flip(config->crtc[i]))
num_crtcs_on++;
else if (config->crtc[i] == crtc->devPrivate)
return FALSE;
}
 
if (num_crtcs_on == 0)
return FALSE;
-- 
2.17.1

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Re: [PATCH] drm/amdgpu: Bump amdgpu version for per-flip plane tiling updates

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Thu, Feb 28, 2019 at 9:59 AM Nicholas Kazlauskas <
nicholas.kazlaus...@amd.com> wrote:

> To help xf86-video-amdgpu and mesa know DC supports updating the
> tiling attributes for a framebuffer per-flip.
>
> Cc: Michel Dänzer 
> Cc: Marek Olšák 
> Signed-off-by: Nicholas Kazlauskas 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 223013ef8466..ae4e3eeb4ae2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -74,9 +74,10 @@
>   * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
>   * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
>   * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
> + * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
>   */
>  #define KMS_DRIVER_MAJOR   3
> -#define KMS_DRIVER_MINOR   30
> +#define KMS_DRIVER_MINOR   31
>  #define KMS_DRIVER_PATCHLEVEL  0
>
>  int amdgpu_vram_limit = 0;
> --
> 2.17.1
>
>
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[PATCH 00/16] DC Patches Feb 28, 2019

[sunpeng.li]

From: Leo Li 

Summary of change:
* Fix cursor-pageflip interactions on DCN1
* Expose plane alpha-blending support

Aric Cyr (1):
  drm/amd/display: 3.2.21

Charlene Liu (1):
  drm/amd/display: add HW i2c arbitration with dmcu

David Francis (1):
  drm/amd/display: On DCN1, Wait for vupdate on cursor updates

Dmytro Laktyushkin (1):
  drm/amd/display: clean up dml_init_instance

Eric Bernstein (2):
  drm/amd/display: Free DCN version of stream encoder
  drm/amd/display: Rename is_hdmi to is_hdmi_tmds type

Josip Pavic (1):
  drm/amd/display: reduce abm min reduction, deviation gain and contrast
factor

Jun Lei (2):
  drm/amd/display: implement bounding box update based on uclk breakdown
  drm/amd/display: fix up reference clock abstractions

Ken Chalmers (1):
  drm/amd/display: Increase DP blank timeout from 30 ms to 50 ms

Nicholas Kazlauskas (1):
  drm/amd/display: Expose support for alpha blending on overlays

SivapiriyanKumarasamy (1):
  drm/amd/display: Add PSR SMU Interrupt support

Wenjing Liu (2):
  drm/amd/display: add pipe lock during stream update
  drm/amd/display: add i2c over aux failure handling

Yongqiang Sun (2):
  drm/amd/display: Refactor reg_set and reg_update.
  drm/amd/display: Combine field toggle macro and sequence write macro.

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 52 +++
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  2 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 26 +-
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c| 31 
 drivers/gpu/drm/amd/display/dc/dc.h|  2 +-
 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h  |  2 +
 drivers/gpu/drm/amd/display/dc/dc_helper.c | 52 +++
 drivers/gpu/drm/amd/display/dc/dc_types.h  |  3 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c   | 24 +
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c  |  7 ++-
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h  | 22 
 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c| 12 -
 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h|  8 ++-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 17 ---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c|  5 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  8 +--
 .../display/dc/dcn10/dcn10_hw_sequencer_debug.c|  4 +-
 .../drm/amd/display/dc/dcn10/dcn10_link_encoder.c  |  2 -
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  | 10 +---
 .../amd/display/dc/dcn10/dcn10_stream_encoder.c|  4 +-
 drivers/gpu/drm/amd/display/dc/dm_services.h   |  9 ++--
 .../gpu/drm/amd/display/dc/dml/display_mode_lib.c  | 58 ++
 .../gpu/drm/amd/display/dc/dml/display_mode_lib.h  |  4 +-
 .../drm/amd/display/dc/dml/display_mode_structs.h  |  5 +-
 .../amd/display/dc/dml/display_rq_dlg_helpers.c|  3 ++
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|  7 ++-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h   |  3 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h   |  4 ++
 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h| 12 ++---
 drivers/gpu/drm/amd/display/include/signal_types.h |  5 ++
 .../drm/amd/display/modules/power/power_helpers.c  | 15 +++---
 33 files changed, 274 insertions(+), 148 deletions(-)

-- 
2.7.4

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[PATCH 08/16] drm/amd/display: Rename is_hdmi to is_hdmi_tmds type

[sunpeng.li]

From: Eric Bernstein 

HDMI has TMDS and FRL signal types. Be specific about what is used.

Signed-off-by: Eric Bernstein 
Reviewed-by: Nevenko Stupar 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  2 +-
 .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c   | 15 ---
 drivers/gpu/drm/amd/display/include/signal_types.h|  5 +
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 05f5fdf..30bfc0a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2579,7 +2579,7 @@ void core_link_enable_stream(
>timing,
stream->output_color_space);
 
-   if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
+   if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
pipe_ctx->stream_res.stream_enc,
>timing,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 21a6218..ae424c7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -616,7 +616,7 @@ dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 
 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 {
-   bool is_hdmi;
+   bool is_hdmi_tmds;
bool is_dp;
 
ASSERT(pipe_ctx->stream);
@@ -624,13 +624,13 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
if (pipe_ctx->stream_res.stream_enc == NULL)
return;  /* this is not root pipe */
 
-   is_hdmi = dc_is_hdmi_signal(pipe_ctx->stream->signal);
+   is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 
-   if (!is_hdmi && !is_dp)
+   if (!is_hdmi_tmds && !is_dp)
return;
 
-   if (is_hdmi)
+   if (is_hdmi_tmds)

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
pipe_ctx->stream_res.stream_enc,
_ctx->stream_res.encoder_info_frame);
@@ -974,8 +974,9 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
set_pme_wa_enable_by_version(core_dc);
/* un-mute audio */
/* TODO: audio should be per stream rather than per link */
-   pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
-   pipe_ctx->stream_res.stream_enc, false);
+   if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+   
pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
+   pipe_ctx->stream_res.stream_enc, false);
}
 }
 
@@ -1026,7 +1027,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int 
option)
struct dc_link *link = stream->link;
struct dc *dc = pipe_ctx->stream->ctx->dc;
 
-   if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
+   if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
pipe_ctx->stream_res.stream_enc);
 
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h 
b/drivers/gpu/drm/amd/display/include/signal_types.h
index f56d289..beed701 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -45,6 +45,11 @@ enum signal_type {
 };
 
 /* help functions for signal types manipulation */
+static inline bool dc_is_hdmi_tmds_signal(enum signal_type signal)
+{
+   return (signal == SIGNAL_TYPE_HDMI_TYPE_A);
+}
+
 static inline bool dc_is_hdmi_signal(enum signal_type signal)
 {
return (signal == SIGNAL_TYPE_HDMI_TYPE_A);
-- 
2.7.4

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[PATCH 13/16] drm/amd/display: Expose support for alpha blending on overlays

[sunpeng.li]

From: Nicholas Kazlauskas 

[Why]
The DRM overlay planes DM exposes support RGBA formats but are currently
forced as fully opaque over whatever they overlay.

[How]
Expose DRM blending mode and alpha properties to userspace.

The overlays exposed support per-pixel pre-multiplied alpha along with
global plane opacity.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Harry Wentland 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 52 +++
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bdbc800..cf66d48 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2627,6 +2627,42 @@ static int fill_plane_attributes_from_fb(struct 
amdgpu_device *adev,
 
 }
 
+static void
+fill_blending_from_plane_state(struct drm_plane_state *plane_state,
+  const struct dc_plane_state *dc_plane_state,
+  bool *per_pixel_alpha, bool *global_alpha,
+  int *global_alpha_value)
+{
+   *per_pixel_alpha = false;
+   *global_alpha = false;
+   *global_alpha_value = 0xff;
+
+   if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
+   return;
+
+   if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
+   static const uint32_t alpha_formats[] = {
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_RGBA,
+   DRM_FORMAT_ABGR,
+   };
+   uint32_t format = plane_state->fb->format->format;
+   unsigned int i;
+
+   for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
+   if (format == alpha_formats[i]) {
+   *per_pixel_alpha = true;
+   break;
+   }
+   }
+   }
+
+   if (plane_state->alpha < 0x) {
+   *global_alpha = true;
+   *global_alpha_value = plane_state->alpha >> 8;
+   }
+}
+
 static int fill_plane_attributes(struct amdgpu_device *adev,
 struct dc_plane_state *dc_plane_state,
 struct drm_plane_state *plane_state,
@@ -2658,6 +2694,11 @@ static int fill_plane_attributes(struct amdgpu_device 
*adev,
dc_plane_state->in_transfer_func = NULL;
}
 
+   fill_blending_from_plane_state(plane_state, dc_plane_state,
+  _plane_state->per_pixel_alpha,
+  _plane_state->global_alpha,
+  _plane_state->global_alpha_value);
+
return ret;
 }
 
@@ -3987,6 +4028,15 @@ static int amdgpu_dm_plane_init(struct 
amdgpu_display_manager *dm,
break;
}
 
+   /* TODO: Check DC plane caps explicitly here for adding propertes */
+   if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
+   unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+ BIT(DRM_MODE_BLEND_PREMULTI);
+
+   drm_plane_create_alpha_property(plane);
+   drm_plane_create_blend_mode_property(plane, blend_caps);
+   }
+
drm_plane_helper_add(plane, _plane_helper_funcs);
 
/* Create (reset) the plane state */
@@ -4851,6 +4901,8 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
bundle->plane_infos[planes_count].stereo_format = 
dc_plane->stereo_format;
bundle->plane_infos[planes_count].tiling_info = 
dc_plane->tiling_info;
bundle->plane_infos[planes_count].visible = dc_plane->visible;
+   bundle->plane_infos[planes_count].global_alpha = 
dc_plane->global_alpha;
+   bundle->plane_infos[planes_count].global_alpha_value = 
dc_plane->global_alpha_value;
bundle->plane_infos[planes_count].per_pixel_alpha = 
dc_plane->per_pixel_alpha;
bundle->plane_infos[planes_count].dcc = dc_plane->dcc;
bundle->surface_updates[planes_count].plane_info = 
>plane_infos[planes_count];
-- 
2.7.4

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[PATCH 05/16] drm/amd/display: Combine field toggle macro and sequence write macro.

[sunpeng.li]

From: Yongqiang Sun 

[Why]
field toggle write is actual field sequence write with the same
field name.

[How]
Use REG_UPDATE_SEQ_2 for both sequence write and toggle.
Rename REG_UPDATE_1by1_3 to REG_UPDATE_SEQ_3.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c   | 22 +++---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c|  5 +++--
 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h|  9 ++---
 3 files changed, 16 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 65b290d..c9b881d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -171,24 +171,24 @@ static void submit_channel_request(
 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
if (REG(AUXN_IMPCAL)) {
/* clear_aux_error */
-   REG_UPDATE_SEQ(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK,
-   1,
-   0);
+   REG_UPDATE_SEQ_2(AUXN_IMPCAL,
+   AUXN_CALOUT_ERROR_AK, 1,
+   AUXN_CALOUT_ERROR_AK, 0);
 
-   REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK,
-   1,
-   0);
+   REG_UPDATE_SEQ_2(AUXP_IMPCAL,
+   AUXP_CALOUT_ERROR_AK, 1,
+   AUXP_CALOUT_ERROR_AK, 0);
 
/* force_default_calibrate */
-   REG_UPDATE_1BY1_2(AUXN_IMPCAL,
+   REG_UPDATE_SEQ_2(AUXN_IMPCAL,
AUXN_IMPCAL_ENABLE, 1,
AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
 
/* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P 
toggles OVERRIDE? */
 
-   REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE,
-   1,
-   0);
+   REG_UPDATE_SEQ_2(AUXP_IMPCAL,
+   AUXP_IMPCAL_OVERRIDE_ENABLE, 1,
+   AUXP_IMPCAL_OVERRIDE_ENABLE, 0);
}
/* set the delay and the number of bytes to write */
 
@@ -267,7 +267,7 @@ static int read_channel_reply(struct dce_aux *engine, 
uint32_t size,
if (!bytes_replied)
return -1;
 
-   REG_UPDATE_1BY1_3(AUX_SW_DATA,
+   REG_UPDATE_SEQ_3(AUX_SW_DATA,
  AUX_SW_INDEX, 0,
  AUX_SW_AUTOINCREMENT_DISABLE, 1,
  AUX_SW_DATA_RW, 1);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index e161ad8..295cbd5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -258,8 +258,9 @@ void hubbub1_wm_change_req_wa(struct hubbub *hubbub)
 {
struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
 
-   REG_UPDATE_SEQ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
-   DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0, 1);
+   REG_UPDATE_SEQ_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+   DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0,
+   DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
 }
 
 void hubbub1_program_watermarks(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h 
b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
index 3768245..8503d9c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -379,16 +379,11 @@
 /* macro to update a register field to specified values in given sequences.
  * useful when toggling bits
  */
-#define REG_UPDATE_SEQ(reg, field, value1, value2) \
-{  uint32_t val = REG_UPDATE(reg, field, value1); \
-   REG_SET(reg, val, field, value2); }
-
-/* macro to update fields in register 1 field at a time in given order */
-#define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \
+#define REG_UPDATE_SEQ_2(reg, f1, v1, f2, v2) \
 {  uint32_t val = REG_UPDATE(reg, f1, v1); \
REG_SET(reg, val, f2, v2); }
 
-#define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \
+#define REG_UPDATE_SEQ_3(reg, f1, v1, f2, v2, f3, v3) \
 {  uint32_t val = REG_UPDATE(reg, f1, v1); \
val = REG_SET(reg, val, f2, v2); \
REG_SET(reg, val, f3, v3); }
-- 
2.7.4

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[PATCH 12/16] drm/amd/display: add HW i2c arbitration with dmcu

[sunpeng.li]

From: Charlene Liu 

Signed-off-by: Charlene Liu 
Reviewed-by: Wenjing Liu 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 12 +++-
 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h |  8 ++--
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 40f2d6e..cd26161 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -346,6 +346,16 @@ static void release_engine(
 
 }
 
+static bool is_engine_available(struct dce_i2c_hw *dce_i2c_hw)
+{
+   unsigned int arbitrate;
+
+   REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, );
+   if (arbitrate == DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY)
+   return false;
+   return true;
+}
+
 struct dce_i2c_hw *acquire_i2c_hw_engine(
struct resource_pool *pool,
struct ddc *ddc)
@@ -368,7 +378,7 @@ struct dce_i2c_hw *acquire_i2c_hw_engine(
if (!dce_i2c_hw)
return NULL;
 
-   if (pool->i2c_hw_buffer_in_use)
+   if (pool->i2c_hw_buffer_in_use || !is_engine_available(dce_i2c_hw))
return NULL;
 
do {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
index 7f19bb4..5755007 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
@@ -29,7 +29,8 @@
 enum dc_i2c_status {
DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
-   DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
+   DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW,
+   DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY = 2,
 };
 
 enum dc_i2c_arbitration {
@@ -129,7 +130,8 @@ enum {
I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\
I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
-   I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh)
+   I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\
+   I2C_SF(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, mask_sh)
 
 #define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
@@ -170,6 +172,7 @@ struct dce_i2c_shift {
uint8_t DC_I2C_INDEX;
uint8_t DC_I2C_INDEX_WRITE;
uint8_t XTAL_REF_DIV;
+   uint8_t DC_I2C_REG_RW_CNTL_STATUS;
 };
 
 struct dce_i2c_mask {
@@ -207,6 +210,7 @@ struct dce_i2c_mask {
uint32_t DC_I2C_INDEX;
uint32_t DC_I2C_INDEX_WRITE;
uint32_t XTAL_REF_DIV;
+   uint32_t DC_I2C_REG_RW_CNTL_STATUS;
 };
 
 struct dce_i2c_registers {
-- 
2.7.4

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[PATCH 10/16] drm/amd/display: 3.2.21

[sunpeng.li]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index e755e2f..9b50536 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.20"
+#define DC_VER "3.2.21"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.7.4

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[PATCH 16/16] drm/amd/display: On DCN1, Wait for vupdate on cursor updates

[sunpeng.li]

From: David Francis 

[Why]
Cursor updates must acquire the pipe control lock to
prevent vupdate from triggering in the middle of cursor
programming. On DCN1 the pipe control lock prevents
pageflips from occurring. This means that a cursor update
right before vupdate can delay a pending pageflip

[How]
If the time until the next vupdate is less than a
conservative estimate of the cursor programming time,
wait until the vupdate has passed before locking.

Signed-off-by: David Francis 
Reviewed-by: Harry Wentland 
Acked-by: Leo Li 
Acked-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 31 +
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 996298c..59ccab3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -29,6 +29,7 @@
 #include "resource.h"
 #include "ipp.h"
 #include "timing_generator.h"
+#include "dcn10/dcn10_hw_sequencer.h"
 
 #define DC_LOGGER dc->ctx->logger
 
@@ -196,6 +197,32 @@ struct dc_stream_status *dc_stream_get_status(
return dc_stream_get_status_from_state(dc->current_state, stream);
 }
 
+static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc 
*dc)
+{
+   unsigned int vupdate_line;
+   unsigned int lines_to_vupdate, us_to_vupdate, vpos, nvpos;
+   struct dc_stream_state *stream = pipe_ctx->stream;
+   unsigned int us_per_line;
+
+   if (stream->ctx->asic_id.chip_family == FAMILY_RV &&
+   
ASIC_REV_IS_RAVEN(stream->ctx->asic_id.hw_internal_rev)) {
+
+   vupdate_line = get_vupdate_offset_from_vsync(pipe_ctx);
+   dc_stream_get_crtc_position(dc, , 1, , );
+
+   if (vpos >= vupdate_line)
+   return;
+
+   us_per_line = stream->timing.h_total * 1 / 
stream->timing.pix_clk_100hz;
+   lines_to_vupdate = vupdate_line - vpos;
+   us_to_vupdate = lines_to_vupdate * us_per_line;
+
+   /* 70 us is a conservative estimate of cursor update time*/
+   if (us_to_vupdate < 70)
+   udelay(us_to_vupdate);
+   }
+}
+
 /**
  * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor 
surface address
  */
@@ -234,6 +261,8 @@ bool dc_stream_set_cursor_attributes(
 
if (!pipe_to_program) {
pipe_to_program = pipe_ctx;
+
+   delay_cursor_until_vupdate(pipe_ctx, core_dc);
core_dc->hwss.pipe_control_lock(core_dc, 
pipe_to_program, true);
}
 
@@ -283,6 +312,8 @@ bool dc_stream_set_cursor_position(
 
if (!pipe_to_program) {
pipe_to_program = pipe_ctx;
+
+   delay_cursor_until_vupdate(pipe_ctx, core_dc);
core_dc->hwss.pipe_control_lock(core_dc, 
pipe_to_program, true);
}
 
-- 
2.7.4

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[PATCH 06/16] drm/amd/display: Increase DP blank timeout from 30 ms to 50 ms

[sunpeng.li]

From: Ken Chalmers 

[Why]
At 24 Hz, a frame is 41.7 ms, so a 30 ms wait can (and does often)
timeout.

[How]
Bump timeout from 30 ms to 50 ms.

Signed-off-by: Ken Chalmers 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index b082541..d370152 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -797,10 +797,10 @@ void enc1_stream_encoder_dp_blank(
 */
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
/* Larger delay to wait until VBLANK - use max retry of
-* 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
+* 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode +
 * a little more because we may not trust delay accuracy.
 */
-   max_retries = DP_BLANK_MAX_RETRY * 150;
+   max_retries = DP_BLANK_MAX_RETRY * 250;
 
/* disable DP stream */
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
-- 
2.7.4

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[PATCH 09/16] drm/amd/display: reduce abm min reduction, deviation gain and contrast factor

[sunpeng.li]

From: Josip Pavic 

[Why]
Increased power savings are desired for ABM 2.2.

[How]
Reduce the minimum reduction level, the deviation gain and the contrast factor
to allow for more aggressive operation of the algorithm.

Signed-off-by: Josip Pavic 
Reviewed-by: Anthony Koo 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 038b882..efd386f 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -41,9 +41,12 @@ static const unsigned char min_reduction_table[13] = {
 static const unsigned char max_reduction_table[13] = {
 0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32};
 
-/* ABM 2.2 Min Reduction effectively disabled (100% for all configs)*/
+/* Possible ABM 2.2 Min Reduction configs from least aggressive to most 
aggressive
+ *  01 2 3 4 5 6 7 8 9 1011   12
+ * 100  100   100   100   100   100   100   90.2  85.1  80.0  80.0  75.3  75.3 
%
+ */
 static const unsigned char min_reduction_table_v_2_2[13] = {
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe6, 0xd9, 0xcc, 0xcc, 0xc0, 0xc0};
 
 /* Possible ABM 2.2 Max Reduction configs from least aggressive to most 
aggressive
  *  01 2 3 4 5 6 7 8 9 1011   12
@@ -408,9 +411,9 @@ void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, 
struct dmcu_iram_parame
ram_table->flags = 0x0;
 
ram_table->deviation_gain[0] = 0xb3;
-   ram_table->deviation_gain[1] = 0xb3;
-   ram_table->deviation_gain[2] = 0xb3;
-   ram_table->deviation_gain[3] = 0xb3;
+   ram_table->deviation_gain[1] = 0xa8;
+   ram_table->deviation_gain[2] = 0x98;
+   ram_table->deviation_gain[3] = 0x68;
 
ram_table->min_reduction[0][0] = 
min_reduction_table_v_2_2[abm_config[set][0]];
ram_table->min_reduction[1][0] = 
min_reduction_table_v_2_2[abm_config[set][0]];
@@ -505,7 +508,7 @@ void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, 
struct dmcu_iram_parame
 
ram_table->contrastFactor[0] = 0x99;
ram_table->contrastFactor[1] = 0x99;
-   ram_table->contrastFactor[2] = 0x99;
+   ram_table->contrastFactor[2] = 0x90;
ram_table->contrastFactor[3] = 0x80;
 
ram_table->iir_curve[0] = 0x65;
-- 
2.7.4

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[PATCH 11/16] drm/amd/display: implement bounding box update based on uclk breakdown

[sunpeng.li]

From: Jun Lei 

[why]
Actual breakdown of DPM level varies by SKU (for the same family)
DC needs some ability to ammend pre-silicon numbers

Signed-off-by: Jun Lei 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index d1771e3..c5b791d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -25,6 +25,8 @@
 #ifndef __DISPLAY_MODE_STRUCTS_H__
 #define __DISPLAY_MODE_STRUCTS_H__
 
+#define MAX_CLOCK_LIMIT_STATES 8
+
 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
 typedef struct _vcs_dpi_ip_params_st ip_params_st;
@@ -103,7 +105,7 @@ struct _vcs_dpi_soc_bounding_box_st {
double xfc_xbuf_latency_tolerance_us;
int use_urgent_burst_bw;
unsigned int num_states;
-   struct _vcs_dpi_voltage_scaling_st clock_limits[8];
+   struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES];
 };
 
 struct _vcs_dpi_ip_params_st {
-- 
2.7.4

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[PATCH 14/16] drm/amd/display: fix up reference clock abstractions

[sunpeng.li]

From: Jun Lei 

[why]
"reference clock" is a very overloaded variable in DC and causes confusion
as there are multiple sources of reference clock, which may be different values
incorrect input values to DML will cause DCHUB to be programmed improperly
and lead to hard to debug underflow issues

[how]
instead of using ref clock everywhere, specify WHICH ref clock:
- xtalin
- dccg refclk
- dchub refclk

these are all distinct values which may not be equal

Signed-off-by: Jun Lei 
Reviewed-by: Yongqiang Sun 
Acked-by: David Francis 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 25 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  2 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  8 +++
 .../display/dc/dcn10/dcn10_hw_sequencer_debug.c|  4 ++--
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|  6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h   |  3 +++
 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h   |  4 
 8 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 8ee182b..0090f74 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -466,7 +466,7 @@ static void dcn_bw_calc_rq_dlg_ttu(
input.clks_cfg.dcfclk_mhz = v->dcfclk;
input.clks_cfg.dispclk_mhz = v->dispclk;
input.clks_cfg.dppclk_mhz = v->dppclk;
-   input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0;
+   input.clks_cfg.refclk_mhz = 
dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
input.clks_cfg.socclk_mhz = v->socclk;
input.clks_cfg.voltage = v->voltage_level;
 // dc->dml.logger = pool->base.logger;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 102..79e760a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -31,6 +31,8 @@
 #include "opp.h"
 #include "timing_generator.h"
 #include "transform.h"
+#include "dccg.h"
+#include "dchubbub.h"
 #include "dpp.h"
 #include "core_types.h"
 #include "set_mode_types.h"
@@ -163,7 +165,28 @@ struct resource_pool *dc_create_resource_pool(
 
if (dc->ctx->dc_bios->funcs->get_firmware_info(
dc->ctx->dc_bios, _info) == BP_RESULT_OK) {
-   res_pool->ref_clock_inKhz = 
fw_info.pll_info.crystal_frequency;
+   res_pool->ref_clocks.xtalin_clock_inKhz = 
fw_info.pll_info.crystal_frequency;
+
+   if 
(IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+   // On FPGA these dividers are currently 
not configured by GDB
+   
res_pool->ref_clocks.dccg_ref_clock_inKhz = 
res_pool->ref_clocks.xtalin_clock_inKhz;
+   
res_pool->ref_clocks.dchub_ref_clock_inKhz = 
res_pool->ref_clocks.xtalin_clock_inKhz;
+   } else if (res_pool->dccg && res_pool->hubbub) {
+   // If DCCG reference frequency cannot 
be determined (usually means not set to xtalin) then this is a critical error
+   // as this value must be known for 
DCHUB programming
+   
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+   
fw_info.pll_info.crystal_frequency,
+   
_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+   // Similarly, if DCHUB reference 
frequency cannot be determined, then it is also a critical error
+   
(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+   
res_pool->ref_clocks.dccg_ref_clock_inKhz,
+   
_pool->ref_clocks.dchub_ref_clock_inKhz);
+   } else {
+   // Not all ASICs have DCCG sw component
+   
res_pool->ref_clocks.dccg_ref_clock_inKhz = 
res_pool->ref_clocks.xtalin_clock_inKhz;
+   
res_pool->ref_clocks.dchub_ref_clock_inKhz = 
res_pool->ref_clocks.xtalin_clock_inKhz;
+   }
} else
ASSERT_CRITICAL(false);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index ae424c7..89f575f 100644
--- 

[PATCH 03/16] drm/amd/display: Refactor reg_set and reg_update.

[sunpeng.li]

From: Yongqiang Sun 

[Why]
Current reg update and reg set use same functions and
only delta is update reads reg value and call update function.

[How]
Refactor reg update and reg set functions.
1.Implement different functions for reg update and reg set.
2.Wrap same process to a help function, both reg update and
reg set will call it.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc_helper.c | 52 ++
 .../drm/amd/display/dc/dcn10/dcn10_link_encoder.c  |  2 -
 drivers/gpu/drm/amd/display/dc/dm_services.h   |  9 ++--
 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h|  3 +-
 4 files changed, 50 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c 
b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 597d383..f9259e4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -51,20 +51,16 @@ static inline void set_reg_field_value_masks(
field_value_mask->mask = field_value_mask->mask | mask;
 }
 
-uint32_t generic_reg_update_ex(const struct dc_context *ctx,
-   uint32_t addr, uint32_t reg_val, int n,
+static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask,
+   uint32_t addr, int n,
uint8_t shift1, uint32_t mask1, uint32_t field_value1,
-   ...)
+   va_list ap)
 {
-   struct dc_reg_value_masks field_value_mask = {0};
uint32_t shift, mask, field_value;
int i = 1;
 
-   va_list ap;
-   va_start(ap, field_value1);
-
/* gather all bits value/mask getting updated in this register */
-   set_reg_field_value_masks(_value_mask,
+   set_reg_field_value_masks(field_value_mask,
field_value1, mask1, shift1);
 
while (i < n) {
@@ -72,10 +68,48 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
mask = va_arg(ap, uint32_t);
field_value = va_arg(ap, uint32_t);
 
-   set_reg_field_value_masks(_value_mask,
+   set_reg_field_value_masks(field_value_mask,
field_value, mask, shift);
i++;
}
+}
+
+uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+   uint32_t addr, int n,
+   uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+   ...)
+{
+   struct dc_reg_value_masks field_value_mask = {0};
+   uint32_t reg_val;
+   va_list ap;
+
+   va_start(ap, field_value1);
+
+   set_reg_field_values(_value_mask, addr, n, shift1, mask1,
+   field_value1, ap);
+
+   va_end(ap);
+
+   /* mmio write directly */
+   reg_val = dm_read_reg(ctx, addr);
+   reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
+   dm_write_reg(ctx, addr, reg_val);
+   return reg_val;
+}
+
+uint32_t generic_reg_set_ex(const struct dc_context *ctx,
+   uint32_t addr, uint32_t reg_val, int n,
+   uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+   ...)
+{
+   struct dc_reg_value_masks field_value_mask = {0};
+   va_list ap;
+
+   va_start(ap, field_value1);
+
+   set_reg_field_values(_value_mask, addr, n, shift1, mask1,
+   field_value1, ap);
+
va_end(ap);
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index a9db372..0126a44 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -1304,7 +1304,6 @@ void dcn10_link_encoder_connect_dig_be_to_fe(
 #define HPD_REG_UPDATE_N(reg_name, n, ...) \
generic_reg_update_ex(CTX, \
HPD_REG(reg_name), \
-   HPD_REG_READ(reg_name), \
n, __VA_ARGS__)
 
 #define HPD_REG_UPDATE(reg_name, field, val)   \
@@ -1337,7 +1336,6 @@ void dcn10_link_encoder_disable_hpd(struct link_encoder 
*enc)
 #define AUX_REG_UPDATE_N(reg_name, n, ...) \
generic_reg_update_ex(CTX, \
AUX_REG(reg_name), \
-   AUX_REG_READ(reg_name), \
n, __VA_ARGS__)
 
 #define AUX_REG_UPDATE(reg_name, field, val)   \
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h 
b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 5683242..a62d53a 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -144,10 +144,14 @@ static inline uint32_t set_reg_field_value_ex(
reg_name ## __ ## reg_field ## _MASK,\
reg_name ## __ ## reg_field ## __SHIFT)
 
-uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+uint32_t 

[PATCH 01/16] drm/amd/display: clean up dml_init_instance

[sunpeng.li]

From: Dmytro Laktyushkin 

Get rid of DV style dml init in favour of the cleaner DC
style.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  2 +-
 .../gpu/drm/amd/display/dc/dml/display_mode_lib.c  | 58 ++
 .../gpu/drm/amd/display/dc/dml/display_mode_lib.h  |  4 +-
 .../drm/amd/display/dc/dml/display_mode_structs.h  |  1 +
 .../amd/display/dc/dml/display_rq_dlg_helpers.c|  3 ++
 5 files changed, 10 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 9f1a009..3d82fdd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1360,7 +1360,7 @@ static bool construct(
goto fail;
}
 
-   dml_init_instance(>dml, DML_PROJECT_RAVEN1);
+   dml_init_instance(>dml, _0_soc, _0_ip, 
DML_PROJECT_RAVEN1);
memcpy(dc->dcn_ip, _ip_defaults, sizeof(dcn10_ip_defaults));
memcpy(dc->dcn_soc, _soc_defaults, sizeof(dcn10_soc_defaults));
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index a2bd3a6..80ffd7d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -26,64 +26,14 @@
 #include "display_mode_lib.h"
 #include "dc_features.h"
 
-extern const struct _vcs_dpi_ip_params_st dcn1_0_ip;
-extern const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc;
-
-static void set_soc_bounding_box_v2(struct display_mode_lib *lib,
-   const struct _vcs_dpi_soc_bounding_box_st *soc_bb)
-{
-   lib->soc =  *soc_bb;
-}
-
-static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, 
enum dml_project project)
-{
-   switch (project) {
-   case DML_PROJECT_RAVEN1:
-   *soc = dcn1_0_soc;
-   break;
-   default:
-   ASSERT(0);
-   break;
-   }
-}
-
-static void set_ip_params_v2(struct display_mode_lib *lib,
-   const struct _vcs_dpi_ip_params_st *ip_params)
-{
-   lib->ip =  *ip_params;
-}
-
-static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project 
project)
-{
-   switch (project) {
-   case DML_PROJECT_RAVEN1:
-   *ip = dcn1_0_ip;
-   break;
-   default:
-   ASSERT(0);
-   break;
-   }
-}
-
-void dml_init_instance(struct display_mode_lib *lib, enum dml_project project)
-{
-   if (lib->project != project) {
-   set_soc_bounding_box(>soc, project);
-   set_ip_params(>ip, project);
-   lib->project = project;
-   }
-}
-
-void dml_init_instance_v2(struct display_mode_lib *lib,
+void dml_init_instance(struct display_mode_lib *lib,
const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
const struct _vcs_dpi_ip_params_st *ip_params,
enum dml_project project)
 {
-   if (lib->project != project) {
-   set_soc_bounding_box_v2(lib, soc_bb);
-   set_ip_params_v2(lib, ip_params);
-   lib->project = project;
-   }
+   lib->soc = *soc_bb;
+   lib->ip = *ip_params;
+   lib->project = project;
 }
 
 const char *dml_get_status_message(enum dm_validation_status status)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index 93c0197..1b546db 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -41,9 +41,7 @@ struct display_mode_lib {
struct dal_logger *logger;
 };
 
-void dml_init_instance(struct display_mode_lib *lib, enum dml_project project);
-
-void dml_init_instance_v2(struct display_mode_lib *lib,
+void dml_init_instance(struct display_mode_lib *lib,
const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
const struct _vcs_dpi_ip_params_st *ip_params,
enum dml_project project);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 391183e..d1771e3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -416,6 +416,7 @@ struct _vcs_dpi_display_dlg_regs_st {
unsigned int refcyc_per_vm_group_flip;
unsigned int refcyc_per_vm_req_vblank;
unsigned int refcyc_per_vm_req_flip;
+   unsigned int refcyc_per_vm_dmdata;
 };
 
 struct _vcs_dpi_display_ttu_regs_st {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
index 48400d6..e2d82aa 100644
--- 

[PATCH 07/16] drm/amd/display: add pipe lock during stream update

[sunpeng.li]

From: Wenjing Liu 

[why]
Stream update will adjust both info packets and stream params,
need to make sure all things are applied togather.

[how]
add pipe lock during stream update

Signed-off-by: Wenjing Liu 
Reviewed-by: Jun Lei 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b65551d..260a01e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1672,6 +1672,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
continue;
 
if (stream_update->dpms_off) {
+   dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
if (*stream_update->dpms_off) {
core_link_disable_stream(pipe_ctx, 
KEEP_ACQUIRED_RESOURCE);
dc->hwss.optimize_bandwidth(dc, 
dc->current_state);
@@ -1679,6 +1680,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
dc->hwss.prepare_bandwidth(dc, 
dc->current_state);

core_link_enable_stream(dc->current_state, pipe_ctx);
}
+   dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
}
 
if (stream_update->abm_level && 
pipe_ctx->stream_res.abm) {
-- 
2.7.4

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[PATCH 04/16] drm/amd/display: Add PSR SMU Interrupt support

[sunpeng.li]

From: SivapiriyanKumarasamy 

[WHY]
We have new bios capabilities enabling s0i2 entry on SMU interrupt. We want
this interrupt to be fired on PSR transitions such that we enter s0i2
when entering PSR active.

[HOW]
Add code to send the SMU interrupt with the appropriate
staticscreen flag when entering and exting PSR. Protect this
code with a config flag since it currently impacts BL PWM.

Signed-off-by: SivapiriyanKumarasamy 
Reviewed-by: Anthony Koo 
Acked-by: Leo Li 
Acked-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/dc/dc_types.h |  3 ++-
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c |  7 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 22 +++---
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index da2009a..00be40a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -550,9 +550,9 @@ struct psr_config {
unsigned char psr_version;
unsigned int psr_rfb_setup_time;
bool psr_exit_link_training_required;
-
bool psr_frame_capture_indication_req;
unsigned int psr_sdp_transmit_line_num_deadline;
+   bool allow_smu_optimizations;
 };
 
 union dmcu_psr_level {
@@ -654,6 +654,7 @@ struct psr_context {
 * continuing powerd own
 */
unsigned int frame_delay;
+   bool allow_smu_optimizations;
 };
 
 struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index c2926cf..aa58667 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -213,9 +213,6 @@ static bool dce_dmcu_setup_psr(struct dmcu *dmcu,
link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
psr_context->sdpTransmitLineNumDeadline);
 
-   if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
-   REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
-
/* waitDMCUReadyForCmd */
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
dmcu_wait_reg_ready_interval,
@@ -594,7 +591,7 @@ static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
psr_context->sdpTransmitLineNumDeadline);
 
-   if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
+   if (psr_context->allow_smu_optimizations)
REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
 
/* waitDMCUReadyForCmd */
@@ -615,6 +612,7 @@ static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
psr_context->psrFrameCaptureIndicationReq;
masterCmdData1.bits.aux_chan = psr_context->channel;
masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
+   masterCmdData1.bits.allow_smu_optimizations = 
psr_context->allow_smu_optimizations;
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
masterCmdData1.u32All);
 
@@ -635,6 +633,7 @@ static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
masterCmdData3.u32All);
 
+
/* setDMCUParam_Cmd */
REG_UPDATE(MASTER_COMM_CMD_REG,
MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index c24c0e5..60ce56f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -199,16 +199,16 @@ struct dce_dmcu {
  **/
 union dce_dmcu_psr_config_data_reg1 {
struct {
-   unsigned int timehyst_frames:8;/*[7:0]*/
-   unsigned int hyst_lines:7; /*[14:8]*/
-   unsigned int rfb_update_auto_en:1; /*[15:15]*/
-   unsigned int dp_port_num:3;/*[18:16]*/
-   unsigned int dcp_sel:3;/*[21:19]*/
-   unsigned int phy_type:1;   /*[22:22]*/
-   unsigned int frame_cap_ind:1;  /*[23:23]*/
-   unsigned int aux_chan:3;   /*[26:24]*/
-   unsigned int aux_repeat:4; /*[30:27]*/
-   unsigned int reserved:1;   /*[31:31]*/
+   unsigned int timehyst_frames:8;  /*[7:0]*/
+   unsigned int hyst_lines:7;   /*[14:8]*/
+   unsigned int rfb_update_auto_en:1;   /*[15:15]*/
+   unsigned int dp_port_num:3;  /*[18:16]*/
+   unsigned int dcp_sel:3;  /*[21:19]*/
+   unsigned int phy_type:1; /*[22:22]*/

[PATCH 02/16] drm/amd/display: Free DCN version of stream encoder

[sunpeng.li]

From: Eric Bernstein 

Cross a TODO item off the list. Cleanup SIGNAL_TYPE_HDMI_FRL, it's
not currently supported.

Signed-off-by: Eric Bernstein 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 8 +---
 drivers/gpu/drm/amd/display/dc/inc/core_types.h   | 1 +
 3 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7f3c7de..102 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -260,6 +260,7 @@ bool resource_construct(
pool->stream_enc_count++;
}
}
+
dc->caps.dynamic_audio = false;
if (pool->audio_count < pool->stream_enc_count) {
dc->caps.dynamic_audio = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 3d82fdd..e879829 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -874,10 +874,7 @@ static void destruct(struct dcn10_resource_pool *pool)
 
for (i = 0; i < pool->base.stream_enc_count; i++) {
if (pool->base.stream_enc[i] != NULL) {
-   /* TODO: free dcn version of stream encoder once 
implemented
-* rather than using virtual stream encoder
-*/
-   kfree(pool->base.stream_enc[i]);
+   
kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
pool->base.stream_enc[i] = NULL;
}
}
@@ -930,9 +927,6 @@ static void destruct(struct dcn10_resource_pool *pool)
}
}
 
-   for (i = 0; i < pool->base.stream_enc_count; i++)
-   kfree(pool->base.stream_enc[i]);
-
for (i = 0; i < pool->base.audio_count; i++) {
if (pool->base.audios[i])
dce_aud_destroy(>base.audios[i]);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h 
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 9df1a2f..ab16683 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -154,6 +154,7 @@ struct resource_pool {
unsigned int pipe_count;
unsigned int underlay_pipe_index;
unsigned int stream_enc_count;
+
unsigned int ref_clock_inKhz;
unsigned int timing_generator_count;
 
-- 
2.7.4

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[PATCH 15/16] drm/amd/display: add i2c over aux failure handling

[sunpeng.li]

From: Wenjing Liu 

[why]
We will not retry when EDID read failure using i2c over aux

[how]
treat i2c over aux failure the same as defer

Signed-off-by: Wenjing Liu 
Reviewed-by: David Francis 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/dc_ddc_types.h | 2 ++
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
index 05c8c31..4ef97f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
@@ -68,6 +68,8 @@ enum aux_transaction_reply {
AUX_TRANSACTION_REPLY_AUX_ACK = 0x00,
AUX_TRANSACTION_REPLY_AUX_NACK = 0x01,
AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02,
+   AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK = 0x04,
+   AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER = 0x08,
 
AUX_TRANSACTION_REPLY_I2C_ACK = 0x00,
AUX_TRANSACTION_REPLY_I2C_NACK = 0x10,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index c9b881d..cdb3042 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -528,6 +528,8 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
break;
 
case AUX_TRANSACTION_REPLY_AUX_DEFER:
+   case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
+   case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
if (++aux_defer_retries >= 
AUX_MAX_DEFER_RETRIES)
goto fail;
break;
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT info v2

[Christian König]

Am 28.02.19 um 18:08 schrieb Russell, Kent:

Add 6 files that return (in bytes):
The total amount of VRAM/visible VRAM/GTT
and the current total used VRAM/visible VRAM/GTT

v2: Split used and total into separate files

Change-Id: I0bd702b166b4253887ef76fb1bba8b9aadc7e2c5
Signed-off-by: Kent Russell 


Having a separate DRM_ERROR for each file looks like a bit overkill, but 
not much of a problem.


Anyway patch is Reviewed-by: Christian König .

And thanks for the LWN link, going to keep that around when somebody 
else asks.


Regards,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c  |  59 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 109 +++
  2 files changed, 168 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index da7b1b92d9cf..62591d081856 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -36,6 +36,47 @@ struct amdgpu_gtt_node {
struct ttm_buffer_object *tbo;
  };
  
+/**

+ * DOC: mem_info_gtt_total
+ *
+ * The amdgpu driver provides a sysfs API for reporting current total size of
+ * the GTT.
+ * The file mem_info_gtt_total is used for this, and returns the total size of
+ * the GTT block, in bytes
+ */
+static ssize_t amdgpu_mem_info_gtt_total_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%llu\n",
+   (adev->mman.bdev.man[TTM_PL_TT].size) * PAGE_SIZE);
+}
+
+/**
+ * DOC: mem_info_gtt_used
+ *
+ * The amdgpu driver provides a sysfs API for reporting current total amount of
+ * used GTT.
+ * The file mem_info_gtt_used is used for this, and returns the current used
+ * size of the GTT block, in bytes
+ */
+static ssize_t amdgpu_mem_info_gtt_used_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%llu\n",
+   amdgpu_gtt_mgr_usage(>mman.bdev.man[TTM_PL_TT]));
+}
+
+static DEVICE_ATTR(mem_info_gtt_total, S_IRUGO,
+  amdgpu_mem_info_gtt_total_show, NULL);
+static DEVICE_ATTR(mem_info_gtt_used, S_IRUGO,
+  amdgpu_mem_info_gtt_used_show, NULL);
+
  /**
   * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
   *
@@ -50,6 +91,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager 
*man,
struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
struct amdgpu_gtt_mgr *mgr;
uint64_t start, size;
+   int ret;
  
  	mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);

if (!mgr)
@@ -61,6 +103,18 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager 
*man,
spin_lock_init(>lock);
atomic64_set(>available, p_size);
man->priv = mgr;
+
+   ret = device_create_file(adev->dev, _attr_mem_info_gtt_total);
+   if (ret) {
+   DRM_ERROR("Failed to create device file mem_info_gtt_total\n");
+   return ret;
+   }
+   ret = device_create_file(adev->dev, _attr_mem_info_gtt_used);
+   if (ret) {
+   DRM_ERROR("Failed to create device file mem_info_gtt_used\n");
+   return ret;
+   }
+
return 0;
  }
  
@@ -74,12 +128,17 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man,

   */
  static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
  {
+   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
struct amdgpu_gtt_mgr *mgr = man->priv;
spin_lock(>lock);
drm_mm_takedown(>mm);
spin_unlock(>lock);
kfree(mgr);
man->priv = NULL;
+
+   device_remove_file(adev->dev, _attr_mem_info_gtt_total);
+   device_remove_file(adev->dev, _attr_mem_info_gtt_used);
+
return 0;
  }
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

index 3f9d5d00c9b3..ec9ea3fdbb4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -32,6 +32,85 @@ struct amdgpu_vram_mgr {
atomic64_t vis_usage;
  };
  
+/**

+ * DOC: mem_info_vram_total
+ *
+ * The amdgpu driver provides a sysfs API for reporting current total VRAM
+ * available on the device
+ * The file mem_info_vram_total is used for this and returns the total
+ * amount of VRAM in bytes
+ */
+static ssize_t amdgpu_mem_info_vram_total_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%llu\n", adev->gmc.real_vram_size);
+}
+
+/**
+ * DOC: 

[PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT info v2

[Russell, Kent]

Add 6 files that return (in bytes):
The total amount of VRAM/visible VRAM/GTT
and the current total used VRAM/visible VRAM/GTT

v2: Split used and total into separate files

Change-Id: I0bd702b166b4253887ef76fb1bba8b9aadc7e2c5
Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c  |  59 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 109 +++
 2 files changed, 168 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index da7b1b92d9cf..62591d081856 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -36,6 +36,47 @@ struct amdgpu_gtt_node {
struct ttm_buffer_object *tbo;
 };
 
+/**
+ * DOC: mem_info_gtt_total
+ *
+ * The amdgpu driver provides a sysfs API for reporting current total size of
+ * the GTT.
+ * The file mem_info_gtt_total is used for this, and returns the total size of
+ * the GTT block, in bytes
+ */
+static ssize_t amdgpu_mem_info_gtt_total_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%llu\n",
+   (adev->mman.bdev.man[TTM_PL_TT].size) * PAGE_SIZE);
+}
+
+/**
+ * DOC: mem_info_gtt_used
+ *
+ * The amdgpu driver provides a sysfs API for reporting current total amount of
+ * used GTT.
+ * The file mem_info_gtt_used is used for this, and returns the current used
+ * size of the GTT block, in bytes
+ */
+static ssize_t amdgpu_mem_info_gtt_used_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%llu\n",
+   amdgpu_gtt_mgr_usage(>mman.bdev.man[TTM_PL_TT]));
+}
+
+static DEVICE_ATTR(mem_info_gtt_total, S_IRUGO,
+  amdgpu_mem_info_gtt_total_show, NULL);
+static DEVICE_ATTR(mem_info_gtt_used, S_IRUGO,
+  amdgpu_mem_info_gtt_used_show, NULL);
+
 /**
  * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
  *
@@ -50,6 +91,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager 
*man,
struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
struct amdgpu_gtt_mgr *mgr;
uint64_t start, size;
+   int ret;
 
mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
if (!mgr)
@@ -61,6 +103,18 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager 
*man,
spin_lock_init(>lock);
atomic64_set(>available, p_size);
man->priv = mgr;
+
+   ret = device_create_file(adev->dev, _attr_mem_info_gtt_total);
+   if (ret) {
+   DRM_ERROR("Failed to create device file mem_info_gtt_total\n");
+   return ret;
+   }
+   ret = device_create_file(adev->dev, _attr_mem_info_gtt_used);
+   if (ret) {
+   DRM_ERROR("Failed to create device file mem_info_gtt_used\n");
+   return ret;
+   }
+
return 0;
 }
 
@@ -74,12 +128,17 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager 
*man,
  */
 static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
 {
+   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
struct amdgpu_gtt_mgr *mgr = man->priv;
spin_lock(>lock);
drm_mm_takedown(>mm);
spin_unlock(>lock);
kfree(mgr);
man->priv = NULL;
+
+   device_remove_file(adev->dev, _attr_mem_info_gtt_total);
+   device_remove_file(adev->dev, _attr_mem_info_gtt_used);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 3f9d5d00c9b3..ec9ea3fdbb4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -32,6 +32,85 @@ struct amdgpu_vram_mgr {
atomic64_t vis_usage;
 };
 
+/**
+ * DOC: mem_info_vram_total
+ *
+ * The amdgpu driver provides a sysfs API for reporting current total VRAM
+ * available on the device
+ * The file mem_info_vram_total is used for this and returns the total
+ * amount of VRAM in bytes
+ */
+static ssize_t amdgpu_mem_info_vram_total_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%llu\n", adev->gmc.real_vram_size);
+}
+
+/**
+ * DOC: mem_info_vis_vram_total
+ *
+ * The amdgpu driver provides a sysfs API for reporting current total
+ * visible VRAM available on the device
+ * The file mem_info_vis_vram_total is used for this and returns the total
+ * amount of visible VRAM in bytes
+ */
+static ssize_t amdgpu_mem_info_vis_vram_total_show(struct 

RE: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT info

[Russell, Kent]

The issue with the pcie_bw file is that the sent/received information needs to 
be obtained simultaneously, so those calculations need to be together and thus 
can't be split over two files (aside: I did find an old article about the whole 
one-value-per-file thing, where it's described as being a rule that ~10% of 
sysfs files don't follow; https://lwn.net/Articles/378884/) .

I have no issue splitting this memory usage apart. The values don't NEED to be 
together, so I can definitely split them up to try to keep with the spirit of 
sysfs. This also means that if the hammer drops and all sysfs files must 
conform to that standard at some point in the future, I'll have less work to do.

 Kent
> -Original Message-
> From: amd-gfx  On Behalf Of
> Deucher, Alexander
> Sent: Thursday, February 28, 2019 11:13 AM
> To: Kuehling, Felix ; Koenig, Christian
> ; Russell, Kent ;
> amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT
> info
> 
> > -Original Message-
> > From: amd-gfx  On Behalf Of
> > Kuehling, Felix
> > Sent: Thursday, February 28, 2019 11:09 AM
> > To: Koenig, Christian ; Russell, Kent
> > ; amd-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH] drm/amdgpu: Add sysfs files for returning
> > VRAM/GTT info
> >
> > On 2/28/2019 9:56 AM, Christian König wrote:
> > > Am 28.02.19 um 16:32 schrieb Russell, Kent:
> > >> Add 3 files that return:
> > >> The total amount of VRAM and the current total used VRAM The total
> > >> amount of VRAM and the current total used visible VRAM The total
> > >> GTT size and the current total of used GTT
> > >>
> > >> Each returns 2 integers, total and used, in bytes
> > >
> > > Well that is a good start, but unfortunately violates the rules for
> > > sysfs. You need to return one value per file.
> >
> > Is this rule written down anywhere. I see that space-separated lists
> > of things are common. E.g. scaling_available_governors in the cpufreq
> directories.
> >
> > In Documentation/admin-guide/sysfs-rules.rst I don't see any rule
> > about single value per file. Maybe that's because these rules are more
> > from user mode usage of sysfs rather than for kernel implementations.
> 
> This (two values) is also more consistent with the pcie bw file IIRC.
> 
> Alex
> 
> >
> > Regards,
> >    Felix
> >
> >
> > >
> > > So you should create 6 files in total.
> > >
> > > Regards,
> > > Christian.
> > >
> > >>
> > >> Change-Id: I0bd702b166b4253887ef76fb1bba8b9aadc7e2c5
> > >> Signed-off-by: Kent Russell 
> > >> ---
> > >>   drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c  | 36
> +++
> > >>   drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 67
> > >> 
> > >>   2 files changed, 103 insertions(+)
> > >>
> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> > >> index da7b1b92d9cf..adfa211c5152 100644
> > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> > >> @@ -36,6 +36,30 @@ struct amdgpu_gtt_node {
> > >>   struct ttm_buffer_object *tbo;
> > >>   };
> > >>   +/**
> > >> + * DOC: mem_info_gtt
> > >> + *
> > >> + * The amdgpu driver provides a sysfs API for reporting current
> > >> + GTT
> > >> information
> > >> + * The file mem_info_gtt is used for this.
> > >> + * The file returns the total size of the GTT block and the
> > >> + current
> > >> amount of
> > >> + * used GTT as 2 separate integers, in bytes  */ static ssize_t
> > >> +amdgpu_mem_info_gtt_show(struct device *dev,
> > >> +    struct device_attribute *attr, char *buf) {
> > >> +    struct drm_device *ddev = dev_get_drvdata(dev);
> > >> +    struct amdgpu_device *adev = ddev->dev_private;
> > >> +    uint64_t used_gtt, total_gtt;
> > >> +
> > >> +    used_gtt =
> > >> +amdgpu_gtt_mgr_usage(>mman.bdev.man[TTM_PL_TT]);
> > >> +    total_gtt = (adev->mman.bdev.man[TTM_PL_TT].size) * PAGE_SIZE;
> > >> +
> > >> +    return snprintf(buf, PAGE_SIZE, "%llu %llu\n",
> > >> +  total_gtt, used_gtt); }
> > >> +
> > >> +static DEVICE_ATTR(mem_info_gtt, S_IRUGO,
> > amdgpu_mem_info_gtt_show,
> > >> NULL);
> > >> +
> > >>   /**
> > >>    * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
> > >>    *
> > >> @@ -50,6 +74,7 @@ static int amdgpu_gtt_mgr_init(struct
> > >> ttm_mem_type_manager *man,
> > >>   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
> > >>   struct amdgpu_gtt_mgr *mgr;
> > >>   uint64_t start, size;
> > >> +    int ret;
> > >>     mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
> > >>   if (!mgr)
> > >> @@ -61,6 +86,13 @@ static int amdgpu_gtt_mgr_init(struct
> > >> ttm_mem_type_manager *man,
> > >>   spin_lock_init(>lock);
> > >>   atomic64_set(>available, p_size);
> > >>   man->priv = mgr;
> > >> +
> > >> +    ret = device_create_file(adev->dev, _attr_mem_info_gtt);
> > >> +    if (ret) {
> > >> +    DRM_ERROR("Failed to create device file 

Re: [PATCH 1/2] drm/amd/powerplay: correct power reading on fiji

[Ernst Sjöstrand]

Wasn't there a long discussion about this timing some months ago... ?

Regards
//Ernst

Den tors 28 feb. 2019 kl 11:47 skrev Xu, Feifei :
>
> Reviewed-by: Feifei Xu 
>
> -Original Message-
> From: amd-gfx  On Behalf Of Evan Quan
> Sent: Thursday, February 28, 2019 6:32 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan 
> Subject: [PATCH 1/2] drm/amd/powerplay: correct power reading on fiji
>
> Set sampling period as 500ms to provide a smooth power reading output. Also, 
> correct the register for power reading.
>
> Change-Id: I13935f3e7fcd026d34aa6a68cf7f683dc6785ab7
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 48187acac59e..83d3d935f3ac 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3491,14 +3491,14 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, 
> u32 *query)
>
> smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
> cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> -   ixSMU_PM_STATUS_94, 
> 0);
> +   ixSMU_PM_STATUS_95, 
> 0);
>
> for (i = 0; i < 10; i++) {
> -   mdelay(1);
> +   mdelay(500);
> smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
> tmp = cgs_read_ind_register(hwmgr->device,
> CGS_IND_REG__SMC,
> -   ixSMU_PM_STATUS_94);
> +   ixSMU_PM_STATUS_95);
> if (tmp != 0)
> break;
> }
> --
> 2.21.0
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH xf86-video-amdgpu] Fix hang when entering into dpms-off mode

[Michel Dänzer]

On 2019-02-28 1:05 p.m., Michel Dänzer wrote:
> On 2019-02-28 3:52 a.m., Aaron Liu wrote:
>>
>> @@ -900,7 +900,12 @@ CARD32 amdgpu_dri2_deferred_event(OsTimerPtr timer, 
>> CARD32 now, pointer data)
>>  delta_seq = delta_t * drmmode_crtc->dpms_last_fps;
>>  delta_seq /= 100;
>>  frame = (CARD64) drmmode_crtc->dpms_last_seq + delta_seq;
>> -if (event_info->drm_queue_seq)
>> +/*
>> + * If CRTC is in DPMS off state, it can't use vblank_handler.
>> + * Because drmmode_wait_vblank is not excuted in such as
>> + * amdgpu_dri2_schedule_swap/amdgpu_dri2_schedule_wait_msc.
>> + */
>> +if (event_info->drm_queue_seq && amdgpu_crtc_is_enabled(crtc))
>>  drmmode_crtc->drmmode->event_context.
>>  vblank_handler(pAMDGPUEnt->fd, frame, drm_now / 100,
>> drm_now % 100,
>>
> 
> This isn't a good solution I'm afraid, as it'll leave the struct
> amdgpu_drm_queue_entry memory associated with event_info->drm_queue_seq
> linked into the amdgpu_drm_queue list, which would gradually slow down
> processing of that list.
> 
> 
> I think I know what the issue is, I'll work on a fix in the afternoon.

Please test
https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu/merge_requests/29
.


-- 
Earthling Michel Dänzer   |  https://www.amd.com
Libre software enthusiast | Mesa and X developer
___
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Re: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT info

[Koenig, Christian]

Am 28.02.19 um 17:09 schrieb Kuehling, Felix:

On 2/28/2019 9:56 AM, Christian König wrote:


Am 28.02.19 um 16:32 schrieb Russell, Kent:


Add 3 files that return:
The total amount of VRAM and the current total used VRAM
The total amount of VRAM and the current total used visible VRAM
The total GTT size and the current total of used GTT

Each returns 2 integers, total and used, in bytes



Well that is a good start, but unfortunately violates the rules for
sysfs. You need to return one value per file.



Is this rule written down anywhere. I see that space-separated lists of
things are common. E.g. scaling_available_governors in the cpufreq
directories.

In Documentation/admin-guide/sysfs-rules.rst I don't see any rule about
single value per file. Maybe that's because these rules are more from
user mode usage of sysfs rather than for kernel implementations.

Certainly somewhere. I only know it because my patches doing this where 
rejected as well.

Quick googling turned up the following:

Attributes should be ASCII text files, preferably with only one value
per file. It is noted that it may not be efficient to contain only one
value per file, so it is socially acceptable to express an array of
values of the same type.

Mixing types, expressing multiple lines of data, and doing fancy
formatting of data is heavily frowned upon. Doing these things may get
you publicly humiliated and your code rewritten without notice.

Regards,
Christian.




Regards,
   Felix





So you should create 6 files in total.

Regards,
Christian.




Change-Id: I0bd702b166b4253887ef76fb1bba8b9aadc7e2c5
Signed-off-by: Kent Russell 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c  | 36 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 67 
  2 files changed, 103 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index da7b1b92d9cf..adfa211c5152 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -36,6 +36,30 @@ struct amdgpu_gtt_node {
  struct ttm_buffer_object *tbo;
  };
  +/**
+ * DOC: mem_info_gtt
+ *
+ * The amdgpu driver provides a sysfs API for reporting current GTT
information
+ * The file mem_info_gtt is used for this.
+ * The file returns the total size of the GTT block and the current
amount of
+ * used GTT as 2 separate integers, in bytes
+ */
+static ssize_t amdgpu_mem_info_gtt_show(struct device *dev,
+struct device_attribute *attr, char *buf)
+{
+struct drm_device *ddev = dev_get_drvdata(dev);
+struct amdgpu_device *adev = ddev->dev_private;
+uint64_t used_gtt, total_gtt;
+
+used_gtt = amdgpu_gtt_mgr_usage(>mman.bdev.man[TTM_PL_TT]);
+total_gtt = (adev->mman.bdev.man[TTM_PL_TT].size) * PAGE_SIZE;
+
+return snprintf(buf, PAGE_SIZE, "%llu %llu\n",
+  total_gtt, used_gtt);
+}
+
+static DEVICE_ATTR(mem_info_gtt, S_IRUGO, amdgpu_mem_info_gtt_show,
NULL);
+
  /**
   * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
   *
@@ -50,6 +74,7 @@ static int amdgpu_gtt_mgr_init(struct
ttm_mem_type_manager *man,
  struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
  struct amdgpu_gtt_mgr *mgr;
  uint64_t start, size;
+int ret;
mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
  if (!mgr)
@@ -61,6 +86,13 @@ static int amdgpu_gtt_mgr_init(struct
ttm_mem_type_manager *man,
  spin_lock_init(>lock);
  atomic64_set(>available, p_size);
  man->priv = mgr;
+
+ret = device_create_file(adev->dev, _attr_mem_info_gtt);
+if (ret) {
+DRM_ERROR("Failed to create device file mem_info_gtt\n");
+return ret;
+}
+
  return 0;
  }
  @@ -74,12 +106,16 @@ static int amdgpu_gtt_mgr_init(struct
ttm_mem_type_manager *man,
   */
  static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
  {
+struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
  struct amdgpu_gtt_mgr *mgr = man->priv;
  spin_lock(>lock);
  drm_mm_takedown(>mm);
  spin_unlock(>lock);
  kfree(mgr);
  man->priv = NULL;
+
+device_remove_file(adev->dev, _attr_mem_info_gtt);
+
  return 0;
  }
  diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 3f9d5d00c9b3..d0bada997cba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -32,6 +32,55 @@ struct amdgpu_vram_mgr {
  atomic64_t vis_usage;
  };
  +/**
+ * DOC: mem_info_vram
+ *
+ * The amdgpu driver provides a sysfs API for reporting current VRAM
information
+ * The file mem_info_vram is used for this.
+ * The file returns the total amount of VRAM and the current total
amount of
+ * used VRAM as 2 separate integers, in bytes
+ */
+static ssize_t amdgpu_mem_info_vram_show(struct device *dev,
+struct device_attribute *attr, char *buf)
+{
+struct drm_device *ddev = 

RE: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT info

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Kuehling, Felix
> Sent: Thursday, February 28, 2019 11:09 AM
> To: Koenig, Christian ; Russell, Kent
> ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT
> info
> 
> On 2/28/2019 9:56 AM, Christian König wrote:
> > Am 28.02.19 um 16:32 schrieb Russell, Kent:
> >> Add 3 files that return:
> >> The total amount of VRAM and the current total used VRAM The total
> >> amount of VRAM and the current total used visible VRAM The total GTT
> >> size and the current total of used GTT
> >>
> >> Each returns 2 integers, total and used, in bytes
> >
> > Well that is a good start, but unfortunately violates the rules for
> > sysfs. You need to return one value per file.
> 
> Is this rule written down anywhere. I see that space-separated lists of things
> are common. E.g. scaling_available_governors in the cpufreq directories.
> 
> In Documentation/admin-guide/sysfs-rules.rst I don't see any rule about
> single value per file. Maybe that's because these rules are more from user
> mode usage of sysfs rather than for kernel implementations.

This (two values) is also more consistent with the pcie bw file IIRC.

Alex

> 
> Regards,
>    Felix
> 
> 
> >
> > So you should create 6 files in total.
> >
> > Regards,
> > Christian.
> >
> >>
> >> Change-Id: I0bd702b166b4253887ef76fb1bba8b9aadc7e2c5
> >> Signed-off-by: Kent Russell 
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c  | 36 +++
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 67
> >> 
> >>   2 files changed, 103 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> >> index da7b1b92d9cf..adfa211c5152 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> >> @@ -36,6 +36,30 @@ struct amdgpu_gtt_node {
> >>   struct ttm_buffer_object *tbo;
> >>   };
> >>   +/**
> >> + * DOC: mem_info_gtt
> >> + *
> >> + * The amdgpu driver provides a sysfs API for reporting current GTT
> >> information
> >> + * The file mem_info_gtt is used for this.
> >> + * The file returns the total size of the GTT block and the current
> >> amount of
> >> + * used GTT as 2 separate integers, in bytes  */ static ssize_t
> >> +amdgpu_mem_info_gtt_show(struct device *dev,
> >> +    struct device_attribute *attr, char *buf) {
> >> +    struct drm_device *ddev = dev_get_drvdata(dev);
> >> +    struct amdgpu_device *adev = ddev->dev_private;
> >> +    uint64_t used_gtt, total_gtt;
> >> +
> >> +    used_gtt =
> >> +amdgpu_gtt_mgr_usage(>mman.bdev.man[TTM_PL_TT]);
> >> +    total_gtt = (adev->mman.bdev.man[TTM_PL_TT].size) * PAGE_SIZE;
> >> +
> >> +    return snprintf(buf, PAGE_SIZE, "%llu %llu\n",
> >> +  total_gtt, used_gtt); }
> >> +
> >> +static DEVICE_ATTR(mem_info_gtt, S_IRUGO,
> amdgpu_mem_info_gtt_show,
> >> NULL);
> >> +
> >>   /**
> >>    * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
> >>    *
> >> @@ -50,6 +74,7 @@ static int amdgpu_gtt_mgr_init(struct
> >> ttm_mem_type_manager *man,
> >>   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
> >>   struct amdgpu_gtt_mgr *mgr;
> >>   uint64_t start, size;
> >> +    int ret;
> >>     mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
> >>   if (!mgr)
> >> @@ -61,6 +86,13 @@ static int amdgpu_gtt_mgr_init(struct
> >> ttm_mem_type_manager *man,
> >>   spin_lock_init(>lock);
> >>   atomic64_set(>available, p_size);
> >>   man->priv = mgr;
> >> +
> >> +    ret = device_create_file(adev->dev, _attr_mem_info_gtt);
> >> +    if (ret) {
> >> +    DRM_ERROR("Failed to create device file mem_info_gtt\n");
> >> +    return ret;
> >> +    }
> >> +
> >>   return 0;
> >>   }
> >>   @@ -74,12 +106,16 @@ static int amdgpu_gtt_mgr_init(struct
> >> ttm_mem_type_manager *man,
> >>    */
> >>   static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
> >>   {
> >> +    struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
> >>   struct amdgpu_gtt_mgr *mgr = man->priv;
> >>   spin_lock(>lock);
> >>   drm_mm_takedown(>mm);
> >>   spin_unlock(>lock);
> >>   kfree(mgr);
> >>   man->priv = NULL;
> >> +
> >> +    device_remove_file(adev->dev, _attr_mem_info_gtt);
> >> +
> >>   return 0;
> >>   }
> >>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> >> index 3f9d5d00c9b3..d0bada997cba 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> >> @@ -32,6 +32,55 @@ struct amdgpu_vram_mgr {
> >>   atomic64_t vis_usage;
> >>   };
> >>   +/**
> >> + * DOC: mem_info_vram
> >> + *
> >> + * The amdgpu driver provides a sysfs API for reporting current VRAM
> >> information
> >> + * The file mem_info_vram is used for this.
> >> + * The file returns 

Re: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT info

[Kuehling, Felix]

On 2/28/2019 9:56 AM, Christian König wrote:
> Am 28.02.19 um 16:32 schrieb Russell, Kent:
>> Add 3 files that return:
>> The total amount of VRAM and the current total used VRAM
>> The total amount of VRAM and the current total used visible VRAM
>> The total GTT size and the current total of used GTT
>>
>> Each returns 2 integers, total and used, in bytes
>
> Well that is a good start, but unfortunately violates the rules for 
> sysfs. You need to return one value per file.

Is this rule written down anywhere. I see that space-separated lists of 
things are common. E.g. scaling_available_governors in the cpufreq 
directories.

In Documentation/admin-guide/sysfs-rules.rst I don't see any rule about 
single value per file. Maybe that's because these rules are more from 
user mode usage of sysfs rather than for kernel implementations.

Regards,
   Felix


>
> So you should create 6 files in total.
>
> Regards,
> Christian.
>
>>
>> Change-Id: I0bd702b166b4253887ef76fb1bba8b9aadc7e2c5
>> Signed-off-by: Kent Russell 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c  | 36 +++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 67 
>>   2 files changed, 103 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
>> index da7b1b92d9cf..adfa211c5152 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
>> @@ -36,6 +36,30 @@ struct amdgpu_gtt_node {
>>   struct ttm_buffer_object *tbo;
>>   };
>>   +/**
>> + * DOC: mem_info_gtt
>> + *
>> + * The amdgpu driver provides a sysfs API for reporting current GTT 
>> information
>> + * The file mem_info_gtt is used for this.
>> + * The file returns the total size of the GTT block and the current 
>> amount of
>> + * used GTT as 2 separate integers, in bytes
>> + */
>> +static ssize_t amdgpu_mem_info_gtt_show(struct device *dev,
>> +    struct device_attribute *attr, char *buf)
>> +{
>> +    struct drm_device *ddev = dev_get_drvdata(dev);
>> +    struct amdgpu_device *adev = ddev->dev_private;
>> +    uint64_t used_gtt, total_gtt;
>> +
>> +    used_gtt = amdgpu_gtt_mgr_usage(>mman.bdev.man[TTM_PL_TT]);
>> +    total_gtt = (adev->mman.bdev.man[TTM_PL_TT].size) * PAGE_SIZE;
>> +
>> +    return snprintf(buf, PAGE_SIZE, "%llu %llu\n",
>> +  total_gtt, used_gtt);
>> +}
>> +
>> +static DEVICE_ATTR(mem_info_gtt, S_IRUGO, amdgpu_mem_info_gtt_show, 
>> NULL);
>> +
>>   /**
>>    * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
>>    *
>> @@ -50,6 +74,7 @@ static int amdgpu_gtt_mgr_init(struct 
>> ttm_mem_type_manager *man,
>>   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
>>   struct amdgpu_gtt_mgr *mgr;
>>   uint64_t start, size;
>> +    int ret;
>>     mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
>>   if (!mgr)
>> @@ -61,6 +86,13 @@ static int amdgpu_gtt_mgr_init(struct 
>> ttm_mem_type_manager *man,
>>   spin_lock_init(>lock);
>>   atomic64_set(>available, p_size);
>>   man->priv = mgr;
>> +
>> +    ret = device_create_file(adev->dev, _attr_mem_info_gtt);
>> +    if (ret) {
>> +    DRM_ERROR("Failed to create device file mem_info_gtt\n");
>> +    return ret;
>> +    }
>> +
>>   return 0;
>>   }
>>   @@ -74,12 +106,16 @@ static int amdgpu_gtt_mgr_init(struct 
>> ttm_mem_type_manager *man,
>>    */
>>   static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
>>   {
>> +    struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
>>   struct amdgpu_gtt_mgr *mgr = man->priv;
>>   spin_lock(>lock);
>>   drm_mm_takedown(>mm);
>>   spin_unlock(>lock);
>>   kfree(mgr);
>>   man->priv = NULL;
>> +
>> +    device_remove_file(adev->dev, _attr_mem_info_gtt);
>> +
>>   return 0;
>>   }
>>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
>> index 3f9d5d00c9b3..d0bada997cba 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
>> @@ -32,6 +32,55 @@ struct amdgpu_vram_mgr {
>>   atomic64_t vis_usage;
>>   };
>>   +/**
>> + * DOC: mem_info_vram
>> + *
>> + * The amdgpu driver provides a sysfs API for reporting current VRAM 
>> information
>> + * The file mem_info_vram is used for this.
>> + * The file returns the total amount of VRAM and the current total 
>> amount of
>> + * used VRAM as 2 separate integers, in bytes
>> + */
>> +static ssize_t amdgpu_mem_info_vram_show(struct device *dev,
>> +    struct device_attribute *attr, char *buf)
>> +{
>> +    struct drm_device *ddev = dev_get_drvdata(dev);
>> +    struct amdgpu_device *adev = ddev->dev_private;
>> +    uint64_t used_vram, total_vram;
>> +
>> +    used_vram = 
>> amdgpu_vram_mgr_usage(>mman.bdev.man[TTM_PL_VRAM]);
>> +    total_vram = adev->gmc.real_vram_size;
>> +
>> +    return snprintf(buf, PAGE_SIZE, "%llu %llu\n", total_vram, 
>> 

RE: [PATCH] drm/amdgpu: Bump amdgpu version for per-flip plane tiling updates

[Deucher, Alexander]

Acked-by: Alex Deucher 

> -Original Message-
> From: amd-gfx  On Behalf Of
> Nicholas Kazlauskas
> Sent: Thursday, February 28, 2019 10:00 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Michel Dänzer ; Kazlauskas, Nicholas
> ; Marek Olšák 
> Subject: [PATCH] drm/amdgpu: Bump amdgpu version for per-flip plane tiling
> updates
> 
> To help xf86-video-amdgpu and mesa know DC supports updating the tiling
> attributes for a framebuffer per-flip.
> 
> Cc: Michel Dänzer 
> Cc: Marek Olšák 
> Signed-off-by: Nicholas Kazlauskas 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 223013ef8466..ae4e3eeb4ae2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -74,9 +74,10 @@
>   * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
>   * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
>   * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
> + * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
>   */
>  #define KMS_DRIVER_MAJOR 3
> -#define KMS_DRIVER_MINOR 30
> +#define KMS_DRIVER_MINOR 31
>  #define KMS_DRIVER_PATCHLEVEL0
> 
>  int amdgpu_vram_limit = 0;
> --
> 2.17.1
> 
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Re: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT info

[Christian König]

Am 28.02.19 um 16:32 schrieb Russell, Kent:

Add 3 files that return:
The total amount of VRAM and the current total used VRAM
The total amount of VRAM and the current total used visible VRAM
The total GTT size and the current total of used GTT

Each returns 2 integers, total and used, in bytes


Well that is a good start, but unfortunately violates the rules for 
sysfs. You need to return one value per file.


So you should create 6 files in total.

Regards,
Christian.



Change-Id: I0bd702b166b4253887ef76fb1bba8b9aadc7e2c5
Signed-off-by: Kent Russell 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c  | 36 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 67 
  2 files changed, 103 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index da7b1b92d9cf..adfa211c5152 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -36,6 +36,30 @@ struct amdgpu_gtt_node {
struct ttm_buffer_object *tbo;
  };
  
+/**

+ * DOC: mem_info_gtt
+ *
+ * The amdgpu driver provides a sysfs API for reporting current GTT information
+ * The file mem_info_gtt is used for this.
+ * The file returns the total size of the GTT block and the current amount of
+ * used GTT as 2 separate integers, in bytes
+ */
+static ssize_t amdgpu_mem_info_gtt_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   uint64_t used_gtt, total_gtt;
+
+   used_gtt = amdgpu_gtt_mgr_usage(>mman.bdev.man[TTM_PL_TT]);
+   total_gtt = (adev->mman.bdev.man[TTM_PL_TT].size) * PAGE_SIZE;
+
+   return snprintf(buf, PAGE_SIZE, "%llu %llu\n",
+ total_gtt, used_gtt);
+}
+
+static DEVICE_ATTR(mem_info_gtt, S_IRUGO, amdgpu_mem_info_gtt_show, NULL);
+
  /**
   * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
   *
@@ -50,6 +74,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager 
*man,
struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
struct amdgpu_gtt_mgr *mgr;
uint64_t start, size;
+   int ret;
  
  	mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);

if (!mgr)
@@ -61,6 +86,13 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager 
*man,
spin_lock_init(>lock);
atomic64_set(>available, p_size);
man->priv = mgr;
+
+   ret = device_create_file(adev->dev, _attr_mem_info_gtt);
+   if (ret) {
+   DRM_ERROR("Failed to create device file mem_info_gtt\n");
+   return ret;
+   }
+
return 0;
  }
  
@@ -74,12 +106,16 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man,

   */
  static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
  {
+   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
struct amdgpu_gtt_mgr *mgr = man->priv;
spin_lock(>lock);
drm_mm_takedown(>mm);
spin_unlock(>lock);
kfree(mgr);
man->priv = NULL;
+
+   device_remove_file(adev->dev, _attr_mem_info_gtt);
+
return 0;
  }
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

index 3f9d5d00c9b3..d0bada997cba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -32,6 +32,55 @@ struct amdgpu_vram_mgr {
atomic64_t vis_usage;
  };
  
+/**

+ * DOC: mem_info_vram
+ *
+ * The amdgpu driver provides a sysfs API for reporting current VRAM 
information
+ * The file mem_info_vram is used for this.
+ * The file returns the total amount of VRAM and the current total amount of
+ * used VRAM as 2 separate integers, in bytes
+ */
+static ssize_t amdgpu_mem_info_vram_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   uint64_t used_vram, total_vram;
+
+   used_vram = amdgpu_vram_mgr_usage(>mman.bdev.man[TTM_PL_VRAM]);
+   total_vram = adev->gmc.real_vram_size;
+
+   return snprintf(buf, PAGE_SIZE, "%llu %llu\n", total_vram, used_vram);
+}
+
+/**
+ * DOC: mem_info_vis_vram
+ *
+ * The amdgpu driver provides a sysfs API for reporting current visible VRAM
+ * information
+ * The file mem_info_vis_vram is used for this.
+ * The file returns the total amount of VRAM and the current total amount of
+ * used visible VRAM as 2 separate integers, in bytes
+ */
+static ssize_t amdgpu_mem_info_vis_vram_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   uint64_t used_vis_vram, total_vram;
+
+   used_vis_vram =
+   

RE: [PATCH 2/2] drm/amd/powerplay: override duty cycle on Vega20

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx  On Behalf Of Evan
> Quan
> Sent: Thursday, February 28, 2019 5:32 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan 
> Subject: [PATCH 2/2] drm/amd/powerplay: override duty cycle on Vega20
> 
> This is needed for the new SMC firmwares only.
> 
> Change-Id: I5934e5161ec53c1dd73cb1542ef6b738ad2e620c
> Signed-off-by: Evan Quan 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c   | 16
> 
>  drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h |  3 ++-
>  2 files changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index 9aa7bec1b5fe..d35f60ab3404 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -828,6 +828,17 @@ static int vega20_override_pcie_parameters(struct
> pp_hwmgr *hwmgr)
>   return 0;
>  }
> 
> +static int vega20_override_duty_cycle(struct pp_hwmgr *hwmgr) {
> + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr-
> >adev);
> + int ret = 0;
> +
> + if (adev->pm.fw_version >= 0x00282700)
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_OverrideDutyCycle);
> +
> + return ret;
> +}
> +
>  static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)  {
>   struct vega20_hwmgr *data =
> @@ -1644,6 +1655,11 @@ static int vega20_enable_dpm_tasks(struct
> pp_hwmgr *hwmgr)
>   "[EnableDPMTasks] Failed to enable all smu
> features!",
>   return result);
> 
> + result = vega20_override_duty_cycle(hwmgr);
> + PP_ASSERT_WITH_CODE(!result,
> + "[EnableDPMTasks] Failed to override duty cycle!",
> + return result);
> +
>   result = vega20_override_pcie_parameters(hwmgr);
>   PP_ASSERT_WITH_CODE(!result,
>   "[EnableDPMTasks] Failed to override pcie
> parameters!", diff --git
> a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> index 4f63a736ea0e..4a1e01f04cf5 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> @@ -119,7 +119,8 @@
>  #define PPSMC_MSG_PrepareMp1ForShutdown  0x5A
>  #define PPSMC_MSG_SetMGpuFanBoostLimitRpm0x5D
>  #define PPSMC_MSG_GetAVFSVoltageByDpm0x5F
> -#define PPSMC_Message_Count  0x60
> +#define PPSMC_MSG_OverrideDutyCycle  0x64
> +#define PPSMC_Message_Count  0x65
> 
>  typedef uint32_t PPSMC_Result;
>  typedef uint32_t PPSMC_Msg;
> --
> 2.21.0
> 
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Re: KASAN caught amdgpu / HMM use-after-free

[Yang, Philip]

Hi Alex,

May you help take a look? It is not merged into amd-staging-drm-next 
yet, maybe missing code-review+2, it was done automatically after code 
review for other patch.

http://git.amd.com:8080/c/brahma/ec/linux/+/206711

Regards,
Philip

On 2019-02-28 6:51 a.m., Michel Dänzer wrote:
> 
> [ Dropping Jérôme and the linux-mm list ]
> 
> On 2019-02-27 7:48 p.m., Yang, Philip wrote:
>> Hi Alex,
>>
>> Pushed, thanks.
>>
>> mm/hmm: use reference counting for HMM struct
> 
> Thanks, but I'm not seeing it yet. Maybe it needs some special
> treatment, because it's not a DRM code change?
> 
> 
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[PATCH AUTOSEL 4.19 28/64] drm/amdgpu: Transfer fences to dmabuf importer

[Sasha Levin]

From: Chris Wilson 

[ Upstream commit 6e11ea9de9576a644045ffdc2067c09bc2012eda ]

amdgpu only uses shared-fences internally, but dmabuf importers rely on
implicit write hazard tracking via the reservation_object.fence_excl.
For example, the importer use the write hazard for timing a page flip to
only occur after the exporter has finished flushing its write into the
surface. As such, on exporting a dmabuf, we must either flush all
outstanding fences (for we do not know which are writes and should have
been exclusive) or alternatively create a new exclusive fence that is
the composite of all the existing shared fences, and so will only be
signaled when all earlier fences are signaled (ensuring that we can not
be signaled before the completion of any earlier write).

v2: reservation_object is already locked by amdgpu_bo_reserve()
v3: Replace looping with get_fences_rcu and special case the promotion
of a single shared fence directly to an exclusive fence, bypassing the
fence array.
v4: Drop the fence array ref after assigning to reservation_object

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107341
Testcase: igt/amd_prime/amd-to-i915
References: 8e94a46c1770 ("drm/amdgpu: Attach exclusive fence to prime exported 
bo's. (v5)")
Signed-off-by: Chris Wilson 
Cc: Alex Deucher 
Cc: "Christian König" 
Reviewed-by: "Christian König" 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 59 ---
 1 file changed, 51 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 1c5d97f4b4dde..8dcf6227ab990 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -37,6 +37,7 @@
 #include "amdgpu_display.h"
 #include 
 #include 
+#include 
 
 static const struct dma_buf_ops amdgpu_dmabuf_ops;
 
@@ -188,6 +189,48 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
return ERR_PTR(ret);
 }
 
+static int
+__reservation_object_make_exclusive(struct reservation_object *obj)
+{
+   struct dma_fence **fences;
+   unsigned int count;
+   int r;
+
+   if (!reservation_object_get_list(obj)) /* no shared fences to convert */
+   return 0;
+
+   r = reservation_object_get_fences_rcu(obj, NULL, , );
+   if (r)
+   return r;
+
+   if (count == 0) {
+   /* Now that was unexpected. */
+   } else if (count == 1) {
+   reservation_object_add_excl_fence(obj, fences[0]);
+   dma_fence_put(fences[0]);
+   kfree(fences);
+   } else {
+   struct dma_fence_array *array;
+
+   array = dma_fence_array_create(count, fences,
+  dma_fence_context_alloc(1), 0,
+  false);
+   if (!array)
+   goto err_fences_put;
+
+   reservation_object_add_excl_fence(obj, >base);
+   dma_fence_put(>base);
+   }
+
+   return 0;
+
+err_fences_put:
+   while (count--)
+   dma_fence_put(fences[count]);
+   kfree(fences);
+   return -ENOMEM;
+}
+
 /**
  * amdgpu_gem_map_attach - _buf_ops.attach implementation
  * @dma_buf: shared DMA buffer
@@ -219,16 +262,16 @@ static int amdgpu_gem_map_attach(struct dma_buf *dma_buf,
 
if (attach->dev->driver != adev->dev->driver) {
/*
-* Wait for all shared fences to complete before we switch to 
future
-* use of exclusive fence on this prime shared bo.
+* We only create shared fences for internal use, but importers
+* of the dmabuf rely on exclusive fences for implicitly
+* tracking write hazards. As any of the current fences may
+* correspond to a write, we need to convert all existing
+* fences on the reservation object into a single exclusive
+* fence.
 */
-   r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
-   true, false,
-   MAX_SCHEDULE_TIMEOUT);
-   if (unlikely(r < 0)) {
-   DRM_DEBUG_PRIME("Fence wait failed: %li\n", r);
+   r = __reservation_object_make_exclusive(bo->tbo.resv);
+   if (r)
goto error_unreserve;
-   }
}
 
/* pin buffer into GTT */
-- 
2.19.1

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[PATCH AUTOSEL 4.19 24/64] drm/amdgpu: Add missing power attribute to APU check

[Sasha Levin]

From: Alex Deucher 

[ Upstream commit dc14eb12f6bb3e779c5461429c1889a339c67aab ]

Add missing power_average to visible check for power
attributes for APUs.  Was missed before.

Reviewed-by: Evan Quan 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 7b4e657a95c70..c3df75a9f65d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1443,7 +1443,8 @@ static umode_t hwmon_attributes_visible(struct kobject 
*kobj,
effective_mode &= ~S_IWUSR;
 
if ((adev->flags & AMD_IS_APU) &&
-   (attr == _dev_attr_power1_cap_max.dev_attr.attr ||
+   (attr == _dev_attr_power1_average.dev_attr.attr ||
+attr == _dev_attr_power1_cap_max.dev_attr.attr ||
 attr == _dev_attr_power1_cap_min.dev_attr.attr||
 attr == _dev_attr_power1_cap.dev_attr.attr))
return 0;
-- 
2.19.1

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[PATCH AUTOSEL 4.20 71/81] drm/amdgpu: use spin_lock_irqsave to protect vm_manager.pasid_idr

[Sasha Levin]

From: Philip Yang 

[ Upstream commit 0a5f49cbf9d6ad3721c16f8a6d823363ea7a160f ]

amdgpu_vm_get_task_info is called from interrupt handler and sched timeout
workqueue, we should use irq version spin_lock to avoid deadlock.

Signed-off-by: Philip Yang 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 62df4bd0a0fc2..16c83155ef5ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -3405,14 +3405,15 @@ void amdgpu_vm_get_task_info(struct amdgpu_device 
*adev, unsigned int pasid,
 struct amdgpu_task_info *task_info)
 {
struct amdgpu_vm *vm;
+   unsigned long flags;
 
-   spin_lock(>vm_manager.pasid_lock);
+   spin_lock_irqsave(>vm_manager.pasid_lock, flags);
 
vm = idr_find(>vm_manager.pasid_idr, pasid);
if (vm)
*task_info = vm->task_info;
 
-   spin_unlock(>vm_manager.pasid_lock);
+   spin_unlock_irqrestore(>vm_manager.pasid_lock, flags);
 }
 
 /**
-- 
2.19.1

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[PATCH AUTOSEL 4.20 50/81] drm/amdgpu: Implement doorbell self-ring for NBIO 7.4

[Sasha Levin]

From: Jay Cornwall 

[ Upstream commit 12292519d919ecde92e7e7c8acbcdb9f0c7c6013 ]

Fixes doorbell reflection on Vega20.

Change-Id: I0495139d160a9032dff5977289b1eec11c16f781
Signed-off-by: Jay Cornwall 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index f8cee95d61cc1..7d5cbadbe1cbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -92,7 +92,20 @@ static void nbio_v7_4_enable_doorbell_aperture(struct 
amdgpu_device *adev,
 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device 
*adev,
bool enable)
 {
+   u32 tmp = 0;
 
+   if (enable) {
+   tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, 
DOORBELL_SELFRING_GPA_APER_EN, 1) |
+ REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, 
DOORBELL_SELFRING_GPA_APER_MODE, 1) |
+ REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, 
DOORBELL_SELFRING_GPA_APER_SIZE, 0);
+
+   WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
+lower_32_bits(adev->doorbell.base));
+   WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
+upper_32_bits(adev->doorbell.base));
+   }
+
+   WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
 }
 
 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
-- 
2.19.1

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[PATCH AUTOSEL 4.20 51/81] drm/amdgpu: fix the incorrect external id for raven series

[Sasha Levin]

From: Huang Rui 

[ Upstream commit 7e4545d372b560df10fa47281ef0783a479ce435 ]

This patch fixes the incorrect external id that kernel reports to user mode
driver. Raven2's rev_id is starts from 0x8, so its external id (0x81) should
start from rev_id + 0x79 (0x81 - 0x8). And Raven's rev_id should be 0x21 while
rev_id == 1.

Reported-by: Crystal Jin 
Signed-off-by: Huang Rui 
Reviewed-by: Hawking Zhang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 4cc0dcb1a1875..825d1cae85abd 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -705,11 +705,13 @@ static int soc15_common_early_init(void *handle)
break;
case CHIP_RAVEN:
if (adev->rev_id >= 0x8)
-   adev->external_rev_id = adev->rev_id + 0x81;
+   adev->external_rev_id = adev->rev_id + 0x79;
else if (adev->pdev->device == 0x15d8)
adev->external_rev_id = adev->rev_id + 0x41;
+   else if (adev->rev_id == 1)
+   adev->external_rev_id = adev->rev_id + 0x20;
else
-   adev->external_rev_id = 0x1;
+   adev->external_rev_id = adev->rev_id + 0x01;
 
if (adev->rev_id >= 0x8) {
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
-- 
2.19.1

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[PATCH AUTOSEL 4.20 32/81] drm/amdgpu: Add missing power attribute to APU check

[Sasha Levin]

From: Alex Deucher 

[ Upstream commit dc14eb12f6bb3e779c5461429c1889a339c67aab ]

Add missing power_average to visible check for power
attributes for APUs.  Was missed before.

Reviewed-by: Evan Quan 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 59cc678de8c15..bbac15fd8caac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1671,7 +1671,8 @@ static umode_t hwmon_attributes_visible(struct kobject 
*kobj,
effective_mode &= ~S_IWUSR;
 
if ((adev->flags & AMD_IS_APU) &&
-   (attr == _dev_attr_power1_cap_max.dev_attr.attr ||
+   (attr == _dev_attr_power1_average.dev_attr.attr ||
+attr == _dev_attr_power1_cap_max.dev_attr.attr ||
 attr == _dev_attr_power1_cap_min.dev_attr.attr||
 attr == _dev_attr_power1_cap.dev_attr.attr))
return 0;
-- 
2.19.1

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[PATCH AUTOSEL 4.20 33/81] drm/radeon: check if device is root before getting pci speed caps

[Sasha Levin]

From: Alex Deucher 

[ Upstream commit afeff4c16edaa6275b903f82b0561406259aa3a3 ]

Check if the device is root rather before attempting to see what
speeds the pcie port supports.  Fixes a crash with pci passthrough
in a VM.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109366
Reviewed-by: Evan Quan 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/ci_dpm.c | 5 +++--
 drivers/gpu/drm/radeon/si_dpm.c | 5 +++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index d587779a80b4d..a97294ac96d59 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -5676,7 +5676,7 @@ int ci_dpm_init(struct radeon_device *rdev)
u16 data_offset, size;
u8 frev, crev;
struct ci_power_info *pi;
-   enum pci_bus_speed speed_cap;
+   enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN;
struct pci_dev *root = rdev->pdev->bus->self;
int ret;
 
@@ -5685,7 +5685,8 @@ int ci_dpm_init(struct radeon_device *rdev)
return -ENOMEM;
rdev->pm.dpm.priv = pi;
 
-   speed_cap = pcie_get_speed_cap(root);
+   if (!pci_is_root_bus(rdev->pdev->bus))
+   speed_cap = pcie_get_speed_cap(root);
if (speed_cap == PCI_SPEED_UNKNOWN) {
pi->sys_pcie_mask = 0;
} else {
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 8fb60b3af0158..0a785ef0ab660 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -6899,7 +6899,7 @@ int si_dpm_init(struct radeon_device *rdev)
struct ni_power_info *ni_pi;
struct si_power_info *si_pi;
struct atom_clock_dividers dividers;
-   enum pci_bus_speed speed_cap;
+   enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN;
struct pci_dev *root = rdev->pdev->bus->self;
int ret;
 
@@ -6911,7 +6911,8 @@ int si_dpm_init(struct radeon_device *rdev)
eg_pi = _pi->eg;
pi = _pi->rv7xx;
 
-   speed_cap = pcie_get_speed_cap(root);
+   if (!pci_is_root_bus(rdev->pdev->bus))
+   speed_cap = pcie_get_speed_cap(root);
if (speed_cap == PCI_SPEED_UNKNOWN) {
si_pi->sys_pcie_mask = 0;
} else {
-- 
2.19.1

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[PATCH AUTOSEL 4.20 37/81] drm/amdgpu: Transfer fences to dmabuf importer

[Sasha Levin]

From: Chris Wilson 

[ Upstream commit 6e11ea9de9576a644045ffdc2067c09bc2012eda ]

amdgpu only uses shared-fences internally, but dmabuf importers rely on
implicit write hazard tracking via the reservation_object.fence_excl.
For example, the importer use the write hazard for timing a page flip to
only occur after the exporter has finished flushing its write into the
surface. As such, on exporting a dmabuf, we must either flush all
outstanding fences (for we do not know which are writes and should have
been exclusive) or alternatively create a new exclusive fence that is
the composite of all the existing shared fences, and so will only be
signaled when all earlier fences are signaled (ensuring that we can not
be signaled before the completion of any earlier write).

v2: reservation_object is already locked by amdgpu_bo_reserve()
v3: Replace looping with get_fences_rcu and special case the promotion
of a single shared fence directly to an exclusive fence, bypassing the
fence array.
v4: Drop the fence array ref after assigning to reservation_object

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107341
Testcase: igt/amd_prime/amd-to-i915
References: 8e94a46c1770 ("drm/amdgpu: Attach exclusive fence to prime exported 
bo's. (v5)")
Signed-off-by: Chris Wilson 
Cc: Alex Deucher 
Cc: "Christian König" 
Reviewed-by: "Christian König" 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 59 ---
 1 file changed, 51 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index e45e929aaab5b..90a5970af4b7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -38,6 +38,7 @@
 #include "amdgpu_gem.h"
 #include 
 #include 
+#include 
 
 static const struct dma_buf_ops amdgpu_dmabuf_ops;
 
@@ -189,6 +190,48 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
return ERR_PTR(ret);
 }
 
+static int
+__reservation_object_make_exclusive(struct reservation_object *obj)
+{
+   struct dma_fence **fences;
+   unsigned int count;
+   int r;
+
+   if (!reservation_object_get_list(obj)) /* no shared fences to convert */
+   return 0;
+
+   r = reservation_object_get_fences_rcu(obj, NULL, , );
+   if (r)
+   return r;
+
+   if (count == 0) {
+   /* Now that was unexpected. */
+   } else if (count == 1) {
+   reservation_object_add_excl_fence(obj, fences[0]);
+   dma_fence_put(fences[0]);
+   kfree(fences);
+   } else {
+   struct dma_fence_array *array;
+
+   array = dma_fence_array_create(count, fences,
+  dma_fence_context_alloc(1), 0,
+  false);
+   if (!array)
+   goto err_fences_put;
+
+   reservation_object_add_excl_fence(obj, >base);
+   dma_fence_put(>base);
+   }
+
+   return 0;
+
+err_fences_put:
+   while (count--)
+   dma_fence_put(fences[count]);
+   kfree(fences);
+   return -ENOMEM;
+}
+
 /**
  * amdgpu_gem_map_attach - _buf_ops.attach implementation
  * @dma_buf: Shared DMA buffer
@@ -220,16 +263,16 @@ static int amdgpu_gem_map_attach(struct dma_buf *dma_buf,
 
if (attach->dev->driver != adev->dev->driver) {
/*
-* Wait for all shared fences to complete before we switch to 
future
-* use of exclusive fence on this prime shared bo.
+* We only create shared fences for internal use, but importers
+* of the dmabuf rely on exclusive fences for implicitly
+* tracking write hazards. As any of the current fences may
+* correspond to a write, we need to convert all existing
+* fences on the reservation object into a single exclusive
+* fence.
 */
-   r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
-   true, false,
-   MAX_SCHEDULE_TIMEOUT);
-   if (unlikely(r < 0)) {
-   DRM_DEBUG_PRIME("Fence wait failed: %li\n", r);
+   r = __reservation_object_make_exclusive(bo->tbo.resv);
+   if (r)
goto error_unreserve;
-   }
}
 
/* pin buffer into GTT */
-- 
2.19.1

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[PATCH] drm/amdgpu: Bump amdgpu version for per-flip plane tiling updates

[Nicholas Kazlauskas]

To help xf86-video-amdgpu and mesa know DC supports updating the
tiling attributes for a framebuffer per-flip.

Cc: Michel Dänzer 
Cc: Marek Olšák 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 223013ef8466..ae4e3eeb4ae2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -74,9 +74,10 @@
  * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
  * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
  * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
+ * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
  */
 #define KMS_DRIVER_MAJOR   3
-#define KMS_DRIVER_MINOR   30
+#define KMS_DRIVER_MINOR   31
 #define KMS_DRIVER_PATCHLEVEL  0
 
 int amdgpu_vram_limit = 0;
-- 
2.17.1

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Re: [PATCH xf86-video-amdgpu] Fix hang when entering into dpms-off mode

[Michel Dänzer]

Hi Aaron,


thanks for the patch. xf86-video-amdgpu now uses GitLab merge requests
for patch submission and review:

https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu/merge_requests

That said, comments on the patch below:


On 2019-02-28 3:52 a.m., Aaron Liu wrote:
> The hang happened in CTS 4.6 glcts. It is dued to inconsistent process
> in amdgpu_dri2_schedule_swap when system entering into dpms-off mode.
> 
> Normally, drmmode_wait_vblank will be excuted. But when entering into
> dpms-off mode, drmmode_wait_vblank can't be excuted and fallback to
> amdgpu_dri2_schedule_event to process.
> Finally in amdgpu_dri2_deferred_event, vblank_handler will be excuted.
> It is the root cause of hang. Instead of vblank_handler, it just use
> amdgpu_dri2_frame_event_handler to process under dpms-off mode.
> 
> Change-Id: I6bfed9692fc02c8c3c86df2a816884c4a1f46cb1
> Signed-off-by: Aaron Liu 
> ---
>  src/amdgpu_dri2.c | 9 +++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/src/amdgpu_dri2.c b/src/amdgpu_dri2.c
> index a6b76a1..c54ad0c 100644
> --- a/src/amdgpu_dri2.c
> +++ b/src/amdgpu_dri2.c
> @@ -884,7 +884,7 @@ CARD32 amdgpu_dri2_deferred_event(OsTimerPtr timer, 
> CARD32 now, pointer data)
>   if (ret) {
>   xf86DrvMsg(scrn->scrnIndex, X_ERROR,
>  "%s cannot get current time\n", __func__);
> - if (event_info->drm_queue_seq)
> + if (event_info->drm_queue_seq && amdgpu_crtc_is_enabled(crtc))
>   drmmode_crtc->drmmode->event_context.
>   vblank_handler(pAMDGPUEnt->fd, 0, 0, 0,
>  
> (void*)event_info->drm_queue_seq);
> @@ -900,7 +900,12 @@ CARD32 amdgpu_dri2_deferred_event(OsTimerPtr timer, 
> CARD32 now, pointer data)
>   delta_seq = delta_t * drmmode_crtc->dpms_last_fps;
>   delta_seq /= 100;
>   frame = (CARD64) drmmode_crtc->dpms_last_seq + delta_seq;
> - if (event_info->drm_queue_seq)
> + /*
> +  * If CRTC is in DPMS off state, it can't use vblank_handler.
> +  * Because drmmode_wait_vblank is not excuted in such as
> +  * amdgpu_dri2_schedule_swap/amdgpu_dri2_schedule_wait_msc.
> +  */
> + if (event_info->drm_queue_seq && amdgpu_crtc_is_enabled(crtc))
>   drmmode_crtc->drmmode->event_context.
>   vblank_handler(pAMDGPUEnt->fd, frame, drm_now / 100,
>  drm_now % 100,
> 

This isn't a good solution I'm afraid, as it'll leave the struct
amdgpu_drm_queue_entry memory associated with event_info->drm_queue_seq
linked into the amdgpu_drm_queue list, which would gradually slow down
processing of that list.


I think I know what the issue is, I'll work on a fix in the afternoon.


-- 
Earthling Michel Dänzer   |  https://www.amd.com
Libre software enthusiast | Mesa and X developer
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Compiler warnings from RAS code

[Michel Dänzer]

It's pretty noisy:

In file included from ./include/linux/list.h:9,
 from ./include/linux/agp_backend.h:33,
 from ./include/drm/drmP.h:35,
 from drivers/gpu/drm//amd/amdgpu/amdgpu_kms.c:28:
drivers/gpu/drm//amd/amdgpu/amdgpu_kms.c: In function ‘amdgpu_info_ioctl’:
./include/linux/kernel.h:846:29: warning: comparison of distinct pointer
types lacks a cast
   (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
 ^~
./include/linux/kernel.h:860:4: note: in expansion of macro ‘__typecheck’
   (__typecheck(x, y) && __no_side_effects(x, y))
^~~
./include/linux/kernel.h:870:24: note: in expansion of macro ‘__safe_cmp’
  __builtin_choose_expr(__safe_cmp(x, y), \
^~
./include/linux/kernel.h:879:19: note: in expansion of macro ‘__careful_cmp’
 #define min(x, y) __careful_cmp(x, y, <)
   ^
drivers/gpu/drm//amd/amdgpu/amdgpu_kms.c:930:5: note: in expansion of
macro ‘min’
 min(size, sizeof(ras->features))) ? -EFAULT : 0;
 ^~~
[...]
drivers/gpu/drm//amd/amdgpu/amdgpu_psp.c: In function ‘psp_ras_initialize’:
drivers/gpu/drm//amd/amdgpu/amdgpu_psp.c:657:31: warning: unused
variable ‘ras_cmd’ [-Wunused-variable]
  struct ta_ras_shared_memory *ras_cmd;
   ^~~
[...]
drivers/gpu/drm//amd/amdgpu/psp_v11_0.c: In function
‘psp_v11_0_init_microcode’:
drivers/gpu/drm//amd/amdgpu/psp_v11_0.c:123:21: warning: ‘ta_hdr’ may be
used uninitialized in this function [-Wmaybe-uninitialized]
   le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
 ^~
[...]
drivers/gpu/drm//amd/amdgpu/gfx_v9_0.c: In function
‘gfx_v9_0_cp_ecc_error_irq’:
drivers/gpu/drm//amd/amdgpu/gfx_v9_0.c:4817:2: warning: ISO C90 forbids
mixed declarations and code [-Wdeclaration-after-statement]
  struct ras_dispatch_if ih_data = {
  ^~
[...]
In file included from ./include/linux/list.h:9,
 from ./include/linux/wait.h:7,
 from ./include/linux/wait_bit.h:8,
 from ./include/linux/fs.h:6,
 from ./include/linux/debugfs.h:15,
 from drivers/gpu/drm//amd/amdgpu/amdgpu_ras.c:24:
drivers/gpu/drm//amd/amdgpu/amdgpu_ras.c: In function
‘amdgpu_ras_debugfs_read’:
./include/linux/kernel.h:846:29: warning: comparison of distinct pointer
types lacks a cast
   (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
 ^~
./include/linux/kernel.h:860:4: note: in expansion of macro ‘__typecheck’
   (__typecheck(x, y) && __no_side_effects(x, y))
^~~
./include/linux/kernel.h:870:24: note: in expansion of macro ‘__safe_cmp’
  __builtin_choose_expr(__safe_cmp(x, y), \
^~
./include/linux/kernel.h:879:19: note: in expansion of macro ‘__careful_cmp’
 #define min(x, y) __careful_cmp(x, y, <)
   ^
drivers/gpu/drm//amd/amdgpu/amdgpu_ras.c:145:6: note: in expansion of
macro ‘min’
  s = min(s, size);
  ^~~
drivers/gpu/drm//amd/amdgpu/amdgpu_ras.c: In function
‘amdgpu_ras_debugfs_write’:
./include/linux/kernel.h:846:29: warning: comparison of distinct pointer
types lacks a cast
   (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
 ^~
./include/linux/kernel.h:860:4: note: in expansion of macro ‘__typecheck’
   (__typecheck(x, y) && __no_side_effects(x, y))
^~~
./include/linux/kernel.h:870:24: note: in expansion of macro ‘__safe_cmp’
  __builtin_choose_expr(__safe_cmp(x, y), \
^~
./include/linux/kernel.h:879:19: note: in expansion of macro ‘__careful_cmp’
 #define min(x, y) __careful_cmp(x, y, <)
   ^
drivers/gpu/drm//amd/amdgpu/amdgpu_ras.c:162:14: note: in expansion of
macro ‘min’
  ssize_t s = min(64ULL, size);
  ^~~



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Libre software enthusiast | Mesa and X developer
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Re: KASAN caught amdgpu / HMM use-after-free

[Michel Dänzer]

[ Dropping Jérôme and the linux-mm list ]

On 2019-02-27 7:48 p.m., Yang, Philip wrote:
> Hi Alex,
> 
> Pushed, thanks.
> 
> mm/hmm: use reference counting for HMM struct

Thanks, but I'm not seeing it yet. Maybe it needs some special
treatment, because it's not a DRM code change?


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RE: [PATCH 1/2] drm/amd/powerplay: correct power reading on fiji

[Xu, Feifei]

Reviewed-by: Feifei Xu 

-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Thursday, February 28, 2019 6:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH 1/2] drm/amd/powerplay: correct power reading on fiji

Set sampling period as 500ms to provide a smooth power reading output. Also, 
correct the register for power reading.

Change-Id: I13935f3e7fcd026d34aa6a68cf7f683dc6785ab7
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 48187acac59e..83d3d935f3ac 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3491,14 +3491,14 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, 
u32 *query)
 
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-   ixSMU_PM_STATUS_94, 0);
+   ixSMU_PM_STATUS_95, 0);
 
for (i = 0; i < 10; i++) {
-   mdelay(1);
+   mdelay(500);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
tmp = cgs_read_ind_register(hwmgr->device,
CGS_IND_REG__SMC,
-   ixSMU_PM_STATUS_94);
+   ixSMU_PM_STATUS_95);
if (tmp != 0)
break;
}
--
2.21.0

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RE: [PATCH 2/2] drm/amd/powerplay: override duty cycle on Vega20

[Xu, Feifei]

Ackced-by: Feifei Xu 

-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Thursday, February 28, 2019 6:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH 2/2] drm/amd/powerplay: override duty cycle on Vega20

This is needed for the new SMC firmwares only.

Change-Id: I5934e5161ec53c1dd73cb1542ef6b738ad2e620c
Signed-off-by: Evan Quan 
---
 .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c   | 16 
 drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h |  3 ++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 9aa7bec1b5fe..d35f60ab3404 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -828,6 +828,17 @@ static int vega20_override_pcie_parameters(struct pp_hwmgr 
*hwmgr)
return 0;
 }
 
+static int vega20_override_duty_cycle(struct pp_hwmgr *hwmgr) {
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   int ret = 0;
+
+   if (adev->pm.fw_version >= 0x00282700)
+   ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_OverrideDutyCycle);
+
+   return ret;
+}
+
 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)  {
struct vega20_hwmgr *data =
@@ -1644,6 +1655,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr 
*hwmgr)
"[EnableDPMTasks] Failed to enable all smu features!",
return result);
 
+   result = vega20_override_duty_cycle(hwmgr);
+   PP_ASSERT_WITH_CODE(!result,
+   "[EnableDPMTasks] Failed to override duty cycle!",
+   return result);
+
result = vega20_override_pcie_parameters(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"[EnableDPMTasks] Failed to override pcie parameters!", 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h 
b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
index 4f63a736ea0e..4a1e01f04cf5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
@@ -119,7 +119,8 @@
 #define PPSMC_MSG_PrepareMp1ForShutdown  0x5A
 #define PPSMC_MSG_SetMGpuFanBoostLimitRpm0x5D
 #define PPSMC_MSG_GetAVFSVoltageByDpm0x5F
-#define PPSMC_Message_Count  0x60
+#define PPSMC_MSG_OverrideDutyCycle  0x64
+#define PPSMC_Message_Count  0x65
 
 typedef uint32_t PPSMC_Result;
 typedef uint32_t PPSMC_Msg;
--
2.21.0

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[PATCH 2/2] drm/amd/powerplay: override duty cycle on Vega20

[Evan Quan]

This is needed for the new SMC firmwares only.

Change-Id: I5934e5161ec53c1dd73cb1542ef6b738ad2e620c
Signed-off-by: Evan Quan 
---
 .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c   | 16 
 drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h |  3 ++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 9aa7bec1b5fe..d35f60ab3404 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -828,6 +828,17 @@ static int vega20_override_pcie_parameters(struct pp_hwmgr 
*hwmgr)
return 0;
 }
 
+static int vega20_override_duty_cycle(struct pp_hwmgr *hwmgr)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   int ret = 0;
+
+   if (adev->pm.fw_version >= 0x00282700)
+   ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_OverrideDutyCycle);
+
+   return ret;
+}
+
 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 {
struct vega20_hwmgr *data =
@@ -1644,6 +1655,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr 
*hwmgr)
"[EnableDPMTasks] Failed to enable all smu features!",
return result);
 
+   result = vega20_override_duty_cycle(hwmgr);
+   PP_ASSERT_WITH_CODE(!result,
+   "[EnableDPMTasks] Failed to override duty cycle!",
+   return result);
+
result = vega20_override_pcie_parameters(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"[EnableDPMTasks] Failed to override pcie parameters!",
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h 
b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
index 4f63a736ea0e..4a1e01f04cf5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
@@ -119,7 +119,8 @@
 #define PPSMC_MSG_PrepareMp1ForShutdown  0x5A
 #define PPSMC_MSG_SetMGpuFanBoostLimitRpm0x5D
 #define PPSMC_MSG_GetAVFSVoltageByDpm0x5F
-#define PPSMC_Message_Count  0x60
+#define PPSMC_MSG_OverrideDutyCycle  0x64
+#define PPSMC_Message_Count  0x65
 
 typedef uint32_t PPSMC_Result;
 typedef uint32_t PPSMC_Msg;
-- 
2.21.0

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[PATCH 1/2] drm/amd/powerplay: correct power reading on fiji

[Evan Quan]

Set sampling period as 500ms to provide a smooth power
reading output. Also, correct the register for power
reading.

Change-Id: I13935f3e7fcd026d34aa6a68cf7f683dc6785ab7
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 48187acac59e..83d3d935f3ac 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3491,14 +3491,14 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, 
u32 *query)
 
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-   ixSMU_PM_STATUS_94, 0);
+   ixSMU_PM_STATUS_95, 0);
 
for (i = 0; i < 10; i++) {
-   mdelay(1);
+   mdelay(500);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
tmp = cgs_read_ind_register(hwmgr->device,
CGS_IND_REG__SMC,
-   ixSMU_PM_STATUS_94);
+   ixSMU_PM_STATUS_95);
if (tmp != 0)
break;
}
-- 
2.21.0

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RE: [PATCH libdrm 2/2] tests/amdgpu: add memcpy dispatch test

[Zhang, Hawking]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Cui, Flora
Sent: 2019年2月28日 13:44
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Cui, Flora 
Subject: [PATCH libdrm 2/2] tests/amdgpu: add memcpy dispatch test

add memcpy dispatch test for gfx9

Change-Id: If433434c5378f3b318209d4e28c19d7ce9cff1a2
Signed-off-by: Flora Cui 
Tested-by: Rui Teng 
---
 tests/amdgpu/basic_tests.c | 129 +
 1 file changed, 129 insertions(+)

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 
d4b0faf..9d2cc95 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -305,6 +305,11 @@ static const uint32_t 
bufferclear_cs_shader_registers_gfx9[][2] = {
 
 static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
 
+static const uint32_t buffercopy_cs_shader_gfx9[] = {
+0xD1FD, 0x04010C08, 0xE00C2000, 0x8100,
+0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF81 };
+
 int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
unsigned alignment, unsigned heap, uint64_t alloc_flags,
uint64_t mapping_flags, amdgpu_bo_handle *bo, void 
**cpu, @@ -2084,6 +2089,128 @@ static void amdgpu_memset_dispatch_test(uint32_t 
ip_type)
 
r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, 
bo_shader_size);
CU_ASSERT_EQUAL(r, 0);
+
+   r = amdgpu_cs_ctx_free(context_handle);
+   CU_ASSERT_EQUAL(r, 0);
+}
+
+static void amdgpu_memcpy_dispatch_test(uint32_t ip_type) {
+   amdgpu_context_handle context_handle;
+   amdgpu_bo_handle bo_src, bo_dst, bo_shader, resources[3];
+   volatile unsigned char *ptr_dst;
+   void *ptr_shader;
+   void *ptr_src;
+   uint64_t mc_address_src, mc_address_dst, mc_address_shader;
+   amdgpu_va_handle va_src, va_dst, va_shader;
+   int i, j, r;
+   uint32_t *ptr;
+   int bo_dst_size = 16384;
+   int bo_shader_size = 4096;
+   struct amdgpu_cs_request ibs_request = {0};
+   struct amdgpu_cs_ib_info ib_info= {0};
+   uint32_t version, ring_id;
+   struct drm_amdgpu_info_hw_ip info;
+
+   r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, );
+   CU_ASSERT_EQUAL(r, 0);
+
+   version = info.hw_ip_version_major;
+   if (version != 9) {
+   printf("\tSkip...memcpy dispatch test is only supported with 
gfx9\n");
+   return;
+   }
+
+   ptr = calloc(256, sizeof(*ptr));
+   CU_ASSERT_NOT_EQUAL(ptr, NULL);
+
+   r = amdgpu_cs_ctx_create(device_handle, _handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
+   AMDGPU_GEM_DOMAIN_VRAM, 0,
+   _shader, _shader,
+   _address_shader, _shader);
+   CU_ASSERT_EQUAL(r, 0);
+
+   memcpy(ptr_shader, buffercopy_cs_shader_gfx9, 
+sizeof(buffercopy_cs_shader_gfx9));
+
+   for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
+   r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+   AMDGPU_GEM_DOMAIN_VRAM, 0,
+   _src, _src,
+   _address_src, _src);
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+   AMDGPU_GEM_DOMAIN_VRAM, 0,
+   _dst, _dst,
+   _address_dst, _dst);
+   CU_ASSERT_EQUAL(r, 0);
+
+   memset(ptr_src, 0x55, bo_dst_size);
+
+   i = 0;
+   i += amdgpu_dispatch_init(ip_type, version, ptr + i);
+
+   /*  Issue commands to set cu mask used in current dispatch */
+   i += amdgpu_dispatch_write_cumask(ip_type, version, ptr + i);
+
+   /* Writes shader state to HW */
+   i += amdgpu_dispatch_write2hw(ip_type, version, ptr + i, 
+mc_address_shader);
+
+   /* Write constant data */
+   /* Writes the texture resource constants data to the SGPRs */
+   ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
+   ptr[i++] = 0x240;
+   ptr[i++] = mc_address_src;
+   ptr[i++] = (mc_address_src > 32) | 0x10;
+   ptr[i++] = 0x400;
+   ptr[i++] = 0x74fac;
+   /* Writes the UAV constant data to the SGPRs. */
+   ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
+   ptr[i++] = 0x244;
+   ptr[i++] = mc_address_dst;
+   ptr[i++] = (mc_address_dst > 32) | 0x10;
+   ptr[i++] = 0x400;
+