RE: [PATCH] drm/amdgpu: fix ras parameter descriptions

[Pan, Xinhui]

Looks good to me.
Thanks.

-Original Message-
From: Evan Quan  
Sent: 2019年3月7日 15:01
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Pan, Xinhui ; 
Deucher, Alexander ; Quan, Evan 
Subject: [PATCH] drm/amdgpu: fix ras parameter descriptions

The descriptions of modinfo wrongly show two parameters for each feature(see 
below). This patch can fix this incorrect outputs.

parm:   amdgpu_ras_enable:Enable RAS features on the GPU (0 = disable, 
1 = enable, -1 = auto (default))
parm:   ras_enable:int
parm:   amdgpu_ras_mask:Mask of RAS features to enable (default 
0x), only valid when ras_enable == 1
parm:   ras_mask:uint

Change-Id: I04f7e505cecca991f196802befd2006dc49b3dcf
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 38dbf6115c15..e0a7712d5d7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -512,18 +512,18 @@ MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 
0 = disable)");  module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
 
 /*
- * DOC: amdgpu_ras_enable (int)
+ * DOC: ras_enable (int)
  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto 
(default))
  */
-MODULE_PARM_DESC(amdgpu_ras_enable, "Enable RAS features on the GPU (0 = 
disable, 1 = enable, -1 = auto (default))");
+MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = 
+disable, 1 = enable, -1 = auto (default))");
 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
 
 /**
- * DOC: amdgpu_ras_mask (uint)
+ * DOC: ras_mask (uint)
  * Mask of RAS features to enable (default 0x), only valid when 
ras_enable == 1
  * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
  */
-MODULE_PARM_DESC(amdgpu_ras_mask, "Mask of RAS features to enable (default 
0x), only valid when ras_enable == 1");
+MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 
+0x), only valid when ras_enable == 1");
 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
 
 
--
2.21.0

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[PATCH] drm/amdgpu: fix ras parameter descriptions

[Evan Quan]

The descriptions of modinfo wrongly show two parameters
for each feature(see below). This patch can fix this
incorrect outputs.

parm:   amdgpu_ras_enable:Enable RAS features on the GPU (0 = disable, 
1 = enable, -1 = auto (default))
parm:   ras_enable:int
parm:   amdgpu_ras_mask:Mask of RAS features to enable (default 
0x), only valid when ras_enable == 1
parm:   ras_mask:uint

Change-Id: I04f7e505cecca991f196802befd2006dc49b3dcf
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 38dbf6115c15..e0a7712d5d7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -512,18 +512,18 @@ MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 
0 = disable)");
 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
 
 /*
- * DOC: amdgpu_ras_enable (int)
+ * DOC: ras_enable (int)
  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto 
(default))
  */
-MODULE_PARM_DESC(amdgpu_ras_enable, "Enable RAS features on the GPU (0 = 
disable, 1 = enable, -1 = auto (default))");
+MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = 
enable, -1 = auto (default))");
 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
 
 /**
- * DOC: amdgpu_ras_mask (uint)
+ * DOC: ras_mask (uint)
  * Mask of RAS features to enable (default 0x), only valid when 
ras_enable == 1
  * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
  */
-MODULE_PARM_DESC(amdgpu_ras_mask, "Mask of RAS features to enable (default 
0x), only valid when ras_enable == 1");
+MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 
0x), only valid when ras_enable == 1");
 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
 
 
-- 
2.21.0

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RE: [PATCH] drm/amdgpu: handle ras resume

[Zhang, Hawking]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Pan, Xinhui  
Sent: 2019年3月7日 11:35
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ; 
Deucher, Alexander 
Subject: [PATCH] drm/amdgpu: handle ras resume

Suspend will put irq, so resume need get irq back.
And in the same time, skip other ras initialization.

Signed-off-by: xinhui pan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 5 -  
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 5 -  
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +-
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dcdd53a701bf..3fb72bf420e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3553,6 +3553,9 @@ static int gfx_v9_0_ecc_late_init(void *handle)
return 0;
}
 
+   if (*ras_if)
+   goto resume;
+
*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
if (!*ras_if)
return -ENOMEM;
@@ -3577,7 +3580,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
r = amdgpu_ras_sysfs_create(adev, _info);
if (r)
goto sysfs;
-
+resume:
r = amdgpu_irq_get(adev, >gfx.cp_ecc_error_irq, 0);
if (r)
goto irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 84904bd680df..df05563babfd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -927,6 +927,9 @@ static int gmc_v9_0_ecc_late_init(void *handle)
amdgpu_ras_feature_enable(adev, _block, 0);
return 0;
}
+   /* handle resume path. */
+   if (*ras_if)
+   goto resume;
 
*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
if (!*ras_if)
@@ -952,7 +955,7 @@ static int gmc_v9_0_ecc_late_init(void *handle)
r = amdgpu_ras_sysfs_create(adev, _info);
if (r)
goto sysfs;
-
+resume:
r = amdgpu_irq_get(adev, >gmc.ecc_irq, 0);
if (r)
goto irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 84db1f4725f7..3ac5abe937f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1522,6 +1522,10 @@ static int sdma_v4_0_late_init(void *handle)
return 0;
}
 
+   /* handle resume path. */
+   if (*ras_if)
+   goto resume;
+
*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
if (!*ras_if)
return -ENOMEM;
@@ -1546,7 +1550,7 @@ static int sdma_v4_0_late_init(void *handle)
r = amdgpu_ras_sysfs_create(adev, _info);
if (r)
goto sysfs;
-
+resume:
r = amdgpu_irq_get(adev, >sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
if (r)
goto irq;
--
2.17.1

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[PATCH] drm/amdgpu: handle ras resume

[Pan, Xinhui]

Suspend will put irq, so resume need get irq back.
And in the same time, skip other ras initialization.

Signed-off-by: xinhui pan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 5 -
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 5 -
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +-
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dcdd53a701bf..3fb72bf420e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3553,6 +3553,9 @@ static int gfx_v9_0_ecc_late_init(void *handle)
return 0;
}
 
+   if (*ras_if)
+   goto resume;
+
*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
if (!*ras_if)
return -ENOMEM;
@@ -3577,7 +3580,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
r = amdgpu_ras_sysfs_create(adev, _info);
if (r)
goto sysfs;
-
+resume:
r = amdgpu_irq_get(adev, >gfx.cp_ecc_error_irq, 0);
if (r)
goto irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 84904bd680df..df05563babfd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -927,6 +927,9 @@ static int gmc_v9_0_ecc_late_init(void *handle)
amdgpu_ras_feature_enable(adev, _block, 0);
return 0;
}
+   /* handle resume path. */
+   if (*ras_if)
+   goto resume;
 
*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
if (!*ras_if)
@@ -952,7 +955,7 @@ static int gmc_v9_0_ecc_late_init(void *handle)
r = amdgpu_ras_sysfs_create(adev, _info);
if (r)
goto sysfs;
-
+resume:
r = amdgpu_irq_get(adev, >gmc.ecc_irq, 0);
if (r)
goto irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 84db1f4725f7..3ac5abe937f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1522,6 +1522,10 @@ static int sdma_v4_0_late_init(void *handle)
return 0;
}
 
+   /* handle resume path. */
+   if (*ras_if)
+   goto resume;
+
*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
if (!*ras_if)
return -ENOMEM;
@@ -1546,7 +1550,7 @@ static int sdma_v4_0_late_init(void *handle)
r = amdgpu_ras_sysfs_create(adev, _info);
if (r)
goto sysfs;
-
+resume:
r = amdgpu_irq_get(adev, >sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
if (r)
goto irq;
-- 
2.17.1

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RE: [PATCH] drm/amd/powerplay: apply Vega20 BACO workaround

[Quan, Evan]

Not now. There is still some issue to work out. I just added you to that thread.

Regards,
Evan
> -Original Message-
> From: Alex Deucher 
> Sent: Thursday, March 07, 2019 10:46 AM
> To: Quan, Evan 
> Cc: amd-gfx list ; Xu, Feifei
> ; Zhang, Hawking 
> Subject: Re: [PATCH] drm/amd/powerplay: apply Vega20 BACO workaround
> 
> On Wed, Mar 6, 2019 at 9:38 PM Evan Quan  wrote:
> >
> > Applied vdci flush workaround for Vega20 BACO.
> >
> > Change-Id: Ia132ae30f826643bfba980402a92fbd0ae7a4236
> > Signed-off-by: Evan Quan 
> 
> Acked-by: Alex Deucher 
> 
> Can we re-enable BACO with this fix?
> 
> Alex
> 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
> >  drivers/gpu/drm/amd/amdgpu/soc15.c|  2 ++
> >  .../gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 12 +++
> > .../gpu/drm/amd/powerplay/hwmgr/vega20_baco.h |  1 +
> >  .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 11 +-
> >  .../gpu/drm/amd/powerplay/inc/vega20_ppsmc.h  |  3 ++-
> > .../drm/amd/powerplay/smumgr/vega20_smumgr.c  | 20
> +++
> > .../drm/amd/powerplay/smumgr/vega20_smumgr.h  |  1 +
> >  8 files changed, 49 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 876486595d89..fe0f5653805b 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -981,6 +981,7 @@ struct amdgpu_device {
> >
> > int asic_reset_res;
> > struct work_struct  xgmi_reset_work;
> > +   boolin_baco_reset;
> >  };
> >
> >  static inline struct amdgpu_device *amdgpu_ttm_adev(struct
> > ttm_bo_device *bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index cc80f050cbf6..75a408a216b9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -452,6 +452,8 @@ static int soc15_asic_baco_reset(struct
> > amdgpu_device *adev)
> >
> > dev_info(adev->dev, "GPU BACO reset\n");
> >
> > +   adev->in_baco_reset = 1;
> > +
> > return 0;
> >  }
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
> > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
> > index 5e8602a79b1c..df6ff9252401 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
> > @@ -27,6 +27,7 @@
> >  #include "vega20_inc.h"
> >  #include "vega20_ppsmc.h"
> >  #include "vega20_baco.h"
> > +#include "vega20_smumgr.h"
> >
> >
> >
> > @@ -101,3 +102,14 @@ int vega20_baco_set_state(struct pp_hwmgr
> *hwmgr,
> > enum BACO_STATE state)
> >
> > return 0;
> >  }
> > +
> > +int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr
> *hwmgr) {
> > +   int ret = 0;
> > +
> > +   ret = vega20_set_pptable_driver_address(hwmgr);
> > +   if (ret)
> > +   return ret;
> > +
> > +   return smum_send_msg_to_smc(hwmgr,
> > +PPSMC_MSG_BacoWorkAroundFlushVDCI);
> > +}
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
> > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
> > index 51c7f8392925..f06471e712dc 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
> > @@ -28,5 +28,6 @@
> >  extern int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool
> > *cap);  extern int vega20_baco_get_state(struct pp_hwmgr *hwmgr,
> enum
> > BACO_STATE *state);  extern int vega20_baco_set_state(struct pp_hwmgr
> > *hwmgr, enum BACO_STATE state);
> > +extern int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr
> > +*hwmgr);
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> > index 9aa7bec1b5fe..664544e7fcdc 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> > @@ -443,6 +443,7 @@ static int vega20_init_sclk_threshold(struct
> > pp_hwmgr *hwmgr)
> >
> >  static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)  {
> > +   struct amdgpu_device *adev = (struct amdgpu_device
> > + *)(hwmgr->adev);
> > int ret = 0;
> >
> > ret = vega20_init_sclk_threshold(hwmgr);
> > @@ -450,7 +451,15 @@ static int vega20_setup_asic_task(struct
> pp_hwmgr *hwmgr)
> > "Failed to init sclk threshold!",
> > return ret);
> >
> > -   return 0;
> > +   if (adev->in_baco_reset) {
> > +   adev->in_baco_reset = 0;
> > +
> > +   ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
> > +   if (ret)
> > +   pr_err("Failed to apply vega20 baco workaround!\n");
> > +   }
> > +
> > +   return ret;
> >  }
> >
> >  /*
> > diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> > 

[PATCH] remove amdgpu_vrr_atom

[Cui, Flora]

it doesn't work as expected

Change-Id: I21c4a5251105f8293686a5d6331b7c23e02854e9
Signed-off-by: Flora Cui 
---
 src/amdgpu_kms.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
index 74d5806..54d7e9e 100644
--- a/src/amdgpu_kms.c
+++ b/src/amdgpu_kms.c
@@ -66,7 +66,6 @@ static DevPrivateKeyRec amdgpu_window_private_key;
 static DevScreenPrivateKeyRec amdgpu_client_private_key;
 DevScreenPrivateKeyRec amdgpu_device_private_key;
 
-static Atom amdgpu_vrr_atom;
 static Bool amdgpu_property_vectors_wrapped;
 static Bool restore_property_vector;
 static int (*saved_change_property) (ClientPtr client);
@@ -136,7 +135,7 @@ amdgpu_change_property(ClientPtr client)
if (ret != Success)
return ret;
 
-   if (stuff->property == amdgpu_vrr_atom &&
+   if (!strcmp(NameForAtom(stuff->property), "_VARIABLE_REFRESH") &&
xf86ScreenToScrn(window->drawable.pScreen)->PreInit ==
AMDGPUPreInit_KMS && stuff->format == 32 && stuff->nUnits == 1) {
uint32_t *value = (uint32_t*)(stuff + 1);
@@ -171,7 +170,7 @@ amdgpu_delete_property(ClientPtr client)
if (ret != Success)
return ret;
 
-   if (stuff->property == amdgpu_vrr_atom &&
+   if (!strcmp(NameForAtom(stuff->property), "_VARIABLE_REFRESH") &&
xf86ScreenToScrn(window->drawable.pScreen)->PreInit ==
AMDGPUPreInit_KMS)
amdgpu_vrr_property_update(window, FALSE);
@@ -2187,9 +2186,6 @@ Bool AMDGPUScreenInit_KMS(ScreenPtr pScreen, int argc, 
char **argv)
ProcVector[X_DeleteProperty] = amdgpu_delete_property;
amdgpu_property_vectors_wrapped = TRUE;
}
-
-   amdgpu_vrr_atom = MakeAtom("_VARIABLE_REFRESH",
-  strlen("_VARIABLE_REFRESH"), TRUE);
}
 
drmmode_init(pScrn, >drmmode);
-- 
2.7.4

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Re: [PATCH] drm/amd/powerplay: apply Vega20 BACO workaround

[Alex Deucher]

On Wed, Mar 6, 2019 at 9:38 PM Evan Quan  wrote:
>
> Applied vdci flush workaround for Vega20 BACO.
>
> Change-Id: Ia132ae30f826643bfba980402a92fbd0ae7a4236
> Signed-off-by: Evan Quan 

Acked-by: Alex Deucher 

Can we re-enable BACO with this fix?

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
>  drivers/gpu/drm/amd/amdgpu/soc15.c|  2 ++
>  .../gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 12 +++
>  .../gpu/drm/amd/powerplay/hwmgr/vega20_baco.h |  1 +
>  .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 11 +-
>  .../gpu/drm/amd/powerplay/inc/vega20_ppsmc.h  |  3 ++-
>  .../drm/amd/powerplay/smumgr/vega20_smumgr.c  | 20 +++
>  .../drm/amd/powerplay/smumgr/vega20_smumgr.h  |  1 +
>  8 files changed, 49 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 876486595d89..fe0f5653805b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -981,6 +981,7 @@ struct amdgpu_device {
>
> int asic_reset_res;
> struct work_struct  xgmi_reset_work;
> +   boolin_baco_reset;
>  };
>
>  static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device 
> *bdev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index cc80f050cbf6..75a408a216b9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -452,6 +452,8 @@ static int soc15_asic_baco_reset(struct amdgpu_device 
> *adev)
>
> dev_info(adev->dev, "GPU BACO reset\n");
>
> +   adev->in_baco_reset = 1;
> +
> return 0;
>  }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
> index 5e8602a79b1c..df6ff9252401 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
> @@ -27,6 +27,7 @@
>  #include "vega20_inc.h"
>  #include "vega20_ppsmc.h"
>  #include "vega20_baco.h"
> +#include "vega20_smumgr.h"
>
>
>
> @@ -101,3 +102,14 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum 
> BACO_STATE state)
>
> return 0;
>  }
> +
> +int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr)
> +{
> +   int ret = 0;
> +
> +   ret = vega20_set_pptable_driver_address(hwmgr);
> +   if (ret)
> +   return ret;
> +
> +   return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI);
> +}
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
> index 51c7f8392925..f06471e712dc 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
> @@ -28,5 +28,6 @@
>  extern int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
>  extern int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE 
> *state);
>  extern int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE 
> state);
> +extern int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr);
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index 9aa7bec1b5fe..664544e7fcdc 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -443,6 +443,7 @@ static int vega20_init_sclk_threshold(struct pp_hwmgr 
> *hwmgr)
>
>  static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
>  {
> +   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
> int ret = 0;
>
> ret = vega20_init_sclk_threshold(hwmgr);
> @@ -450,7 +451,15 @@ static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
> "Failed to init sclk threshold!",
> return ret);
>
> -   return 0;
> +   if (adev->in_baco_reset) {
> +   adev->in_baco_reset = 0;
> +
> +   ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
> +   if (ret)
> +   pr_err("Failed to apply vega20 baco workaround!\n");
> +   }
> +
> +   return ret;
>  }
>
>  /*
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h 
> b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> index 4f63a736ea0e..a0883038f3c3 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> @@ -119,7 +119,8 @@
>  #define PPSMC_MSG_PrepareMp1ForShutdown  0x5A
>  #define PPSMC_MSG_SetMGpuFanBoostLimitRpm0x5D
>  #define PPSMC_MSG_GetAVFSVoltageByDpm0x5F
> -#define PPSMC_Message_Count  0x60
> +#define PPSMC_MSG_BacoWorkAroundFlushVDCI0x60
> +#define PPSMC_Message_Count  0x61
>
>  typedef uint32_t 

[PATCH 2/3] drm/amdgpu: support userptr cross VMAs case with HMM v2

[Yang, Philip]

userptr may cross two VMAs if the forked child process (not call exec
after fork) malloc buffer, then free it, and then malloc larger size
buf, kerenl will create new VMA adjacent to old VMA which was cloned
from parent process, some pages of userptr are in the first VMA, the
rest pages are in the second VMA.

HMM expects range only have one VMA, loop over all VMAs in the address
range, create multiple ranges to handle this case. See
is_mergeable_anon_vma in mm/mmap.c for details.

Change-Id: I0ca8c77e28deabccc139906f9ffee04b7e383314
Signed-off-by: Philip Yang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 123 +---
 1 file changed, 88 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 7cc0ba24369d..802bec7ef917 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -711,7 +711,8 @@ struct amdgpu_ttm_tt {
struct task_struct  *usertask;
uint32_tuserflags;
 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
-   struct hmm_rangerange;
+   struct hmm_range*ranges;
+   int nr_ranges;
 #endif
 };
 
@@ -723,62 +724,105 @@ struct amdgpu_ttm_tt {
  * once afterwards to stop HMM tracking
  */
 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
+
+/* Support Userptr pages cross max 16 vmas */
+#define MAX_NR_VMAS(16)
+
 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 {
struct amdgpu_ttm_tt *gtt = (void *)ttm;
struct mm_struct *mm = gtt->usertask->mm;
-   unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
-   struct hmm_range *range = >range;
-   int r = 0, i;
+   unsigned long start = gtt->userptr;
+   unsigned long end = start + ttm->num_pages * PAGE_SIZE;
+   struct hmm_range *ranges;
+   struct vm_area_struct *vma = NULL, *vmas[MAX_NR_VMAS];
+   uint64_t *pfns, f;
+   int r = 0, i, nr_pages;
 
if (!mm) /* Happens during process shutdown */
return -ESRCH;
 
-   amdgpu_hmm_init_range(range);
-
down_read(>mmap_sem);
 
-   range->vma = find_vma(mm, gtt->userptr);
-   if (!range_in_vma(range->vma, gtt->userptr, end))
-   r = -EFAULT;
-   else if ((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
-   range->vma->vm_file)
+   /* user pages may cross multiple VMAs */
+   gtt->nr_ranges = 0;
+   do {
+   if (gtt->nr_ranges >= MAX_NR_VMAS) {
+   DRM_ERROR("Too many VMAs in userptr range\n");
+   r = -EFAULT;
+   goto out;
+   }
+
+   vma = find_vma(mm, vma ? vma->vm_end : start);
+   if (unlikely(!vma)) {
+   r = -EFAULT;
+   goto out;
+   }
+   vmas[gtt->nr_ranges++] = vma;
+   } while (end > vma->vm_end);
+
+   DRM_DEBUG_DRIVER("0x%lx nr_ranges %d pages 0x%lx\n",
+   start, gtt->nr_ranges, ttm->num_pages);
+
+   if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
+   vmas[0]->vm_file)) {
r = -EPERM;
-   if (r)
goto out;
+   }
 
-   range->pfns = kvmalloc_array(ttm->num_pages, sizeof(uint64_t),
-GFP_KERNEL);
-   if (range->pfns == NULL) {
+   ranges = kvmalloc_array(gtt->nr_ranges, sizeof(*ranges), GFP_KERNEL);
+   if (unlikely(!ranges)) {
r = -ENOMEM;
goto out;
}
-   range->start = gtt->userptr;
-   range->end = end;
 
-   range->pfns[0] = range->flags[HMM_PFN_VALID];
-   range->pfns[0] |= amdgpu_ttm_tt_is_readonly(ttm) ?
-   0 : range->flags[HMM_PFN_WRITE];
-   for (i = 1; i < ttm->num_pages; i++)
-   range->pfns[i] = range->pfns[0];
+   pfns = kvmalloc_array(ttm->num_pages, sizeof(*pfns), GFP_KERNEL);
+   if (unlikely(!pfns)) {
+   r = -ENOMEM;
+   goto out_free_ranges;
+   }
+
+   for (i = 0; i < gtt->nr_ranges; i++)
+   amdgpu_hmm_init_range([i]);
+
+   f = ranges[0].flags[HMM_PFN_VALID];
+   f |= amdgpu_ttm_tt_is_readonly(ttm) ?
+   0 : ranges[0].flags[HMM_PFN_WRITE];
+   memset64(pfns, f, ttm->num_pages);
+
+   for (nr_pages = 0, i = 0; i < gtt->nr_ranges; i++) {
+   ranges[i].vma = vmas[i];
+   ranges[i].start = max(start, vmas[i]->vm_start);
+   ranges[i].end = min(end, vmas[i]->vm_end);
+   ranges[i].pfns = pfns + nr_pages;
+   nr_pages += (ranges[i].end - ranges[i].start) / PAGE_SIZE;
+
+   r = hmm_vma_fault([i], true);
+   if (unlikely(r))
+   break;
+   }
+   if (unlikely(r)) {
+   while (i--)
+ 

[PATCH 1/3] drm/amdkfd: support concurrent userptr update for HMM v2

[Yang, Philip]

Userptr restore may have concurrent userptr invalidation after
hmm_vma_fault adds the range to the hmm->ranges list, needs call
hmm_vma_range_done to remove the range from hmm->ranges list first,
then reschedule the restore worker. Otherwise hmm_vma_fault will add
same range to the list, this will cause loop in the list because
range->next point to range itself.

Add function untrack_invalid_user_pages to reduce code duplication.

Change-Id: I31407739dc10554f8e418c7a0e0415d3d95552f1
Signed-off-by: Philip Yang 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 25 ++-
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index d2e315f42dad..60d53b0b497a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1935,6 +1935,23 @@ static int update_invalid_user_pages(struct 
amdkfd_process_info *process_info,
return 0;
 }
 
+/* Remove invalid userptr BOs from hmm track list
+ *
+ * Stop HMM track the userptr update
+ */
+static void untrack_invalid_user_pages(struct amdkfd_process_info 
*process_info)
+{
+   struct kgd_mem *mem, *tmp_mem;
+   struct amdgpu_bo *bo;
+
+   list_for_each_entry_safe(mem, tmp_mem,
+_info->userptr_inval_list,
+validate_list.head) {
+   bo = mem->bo;
+   amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
+   }
+}
+
 /* Validate invalid userptr BOs
  *
  * Validates BOs on the userptr_inval_list, and moves them back to the
@@ -2052,12 +2069,6 @@ static int validate_invalid_user_pages(struct 
amdkfd_process_info *process_info)
 out_free:
kfree(pd_bo_list_entries);
 out_no_mem:
-   list_for_each_entry_safe(mem, tmp_mem,
-_info->userptr_inval_list,
-validate_list.head) {
-   bo = mem->bo;
-   amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
-   }
 
return ret;
 }
@@ -2122,7 +2133,9 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct 
work_struct *work)
 * hanging. No point trying again.
 */
}
+
 unlock_out:
+   untrack_invalid_user_pages(process_info);
mutex_unlock(_info->lock);
mmput(mm);
put_task_struct(usertask);
-- 
2.17.1

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[PATCH] drm/amd/powerplay: apply Vega20 BACO workaround

[Evan Quan]

Applied vdci flush workaround for Vega20 BACO.

Change-Id: Ia132ae30f826643bfba980402a92fbd0ae7a4236
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c|  2 ++
 .../gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 12 +++
 .../gpu/drm/amd/powerplay/hwmgr/vega20_baco.h |  1 +
 .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 11 +-
 .../gpu/drm/amd/powerplay/inc/vega20_ppsmc.h  |  3 ++-
 .../drm/amd/powerplay/smumgr/vega20_smumgr.c  | 20 +++
 .../drm/amd/powerplay/smumgr/vega20_smumgr.h  |  1 +
 8 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 876486595d89..fe0f5653805b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -981,6 +981,7 @@ struct amdgpu_device {
 
int asic_reset_res;
struct work_struct  xgmi_reset_work;
+   boolin_baco_reset;
 };
 
 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index cc80f050cbf6..75a408a216b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -452,6 +452,8 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 
dev_info(adev->dev, "GPU BACO reset\n");
 
+   adev->in_baco_reset = 1;
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
index 5e8602a79b1c..df6ff9252401 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
@@ -27,6 +27,7 @@
 #include "vega20_inc.h"
 #include "vega20_ppsmc.h"
 #include "vega20_baco.h"
+#include "vega20_smumgr.h"
 
 
 
@@ -101,3 +102,14 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum 
BACO_STATE state)
 
return 0;
 }
+
+int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr)
+{
+   int ret = 0;
+
+   ret = vega20_set_pptable_driver_address(hwmgr);
+   if (ret)
+   return ret;
+
+   return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI);
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
index 51c7f8392925..f06471e712dc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
@@ -28,5 +28,6 @@
 extern int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
 extern int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE 
*state);
 extern int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE 
state);
+extern int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 9aa7bec1b5fe..664544e7fcdc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -443,6 +443,7 @@ static int vega20_init_sclk_threshold(struct pp_hwmgr 
*hwmgr)
 
 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
 {
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
int ret = 0;
 
ret = vega20_init_sclk_threshold(hwmgr);
@@ -450,7 +451,15 @@ static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
"Failed to init sclk threshold!",
return ret);
 
-   return 0;
+   if (adev->in_baco_reset) {
+   adev->in_baco_reset = 0;
+
+   ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
+   if (ret)
+   pr_err("Failed to apply vega20 baco workaround!\n");
+   }
+
+   return ret;
 }
 
 /*
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h 
b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
index 4f63a736ea0e..a0883038f3c3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
@@ -119,7 +119,8 @@
 #define PPSMC_MSG_PrepareMp1ForShutdown  0x5A
 #define PPSMC_MSG_SetMGpuFanBoostLimitRpm0x5D
 #define PPSMC_MSG_GetAVFSVoltageByDpm0x5F
-#define PPSMC_Message_Count  0x60
+#define PPSMC_MSG_BacoWorkAroundFlushVDCI0x60
+#define PPSMC_Message_Count  0x61
 
 typedef uint32_t PPSMC_Result;
 typedef uint32_t PPSMC_Msg;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
index ba00744c3413..f301a73f6df1 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
@@ -367,6 +367,26 @@ static int 

Re: [PATCH 2/3] drm/amdgpu: support userptr cross VMAs case with HMM

[Yang, Philip]

I will submit v2 to fix those issues. Some comments inline...

On 2019-03-06 3:11 p.m., Kuehling, Felix wrote:
> Some comments inline ...
> 
> On 3/5/2019 1:09 PM, Yang, Philip wrote:
>> userptr may cross two VMAs if the forked child process (not call exec
>> after fork) malloc buffer, then free it, and then malloc larger size
>> buf, kerenl will create new VMA adjacent to old VMA which was cloned
>> from parent process, some pages of userptr are in the first VMA, the
>> rest pages are in the second VMA.
>>
>> HMM expects range only have one VMA, loop over all VMAs in the address
>> range, create multiple ranges to handle this case. See
>> is_mergeable_anon_vma in mm/mmap.c for details.
>>
>> Change-Id: I0ca8c77e28deabccc139906f9ffee04b7e383314
>> Signed-off-by: Philip Yang 
>> ---
>>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 122 +---
>>1 file changed, 87 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> index cd0ccfbbcb84..173bf4db5994 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> @@ -711,7 +711,8 @@ struct amdgpu_ttm_tt {
>>  struct task_struct  *usertask;
>>  uint32_tuserflags;
>>#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
>> -struct hmm_rangerange;
>> +struct hmm_range*ranges;
>> +int nr_ranges;
>>#endif
>>};
>>
>> @@ -723,62 +724,104 @@ struct amdgpu_ttm_tt {
>> * once afterwards to stop HMM tracking
>> */
>>#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
>> +
>> +/* Support Userptr pages cross max 16 vmas */
>> +#define MAX_NR_VMAS (16)
>> +
>>int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
>>{
>>  struct amdgpu_ttm_tt *gtt = (void *)ttm;
>>  struct mm_struct *mm = gtt->usertask->mm;
>> -unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
>> -struct hmm_range *range = >range;
>> -int r = 0, i;
>> +unsigned long start = gtt->userptr;
>> +unsigned long end = start + ttm->num_pages * PAGE_SIZE;
>> +struct hmm_range *ranges;
>> +struct vm_area_struct *vma = NULL, *vmas[MAX_NR_VMAS];
>> +uint64_t *pfns, f;
>> +int r = 0, i, nr_pages;
>>
>>  if (!mm) /* Happens during process shutdown */
>>  return -ESRCH;
>>
>> -amdgpu_hmm_init_range(range);
>> -
>>  down_read(>mmap_sem);
>>
>> -range->vma = find_vma(mm, gtt->userptr);
>> -if (!range_in_vma(range->vma, gtt->userptr, end))
>> -r = -EFAULT;
>> -else if ((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
>> -range->vma->vm_file)
>> +/* user pages may cross multiple VMAs */
>> +gtt->nr_ranges = 0;
>> +do {
>> +vma = find_vma(mm, vma ? vma->vm_end : start);
>> +if (unlikely(!vma)) {
>> +r = -EFAULT;
>> +goto out;
>> +}
>> +vmas[gtt->nr_ranges++] = vma;
>> +if (gtt->nr_ranges >= MAX_NR_VMAS) {
> 
> This will lead to a failure when you have exactly 16 VMAs. If you move
> the check to the start of the loop, it will only trigger when you exceed
> the limit not just after you reach it.
> 
Ok
> 
>> +DRM_ERROR("invalid userptr range\n");
> 
> The userptr range is not really invalid. It only exceeds some artificial
> limitation in this code. A message like "Too many VMAs in userptr range"
> would be more appropriate.
> 
Ok
> 
>> +r = -EFAULT;
>> +goto out;
>> +}
>> +} while (end > vma->vm_end);
>> +
>> +DRM_DEBUG_DRIVER("0x%lx nr_ranges %d pages 0x%lx\n",
>> +start, gtt->nr_ranges, ttm->num_pages);
>> +
>> +if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
>> +vmas[0]->vm_file)) {
>>  r = -EPERM;
>> -if (r)
>>  goto out;
>> +}
>>
>> -range->pfns = kvmalloc_array(ttm->num_pages, sizeof(uint64_t),
>> - GFP_KERNEL);
>> -if (range->pfns == NULL) {
>> +ranges = kvmalloc_array(gtt->nr_ranges, sizeof(*ranges), GFP_KERNEL);
>> +if (unlikely(!ranges)) {
>>  r = -ENOMEM;
>>  goto out;
>>  }
>> -range->start = gtt->userptr;
>> -range->end = end;
>>
>> -range->pfns[0] = range->flags[HMM_PFN_VALID];
>> -range->pfns[0] |= amdgpu_ttm_tt_is_readonly(ttm) ?
>> -0 : range->flags[HMM_PFN_WRITE];
>> -for (i = 1; i < ttm->num_pages; i++)
>> -range->pfns[i] = range->pfns[0];
>> +pfns = kvmalloc_array(ttm->num_pages, sizeof(*pfns), GFP_KERNEL);
>> +if (unlikely(!pfns)) {
>> +r = -ENOMEM;
>> +goto out_free_ranges;
>> +}
>> +
>> +for (i = 0; i < gtt->nr_ranges; i++)
>> +amdgpu_hmm_init_range([i]);
>> +
>> +f = 

Re: [PATCH 1/3] drm/amdkfd: support concurrent userptr update for HMM

[Yang, Philip]

Hi Felix,

Thanks, there are other corner cases, call untrack at end of restore 
userptr worker is better place to cleanup. I will submit v2 patch, to 
fix this issue completely.

Philip

On 2019-03-06 3:01 p.m., Kuehling, Felix wrote:
> Hmm, I'm not sure. This change probably fixes this issue, but there may
> be other similar corner cases in other situations where the restore
> worker fails and needs to retry. The better place to call untrack in
> amdgpu_amdkfd_restore_userptr_worker would be at the very end. Anything
> that's left in the userptr_inval_list at that point needs to be untracked.
> 
> For now as a quick fix for an urgent bug, this change is Reviewed-by:
> Felix Kuehling . But please revisit this and
> check if there are similar corner cases as I explained above.
> 
> Regards,
>     Felix
> 
> On 3/5/2019 1:09 PM, Yang, Philip wrote:
>> Userptr restore may have concurrent userptr invalidation after
>> hmm_vma_fault adds the range to the hmm->ranges list, needs call
>> hmm_vma_range_done to remove the range from hmm->ranges list first,
>> then reschedule the restore worker. Otherwise hmm_vma_fault will add
>> same range to the list, this will cause loop in the list because
>> range->next point to range itself.
>>
>> Add function untrack_invalid_user_pages to reduce code duplication.
>>
>> Change-Id: I31407739dc10554f8e418c7a0e0415d3d95552f1
>> Signed-off-by: Philip Yang 
>> ---
>>.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 28 ++-
>>1 file changed, 21 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> index 314c048fcac6..783d760ccfe3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> @@ -1731,6 +1731,23 @@ static int update_invalid_user_pages(struct 
>> amdkfd_process_info *process_info,
>>  return 0;
>>}
>>
>> +/* Remove invalid userptr BOs from hmm track list
>> + *
>> + * Stop HMM track the userptr update
>> + */
>> +static void untrack_invalid_user_pages(struct amdkfd_process_info 
>> *process_info)
>> +{
>> +struct kgd_mem *mem, *tmp_mem;
>> +struct amdgpu_bo *bo;
>> +
>> +list_for_each_entry_safe(mem, tmp_mem,
>> + _info->userptr_inval_list,
>> + validate_list.head) {
>> +bo = mem->bo;
>> +amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
>> +}
>> +}
>> +
>>/* Validate invalid userptr BOs
>> *
>> * Validates BOs on the userptr_inval_list, and moves them back to the
>> @@ -1848,12 +1865,7 @@ static int validate_invalid_user_pages(struct 
>> amdkfd_process_info *process_info)
>>out_free:
>>  kfree(pd_bo_list_entries);
>>out_no_mem:
>> -list_for_each_entry_safe(mem, tmp_mem,
>> - _info->userptr_inval_list,
>> - validate_list.head) {
>> -bo = mem->bo;
>> -amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
>> -}
>> +untrack_invalid_user_pages(process_info);
>>
>>  return ret;
>>}
>> @@ -1897,8 +1909,10 @@ static void 
>> amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
>>   * and we can just restart the queues.
>>   */
>>  if (!list_empty(_info->userptr_inval_list)) {
>> -if (atomic_read(_info->evicted_bos) != evicted_bos)
>> +if (atomic_read(_info->evicted_bos) != evicted_bos) {
>> +untrack_invalid_user_pages(process_info);
>>  goto unlock_out; /* Concurrent eviction, try again */
>> +}
>>
>>  if (validate_invalid_user_pages(process_info))
>>  goto unlock_out;
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[PATCH] drm/amdgpu: Move IB pool init and fini.

[Andrey Grodzovsky]

Problem:
Using SDMA for TLB invalidation in certain ASICs exposed a problem
of IB pool not being ready while SDMA already up on Init and already
shutt down while SDMA still running on Fini. This caused
IB allocation failure. Temproary fix was commited into a
bringup branch but this is the generic fix.

Fix:
Init IB pool rigth after GMC is ready but before SDMA is ready.
Do th opposite for Fini.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 +++-
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 00def57..c05a551 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1686,6 +1686,13 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
}
}
 
+   r = amdgpu_ib_pool_init(adev);
+   if (r) {
+   dev_err(adev->dev, "IB initialization failed (%d).\n", r);
+   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
+   goto init_failed;
+   }
+
r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init 
complete*/
if (r)
goto init_failed;
@@ -1888,7 +1895,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.hw)
continue;
-   if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
+   if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
+   adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA) 
{
r = adev->ip_blocks[i].version->funcs->hw_fini((void 
*)adev);
/* XXX handle errors */
if (r) {
@@ -1900,6 +1908,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device 
*adev)
}
}
 
+   amdgpu_ib_pool_fini(adev);
+
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.hw)
continue;
@@ -2651,13 +2661,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
/* Get a log2 for easy divisions. */
adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
 
-   r = amdgpu_ib_pool_init(adev);
-   if (r) {
-   dev_err(adev->dev, "IB initialization failed (%d).\n", r);
-   amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
-   goto failed;
-   }
-
amdgpu_fbdev_init(adev);
 
r = amdgpu_pm_sysfs_init(adev);
@@ -2735,7 +2738,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
else
drm_atomic_helper_shutdown(adev->ddev);
}
-   amdgpu_ib_pool_fini(adev);
amdgpu_fence_driver_fini(adev);
amdgpu_pm_sysfs_fini(adev);
amdgpu_fbdev_fini(adev);
-- 
2.7.4

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Re: [PATCH 2/3] drm/amdgpu: support userptr cross VMAs case with HMM

[Kuehling, Felix]

Some comments inline ...

On 3/5/2019 1:09 PM, Yang, Philip wrote:
> userptr may cross two VMAs if the forked child process (not call exec
> after fork) malloc buffer, then free it, and then malloc larger size
> buf, kerenl will create new VMA adjacent to old VMA which was cloned
> from parent process, some pages of userptr are in the first VMA, the
> rest pages are in the second VMA.
>
> HMM expects range only have one VMA, loop over all VMAs in the address
> range, create multiple ranges to handle this case. See
> is_mergeable_anon_vma in mm/mmap.c for details.
>
> Change-Id: I0ca8c77e28deabccc139906f9ffee04b7e383314
> Signed-off-by: Philip Yang 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 122 +---
>   1 file changed, 87 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index cd0ccfbbcb84..173bf4db5994 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -711,7 +711,8 @@ struct amdgpu_ttm_tt {
>   struct task_struct  *usertask;
>   uint32_tuserflags;
>   #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
> - struct hmm_rangerange;
> + struct hmm_range*ranges;
> + int nr_ranges;
>   #endif
>   };
>   
> @@ -723,62 +724,104 @@ struct amdgpu_ttm_tt {
>* once afterwards to stop HMM tracking
>*/
>   #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
> +
> +/* Support Userptr pages cross max 16 vmas */
> +#define MAX_NR_VMAS  (16)
> +
>   int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
>   {
>   struct amdgpu_ttm_tt *gtt = (void *)ttm;
>   struct mm_struct *mm = gtt->usertask->mm;
> - unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
> - struct hmm_range *range = >range;
> - int r = 0, i;
> + unsigned long start = gtt->userptr;
> + unsigned long end = start + ttm->num_pages * PAGE_SIZE;
> + struct hmm_range *ranges;
> + struct vm_area_struct *vma = NULL, *vmas[MAX_NR_VMAS];
> + uint64_t *pfns, f;
> + int r = 0, i, nr_pages;
>   
>   if (!mm) /* Happens during process shutdown */
>   return -ESRCH;
>   
> - amdgpu_hmm_init_range(range);
> -
>   down_read(>mmap_sem);
>   
> - range->vma = find_vma(mm, gtt->userptr);
> - if (!range_in_vma(range->vma, gtt->userptr, end))
> - r = -EFAULT;
> - else if ((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
> - range->vma->vm_file)
> + /* user pages may cross multiple VMAs */
> + gtt->nr_ranges = 0;
> + do {
> + vma = find_vma(mm, vma ? vma->vm_end : start);
> + if (unlikely(!vma)) {
> + r = -EFAULT;
> + goto out;
> + }
> + vmas[gtt->nr_ranges++] = vma;
> + if (gtt->nr_ranges >= MAX_NR_VMAS) {

This will lead to a failure when you have exactly 16 VMAs. If you move 
the check to the start of the loop, it will only trigger when you exceed 
the limit not just after you reach it.


> + DRM_ERROR("invalid userptr range\n");

The userptr range is not really invalid. It only exceeds some artificial 
limitation in this code. A message like "Too many VMAs in userptr range" 
would be more appropriate.


> + r = -EFAULT;
> + goto out;
> + }
> + } while (end > vma->vm_end);
> +
> + DRM_DEBUG_DRIVER("0x%lx nr_ranges %d pages 0x%lx\n",
> + start, gtt->nr_ranges, ttm->num_pages);
> +
> + if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
> + vmas[0]->vm_file)) {
>   r = -EPERM;
> - if (r)
>   goto out;
> + }
>   
> - range->pfns = kvmalloc_array(ttm->num_pages, sizeof(uint64_t),
> -  GFP_KERNEL);
> - if (range->pfns == NULL) {
> + ranges = kvmalloc_array(gtt->nr_ranges, sizeof(*ranges), GFP_KERNEL);
> + if (unlikely(!ranges)) {
>   r = -ENOMEM;
>   goto out;
>   }
> - range->start = gtt->userptr;
> - range->end = end;
>   
> - range->pfns[0] = range->flags[HMM_PFN_VALID];
> - range->pfns[0] |= amdgpu_ttm_tt_is_readonly(ttm) ?
> - 0 : range->flags[HMM_PFN_WRITE];
> - for (i = 1; i < ttm->num_pages; i++)
> - range->pfns[i] = range->pfns[0];
> + pfns = kvmalloc_array(ttm->num_pages, sizeof(*pfns), GFP_KERNEL);
> + if (unlikely(!pfns)) {
> + r = -ENOMEM;
> + goto out_free_ranges;
> + }
> +
> + for (i = 0; i < gtt->nr_ranges; i++)
> + amdgpu_hmm_init_range([i]);
> +
> + f = ranges[0].flags[HMM_PFN_VALID];
> + f |= amdgpu_ttm_tt_is_readonly(ttm) ?
> + 0 : ranges[0].flags[HMM_PFN_WRITE];
> + memset64(pfns, f, ttm->num_pages);
> +
> + 

Re: [PATCH 1/3] drm/amdkfd: support concurrent userptr update for HMM

[Kuehling, Felix]

Hmm, I'm not sure. This change probably fixes this issue, but there may 
be other similar corner cases in other situations where the restore 
worker fails and needs to retry. The better place to call untrack in  
amdgpu_amdkfd_restore_userptr_worker would be at the very end. Anything 
that's left in the userptr_inval_list at that point needs to be untracked.

For now as a quick fix for an urgent bug, this change is Reviewed-by: 
Felix Kuehling . But please revisit this and 
check if there are similar corner cases as I explained above.

Regards,
   Felix

On 3/5/2019 1:09 PM, Yang, Philip wrote:
> Userptr restore may have concurrent userptr invalidation after
> hmm_vma_fault adds the range to the hmm->ranges list, needs call
> hmm_vma_range_done to remove the range from hmm->ranges list first,
> then reschedule the restore worker. Otherwise hmm_vma_fault will add
> same range to the list, this will cause loop in the list because
> range->next point to range itself.
>
> Add function untrack_invalid_user_pages to reduce code duplication.
>
> Change-Id: I31407739dc10554f8e418c7a0e0415d3d95552f1
> Signed-off-by: Philip Yang 
> ---
>   .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 28 ++-
>   1 file changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 314c048fcac6..783d760ccfe3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1731,6 +1731,23 @@ static int update_invalid_user_pages(struct 
> amdkfd_process_info *process_info,
>   return 0;
>   }
>   
> +/* Remove invalid userptr BOs from hmm track list
> + *
> + * Stop HMM track the userptr update
> + */
> +static void untrack_invalid_user_pages(struct amdkfd_process_info 
> *process_info)
> +{
> + struct kgd_mem *mem, *tmp_mem;
> + struct amdgpu_bo *bo;
> +
> + list_for_each_entry_safe(mem, tmp_mem,
> +  _info->userptr_inval_list,
> +  validate_list.head) {
> + bo = mem->bo;
> + amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
> + }
> +}
> +
>   /* Validate invalid userptr BOs
>*
>* Validates BOs on the userptr_inval_list, and moves them back to the
> @@ -1848,12 +1865,7 @@ static int validate_invalid_user_pages(struct 
> amdkfd_process_info *process_info)
>   out_free:
>   kfree(pd_bo_list_entries);
>   out_no_mem:
> - list_for_each_entry_safe(mem, tmp_mem,
> -  _info->userptr_inval_list,
> -  validate_list.head) {
> - bo = mem->bo;
> - amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
> - }
> + untrack_invalid_user_pages(process_info);
>   
>   return ret;
>   }
> @@ -1897,8 +1909,10 @@ static void 
> amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
>* and we can just restart the queues.
>*/
>   if (!list_empty(_info->userptr_inval_list)) {
> - if (atomic_read(_info->evicted_bos) != evicted_bos)
> + if (atomic_read(_info->evicted_bos) != evicted_bos) {
> + untrack_invalid_user_pages(process_info);
>   goto unlock_out; /* Concurrent eviction, try again */
> + }
>   
>   if (validate_invalid_user_pages(process_info))
>   goto unlock_out;
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Re: [PATCH] drm/amdgpu: Add sysfs entries for xgmi hive.

[StDenis, Tom]

On 2019-03-05 2:16 p.m., Grodzovsky, Andrey wrote:
> In each /sys/class/drm/cardX/device/ device you will see the following
> 
> xgmi_device_id /* contains the device id within the hive */
> xgmi_hive_info ->
> ../../../../:00:01.1/:02:00.0/:03:00.0/:04:00.0/xgmi_hive_info/
> /* hive info folder */
> 
> inside xgmi_hive_info are back pointers to /sys/class/drm/cardX/device/
> for each hive member -
> 
> lrwxrwxrwx  1 root root    0 Mar  5 12:27 node1 -> ../../:04:00.0/
> lrwxrwxrwx  1 root root    0 Mar  5 12:27 node2 ->
> ../../../../../:00:1b.0/:05:00.0/:06:00.0/:07:00.0/
> 
> -r--r--r--  1 root root 4096 Mar  5 12:27 xgmi_hive_id /* contains the
> hive id */

Could I get an ssh on such a box to test out the umr code (which I 
haven't written yet)?

Thanks,
Tom
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[ANNOUNCE] xf86-video-ati 19.0.0

[Michel Dänzer]

I'm pleased to announce the 19.0.0 release of xf86-video-ati, the Xorg
driver for ATI/AMD Radeon GPUs supported by the radeon kernel driver.
This release supports xserver versions 1.13-1.20.

Highlights:

* Various TearFree related fixes and robustness improvements.
* Up to six independent instances per GPU are now supported in "Zaphod"
  style multi-head configurations.

Plus other improvements and fixes. Thanks to everybody who contributed
to this release in any way!


Alan Coopersmith (1):
  Update README for gitlab migration

Mario Kleiner (1):
  Fix crash when page flipping in multi-X-Screen/Zaphod mode

Michel Dänzer (30):
  dri3: Handle radeon_get_pixmap_bo returning NULL
  Handle pending scanout update in drmmode_crtc_scanout_free
  Make wait_pending_flip / handle_deferred symmetric in set_mode_major
  Allow up to six instances in Zaphod mode
  Post-release version bump
  Detect and fix up non-premultiplied cursor data
  Skip gamma correction of cursor data if premultiplied R/G/B > alpha
  glamor: Can work at depth >= 15 with current xserver Git master
  Use drm_abort_one in drm_queue_handler
  Explicitly keep track of whether a DRM event is for a flip or not
  Move deferred vblank events to separate drm_vblank_deferred list
  Perform scanout buffer update immediately if drmmode_wait_vblank fails
  Cancel pending scanout update in drmmode_crtc_scanout_update
  Automatically try re-enabling TearFree after a flip failed
  Drop RADEONInfoRec::cursor_bo array
  Use drmIoctl in drmmode_show_cursor
  Update cursor position in drmmode_show_cursor if hotspot changed
  Use two HW cursor buffers per CRTC
  Only call drmmode_uevent_init if RandR is enabled
  Only call drmmode_validate_leases if RandR is enabled
  dri3: Flush if necessary in dri3_fd_from_pixmap
  dri2: Flush in dri2_create_buffer2 after calling glamor_set_pixmap_bo
  glamor: Avoid glamor_create_pixmap for pixmaps backing windows
  Don't allow TearFree scanout flips to complete in the same vblank period
  Only update drmmode_crtc->flip_pending after actually submitting a flip
  Call drmHandleEvent again if it was interrupted by a signal
  Keep waiting for a pending flip if drm_handle_event returns 0
  present: Check that flip and screen pixmap pitches match
  dri2: Call drm_queue_handle_deferred in dri2_deferred_event
  Bump version for 19.0.0 release

git tag: xf86-video-ati-19.0.0

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-19.0.0.tar.bz2
MD5:  0a95c1c8158d658bd0b3ac38a1b31382  xf86-video-ati-19.0.0.tar.bz2
SHA1: c7bb5d25ca725b8fa625a5f1a6948433e51b98a5  xf86-video-ati-19.0.0.tar.bz2
SHA256: dd907d318884bb6e81e7e62da7bb34af26aeeed3a81c21e0b46a4f3cae3ff457  
xf86-video-ati-19.0.0.tar.bz2
SHA512: 
0674c8befa926fd3b431ce80d90f2cd0de17314efe7fd3a5ed0d78018d6cd32625b514bf68436a47eb15e5ad4b50317f3c09fd687b77e69a067d1210ee459827
  xf86-video-ati-19.0.0.tar.bz2
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-19.0.0.tar.bz2.sig

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-19.0.0.tar.gz
MD5:  b00599fcb50647d0ead2e47b020bcd3d  xf86-video-ati-19.0.0.tar.gz
SHA1: 530769c5497f24438e1061a5f10cd17eb5b9b7b2  xf86-video-ati-19.0.0.tar.gz
SHA256: cf3e10db23c6fd1e6be7662662073f580705652ef2f450ac7948c2ee6b021163  
xf86-video-ati-19.0.0.tar.gz
SHA512: 
189786e996200a0561ab1ce62c85a4d1be8c679c371a43e547a2c8617ffe530812b17ee70729d71fec4e876c55f66deea3468edfeba669e4aeaa958f7529180c
  xf86-video-ati-19.0.0.tar.gz
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-19.0.0.tar.gz.sig


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer



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Re: [PATCH] drm/amdkfd: fix a compiling error when CONFIG_HSA_AMD disalbed

[Huang, JinHuiEric]

Oops. I submitted it moments ago. Thanks for your catch anyway.


Eric


On 2019-03-06 11:34 a.m., William Lewis wrote:

Typo in patch description:  s/disalbed/disabled/


On 3/6/19 10:11 AM, Deucher, Alexander wrote:
Add a line like:

Fixes: 9032ea09e2d2ef ("drm/amdkfd: add RAS ECC event support")

With that added:
Reviewed-by: Alex Deucher 



From: amd-gfx 

 on behalf of Huang, JinHuiEric 

Sent: Wednesday, March 6, 2019 10:59 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, JinHuiEric
Subject: [PATCH] drm/amdkfd: fix a compiling error when CONFIG_HSA_AMD disalbed

It fixes a commpiling error on commit
9032ea09e2d2ef0d10e5cd793713bf2eb21643c5
drm/amdkfd: add RAS ECC event support

Change-Id: I8792767726e28eed3a3fcf9072f608701be13c79
Signed-off-by: Eric Huang 

---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index fe1d736..acf8ae0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -640,4 +640,8 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
 {
 }
+
+void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
+{
+}
 #endif
--
2.7.4

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Re: [PATCH] drm/amdkfd: fix a compiling error when CONFIG_HSA_AMD disalbed

[William Lewis]

Typo in patch description:  s/disalbed/disabled/


On 3/6/19 10:11 AM, Deucher, Alexander wrote:
Add a line like:

Fixes: 9032ea09e2d2ef ("drm/amdkfd: add RAS ECC event support")

With that added:
Reviewed-by: Alex Deucher 



From: amd-gfx 

 on behalf of Huang, JinHuiEric 

Sent: Wednesday, March 6, 2019 10:59 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, JinHuiEric
Subject: [PATCH] drm/amdkfd: fix a compiling error when CONFIG_HSA_AMD disalbed

It fixes a commpiling error on commit
9032ea09e2d2ef0d10e5cd793713bf2eb21643c5
drm/amdkfd: add RAS ECC event support

Change-Id: I8792767726e28eed3a3fcf9072f608701be13c79
Signed-off-by: Eric Huang 

---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index fe1d736..acf8ae0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -640,4 +640,8 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
 {
 }
+
+void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
+{
+}
 #endif
--
2.7.4

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Recall: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config

[Zeng, Oak]

Zeng, Oak would like to recall the message, "[PATCH 1/3] drm/amdgpu: change 
Vega IH ring 1 config".
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Re: [PATCH] drm/amdgpu: XGMI pstate switch initial support

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Liu, Shaoyun 

Sent: Wednesday, March 6, 2019 11:03 AM
To: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: XGMI pstate switch initial support

Ping

-Original Message-
From: Liu, Shaoyun 
Sent: Tuesday, March 5, 2019 11:25 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun 
Subject: [PATCH] drm/amdgpu: XGMI pstate switch initial support

Driver vote low to high pstate switch whenever there is an outstanding XGMI 
mapping request. Driver vote high to low pstate when all the outstanding XGMI 
mapping is terminated.

Change-Id: I499fb1c389077632fe9cfce4b6dc9a33deff6875
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  3 +++  
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 29 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c   | 15 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h   |  2 ++
 6 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f0dada9..c3c8392 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -930,6 +930,10 @@ struct amdgpu_device {

 int asic_reset_res;
 struct work_struct  xgmi_reset_work;
+
+   /* counter of mapped memory through xgmi */
+   atomic_txgmi_map_counter;
+
 };

 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device 
*bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 00def57..f28abb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2008,6 +2008,9 @@ static void 
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
 r = amdgpu_device_enable_mgpu_fan_boost();
 if (r)
 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
+
+   /*set to low pstate by default */
+   amdgpu_xgmi_set_pstate(adev, 0);
 }

 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) diff 
--git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 220a6a7..6f176bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -54,6 +54,7 @@ struct amdgpu_bo_va_mapping {
 uint64_t__subtree_last;
 uint64_toffset;
 uint64_tflags;
+   boolis_xgmi;
 };

 /* User space allocated BO in a VM */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index c0f315b..5765761 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -34,6 +34,7 @@
 #include "amdgpu_trace.h"
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_gmc.h"
+#include "amdgpu_xgmi.h"

 /**
  * DOC: GPUVM
@@ -2013,8 +2014,9 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 struct ttm_mem_reg *mem;
 struct drm_mm_node *nodes;
 struct dma_fence *exclusive, **last_update;
-   uint64_t flags;
 struct amdgpu_device *bo_adev = adev;
+   bool is_xgmi = false;
+   uint64_t flags;
 int r;

 if (clear || !bo) {
@@ -2036,6 +2038,10 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 if (bo) {
 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (adev != bo_adev &&
+   adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id)
+   is_xgmi = true;
 } else {
 flags = 0x0;
 }
@@ -2054,6 +2060,19 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 }

 list_for_each_entry(mapping, _va->invalids, list) {
+   if (mapping->is_xgmi != is_xgmi) {
+   if (is_xgmi) {
+   /* Adding an XGMI mapping to the PT */
+   if (atomic_inc_return(>xgmi_map_counter) 
== 1)
+   amdgpu_xgmi_set_pstate(adev, 1);
+   } else {
+   /* Removing an XGMI mapping from the PT */
+   if (atomic_dec_return(>xgmi_map_counter) 
== 0)
+   amdgpu_xgmi_set_pstate(adev, 0);
+   }
+   mapping->is_xgmi = is_xgmi;
+   }
+
 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
mapping, flags, 

Re: [PATCH] drm/amdkfd: fix a compiling error when CONFIG_HSA_AMD disalbed

[Deucher, Alexander]

Add a line like:

Fixes: 9032ea09e2d2ef ("drm/amdkfd: add RAS ECC event support")

With that added:
Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Huang, 
JinHuiEric 
Sent: Wednesday, March 6, 2019 10:59 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, JinHuiEric
Subject: [PATCH] drm/amdkfd: fix a compiling error when CONFIG_HSA_AMD disalbed

It fixes a commpiling error on commit
9032ea09e2d2ef0d10e5cd793713bf2eb21643c5
drm/amdkfd: add RAS ECC event support

Change-Id: I8792767726e28eed3a3fcf9072f608701be13c79
Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index fe1d736..acf8ae0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -640,4 +640,8 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
 {
 }
+
+void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
+{
+}
 #endif
--
2.7.4

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RE: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config

[Zeng, Oak]

Copied register definitions below. I guess with this change, you changed how 
the IH block treat new interrupt when ring is full. Before this change, IH keep 
new interrupt in the ring and overwrite oldest interrupt. After your change, IH 
will simply drop new interrupt and keep old interrupt in the ring (keep wptr 
unchanged).



Is above understanding correct? If yes, can you explain why the new scheme is 
more reliable? If this is more reliable, should we use this scheme for all 3 
interrupt ring?


RB_FULL_DRAIN_ENABLE

9

0x0

When Ring Buffer is full, this enables draining of interrupts to prevent back 
pressure to IH clients.
 POSSIBLE VALUES:
  00 - Disable

WPTR_OVERFLOW_ENABLE

16

0x1

Ring Buffer write pointer overflow.
 POSSIBLE VALUES:
  00 - Disable
  01 - Enable






Regards,

Oak



-Original Message-
From: amd-gfx  On Behalf Of Christian 
König
Sent: Wednesday, March 6, 2019 4:29 AM
To: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config



Ping? Can anybody review this?



Thanks,

Christian.



Am 04.03.19 um 20:10 schrieb Christian König:

> Disable overflow and enable full drain. This makes fault handling on

> ring 1 much more reliable since we don't generate back pressure any more.

>

> Signed-off-by: Christian König 
> mailto:christian.koe...@amd.com>>

> ---

>   drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 

>   1 file changed, 4 insertions(+)

>

> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> index 6d1f804277f8..d4a3cc413af8 100644

> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> @@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct

> amdgpu_device *adev)

>

>ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, 
> mmIH_RB_CNTL_RING1);

>ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);

> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

> + 
> WPTR_OVERFLOW_ENABLE, 0);

> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

> + 
> RB_FULL_DRAIN_ENABLE, 1);

>WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, 
> ih_rb_cntl);

>

>/* set rptr, wptr to 0 */



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RE: [PATCH] drm/amdgpu: XGMI pstate switch initial support

[Liu, Shaoyun]

Ping

-Original Message-
From: Liu, Shaoyun  
Sent: Tuesday, March 5, 2019 11:25 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun 
Subject: [PATCH] drm/amdgpu: XGMI pstate switch initial support

Driver vote low to high pstate switch whenever there is an outstanding XGMI 
mapping request. Driver vote high to low pstate when all the outstanding XGMI 
mapping is terminated.

Change-Id: I499fb1c389077632fe9cfce4b6dc9a33deff6875
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  3 +++  
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 29 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c   | 15 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h   |  2 ++
 6 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f0dada9..c3c8392 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -930,6 +930,10 @@ struct amdgpu_device {
 
int asic_reset_res;
struct work_struct  xgmi_reset_work;
+
+   /* counter of mapped memory through xgmi */
+   atomic_txgmi_map_counter;
+
 };
 
 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device 
*bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 00def57..f28abb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2008,6 +2008,9 @@ static void 
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
r = amdgpu_device_enable_mgpu_fan_boost();
if (r)
DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
+
+   /*set to low pstate by default */
+   amdgpu_xgmi_set_pstate(adev, 0);
 }
 
 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) diff 
--git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 220a6a7..6f176bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -54,6 +54,7 @@ struct amdgpu_bo_va_mapping {
uint64_t__subtree_last;
uint64_toffset;
uint64_tflags;
+   boolis_xgmi;
 };
 
 /* User space allocated BO in a VM */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index c0f315b..5765761 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -34,6 +34,7 @@
 #include "amdgpu_trace.h"
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_gmc.h"
+#include "amdgpu_xgmi.h"
 
 /**
  * DOC: GPUVM
@@ -2013,8 +2014,9 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct ttm_mem_reg *mem;
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
-   uint64_t flags;
struct amdgpu_device *bo_adev = adev;
+   bool is_xgmi = false;
+   uint64_t flags;
int r;
 
if (clear || !bo) {
@@ -2036,6 +2038,10 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
if (bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (adev != bo_adev &&
+   adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id)
+   is_xgmi = true;
} else {
flags = 0x0;
}
@@ -2054,6 +2060,19 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
}
 
list_for_each_entry(mapping, _va->invalids, list) {
+   if (mapping->is_xgmi != is_xgmi) {
+   if (is_xgmi) {
+   /* Adding an XGMI mapping to the PT */
+   if (atomic_inc_return(>xgmi_map_counter) 
== 1)
+   amdgpu_xgmi_set_pstate(adev, 1);
+   } else {
+   /* Removing an XGMI mapping from the PT */
+   if (atomic_dec_return(>xgmi_map_counter) 
== 0)
+   amdgpu_xgmi_set_pstate(adev, 0);
+   }
+   mapping->is_xgmi = is_xgmi;
+   }
+
r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
   mapping, flags, bo_adev, nodes,
   last_update);
@@ -2271,6 +2290,13 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
 

[PATCH] drm/amdkfd: fix a compiling error when CONFIG_HSA_AMD disalbed

[Huang, JinHuiEric]

It fixes a commpiling error on commit
9032ea09e2d2ef0d10e5cd793713bf2eb21643c5
drm/amdkfd: add RAS ECC event support

Change-Id: I8792767726e28eed3a3fcf9072f608701be13c79
Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index fe1d736..acf8ae0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -640,4 +640,8 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
 {
 }
+
+void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
+{
+}
 #endif
-- 
2.7.4

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Re: [PATCH 3/3] drm/amdgpu: more descriptive message if HMM not enabled v3

[Michel Dänzer]

On 2019-03-06 4:41 p.m., Yang, Philip wrote:
> If using old kernel config file, CONFIG_ZONE_DEVICE is not selected,
> so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver
> error message "Failed to register MMU notifier" is not clear. Inform
> user with more descriptive message on how to fix the missing kernel
> config option.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808
> 
> Change-Id: Idfebaeababa4c37c1ef093c2b91a26910a167585
> Signed-off-by: Philip Yang 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
> index 4803e216e174..ee5541b49604 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
> @@ -53,6 +53,8 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct 
> amdgpu_device *adev,
>  }
>  static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long 
> addr)
>  {
> + DRM_WARN_ONCE("HMM_MIRROR kernel config option is not enabled, "
> + "add CONFIG_ZONE_DEVICE=y in config file to fix this\n");

With the second line indentation fixed to properly line up with the
opening parenthesis,

Reviewed-by: Michel Dänzer 


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[PATCH 3/3] drm/amdgpu: more descriptive message if HMM not enabled v3

[Yang, Philip]

If using old kernel config file, CONFIG_ZONE_DEVICE is not selected,
so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver
error message "Failed to register MMU notifier" is not clear. Inform
user with more descriptive message on how to fix the missing kernel
config option.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808

Change-Id: Idfebaeababa4c37c1ef093c2b91a26910a167585
Signed-off-by: Philip Yang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
index 4803e216e174..ee5541b49604 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
@@ -53,6 +53,8 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct 
amdgpu_device *adev,
 }
 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
 {
+   DRM_WARN_ONCE("HMM_MIRROR kernel config option is not enabled, "
+   "add CONFIG_ZONE_DEVICE=y in config file to fix this\n");
return -ENODEV;
 }
 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
-- 
2.17.1

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Re: [PATCH 3/3] drm/amdgpu: more descriptive message if HMM not enabled v2

[Michel Dänzer]

On 2019-03-06 4:16 p.m., Yang, Philip wrote:
> On 2019-03-06 10:04 a.m., Christian König wrote:
>> Am 06.03.19 um 16:02 schrieb Yang, Philip:
>>> If using old kernel config file, CONFIG_ZONE_DEVICE is not selected,
>>> so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver
>>> error message "Failed to register MMU notifier" is not clear. Inform
>>> user with more descriptive message on how to fix the missing kernel
>>> config option.
>>>
>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808
>>>
>>> Change-Id: Idfebaeababa4c37c1ef093c2b91a26910a167585
>>> Signed-off-by: Philip Yang 
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
>>> index 4803e216e174..a5fd73fc24bf 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
>>> @@ -53,6 +53,8 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct 
>>> amdgpu_device *adev,
>>>   }
>>>   static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned 
>>> long addr)
>>>   {
>>> +    DRM_WARN_ONCE("HMM_MIRROR kernel config option is not enabled\n");
>>> +    DRM_WARN_ONCE("add CONFIG_ZONE_DEVICE=y in config file to fix 
>>> this\n");
>>
>> One message please, apart from that looks good to me.
>>
>> Christian.
>>
> Do you mean use multiple line string with one DRM_WARN_ONCE call? That 
> will get checkpatch warning "WARNING: quoted string split across lines".
> Can I just ignore that checkpatch warning?

Probably, though it depends what exactly the corresponding patch looks like.


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Re: [PATCH v2] tests/amdgpu: add deadlock test for sdma

[Grodzovsky, Andrey]

On 3/6/19 1:37 AM, Cui, Flora wrote:

> deadlock test for sdma will cause gpu recoverty.
> disable the test for now until GPU reset recovery could survive at least
> 1000 times test.

Can you specify what issues you see and on what ASIC ?

Andrey

>
> v2: add modprobe parameter
>
> Change-Id: I9adac63c62db22107345eddb30e7d81a1bda838c
> Signed-off-by: Flora Cui 
> ---
>   tests/amdgpu/amdgpu_test.c|   4 ++
>   tests/amdgpu/deadlock_tests.c | 103 
> +-
>   2 files changed, 106 insertions(+), 1 deletion(-)
>
> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
> index ebf4409..38b8a68 100644
> --- a/tests/amdgpu/amdgpu_test.c
> +++ b/tests/amdgpu/amdgpu_test.c
> @@ -426,6 +426,10 @@ static void amdgpu_disable_suites()
>   "compute ring block test (set 
> amdgpu.lockup_timeout=50)", CU_FALSE))
>   fprintf(stderr, "test deactivation failed - %s\n", 
> CU_get_error_msg());
>   
> + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
> + "sdma ring block test (set 
> amdgpu.lockup_timeout=50)", CU_FALSE))
> + fprintf(stderr, "test deactivation failed - %s\n", 
> CU_get_error_msg());
> +
>   if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
>   fprintf(stderr, "test deactivation failed - %s\n", 
> CU_get_error_msg());
>   
> diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
> index a6c2635..91368c1 100644
> --- a/tests/amdgpu/deadlock_tests.c
> +++ b/tests/amdgpu/deadlock_tests.c
> @@ -96,6 +96,9 @@
>   
>   #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR  
> 0x54f
>   
> +#define SDMA_PKT_HEADER_OP(x)(x & 0xff)
> +#define SDMA_OP_POLL_REGMEM  8
> +
>   static  amdgpu_device_handle device_handle;
>   static  uint32_t  major_version;
>   static  uint32_t  minor_version;
> @@ -110,6 +113,7 @@ static void amdgpu_deadlock_gfx(void);
>   static void amdgpu_deadlock_compute(void);
>   static void amdgpu_illegal_reg_access();
>   static void amdgpu_illegal_mem_access();
> +static void amdgpu_deadlock_sdma(void);
>   
>   CU_BOOL suite_deadlock_tests_enable(void)
>   {
> @@ -171,6 +175,7 @@ int suite_deadlock_tests_clean(void)
>   CU_TestInfo deadlock_tests[] = {
>   { "gfx ring block test (set amdgpu.lockup_timeout=50)", 
> amdgpu_deadlock_gfx },
>   { "compute ring block test (set amdgpu.lockup_timeout=50)", 
> amdgpu_deadlock_compute },
> + { "sdma ring block test (set amdgpu.lockup_timeout=50)", 
> amdgpu_deadlock_sdma },
>   { "illegal reg access test", amdgpu_illegal_reg_access },
>   { "illegal mem access test (set amdgpu.vm_fault_stop=2)", 
> amdgpu_illegal_mem_access },
>   CU_TEST_INFO_NULL,
> @@ -260,7 +265,6 @@ static void amdgpu_deadlock_helper(unsigned ip_type)
>   ibs_request.ibs = _info;
>   ibs_request.resources = bo_list;
>   ibs_request.fence_info.handle = NULL;
> -
>   for (i = 0; i < 200; i++) {
>   r = amdgpu_cs_submit(context_handle, 0,_request, 1);
>   CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
> @@ -291,6 +295,103 @@ static void amdgpu_deadlock_helper(unsigned ip_type)
>   CU_ASSERT_EQUAL(r, 0);
>   }
>   
> +static void amdgpu_deadlock_sdma(void)
> +{
> + amdgpu_context_handle context_handle;
> + amdgpu_bo_handle ib_result_handle;
> + void *ib_result_cpu;
> + uint64_t ib_result_mc_address;
> + struct amdgpu_cs_request ibs_request;
> + struct amdgpu_cs_ib_info ib_info;
> + struct amdgpu_cs_fence fence_status;
> + uint32_t expired;
> + int i, r;
> + amdgpu_bo_list_handle bo_list;
> + amdgpu_va_handle va_handle;
> + struct drm_amdgpu_info_hw_ip info;
> + uint32_t ring_id;
> +
> + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, );
> + CU_ASSERT_EQUAL(r, 0);
> +
> + r = amdgpu_cs_ctx_create(device_handle, _handle);
> + CU_ASSERT_EQUAL(r, 0);
> +
> + for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
> + r = pthread_create(_thread, NULL, write_mem_address, 
> NULL);
> + CU_ASSERT_EQUAL(r, 0);
> +
> + r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
> + AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? 
> AMDGPU_VM_MTYPE_UC : 0,
> + _result_handle, 
> _result_cpu,
> + 
> _result_mc_address, _handle);
> + CU_ASSERT_EQUAL(r, 0);
> +
> + r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
> +_list);
> + CU_ASSERT_EQUAL(r, 0);
> +
> + ptr = ib_result_cpu;
> + i = 0;
> +
> + ptr[i++] = SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
> + (0 << 26) | /* WAIT_REG_MEM */
> +   

Re: [PATCH 3/3] drm/amdgpu: more descriptive message if HMM not enabled v2

[Yang, Philip]

On 2019-03-06 10:04 a.m., Christian König wrote:
> Am 06.03.19 um 16:02 schrieb Yang, Philip:
>> If using old kernel config file, CONFIG_ZONE_DEVICE is not selected,
>> so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver
>> error message "Failed to register MMU notifier" is not clear. Inform
>> user with more descriptive message on how to fix the missing kernel
>> config option.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808
>>
>> Change-Id: Idfebaeababa4c37c1ef093c2b91a26910a167585
>> Signed-off-by: Philip Yang 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
>> index 4803e216e174..a5fd73fc24bf 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
>> @@ -53,6 +53,8 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct 
>> amdgpu_device *adev,
>>   }
>>   static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned 
>> long addr)
>>   {
>> +    DRM_WARN_ONCE("HMM_MIRROR kernel config option is not enabled\n");
>> +    DRM_WARN_ONCE("add CONFIG_ZONE_DEVICE=y in config file to fix 
>> this\n");
> 
> One message please, apart from that looks good to me.
> 
> Christian.
> 
Do you mean use multiple line string with one DRM_WARN_ONCE call? That 
will get checkpatch warning "WARNING: quoted string split across lines".
Can I just ignore that checkpatch warning?

Philip
>>   return -ENODEV;
>>   }
>>   static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
> 
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Re: [PATCH 3/3] drm/amdgpu: more descriptive message if HMM not enabled v2

[Christian König]

Am 06.03.19 um 16:02 schrieb Yang, Philip:

If using old kernel config file, CONFIG_ZONE_DEVICE is not selected,
so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver
error message "Failed to register MMU notifier" is not clear. Inform
user with more descriptive message on how to fix the missing kernel
config option.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808

Change-Id: Idfebaeababa4c37c1ef093c2b91a26910a167585
Signed-off-by: Philip Yang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
index 4803e216e174..a5fd73fc24bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
@@ -53,6 +53,8 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct 
amdgpu_device *adev,
  }
  static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
  {
+   DRM_WARN_ONCE("HMM_MIRROR kernel config option is not enabled\n");
+   DRM_WARN_ONCE("add CONFIG_ZONE_DEVICE=y in config file to fix this\n");


One message please, apart from that looks good to me.

Christian.


return -ENODEV;
  }
  static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}


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[PATCH 3/3] drm/amdgpu: more descriptive message if HMM not enabled v2

[Yang, Philip]

If using old kernel config file, CONFIG_ZONE_DEVICE is not selected,
so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver
error message "Failed to register MMU notifier" is not clear. Inform
user with more descriptive message on how to fix the missing kernel
config option.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808

Change-Id: Idfebaeababa4c37c1ef093c2b91a26910a167585
Signed-off-by: Philip Yang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
index 4803e216e174..a5fd73fc24bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
@@ -53,6 +53,8 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct 
amdgpu_device *adev,
 }
 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
 {
+   DRM_WARN_ONCE("HMM_MIRROR kernel config option is not enabled\n");
+   DRM_WARN_ONCE("add CONFIG_ZONE_DEVICE=y in config file to fix this\n");
return -ENODEV;
 }
 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
-- 
2.17.1

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Re: randr: Virtual monitor not present with MST display

[Michel Dänzer]

On 2019-03-06 1:41 p.m., Paul Menzel wrote:
> On 03/05/19 20:07, Alex Deucher wrote:
>> On Tue, Mar 5, 2019 at 1:16 PM Paul Menzel wrote:
> 
>>> Using the MST display Dell UP3214Q (two panels) with an AMD system,
>>> the virtual monitor object is not created. GDM and Xfce consider both
>>> panels as separate screens (`xrandr --listmonitors`).
>>>
>>> [0.00] Linux version 4.20.13.mx64.248 
>>> (r...@holidayincambodia.molgen.mpg.de) (gcc version 7.3.0 (GCC)) #1 SMP Wed 
>>> Feb 27 14:10:55 CET 2019
>>>
>>> [   79.494297] [drm] DM_MST: stopping TM on aconnector: a8109331 
>>> [id: 56]
>>> [   79.494362] [drm] DM_MST: Disabling connector: 776ea22b [id: 63] 
>>> [master: a8109331]
>>> [   79.494406] [drm] DM_MST: Disabling connector: 057ebdbb [id: 67] 
>>> [master: a8109331]
>>> [   79.781882] snd_hda_intel :00:1f.3: spurious response 0x0:0x2, last 
>>> cmd=0x201f0500
>>> [   86.028806] [drm] DM_MST: starting TM on aconnector: a8109331 
>>> [id: 56]
>>> [   86.053072] [drm] DM_MST: added connector: 1c9b49ed [id: 71] 
>>> [master: a8109331]
>>> [   86.108540] [drm] SADs count is: -2, don't need to read it
>>> [   86.386661] [drm:create_stream_for_sink [amdgpu]] *ERROR* Failed to 
>>> create stream for sink!
>>> [   87.237878] [drm] DM_MST: added connector: c3ffcbbb [id: 80] 
>>> [master: a8109331]
>>> [   87.293028] [drm] SADs count is: -2, don't need to read it
>>> [  206.993344] [drm] DM_MST: stopping TM on aconnector: a8109331 
>>> [id: 56]
>>> [  206.993423] [drm] DM_MST: Disabling connector: 1c9b49ed [id: 71] 
>>> [master: a8109331]
>>> [  206.993456] [drm] DM_MST: Disabling connector: c3ffcbbb [id: 80] 
>>> [master: a8109331]
>>> [  207.548051] [drm:create_stream_for_sink [amdgpu]] *ERROR* Failed to 
>>> create stream for sink!
>>> [  207.603193] [drm:create_stream_for_sink [amdgpu]] *ERROR* Failed to 
>>> create stream for sink!
>>> [  207.762388] traps: xfdesktop[2225] general protection fault 
>>> ip:7f588981226c sp:7ffee65af370 error:0 in 
>>> libgobject-2.0.so.0.5800.1[7f58897da000+56000]
>>> [  210.320612] [drm] DM_MST: starting TM on aconnector: b456cd59 
>>> [id: 62]
>>> [  210.343497] [drm] DM_MST: added connector: 735839d5 [id: 73] 
>>> [master: b456cd59]
>>> [  210.399168] [drm] SADs count is: -2, don't need to read it
>>> [  210.404454] [drm] DM_MST: added connector: cccb0c2d [id: 88] 
>>> [master: b456cd59]
>>> [  210.675589] [drm] SADs count is: -2, don't need to read it
> 
> I didn’t provide the output of xrandr in my previous message.
> 
> $ xrandr --listmonitors
>  Monitors: 2
>  0: +DisplayPort-9 1920/698x2160/392+0+0  DisplayPort-9
>  1: +DisplayPort-10 1920/698x2160/392+1920+0  DisplayPort-10
> 
> Please find the X.Org X Server log attached.
> 
>>> With an Intel system, the monitor object is shown.
> 
> To clarify, the modesetting driver is used with the Intel hardware.

Does this work better with the modesetting driver on the AMD system?


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Re: [PATCH 3/3] drm/amdgpu: more descriptive message if HMM not enabled

[Yang, Philip]

On 2019-03-06 4:05 a.m., Michel Dänzer wrote:
> On 2019-03-05 7:09 p.m., Yang, Philip wrote:
>> If using old kernel config file, CONFIG_ZONE_DEVICE is not selected,
>> so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver
>> error message "Failed to register MMU notifier" is not clear. Inform
>> user with more descriptive message on how to fix the missing kernel
>> config option.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808
>>
>> Change-Id: Idfebaeababa4c37c1ef093c2b91a26910a167585
>> Signed-off-by: Philip Yang 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
>> index 4803e216e174..b155cac52aca 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
>> @@ -53,6 +53,8 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct 
>> amdgpu_device *adev,
>>   }
>>   static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long 
>> addr)
>>   {
>> +DRM_ERROR("HMM_MIRROR kernel config option is not enabled\n");
>> +DRM_ERROR("add CONFIG_ZONE_DEVICE=y in config file to fix this\n");
>>  return -ENODEV;
>>   }
>>   static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
>>
> 
> amdgpu_gem_userptr_ioctl calls amdgpu_mn_register if userspace sets the
> AMDGPU_GEM_USERPTR_REGISTER flag, so buggy/malicious userspace could
> spam dmesg with these errors. I'm afraid a different solution is needed.
> 
> The error message is inside dummy function amdgpu_mn_register, it only 
shows if kernel config option HMM is not enabled. Driver does need HMM 
kernel option to support userptr. We want to provide obvious message to 
users to update kernel config file from old kernel, otherwise all 
userptr related functions are broken. I will change this to WARN_ONCE to 
avoid spam dmesg.

Regards,
Philip
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Re: [PATCH] drm/amdgpu: force to use CPU_ACCESS hint optimization

[Chunming Zhou]

在 2019/3/6 20:30, Christian König 写道:
> Am 06.03.19 um 13:00 schrieb Zhou, David(ChunMing):
>>
>>> -Original Message-
>>> From: Christian König 
>>> Sent: Wednesday, March 06, 2019 7:55 PM
>>> To: Zhou, David(ChunMing) ; Koenig, Christian
>>> ; amd-gfx@lists.freedesktop.org
>>> Subject: Re: [PATCH] drm/amdgpu: force to use CPU_ACCESS hint
>>> optimization
>>>
>>> Am 06.03.19 um 12:52 schrieb Chunming Zhou:
 As we know, visible vram can be placed to invisible when no cpu 
 access.

 Signed-off-by: Chunming Zhou 
 ---
    drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 +++-
    1 file changed, 3 insertions(+), 5 deletions(-)

 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
 b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
 index bc62bf41b7e9..823deb66f5da 100644
 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
 +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
 @@ -592,8 +592,7 @@ static int amdgpu_info_ioctl(struct drm_device
 *dev, void *data, struct drm_file

    vram_gtt.vram_size = adev->gmc.real_vram_size -
    atomic64_read(>vram_pin_size);
 -    vram_gtt.vram_cpu_accessible_size = adev-
 gmc.visible_vram_size -
 -    atomic64_read(>visible_pin_size);
 +    vram_gtt.vram_cpu_accessible_size = vram_gtt.vram_size;
>>> Well, NAK that would of course report the full VRAM as visible which 
>>> isn't
>>> correct.
>> UMD also said same reason that they like report explicit vram info to 
>> application.
>
> Yeah, I mean that is a rather good argument. The application should 
> certainly know that.
>
>> No idea to do that.
>
> Well if I understood that correctly Vulkan had the same problem with 
> cached and uncached system memory. How is it handled there?

Which problem with cached and uncached system memory?

-David

>
> Christian.
>
>>
>> -David
>>> Christian.
>>>
    vram_gtt.gtt_size = adev-
 mman.bdev.man[TTM_PL_TT].size;
    vram_gtt.gtt_size *= PAGE_SIZE;
    vram_gtt.gtt_size -= atomic64_read(>gart_pin_size);
 @@ -612,9 +611,8 @@ static int amdgpu_info_ioctl(struct drm_device
>>> *dev, void *data, struct drm_file
    mem.vram.max_allocation = mem.vram.usable_heap_size *
>>> 3 / 4;
 mem.cpu_accessible_vram.total_heap_size =
 -    adev->gmc.visible_vram_size;
 -    mem.cpu_accessible_vram.usable_heap_size = adev-
 gmc.visible_vram_size -
 -    atomic64_read(>visible_pin_size);
 +    mem.vram.total_heap_size;
 +    mem.cpu_accessible_vram.usable_heap_size =
 +mem.vram.usable_heap_size;
    mem.cpu_accessible_vram.heap_usage =
    amdgpu_vram_mgr_vis_usage(
 mman.bdev.man[TTM_PL_VRAM]);
    mem.cpu_accessible_vram.max_allocation =
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Re: randr: Virtual monitor not present with MST display

[Paul Menzel]

Dear Alex,


On 03/05/19 20:07, Alex Deucher wrote:
> On Tue, Mar 5, 2019 at 1:16 PM Paul Menzel wrote:

>> Using the MST display Dell UP3214Q (two panels) with an AMD system,
>> the virtual monitor object is not created. GDM and Xfce consider both
>> panels as separate screens (`xrandr --listmonitors`).
>>
>> [0.00] Linux version 4.20.13.mx64.248 
>> (r...@holidayincambodia.molgen.mpg.de) (gcc version 7.3.0 (GCC)) #1 SMP Wed 
>> Feb 27 14:10:55 CET 2019
>>
>> [   79.494297] [drm] DM_MST: stopping TM on aconnector: a8109331 
>> [id: 56]
>> [   79.494362] [drm] DM_MST: Disabling connector: 776ea22b [id: 63] 
>> [master: a8109331]
>> [   79.494406] [drm] DM_MST: Disabling connector: 057ebdbb [id: 67] 
>> [master: a8109331]
>> [   79.781882] snd_hda_intel :00:1f.3: spurious response 0x0:0x2, last 
>> cmd=0x201f0500
>> [   86.028806] [drm] DM_MST: starting TM on aconnector: a8109331 
>> [id: 56]
>> [   86.053072] [drm] DM_MST: added connector: 1c9b49ed [id: 71] 
>> [master: a8109331]
>> [   86.108540] [drm] SADs count is: -2, don't need to read it
>> [   86.386661] [drm:create_stream_for_sink [amdgpu]] *ERROR* Failed to 
>> create stream for sink!
>> [   87.237878] [drm] DM_MST: added connector: c3ffcbbb [id: 80] 
>> [master: a8109331]
>> [   87.293028] [drm] SADs count is: -2, don't need to read it
>> [  206.993344] [drm] DM_MST: stopping TM on aconnector: a8109331 
>> [id: 56]
>> [  206.993423] [drm] DM_MST: Disabling connector: 1c9b49ed [id: 71] 
>> [master: a8109331]
>> [  206.993456] [drm] DM_MST: Disabling connector: c3ffcbbb [id: 80] 
>> [master: a8109331]
>> [  207.548051] [drm:create_stream_for_sink [amdgpu]] *ERROR* Failed to 
>> create stream for sink!
>> [  207.603193] [drm:create_stream_for_sink [amdgpu]] *ERROR* Failed to 
>> create stream for sink!
>> [  207.762388] traps: xfdesktop[2225] general protection fault 
>> ip:7f588981226c sp:7ffee65af370 error:0 in 
>> libgobject-2.0.so.0.5800.1[7f58897da000+56000]
>> [  210.320612] [drm] DM_MST: starting TM on aconnector: b456cd59 
>> [id: 62]
>> [  210.343497] [drm] DM_MST: added connector: 735839d5 [id: 73] 
>> [master: b456cd59]
>> [  210.399168] [drm] SADs count is: -2, don't need to read it
>> [  210.404454] [drm] DM_MST: added connector: cccb0c2d [id: 88] 
>> [master: b456cd59]
>> [  210.675589] [drm] SADs count is: -2, don't need to read it

I didn’t provide the output of xrandr in my previous message.

$ xrandr --listmonitors
 Monitors: 2
 0: +DisplayPort-9 1920/698x2160/392+0+0  DisplayPort-9
 1: +DisplayPort-10 1920/698x2160/392+1920+0  DisplayPort-10

Please find the X.Org X Server log attached.

>> With an Intel system, the monitor object is shown.

To clarify, the modesetting driver is used with the Intel hardware.

>> $ xrandr --listmonitors
>> Monitors: 1
>>  0: +Auto-Monitor-1 3840/698x2160/392+0+0  DP-1-9 DP-1-8
>>
>> Do you have an idea, what the AMD drivers does differently, and how
>> to fix this?
> 
> + dri-devel
> 
> My understanding is that this is handled at the Desktop level rather
> than the driver.  X exposes the tile info via randr 1.5 and the
> desktop environment should handle it as a single monitor.  Mutter
> handles this in GNOME for example.
> 
> https://cgit.freedesktop.org/xorg/xserver/commit/?id=7e1f86d42b54fb7f6492875e47a718eaeca3069b
> https://lists.x.org/archives/xorg-announce/2015-May/002605.html
> https://mail.gnome.org/archives/desktop-devel-list/2015-November/msg00018.html

As it works with the modesetting driver, it looks to me like Xfce
supports it, and it’s a driver issue. The Linux error messages
also do not look promising. Any idea, if they are related?
Lastly, shouldn’t at least the output of `xrandr` be correct, if
everything is set up correctly?


Kind regards,

Paul
[57.665] 
X.Org X Server 1.20.4
X Protocol Version 11, Revision 0
[57.665] Build Operating System: Linux 4.19.19.mx64.244 x86_64 
[57.665] Current Operating System: Linux inbetweenmove.molgen.mpg.de 4.19.19.mx64.244 #1 SMP Tue Feb 5 13:01:13 CET 2019 x86_64
[57.665] Kernel command line: BOOT_IMAGE=/boot/bzImage-4.19.19.mx64.244 crashkernel=256M root=LABEL=root ro console=ttyS1,115200n8 console=tty0 init=/bin/systemd audit=0
[57.665] Build Date: 27 February 2019  12:32:24PM
[57.665]  
[57.665] Current version of pixman: 0.38.0
[57.665] 	Before reporting problems, check http://wiki.x.org
	to make sure that you have the latest version.
[57.665] Markers: (--) probed, (**) from config file, (==) default setting,
	(++) from command line, (!!) notice, (II) informational,
	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
[57.665] (==) Log file: "/var/log/Xorg.0.log", Time: Wed Mar  6 13:24:58 2019
[57.665] (==) Using config directory: "/etc/X11/xorg.conf.d"
[57.665] (==) Using system 

RE: [PATCH] drm/amd/powerplay: simplify sw-smu message map macro

[Huang, Ray]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Wang, Kevin(Yang)
> Sent: Wednesday, March 06, 2019 7:53 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Wang, Kevin(Yang)
> 
> Subject: [PATCH] drm/amd/powerplay: simplify sw-smu message map macro
> 
> simplify macro of MSG_MAP for sw-smu
> 
> Signed-off-by:Kevin Wang 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 170 ++
> ---
>  1 file changed, 85 insertions(+), 85 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> index c9cc7bb..f4869353 100644
> --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> @@ -40,8 +40,8 @@
>  #define smnPCIE_LC_SPEED_CNTL0x11140290
>  #define smnPCIE_LC_LINK_WIDTH_CNTL   0x11140288
> 
> -#define MSG_MAP(msg, index) \
> - [SMU_MSG_##msg] = index
> +#define MSG_MAP(msg) \
> + [SMU_MSG_##msg] = PPSMC_MSG_##msg
> 
>  #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
>FEATURE_DPM_GFXCLK_MASK | \
> @@ -54,89 +54,89 @@
>FEATURE_DPM_DCEFCLK_MASK)
> 
>  static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
> - MSG_MAP(TestMessage,
>   PPSMC_MSG_TestMessage),
> - MSG_MAP(GetSmuVersion,
>   PPSMC_MSG_GetSmuVersion),
> - MSG_MAP(GetDriverIfVersion,
>   PPSMC_MSG_GetDriverIfVersion),
> - MSG_MAP(SetAllowedFeaturesMaskLow,
>   PPSMC_MSG_SetAllowedFeaturesMaskLow),
> - MSG_MAP(SetAllowedFeaturesMaskHigh,
>   PPSMC_MSG_SetAllowedFeaturesMaskHigh),
> - MSG_MAP(EnableAllSmuFeatures,
>   PPSMC_MSG_EnableAllSmuFeatures),
> - MSG_MAP(DisableAllSmuFeatures,
>   PPSMC_MSG_DisableAllSmuFeatures),
> - MSG_MAP(EnableSmuFeaturesLow,
>   PPSMC_MSG_EnableSmuFeaturesLow),
> - MSG_MAP(EnableSmuFeaturesHigh,
>   PPSMC_MSG_EnableSmuFeaturesHigh),
> - MSG_MAP(DisableSmuFeaturesLow,
>   PPSMC_MSG_DisableSmuFeaturesLow),
> - MSG_MAP(DisableSmuFeaturesHigh,
>   PPSMC_MSG_DisableSmuFeaturesHigh),
> - MSG_MAP(GetEnabledSmuFeaturesLow,
>   PPSMC_MSG_GetEnabledSmuFeaturesLow),
> - MSG_MAP(GetEnabledSmuFeaturesHigh,
>   PPSMC_MSG_GetEnabledSmuFeaturesHigh),
> - MSG_MAP(SetWorkloadMask,
>   PPSMC_MSG_SetWorkloadMask),
> - MSG_MAP(SetPptLimit,
>   PPSMC_MSG_SetPptLimit),
> - MSG_MAP(SetDriverDramAddrHigh,
>   PPSMC_MSG_SetDriverDramAddrHigh),
> - MSG_MAP(SetDriverDramAddrLow,
>   PPSMC_MSG_SetDriverDramAddrLow),
> - MSG_MAP(SetToolsDramAddrHigh,
>   PPSMC_MSG_SetToolsDramAddrHigh),
> - MSG_MAP(SetToolsDramAddrLow,
>   PPSMC_MSG_SetToolsDramAddrLow),
> - MSG_MAP(TransferTableSmu2Dram,
>   PPSMC_MSG_TransferTableSmu2Dram),
> - MSG_MAP(TransferTableDram2Smu,
>   PPSMC_MSG_TransferTableDram2Smu),
> - MSG_MAP(UseDefaultPPTable,
>   PPSMC_MSG_UseDefaultPPTable),
> - MSG_MAP(UseBackupPPTable,
>   PPSMC_MSG_UseBackupPPTable),
> - MSG_MAP(RunBtc,
>   PPSMC_MSG_RunBtc),
> - MSG_MAP(RequestI2CBus,
>   PPSMC_MSG_RequestI2CBus),
> - MSG_MAP(ReleaseI2CBus,
>   PPSMC_MSG_ReleaseI2CBus),
> - MSG_MAP(SetFloorSocVoltage,
>   PPSMC_MSG_SetFloorSocVoltage),
> - MSG_MAP(SoftReset,  PPSMC_MSG_SoftReset),
> - MSG_MAP(StartBacoMonitor,
>   PPSMC_MSG_StartBacoMonitor),
> - MSG_MAP(CancelBacoMonitor,
>   PPSMC_MSG_CancelBacoMonitor),
> - MSG_MAP(EnterBaco,  PPSMC_MSG_EnterBaco),
> - MSG_MAP(SetSoftMinByFreq,
>   PPSMC_MSG_SetSoftMinByFreq),
> - MSG_MAP(SetSoftMaxByFreq,
>   PPSMC_MSG_SetSoftMaxByFreq),
> - MSG_MAP(SetHardMinByFreq,
>   PPSMC_MSG_SetHardMinByFreq),
> - MSG_MAP(SetHardMaxByFreq,
>   PPSMC_MSG_SetHardMaxByFreq),
> - MSG_MAP(GetMinDpmFreq,
>   PPSMC_MSG_GetMinDpmFreq),
> - MSG_MAP(GetMaxDpmFreq,
>   PPSMC_MSG_GetMaxDpmFreq),
> - MSG_MAP(GetDpmFreqByIndex,
>   PPSMC_MSG_GetDpmFreqByIndex),
> - MSG_MAP(GetDpmClockFreq,
>   PPSMC_MSG_GetDpmClockFreq),
> - MSG_MAP(GetSsVoltageByDpm,
>   PPSMC_MSG_GetSsVoltageByDpm),
> - MSG_MAP(SetMemoryChannelConfig,
>   PPSMC_MSG_SetMemoryChannelConfig),
> - MSG_MAP(SetGeminiMode,
>   PPSMC_MSG_SetGeminiMode),
> - MSG_MAP(SetGeminiApertureHigh,
>   PPSMC_MSG_SetGeminiApertureHigh),
> - MSG_MAP(SetGeminiApertureLow,
>   PPSMC_MSG_SetGeminiApertureLow),
> - MSG_MAP(SetMinLinkDpmByIndex,
>   PPSMC_MSG_SetMinLinkDpmByIndex),
> - MSG_MAP(OverridePcieParameters,
>   PPSMC_MSG_OverridePcieParameters),
> - MSG_MAP(OverDriveSetPercentage,
>   PPSMC_MSG_OverDriveSetPercentage),
> - MSG_MAP(SetMinDeepSleepDcefclk,
>   PPSMC_MSG_SetMinDeepSleepDcefclk),
> - MSG_MAP(ReenableAcDcInterrupt,
>   

Re: [PATCH] drm/amdgpu: force to use CPU_ACCESS hint optimization

[Christian König]

Am 06.03.19 um 13:00 schrieb Zhou, David(ChunMing):



-Original Message-
From: Christian König 
Sent: Wednesday, March 06, 2019 7:55 PM
To: Zhou, David(ChunMing) ; Koenig, Christian
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: force to use CPU_ACCESS hint
optimization

Am 06.03.19 um 12:52 schrieb Chunming Zhou:

As we know, visible vram can be placed to invisible when no cpu access.

Signed-off-by: Chunming Zhou 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 +++-
   1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bc62bf41b7e9..823deb66f5da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -592,8 +592,7 @@ static int amdgpu_info_ioctl(struct drm_device
*dev, void *data, struct drm_file

vram_gtt.vram_size = adev->gmc.real_vram_size -
atomic64_read(>vram_pin_size);
-   vram_gtt.vram_cpu_accessible_size = adev-
gmc.visible_vram_size -
-   atomic64_read(>visible_pin_size);
+   vram_gtt.vram_cpu_accessible_size = vram_gtt.vram_size;

Well, NAK that would of course report the full VRAM as visible which isn't
correct.

UMD also said same reason that they like report explicit vram info to 
application.


Yeah, I mean that is a rather good argument. The application should 
certainly know that.



No idea to do that.


Well if I understood that correctly Vulkan had the same problem with 
cached and uncached system memory. How is it handled there?


Christian.



-David

Christian.


vram_gtt.gtt_size = adev-
mman.bdev.man[TTM_PL_TT].size;
vram_gtt.gtt_size *= PAGE_SIZE;
vram_gtt.gtt_size -= atomic64_read(>gart_pin_size);
@@ -612,9 +611,8 @@ static int amdgpu_info_ioctl(struct drm_device

*dev, void *data, struct drm_file

mem.vram.max_allocation = mem.vram.usable_heap_size *

3 / 4;

mem.cpu_accessible_vram.total_heap_size =
-   adev->gmc.visible_vram_size;
-   mem.cpu_accessible_vram.usable_heap_size = adev-
gmc.visible_vram_size -
-   atomic64_read(>visible_pin_size);
+   mem.vram.total_heap_size;
+   mem.cpu_accessible_vram.usable_heap_size =
+mem.vram.usable_heap_size;
mem.cpu_accessible_vram.heap_usage =
amdgpu_vram_mgr_vis_usage(
mman.bdev.man[TTM_PL_VRAM]);
mem.cpu_accessible_vram.max_allocation =

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RE: [PATCH] drm/amdgpu: force to use CPU_ACCESS hint optimization

[Zhou, David(ChunMing)]

> -Original Message-
> From: Christian König 
> Sent: Wednesday, March 06, 2019 7:55 PM
> To: Zhou, David(ChunMing) ; Koenig, Christian
> ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: force to use CPU_ACCESS hint
> optimization
> 
> Am 06.03.19 um 12:52 schrieb Chunming Zhou:
> > As we know, visible vram can be placed to invisible when no cpu access.
> >
> > Signed-off-by: Chunming Zhou 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 +++-
> >   1 file changed, 3 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index bc62bf41b7e9..823deb66f5da 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -592,8 +592,7 @@ static int amdgpu_info_ioctl(struct drm_device
> > *dev, void *data, struct drm_file
> >
> > vram_gtt.vram_size = adev->gmc.real_vram_size -
> > atomic64_read(>vram_pin_size);
> > -   vram_gtt.vram_cpu_accessible_size = adev-
> >gmc.visible_vram_size -
> > -   atomic64_read(>visible_pin_size);
> > +   vram_gtt.vram_cpu_accessible_size = vram_gtt.vram_size;
> 
> Well, NAK that would of course report the full VRAM as visible which isn't
> correct.

UMD also said same reason that they like report explicit vram info to 
application.
No idea to do that.

-David
> 
> Christian.
> 
> > vram_gtt.gtt_size = adev-
> >mman.bdev.man[TTM_PL_TT].size;
> > vram_gtt.gtt_size *= PAGE_SIZE;
> > vram_gtt.gtt_size -= atomic64_read(>gart_pin_size);
> > @@ -612,9 +611,8 @@ static int amdgpu_info_ioctl(struct drm_device
> *dev, void *data, struct drm_file
> > mem.vram.max_allocation = mem.vram.usable_heap_size *
> 3 / 4;
> >
> > mem.cpu_accessible_vram.total_heap_size =
> > -   adev->gmc.visible_vram_size;
> > -   mem.cpu_accessible_vram.usable_heap_size = adev-
> >gmc.visible_vram_size -
> > -   atomic64_read(>visible_pin_size);
> > +   mem.vram.total_heap_size;
> > +   mem.cpu_accessible_vram.usable_heap_size =
> > +mem.vram.usable_heap_size;
> > mem.cpu_accessible_vram.heap_usage =
> > amdgpu_vram_mgr_vis_usage(
> >mman.bdev.man[TTM_PL_VRAM]);
> > mem.cpu_accessible_vram.max_allocation =

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Re: [PATCH] drm/amdgpu: force to use CPU_ACCESS hint optimization

[Christian König]

Am 06.03.19 um 12:52 schrieb Chunming Zhou:

As we know, visible vram can be placed to invisible when no cpu access.

Signed-off-by: Chunming Zhou 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 +++-
  1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bc62bf41b7e9..823deb66f5da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -592,8 +592,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
  
  		vram_gtt.vram_size = adev->gmc.real_vram_size -

atomic64_read(>vram_pin_size);
-   vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size 
-
-   atomic64_read(>visible_pin_size);
+   vram_gtt.vram_cpu_accessible_size = vram_gtt.vram_size;


Well, NAK that would of course report the full VRAM as visible which 
isn't correct.


Christian.


vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
vram_gtt.gtt_size *= PAGE_SIZE;
vram_gtt.gtt_size -= atomic64_read(>gart_pin_size);
@@ -612,9 +611,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
  
  		mem.cpu_accessible_vram.total_heap_size =

-   adev->gmc.visible_vram_size;
-   mem.cpu_accessible_vram.usable_heap_size = 
adev->gmc.visible_vram_size -
-   atomic64_read(>visible_pin_size);
+   mem.vram.total_heap_size;
+   mem.cpu_accessible_vram.usable_heap_size = 
mem.vram.usable_heap_size;
mem.cpu_accessible_vram.heap_usage =

amdgpu_vram_mgr_vis_usage(>mman.bdev.man[TTM_PL_VRAM]);
mem.cpu_accessible_vram.max_allocation =


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RE: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config

[Zhou, David(ChunMing)]

Acked-by: Chunming Zhou 


> -Original Message-
> From: amd-gfx  On Behalf Of
> Christian K?nig
> Sent: Wednesday, March 06, 2019 5:29 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config
> 
> Ping? Can anybody review this?
> 
> Thanks,
> Christian.
> 
> Am 04.03.19 um 20:10 schrieb Christian König:
> > Disable overflow and enable full drain. This makes fault handling on
> > ring 1 much more reliable since we don't generate back pressure any more.
> >
> > Signed-off-by: Christian König 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 
> >   1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > index 6d1f804277f8..d4a3cc413af8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > @@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct
> > amdgpu_device *adev)
> >
> > ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
> mmIH_RB_CNTL_RING1);
> > ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
> > +   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> > +  WPTR_OVERFLOW_ENABLE, 0);
> > +   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> > +  RB_FULL_DRAIN_ENABLE, 1);
> > WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1,
> ih_rb_cntl);
> >
> > /* set rptr, wptr to 0 */
> 
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[PATCH] drm/amd/powerplay: simplify sw-smu message map macro

[Wang, Kevin(Yang)]

simplify macro of MSG_MAP for sw-smu

Signed-off-by:Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 170 ++---
 1 file changed, 85 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c 
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index c9cc7bb..f4869353 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -40,8 +40,8 @@
 #define smnPCIE_LC_SPEED_CNTL  0x11140290
 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
 
-#define MSG_MAP(msg, index) \
-   [SMU_MSG_##msg] = index
+#define MSG_MAP(msg) \
+   [SMU_MSG_##msg] = PPSMC_MSG_##msg
 
 #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
 FEATURE_DPM_GFXCLK_MASK | \
@@ -54,89 +54,89 @@
 FEATURE_DPM_DCEFCLK_MASK)
 
 static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
-   MSG_MAP(TestMessage,PPSMC_MSG_TestMessage),
-   MSG_MAP(GetSmuVersion,  PPSMC_MSG_GetSmuVersion),
-   MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
-   MSG_MAP(SetAllowedFeaturesMaskLow,  
PPSMC_MSG_SetAllowedFeaturesMaskLow),
-   MSG_MAP(SetAllowedFeaturesMaskHigh, 
PPSMC_MSG_SetAllowedFeaturesMaskHigh),
-   MSG_MAP(EnableAllSmuFeatures,   PPSMC_MSG_EnableAllSmuFeatures),
-   MSG_MAP(DisableAllSmuFeatures,  
PPSMC_MSG_DisableAllSmuFeatures),
-   MSG_MAP(EnableSmuFeaturesLow,   PPSMC_MSG_EnableSmuFeaturesLow),
-   MSG_MAP(EnableSmuFeaturesHigh,  
PPSMC_MSG_EnableSmuFeaturesHigh),
-   MSG_MAP(DisableSmuFeaturesLow,  
PPSMC_MSG_DisableSmuFeaturesLow),
-   MSG_MAP(DisableSmuFeaturesHigh, 
PPSMC_MSG_DisableSmuFeaturesHigh),
-   MSG_MAP(GetEnabledSmuFeaturesLow,   
PPSMC_MSG_GetEnabledSmuFeaturesLow),
-   MSG_MAP(GetEnabledSmuFeaturesHigh,  
PPSMC_MSG_GetEnabledSmuFeaturesHigh),
-   MSG_MAP(SetWorkloadMask,PPSMC_MSG_SetWorkloadMask),
-   MSG_MAP(SetPptLimit,PPSMC_MSG_SetPptLimit),
-   MSG_MAP(SetDriverDramAddrHigh,  
PPSMC_MSG_SetDriverDramAddrHigh),
-   MSG_MAP(SetDriverDramAddrLow,   PPSMC_MSG_SetDriverDramAddrLow),
-   MSG_MAP(SetToolsDramAddrHigh,   PPSMC_MSG_SetToolsDramAddrHigh),
-   MSG_MAP(SetToolsDramAddrLow,PPSMC_MSG_SetToolsDramAddrLow),
-   MSG_MAP(TransferTableSmu2Dram,  
PPSMC_MSG_TransferTableSmu2Dram),
-   MSG_MAP(TransferTableDram2Smu,  
PPSMC_MSG_TransferTableDram2Smu),
-   MSG_MAP(UseDefaultPPTable,  PPSMC_MSG_UseDefaultPPTable),
-   MSG_MAP(UseBackupPPTable,   PPSMC_MSG_UseBackupPPTable),
-   MSG_MAP(RunBtc, PPSMC_MSG_RunBtc),
-   MSG_MAP(RequestI2CBus,  PPSMC_MSG_RequestI2CBus),
-   MSG_MAP(ReleaseI2CBus,  PPSMC_MSG_ReleaseI2CBus),
-   MSG_MAP(SetFloorSocVoltage, PPSMC_MSG_SetFloorSocVoltage),
-   MSG_MAP(SoftReset,  PPSMC_MSG_SoftReset),
-   MSG_MAP(StartBacoMonitor,   PPSMC_MSG_StartBacoMonitor),
-   MSG_MAP(CancelBacoMonitor,  PPSMC_MSG_CancelBacoMonitor),
-   MSG_MAP(EnterBaco,  PPSMC_MSG_EnterBaco),
-   MSG_MAP(SetSoftMinByFreq,   PPSMC_MSG_SetSoftMinByFreq),
-   MSG_MAP(SetSoftMaxByFreq,   PPSMC_MSG_SetSoftMaxByFreq),
-   MSG_MAP(SetHardMinByFreq,   PPSMC_MSG_SetHardMinByFreq),
-   MSG_MAP(SetHardMaxByFreq,   PPSMC_MSG_SetHardMaxByFreq),
-   MSG_MAP(GetMinDpmFreq,  PPSMC_MSG_GetMinDpmFreq),
-   MSG_MAP(GetMaxDpmFreq,  PPSMC_MSG_GetMaxDpmFreq),
-   MSG_MAP(GetDpmFreqByIndex,  PPSMC_MSG_GetDpmFreqByIndex),
-   MSG_MAP(GetDpmClockFreq,PPSMC_MSG_GetDpmClockFreq),
-   MSG_MAP(GetSsVoltageByDpm,  PPSMC_MSG_GetSsVoltageByDpm),
-   MSG_MAP(SetMemoryChannelConfig, 
PPSMC_MSG_SetMemoryChannelConfig),
-   MSG_MAP(SetGeminiMode,  PPSMC_MSG_SetGeminiMode),
-   MSG_MAP(SetGeminiApertureHigh,  
PPSMC_MSG_SetGeminiApertureHigh),
-   MSG_MAP(SetGeminiApertureLow,   PPSMC_MSG_SetGeminiApertureLow),
-   MSG_MAP(SetMinLinkDpmByIndex,   PPSMC_MSG_SetMinLinkDpmByIndex),
-   MSG_MAP(OverridePcieParameters, 
PPSMC_MSG_OverridePcieParameters),
-   MSG_MAP(OverDriveSetPercentage, 
PPSMC_MSG_OverDriveSetPercentage),
-   MSG_MAP(SetMinDeepSleepDcefclk, 
PPSMC_MSG_SetMinDeepSleepDcefclk),
-   MSG_MAP(ReenableAcDcInterrupt,  
PPSMC_MSG_ReenableAcDcInterrupt),
-   MSG_MAP(NotifyPowerSource,  PPSMC_MSG_NotifyPowerSource),
-   MSG_MAP(SetUclkFastSwitch,  PPSMC_MSG_SetUclkFastSwitch),
-   

[PATCH] drm/amdgpu: force to use CPU_ACCESS hint optimization

[Chunming Zhou]

As we know, visible vram can be placed to invisible when no cpu access.

Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bc62bf41b7e9..823deb66f5da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -592,8 +592,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
 
vram_gtt.vram_size = adev->gmc.real_vram_size -
atomic64_read(>vram_pin_size);
-   vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size 
-
-   atomic64_read(>visible_pin_size);
+   vram_gtt.vram_cpu_accessible_size = vram_gtt.vram_size;
vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
vram_gtt.gtt_size *= PAGE_SIZE;
vram_gtt.gtt_size -= atomic64_read(>gart_pin_size);
@@ -612,9 +611,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 
mem.cpu_accessible_vram.total_heap_size =
-   adev->gmc.visible_vram_size;
-   mem.cpu_accessible_vram.usable_heap_size = 
adev->gmc.visible_vram_size -
-   atomic64_read(>visible_pin_size);
+   mem.vram.total_heap_size;
+   mem.cpu_accessible_vram.usable_heap_size = 
mem.vram.usable_heap_size;
mem.cpu_accessible_vram.heap_usage =

amdgpu_vram_mgr_vis_usage(>mman.bdev.man[TTM_PL_VRAM]);
mem.cpu_accessible_vram.max_allocation =
-- 
2.17.1

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[ANNOUNCE] xf86-video-amdgpu 19.0.0

[Michel Dänzer]

I'm pleased to announce the 19.0.0 release of xf86-video-amdgpu, the
Xorg driver for AMD Radeon GPUs supported by the amdgpu kernel driver.
This release supports xserver versions 1.13-1.20.

Highlights:

* Support for FreeSync variable refresh rate (this also requires the
  amdgpu driver from kernel 5.0 or newer, and radeonsi from Mesa 19.0 or
  newer).
* Various TearFree related fixes and robustness improvements.
* Support for scanout buffers using DCC colour compression.
* Up to six independent instances per GPU are now supported in "Zaphod"
  style multi-head configurations.

Plus other improvements and fixes. Thanks to everybody who contributed
to this release in any way!


Mario Kleiner (1):
  Fix crash when page flipping in multi-X-Screen/Zaphod mode

Michel Dänzer (53):
  Post-release version bump
  Convert README to markdown
  Handle pending scanout update in drmmode_crtc_scanout_free
  Make wait_pending_flip / handle_deferred symmetric in set_mode_major
  Cast return value of amdgpu_get_marketing_name to char*
  Fix --disable-glamor build
  Add GitLab CI configuration
  Fix condition for calling set_pixmap_bo in drmmode_xf86crtc_resize
  Allow up to six instances in Zaphod mode
  Detect and fix up non-premultiplied cursor data
  glamor: Can work at depth >= 15 with current xserver Git master
  man: This driver supports colour depths 8, 15 and 16
  Add README.md to EXTRA_DIST
  Relax detection of non-premultiplied alpha cursor data
  Use drm_abort_one in drm_queue_handler
  Explicitly keep track of whether a DRM event is for a flip or not
  Move deferred vblank events to separate drm_vblank_deferred list
  Skip gamma correction of cursor data if premultiplied R/G/B > alpha
  Generate docker image as part of CI pipeline
  Perform scanout buffer update immediately if drmmode_wait_vblank fails
  Cancel pending scanout update in drmmode_crtc_scanout_update
  Automatically try re-enabling TearFree after a flip failed
  Don't use GBM for allocating HW cursor BOs
  Drop AMDGPUInfoRec::cursor_buffer array
  Use drmIoctl in drmmode_show_cursor
  Update cursor position in drmmode_show_cursor if hotspot changed
  Use two HW cursor buffers per CRTC
  Don't clear info->flip_window in present_unflip
  Remove superfluous vrr_flipping field and clean up related code
  gitlab-ci: Use kaniko instead of docker-in-docker for image generation
  Only call drmmode_uevent_init if RandR is enabled
  Only call drmmode_validate_leases if RandR is enabled
  dri3: Flush if necessary in dri3_fd_from_pixmap
  dri2: Flush in dri2_create_buffer2 after calling glamor_set_pixmap_bo
  glamor: Avoid glamor_create_pixmap for pixmaps backing windows
  Don't allow TearFree scanout flips to complete in the same vblank period
  Only update drmmode_crtc->flip_pending after actually submitting a flip
  Call drmHandleEvent again if it was interrupted by a signal
  Keep waiting for a pending flip if drm_handle_event returns 0
  gitlab-ci: Only run docker-image stage if relevant source files change
  gitlab-ci: Don't rely on $CI_PROJECT_NAME
  Don't register a window private if VRR is disabled
  Don't enable the VRR support code for GPU screens
  Wrap change/delete window property request handlers
  Make use of property request wrappers for VRR property
  Call amdgpu_present_set_screen_vrr from amdgpu_vrr_property_update
  present: Check that flip and screen pixmap pitches match
  dri2: Call drm_queue_handle_deferred in dri2_deferred_event
  Revert "gitlab-ci: Only run docker-image stage if relevant source files 
change"
  Revert "Remove set but unused amdgpu_dri2::pKernelDRMVersion"
  Make drmmode_cm_enabled an inline function
  present: Don't check tiling parameters with DC & DRM minor version >= 31
  Bump version for the 19.0.0 release

Nicholas Kazlauskas (2):
  Check last flip window instead of screen root before flipping
  Support CRTC variable refresh for windows using Present flips

git tag: xf86-video-amdgpu-19.0.0

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-19.0.0.tar.bz2
MD5:  a9a1bee983e570614a78ae9070223149  xf86-video-amdgpu-19.0.0.tar.bz2
SHA1: 7a9c6f08ec7c0a8cc665079c8f49716febc73729  xf86-video-amdgpu-19.0.0.tar.bz2
SHA256: 8836147d4755908ec9e192b7cc485fbc2ce7706de33f7bea515294d3ba4c4f51  
xf86-video-amdgpu-19.0.0.tar.bz2
SHA512: 
6a30fc03185816307f16693cd6b07f13694ca1b6b1327c58a951bccc8082f112bb768ab610229dc1040617eef860fc1ab17a7e6bf635c5a4e454e252f3addca8
  xf86-video-amdgpu-19.0.0.tar.bz2
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-19.0.0.tar.bz2.sig

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-19.0.0.tar.gz
MD5:  0bac9edb72a3692c878647da7eed3f79  xf86-video-amdgpu-19.0.0.tar.gz
SHA1: 

Re: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config

[Christian König]

Ping? Can anybody review this?

Thanks,
Christian.

Am 04.03.19 um 20:10 schrieb Christian König:

Disable overflow and enable full drain. This makes fault handling on ring 1
much more reliable since we don't generate back pressure any more.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 6d1f804277f8..d4a3cc413af8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
  
  		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);

ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+  WPTR_OVERFLOW_ENABLE, 0);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+  RB_FULL_DRAIN_ENABLE, 1);
WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
  
  		/* set rptr, wptr to 0 */


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Re: [PATCH 3/3] drm/amdgpu: more descriptive message if HMM not enabled

[Michel Dänzer]

On 2019-03-05 7:09 p.m., Yang, Philip wrote:
> If using old kernel config file, CONFIG_ZONE_DEVICE is not selected,
> so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver
> error message "Failed to register MMU notifier" is not clear. Inform
> user with more descriptive message on how to fix the missing kernel
> config option.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808
> 
> Change-Id: Idfebaeababa4c37c1ef093c2b91a26910a167585
> Signed-off-by: Philip Yang 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
> index 4803e216e174..b155cac52aca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
> @@ -53,6 +53,8 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct 
> amdgpu_device *adev,
>  }
>  static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long 
> addr)
>  {
> + DRM_ERROR("HMM_MIRROR kernel config option is not enabled\n");
> + DRM_ERROR("add CONFIG_ZONE_DEVICE=y in config file to fix this\n");
>   return -ENODEV;
>  }
>  static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
> 

amdgpu_gem_userptr_ioctl calls amdgpu_mn_register if userspace sets the
AMDGPU_GEM_USERPTR_REGISTER flag, so buggy/malicious userspace could
spam dmesg with these errors. I'm afraid a different solution is needed.


-- 
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Libre software enthusiast | Mesa and X developer
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Re: [PATCH] drm/amdkfd: Fix "-Wmisleading-indentation" warning

[Michel Dänzer]

On 2019-03-05 8:28 p.m., sunpeng...@amd.com wrote:
> From: Leo Li 
> 
> The following warning is seen during compile:
> 
> ./include/linux/idr.h:212:2: warning: this ‘for’ clause does not
> guard... [-Wmisleading-indentation]
>   for ((entry) = idr_get_next((idr), &(id));   \
>   ^
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.c:1038:3: note: in
> expansion of macro ‘idr_for_each_entry_continue’
>idr_for_each_entry_continue(>event_idr, ev, id)
>^~~
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.c:1043:4: note: ...this
> statement, but the latter is misleadingly indented as if it were guarded
> by the ‘for’
> if (ev->type == KFD_EVENT_TYPE_MEMORY &&
> ^~
> 
> Place braces around the indented block, as seemingly intended.
> 
> Signed-off-by: Leo Li 

Thanks Leo, but I already sent a fix for this:

https://patchwork.freedesktop.org/patch/290410/


-- 
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Re: [PATCH v2] tests/amdgpu: add deadlock test for sdma

[Christian König]

Am 06.03.19 um 07:37 schrieb Cui, Flora:

deadlock test for sdma will cause gpu recoverty.
disable the test for now until GPU reset recovery could survive at least
1000 times test.

v2: add modprobe parameter

Change-Id: I9adac63c62db22107345eddb30e7d81a1bda838c
Signed-off-by: Flora Cui 


Acked-by: Christian König 


---
  tests/amdgpu/amdgpu_test.c|   4 ++
  tests/amdgpu/deadlock_tests.c | 103 +-
  2 files changed, 106 insertions(+), 1 deletion(-)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index ebf4409..38b8a68 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -426,6 +426,10 @@ static void amdgpu_disable_suites()
"compute ring block test (set 
amdgpu.lockup_timeout=50)", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", 
CU_get_error_msg());
  
+	if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,

+   "sdma ring block test (set 
amdgpu.lockup_timeout=50)", CU_FALSE))
+   fprintf(stderr, "test deactivation failed - %s\n", 
CU_get_error_msg());
+
if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", 
CU_get_error_msg());
  
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c

index a6c2635..91368c1 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -96,6 +96,9 @@
  
  #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR  0x54f
  
+#define SDMA_PKT_HEADER_OP(x)	(x & 0xff)

+#define SDMA_OP_POLL_REGMEM  8
+
  static  amdgpu_device_handle device_handle;
  static  uint32_t  major_version;
  static  uint32_t  minor_version;
@@ -110,6 +113,7 @@ static void amdgpu_deadlock_gfx(void);
  static void amdgpu_deadlock_compute(void);
  static void amdgpu_illegal_reg_access();
  static void amdgpu_illegal_mem_access();
+static void amdgpu_deadlock_sdma(void);
  
  CU_BOOL suite_deadlock_tests_enable(void)

  {
@@ -171,6 +175,7 @@ int suite_deadlock_tests_clean(void)
  CU_TestInfo deadlock_tests[] = {
{ "gfx ring block test (set amdgpu.lockup_timeout=50)", 
amdgpu_deadlock_gfx },
{ "compute ring block test (set amdgpu.lockup_timeout=50)", 
amdgpu_deadlock_compute },
+   { "sdma ring block test (set amdgpu.lockup_timeout=50)", 
amdgpu_deadlock_sdma },
{ "illegal reg access test", amdgpu_illegal_reg_access },
{ "illegal mem access test (set amdgpu.vm_fault_stop=2)", 
amdgpu_illegal_mem_access },
CU_TEST_INFO_NULL,
@@ -260,7 +265,6 @@ static void amdgpu_deadlock_helper(unsigned ip_type)
ibs_request.ibs = _info;
ibs_request.resources = bo_list;
ibs_request.fence_info.handle = NULL;
-
for (i = 0; i < 200; i++) {
r = amdgpu_cs_submit(context_handle, 0,_request, 1);
CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
@@ -291,6 +295,103 @@ static void amdgpu_deadlock_helper(unsigned ip_type)
CU_ASSERT_EQUAL(r, 0);
  }
  
+static void amdgpu_deadlock_sdma(void)

+{
+   amdgpu_context_handle context_handle;
+   amdgpu_bo_handle ib_result_handle;
+   void *ib_result_cpu;
+   uint64_t ib_result_mc_address;
+   struct amdgpu_cs_request ibs_request;
+   struct amdgpu_cs_ib_info ib_info;
+   struct amdgpu_cs_fence fence_status;
+   uint32_t expired;
+   int i, r;
+   amdgpu_bo_list_handle bo_list;
+   amdgpu_va_handle va_handle;
+   struct drm_amdgpu_info_hw_ip info;
+   uint32_t ring_id;
+
+   r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, );
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = amdgpu_cs_ctx_create(device_handle, _handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
+   r = pthread_create(_thread, NULL, write_mem_address, 
NULL);
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
+   AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? 
AMDGPU_VM_MTYPE_UC : 0,
+   _result_handle, 
_result_cpu,
+   _result_mc_address, 
_handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+  _list);
+   CU_ASSERT_EQUAL(r, 0);
+
+   ptr = ib_result_cpu;
+   i = 0;
+
+   ptr[i++] = SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+   (0 << 26) | /* WAIT_REG_MEM */
+   (4 << 28) | /* != */
+   (1 << 31); /* memory */
+   ptr[i++] = (ib_result_mc_address + 256*4) & 0xfffc;
+   ptr[i++] = 

Re: [PATCH v2] drm/amdgpu: Add sysfs entries for xgmi hive.

[Christian König]

Am 05.03.19 um 20:30 schrieb Andrey Grodzovsky:

For each device a file xgmi_device_id is created.
On the first device a subdirectory named xgmi_hive_info is created,
It contains  a file named hive_id and symlinks named node 1-4 linking
to each device in the hive.

v2: Return error codes instead of '-1' and few misspellings.

Signed-off-by: Andrey Grodzovsky 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 145 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h |   6 +-
  2 files changed, 146 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 407dd16c..fcc4b05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -34,12 +34,132 @@ static DEFINE_MUTEX(xgmi_mutex);
  static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
  static unsigned hive_count = 0;
  
-

  void *amdgpu_xgmi_hive_try_lock(struct amdgpu_hive_info *hive)
  {
return >device_list;
  }
  
+static ssize_t amdgpu_xgmi_show_hive_id(struct device *dev,

+   struct device_attribute *attr, char *buf)
+{
+   struct amdgpu_hive_info *hive =
+   container_of(attr, struct amdgpu_hive_info, dev_attr);
+
+   return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id);
+}
+
+static int amdgpu_xgmi_sysfs_create(struct amdgpu_device *adev,
+   struct amdgpu_hive_info *hive)
+{
+   int ret = 0;
+
+   if (WARN_ON(hive->kobj))
+   return -EINVAL;
+
+   hive->kobj = kobject_create_and_add("xgmi_hive_info", >dev->kobj);
+   if (!hive->kobj) {
+   dev_err(adev->dev, "XGMI: Failed to allocate sysfs entry!\n");
+   return -EINVAL;
+   }
+
+   hive->dev_attr = (struct device_attribute) {
+   .attr = {
+   .name = "xgmi_hive_id",
+   .mode = S_IRUGO,
+
+   },
+   .show = amdgpu_xgmi_show_hive_id,
+   };
+
+   ret = sysfs_create_file(hive->kobj, >dev_attr.attr);
+   if (ret) {
+   dev_err(adev->dev, "XGMI: Failed to create device file 
xgmi_hive_id\n");
+   kobject_del(hive->kobj);
+   kobject_put(hive->kobj);
+   hive->kobj = NULL;
+   }
+
+   return ret;
+}
+
+static void amdgpu_xgmi_sysfs_destroy(struct amdgpu_device *adev,
+   struct amdgpu_hive_info *hive)
+{
+   sysfs_remove_file(hive->kobj, >dev_attr.attr);
+   kobject_del(hive->kobj);
+   kobject_put(hive->kobj);
+   hive->kobj = NULL;
+}
+
+static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
+struct device_attribute *attr,
+char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%llu\n", adev->gmc.xgmi.node_id);
+
+}
+
+
+static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
+
+
+static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
+struct amdgpu_hive_info *hive)
+{
+   int ret = 0;
+   char node[10] = { 0 };
+
+   /* Create xgmi device id file */
+   ret = device_create_file(adev->dev, _attr_xgmi_device_id);
+   if (ret) {
+   dev_err(adev->dev, "XGMI: Failed to create device file 
xgmi_device_id\n");
+   return ret;
+   }
+
+   /* Create sysfs link to hive info folder on the first device */
+   if (adev != hive->adev) {
+   ret = sysfs_create_link(>dev->kobj, hive->kobj,
+   "xgmi_hive_info");
+   if (ret) {
+   dev_err(adev->dev, "XGMI: Failed to create link to hive 
info");
+   goto remove_file;
+   }
+   }
+
+   sprintf(node, "node%d", hive->number_devices);
+   /* Create sysfs link form the hive folder to yourself */
+   ret = sysfs_create_link(hive->kobj, >dev->kobj, node);
+   if (ret) {
+   dev_err(adev->dev, "XGMI: Failed to create link from hive 
info");
+   goto remove_link;
+   }
+
+   goto success;
+
+
+remove_link:
+   sysfs_remove_link(>dev->kobj, adev->ddev->unique);
+
+remove_file:
+   device_remove_file(adev->dev, _attr_xgmi_device_id);
+
+success:
+   return ret;
+}
+
+static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
+ struct amdgpu_hive_info *hive)
+{
+   device_remove_file(adev->dev, _attr_xgmi_device_id);
+   sysfs_remove_link(>dev->kobj, adev->ddev->unique);
+   sysfs_remove_link(hive->kobj, adev->ddev->unique);
+}
+
+
+
  struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device