RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

[Gui, Jack]

Reviewed-by: Jack Gui 

-Original Message-
From: Wang, Kevin(Yang)  
Sent: Friday, July 19, 2019 11:46 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; 
Huang, Ray ; Xu, Feifei ; Gui, Jack 
; Wang, Kevin(Yang) 
Subject: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

1.NAVI10_PEAK_SCLK_XTX1830 Mhz
2.NAVI10_PEAK_SCLK_XT 1755 Mhz
3.NAVI10_PEAK_SCLK_XL 1625 Mhz

Change-Id: I48863a9d0e261b9e7778a6c0e4a8762d7c978da6
Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 65 ++-
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  4 ++
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 55 
 drivers/gpu/drm/amd/powerplay/navi10_ppt.h|  4 ++
 4 files changed, 97 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 7f51bbd2ac90..ab389dde9562 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1360,37 +1360,40 @@ int smu_adjust_power_state_dynamic(struct smu_context 
*smu,
}
 
if (smu_dpm_ctx->dpm_level != level) {
-   switch (level) {
-   case AMD_DPM_FORCED_LEVEL_HIGH:
-   ret = smu_force_dpm_limit_value(smu, true);
-   break;
-   case AMD_DPM_FORCED_LEVEL_LOW:
-   ret = smu_force_dpm_limit_value(smu, false);
-   break;
-
-   case AMD_DPM_FORCED_LEVEL_AUTO:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
-   ret = smu_unforce_dpm_levels(smu);
-   break;
-
-   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
-   ret = smu_get_profiling_clk_mask(smu, level,
-_mask,
-_mask,
-_mask);
-   if (ret)
-   return ret;
-   smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
-   smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
-   smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
-   break;
-
-   case AMD_DPM_FORCED_LEVEL_MANUAL:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
-   default:
-   break;
+   ret = smu_set_performance_level(smu, level);
+   if (ret) {
+   switch (level) {
+   case AMD_DPM_FORCED_LEVEL_HIGH:
+   ret = smu_force_dpm_limit_value(smu, true);
+   break;
+   case AMD_DPM_FORCED_LEVEL_LOW:
+   ret = smu_force_dpm_limit_value(smu, false);
+   break;
+
+   case AMD_DPM_FORCED_LEVEL_AUTO:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+   ret = smu_unforce_dpm_levels(smu);
+   break;
+
+   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+   ret = smu_get_profiling_clk_mask(smu, level,
+_mask,
+_mask,
+_mask);
+   if (ret)
+   return ret;
+   smu_force_clk_levels(smu, SMU_SCLK, 1 << 
sclk_mask);
+   smu_force_clk_levels(smu, SMU_MCLK, 1 << 
mclk_mask);
+   smu_force_clk_levels(smu, SMU_SOCCLK, 1 << 
soc_mask);
+   break;
+
+   case AMD_DPM_FORCED_LEVEL_MANUAL:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+   default:
+   break;
+   }
}
 
if (!ret)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 514d31518853..ba5ddafcbdba 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -631,6 +631,7 @@ struct pptable_funcs {
int (*get_thermal_temperature_range)(struct smu_context *smu, struct 
smu_temperature_range *range);
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t 

Re: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

[Wang, Kevin(Yang)]

Comment inline


From: Quan, Evan 
Sent: Friday, July 19, 2019 1:03 PM
To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org 

Cc: Feng, Kenneth ; Huang, Ray ; Xu, 
Feifei ; Gui, Jack 
Subject: RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

Comment inline

> -Original Message-
> From: Wang, Kevin(Yang) 
> Sent: Friday, July 19, 2019 11:46 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth ; Quan, Evan
> ; Huang, Ray ; Xu, Feifei
> ; Gui, Jack ; Wang, Kevin(Yang)
> 
> Subject: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10
>
> 1.NAVI10_PEAK_SCLK_XTX1830 Mhz
> 2.NAVI10_PEAK_SCLK_XT 1755 Mhz
> 3.NAVI10_PEAK_SCLK_XL 1625 Mhz
>
> Change-Id: I48863a9d0e261b9e7778a6c0e4a8762d7c978da6
> Signed-off-by: Kevin Wang 
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 65 ++
> -
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  4 ++
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 55 
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.h|  4 ++
>  4 files changed, 97 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 7f51bbd2ac90..ab389dde9562 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1360,37 +1360,40 @@ int smu_adjust_power_state_dynamic(struct
> smu_context *smu,
>}
>
>if (smu_dpm_ctx->dpm_level != level) {
> - switch (level) {
> - case AMD_DPM_FORCED_LEVEL_HIGH:
> - ret = smu_force_dpm_limit_value(smu, true);
> - break;
> - case AMD_DPM_FORCED_LEVEL_LOW:
> - ret = smu_force_dpm_limit_value(smu, false);
> - break;
> -
> - case AMD_DPM_FORCED_LEVEL_AUTO:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> - ret = smu_unforce_dpm_levels(smu);
> - break;
> -
> - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> - ret = smu_get_profiling_clk_mask(smu, level,
> -  _mask,
> -  _mask,
> -  _mask);
> - if (ret)
> - return ret;
> - smu_force_clk_levels(smu, SMU_SCLK, 1 <<
> sclk_mask);
> - smu_force_clk_levels(smu, SMU_MCLK, 1 <<
> mclk_mask);
> - smu_force_clk_levels(smu, SMU_SOCCLK, 1 <<
> soc_mask);
> - break;
> -
> - case AMD_DPM_FORCED_LEVEL_MANUAL:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
> - default:
> - break;
> + ret = smu_set_performance_level(smu, level);
> + if (ret) {
[Quan, Evan] Since this actually handles AMD_DPM_FORCED_LEVEL_PROFILE_PEAK 
only. Please move this under "case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:".
And please give it a more meaningful name e.g. smu_set_asic_peak_profile().

[kevin]: in the future, for specifc asic, it may be custom other performance 
level, so we should have this capacity to support other asic with any 
performance level. and i think it is not a good way to handle performance level 
use case by case method for each asic.

> + switch (level) {
> + case AMD_DPM_FORCED_LEVEL_HIGH:
> + ret = smu_force_dpm_limit_value(smu, true);
> + break;
> + case AMD_DPM_FORCED_LEVEL_LOW:
> + ret = smu_force_dpm_limit_value(smu,
> false);
> + break;
> +
> + case AMD_DPM_FORCED_LEVEL_AUTO:
> + case
> AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> + ret = smu_unforce_dpm_levels(smu);
> + break;
> +
> + case
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> + case
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> + ret = smu_get_profiling_clk_mask(smu, level,
> +  _mask,
> +  _mask,
> +  _mask);
> + if (ret)
> + return ret;
> + smu_force_clk_levels(smu, SMU_SCLK, 1 <<
> sclk_mask);
> + smu_force_clk_levels(smu, SMU_MCLK, 1 <<
> mclk_mask);
> +  

RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

[Quan, Evan]

Comment inline

> -Original Message-
> From: Wang, Kevin(Yang) 
> Sent: Friday, July 19, 2019 11:46 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth ; Quan, Evan
> ; Huang, Ray ; Xu, Feifei
> ; Gui, Jack ; Wang, Kevin(Yang)
> 
> Subject: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10
> 
> 1.NAVI10_PEAK_SCLK_XTX1830 Mhz
> 2.NAVI10_PEAK_SCLK_XT 1755 Mhz
> 3.NAVI10_PEAK_SCLK_XL 1625 Mhz
> 
> Change-Id: I48863a9d0e261b9e7778a6c0e4a8762d7c978da6
> Signed-off-by: Kevin Wang 
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 65 ++
> -
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  4 ++
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 55 
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.h|  4 ++
>  4 files changed, 97 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 7f51bbd2ac90..ab389dde9562 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1360,37 +1360,40 @@ int smu_adjust_power_state_dynamic(struct
> smu_context *smu,
>   }
> 
>   if (smu_dpm_ctx->dpm_level != level) {
> - switch (level) {
> - case AMD_DPM_FORCED_LEVEL_HIGH:
> - ret = smu_force_dpm_limit_value(smu, true);
> - break;
> - case AMD_DPM_FORCED_LEVEL_LOW:
> - ret = smu_force_dpm_limit_value(smu, false);
> - break;
> -
> - case AMD_DPM_FORCED_LEVEL_AUTO:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> - ret = smu_unforce_dpm_levels(smu);
> - break;
> -
> - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> - ret = smu_get_profiling_clk_mask(smu, level,
> -  _mask,
> -  _mask,
> -  _mask);
> - if (ret)
> - return ret;
> - smu_force_clk_levels(smu, SMU_SCLK, 1 <<
> sclk_mask);
> - smu_force_clk_levels(smu, SMU_MCLK, 1 <<
> mclk_mask);
> - smu_force_clk_levels(smu, SMU_SOCCLK, 1 <<
> soc_mask);
> - break;
> -
> - case AMD_DPM_FORCED_LEVEL_MANUAL:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
> - default:
> - break;
> + ret = smu_set_performance_level(smu, level);
> + if (ret) {
[Quan, Evan] Since this actually handles AMD_DPM_FORCED_LEVEL_PROFILE_PEAK 
only. Please move this under "case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:".
And please give it a more meaningful name e.g. smu_set_asic_peak_profile().
> + switch (level) {
> + case AMD_DPM_FORCED_LEVEL_HIGH:
> + ret = smu_force_dpm_limit_value(smu, true);
> + break;
> + case AMD_DPM_FORCED_LEVEL_LOW:
> + ret = smu_force_dpm_limit_value(smu,
> false);
> + break;
> +
> + case AMD_DPM_FORCED_LEVEL_AUTO:
> + case
> AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> + ret = smu_unforce_dpm_levels(smu);
> + break;
> +
> + case
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> + case
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> + ret = smu_get_profiling_clk_mask(smu, level,
> +  _mask,
> +  _mask,
> +  _mask);
> + if (ret)
> + return ret;
> + smu_force_clk_levels(smu, SMU_SCLK, 1 <<
> sclk_mask);
> + smu_force_clk_levels(smu, SMU_MCLK, 1 <<
> mclk_mask);
> + smu_force_clk_levels(smu, SMU_SOCCLK, 1
> << soc_mask);
> + break;
> +
> + case AMD_DPM_FORCED_LEVEL_MANUAL:
> + case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
> + default:
> + break;
> + }
>   }
> 
>   if (!ret)
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 514d31518853..ba5ddafcbdba 100644
> --- 

RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

[Feng, Kenneth]

With this change, all the below requests have the same sclk and mclk values on 
navi10 XT.
Is it expected?
enum amd_dpm_forced_level {
AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
AMD_DPM_FORCED_LEVEL_LOW = 0x4,
AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
};

-Original Message-
From: Wang, Kevin(Yang) 
Sent: Friday, July 19, 2019 11:46 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; 
Huang, Ray ; Xu, Feifei ; Gui, Jack 
; Wang, Kevin(Yang) 
Subject: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

1.NAVI10_PEAK_SCLK_XTX1830 Mhz
2.NAVI10_PEAK_SCLK_XT 1755 Mhz
3.NAVI10_PEAK_SCLK_XL 1625 Mhz

Change-Id: I48863a9d0e261b9e7778a6c0e4a8762d7c978da6
Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 65 ++-
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  4 ++
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 55 
 drivers/gpu/drm/amd/powerplay/navi10_ppt.h|  4 ++
 4 files changed, 97 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 7f51bbd2ac90..ab389dde9562 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1360,37 +1360,40 @@ int smu_adjust_power_state_dynamic(struct smu_context 
*smu,
}
 
if (smu_dpm_ctx->dpm_level != level) {
-   switch (level) {
-   case AMD_DPM_FORCED_LEVEL_HIGH:
-   ret = smu_force_dpm_limit_value(smu, true);
-   break;
-   case AMD_DPM_FORCED_LEVEL_LOW:
-   ret = smu_force_dpm_limit_value(smu, false);
-   break;
-
-   case AMD_DPM_FORCED_LEVEL_AUTO:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
-   ret = smu_unforce_dpm_levels(smu);
-   break;
-
-   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
-   ret = smu_get_profiling_clk_mask(smu, level,
-_mask,
-_mask,
-_mask);
-   if (ret)
-   return ret;
-   smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
-   smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
-   smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
-   break;
-
-   case AMD_DPM_FORCED_LEVEL_MANUAL:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
-   default:
-   break;
+   ret = smu_set_performance_level(smu, level);
+   if (ret) {
+   switch (level) {
+   case AMD_DPM_FORCED_LEVEL_HIGH:
+   ret = smu_force_dpm_limit_value(smu, true);
+   break;
+   case AMD_DPM_FORCED_LEVEL_LOW:
+   ret = smu_force_dpm_limit_value(smu, false);
+   break;
+
+   case AMD_DPM_FORCED_LEVEL_AUTO:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+   ret = smu_unforce_dpm_levels(smu);
+   break;
+
+   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+   ret = smu_get_profiling_clk_mask(smu, level,
+_mask,
+_mask,
+_mask);
+   if (ret)
+   return ret;
+   smu_force_clk_levels(smu, SMU_SCLK, 1 << 
sclk_mask);
+   smu_force_clk_levels(smu, SMU_MCLK, 1 << 
mclk_mask);
+   smu_force_clk_levels(smu, SMU_SOCCLK, 1 << 
soc_mask);
+   break;
+
+   case AMD_DPM_FORCED_LEVEL_MANUAL:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+   default:
+   break;
+  

[PATCH AUTOSEL 4.19 029/101] drm/amd/display: fix compilation error

[Sasha Levin]

From: Hariprasad Kelam 

[ Upstream commit 88099f53cc3717437f5fc9cf84205c5b65118377 ]

this patch fixes below compilation error

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In
function ‘dcn10_apply_ctx_for_surface’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2378:3:
error: implicit declaration of function ‘udelay’
[-Werror=implicit-function-declaration]
   udelay(underflow_check_delay_us);

Signed-off-by: Hariprasad Kelam 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7736ef123e9b..ead221ccb93e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include 
 #include "dm_services.h"
 #include "core_types.h"
 #include "resource.h"
-- 
2.20.1

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[PATCH AUTOSEL 4.19 010/101] drm/amd/display: Fill prescale_params->scale for RGB565

[Sasha Levin]

From: Nicholas Kazlauskas 

[ Upstream commit 1352c779cb74d427f4150cbe779a2f7886f70cae ]

[Why]
An assertion is thrown when using SURFACE_PIXEL_FORMAT_GRPH_RGB565
formats on DCE since the prescale_params->scale wasn't being filled.

Found by a dmesg-fail when running the
igt@kms_plane@pixel-format-pipe-a-planes test on Baffin.

[How]
Fill in the scale parameter.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Roman Li 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 53ccacf99eca..c3ad2bbec1a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -242,6 +242,9 @@ static void build_prescale_params(struct 
ipp_prescale_params *prescale_params,
prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 
switch (plane_state->format) {
+   case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
+   prescale_params->scale = 0x2082;
+   break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR:
prescale_params->scale = 0x2020;
-- 
2.20.1

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[PATCH AUTOSEL 4.19 011/101] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE

[Sasha Levin]

From: Tiecheng Zhou 

[ Upstream commit fe2b5323d2c3cedaa3bf943dc7a0d233c853c914 ]

it requires to initialize HDP_NONSURFACE_BASE, so as to avoid
using the value left by a previous VM under sriov scenario.

v2: it should not hurt baremetal, generalize it for both sriov
and baremetal

Signed-off-by: Emily Deng 
Signed-off-by: Tiecheng Zhou 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 72f8018fa2a8..ede27dab675f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1037,6 +1037,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device 
*adev)
tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
 
+   WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 
8));
+   WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 
40));
+
/* After HDP is initialized, flush HDP.*/
adev->nbio_funcs->hdp_flush(adev, NULL);
 
-- 
2.20.1

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[PATCH AUTOSEL 4.19 026/101] drm/amd/display: Always allocate initial connector state state

[Sasha Levin]

From: Nicholas Kazlauskas 

[ Upstream commit f04bee34d6e35df26cbb2d65e801adfd0d8fe20d ]

[Why]
Unlike our regular connectors, MST connectors don't start off with
an initial connector state. This causes a NULL pointer dereference to
occur when attaching the bpc property since it tries to modify the
connector state.

We need an initial connector state on the connector to avoid the crash.

[How]
Use our reset helper to allocate an initial state and reset the values
to their defaults. We were already doing this before, just not for
MST connectors.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index dac7978f5ee1..221de241535a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3644,6 +3644,13 @@ void amdgpu_dm_connector_init_helper(struct 
amdgpu_display_manager *dm,
 {
struct amdgpu_device *adev = dm->ddev->dev_private;
 
+   /*
+* Some of the properties below require access to state, like bpc.
+* Allocate some default initial connector state with our reset helper.
+*/
+   if (aconnector->base.funcs->reset)
+   aconnector->base.funcs->reset(>base);
+
aconnector->connector_id = link_index;
aconnector->dc_link = link;
aconnector->base.interlace_allowed = false;
@@ -3811,9 +3818,6 @@ static int amdgpu_dm_connector_init(struct 
amdgpu_display_manager *dm,
>base,
_dm_connector_helper_funcs);
 
-   if (aconnector->base.funcs->reset)
-   aconnector->base.funcs->reset(>base);
-
amdgpu_dm_connector_init_helper(
dm,
aconnector,
-- 
2.20.1

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[PATCH AUTOSEL 4.19 014/101] drm/amdkfd: Fix sdma queue map issue

[Sasha Levin]

From: Oak Zeng 

[ Upstream commit 065e4bdfa1f3ab2884c110394d8b7e7ebe3b988c ]

Previous codes assumes there are two sdma engines.
This is not true e.g., Raven only has 1 SDMA engine.
Fix the issue by using sdma engine number info in
device_info.

Signed-off-by: Oak Zeng 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../drm/amd/amdkfd/kfd_device_queue_manager.c | 21 +++
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 4f22e745df51..189212cb3547 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1268,12 +1268,17 @@ int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
return 0;
 }
 
-static int unmap_sdma_queues(struct device_queue_manager *dqm,
-   unsigned int sdma_engine)
+static int unmap_sdma_queues(struct device_queue_manager *dqm)
 {
-   return pm_send_unmap_queue(>packets, KFD_QUEUE_TYPE_SDMA,
-   KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false,
-   sdma_engine);
+   int i, retval = 0;
+
+   for (i = 0; i < dqm->dev->device_info->num_sdma_engines; i++) {
+   retval = pm_send_unmap_queue(>packets, KFD_QUEUE_TYPE_SDMA,
+   KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false, i);
+   if (retval)
+   return retval;
+   }
+   return retval;
 }
 
 /* dqm->lock mutex has to be locked before calling this function */
@@ -1312,10 +1317,8 @@ static int unmap_queues_cpsch(struct 
device_queue_manager *dqm,
pr_debug("Before destroying queues, sdma queue count is : %u\n",
dqm->sdma_queue_count);
 
-   if (dqm->sdma_queue_count > 0) {
-   unmap_sdma_queues(dqm, 0);
-   unmap_sdma_queues(dqm, 1);
-   }
+   if (dqm->sdma_queue_count > 0)
+   unmap_sdma_queues(dqm);
 
retval = pm_send_unmap_queue(>packets, KFD_QUEUE_TYPE_COMPUTE,
filter, filter_param, false, 0);
-- 
2.20.1

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[PATCH AUTOSEL 4.19 012/101] drm/amd/display: Disable ABM before destroy ABM struct

[Sasha Levin]

From: Paul Hsieh 

[ Upstream commit 1090d58d4815b1fcd95a80987391006c86398b4c ]

[Why]
When disable driver, OS will set backlight optimization
then do stop device.  But this flag will cause driver to
enable ABM when driver disabled.

[How]
Send ABM disable command before destroy ABM construct

Signed-off-by: Paul Hsieh 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index 29294db1a96b..070ab56a8aca 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -474,6 +474,8 @@ void dce_abm_destroy(struct abm **abm)
 {
struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
 
+   abm_dce->base.funcs->set_abm_immediate_disable(*abm);
+
kfree(abm_dce);
*abm = NULL;
 }
-- 
2.20.1

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[PATCH AUTOSEL 4.19 013/101] drm/amdkfd: Fix a potential memory leak

[Sasha Levin]

From: Oak Zeng 

[ Upstream commit e73390d181103a19eec2f25559a0570e9fe0 ]

Free mqd_mem_obj it GTT buffer allocation for MQD+control stack fails.

Signed-off-by: Oak Zeng 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index 0cedb37cf513..985bebde5a34 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -75,6 +75,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd,
struct v9_mqd *m;
struct kfd_dev *kfd = mm->dev;
 
+   *mqd_mem_obj = NULL;
/* From V9,  for CWSR, the control stack is located on the next page
 * boundary after the mqd, we will use the gtt allocation function
 * instead of sub-allocation function.
@@ -92,8 +93,10 @@ static int init_mqd(struct mqd_manager *mm, void **mqd,
} else
retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct v9_mqd),
mqd_mem_obj);
-   if (retval != 0)
+   if (retval) {
+   kfree(*mqd_mem_obj);
return -ENOMEM;
+   }
 
m = (struct v9_mqd *) (*mqd_mem_obj)->cpu_ptr;
addr = (*mqd_mem_obj)->gpu_addr;
-- 
2.20.1

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[PATCH AUTOSEL 5.1 042/141] drm/amd/display: fix compilation error

[Sasha Levin]

From: Hariprasad Kelam 

[ Upstream commit 88099f53cc3717437f5fc9cf84205c5b65118377 ]

this patch fixes below compilation error

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In
function ‘dcn10_apply_ctx_for_surface’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2378:3:
error: implicit declaration of function ‘udelay’
[-Werror=implicit-function-declaration]
   udelay(underflow_check_delay_us);

Signed-off-by: Hariprasad Kelam 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 1fac86d3032d..289283ddaee4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include 
 #include "dm_services.h"
 #include "core_types.h"
 #include "resource.h"
-- 
2.20.1

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[PATCH AUTOSEL 5.1 038/141] drm/amd/display: Always allocate initial connector state state

[Sasha Levin]

From: Nicholas Kazlauskas 

[ Upstream commit f04bee34d6e35df26cbb2d65e801adfd0d8fe20d ]

[Why]
Unlike our regular connectors, MST connectors don't start off with
an initial connector state. This causes a NULL pointer dereference to
occur when attaching the bpc property since it tries to modify the
connector state.

We need an initial connector state on the connector to avoid the crash.

[How]
Use our reset helper to allocate an initial state and reset the values
to their defaults. We were already doing this before, just not for
MST connectors.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bfb65e8c728f..9a070da12568 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4133,6 +4133,13 @@ void amdgpu_dm_connector_init_helper(struct 
amdgpu_display_manager *dm,
 {
struct amdgpu_device *adev = dm->ddev->dev_private;
 
+   /*
+* Some of the properties below require access to state, like bpc.
+* Allocate some default initial connector state with our reset helper.
+*/
+   if (aconnector->base.funcs->reset)
+   aconnector->base.funcs->reset(>base);
+
aconnector->connector_id = link_index;
aconnector->dc_link = link;
aconnector->base.interlace_allowed = false;
@@ -4315,9 +4322,6 @@ static int amdgpu_dm_connector_init(struct 
amdgpu_display_manager *dm,
>base,
_dm_connector_helper_funcs);
 
-   if (aconnector->base.funcs->reset)
-   aconnector->base.funcs->reset(>base);
-
amdgpu_dm_connector_init_helper(
dm,
aconnector,
-- 
2.20.1

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[PATCH AUTOSEL 5.1 027/141] drm/amd/display: Increase Backlight Gain Step Size

[Sasha Levin]

From: Eryk Brol 

[ Upstream commit e25228b02e4833e5b0fdd262801a2ae6cc72b39d ]

[Why]
Some backlight tests fail due to backlight settling
taking too long. This happens because the step
size used to change backlight levels is too small.

[How]
1. Change the size of the backlight gain step size
2. Change how DMCU firmware gets the step size value
   so that it is passed in by driver during DMCU initn

Signed-off-by: Eryk Brol 
Reviewed-by: Jun Lei 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index c2926cf19dee..407fb22be66a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -365,6 +365,9 @@ static bool dcn10_dmcu_init(struct dmcu *dmcu)
/* Set initialized ramping boundary value */
REG_WRITE(MASTER_COMM_DATA_REG1, 0x);
 
+   /* Set backlight ramping stepsize */
+   REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize);
+
/* Set command to initialize microcontroller */
REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
MCP_INIT_DMCU);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index c24c0e5ea44e..249a3c23b607 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -263,4 +263,6 @@ struct dmcu *dcn10_dmcu_create(
 
 void dce_dmcu_destroy(struct dmcu **dmcu);
 
+static const uint32_t abm_gain_stepsize = 0x0060;
+
 #endif /* _DCE_ABM_H_ */
-- 
2.20.1

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[PATCH AUTOSEL 5.1 040/141] drm/amd/display: set link->dongle_max_pix_clk to 0 on a disconnect

[Sasha Levin]

From: Samson Tam 

[ Upstream commit 233d87a579b8adcc6da5823fa507ecb6675e7562 ]

[Why]
Found issue in EDID Emulation where if we connect a display using
 a passive HDMI-DP dongle, disconnect it and then try to emulate
 a display using DP, we could not see 4K modes.  This was because
 on a disconnect, dongle_max_pix_clk was still set so when we
 emulate using DP, in dc_link_validate_mode_timing(), it would
 think we were still using a dongle and limit the modes we support.

[How]
In dc_link_detect(), set dongle_max_pix_clk to 0 when we detect
 a hotplug out ( if new_connection_type = dc_connection_none ).

Signed-off-by: Samson Tam 
Reviewed-by: Jun Lei 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 6072636da388..1367e2679082 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -922,6 +922,12 @@ bool dc_link_detect(struct dc_link *link, enum 
dc_detect_reason reason)
 
link->type = dc_connection_none;
sink_caps.signal = SIGNAL_TYPE_NONE;
+   /* When we unplug a passive DP-HDMI dongle connection, 
dongle_max_pix_clk
+*  is not cleared. If we emulate a DP signal on this 
connection, it thinks
+*  the dongle is still there and limits the number of modes we 
can emulate.
+*  Clear dongle_max_pix_clk on disconnect to fix this
+*/
+   link->dongle_max_pix_clk = 0;
}
 
LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d 
edid same=%d\n",
-- 
2.20.1

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[PATCH AUTOSEL 5.1 026/141] drm/amd/display: CS_TFM_1D only applied post EOTF

[Sasha Levin]

From: Krunoslav Kovac 

[ Upstream commit 6ad34adeaec5b56a5ba90e90099cabf1c1fe9dd2 ]

[Why]
There's some unnecessary mem allocation for CS_TFM_ID. What's worse, it
depends on LUT size and since it's 4K for CS_TFM_1D, it is 16x bigger
than in regular case when it's actually needed. This leads to some
crashes in stress conditions.

[How]
Skip ramp combining designed for RGB256 and DXGI gamma with CS_TFM_1D.

Signed-off-by: Krunoslav Kovac 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index a1055413bade..31f867bb5afe 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1564,7 +1564,8 @@ bool mod_color_calculate_regamma_params(struct 
dc_transfer_func *output_tf,
 
output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
 
-   if (ramp && (mapUserRamp || ramp->type != GAMMA_RGB_256)) {
+   if (ramp && ramp->type != GAMMA_CS_TFM_1D &&
+   (mapUserRamp || ramp->type != GAMMA_RGB_256)) {
rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
sizeof(*rgb_user),
GFP_KERNEL);
-- 
2.20.1

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[PATCH AUTOSEL 5.1 019/141] drm/amdkfd: Fix a potential memory leak

[Sasha Levin]

From: Oak Zeng 

[ Upstream commit e73390d181103a19eec2f25559a0570e9fe0 ]

Free mqd_mem_obj it GTT buffer allocation for MQD+control stack fails.

Signed-off-by: Oak Zeng 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index 9dbba609450e..8fe74b821b32 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -76,6 +76,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd,
struct v9_mqd *m;
struct kfd_dev *kfd = mm->dev;
 
+   *mqd_mem_obj = NULL;
/* From V9,  for CWSR, the control stack is located on the next page
 * boundary after the mqd, we will use the gtt allocation function
 * instead of sub-allocation function.
@@ -93,8 +94,10 @@ static int init_mqd(struct mqd_manager *mm, void **mqd,
} else
retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct v9_mqd),
mqd_mem_obj);
-   if (retval != 0)
+   if (retval) {
+   kfree(*mqd_mem_obj);
return -ENOMEM;
+   }
 
m = (struct v9_mqd *) (*mqd_mem_obj)->cpu_ptr;
addr = (*mqd_mem_obj)->gpu_addr;
-- 
2.20.1

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[PATCH AUTOSEL 5.1 015/141] drm/amdgpu: Reserve shared fence for eviction fence

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit dd68722c427d5b33420dce0ed0c44b4881e0a416 ]

Need to reserve space for the shared eviction fence when initializing
a KFD VM.

Signed-off-by: Felix Kuehling 
Acked-by: Christian König 
Reviewed-by: Harish Kasiviswanathan 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 1921dec3df7a..c7de68c495b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -909,6 +909,9 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void 
**process_info,
amdgpu_bo_sync_wait(vm->root.base.bo, AMDGPU_FENCE_OWNER_KFD, false);
if (ret)
goto wait_pd_fail;
+   ret = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv, 1);
+   if (ret)
+   goto reserve_shared_fail;
amdgpu_bo_fence(vm->root.base.bo,
>process_info->eviction_fence->base, true);
amdgpu_bo_unreserve(vm->root.base.bo);
@@ -922,6 +925,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void 
**process_info,
 
return 0;
 
+reserve_shared_fail:
 wait_pd_fail:
 validate_pd_fail:
amdgpu_bo_unreserve(vm->root.base.bo);
-- 
2.20.1

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[PATCH AUTOSEL 5.1 020/141] drm/amdkfd: Fix sdma queue map issue

[Sasha Levin]

From: Oak Zeng 

[ Upstream commit 065e4bdfa1f3ab2884c110394d8b7e7ebe3b988c ]

Previous codes assumes there are two sdma engines.
This is not true e.g., Raven only has 1 SDMA engine.
Fix the issue by using sdma engine number info in
device_info.

Signed-off-by: Oak Zeng 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../drm/amd/amdkfd/kfd_device_queue_manager.c | 21 +++
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index c6c9530e704e..722fa1f5244b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1269,12 +1269,17 @@ int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
return 0;
 }
 
-static int unmap_sdma_queues(struct device_queue_manager *dqm,
-   unsigned int sdma_engine)
+static int unmap_sdma_queues(struct device_queue_manager *dqm)
 {
-   return pm_send_unmap_queue(>packets, KFD_QUEUE_TYPE_SDMA,
-   KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false,
-   sdma_engine);
+   int i, retval = 0;
+
+   for (i = 0; i < dqm->dev->device_info->num_sdma_engines; i++) {
+   retval = pm_send_unmap_queue(>packets, KFD_QUEUE_TYPE_SDMA,
+   KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false, i);
+   if (retval)
+   return retval;
+   }
+   return retval;
 }
 
 /* dqm->lock mutex has to be locked before calling this function */
@@ -1313,10 +1318,8 @@ static int unmap_queues_cpsch(struct 
device_queue_manager *dqm,
pr_debug("Before destroying queues, sdma queue count is : %u\n",
dqm->sdma_queue_count);
 
-   if (dqm->sdma_queue_count > 0) {
-   unmap_sdma_queues(dqm, 0);
-   unmap_sdma_queues(dqm, 1);
-   }
+   if (dqm->sdma_queue_count > 0)
+   unmap_sdma_queues(dqm);
 
retval = pm_send_unmap_queue(>packets, KFD_QUEUE_TYPE_COMPUTE,
filter, filter_param, false, 0);
-- 
2.20.1

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[PATCH AUTOSEL 5.1 018/141] drm/amd/display: Disable ABM before destroy ABM struct

[Sasha Levin]

From: Paul Hsieh 

[ Upstream commit 1090d58d4815b1fcd95a80987391006c86398b4c ]

[Why]
When disable driver, OS will set backlight optimization
then do stop device.  But this flag will cause driver to
enable ABM when driver disabled.

[How]
Send ABM disable command before destroy ABM construct

Signed-off-by: Paul Hsieh 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index da96229db53a..2959c3c9390b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -473,6 +473,8 @@ void dce_abm_destroy(struct abm **abm)
 {
struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
 
+   abm_dce->base.funcs->set_abm_immediate_disable(*abm);
+
kfree(abm_dce);
*abm = NULL;
 }
-- 
2.20.1

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[PATCH AUTOSEL 5.1 014/141] drm/amd/display: Fill prescale_params->scale for RGB565

[Sasha Levin]

From: Nicholas Kazlauskas 

[ Upstream commit 1352c779cb74d427f4150cbe779a2f7886f70cae ]

[Why]
An assertion is thrown when using SURFACE_PIXEL_FORMAT_GRPH_RGB565
formats on DCE since the prescale_params->scale wasn't being filled.

Found by a dmesg-fail when running the
igt@kms_plane@pixel-format-pipe-a-planes test on Baffin.

[How]
Fill in the scale parameter.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Roman Li 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 5e4db3712eef..88d37e850a12 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -242,6 +242,9 @@ static void build_prescale_params(struct 
ipp_prescale_params *prescale_params,
prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 
switch (plane_state->format) {
+   case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
+   prescale_params->scale = 0x2082;
+   break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR:
prescale_params->scale = 0x2020;
-- 
2.20.1

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[PATCH AUTOSEL 5.1 017/141] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE

[Sasha Levin]

From: Tiecheng Zhou 

[ Upstream commit fe2b5323d2c3cedaa3bf943dc7a0d233c853c914 ]

it requires to initialize HDP_NONSURFACE_BASE, so as to avoid
using the value left by a previous VM under sriov scenario.

v2: it should not hurt baremetal, generalize it for both sriov
and baremetal

Signed-off-by: Emily Deng 
Signed-off-by: Tiecheng Zhou 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 1611bef19a2c..c0446af00cdd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1135,6 +1135,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device 
*adev)
tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
 
+   WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 
8));
+   WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 
40));
+
/* After HDP is initialized, flush HDP.*/
adev->nbio_funcs->hdp_flush(adev, NULL);
 
-- 
2.20.1

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[PATCH AUTOSEL 5.2 057/171] drm/amd/display: fix compilation error

[Sasha Levin]

From: Hariprasad Kelam 

[ Upstream commit 88099f53cc3717437f5fc9cf84205c5b65118377 ]

this patch fixes below compilation error

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In
function ‘dcn10_apply_ctx_for_surface’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2378:3:
error: implicit declaration of function ‘udelay’
[-Werror=implicit-function-declaration]
   udelay(underflow_check_delay_us);

Signed-off-by: Hariprasad Kelam 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 33d311cea28c..9e4d70a0055e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include 
 #include "dm_services.h"
 #include "core_types.h"
 #include "resource.h"
-- 
2.20.1

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[PATCH AUTOSEL 5.2 053/171] drm/amd/display: Update link rate from DPCD 10

[Sasha Levin]

From: Wesley Chalmers 

[ Upstream commit 53c81fc7875bc2dca358485dac3999e14ec91a00 ]

[WHY]
Some panels return a link rate of 0 (unknown) in DPCD 0. In this case,
an appropriate mode cannot be set, and certain panels will show
corruption as they are forced to use a mode they do not support.

[HOW]
Read DPCD 10 in the case where supported link rate from DPCD 0 is
unknown, and pass that value on to the reported link rate.
This re-introduces behaviour present in previous versions that appears
to have been accidentally removed.

Signed-off-by: Wesley Chalmers 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 1ee544a32ebb..253311864cdd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1624,8 +1624,7 @@ static bool decide_edp_link_settings(struct dc_link 
*link, struct dc_link_settin
uint32_t link_bw;
 
if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
-   link->dpcd_caps.edp_supported_link_rates_count == 0 ||
-   link->dc->config.optimize_edp_link_rate == false) {
+   link->dpcd_caps.edp_supported_link_rates_count == 0) {
*link_setting = link->verified_link_cap;
return true;
}
@@ -2597,7 +2596,8 @@ void detect_edp_sink_caps(struct dc_link *link)
memset(supported_link_rates, 0, sizeof(supported_link_rates));
 
if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
-   link->dc->config.optimize_edp_link_rate) {
+   (link->dc->config.optimize_edp_link_rate ||
+   link->reported_link_cap.link_rate == 
LINK_RATE_UNKNOWN)) {
// Read DPCD 00010h - 0001Fh 16 bytes at one shot
core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
supported_link_rates, 
sizeof(supported_link_rates));
@@ -2612,6 +2612,9 @@ void detect_edp_sink_caps(struct dc_link *link)
link_rate = 
linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);

link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count]
 = link_rate;

link->dpcd_caps.edp_supported_link_rates_count++;
+
+   if (link->reported_link_cap.link_rate < 
link_rate)
+   link->reported_link_cap.link_rate = 
link_rate;
}
}
}
-- 
2.20.1

[PATCH AUTOSEL 5.2 052/171] drm/amd/display: Always allocate initial connector state state

[Sasha Levin]

From: Nicholas Kazlauskas 

[ Upstream commit f04bee34d6e35df26cbb2d65e801adfd0d8fe20d ]

[Why]
Unlike our regular connectors, MST connectors don't start off with
an initial connector state. This causes a NULL pointer dereference to
occur when attaching the bpc property since it tries to modify the
connector state.

We need an initial connector state on the connector to avoid the crash.

[How]
Use our reset helper to allocate an initial state and reset the values
to their defaults. We were already doing this before, just not for
MST connectors.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0e482349a5cb..dc3ac66a4450 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4627,6 +4627,13 @@ void amdgpu_dm_connector_init_helper(struct 
amdgpu_display_manager *dm,
 {
struct amdgpu_device *adev = dm->ddev->dev_private;
 
+   /*
+* Some of the properties below require access to state, like bpc.
+* Allocate some default initial connector state with our reset helper.
+*/
+   if (aconnector->base.funcs->reset)
+   aconnector->base.funcs->reset(>base);
+
aconnector->connector_id = link_index;
aconnector->dc_link = link;
aconnector->base.interlace_allowed = false;
@@ -4809,9 +4816,6 @@ static int amdgpu_dm_connector_init(struct 
amdgpu_display_manager *dm,
>base,
_dm_connector_helper_funcs);
 
-   if (aconnector->base.funcs->reset)
-   aconnector->base.funcs->reset(>base);
-
amdgpu_dm_connector_init_helper(
dm,
aconnector,
-- 
2.20.1

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[PATCH AUTOSEL 5.2 055/171] drm/amd/display: set link->dongle_max_pix_clk to 0 on a disconnect

[Sasha Levin]

From: Samson Tam 

[ Upstream commit 233d87a579b8adcc6da5823fa507ecb6675e7562 ]

[Why]
Found issue in EDID Emulation where if we connect a display using
 a passive HDMI-DP dongle, disconnect it and then try to emulate
 a display using DP, we could not see 4K modes.  This was because
 on a disconnect, dongle_max_pix_clk was still set so when we
 emulate using DP, in dc_link_validate_mode_timing(), it would
 think we were still using a dongle and limit the modes we support.

[How]
In dc_link_detect(), set dongle_max_pix_clk to 0 when we detect
 a hotplug out ( if new_connection_type = dc_connection_none ).

Signed-off-by: Samson Tam 
Reviewed-by: Jun Lei 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b37ecc3ede61..a3ff33ff6da1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -960,6 +960,12 @@ bool dc_link_detect(struct dc_link *link, enum 
dc_detect_reason reason)
 
link->type = dc_connection_none;
sink_caps.signal = SIGNAL_TYPE_NONE;
+   /* When we unplug a passive DP-HDMI dongle connection, 
dongle_max_pix_clk
+*  is not cleared. If we emulate a DP signal on this 
connection, it thinks
+*  the dongle is still there and limits the number of modes we 
can emulate.
+*  Clear dongle_max_pix_clk on disconnect to fix this
+*/
+   link->dongle_max_pix_clk = 0;
}
 
LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d 
edid same=%d\n",
-- 
2.20.1

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[PATCH AUTOSEL 5.2 026/171] drm/amd/display: Disable ABM before destroy ABM struct

[Sasha Levin]

From: Paul Hsieh 

[ Upstream commit 1090d58d4815b1fcd95a80987391006c86398b4c ]

[Why]
When disable driver, OS will set backlight optimization
then do stop device.  But this flag will cause driver to
enable ABM when driver disabled.

[How]
Send ABM disable command before destroy ABM construct

Signed-off-by: Paul Hsieh 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index da96229db53a..2959c3c9390b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -473,6 +473,8 @@ void dce_abm_destroy(struct abm **abm)
 {
struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
 
+   abm_dce->base.funcs->set_abm_immediate_disable(*abm);
+
kfree(abm_dce);
*abm = NULL;
 }
-- 
2.20.1

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[PATCH AUTOSEL 5.2 022/171] drm/amd/display: Fill plane attrs only for valid pxl format

[Sasha Levin]

From: Roman Li 

[ Upstream commit 1894478ad1f8fd7366edc5cee49ee9caea0e3d52 ]

[Why]
In fill_plane_buffer_attributes() we calculate chroma/luma
assuming that the surface_pixel_format is always valid.
If it's not the case, there's a risk of divide by zero error.

[How]
Check if format valid before calculating pixel format attributes

Signed-off-by: Roman Li 
Reviewed-by: David Francis 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fa268dd736f4..31530bfd002a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2592,7 +2592,7 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
address->type = PLN_ADDR_TYPE_GRAPHICS;
address->grph.addr.low_part = lower_32_bits(afb->address);
address->grph.addr.high_part = upper_32_bits(afb->address);
-   } else {
+   } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
uint64_t chroma_addr = afb->address + fb->offsets[1];
 
plane_size->video.luma_size.x = 0;
-- 
2.20.1

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[PATCH AUTOSEL 5.2 028/171] drm/amdkfd: Fix sdma queue map issue

[Sasha Levin]

From: Oak Zeng 

[ Upstream commit 065e4bdfa1f3ab2884c110394d8b7e7ebe3b988c ]

Previous codes assumes there are two sdma engines.
This is not true e.g., Raven only has 1 SDMA engine.
Fix the issue by using sdma engine number info in
device_info.

Signed-off-by: Oak Zeng 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../drm/amd/amdkfd/kfd_device_queue_manager.c | 21 +++
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index ae381450601c..afbaf6f5131e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1268,12 +1268,17 @@ int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
return 0;
 }
 
-static int unmap_sdma_queues(struct device_queue_manager *dqm,
-   unsigned int sdma_engine)
+static int unmap_sdma_queues(struct device_queue_manager *dqm)
 {
-   return pm_send_unmap_queue(>packets, KFD_QUEUE_TYPE_SDMA,
-   KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false,
-   sdma_engine);
+   int i, retval = 0;
+
+   for (i = 0; i < dqm->dev->device_info->num_sdma_engines; i++) {
+   retval = pm_send_unmap_queue(>packets, KFD_QUEUE_TYPE_SDMA,
+   KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false, i);
+   if (retval)
+   return retval;
+   }
+   return retval;
 }
 
 /* dqm->lock mutex has to be locked before calling this function */
@@ -1312,10 +1317,8 @@ static int unmap_queues_cpsch(struct 
device_queue_manager *dqm,
pr_debug("Before destroying queues, sdma queue count is : %u\n",
dqm->sdma_queue_count);
 
-   if (dqm->sdma_queue_count > 0) {
-   unmap_sdma_queues(dqm, 0);
-   unmap_sdma_queues(dqm, 1);
-   }
+   if (dqm->sdma_queue_count > 0)
+   unmap_sdma_queues(dqm);
 
retval = pm_send_unmap_queue(>packets, KFD_QUEUE_TYPE_COMPUTE,
filter, filter_param, false, 0);
-- 
2.20.1

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[PATCH AUTOSEL 5.2 021/171] drm/amd/display: Disable cursor when offscreen in negative direction

[Sasha Levin]

From: Nicholas Kazlauskas 

[ Upstream commit e371e19c10a264bd72c2ff1d21e2167b994710d1 ]

[Why]
When x or y is negative we set the x and y values to 0 and compensate
with a positive cursor hotspot in DM since DC expects positive cursor
values.

When x or y is less than or equal to the maximum cursor width or height
the cursor hotspot is clamped so the hotspot doesn't exceed the
cursor size:

if (x < 0) {
xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
x = 0;
}

if (y < 0) {
yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
y = 0;
}

This incorrectly forces the cursor to be at least 1 pixel on the screen
in either direction when x or y is sufficiently negative.

[How]
Just disable the cursor when it goes far enough off the screen in one
of these directions.

This fixes kms_cursor_crc@cursor-256x256-offscreen.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Sun peng Li 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ab7c5c3004ee..fa268dd736f4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4952,12 +4952,12 @@ static int get_cursor_position(struct drm_plane *plane, 
struct drm_crtc *crtc,
int x, y;
int xorigin = 0, yorigin = 0;
 
-   if (!crtc || !plane->state->fb) {
-   position->enable = false;
-   position->x = 0;
-   position->y = 0;
+   position->enable = false;
+   position->x = 0;
+   position->y = 0;
+
+   if (!crtc || !plane->state->fb)
return 0;
-   }
 
if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
(plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
@@ -4971,6 +4971,10 @@ static int get_cursor_position(struct drm_plane *plane, 
struct drm_crtc *crtc,
x = plane->state->crtc_x;
y = plane->state->crtc_y;
 
+   if (x <= -amdgpu_crtc->max_cursor_width ||
+   y <= -amdgpu_crtc->max_cursor_height)
+   return 0;
+
if (crtc->primary->state) {
/* avivo cursor are offset into the total surface */
x += crtc->primary->state->src_x >> 16;
-- 
2.20.1

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[PATCH AUTOSEL 5.2 019/171] drm/amd/display: fix multi display seamless boot case

[Sasha Levin]

From: Anthony Koo 

[ Upstream commit 4cd75ff096f4ef49c343093b52a952f27aba7796 ]

[Why]
There is a scenario that causes eDP to become blank if
there are multiple displays connected, and the external
display is set as the primary display such that the first
flip comes to the external display.

In this scenario, we call our optimize function before
the eDP even has a chance to flip.

[How]
There is a check that prevents bandwidth optimize from
occurring before first flip is complete on the seamless boot
display.
But actually it assumed the seamless boot display is the
first one to flip. But in this scenario it is not.
Modify the check to ensure the steam with the seamless
boot flag set is the one that has completed the first flip.

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 18c775a950cc..ee6b646180b6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1138,9 +1138,6 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
const struct dc_link *link = context->streams[i]->link;
struct dc_stream_status *status;
 
-   if (context->streams[i]->apply_seamless_boot_optimization)
-   context->streams[i]->apply_seamless_boot_optimization = 
false;
-
if (!context->streams[i]->mode_changed)
continue;
 
@@ -1792,10 +1789,15 @@ static void commit_planes_for_stream(struct dc *dc,
if (dc->optimize_seamless_boot && surface_count > 0) {
/* Optimize seamless boot flag keeps clocks and watermarks high 
until
 * first flip. After first flip, optimization is required to 
lower
-* bandwidth.
+* bandwidth. Important to note that it is expected UEFI will
+* only light up a single display on POST, therefore we only 
expect
+* one stream with seamless boot flag set.
 */
-   dc->optimize_seamless_boot = false;
-   dc->optimized_required = true;
+   if (stream->apply_seamless_boot_optimization) {
+   stream->apply_seamless_boot_optimization = false;
+   dc->optimize_seamless_boot = false;
+   dc->optimized_required = true;
+   }
}
 
if (update_type == UPDATE_TYPE_FULL && !dc->optimize_seamless_boot) {
-- 
2.20.1

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[PATCH AUTOSEL 5.2 035/171] drm/amd/display: Reset planes for color management changes

[Sasha Levin]

From: Nicholas Kazlauskas 

[ Upstream commit 7316c4ad299663a16ca9ce13e5e817b4ca760809 ]

[Why]
For commits with allow_modeset=false and CRTC degamma changes the planes
aren't reset. This results in incorrect rendering.

[How]
Reset the planes when color management has changed on the CRTC.
Technically this will include regamma changes as well, but it doesn't
really after legacy userspace since those commit with
allow_modeset=true.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Harry Wentland 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 31530bfd002a..0e482349a5cb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6331,6 +6331,10 @@ static bool should_reset_plane(struct drm_atomic_state 
*state,
if (!new_crtc_state)
return true;
 
+   /* CRTC Degamma changes currently require us to recreate planes. */
+   if (new_crtc_state->color_mgmt_changed)
+   return true;
+
if (drm_atomic_crtc_needs_modeset(new_crtc_state))
return true;
 
-- 
2.20.1

[PATCH AUTOSEL 5.2 023/171] drm/amdgpu: Reserve shared fence for eviction fence

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit dd68722c427d5b33420dce0ed0c44b4881e0a416 ]

Need to reserve space for the shared eviction fence when initializing
a KFD VM.

Signed-off-by: Felix Kuehling 
Acked-by: Christian König 
Reviewed-by: Harish Kasiviswanathan 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index a6e5184d436c..4b192e0ce92f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -896,6 +896,9 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void 
**process_info,
  AMDGPU_FENCE_OWNER_KFD, false);
if (ret)
goto wait_pd_fail;
+   ret = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv, 1);
+   if (ret)
+   goto reserve_shared_fail;
amdgpu_bo_fence(vm->root.base.bo,
>process_info->eviction_fence->base, true);
amdgpu_bo_unreserve(vm->root.base.bo);
@@ -909,6 +912,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void 
**process_info,
 
return 0;
 
+reserve_shared_fail:
 wait_pd_fail:
 validate_pd_fail:
amdgpu_bo_unreserve(vm->root.base.bo);
-- 
2.20.1

[PATCH AUTOSEL 5.2 027/171] drm/amdkfd: Fix a potential memory leak

[Sasha Levin]

From: Oak Zeng 

[ Upstream commit e73390d181103a19eec2f25559a0570e9fe0 ]

Free mqd_mem_obj it GTT buffer allocation for MQD+control stack fails.

Signed-off-by: Oak Zeng 
Reviewed-by: Felix Kuehling 
Signed-off-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index 9dbba609450e..8fe74b821b32 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -76,6 +76,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd,
struct v9_mqd *m;
struct kfd_dev *kfd = mm->dev;
 
+   *mqd_mem_obj = NULL;
/* From V9,  for CWSR, the control stack is located on the next page
 * boundary after the mqd, we will use the gtt allocation function
 * instead of sub-allocation function.
@@ -93,8 +94,10 @@ static int init_mqd(struct mqd_manager *mm, void **mqd,
} else
retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct v9_mqd),
mqd_mem_obj);
-   if (retval != 0)
+   if (retval) {
+   kfree(*mqd_mem_obj);
return -ENOMEM;
+   }
 
m = (struct v9_mqd *) (*mqd_mem_obj)->cpu_ptr;
addr = (*mqd_mem_obj)->gpu_addr;
-- 
2.20.1

[PATCH AUTOSEL 5.2 036/171] drm/amd/display: CS_TFM_1D only applied post EOTF

[Sasha Levin]

From: Krunoslav Kovac 

[ Upstream commit 6ad34adeaec5b56a5ba90e90099cabf1c1fe9dd2 ]

[Why]
There's some unnecessary mem allocation for CS_TFM_ID. What's worse, it
depends on LUT size and since it's 4K for CS_TFM_1D, it is 16x bigger
than in regular case when it's actually needed. This leads to some
crashes in stress conditions.

[How]
Skip ramp combining designed for RGB256 and DXGI gamma with CS_TFM_1D.

Signed-off-by: Krunoslav Kovac 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index a1055413bade..31f867bb5afe 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1564,7 +1564,8 @@ bool mod_color_calculate_regamma_params(struct 
dc_transfer_func *output_tf,
 
output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
 
-   if (ramp && (mapUserRamp || ramp->type != GAMMA_RGB_256)) {
+   if (ramp && ramp->type != GAMMA_CS_TFM_1D &&
+   (mapUserRamp || ramp->type != GAMMA_RGB_256)) {
rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
sizeof(*rgb_user),
GFP_KERNEL);
-- 
2.20.1

[PATCH AUTOSEL 5.2 037/171] drm/amd/display: Increase Backlight Gain Step Size

[Sasha Levin]

From: Eryk Brol 

[ Upstream commit e25228b02e4833e5b0fdd262801a2ae6cc72b39d ]

[Why]
Some backlight tests fail due to backlight settling
taking too long. This happens because the step
size used to change backlight levels is too small.

[How]
1. Change the size of the backlight gain step size
2. Change how DMCU firmware gets the step size value
   so that it is passed in by driver during DMCU initn

Signed-off-by: Eryk Brol 
Reviewed-by: Jun Lei 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index 818536eea00a..c6a607cd0e4b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -388,6 +388,9 @@ static bool dcn10_dmcu_init(struct dmcu *dmcu)
/* Set initialized ramping boundary value */
REG_WRITE(MASTER_COMM_DATA_REG1, 0x);
 
+   /* Set backlight ramping stepsize */
+   REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize);
+
/* Set command to initialize microcontroller */
REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
MCP_INIT_DMCU);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index 60ce56f60ae3..5bd0df55aa5d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -263,4 +263,6 @@ struct dmcu *dcn10_dmcu_create(
 
 void dce_dmcu_destroy(struct dmcu **dmcu);
 
+static const uint32_t abm_gain_stepsize = 0x0060;
+
 #endif /* _DCE_ABM_H_ */
-- 
2.20.1

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[PATCH AUTOSEL 5.2 025/171] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE

[Sasha Levin]

From: Tiecheng Zhou 

[ Upstream commit fe2b5323d2c3cedaa3bf943dc7a0d233c853c914 ]

it requires to initialize HDP_NONSURFACE_BASE, so as to avoid
using the value left by a previous VM under sriov scenario.

v2: it should not hurt baremetal, generalize it for both sriov
and baremetal

Signed-off-by: Emily Deng 
Signed-off-by: Tiecheng Zhou 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 72837b8c7031..c2086eb00555 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1163,6 +1163,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device 
*adev)
tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
 
+   WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 
8));
+   WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 
40));
+
/* After HDP is initialized, flush HDP.*/
adev->nbio_funcs->hdp_flush(adev, NULL);
 
-- 
2.20.1

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[PATCH AUTOSEL 5.2 018/171] drm/amd/display: Fill prescale_params->scale for RGB565

[Sasha Levin]

From: Nicholas Kazlauskas 

[ Upstream commit 1352c779cb74d427f4150cbe779a2f7886f70cae ]

[Why]
An assertion is thrown when using SURFACE_PIXEL_FORMAT_GRPH_RGB565
formats on DCE since the prescale_params->scale wasn't being filled.

Found by a dmesg-fail when running the
igt@kms_plane@pixel-format-pipe-a-planes test on Baffin.

[How]
Fill in the scale parameter.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Roman Li 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 7ac50ab1b762..7d7e93c87c28 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -242,6 +242,9 @@ static void build_prescale_params(struct 
ipp_prescale_params *prescale_params,
prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 
switch (plane_state->format) {
+   case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
+   prescale_params->scale = 0x2082;
+   break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR:
prescale_params->scale = 0x2020;
-- 
2.20.1

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RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

[Huang, Ray]

> -Original Message-
> From: Wang, Kevin(Yang) 
> Sent: Friday, July 19, 2019 11:46 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth ; Quan, Evan
> ; Huang, Ray ; Xu, Feifei
> ; Gui, Jack ; Wang, Kevin(Yang)
> 
> Subject: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10
> 
> 1.NAVI10_PEAK_SCLK_XTX1830 Mhz
> 2.NAVI10_PEAK_SCLK_XT 1755 Mhz
> 3.NAVI10_PEAK_SCLK_XL 1625 Mhz
> 
> Change-Id: I48863a9d0e261b9e7778a6c0e4a8762d7c978da6
> Signed-off-by: Kevin Wang 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 65 ++-
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  4 ++
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 55 
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.h|  4 ++
>  4 files changed, 97 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 7f51bbd2ac90..ab389dde9562 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1360,37 +1360,40 @@ int smu_adjust_power_state_dynamic(struct
> smu_context *smu,
>   }
> 
>   if (smu_dpm_ctx->dpm_level != level) {
> - switch (level) {
> - case AMD_DPM_FORCED_LEVEL_HIGH:
> - ret = smu_force_dpm_limit_value(smu, true);
> - break;
> - case AMD_DPM_FORCED_LEVEL_LOW:
> - ret = smu_force_dpm_limit_value(smu, false);
> - break;
> -
> - case AMD_DPM_FORCED_LEVEL_AUTO:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> - ret = smu_unforce_dpm_levels(smu);
> - break;
> -
> - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> - ret = smu_get_profiling_clk_mask(smu, level,
> -  _mask,
> -  _mask,
> -  _mask);
> - if (ret)
> - return ret;
> - smu_force_clk_levels(smu, SMU_SCLK, 1 <<
> sclk_mask);
> - smu_force_clk_levels(smu, SMU_MCLK, 1 <<
> mclk_mask);
> - smu_force_clk_levels(smu, SMU_SOCCLK, 1 <<
> soc_mask);
> - break;
> -
> - case AMD_DPM_FORCED_LEVEL_MANUAL:
> - case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
> - default:
> - break;
> + ret = smu_set_performance_level(smu, level);
> + if (ret) {
> + switch (level) {
> + case AMD_DPM_FORCED_LEVEL_HIGH:
> + ret = smu_force_dpm_limit_value(smu, true);
> + break;
> + case AMD_DPM_FORCED_LEVEL_LOW:
> + ret = smu_force_dpm_limit_value(smu, false);
> + break;
> +
> + case AMD_DPM_FORCED_LEVEL_AUTO:
> + case
> AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> + ret = smu_unforce_dpm_levels(smu);
> + break;
> +
> + case
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> + case
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> + ret = smu_get_profiling_clk_mask(smu, level,
> +  _mask,
> +  _mask,
> +  _mask);
> + if (ret)
> + return ret;
> + smu_force_clk_levels(smu, SMU_SCLK, 1 <<
> sclk_mask);
> + smu_force_clk_levels(smu, SMU_MCLK, 1 <<
> mclk_mask);
> + smu_force_clk_levels(smu, SMU_SOCCLK, 1
> << soc_mask);
> + break;
> +
> + case AMD_DPM_FORCED_LEVEL_MANUAL:
> + case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
> + default:
> + break;
> + }
>   }
> 
>   if (!ret)
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 514d31518853..ba5ddafcbdba 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -631,6 +631,7 @@ struct pptable_funcs {
>   int (*get_thermal_temperature_range)(struct smu_context *smu,
> struct 

[PATCH] drm/amd/powerplay: custom peak clock freq for navi10

[Wang, Kevin(Yang)]

1.NAVI10_PEAK_SCLK_XTX1830 Mhz
2.NAVI10_PEAK_SCLK_XT 1755 Mhz
3.NAVI10_PEAK_SCLK_XL 1625 Mhz

Change-Id: I48863a9d0e261b9e7778a6c0e4a8762d7c978da6
Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 65 ++-
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  4 ++
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 55 
 drivers/gpu/drm/amd/powerplay/navi10_ppt.h|  4 ++
 4 files changed, 97 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 7f51bbd2ac90..ab389dde9562 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1360,37 +1360,40 @@ int smu_adjust_power_state_dynamic(struct smu_context 
*smu,
}
 
if (smu_dpm_ctx->dpm_level != level) {
-   switch (level) {
-   case AMD_DPM_FORCED_LEVEL_HIGH:
-   ret = smu_force_dpm_limit_value(smu, true);
-   break;
-   case AMD_DPM_FORCED_LEVEL_LOW:
-   ret = smu_force_dpm_limit_value(smu, false);
-   break;
-
-   case AMD_DPM_FORCED_LEVEL_AUTO:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
-   ret = smu_unforce_dpm_levels(smu);
-   break;
-
-   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
-   ret = smu_get_profiling_clk_mask(smu, level,
-_mask,
-_mask,
-_mask);
-   if (ret)
-   return ret;
-   smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
-   smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
-   smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
-   break;
-
-   case AMD_DPM_FORCED_LEVEL_MANUAL:
-   case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
-   default:
-   break;
+   ret = smu_set_performance_level(smu, level);
+   if (ret) {
+   switch (level) {
+   case AMD_DPM_FORCED_LEVEL_HIGH:
+   ret = smu_force_dpm_limit_value(smu, true);
+   break;
+   case AMD_DPM_FORCED_LEVEL_LOW:
+   ret = smu_force_dpm_limit_value(smu, false);
+   break;
+
+   case AMD_DPM_FORCED_LEVEL_AUTO:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+   ret = smu_unforce_dpm_levels(smu);
+   break;
+
+   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+   ret = smu_get_profiling_clk_mask(smu, level,
+_mask,
+_mask,
+_mask);
+   if (ret)
+   return ret;
+   smu_force_clk_levels(smu, SMU_SCLK, 1 << 
sclk_mask);
+   smu_force_clk_levels(smu, SMU_MCLK, 1 << 
mclk_mask);
+   smu_force_clk_levels(smu, SMU_SOCCLK, 1 << 
soc_mask);
+   break;
+
+   case AMD_DPM_FORCED_LEVEL_MANUAL:
+   case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+   default:
+   break;
+   }
}
 
if (!ret)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 514d31518853..ba5ddafcbdba 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -631,6 +631,7 @@ struct pptable_funcs {
int (*get_thermal_temperature_range)(struct smu_context *smu, struct 
smu_temperature_range *range);
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t 
*clocks_in_khz, uint32_t *num_states);
int (*set_default_od_settings)(struct smu_context *smu, bool 
initialize);
+   int (*set_performance_level)(struct smu_context *smu, int32_t level);
 };
 
 struct smu_funcs
@@ -928,6 +929,9 @@ struct smu_funcs
((smu)->funcs->baco_get_state? 

Re: [PATCH 5/7] drm/amd/display: Use proper enum conversion functions

[Nathan Chancellor]

On Wed, Jul 03, 2019 at 10:52:16PM -0700, Nathan Chancellor wrote:
> clang warns:
> 
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:336:8:
> warning: implicit conversion from enumeration type 'enum smu_clk_type'
> to different enumeration type 'enum amd_pp_clock_type'
> [-Wenum-conversion]
> dc_to_smu_clock_type(clk_type),
> ^~~
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:421:14:
> warning: implicit conversion from enumeration type 'enum
> amd_pp_clock_type' to different enumeration type 'enum smu_clk_type'
> [-Wenum-conversion]
> dc_to_pp_clock_type(clk_type),
> ^~
> 
> There are functions to properly convert between all of these types, use
> them so there are no longer any warnings.
> 
> Fixes: a43913ea50a5 ("drm/amd/powerplay: add function 
> get_clock_by_type_with_latency for navi10")
> Fixes: e5e4e22391c2 ("drm/amd/powerplay: add interface to get clock by type 
> with latency for display (v2)")
> Link: https://github.com/ClangBuiltLinux/linux/issues/586
> Signed-off-by: Nathan Chancellor 
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index eac09bfe3be2..0f76cfff9d9b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -333,7 +333,7 @@ bool dm_pp_get_clock_levels_by_type(
>   }
>   } else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {
>   if (smu_get_clock_by_type(>smu,
> -   dc_to_smu_clock_type(clk_type),
> +   dc_to_pp_clock_type(clk_type),
> _clks)) {
>   get_default_clock_levels(clk_type, dc_clks);
>   return true;
> @@ -418,7 +418,7 @@ bool dm_pp_get_clock_levels_by_type_with_latency(
>   return false;
>   } else if (adev->smu.ppt_funcs && 
> adev->smu.ppt_funcs->get_clock_by_type_with_latency) {
>   if (smu_get_clock_by_type_with_latency(>smu,
> -
> dc_to_pp_clock_type(clk_type),
> +
> dc_to_smu_clock_type(clk_type),
>      _clks))
>   return false;
>   }
> -- 
> 2.22.0
> 

Gentle ping for review, this is the last remaining warning that I see
from amdgpu on next-20190718.

Cheers,
Nathan

RE: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

[Gui, Jack]

Hi Evan,
1, The hack hard code was just served for profile_peak mode and (max_count - 1) 
level always used for GFX clock, we just force the limit value with data from 
tool team.
2, The requirement from tool team is to force GFX clock limit value with 
different SKU’s clocks when enter profile peak mode, so the hack code was added 
when  clock adjust rules was applied.

From: Quan, Evan 
Sent: Thursday, July 18, 2019 6:32 PM
To: Gui, Jack ; amd-gfx@lists.freedesktop.org
Cc: Gui, Jack 
Subject: Re: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

1. In navi10_force_clk_levels, i think you need to compare the max level user 
requested with the peak limit and set the smaller one.
2. can you help me to understand why the change in apply_clock_rules is needed?


发件人: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 代表 Chengming Gui mailto:jack@amd.com>>
发送时间: Thursday, July 18, 2019 6:02:17 PM
收件人: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
抄送: Gui, Jack mailto:jack@amd.com>>
主题: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

force different GFX clocks with different SKUs for navi10:
XL  (other rev_id):  1625MHz
XT (F1/C1):  1755MHz
XTX(F0/C0):  1830MHz

Signed-off-by: Chengming Gui mailto:jack@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  2 +
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  2 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 66 +-
 3 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 122985c..693414f 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -664,6 +664,8 @@ static int smu_sw_init(void *handle)
 smu->watermarks_bitmap = 0;
 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+   smu->smu_dpm.default_sclk_limit = 0;
+   smu->smu_dpm.peak_sclk_limit = 0;

 smu->workload_mask = 1 << 
smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 135a323..acb522b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -441,6 +441,8 @@ struct smu_dpm_context {
 void *dpm_context;
 void *golden_dpm_context;
 bool enable_umd_pstate;
+   uint32_t default_sclk_limit;
+   uint32_t peak_sclk_limit;
 enum amd_dpm_forced_level dpm_level;
 enum amd_dpm_forced_level saved_dpm_level;
 enum amd_dpm_forced_level requested_dpm_level;
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e5..b4deb9e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -37,6 +37,15 @@

 #include "asic_reg/mp/mp_11_0_sh_mask.h"

+#define NV_NV10_F0 0xF0
+#define NV_NV10_C0 0xC0
+#define NV_NV10_F1 0xF1
+#define NV_NV10_C1 0xC1
+
+#define NV_NV10_PEAK_SCLK_XTX 1830
+#define NV_NV10_PEAK_SCLK_XT  1755
+#define NV_NV10_PEAK_SCLK_XL  1625
+
 #define FEATURE_MASK(feature) (1ULL << feature)
 #define SMC_DPM_FEATURE ( \
 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
@@ -675,6 +684,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,

 int ret = 0, size = 0;
 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, 
max_freq = 0;
+   struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);

 soft_min_level = mask ? (ffs(mask) - 1) : 0;
 soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -682,6 +692,23 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 switch (clk_type) {
 case SMU_GFXCLK:
 case SMU_SCLK:
+   if (smu_dpm_ctx->peak_sclk_limit) {
+   max_freq = smu_dpm_ctx->peak_sclk_limit;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
+   if (ret)
+   return size;
+   } else {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
+   if (ret)
+   return size;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_max_level, _freq);
+   if (ret)
+   return size;
+   }
+   ret = smu_set_soft_freq_range(smu, clk_type, min_freq, 
max_freq);
+   if (ret)
+   return size;
+   break;

RE: [PATCH] drm/amdgpu/smu: move fan rpm query into the asic specific code

[Quan, Evan]

Reviewed-by: Evan Quan 

> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: Friday, July 19, 2019 4:28 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH] drm/amdgpu/smu: move fan rpm query into the asic
> specific code
> 
> On vega20, there is an SMU message to query it.  On navi, it's fetched from
> the metrics table.
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c|  4 ++--
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  6 +++---
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 12 ++-
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 -
>  drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 20
> ++-
>  5 files changed, 31 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 8b7efd0a7028..03ca8c69114f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1734,7 +1734,7 @@ static ssize_t
> amdgpu_hwmon_get_fan1_input(struct device *dev,
>   return -EINVAL;
> 
>   if (is_support_sw_smu(adev)) {
> - err = smu_get_current_rpm(>smu, );
> + err = smu_get_fan_speed_rpm(>smu, );
>   if (err)
>   return err;
>   } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) { @@ -
> 1794,7 +1794,7 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct
> device *dev,
>   return -EINVAL;
> 
>   if (is_support_sw_smu(adev)) {
> - err = smu_get_current_rpm(>smu, );
> + err = smu_get_fan_speed_rpm(>smu, );
>   if (err)
>   return err;
>   } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) { diff --
> git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 514d31518853..87e44c3a2d73 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -623,6 +623,7 @@ struct pptable_funcs {
>   int (*tables_init)(struct smu_context *smu, struct smu_table
> *tables);
>   int (*set_thermal_fan_table)(struct smu_context *smu);
>   int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t
> *speed);
> + int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t
> *speed);
>   int (*set_watermarks_table)(struct smu_context *smu, void
> *watermarks,
>   struct
> dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
>   int (*get_current_clk_freq_by_table)(struct smu_context *smu,
> @@ -695,7 +696,6 @@ struct smu_funcs
>   int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
>  struct
> dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
>   int (*conv_power_profile_to_pplib_workload)(int power_profile);
> - int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
>   uint32_t (*get_fan_control_mode)(struct smu_context *smu);
>   int (*set_fan_control_mode)(struct smu_context *smu, uint32_t
> mode);
>   int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t
> speed); @@ -761,8 +761,6 @@ struct smu_funcs
>   ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs-
> >init_max_sustainable_clocks((smu)) : 0)  #define
> smu_set_default_od_settings(smu, initialize) \
>   ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs-
> >set_default_od_settings((smu), (initialize)) : 0) -#define
> smu_get_current_rpm(smu, speed) \
> - ((smu)->funcs->get_current_rpm ? (smu)->funcs-
> >get_current_rpm((smu), (speed)) : 0)
>  #define smu_set_fan_speed_rpm(smu, speed) \
>   ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs-
> >set_fan_speed_rpm((smu), (speed)) : 0)  #define
> smu_send_smc_msg(smu, msg) \ @@ -851,6 +849,8 @@ struct smu_funcs
>   ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs-
> >get_fan_speed_percent((smu), (speed)) : 0)  #define
> smu_set_fan_speed_percent(smu, speed) \
>   ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs-
> >set_fan_speed_percent((smu), (speed)) : 0)
> +#define smu_get_fan_speed_rpm(smu, speed) \
> + ((smu)->ppt_funcs->get_fan_speed_rpm ?
> +(smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
> 
>  #define smu_msg_get_index(smu, msg) \
>   ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index?
> (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 80daded31970..352fab1b3444 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -974,12 +974,13 @@ static bool navi10_is_dpm_running(struct
> smu_context *smu)
>   return !!(feature_enabled & SMC_DPM_FEATURE);  }
> 
> 

Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends

[Kuehling, Felix]

On 2019-07-18 4:47 a.m., Christian König wrote:

[snip]

>>> This is a corner case we can handle later on. As long as the VM is
>>> still alive just allocating page tables again should be sufficient for
>>> this.
>> Do you mean, instead of migrating page tables back, throwing them away
>> and allocating a new one?
>
> Yes, exactly that's the idea here. 

OK, I think that would work. The thing with direct submission and not 
waiting for fences is, that you only have implicit synchronization with 
anything else that was also submitted directly to the same SDMA ring. So 
page table allocation and initialization would work fine. Migration 
would not, unless you have special cases for migration of page table BOs.

There is also a more general issue with direct submission that I found 
while you were on vacation. There is no locking of the ring buffer. So 
direct and non-direct submission to the same ring is broken at the moment.


> I mean it's perfectly possible that the process is killed while 
> faults
> are still in the pipeline.
>
>> I think it's possible that a page table gets evicted while a page
>> fault
>> is pending. Maybe not with graphics, but definitely with compute 
>> where
>> waves can be preempted while waiting for a page fault. In that case
>> the
>> direct access would break.
>>
>> Even with graphics I think it's still possible that new page tables
>> need
>> to be allocated to handle a page fault. When that happens, you 
>> need to
>> wait for fences to let new page tables be validated and initialized.
> Yeah, the problem here is that when you wait on fences which in turn
> depend on your submission your end up in a deadlock.
>
 I think this implies that you have amdgpu_cs fences attached to page
 tables. I believe this is the fundamental issue that needs to be 
 fixed.
>>> We still need this cause even with page faults the root PD can't be
>>> evicted.
>>>
>>> What we can probably do is to split up the PDs/PTs into the root PD
>>> and everything else.
>> Yeah, the root PD always exists as long as the VM exists. Everything
>> else can be created/destroyed/moved dynamically.
>
> Yeah, exactly. The question is how do we want to keep the root PD in 
> place?
>
> We could still add the fence or we could pin it permanently.

Right. I was thinking permanent pinning can lead to fragmentation. It 
would be good if those small root PDs could be moved around to make room 
for bigger contiguous allocations when needed.


>
 If you want to manage page tables in page fault interrupt handlers, 
 you
 can't have command submission fences attached to your page tables. You
 can allow page tables to be evicted while the command submission is in
 progress. A page fault will fault it back in if it's needed. If you
 eliminate command submission fences on the page tables, you remove the
 potential for deadlocks.
>>> No, there is still a huge potential for deadlocks here.
>>>
>>> Additional to the root PDs you can have a MM submission which needs to
>>> wait for a compute submission to be finished.
>> I assume by MM you mean "memory manger", not "multi-media". [SNIP]
>
> Sorry I meant "multi-media", so just snipped your response.
>
> What I want to say here is that I don't believe we can keep user CS 
> fences our of memory management.
>
> See there can be submission from engines which don't support or don't 
> want to enabled recoverable page faults which depend on submissions 
> which do use recoverable page faults.
>
> I mean it was your requirement that we have a mix of page fault and 
> pre-filled page tables in the same process.

Right. There are a few different requirements:

 1. Disable retry faults and instruction replay for a VM completely
(better performance for ML shaders)
 2. Pre-fill page tables even when retry faults are enabled

In case #2 we could deal with page tables being evicted (not fenced). 
But MM engines that don't support retry faults would throw a wrench in 
this idea.


>
>>> If you then make your new allocation depend on the MM submission to be
>>> finished you have a classical circle dependency and a deadlock at hand.
>> I don't see it. Allocate page table, wait for fence associated with that
>> page table initialization, update PTEs. At no point do we depend on the
>> user CS being stalled by the page fault. There is not user submission on
>> the paging ring. Anything that has been scheduled on the paging ring has
>> its dependencies satisfied.
>
> Allocation is the main problem here. We need to make sure that we 
> never ever depend on user CS when making memory allocation in the page 
> fault handler.
>> We may need separate scheduler entities
>> (queues) for regular MM submissions that can depend on user fences and
>> VM submissions that must not.
>
> Yeah, thought about that as well but even then you need a way to note 
> that you want to use this separate 

[pull] amdgpu, amdkfd drm-next-5.3

[Alex Deucher]

Hi Dave, Daniel,

Fixes for 5.3, mostly for Navi.

The following changes since commit 7f963d9f69bf28d639013630da30d7a4c95edd5d:

  drm/amdgpu/navi10: add uclk activity sensor (2019-07-09 17:43:36 -0500)

are available in the Git repository at:

  git://people.freedesktop.org/~agd5f/linux tags/drm-next-5.3-2019-07-18

for you to fetch changes up to 41a5a2a8531f95d18bb4efddea581ccb469e8ee5:

  drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq 
(2019-07-18 14:12:08 -0500)


drm-next-5.3-2019-07-18:

amdgpu:
- Navi DC fix for secondary adapters
- Fix Navi flickering with high res panels
- Navi SMU fixes
- Vega20 SMU fixes
- Fixes for audio hotplug on HG systems
- Fix for potential integer overflows on large buffer
  migrations
- debugfs fixes for umr
- Various other small fixes

amdkfd:
- Apply noretry setting consistently
- Fix hang in eviction
- Properly clean up GWS on uninit

UAPI:
- clarify a comment on ctx priority


Alex Deucher (4):
  drm/amdgpu/psp: add a mutex to protect access to the psp ring
  drm/amdgpu: enable IP discovery by default on navi
  drm/amdgpu: drop dead header
  drm/amdgpu/pm: remove check for pp funcs in freq sysfs handlers

Arnd Bergmann (3):
  drm/amd/display: Support clang option for stack alignment
  drm/amd/display: return 'NULL' instead of 'false' from 
dcn20_acquire_idle_pipe_for_layer
  drm/amd/amdgpu: hide #warning for missing DC config

Emil Velikov (1):
  drm/amdgpu: extend AMDGPU_CTX_PRIORITY_NORMAL comment

Eric Huang (1):
  drm/amdkfd: fix cp hang in eviction

Evan Quan (7):
  drm/amd/powerplay: increase the SMU msg response waiting time
  drm/amd/powerplay: fix memory allocation failure check V2
  drm/amd/powerplay: avoid access before allocation
  drm/amd/powerplay: fix deadlock around smu_handle_task V2
  drm/amd/powerplay: correct smu_update_table usage
  drm/amd/powerplay: maintain SMU FW backward compatibility
  drm/amd/powerplay: update vega20 driver if to fit latest SMU firmware

Felix Kuehling (4):
  drm/amdgpu: Fix potential integer overflows
  drm/amdkfd: Consistently apply noretry setting
  drm/amdgpu: Fix unaligned memory copies
  drm/amdgpu: Fix silent amdgpu_bo_move failures

Fuqian Huang (1):
  drm/amdgpu: remove memset after kzalloc

Hawking Zhang (3):
  drm/amdgpu: switch to macro for psp bootloader command
  drm/amdgpu: support key database loading for navi10
  drm/amdgpu: check kdb_bin_size to exclude kdb loading sequence

Joseph Greathouse (1):
  drm/amdkfd: Remove GWS from process during uninit

Kenneth Feng (2):
  drm/amd/powerplay: bug fix for sysfs
  drm/amd/powerplay: enable fw ctf,apcc dfll and gfx ss

Kent Russell (1):
  drm/amdgpu: Fix Vega20 Perf counter for pcie_bw

Kevin Wang (7):
  drm/amd/powerplay: fix smu clock type change miss error
  drm/amd/powerplay: add pstate mclk(uclk) support for navi10
  drm/amd/powerplay: add socclk profile dpm support.
  drm/amd/powerplay: add standard profile dpm support for smu
  drm/amd/powerplay: avoid double check feature enabled
  drm/amd/powerplay: fix save dpm level error for smu
  drm/amd/powerplay: add helper of smu_clk_dpm_is_enabled for smu

Nathan Chancellor (1):
  drm/amd/powerplay: Use proper enums in vega20_print_clk_levels

Nicholas Kazlauskas (3):
  drm/amd/display: Expose audio inst from DC to DM
  drm/amd/display: Add drm_audio_component support to amdgpu_dm
  drm/amd/display: Force uclk to max for every state

Nicolai Hähnle (1):
  drm/amdgpu/gfx10: set SH_MEM_CONFIG.INITIAL_INST_PREFETCH

Paul Menzel (1):
  drm/amdgpu: Print out voltage in DM_PPLIB

Tom St Denis (3):
  drm/amd/amdgpu: Add VMID to SRBM debugfs bank selection
  drm/amd/amdgpu: Add missing select_me_pipe_q() for gfx10
  drm/amd/amdgpu: Fix offset for vmid selection in debugfs interface

Wang Xiayang (1):
  drm/amdgpu: replace simple_strtol() by kstrtou32()

hersen wu (1):
  drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq

tiancyin (1):
  drm/amdgpu/discovery: fix DCE_HWIP mapping error in hw_id_map array

 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|   9 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c  |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  19 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h|   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  13 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c|  25 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h|  12 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  51 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c  |   6 +
 

RE: [PATCH v2] drm/amdgpu: Default disable GDS for compute VMIDs

[Greathouse, Joseph]

> -Original Message-
> From: Christian König 
> Sent: Thursday, July 18, 2019 3:14 AM
> To: Kuehling, Felix ; Greathouse, Joseph
> ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2] drm/amdgpu: Default disable GDS for compute
> VMIDs
> 
> Am 17.07.19 um 22:09 schrieb Kuehling, Felix:
> > On 2019-07-17 14:23, Greathouse, Joseph wrote:
> >> The GDS and GWS blocks default to allowing all VMIDs to
> >> access all entries. Graphics VMIDs can handle setting
> >> these limits when the driver launches work. However,
> >> compute workloads under HWS control don't go through the
> >> kernel driver. Instead, HWS firmware should set these
> >> limits when a process is put into a VMID slot.
> >>
> >> Disable access to these devices by default by turning off
> >> all mask bits (for OA) and setting BASE=SIZE=0 (for GDS
> >> and GWS) for all compute VMIDs. If a process wants to use
> >> these resources, they can request this from the HWS
> >> firmware (when such capabilities are enabled). HWS will
> >> then handle setting the base and limit for the process when
> >> it is assigned to a VMID.
> >>
> >> This will also prevent user kernels from getting 'stuck' in
> >> GWS by accident if they write GWS-using code but HWS
> >> firmware is not set up to handle GWS reset. Until HWS is
> >> enabled to handle GWS properly, all GWS accesses will
> >> MEM_VIOL fault the kernel.
> >>
> >> v2: Move initialization outside of SRBM mutex
> >>
> >> Change-Id: I8edcea9d0b14d16a7444bcf9fbf9451aef8b707d
> >> Signed-off-by: Joseph Greathouse 
> > Reviewed-by: Felix Kuehling 
> 
> Might be a good idea to do this for all VMIDs during initialization and
> not just for the ones used for compute.
> 
> But anyway patch is Reviewed-by: Christian König
> .

Hmm, good point. It looks like graphics jobs will eventually call through to 
emit_gds_switch() to set these when launching a job, but it may be worthwhile 
to set these to zero as a default. I didn't want to step on any toes on the 
graphics side without checking first.

Do you have opinions on the most reasonable location to do this? early_init(), 
late_init()? The various gfx_v*_set_gds_init() might be a good place -- a quick 
test of setting all 16 VMIDs in gfx_v9_0_set_gds_init() appears to work fine on 
my Vega 20.

-Joe
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Re: The problem "ring gfx timeout" are experienced yet another AMD GPU Vega 8 user

[Mikhail Gavrilov]

On Wed, 3 Jul 2019 at 23:57, Marek Olšák  wrote:
>
> It looks like memory corruption. You can try to disable IOMMU in the BIOS.
>

We disabled IOMMU in the BIOS [1].
And was run the memory check with MemTest86.
MemTest86 did not find any memory problems [2].

But previously reported issue with GPU hanging, unfortunately, happens again.

[17571.578988] amdgpu :08:00.0: [gfxhub] no-retry page fault
(src_id:0 ring:158 vmid:7 pasid:32776, for process hoi4 pid 9225
thread hoi4:cs0 pid 9226)
[17571.578992] amdgpu :08:00.0:   in page starting at address
0x4416 from 27
[17571.578994] amdgpu :08:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x0070153C
[17576.635622] [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR*
Waiting for fences timed out.
[17581.755948] [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR*
Waiting for fences timed out.
[17581.765672] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx
timeout, signaled seq=1520345, emitted seq=1520347
[17581.765765] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process
information: process hoi4 pid 9225 thread hoi4:cs0 pid 9226
[17581.765766] [drm] GPU recovery disabled.
[17586.875783] [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR*
Waiting for fences timed out.
[17592.005836] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx
timeout, signaled seq=1520345, emitted seq=1520347
[17592.005921] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process
information: process hoi4 pid 9225 thread hoi4:cs0 pid 9226
[17592.005923] [drm] GPU recovery disabled.


No more ideas on how memory may be corrupted?

Fresh logs uploaded here [3].

Thanks.

[1] https://postimg.cc/RJLYWgH7
[2] https://postimg.cc/Fk4qFM7F
[3] https://mega.nz/#F!8xphjAJL!7HVUz-NyRaICjCSu_x-fFA

--
Best Regards,
Mike Gavrilov.
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[PATCH] drm/amdgpu/smu: move fan rpm query into the asic specific code

[Alex Deucher]

On vega20, there is an SMU message to query it.  On navi, it's fetched
from the metrics table.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c|  4 ++--
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  6 +++---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 12 ++-
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 -
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 20 ++-
 5 files changed, 31 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 8b7efd0a7028..03ca8c69114f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1734,7 +1734,7 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device 
*dev,
return -EINVAL;
 
if (is_support_sw_smu(adev)) {
-   err = smu_get_current_rpm(>smu, );
+   err = smu_get_fan_speed_rpm(>smu, );
if (err)
return err;
} else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
@@ -1794,7 +1794,7 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct device 
*dev,
return -EINVAL;
 
if (is_support_sw_smu(adev)) {
-   err = smu_get_current_rpm(>smu, );
+   err = smu_get_fan_speed_rpm(>smu, );
if (err)
return err;
} else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 514d31518853..87e44c3a2d73 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -623,6 +623,7 @@ struct pptable_funcs {
int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
int (*set_thermal_fan_table)(struct smu_context *smu);
int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
+   int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
struct 
dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
int (*get_current_clk_freq_by_table)(struct smu_context *smu,
@@ -695,7 +696,6 @@ struct smu_funcs
int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
   struct 
dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
int (*conv_power_profile_to_pplib_workload)(int power_profile);
-   int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
uint32_t (*get_fan_control_mode)(struct smu_context *smu);
int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
@@ -761,8 +761,6 @@ struct smu_funcs
((smu)->funcs->init_max_sustainable_clocks ? 
(smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
 #define smu_set_default_od_settings(smu, initialize) \
((smu)->ppt_funcs->set_default_od_settings ? 
(smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
-#define smu_get_current_rpm(smu, speed) \
-   ((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), 
(speed)) : 0)
 #define smu_set_fan_speed_rpm(smu, speed) \
((smu)->funcs->set_fan_speed_rpm ? 
(smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
 #define smu_send_smc_msg(smu, msg) \
@@ -851,6 +849,8 @@ struct smu_funcs
((smu)->ppt_funcs->get_fan_speed_percent ? 
(smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
 #define smu_set_fan_speed_percent(smu, speed) \
((smu)->funcs->set_fan_speed_percent ? 
(smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
+#define smu_get_fan_speed_rpm(smu, speed) \
+   ((smu)->ppt_funcs->get_fan_speed_rpm ? 
(smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
 
 #define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? 
(smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 80daded31970..352fab1b3444 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -974,12 +974,13 @@ static bool navi10_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
 }
 
-static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value)
+static int navi10_get_fan_speed_rpm(struct smu_context *smu,
+   uint32_t *speed)
 {
SmuMetrics_t metrics;
int ret = 0;
 
-   if (!value)
+   if (!speed)
return -EINVAL;
 
memset(, 0, sizeof(metrics));
@@ -989,7 +990,7 @@ static int 

[PATCH] Collect all page_base_address bits for pte-further addresses (v2)

[StDenis, Tom]

The specification says to treat a PTE with the F bit set "like a PDE"
which means that all but the lower 6 bits are part of the page base
address.  Indeed, in the wild a comment came back indicating that
we were stripping off bits needed to properly fetch the next
PTE.

(v2): Only capture excess bits if it is a PTE-FURTHER entry

Signed-off-by: Tom St Denis 
---
 src/lib/read_vram.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c
index cba8f6b..e83a85c 100644
--- a/src/lib/read_vram.c
+++ b/src/lib/read_vram.c
@@ -676,7 +676,7 @@ pde_is_pte:
pte_idx = (address >> 12) & ((1ULL << 
pde_fields.frag_size) - 1);
 
// grab PTE base address from the PTE that has 
the F bit set.
-   pde_fields.pte_base_addr = 
pte_fields.page_base_addr;
+   pde_fields.pte_base_addr = pte_entry & 
0xFFC0ULL;
goto pte_further;
}
 
-- 
2.21.0

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Re: [PATCH] drm/radeon: Prefer pcie_capability_read_word()

[Bjorn Helgaas]

On Wed, Jul 17, 2019 at 9:08 PM Frederick Lawler  wrote:
>
> Commit 8c0d3a02c130 ("PCI: Add accessors for PCI Express Capability")
> added accessors for the PCI Express Capability so that drivers didn't
> need to be aware of differences between v1 and v2 of the PCI
> Express Capability.
>
> Replace pci_read_config_word() and pci_write_config_word() calls with
> pcie_capability_read_word() and pcie_capability_write_word().
>
> Signed-off-by: Frederick Lawler 
> ---
>  drivers/gpu/drm/radeon/cik.c | 70 +-
>  drivers/gpu/drm/radeon/si.c  | 73 +++-
>  2 files changed, 90 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index ab7b4e2ffcd2..f6c91ac5427a 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -9500,7 +9500,6 @@ static void cik_pcie_gen3_enable(struct radeon_device 
> *rdev)
>  {
> struct pci_dev *root = rdev->pdev->bus->self;
> enum pci_bus_speed speed_cap;
> -   int bridge_pos, gpu_pos;
> u32 speed_cntl, current_data_rate;
> int i;
> u16 tmp16;
> @@ -9542,12 +9541,7 @@ static void cik_pcie_gen3_enable(struct radeon_device 
> *rdev)
> DRM_INFO("enabling PCIE gen 2 link speeds, disable with 
> radeon.pcie_gen2=0\n");
> }
>
> -   bridge_pos = pci_pcie_cap(root);
> -   if (!bridge_pos)
> -   return;
> -
> -   gpu_pos = pci_pcie_cap(rdev->pdev);
> -   if (!gpu_pos)
> +   if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))
> return;
>
> if (speed_cap == PCIE_SPEED_8_0GT) {
> @@ -9557,14 +9551,17 @@ static void cik_pcie_gen3_enable(struct radeon_device 
> *rdev)
> u16 bridge_cfg2, gpu_cfg2;
> u32 max_lw, current_lw, tmp;
>
> -   pci_read_config_word(root, bridge_pos + 
> PCI_EXP_LNKCTL, _cfg);
> -   pci_read_config_word(rdev->pdev, gpu_pos + 
> PCI_EXP_LNKCTL, _cfg);
> +   pcie_capability_read_word(root, PCI_EXP_LNKCTL,
> + _cfg);
> +   pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
> + _cfg);
>
> tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
> -   pci_write_config_word(root, bridge_pos + 
> PCI_EXP_LNKCTL, tmp16);
> +   pcie_capability_write_word(root, PCI_EXP_LNKCTL, 
> tmp16);
>
> tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
> -   pci_write_config_word(rdev->pdev, gpu_pos + 
> PCI_EXP_LNKCTL, tmp16);
> +   pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
> +  tmp16);
>
> tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
> max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> 
> LC_DETECTED_LINK_WIDTH_SHIFT;
> @@ -9582,15 +9579,23 @@ static void cik_pcie_gen3_enable(struct radeon_device 
> *rdev)
>
> for (i = 0; i < 10; i++) {
> /* check status */
> -   pci_read_config_word(rdev->pdev, gpu_pos + 
> PCI_EXP_DEVSTA, );
> +   pcie_capability_read_word(rdev->pdev,
> + PCI_EXP_DEVSTA,
> + );
> if (tmp16 & PCI_EXP_DEVSTA_TRPND)
> break;
>
> -   pci_read_config_word(root, bridge_pos + 
> PCI_EXP_LNKCTL, _cfg);
> -   pci_read_config_word(rdev->pdev, gpu_pos + 
> PCI_EXP_LNKCTL, _cfg);
> +   pcie_capability_read_word(root, 
> PCI_EXP_LNKCTL,
> + _cfg);
> +   pcie_capability_read_word(rdev->pdev,
> + PCI_EXP_LNKCTL,
> + _cfg);
>
> -   pci_read_config_word(root, bridge_pos + 
> PCI_EXP_LNKCTL2, _cfg2);
> -   pci_read_config_word(rdev->pdev, gpu_pos + 
> PCI_EXP_LNKCTL2, _cfg2);
> +   pcie_capability_read_word(root, 
> PCI_EXP_LNKCTL2,
> + _cfg2);
> +   pcie_capability_read_word(rdev->pdev,
> + PCI_EXP_LNKCTL2,
> + _cfg2);
>
> tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
> tmp |= LC_SET_QUIESCE;
> @@ -9603,26 

[PATCH] Collect all page_base_address bits for pte-further addresses

[StDenis, Tom]

The specification says to treat a PTE with the F bit set "like a PDE"
which means that all but the lower 6 bits are part of the page base
address.  Indeed, in the wild a comment came back indicating that
we were stripping off bits needed to properly fetch the next
PTE.

Signed-off-by: Tom St Denis 
---
 src/lib/read_vram.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c
index cba8f6b..209ca84 100644
--- a/src/lib/read_vram.c
+++ b/src/lib/read_vram.c
@@ -654,7 +654,7 @@ pte_further:
 
// decode PTE values
 pde_is_pte:
-   pte_fields.page_base_addr = pte_entry & 
0xF000ULL;
+   pte_fields.page_base_addr = pte_entry & 
0xFFC0ULL; // all but bottom 6 bits are PBA
pte_fields.fragment   = (pte_entry >> 7)  & 0x1F;
pte_fields.system = (pte_entry >> 1) & 1;
pte_fields.valid  = pte_entry & 1;
-- 
2.21.0

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Re: [PATCH 07/87] drm/amd/display: move bw calc code into helpers

[Li, Sun peng (Leo)]

On 2019-07-18 10:49 a.m., Michel Dänzer wrote:
> On 2019-07-15 11:19 p.m., sunpeng...@amd.com wrote:
>> From: Eric Yang 
>>
>> [Why]
>> For better readability and reusability
>>
>> [How]
>> Move snippets of BW calculation code into helpers.
>>
>> Signed-off-by: Eric Yang 
>> Reviewed-by: Fatemeh Darbehani 
>> Acked-by: Leo Li 
>> ---
>>  [...]
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index 086d2f3b0db3..e9ccf41e31ee 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -126,6 +126,7 @@ static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
>>  amdgpu_device_get_pcie_replay_count, NULL);
>>  
>>  static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
>> +static void amdgpu_device_parse_faked_did(struct amdgpu_device *adev);
> 
> This function isn't defined anywhere, producing a warning:
> 
> drivers/gpu/drm//amd/amdgpu/amdgpu_device.c:131:13: warning: 
> ‘amdgpu_device_parse_faked_did’ declared ‘static’ but never defined 
> [-Wunused-function]
>  static void amdgpu_device_parse_faked_did(struct amdgpu_device *adev);
>  ^

Oops, I don't know how that managed to get in there. It's not even in
the display dir...

Sent a fix.

Leo
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[PATCH xf86-video-ati] Don't disable page flipping completely with SW cursor

[Michel Dänzer]

From: Michel Dänzer 

Even with SW cursor, page flipping can be used while no X cursor is
visible.

Occurred to me in the context of xorg/xserver#828.
(Ported from amdgpu commit 87f41ace4920fd2069794211683659eb25b025a6)

Signed-off-by: Michel Dänzer 
---
 src/radeon_kms.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index ff4f8dcf6..777fc14ee 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -1917,19 +1917,15 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
 
 if (!pScrn->is_gpu) {
if (info->dri2.pKernelDRMVersion->version_minor >= 8) {
-   Bool sw_cursor = xf86ReturnOptValBool(info->Options,
- OPTION_SW_CURSOR, FALSE);
-
info->allowPageFlip = xf86ReturnOptValBool(info->Options,
   OPTION_PAGE_FLIP, TRUE);
 
-   if (sw_cursor || info->shadow_primary) {
+   if (info->shadow_primary) {
xf86DrvMsg(pScrn->scrnIndex,
   info->allowPageFlip ? X_WARNING : X_DEFAULT,
   "KMS Pageflipping: disabled%s\n",
   info->allowPageFlip ?
-  (sw_cursor ? " because of SWcursor" :
-   " because of ShadowPrimary") : "");
+  " because of ShadowPrimary" : "");
info->allowPageFlip = FALSE;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-- 
2.22.0

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[PATCH] drm/amdgpu: Remove undefined amdgpu_device_parse_faked_did

[sunpeng.li]

From: Leo Li 

This forward declare was added for no apparent reason. Remove it to
resolve this warning:

drivers/gpu/drm//amd/amdgpu/amdgpu_device.c:131:13: warning: 
‘amdgpu_device_parse_faked_did’ declared ‘static’ but never defined 
[-Wunused-function]
 static void amdgpu_device_parse_faked_did(struct amdgpu_device *adev);

Cc: Michel Dänzer 
Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 76106ad8ac84..4425ff06ecc4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -128,7 +128,6 @@ static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
amdgpu_device_get_pcie_replay_count, NULL);
 
 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
-static void amdgpu_device_parse_faked_did(struct amdgpu_device *adev);
 
 /**
  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
-- 
2.22.0

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RE: [PATCH 87/87] drm/amd/display: Force uclk to max for every state

[Liu, Zhan]

Reviewed-by: Zhan Liu 




-Original Message-
From: amd-gfx  On Behalf Of 
sunpeng...@amd.com
Sent: Monday, July 15, 2019 5:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Sun peng (Leo) ; Kazlauskas, Nicholas 

Subject: [PATCH 87/87] drm/amd/display: Force uclk to max for every state

From: Nicholas Kazlauskas 

Workaround for now to avoid underflow.

The uclk switch time should really be bumped up to 404, but doing so would 
expose p-state hang issues for higher bandwidth display configurations.

Change-Id: I98060fc9c4eeece07ef54e13a144def88a3c3d21
Signed-off-by: Nicholas Kazlauskas 
Signed-off-by: Leo Li 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c   |  6 +++---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  | 10 ++
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 983a1bd56272..74697cef5dfe 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -912,11 +912,11 @@ void dm_pp_get_funcs(
/* todo set_pme_wa_enable cause 4k@6ohz display not light up */
funcs->nv_funcs.set_pme_wa_enable = NULL;
/* todo debug waring message */
-   funcs->nv_funcs.set_hard_min_uclk_by_freq = NULL;
+   funcs->nv_funcs.set_hard_min_uclk_by_freq = 
+pp_nv_set_hard_min_uclk_by_freq;
/* todo  compare data with window driver*/
-   funcs->nv_funcs.get_maximum_sustainable_clocks = NULL;
+   funcs->nv_funcs.get_maximum_sustainable_clocks = 
+pp_nv_get_maximum_sustainable_clocks;
/*todo  compare data with window driver */
-   funcs->nv_funcs.get_uclk_dpm_states = NULL;
+   funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
break;
 #endif
default:
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2cf788a3704e..44537651f0a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2707,6 +2707,9 @@ static void cap_soc_clocks(
&& max_clocks.uClockInKhz != 0)
bb->clock_limits[i].dram_speed_mts = 
(max_clocks.uClockInKhz / 1000) * 16;
 
+   // HACK: Force every uclk to max for now to "disable" uclk 
switching.
+   bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 
1000) 
+* 16;
+
if ((bb->clock_limits[i].fabricclk_mhz > 
(max_clocks.fabricClockInKhz / 1000))
&& max_clocks.fabricClockInKhz 
!= 0)
bb->clock_limits[i].fabricclk_mhz = 
(max_clocks.fabricClockInKhz / 1000); @@ -2922,6 +2925,8 @@ static bool 
init_soc_bounding_box(struct dc *dc,
le32_to_cpu(bb->vmm_page_size_bytes);
dcn2_0_soc.dram_clock_change_latency_us =

fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
+   // HACK!! Lower uclock latency switch time so we don't switch
+   dcn2_0_soc.dram_clock_change_latency_us = 10;
dcn2_0_soc.writeback_dram_clock_change_latency_us =

fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
dcn2_0_soc.return_bus_width_bytes =
@@ -2963,6 +2968,7 @@ static bool init_soc_bounding_box(struct dc *dc,
struct pp_smu_nv_clock_table max_clocks = {0};
unsigned int uclk_states[8] = {0};
unsigned int num_states = 0;
+   int i;
enum pp_smu_status status;
bool clock_limits_available = false;
bool uclk_states_available = false;
@@ -2984,6 +2990,10 @@ static bool init_soc_bounding_box(struct dc *dc,
clock_limits_available = (status == PP_SMU_RESULT_OK);
}
 
+   // HACK: Use the max uclk_states value for all elements.
+   for (i = 0; i < num_states; i++)
+   uclk_states[i] = uclk_states[num_states - 1];
+
if (clock_limits_available && uclk_states_available && 
num_states)
update_bounding_box(dc, _0_soc, _clocks, 
uclk_states, num_states);
else if (clock_limits_available)
--
2.22.0

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Re: [PATCH] drm/amdgpu/: use VCN firmware offset for cache window

[Deucher, Alexander]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Liu, Leo 

Sent: Thursday, July 18, 2019 11:46 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Leo
Subject: [PATCH] drm/amdgpu/: use VCN firmware offset for cache window

Since we are using the signed FW now, and also using PSP firmware loading,
but it's still potential to break driver when loading FW directly
instead of PSP, so we should add offset.

Signed-off-by: Leo Liu 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 3cb62e448a37..88e3dedcf926 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -379,11 +379,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 upper_32_bits(adev->vcn.inst->gpu_addr));
 offset = size;
-   /* No signed header for now from firmware
 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
-   */
-   WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 }

 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
--
2.20.1

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[PATCH] drm/amdgpu: use VCN firmware offset for cache window

[Liu, Leo]

Since we are using the signed FW now, and also using PSP firmware loading,
but it's still potential to break driver when loading FW directly
instead of PSP, so we should add offset.

Signed-off-by: Leo Liu 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 3cb62e448a37..88e3dedcf926 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -379,11 +379,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
upper_32_bits(adev->vcn.inst->gpu_addr));
offset = size;
-   /* No signed header for now from firmware
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
-   */
-   WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
}
 
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
-- 
2.20.1

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[PATCH] drm/amdgpu/: use VCN firmware offset for cache window

[Liu, Leo]

Since we are using the signed FW now, and also using PSP firmware loading,
but it's still potential to break driver when loading FW directly
instead of PSP, so we should add offset.

Signed-off-by: Leo Liu 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 3cb62e448a37..88e3dedcf926 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -379,11 +379,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
upper_32_bits(adev->vcn.inst->gpu_addr));
offset = size;
-   /* No signed header for now from firmware
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
-   */
-   WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
}
 
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
-- 
2.20.1

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[PATCH] drm/amdkfd: Add DID for Navi12

[Liu, Shaoyun]

Add device id for KFD

Change-Id: I44e8e884d0dc86209de7c0b6f4784d06ee371079
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 2514263..cb6bd3a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -458,6 +458,9 @@ static const struct kfd_deviceid supported_devices[] = {
{ 0x7318, _device_info },/* Navi10 */
{ 0x731a, _device_info },/* Navi10 */
{ 0x731f, _device_info },/* Navi10 */
+   /* Navi12 */
+   { 0x7360, _device_info },/* Navi12 */
+   { 0x69b0, _device_info },/* Navi12 */
 };
 
 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
-- 
2.7.4

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Re: [PATCH 07/87] drm/amd/display: move bw calc code into helpers

[Michel Dänzer]

On 2019-07-15 11:19 p.m., sunpeng...@amd.com wrote:
> From: Eric Yang 
> 
> [Why]
> For better readability and reusability
> 
> [How]
> Move snippets of BW calculation code into helpers.
> 
> Signed-off-by: Eric Yang 
> Reviewed-by: Fatemeh Darbehani 
> Acked-by: Leo Li 
> ---
>  [...]
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 086d2f3b0db3..e9ccf41e31ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -126,6 +126,7 @@ static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
>   amdgpu_device_get_pcie_replay_count, NULL);
>  
>  static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
> +static void amdgpu_device_parse_faked_did(struct amdgpu_device *adev);

This function isn't defined anywhere, producing a warning:

drivers/gpu/drm//amd/amdgpu/amdgpu_device.c:131:13: warning: 
‘amdgpu_device_parse_faked_did’ declared ‘static’ but never defined 
[-Wunused-function]
 static void amdgpu_device_parse_faked_did(struct amdgpu_device *adev);
 ^


-- 
Earthling Michel Dänzer   |  https://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [PATCH] drm/amdgpu: Prefer pcie_capability_read_word()

[Bjorn Helgaas]

On Wed, Jul 17, 2019 at 9:08 PM Frederick Lawler  wrote:
>
> Commit 8c0d3a02c130 ("PCI: Add accessors for PCI Express Capability")
> added accessors for the PCI Express Capability so that drivers didn't
> need to be aware of differences between v1 and v2 of the PCI
> Express Capability.
>
> Replace pci_read_config_word() and pci_write_config_word() calls with
> pcie_capability_read_word() and pcie_capability_write_word().
>
> Signed-off-by: Frederick Lawler 

> -   pci_read_config_word(adev->pdev, gpu_pos + 
> PCI_EXP_LNKCTL2, );
> +   pcie_capability_read_word(adev->pdev,
> + PCI_EXP_LNKCTL2,
> + );
> tmp16 &= ~((1 << 4) | (7 << 9));
> tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));

Same comments as for radeon.  Looks like a lot of similar code between
radeon and amdgpu.

Re: [PATCH 1/3] drm/amd/powerplay: remove mutex lock for smu_handle_task when smu late init

[Quan, Evan]

please hold on the mutex changes of patch1 and patch3. We need an overall 
thought over the smu mutex machinsim. Let us have some internal discussions 
first.


发件人: amd-gfx  代表 Chengming Gui 

发送时间: Thursday, July 18, 2019 6:02:16 PM
收件人: amd-gfx@lists.freedesktop.org 
抄送: Gui, Jack 
主题: [PATCH 1/3] drm/amd/powerplay: remove mutex lock for smu_handle_task when 
smu late init

remove mutex lock when smu late init to call smu_handle_task

Signed-off-by: Chengming Gui 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 7d1bd09..122985c 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -569,11 +569,9 @@ static int smu_late_init(void *handle)

 if (!smu->pm_enabled)
 return 0;
-   mutex_lock(>mutex);
 smu_handle_task(>smu,
 smu->smu_dpm.dpm_level,
 AMD_PP_TASK_COMPLETE_INIT);
-   mutex_unlock(>mutex);

 return 0;
 }
--
2.7.4

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Re: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

[Quan, Evan]

1. In navi10_force_clk_levels, i think you need to compare the max level user 
requested with the peak limit and set the smaller one.
2. can you help me to understand why the change in apply_clock_rules is needed?


发件人: amd-gfx  代表 Chengming Gui 

发送时间: Thursday, July 18, 2019 6:02:17 PM
收件人: amd-gfx@lists.freedesktop.org 
抄送: Gui, Jack 
主题: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

force different GFX clocks with different SKUs for navi10:
XL  (other rev_id):  1625MHz
XT (F1/C1):  1755MHz
XTX(F0/C0):  1830MHz

Signed-off-by: Chengming Gui 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  2 +
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  2 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 66 +-
 3 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 122985c..693414f 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -664,6 +664,8 @@ static int smu_sw_init(void *handle)
 smu->watermarks_bitmap = 0;
 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+   smu->smu_dpm.default_sclk_limit = 0;
+   smu->smu_dpm.peak_sclk_limit = 0;

 smu->workload_mask = 1 << 
smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 135a323..acb522b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -441,6 +441,8 @@ struct smu_dpm_context {
 void *dpm_context;
 void *golden_dpm_context;
 bool enable_umd_pstate;
+   uint32_t default_sclk_limit;
+   uint32_t peak_sclk_limit;
 enum amd_dpm_forced_level dpm_level;
 enum amd_dpm_forced_level saved_dpm_level;
 enum amd_dpm_forced_level requested_dpm_level;
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e5..b4deb9e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -37,6 +37,15 @@

 #include "asic_reg/mp/mp_11_0_sh_mask.h"

+#define NV_NV10_F0 0xF0
+#define NV_NV10_C0 0xC0
+#define NV_NV10_F1 0xF1
+#define NV_NV10_C1 0xC1
+
+#define NV_NV10_PEAK_SCLK_XTX 1830
+#define NV_NV10_PEAK_SCLK_XT  1755
+#define NV_NV10_PEAK_SCLK_XL  1625
+
 #define FEATURE_MASK(feature) (1ULL << feature)
 #define SMC_DPM_FEATURE ( \
 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
@@ -675,6 +684,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,

 int ret = 0, size = 0;
 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, 
max_freq = 0;
+   struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);

 soft_min_level = mask ? (ffs(mask) - 1) : 0;
 soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -682,6 +692,23 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 switch (clk_type) {
 case SMU_GFXCLK:
 case SMU_SCLK:
+   if (smu_dpm_ctx->peak_sclk_limit) {
+   max_freq = smu_dpm_ctx->peak_sclk_limit;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
+   if (ret)
+   return size;
+   } else {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
+   if (ret)
+   return size;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_max_level, _freq);
+   if (ret)
+   return size;
+   }
+   ret = smu_set_soft_freq_range(smu, clk_type, min_freq, 
max_freq);
+   if (ret)
+   return size;
+   break;
 case SMU_SOCCLK:
 case SMU_MCLK:
 case SMU_UCLK:
@@ -690,11 +717,9 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, 
_freq);
 if (ret)
 return size;
-
 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, 
_freq);
 if (ret)
 return size;
-
 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, 
max_freq);
 if (ret)
 return size;
@@ -838,6 +863,7 @@ static int navi10_unforce_dpm_levels(struct smu_context 
*smu)
 int ret = 0, i = 0;
 uint32_t min_freq, max_freq;
  

RE: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

[Huang, Ray]

> -Original Message-
> From: Wang, Kevin(Yang) 
> Sent: Thursday, July 18, 2019 5:43 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth ; Quan, Evan
> ; Huang, Ray ; Xu, Feifei
> ; Wang, Kevin(Yang) 
> Subject: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format
> for navi10
> 
> v2:
> set average clock value on level 1 when current clock equal min or max clock
> (fine grained dpm support).
> 
> the navi10 gfxclk (sclk) support fine grained DPM, so use level 1 to show
> current dpm freq in sysfs pp_dpm_xxx
> 
> Change-Id: I14daa6e30c52c89795708ec06660862bb4591036
> Signed-off-by: Kevin Wang 

Acked-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 47 +++-
> --
>  1 file changed, 41 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 895a4e592d5a..1f721b85c0f6 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -627,11 +627,26 @@ static int
> navi10_get_current_clk_freq_by_table(struct smu_context *smu,
>   return ret;
>  }
> 
> +static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu,
> +enum smu_clk_type clk_type) {
> + PPTable_t *pptable = smu->smu_table.driver_pptable;
> + DpmDescriptor_t *dpm_desc = NULL;
> + uint32_t clk_index = 0;
> +
> + clk_index = smu_clk_get_index(smu, clk_type);
> + dpm_desc = >DpmDescriptor[clk_index];
> +
> + /* 0 - Fine grained DPM, 1 - Discrete DPM */
> + return dpm_desc->SnapToDiscrete == 0 ? true : false; }
> +
>  static int navi10_print_clk_levels(struct smu_context *smu,
>   enum smu_clk_type clk_type, char *buf)  {
>   int i, size = 0, ret = 0;
>   uint32_t cur_value = 0, value = 0, count = 0;
> + uint32_t freq_values[3] = {0};
> + uint32_t mark_index = 0;
> 
>   switch (clk_type) {
>   case SMU_GFXCLK:
> @@ -644,22 +659,42 @@ static int navi10_print_clk_levels(struct
> smu_context *smu,
>   ret = smu_get_current_clk_freq(smu, clk_type, _value);
>   if (ret)
>   return size;
> +
>   /* 10KHz -> MHz */
>   cur_value = cur_value / 100;
> 
> - size += sprintf(buf, "current clk: %uMhz\n", cur_value);
> -
>   ret = smu_get_dpm_level_count(smu, clk_type, );
>   if (ret)
>   return size;
> 
> - for (i = 0; i < count; i++) {
> - ret = smu_get_dpm_freq_by_index(smu, clk_type, i,
> );
> + if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
> + for (i = 0; i < count; i++) {
> + ret = smu_get_dpm_freq_by_index(smu,
> clk_type, i, );
> + if (ret)
> + return size;
> +
> + size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, value,
> + cur_value == value ? "*" : "");
> + }
> + } else {
> + ret = smu_get_dpm_freq_by_index(smu, clk_type, 0,
> _values[0]);
> + if (ret)
> + return size;
> + ret = smu_get_dpm_freq_by_index(smu, clk_type,
> count - 1,
> +_values[2]);
>   if (ret)
>   return size;
> 
> - size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
> - cur_value == value ? "*" : "");
> + freq_values[1] = cur_value;
> + mark_index = cur_value == freq_values[0] ? 0 :
> +  cur_value == freq_values[2] ? 2 : 1;
> + if (mark_index != 1)
> + freq_values[1] = (freq_values[0] +
> freq_values[2]) / 2;
> +
> + for (i = 0; i < 3; i++) {
> + size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, freq_values[i],
> + i == mark_index ? "*" : "");
> + }
> +
>   }
>   break;
>   default:
> --
> 2.22.0

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Re: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

[Quan, Evan]

reviewed-by: Evan Quan 

获取 Outlook for iOS

发件人: Feng, Kenneth 
发送时间: Thursday, July 18, 2019 5:49:56 PM
收件人: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org 

抄送: Quan, Evan ; Huang, Ray ; Xu, Feifei 

主题: RE: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

Reviewed-by: Kenneth Feng 



-Original Message-
From: Wang, Kevin(Yang)
Sent: Thursday, July 18, 2019 5:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; 
Huang, Ray ; Xu, Feifei ; Wang, 
Kevin(Yang) 
Subject: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

v2:
set average clock value on level 1 when current clock equal min or max clock 
(fine grained dpm support).

the navi10 gfxclk (sclk) support fine grained DPM, so use level 1 to show 
current dpm freq in sysfs pp_dpm_xxx

Change-Id: I14daa6e30c52c89795708ec06660862bb4591036
Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 47 +++---
 1 file changed, 41 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e592d5a..1f721b85c0f6 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -627,11 +627,26 @@ static int navi10_get_current_clk_freq_by_table(struct 
smu_context *smu,
 return ret;
 }

+static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu,
+enum smu_clk_type clk_type) {
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
+   DpmDescriptor_t *dpm_desc = NULL;
+   uint32_t clk_index = 0;
+
+   clk_index = smu_clk_get_index(smu, clk_type);
+   dpm_desc = >DpmDescriptor[clk_index];
+
+   /* 0 - Fine grained DPM, 1 - Discrete DPM */
+   return dpm_desc->SnapToDiscrete == 0 ? true : false; }
+
 static int navi10_print_clk_levels(struct smu_context *smu,
 enum smu_clk_type clk_type, char *buf)  {
 int i, size = 0, ret = 0;
 uint32_t cur_value = 0, value = 0, count = 0;
+   uint32_t freq_values[3] = {0};
+   uint32_t mark_index = 0;

 switch (clk_type) {
 case SMU_GFXCLK:
@@ -644,22 +659,42 @@ static int navi10_print_clk_levels(struct smu_context 
*smu,
 ret = smu_get_current_clk_freq(smu, clk_type, _value);
 if (ret)
 return size;
+
 /* 10KHz -> MHz */
 cur_value = cur_value / 100;

-   size += sprintf(buf, "current clk: %uMhz\n", cur_value);
-
 ret = smu_get_dpm_level_count(smu, clk_type, );
 if (ret)
 return size;

-   for (i = 0; i < count; i++) {
-   ret = smu_get_dpm_freq_by_index(smu, clk_type, i, 
);
+   if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
+   for (i = 0; i < count; i++) {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
i, );
+   if (ret)
+   return size;
+
+   size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, value,
+   cur_value == value ? "*" : "");
+   }
+   } else {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, 
_values[0]);
+   if (ret)
+   return size;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 
1,
+_values[2]);
 if (ret)
 return size;

-   size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
-   cur_value == value ? "*" : "");
+   freq_values[1] = cur_value;
+   mark_index = cur_value == freq_values[0] ? 0 :
+cur_value == freq_values[2] ? 2 : 1;
+   if (mark_index != 1)
+   freq_values[1] = (freq_values[0] + 
freq_values[2]) / 2;
+
+   for (i = 0; i < 3; i++) {
+   size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, freq_values[i],
+   i == mark_index ? "*" : "");
+   }
+
 }
 break;
 default:
--
2.22.0

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[PATCH 1/3] drm/amd/powerplay: remove mutex lock for smu_handle_task when smu late init

[Chengming Gui]

remove mutex lock when smu late init to call smu_handle_task

Signed-off-by: Chengming Gui 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 7d1bd09..122985c 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -569,11 +569,9 @@ static int smu_late_init(void *handle)
 
if (!smu->pm_enabled)
return 0;
-   mutex_lock(>mutex);
smu_handle_task(>smu,
smu->smu_dpm.dpm_level,
AMD_PP_TASK_COMPLETE_INIT);
-   mutex_unlock(>mutex);
 
return 0;
 }
-- 
2.7.4

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[PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

[Chengming Gui]

force different GFX clocks with different SKUs for navi10:
XL  (other rev_id):  1625MHz
XT (F1/C1):  1755MHz
XTX(F0/C0):  1830MHz

Signed-off-by: Chengming Gui 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  2 +
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  2 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 66 +-
 3 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 122985c..693414f 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -664,6 +664,8 @@ static int smu_sw_init(void *handle)
smu->watermarks_bitmap = 0;
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+   smu->smu_dpm.default_sclk_limit = 0;
+   smu->smu_dpm.peak_sclk_limit = 0;
 
smu->workload_mask = 1 << 
smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 135a323..acb522b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -441,6 +441,8 @@ struct smu_dpm_context {
void *dpm_context;
void *golden_dpm_context;
bool enable_umd_pstate;
+   uint32_t default_sclk_limit;
+   uint32_t peak_sclk_limit;
enum amd_dpm_forced_level dpm_level;
enum amd_dpm_forced_level saved_dpm_level;
enum amd_dpm_forced_level requested_dpm_level;
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e5..b4deb9e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -37,6 +37,15 @@
 
 #include "asic_reg/mp/mp_11_0_sh_mask.h"
 
+#define NV_NV10_F0 0xF0
+#define NV_NV10_C0 0xC0
+#define NV_NV10_F1 0xF1
+#define NV_NV10_C1 0xC1
+
+#define NV_NV10_PEAK_SCLK_XTX 1830
+#define NV_NV10_PEAK_SCLK_XT  1755
+#define NV_NV10_PEAK_SCLK_XL  1625
+
 #define FEATURE_MASK(feature) (1ULL << feature)
 #define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
@@ -675,6 +684,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 
int ret = 0, size = 0;
uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq 
= 0;
+   struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -682,6 +692,23 @@ static int navi10_force_clk_levels(struct smu_context *smu,
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
+   if (smu_dpm_ctx->peak_sclk_limit) {
+   max_freq = smu_dpm_ctx->peak_sclk_limit;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
+   if (ret)
+   return size;
+   } else {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
+   if (ret)
+   return size;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_max_level, _freq);
+   if (ret)
+   return size;
+   }
+   ret = smu_set_soft_freq_range(smu, clk_type, min_freq, 
max_freq);
+   if (ret)
+   return size;
+   break;
case SMU_SOCCLK:
case SMU_MCLK:
case SMU_UCLK:
@@ -690,11 +717,9 @@ static int navi10_force_clk_levels(struct smu_context *smu,
ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, 
_freq);
if (ret)
return size;
-
ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, 
_freq);
if (ret)
return size;
-
ret = smu_set_soft_freq_range(smu, clk_type, min_freq, 
max_freq);
if (ret)
return size;
@@ -838,6 +863,7 @@ static int navi10_unforce_dpm_levels(struct smu_context 
*smu)
int ret = 0, i = 0;
uint32_t min_freq, max_freq;
enum smu_clk_type clk_type;
+   struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 
enum smu_clk_type clks[] = {
SMU_GFXCLK,
@@ -851,10 +877,18 @@ static int navi10_unforce_dpm_levels(struct smu_context 
*smu)
if (ret)
return ret;
 
+   if (clk_type == SMU_GFXCLK && smu_dpm_ctx->default_sclk_limit 
!= 0) {
+   max_freq = smu_dpm_ctx->default_sclk_limit;
+   

[PATCH 3/3] drm/amd/powerplay: add mutex lock to protect dpm context resource

[Chengming Gui]

add mutex lock to protect dpm context resource

Signed-off-by: Chengming Gui 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 +++--
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 693414f..ac01960 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -664,6 +664,7 @@ static int smu_sw_init(void *handle)
smu->watermarks_bitmap = 0;
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+   mutex_init(>smu_dpm.mutex);
smu->smu_dpm.default_sclk_limit = 0;
smu->smu_dpm.peak_sclk_limit = 0;
 
@@ -1471,9 +1472,9 @@ enum amd_dpm_forced_level 
smu_get_performance_level(struct smu_context *smu)
if (!smu_dpm_ctx->dpm_context)
return -EINVAL;
 
-   mutex_lock(&(smu->mutex));
+   mutex_lock(&(smu_dpm_ctx->mutex));
level = smu_dpm_ctx->dpm_level;
-   mutex_unlock(&(smu->mutex));
+   mutex_unlock(&(smu_dpm_ctx->mutex));
 
return level;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index acb522b..b6fcad2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -449,6 +449,7 @@ struct smu_dpm_context {
struct smu_power_state *dpm_request_power_state;
struct smu_power_state *dpm_current_power_state;
struct mclock_latency_table *mclk_latency_table;
+   struct mutex mutex;
 };
 
 struct smu_power_gate {
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index b4deb9e..2079097 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -693,7 +693,9 @@ static int navi10_force_clk_levels(struct smu_context *smu,
case SMU_GFXCLK:
case SMU_SCLK:
if (smu_dpm_ctx->peak_sclk_limit) {
+   mutex_lock(_dpm_ctx->mutex);
max_freq = smu_dpm_ctx->peak_sclk_limit;
+   mutex_unlock(_dpm_ctx->mutex);
ret = smu_get_dpm_freq_by_index(smu, clk_type, 
soft_min_level, _freq);
if (ret)
return size;
@@ -878,7 +880,9 @@ static int navi10_unforce_dpm_levels(struct smu_context 
*smu)
return ret;
 
if (clk_type == SMU_GFXCLK && smu_dpm_ctx->default_sclk_limit 
!= 0) {
+   mutex_lock(_dpm_ctx->mutex);
max_freq = smu_dpm_ctx->default_sclk_limit;
+   mutex_unlock(_dpm_ctx->mutex);
ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
 _freq, NULL);
if (ret)
@@ -888,7 +892,9 @@ static int navi10_unforce_dpm_levels(struct smu_context 
*smu)
if (ret)
return ret;
}
+   mutex_lock(_dpm_ctx->mutex);
smu_dpm_ctx->peak_sclk_limit = 0;
+   mutex_unlock(_dpm_ctx->mutex);
 
return ret;
 }
@@ -1571,6 +1577,7 @@ static int navi10_apply_clocks_adjust_rules(struct 
smu_context *smu)
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
struct amdgpu_device *adev = smu->adev;
 
+   mutex_lock(_dpm_ctx->mutex);
if (smu_dpm_ctx->default_sclk_limit == 0) {
ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL,
 _dpm_ctx->default_sclk_limit);
@@ -1588,6 +1595,7 @@ static int navi10_apply_clocks_adjust_rules(struct 
smu_context *smu)
} else if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK 
&& smu_dpm_ctx->peak_sclk_limit != 0) {
smu_dpm_ctx->peak_sclk_limit = 0;
}
+   mutex_unlock(_dpm_ctx->mutex);
 
return 0;
 }
-- 
2.7.4

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RE: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

[Feng, Kenneth]

Reviewed-by: Kenneth Feng 



-Original Message-
From: Wang, Kevin(Yang) 
Sent: Thursday, July 18, 2019 5:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; 
Huang, Ray ; Xu, Feifei ; Wang, 
Kevin(Yang) 
Subject: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

v2:
set average clock value on level 1 when current clock equal min or max clock 
(fine grained dpm support).

the navi10 gfxclk (sclk) support fine grained DPM, so use level 1 to show 
current dpm freq in sysfs pp_dpm_xxx

Change-Id: I14daa6e30c52c89795708ec06660862bb4591036
Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 47 +++---
 1 file changed, 41 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e592d5a..1f721b85c0f6 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -627,11 +627,26 @@ static int navi10_get_current_clk_freq_by_table(struct 
smu_context *smu,
return ret;
 }
 
+static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, 
+enum smu_clk_type clk_type) {
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
+   DpmDescriptor_t *dpm_desc = NULL;
+   uint32_t clk_index = 0;
+
+   clk_index = smu_clk_get_index(smu, clk_type);
+   dpm_desc = >DpmDescriptor[clk_index];
+
+   /* 0 - Fine grained DPM, 1 - Discrete DPM */
+   return dpm_desc->SnapToDiscrete == 0 ? true : false; }
+
 static int navi10_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)  {
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
+   uint32_t freq_values[3] = {0};
+   uint32_t mark_index = 0;
 
switch (clk_type) {
case SMU_GFXCLK:
@@ -644,22 +659,42 @@ static int navi10_print_clk_levels(struct smu_context 
*smu,
ret = smu_get_current_clk_freq(smu, clk_type, _value);
if (ret)
return size;
+
/* 10KHz -> MHz */
cur_value = cur_value / 100;
 
-   size += sprintf(buf, "current clk: %uMhz\n", cur_value);
-
ret = smu_get_dpm_level_count(smu, clk_type, );
if (ret)
return size;
 
-   for (i = 0; i < count; i++) {
-   ret = smu_get_dpm_freq_by_index(smu, clk_type, i, 
);
+   if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
+   for (i = 0; i < count; i++) {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
i, );
+   if (ret)
+   return size;
+
+   size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, value,
+   cur_value == value ? "*" : "");
+   }
+   } else {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, 
_values[0]);
+   if (ret)
+   return size;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 
1, 
+_values[2]);
if (ret)
return size;
 
-   size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
-   cur_value == value ? "*" : "");
+   freq_values[1] = cur_value;
+   mark_index = cur_value == freq_values[0] ? 0 :
+cur_value == freq_values[2] ? 2 : 1;
+   if (mark_index != 1)
+   freq_values[1] = (freq_values[0] + 
freq_values[2]) / 2;
+
+   for (i = 0; i < 3; i++) {
+   size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, freq_values[i],
+   i == mark_index ? "*" : "");
+   }
+
}
break;
default:
--
2.22.0

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[PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

[Wang, Kevin(Yang)]

v2:
set average clock value on level 1 when current clock equal
min or max clock (fine grained dpm support).

the navi10 gfxclk (sclk) support fine grained DPM,
so use level 1 to show current dpm freq in sysfs pp_dpm_xxx

Change-Id: I14daa6e30c52c89795708ec06660862bb4591036
Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 47 +++---
 1 file changed, 41 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e592d5a..1f721b85c0f6 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -627,11 +627,26 @@ static int navi10_get_current_clk_freq_by_table(struct 
smu_context *smu,
return ret;
 }
 
+static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum 
smu_clk_type clk_type)
+{
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
+   DpmDescriptor_t *dpm_desc = NULL;
+   uint32_t clk_index = 0;
+
+   clk_index = smu_clk_get_index(smu, clk_type);
+   dpm_desc = >DpmDescriptor[clk_index];
+
+   /* 0 - Fine grained DPM, 1 - Discrete DPM */
+   return dpm_desc->SnapToDiscrete == 0 ? true : false;
+}
+
 static int navi10_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
 {
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
+   uint32_t freq_values[3] = {0};
+   uint32_t mark_index = 0;
 
switch (clk_type) {
case SMU_GFXCLK:
@@ -644,22 +659,42 @@ static int navi10_print_clk_levels(struct smu_context 
*smu,
ret = smu_get_current_clk_freq(smu, clk_type, _value);
if (ret)
return size;
+
/* 10KHz -> MHz */
cur_value = cur_value / 100;
 
-   size += sprintf(buf, "current clk: %uMhz\n", cur_value);
-
ret = smu_get_dpm_level_count(smu, clk_type, );
if (ret)
return size;
 
-   for (i = 0; i < count; i++) {
-   ret = smu_get_dpm_freq_by_index(smu, clk_type, i, 
);
+   if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
+   for (i = 0; i < count; i++) {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
i, );
+   if (ret)
+   return size;
+
+   size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, value,
+   cur_value == value ? "*" : "");
+   }
+   } else {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, 
_values[0]);
+   if (ret)
+   return size;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 
1, _values[2]);
if (ret)
return size;
 
-   size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
-   cur_value == value ? "*" : "");
+   freq_values[1] = cur_value;
+   mark_index = cur_value == freq_values[0] ? 0 :
+cur_value == freq_values[2] ? 2 : 1;
+   if (mark_index != 1)
+   freq_values[1] = (freq_values[0] + 
freq_values[2]) / 2;
+
+   for (i = 0; i < 3; i++) {
+   size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, freq_values[i],
+   i == mark_index ? "*" : "");
+   }
+
}
break;
default:
-- 
2.22.0

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Re: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[Christian König]

Am 18.07.19 um 10:10 schrieb Cui, Flora:

1. skip test if there's no desired ring
2. clear shader buffer
3. update command buffer for gfx9

Change-Id: I5e4e92842c4fd1088c14dc048bedf4fe84892b36
Signed-off-by: Flora Cui 


Acked-by: Christian König 


---
  tests/amdgpu/basic_tests.c | 36 
  1 file changed, 28 insertions(+), 8 deletions(-)

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 2d47269..8fa7088 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -329,14 +329,15 @@ static const uint32_t preamblecache_gfx9[] = {
0xc0016900, 0x2d5, 0x1, 0xc0016900,  0x2dc, 0x0,
0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 
0x0, 0x0,
0xc0056900, 0x2f9, 0x5, 0x3f80, 0x3f80, 0x3f80, 0x3f80,
-   0xc0026900, 0x311,  0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
+   0xc0036900, 0x311, 0x3, 0, 0x10, 0xc0026900, 0x316, 0x1e, 0x20,
0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0xc0026900, 0x204, 0x9, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0x, 0x,
-   0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
+   0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
+   0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 
0x2243, 0x0,
0xc0017900, 0x248, 0x, 0xc0017900, 0x249, 0x0, 0xc0017900, 
0x24a, 0x0,
0xc0017900, 0x24b, 0x0
@@ -450,7 +451,7 @@ static const uint32_t cached_cmd_gfx9[] = {
0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
0xc0016900, 0x83, 0x, 0xc0026900, 0x8e, 0xf, 0xf,
-   0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x12,
+   0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x1a,
0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
0xc0036900, 0x200, 0x0, 0x1, 0xcc0011,
0xc0026900, 0x292, 0x20, 0x60201b8,
@@ -2094,10 +2095,7 @@ static int amdgpu_dispatch_init(uint32_t *ptr, uint32_t 
ip_type)
ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
ptr[i++] = 0x204;
i += 3;
-   /* clear mmCOMPUTE_RESOURCE_LIMITS */
-   ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
-   ptr[i++] = 0x215;
-   ptr[i++] = 0;
+
/* clear mmCOMPUTE_TMPRING_SIZE */
ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
ptr[i++] = 0x218;
@@ -2184,6 +2182,7 @@ static void 
amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
_shader, _shader,
_address_shader, _shader);
CU_ASSERT_EQUAL(r, 0);
+   memset(ptr_shader, 0, bo_shader_size);
  
  	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);

CU_ASSERT_EQUAL(r, 0);
@@ -2220,6 +2219,11 @@ static void 
amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
ptr_cmd[i++] = 0x;
ptr_cmd[i++] = 0x;
  
+	/* clear mmCOMPUTE_RESOURCE_LIMITS */

+   ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+   ptr_cmd[i++] = 0x215;
+   ptr_cmd[i++] = 0;
+
/* dispatch direct command */
ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
ptr_cmd[i++] = 0x10;
@@ -2321,6 +2325,7 @@ static void 
amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
_shader, _shader,
_address_shader, _shader);
CU_ASSERT_EQUAL(r, 0);
+   memset(ptr_shader, 0, bo_shader_size);
  
  	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );

CU_ASSERT_EQUAL(r, 0);
@@ -2365,6 +2370,11 @@ static void 
amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
ptr_cmd[i++] = 0x400;
ptr_cmd[i++] = 0x74fac;
  
+	/* clear mmCOMPUTE_RESOURCE_LIMITS */

+   ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+   ptr_cmd[i++] = 0x215;
+   ptr_cmd[i++] = 0;
+
/* dispatch direct command */
ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
ptr_cmd[i++] = 0x10;
@@ -2438,6 +2448,8 @@ static void amdgpu_dispatch_test(void)
  
  	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, );

CU_ASSERT_EQUAL(r, 0);
+   if (!info.available_rings)
+   printf("SKIP ... as there's no compute ring\n");
  
  	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {

amdgpu_memset_dispatch_test(device_handle, 
AMDGPU_HW_IP_COMPUTE, ring_id);
@@ -2446,6 +2458,8 @@ static void 

RE: [PATCH libdrm 2/2] tests/amdgpu: add gpu reset test

[Zhang, Hawking]

Series is:

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Cui, Flora
Sent: 2019年7月18日 16:11
To: amd-gfx@lists.freedesktop.org
Cc: Cui, Flora 
Subject: [PATCH libdrm 2/2] tests/amdgpu: add gpu reset test

1. perform gpu reset
2. perform dispatch test to verify gpu reset to a good state

Change-Id: I4bba0d1b829288bba7b6885d7e68c8f69ef8f4b5
Signed-off-by: Flora Cui 
---
 tests/amdgpu/amdgpu_test.c |  5 +
 tests/amdgpu/basic_tests.c | 38 ++
 2 files changed, 43 insertions(+)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 
73403fb..0c9364a 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -472,6 +472,11 @@ static void amdgpu_disable_suites()
if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
if (amdgpu_set_test_active(BASIC_TESTS_STR, "Draw Test", 
CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", 
CU_get_error_msg());
+
+   /* This test was ran on GFX9 only */
+   if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
+   if (amdgpu_set_test_active(BASIC_TESTS_STR, "GPU reset Test", 
CU_FALSE))
+   fprintf(stderr, "test deactivation failed - %s\n", 
+CU_get_error_msg());
 }
 
 /* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 
8fa7088..c04df8b 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -24,6 +24,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #ifdef HAVE_ALLOCA_H
 # include 
 #endif
@@ -51,6 +54,7 @@ static void amdgpu_sync_dependency_test(void);
 static void amdgpu_bo_eviction_test(void);  static void 
amdgpu_dispatch_test(void);  static void amdgpu_draw_test(void);
+static void amdgpu_gpu_reset_test(void);
 
 static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);  
static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); @@ 
-74,6 +78,7 @@ CU_TestInfo basic_tests[] = {
{ "Sync dependency Test",  amdgpu_sync_dependency_test },
{ "Dispatch Test",  amdgpu_dispatch_test },
{ "Draw Test",  amdgpu_draw_test },
+   { "GPU reset Test", amdgpu_gpu_reset_test },
CU_TEST_INFO_NULL,
 };
 #define BUFFER_SIZE (8 * 1024)
@@ -3131,3 +3136,36 @@ static void amdgpu_draw_test(void)
amdgpu_memcpy_draw_test(device_handle, ring_id);
}
 }
+
+static void amdgpu_gpu_reset_test(void) {
+   int r;
+   char debugfs_path[256], tmp[10];
+   int fd;
+   struct stat sbuf;
+   amdgpu_context_handle context_handle;
+   uint32_t hang_state, hangs;
+
+   r = amdgpu_cs_ctx_create(device_handle, _handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = fstat(drm_amdgpu[0], );
+   CU_ASSERT_EQUAL(r, 0);
+
+   sprintf(debugfs_path, "/sys/kernel/debug/dri/%d/amdgpu_gpu_recover", 
minor(sbuf.st_rdev));
+   fd = open(debugfs_path, O_RDONLY);
+   CU_ASSERT(fd >= 0);
+
+   r = read(fd, tmp, sizeof(tmp)/sizeof(char));
+   CU_ASSERT(r > 0);
+
+   r = amdgpu_cs_query_reset_state(context_handle, _state, );
+   CU_ASSERT_EQUAL(r, 0);
+   CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET);
+
+   close(fd);
+   r = amdgpu_cs_ctx_free(context_handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   amdgpu_dispatch_test();
+}
--
2.7.4

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RE: [PATCH 4/4] drm/amdgpu: drop ras self test

[Xu, Feifei]

Series is Reviewed-by: Feifei Xu 

-Original Message-
From: amd-gfx  On Behalf Of Hawking Zhang
Sent: Thursday, July 18, 2019 4:20 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking 
Subject: [PATCH 4/4] drm/amdgpu: drop ras self test

this function is not needed any more. error injection is the only way to 
validate ras but it can't be executed in amdgpu_ras_init, where gpu is even not 
initialized

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 5ee73f5..4a50bef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -66,11 +66,6 @@ static int amdgpu_ras_reserve_vram(struct amdgpu_device 
*adev,  static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
struct amdgpu_bo **bo_ptr);
 
-static void amdgpu_ras_self_test(struct amdgpu_device *adev) -{
-   /* TODO */
-}
-
 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
 {
@@ -1521,8 +1516,6 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
if (amdgpu_ras_fs_init(adev))
goto fs_out;
 
-   amdgpu_ras_self_test(adev);
-
DRM_INFO("RAS INFO: ras initialized successfully, "
"hardware ability[%x] ras_mask[%x]\n",
con->hw_supported, con->supported);
--
2.7.4

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Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends

[Christian König]

Am 17.07.19 um 22:31 schrieb Kuehling, Felix:

On 2019-07-17 5:10, Christian König wrote:

Am 16.07.19 um 18:40 schrieb Kuehling, Felix:

On 2019-07-16 9:36 a.m., Christian König wrote:

Am 02.07.19 um 21:35 schrieb Kuehling, Felix:

This assumes that page tables are resident when a page fault is
handled.

Yeah, that is correct. I also haven't completely figured out how we
can prevent the VM from being destroyed while handling the fault.

There are other cases I had in mind: Page tables can be evicted. For KFD
processes which can be preempted with CWSR, it's possible that a wave
that caused a page fault is preempted due to a page table eviction. That
means, by the time the page fault is handled, the page table is no
longer resident.

This is a corner case we can handle later on. As long as the VM is
still alive just allocating page tables again should be sufficient for
this.

Do you mean, instead of migrating page tables back, throwing them away
and allocating a new one?


Yes, exactly that's the idea here.


Also, this may be a corner case. But I feel you're limiting yourself to
a small range of current use cases. I'm not convinced that the design
you're building here will scale to future use cases for HMM updating
page tables for random virtual addresses. I'm looking for a general
solution that will work for those future use cases. Otherwise we'll end
up having to rewrite this page-table-update-in-fault-handler code from
scratch in a month or two.


Well actually I'm keeping mostly HMM in mind. Filling page tables on 
demand is just a step in between.


I also want to support a use case where per-VM-BOs are swapped in and 
out on demand, but I think that we will just use that for testing.



I mean it's perfectly possible that the process is killed while faults
are still in the pipeline.


I think it's possible that a page table gets evicted while a page
fault
is pending. Maybe not with graphics, but definitely with compute where
waves can be preempted while waiting for a page fault. In that case
the
direct access would break.

Even with graphics I think it's still possible that new page tables
need
to be allocated to handle a page fault. When that happens, you need to
wait for fences to let new page tables be validated and initialized.

Yeah, the problem here is that when you wait on fences which in turn
depend on your submission your end up in a deadlock.


I think this implies that you have amdgpu_cs fences attached to page
tables. I believe this is the fundamental issue that needs to be fixed.

We still need this cause even with page faults the root PD can't be
evicted.

What we can probably do is to split up the PDs/PTs into the root PD
and everything else.

Yeah, the root PD always exists as long as the VM exists. Everything
else can be created/destroyed/moved dynamically.


Yeah, exactly. The question is how do we want to keep the root PD in place?

We could still add the fence or we could pin it permanently.


If you want to manage page tables in page fault interrupt handlers, you
can't have command submission fences attached to your page tables. You
can allow page tables to be evicted while the command submission is in
progress. A page fault will fault it back in if it's needed. If you
eliminate command submission fences on the page tables, you remove the
potential for deadlocks.

No, there is still a huge potential for deadlocks here.

Additional to the root PDs you can have a MM submission which needs to
wait for a compute submission to be finished.

I assume by MM you mean "memory manger", not "multi-media". [SNIP]


Sorry I meant "multi-media", so just snipped your response.

What I want to say here is that I don't believe we can keep user CS 
fences our of memory management.


See there can be submission from engines which don't support or don't 
want to enabled recoverable page faults which depend on submissions 
which do use recoverable page faults.


I mean it was your requirement that we have a mix of page fault and 
pre-filled page tables in the same process.



If you then make your new allocation depend on the MM submission to be
finished you have a classical circle dependency and a deadlock at hand.

I don't see it. Allocate page table, wait for fence associated with that
page table initialization, update PTEs. At no point do we depend on the
user CS being stalled by the page fault. There is not user submission on
the paging ring. Anything that has been scheduled on the paging ring has
its dependencies satisfied.


Allocation is the main problem here. We need to make sure that we never 
ever depend on user CS when making memory allocation in the page fault 
handler.



We may need separate scheduler entities
(queues) for regular MM submissions that can depend on user fences and
VM submissions that must not.


Yeah, thought about that as well but even then you need a way to note 
that you want to use this separate entity.



The only way around that is to allocate the new page 

Re: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

[Wang, Kevin(Yang)]

Hi Evan,


1. the other clock type also will check dpm fine grained support.

2. i will change code to v2 to avoid below case

0: 300M *
1: 300M
 2: 1800M


Best Regards,

Kevin


From: Quan, Evan
Sent: Thursday, July 18, 2019 4:16:22 PM
To: Wang, Kevin(Yang); amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth; Huang, Ray; Xu, Feifei
Subject: RE: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for 
navi10

1. Please commonilzie a new API e.g. smu_is_fine_grained_dpm which can be 
shared for other clocks in future.
2. if the current clock is same as min or max, the output will be a little 
strange
0: 300M *
1: 300M
 2: 1800M
Please check how raven handle this situation.

Regards,
Evan
> -Original Message-
> From: Wang, Kevin(Yang) 
> Sent: Thursday, July 18, 2019 4:02 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth ; Quan, Evan
> ; Huang, Ray ; Xu, Feifei
> ; Wang, Kevin(Yang) 
> Subject: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for
> navi10
>
> the navi10 gfxclk (sclk) support fine grained DPM,
> so use level 1 to show current dpm freq in sysfs pp_dpm_xxx
>
> Change-Id: Idae2424f8cc91fe94cebe7f3103e112b4f912fbc
> Signed-off-by: Kevin Wang 
> ---
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 41 +--
> ---
>  1 file changed, 33 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 895a4e592d5a..ef60b92fef6c 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -632,6 +632,10 @@ static int navi10_print_clk_levels(struct smu_context
> *smu,
>  {
>int i, size = 0, ret = 0;
>uint32_t cur_value = 0, value = 0, count = 0;
> + uint32_t freq_values[3] = {0};
> + uint32_t clk_index = 0, mark_index = 0;
> + PPTable_t *pptable = smu->smu_table.driver_pptable;
> + DpmDescriptor_t *dpm_desc = NULL;
>
>switch (clk_type) {
>case SMU_GFXCLK:
> @@ -641,25 +645,46 @@ static int navi10_print_clk_levels(struct
> smu_context *smu,
>case SMU_UCLK:
>case SMU_FCLK:
>case SMU_DCEFCLK:
> + clk_index = smu_clk_get_index(smu, clk_type);
> + dpm_desc = >DpmDescriptor[clk_index];
> +
>ret = smu_get_current_clk_freq(smu, clk_type, _value);
>if (ret)
>return size;
> - /* 10KHz -> MHz */
> - cur_value = cur_value / 100;
> -
> - size += sprintf(buf, "current clk: %uMhz\n", cur_value);
>
>ret = smu_get_dpm_level_count(smu, clk_type, );
>if (ret)
>return size;
>
> - for (i = 0; i < count; i++) {
> - ret = smu_get_dpm_freq_by_index(smu, clk_type, i,
> );
> + /* 0 - Fine grained DPM, 1 - Discrete DPM */
> + if (dpm_desc->SnapToDiscrete == 1) {
> + /* 10KHz -> MHz */
> + cur_value = cur_value / 100;
> + for (i = 0; i < count; i++) {
> + ret = smu_get_dpm_freq_by_index(smu,
> clk_type, i, );
> + if (ret)
> + return size;
> +
> + size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, value,
> + cur_value == value ? "*" : "");
> + }
> + } else {
> + ret = smu_get_dpm_freq_by_index(smu, clk_type, 0,
> _values[0]);
> + if (ret)
> + return size;
> + ret = smu_get_dpm_freq_by_index(smu, clk_type,
> count - 1, _values[2]);
>if (ret)
>return size;
>
> - size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
> - cur_value == value ? "*" : "");
> + freq_values[1] = cur_value / 100;
> + mark_index = cur_value == freq_values[0] ? 0 :
> +  cur_value == freq_values[2] ? 2 : 1;
> +
> + for (i = 0; i < 3; i++) {
> + size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, freq_values[i],
> + i == mark_index ? "*" : "");
> + }
> +
>}
>break;
>default:
> --
> 2.22.0

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RE: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

[Feng, Kenneth]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Wang, Kevin(Yang) 
Sent: Thursday, July 18, 2019 4:02 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; 
Huang, Ray ; Xu, Feifei ; Wang, 
Kevin(Yang) 
Subject: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

the navi10 gfxclk (sclk) support fine grained DPM, so use level 1 to show 
current dpm freq in sysfs pp_dpm_xxx

Change-Id: Idae2424f8cc91fe94cebe7f3103e112b4f912fbc
Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 41 +-
 1 file changed, 33 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e592d5a..ef60b92fef6c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -632,6 +632,10 @@ static int navi10_print_clk_levels(struct smu_context 
*smu,  {
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
+   uint32_t freq_values[3] = {0};
+   uint32_t clk_index = 0, mark_index = 0;
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
+   DpmDescriptor_t *dpm_desc = NULL;
 
switch (clk_type) {
case SMU_GFXCLK:
@@ -641,25 +645,46 @@ static int navi10_print_clk_levels(struct smu_context 
*smu,
case SMU_UCLK:
case SMU_FCLK:
case SMU_DCEFCLK:
+   clk_index = smu_clk_get_index(smu, clk_type);
+   dpm_desc = >DpmDescriptor[clk_index];
+
ret = smu_get_current_clk_freq(smu, clk_type, _value);
if (ret)
return size;
-   /* 10KHz -> MHz */
-   cur_value = cur_value / 100;
-
-   size += sprintf(buf, "current clk: %uMhz\n", cur_value);
 
ret = smu_get_dpm_level_count(smu, clk_type, );
if (ret)
return size;
 
-   for (i = 0; i < count; i++) {
-   ret = smu_get_dpm_freq_by_index(smu, clk_type, i, 
);
+   /* 0 - Fine grained DPM, 1 - Discrete DPM */
+   if (dpm_desc->SnapToDiscrete == 1) {
+   /* 10KHz -> MHz */
+   cur_value = cur_value / 100;
+   for (i = 0; i < count; i++) {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
i, );
+   if (ret)
+   return size;
+
+   size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, value,
+   cur_value == value ? "*" : "");
+   }
+   } else {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, 
_values[0]);
+   if (ret)
+   return size;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 
1, 
+_values[2]);
if (ret)
return size;
 
-   size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
-   cur_value == value ? "*" : "");
+   freq_values[1] = cur_value / 100;
+   mark_index = cur_value == freq_values[0] ? 0 :
+cur_value == freq_values[2] ? 2 : 1;
+
+   for (i = 0; i < 3; i++) {
+   size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, freq_values[i],
+   i == mark_index ? "*" : "");
+   }
+
}
break;
default:
--
2.22.0

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[PATCH 2/4] drm/amdgpu: disable GFX RAS by default

[Hawking Zhang]

GFX RAS has not been stablized yet. disable GFX ras until
it is fully funcitonal.

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 63e2449..9856a59 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -154,7 +154,7 @@ struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
 };
 int amdgpu_ras_enable = -1;
-uint amdgpu_ras_mask = 0x;
+uint amdgpu_ras_mask = 0xfffb;
 
 /**
  * DOC: vramlimit (int)
-- 
2.7.4

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[PATCH 1/4] drm/amdgpu: do not create ras debugfs/sysfs node for ASICs that don't have ras ability

[Hawking Zhang]

driver shouldn't init any ras debugfs/sysfs node for ASICs that don't have ras
hardware ability

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index c20d03b..bda9025 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1496,6 +1496,12 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
 
amdgpu_ras_check_supported(adev, >hw_supported,
>supported);
+   if (!con->hw_supported) {
+   amdgpu_ras_set_context(adev, NULL);
+   kfree(con);
+   return 0;
+   }
+
con->features = 0;
INIT_LIST_HEAD(>head);
/* Might need get this flag from vbios. */
-- 
2.7.4

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[PATCH 3/4] drm/amdgpu: only allow error injection to UMC IP block

[Hawking Zhang]

error injection to other IP blocks (except UMC) will be enabled
until RAS feature stablize on those IP blocks

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index bda9025..5ee73f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -627,6 +627,12 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
if (!obj)
return -EINVAL;
 
+   if (block_info.block_id != TA_RAS_BLOCK__UMC) {
+   DRM_INFO("%s error injection is not supported yet\n",
+ras_block_str(info->head.block));
+   return -EINVAL;
+   }
+
ret = psp_ras_trigger_error(>psp, _info);
if (ret)
DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
-- 
2.7.4

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[PATCH 4/4] drm/amdgpu: drop ras self test

[Hawking Zhang]

this function is not needed any more. error injection is
the only way to validate ras but it can't be executed in
amdgpu_ras_init, where gpu is even not initialized

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 5ee73f5..4a50bef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -66,11 +66,6 @@ static int amdgpu_ras_reserve_vram(struct amdgpu_device 
*adev,
 static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
struct amdgpu_bo **bo_ptr);
 
-static void amdgpu_ras_self_test(struct amdgpu_device *adev)
-{
-   /* TODO */
-}
-
 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
 {
@@ -1521,8 +1516,6 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
if (amdgpu_ras_fs_init(adev))
goto fs_out;
 
-   amdgpu_ras_self_test(adev);
-
DRM_INFO("RAS INFO: ras initialized successfully, "
"hardware ability[%x] ras_mask[%x]\n",
con->hw_supported, con->supported);
-- 
2.7.4

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RE: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

[Quan, Evan]

1. Please commonilzie a new API e.g. smu_is_fine_grained_dpm which can be 
shared for other clocks in future.
2. if the current clock is same as min or max, the output will be a little 
strange
0: 300M *
1: 300M
 2: 1800M
Please check how raven handle this situation.

Regards,
Evan
> -Original Message-
> From: Wang, Kevin(Yang) 
> Sent: Thursday, July 18, 2019 4:02 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth ; Quan, Evan
> ; Huang, Ray ; Xu, Feifei
> ; Wang, Kevin(Yang) 
> Subject: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for
> navi10
> 
> the navi10 gfxclk (sclk) support fine grained DPM,
> so use level 1 to show current dpm freq in sysfs pp_dpm_xxx
> 
> Change-Id: Idae2424f8cc91fe94cebe7f3103e112b4f912fbc
> Signed-off-by: Kevin Wang 
> ---
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 41 +--
> ---
>  1 file changed, 33 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 895a4e592d5a..ef60b92fef6c 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -632,6 +632,10 @@ static int navi10_print_clk_levels(struct smu_context
> *smu,
>  {
>   int i, size = 0, ret = 0;
>   uint32_t cur_value = 0, value = 0, count = 0;
> + uint32_t freq_values[3] = {0};
> + uint32_t clk_index = 0, mark_index = 0;
> + PPTable_t *pptable = smu->smu_table.driver_pptable;
> + DpmDescriptor_t *dpm_desc = NULL;
> 
>   switch (clk_type) {
>   case SMU_GFXCLK:
> @@ -641,25 +645,46 @@ static int navi10_print_clk_levels(struct
> smu_context *smu,
>   case SMU_UCLK:
>   case SMU_FCLK:
>   case SMU_DCEFCLK:
> + clk_index = smu_clk_get_index(smu, clk_type);
> + dpm_desc = >DpmDescriptor[clk_index];
> +
>   ret = smu_get_current_clk_freq(smu, clk_type, _value);
>   if (ret)
>   return size;
> - /* 10KHz -> MHz */
> - cur_value = cur_value / 100;
> -
> - size += sprintf(buf, "current clk: %uMhz\n", cur_value);
> 
>   ret = smu_get_dpm_level_count(smu, clk_type, );
>   if (ret)
>   return size;
> 
> - for (i = 0; i < count; i++) {
> - ret = smu_get_dpm_freq_by_index(smu, clk_type, i,
> );
> + /* 0 - Fine grained DPM, 1 - Discrete DPM */
> + if (dpm_desc->SnapToDiscrete == 1) {
> + /* 10KHz -> MHz */
> + cur_value = cur_value / 100;
> + for (i = 0; i < count; i++) {
> + ret = smu_get_dpm_freq_by_index(smu,
> clk_type, i, );
> + if (ret)
> + return size;
> +
> + size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, value,
> + cur_value == value ? "*" : "");
> + }
> + } else {
> + ret = smu_get_dpm_freq_by_index(smu, clk_type, 0,
> _values[0]);
> + if (ret)
> + return size;
> + ret = smu_get_dpm_freq_by_index(smu, clk_type,
> count - 1, _values[2]);
>   if (ret)
>   return size;
> 
> - size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
> - cur_value == value ? "*" : "");
> + freq_values[1] = cur_value / 100;
> + mark_index = cur_value == freq_values[0] ? 0 :
> +  cur_value == freq_values[2] ? 2 : 1;
> +
> + for (i = 0; i < 3; i++) {
> + size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, freq_values[i],
> + i == mark_index ? "*" : "");
> + }
> +
>   }
>   break;
>   default:
> --
> 2.22.0

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Re: [PATCH v2] drm/amdgpu: Default disable GDS for compute VMIDs

[Christian König]

Am 17.07.19 um 22:09 schrieb Kuehling, Felix:

On 2019-07-17 14:23, Greathouse, Joseph wrote:

The GDS and GWS blocks default to allowing all VMIDs to
access all entries. Graphics VMIDs can handle setting
these limits when the driver launches work. However,
compute workloads under HWS control don't go through the
kernel driver. Instead, HWS firmware should set these
limits when a process is put into a VMID slot.

Disable access to these devices by default by turning off
all mask bits (for OA) and setting BASE=SIZE=0 (for GDS
and GWS) for all compute VMIDs. If a process wants to use
these resources, they can request this from the HWS
firmware (when such capabilities are enabled). HWS will
then handle setting the base and limit for the process when
it is assigned to a VMID.

This will also prevent user kernels from getting 'stuck' in
GWS by accident if they write GWS-using code but HWS
firmware is not set up to handle GWS reset. Until HWS is
enabled to handle GWS properly, all GWS accesses will
MEM_VIOL fault the kernel.

v2: Move initialization outside of SRBM mutex

Change-Id: I8edcea9d0b14d16a7444bcf9fbf9451aef8b707d
Signed-off-by: Joseph Greathouse 

Reviewed-by: Felix Kuehling 


Might be a good idea to do this for all VMIDs during initialization and 
not just for the ones used for compute.


But anyway patch is Reviewed-by: Christian König .





---
   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 +
   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 9 +
   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 9 +
   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 9 +
   4 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 618291df659b..73dcb632a3ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1516,6 +1516,15 @@ static void gfx_v10_0_init_compute_vmid(struct 
amdgpu_device *adev)
}
nv_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
+
+   /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+  acccess. These should be enabled by FW for target VMIDs. */
+   for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+   WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+   WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+   WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+   WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+   }
   }
   
   static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index e1e2a44ee13c..3f98624772a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1877,6 +1877,15 @@ static void gfx_v7_0_init_compute_vmid(struct 
amdgpu_device *adev)
}
cik_srbm_select(adev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
+
+   /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+  acccess. These should be enabled by FW for target VMIDs. */
+   for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+   WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
+   WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
+   WREG32(amdgpu_gds_reg_offset[i].gws, 0);
+   WREG32(amdgpu_gds_reg_offset[i].oa, 0);
+   }
   }
   
   static void gfx_v7_0_config_init(struct amdgpu_device *adev)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 8c590a554675..e4028d54f8f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3702,6 +3702,15 @@ static void gfx_v8_0_init_compute_vmid(struct 
amdgpu_device *adev)
}
vi_srbm_select(adev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
+
+   /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+  acccess. These should be enabled by FW for target VMIDs. */
+   for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+   WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
+   WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
+   WREG32(amdgpu_gds_reg_offset[i].gws, 0);
+   WREG32(amdgpu_gds_reg_offset[i].oa, 0);
+   }
   }
   
   static void gfx_v8_0_config_init(struct amdgpu_device *adev)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5af60e1c735a..259a35395fec 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2025,6 +2025,15 @@ static void gfx_v9_0_init_compute_vmid(struct 
amdgpu_device *adev)
}
soc15_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
+
+   /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+  acccess. These should be enabled by FW for target 

[PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

[Cui, Flora]

1. skip test if there's no desired ring
2. clear shader buffer
3. update command buffer for gfx9

Change-Id: I5e4e92842c4fd1088c14dc048bedf4fe84892b36
Signed-off-by: Flora Cui 
---
 tests/amdgpu/basic_tests.c | 36 
 1 file changed, 28 insertions(+), 8 deletions(-)

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 2d47269..8fa7088 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -329,14 +329,15 @@ static const uint32_t preamblecache_gfx9[] = {
0xc0016900, 0x2d5, 0x1, 0xc0016900,  0x2dc, 0x0,
0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 
0x0, 0x0,
0xc0056900, 0x2f9, 0x5, 0x3f80, 0x3f80, 0x3f80, 0x3f80,
-   0xc0026900, 0x311,  0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
+   0xc0036900, 0x311, 0x3, 0, 0x10, 0xc0026900, 0x316, 0x1e, 0x20,
0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0xc0026900, 0x204, 0x9, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0x, 0x,
-   0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
+   0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
+   0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 
0x2243, 0x0,
0xc0017900, 0x248, 0x, 0xc0017900, 0x249, 0x0, 0xc0017900, 
0x24a, 0x0,
0xc0017900, 0x24b, 0x0
@@ -450,7 +451,7 @@ static const uint32_t cached_cmd_gfx9[] = {
0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
0xc0016900, 0x83, 0x, 0xc0026900, 0x8e, 0xf, 0xf,
-   0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x12,
+   0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x1a,
0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
0xc0036900, 0x200, 0x0, 0x1, 0xcc0011,
0xc0026900, 0x292, 0x20, 0x60201b8,
@@ -2094,10 +2095,7 @@ static int amdgpu_dispatch_init(uint32_t *ptr, uint32_t 
ip_type)
ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
ptr[i++] = 0x204;
i += 3;
-   /* clear mmCOMPUTE_RESOURCE_LIMITS */
-   ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
-   ptr[i++] = 0x215;
-   ptr[i++] = 0;
+
/* clear mmCOMPUTE_TMPRING_SIZE */
ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
ptr[i++] = 0x218;
@@ -2184,6 +2182,7 @@ static void 
amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
_shader, _shader,
_address_shader, _shader);
CU_ASSERT_EQUAL(r, 0);
+   memset(ptr_shader, 0, bo_shader_size);
 
r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);
CU_ASSERT_EQUAL(r, 0);
@@ -2220,6 +2219,11 @@ static void 
amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
ptr_cmd[i++] = 0x;
ptr_cmd[i++] = 0x;
 
+   /* clear mmCOMPUTE_RESOURCE_LIMITS */
+   ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+   ptr_cmd[i++] = 0x215;
+   ptr_cmd[i++] = 0;
+
/* dispatch direct command */
ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
ptr_cmd[i++] = 0x10;
@@ -2321,6 +2325,7 @@ static void 
amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
_shader, _shader,
_address_shader, _shader);
CU_ASSERT_EQUAL(r, 0);
+   memset(ptr_shader, 0, bo_shader_size);
 
r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );
CU_ASSERT_EQUAL(r, 0);
@@ -2365,6 +2370,11 @@ static void 
amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
ptr_cmd[i++] = 0x400;
ptr_cmd[i++] = 0x74fac;
 
+   /* clear mmCOMPUTE_RESOURCE_LIMITS */
+   ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+   ptr_cmd[i++] = 0x215;
+   ptr_cmd[i++] = 0;
+
/* dispatch direct command */
ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
ptr_cmd[i++] = 0x10;
@@ -2438,6 +2448,8 @@ static void amdgpu_dispatch_test(void)
 
r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, 
);
CU_ASSERT_EQUAL(r, 0);
+   if (!info.available_rings)
+   printf("SKIP ... as there's no compute ring\n");
 
for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
amdgpu_memset_dispatch_test(device_handle, 
AMDGPU_HW_IP_COMPUTE, ring_id);
@@ -2446,6 +2458,8 @@ static void amdgpu_dispatch_test(void)
 
r = 

[PATCH libdrm 2/2] tests/amdgpu: add gpu reset test

[Cui, Flora]

1. perform gpu reset
2. perform dispatch test to verify gpu reset to a good state

Change-Id: I4bba0d1b829288bba7b6885d7e68c8f69ef8f4b5
Signed-off-by: Flora Cui 
---
 tests/amdgpu/amdgpu_test.c |  5 +
 tests/amdgpu/basic_tests.c | 38 ++
 2 files changed, 43 insertions(+)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 73403fb..0c9364a 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -472,6 +472,11 @@ static void amdgpu_disable_suites()
if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
if (amdgpu_set_test_active(BASIC_TESTS_STR, "Draw Test", 
CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", 
CU_get_error_msg());
+
+   /* This test was ran on GFX9 only */
+   if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
+   if (amdgpu_set_test_active(BASIC_TESTS_STR, "GPU reset Test", 
CU_FALSE))
+   fprintf(stderr, "test deactivation failed - %s\n", 
CU_get_error_msg());
 }
 
 /* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 8fa7088..c04df8b 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -24,6 +24,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #ifdef HAVE_ALLOCA_H
 # include 
 #endif
@@ -51,6 +54,7 @@ static void amdgpu_sync_dependency_test(void);
 static void amdgpu_bo_eviction_test(void);
 static void amdgpu_dispatch_test(void);
 static void amdgpu_draw_test(void);
+static void amdgpu_gpu_reset_test(void);
 
 static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
 static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -74,6 +78,7 @@ CU_TestInfo basic_tests[] = {
{ "Sync dependency Test",  amdgpu_sync_dependency_test },
{ "Dispatch Test",  amdgpu_dispatch_test },
{ "Draw Test",  amdgpu_draw_test },
+   { "GPU reset Test", amdgpu_gpu_reset_test },
CU_TEST_INFO_NULL,
 };
 #define BUFFER_SIZE (8 * 1024)
@@ -3131,3 +3136,36 @@ static void amdgpu_draw_test(void)
amdgpu_memcpy_draw_test(device_handle, ring_id);
}
 }
+
+static void amdgpu_gpu_reset_test(void)
+{
+   int r;
+   char debugfs_path[256], tmp[10];
+   int fd;
+   struct stat sbuf;
+   amdgpu_context_handle context_handle;
+   uint32_t hang_state, hangs;
+
+   r = amdgpu_cs_ctx_create(device_handle, _handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   r = fstat(drm_amdgpu[0], );
+   CU_ASSERT_EQUAL(r, 0);
+
+   sprintf(debugfs_path, "/sys/kernel/debug/dri/%d/amdgpu_gpu_recover", 
minor(sbuf.st_rdev));
+   fd = open(debugfs_path, O_RDONLY);
+   CU_ASSERT(fd >= 0);
+
+   r = read(fd, tmp, sizeof(tmp)/sizeof(char));
+   CU_ASSERT(r > 0);
+
+   r = amdgpu_cs_query_reset_state(context_handle, _state, );
+   CU_ASSERT_EQUAL(r, 0);
+   CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET);
+
+   close(fd);
+   r = amdgpu_cs_ctx_free(context_handle);
+   CU_ASSERT_EQUAL(r, 0);
+
+   amdgpu_dispatch_test();
+}
-- 
2.7.4

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[PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

[Wang, Kevin(Yang)]

the navi10 gfxclk (sclk) support fine grained DPM,
so use level 1 to show current dpm freq in sysfs pp_dpm_xxx

Change-Id: Idae2424f8cc91fe94cebe7f3103e112b4f912fbc
Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 41 +-
 1 file changed, 33 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e592d5a..ef60b92fef6c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -632,6 +632,10 @@ static int navi10_print_clk_levels(struct smu_context *smu,
 {
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
+   uint32_t freq_values[3] = {0};
+   uint32_t clk_index = 0, mark_index = 0;
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
+   DpmDescriptor_t *dpm_desc = NULL;
 
switch (clk_type) {
case SMU_GFXCLK:
@@ -641,25 +645,46 @@ static int navi10_print_clk_levels(struct smu_context 
*smu,
case SMU_UCLK:
case SMU_FCLK:
case SMU_DCEFCLK:
+   clk_index = smu_clk_get_index(smu, clk_type);
+   dpm_desc = >DpmDescriptor[clk_index];
+
ret = smu_get_current_clk_freq(smu, clk_type, _value);
if (ret)
return size;
-   /* 10KHz -> MHz */
-   cur_value = cur_value / 100;
-
-   size += sprintf(buf, "current clk: %uMhz\n", cur_value);
 
ret = smu_get_dpm_level_count(smu, clk_type, );
if (ret)
return size;
 
-   for (i = 0; i < count; i++) {
-   ret = smu_get_dpm_freq_by_index(smu, clk_type, i, 
);
+   /* 0 - Fine grained DPM, 1 - Discrete DPM */
+   if (dpm_desc->SnapToDiscrete == 1) {
+   /* 10KHz -> MHz */
+   cur_value = cur_value / 100;
+   for (i = 0; i < count; i++) {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 
i, );
+   if (ret)
+   return size;
+
+   size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, value,
+   cur_value == value ? "*" : "");
+   }
+   } else {
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, 
_values[0]);
+   if (ret)
+   return size;
+   ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 
1, _values[2]);
if (ret)
return size;
 
-   size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
-   cur_value == value ? "*" : "");
+   freq_values[1] = cur_value / 100;
+   mark_index = cur_value == freq_values[0] ? 0 :
+cur_value == freq_values[2] ? 2 : 1;
+
+   for (i = 0; i < 3; i++) {
+   size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, freq_values[i],
+   i == mark_index ? "*" : "");
+   }
+
}
break;
default:
-- 
2.22.0

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