Re: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

[Wang, Kevin(Yang)]

I don't recommend it.

each asic maybe has different thermal policy, you can custom this value in asic 
file  .
and your patch define a new array in smu_v11_0.h header file.
it's never done that before, and the code looks is not clearly.

Best Regards,
Kevin

From: Feng, Kenneth 
Sent: Tuesday, August 20, 2019 10:51 AM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org 

Cc: Wang, Kevin(Yang) 
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings


Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>





From: Quan, Evan
Sent: Tuesday, August 20, 2019 10:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Wang, Kevin(Yang) 

Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings



Ping..



From: Quan, Evan
Sent: Monday, August 19, 2019 1:27 PM
To: Feng, Kenneth mailto:kenneth.f...@amd.com>>; Wang, 
Kevin(Yang) mailto:kevin1.w...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings



Yes, the lowest settings for thermal controller is 0.



Regards

Evan

From: Feng, Kenneth mailto:kenneth.f...@amd.com>>
Sent: Monday, August 19, 2019 1:12 PM
To: Quan, Evan mailto:evan.q...@amd.com>>; Wang, Kevin(Yang) 
mailto:kevin1.w...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings



Hi Evan,

So due to the below code, we don’t get a chance to set -273.15, right?

+   low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
+   range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
+   range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);



From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Quan, 
Evan
Sent: Monday, August 19, 2019 10:16 AM
To: Wang, Kevin(Yang) mailto:kevin1.w...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings



[CAUTION: External Email]

Comment inline



From: Wang, Kevin(Yang) mailto:kevin1.w...@amd.com>>
Sent: Friday, August 16, 2019 7:04 PM
To: Quan, Evan mailto:evan.q...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings



Hi Evan,



the temperature min value should be 0, not -273 on smu11.

you can refrence window driver code or register spec.

output_ptr->operating_temperature_min_Limit = 0;
output_ptr->operating_temperature_max_Limit = 
ppt_info->software_shutdown_temp;

[Quan, Evan] There was a discussion over the min value(0 or -273.15) and we 
decided to use the later considering the OD case.

All the existing and coming ASICs should  follow this design.

and in smu11, the thermal control has a 8bit register to set min and max value, 
and the unit is temperature.

[Quan, Evan] That is still honored, no violation here.

so there is something wrong with this patch.



Best Regards,
Kevin



From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Evan Quan mailto:evan.q...@amd.com>>
Sent: Friday, August 16, 2019 5:31 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Quan, Evan mailto:evan.q...@amd.com>>
Subject: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings



Problems with current settings:
1. The min value was overrided to 0 on Vega20 & Navi10. While
   the expected should be -273.15 C.
2. The thermal min/max threshold was output in wrong unit on
   Navi10 & Arcturus. As TEMP_RANGE_MIN/MAX is already in
   millicelsius. And "*1000" in smu_v11_0_start_thermal_control
   makes the output wrongly.

Change-Id: I2f1866edd1baf264f521310343f492eaede26c33
Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 10 
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  6 +++
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c|  5 +-
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 51 +++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 20 +---
 5 files changed, 38 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 4060607fbb35..1a1f64a9e1e0 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -880,23 +880,14 @@ static int arcturus_force_clk_levels(struct smu_context 
*smu,
 return ret;
 }

-static const struct smu_temperature_range arcturus_thermal_policy[] =
-{
-   {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
-   { 12, 12, 12, 12, 12, 12, 

RE: [PATCH] drm/amd/powerplay: remove duplicate macro smu_get_uclk_dpm_states in amdgpu_smu.h

[Huang, Ray]

> -Original Message-
> From: Wang, Kevin(Yang) 
> Sent: Tuesday, August 20, 2019 1:36 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Wang, Kevin(Yang)
> 
> Subject: [PATCH] drm/amd/powerplay: remove duplicate macro
> smu_get_uclk_dpm_states in amdgpu_smu.h
> 
> remove duplicate macro smu_get_uclk_dpm_states in amdgpu_smu.h
> 
> "
>  #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
>  ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs-
> >get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
>  #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
>  ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs-
> >get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
>  #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
>  ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs-
> >get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
> "
> 
> Signed-off-by: Kevin Wang 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index ca9b9ec39de8..fc59d9686e61 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -730,8 +730,6 @@ struct smu_funcs
>   ((smu)->funcs->register_irq_handler ? (smu)->funcs-
> >register_irq_handler(smu) : 0)
>  #define smu_set_azalia_d3_pme(smu) \
>   ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs-
> >set_azalia_d3_pme((smu)) : 0)
> -#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
> - ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs-
> >get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
>  #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
>   ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs-
> >get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
>  #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
> --
> 2.22.0

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[PATCH] drm/amd/powerplay: remove duplicate macro smu_get_uclk_dpm_states in amdgpu_smu.h

[Wang, Kevin(Yang)]

remove duplicate macro smu_get_uclk_dpm_states in amdgpu_smu.h

"
 #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
 ((smu)->ppt_funcs->get_uclk_dpm_states ? 
(smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
 #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
 ((smu)->funcs->get_max_sustainable_clocks_by_dc ? 
(smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
 #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
 ((smu)->ppt_funcs->get_uclk_dpm_states ? 
(smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
"

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ca9b9ec39de8..fc59d9686e61 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -730,8 +730,6 @@ struct smu_funcs
((smu)->funcs->register_irq_handler ? 
(smu)->funcs->register_irq_handler(smu) : 0)
 #define smu_set_azalia_d3_pme(smu) \
((smu)->funcs->set_azalia_d3_pme ? 
(smu)->funcs->set_azalia_d3_pme((smu)) : 0)
-#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
-   ((smu)->ppt_funcs->get_uclk_dpm_states ? 
(smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
 #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
((smu)->funcs->get_max_sustainable_clocks_by_dc ? 
(smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
 #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
-- 
2.22.0

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Re: [PATCH] drm/amd/powerplay: correct typo

[Wang, Kevin(Yang)]

Reviewed-by: Kevin Wang 

Best Regards,
Kevin


From: amd-gfx  on behalf of Evan Quan 

Sent: Tuesday, August 20, 2019 12:23 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Quan, Evan 
Subject: [PATCH] drm/amd/powerplay: correct typo

"COMPUTE" was wrongly spelled as "CUSTOM".

Change-Id: I11693c0e55c2ce5c889d57bb7411fdf9795a8739
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index b3d4cdc387c8..6f9dab1db2c2 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -181,7 +181,7 @@ static struct smu_11_0_cmn2aisc_mapping 
arcturus_workload_map[PP_SMC_POWER_PROFI
 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,   
WORKLOAD_PPLIB_DEFAULT_BIT),
 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,  
WORKLOAD_PPLIB_POWER_SAVING_BIT),
 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,
WORKLOAD_PPLIB_VIDEO_BIT),
-   WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,  
WORKLOAD_PPLIB_CUSTOM_BIT),
+   WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,  
WORKLOAD_PPLIB_COMPUTE_BIT),
 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,   
WORKLOAD_PPLIB_CUSTOM_BIT),
 };

--
2.22.0

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[PATCH] drm/amd/powerplay: correct typo

[Evan Quan]

"COMPUTE" was wrongly spelled as "CUSTOM".

Change-Id: I11693c0e55c2ce5c889d57bb7411fdf9795a8739
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index b3d4cdc387c8..6f9dab1db2c2 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -181,7 +181,7 @@ static struct smu_11_0_cmn2aisc_mapping 
arcturus_workload_map[PP_SMC_POWER_PROFI
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,   
WORKLOAD_PPLIB_DEFAULT_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,  
WORKLOAD_PPLIB_POWER_SAVING_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,
WORKLOAD_PPLIB_VIDEO_BIT),
-   WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,  
WORKLOAD_PPLIB_CUSTOM_BIT),
+   WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,  
WORKLOAD_PPLIB_COMPUTE_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,   
WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
-- 
2.22.0

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RE: [PATCH] drm/amdgpu: correct ras error count type

[Zhou1, Tao]

Consider amdgpu_ras_error_query < 0 and !con are almost impossible, the patch 
is:

Reviewed-by: Tao Zhou 

> -Original Message-
> From: amd-gfx  On Behalf Of
> Guchun Chen
> Sent: 2019年8月20日 10:25
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Li, Dennis ; Pan, Xinhui
> ; Zhou1, Tao 
> Cc: Chen, Guchun 
> Subject: [PATCH] drm/amdgpu: correct ras error count type
> 
> Use unsigned long type for the same ras count variable.
> This will avoid overflow on 64 bit system.
> 
> Change-Id: I011406d81bad69a65433b63960e1691c4959bbc5
> Signed-off-by: Guchun Chen 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 +-
>  4 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index 89c26bb0f05c..da337a2bab65 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -352,7 +352,7 @@ static int amdgpu_ctx_query2(struct amdgpu_device
> *adev,  {
>   struct amdgpu_ctx *ctx;
>   struct amdgpu_ctx_mgr *mgr;
> - uint32_t ras_counter;
> + unsigned long ras_counter;
> 
>   if (!fpriv)
>   return -EINVAL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> index 5f1b54c9bcdb..da808633732b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> @@ -49,8 +49,8 @@ struct amdgpu_ctx {
>   enum drm_sched_priority override_priority;
>   struct mutexlock;
>   atomic_tguilty;
> - uint32_tras_counter_ce;
> - uint32_tras_counter_ue;
> + unsigned long   ras_counter_ce;
> + unsigned long   ras_counter_ue;
>  };
> 
>  struct amdgpu_ctx_mgr {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index 50c13b02d234..df4b9ae39c5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -686,7 +686,7 @@ int amdgpu_ras_error_cure(struct amdgpu_device
> *adev,  }
> 
>  /* get the total error counts on all IPs */ -int
> amdgpu_ras_query_error_count(struct amdgpu_device *adev,
> +unsigned long amdgpu_ras_query_error_count(struct amdgpu_device
> *adev,
>   bool is_ce)
>  {
>   struct amdgpu_ras *con = amdgpu_ras_get_context(adev); @@ -
> 694,7 +694,7 @@ int amdgpu_ras_query_error_count(struct amdgpu_device
> *adev,
>   struct ras_err_data data = {0, 0};
> 
>   if (!con)
> - return -EINVAL;
> + return 0;
> 
>   list_for_each_entry(obj, >head, node) {
>   struct ras_query_if info = {
> @@ -702,7 +702,7 @@ int amdgpu_ras_query_error_count(struct
> amdgpu_device *adev,
>   };
> 
>   if (amdgpu_ras_error_query(adev, ))
> - return -EINVAL;
> + return 0;
> 
>   data.ce_count += info.ce_count;
>   data.ue_count += info.ue_count;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> index 2765f2dbb1e6..02a51e3dfa14 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> @@ -484,7 +484,7 @@ int amdgpu_ras_request_reset_on_boot(struct
> amdgpu_device *adev,  void amdgpu_ras_resume(struct amdgpu_device
> *adev);  void amdgpu_ras_suspend(struct amdgpu_device *adev);
> 
> -int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
> +unsigned long amdgpu_ras_query_error_count(struct amdgpu_device
> *adev,
>   bool is_ce);
> 
>  /* error handling functions */
> --
> 2.17.1
> 
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RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

[Feng, Kenneth]

Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>


From: Quan, Evan
Sent: Tuesday, August 20, 2019 10:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Wang, Kevin(Yang) 

Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

Ping..

From: Quan, Evan
Sent: Monday, August 19, 2019 1:27 PM
To: Feng, Kenneth mailto:kenneth.f...@amd.com>>; Wang, 
Kevin(Yang) mailto:kevin1.w...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

Yes, the lowest settings for thermal controller is 0.

Regards
Evan
From: Feng, Kenneth mailto:kenneth.f...@amd.com>>
Sent: Monday, August 19, 2019 1:12 PM
To: Quan, Evan mailto:evan.q...@amd.com>>; Wang, Kevin(Yang) 
mailto:kevin1.w...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

Hi Evan,
So due to the below code, we don't get a chance to set -273.15, right?
+   low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
+   range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
+   range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);

From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Quan, 
Evan
Sent: Monday, August 19, 2019 10:16 AM
To: Wang, Kevin(Yang) mailto:kevin1.w...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

[CAUTION: External Email]
Comment inline

From: Wang, Kevin(Yang) mailto:kevin1.w...@amd.com>>
Sent: Friday, August 16, 2019 7:04 PM
To: Quan, Evan mailto:evan.q...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

Hi Evan,

the temperature min value should be 0, not -273 on smu11.
you can refrence window driver code or register spec.
output_ptr->operating_temperature_min_Limit = 0;
output_ptr->operating_temperature_max_Limit = 
ppt_info->software_shutdown_temp;
[Quan, Evan] There was a discussion over the min value(0 or -273.15) and we 
decided to use the later considering the OD case.
All the existing and coming ASICs should  follow this design.
and in smu11, the thermal control has a 8bit register to set min and max value, 
and the unit is temperature.
[Quan, Evan] That is still honored, no violation here.
so there is something wrong with this patch.

Best Regards,
Kevin

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Evan Quan mailto:evan.q...@amd.com>>
Sent: Friday, August 16, 2019 5:31 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Quan, Evan mailto:evan.q...@amd.com>>
Subject: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

Problems with current settings:
1. The min value was overrided to 0 on Vega20 & Navi10. While
   the expected should be -273.15 C.
2. The thermal min/max threshold was output in wrong unit on
   Navi10 & Arcturus. As TEMP_RANGE_MIN/MAX is already in
   millicelsius. And "*1000" in smu_v11_0_start_thermal_control
   makes the output wrongly.

Change-Id: I2f1866edd1baf264f521310343f492eaede26c33
Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 10 
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  6 +++
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c|  5 +-
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 51 +++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 20 +---
 5 files changed, 38 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 4060607fbb35..1a1f64a9e1e0 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -880,23 +880,14 @@ static int arcturus_force_clk_levels(struct smu_context 
*smu,
 return ret;
 }

-static const struct smu_temperature_range arcturus_thermal_policy[] =
-{
-   {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
-   { 12, 12, 12, 12, 12, 12, 12, 12, 
12},
-};
-
 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 struct smu_temperature_range 
*range)
 {
-
 PPTable_t *pptable = smu->smu_table.driver_pptable;

 if (!range)
 return -EINVAL;

-   memcpy(range, _thermal_policy[0], sizeof(struct 
smu_temperature_range));
-
 range->max = pptable->TedgeLimit *
 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 range->edge_emergency_max = 

Re: [PATCH] drm/amd/powerplay: add smu_smc_read_sensor support for arcturus

[Wang, Kevin(Yang)]

From: Alex Deucher 
Sent: Monday, August 19, 2019 11:33 PM
To: Wang, Kevin(Yang) 
Cc: amd-gfx@lists.freedesktop.org ; Feng, 
Kenneth ; Quan, Evan ; Huang, Ray 

Subject: Re: [PATCH] drm/amd/powerplay: add smu_smc_read_sensor support for 
arcturus

On Fri, Aug 16, 2019 at 3:22 AM Wang, Kevin(Yang)  wrote:
>
> the bellow patch refine the sensor read sequence,
> but missed to add arcuturs support. (arcuturs_ppt.c)
>
> drm/amd/powerplay: change smu_read_sensor sequence in smu
>
> Signed-off-by: Kevin Wang 
> ---
>  drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index fcf623cf5d2c..850b2a1ef329 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -1012,6 +1012,9 @@ static int arcturus_read_sensor(struct smu_context *smu,
> PPTable_t *pptable = table_context->driver_pptable;
> int ret = 0;
>
> +   if(!data || !size)

Please add a space between if the if and the (.  E.g.,
if (!data || !size)

Alex

[kevin]:
thanks, i will correct it.

> +   return -EINVAL;
> +
> switch (sensor) {
> case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
> *(uint32_t *)data = pptable->FanMaximumRpm;
> @@ -1036,7 +1039,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
> *size = 4;
> break;
> default:
> -   return -EINVAL;
> +   ret = smu_smc_read_sensor(smu, sensor, data, size);
> }
>
> return ret;
> --
> 2.22.0
>
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

[Wang, Kevin(Yang)]

Reviewed-by: Kevin Wang 

Best Regards,
Kevin

From: Quan, Evan 
Sent: Tuesday, August 20, 2019 10:09 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Wang, Kevin(Yang) 
Subject: RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value


Ping..



From: Quan, Evan
Sent: Friday, August 16, 2019 4:00 PM
To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value



Since smu_get_atom_data_table() was already used in 
smu_v11_0_get_vbios_bootup_values(). We should get all our needed information 
at once.

Also, what smu_get_atom_data_table() does is to get the data table from vbios. 
It’s a time and resource cost job.

I do not think it’s a good idea to call it again just to get some information 
we should already know.



Regards,

Evan

From: Wang, Kevin(Yang) mailto:kevin1.w...@amd.com>>
Sent: Friday, August 16, 2019 3:10 PM
To: Quan, Evan mailto:evan.q...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value



i think we can use a function to retrieve this information without storing it 
separately.

likes:  ret = smu_get_atom_data_table(smu, index, , , ,
  (uint8_t **));

because these information is a generic information from 
atom_common_table_header.

and other function don't care it except in smu_v11_0_get_clk_info_from_vbios.



Best Regards,
Kevin



From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Evan Quan mailto:evan.q...@amd.com>>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Quan, Evan mailto:evan.q...@amd.com>>
Subject: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value



This is available with firmwareinfo table v3.2 or later.

Change-Id: I223edf3c616b9e3e2527c752214fef5ab53d1cea
Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 21 +++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ca9b9ec39de8..2c16eb412954 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -222,6 +222,9 @@ struct smu_bios_boot_up_values
 uint16_tvdd_gfx;
 uint8_t cooling_id;
 uint32_tpp_table_id;
+   uint32_tformat_revision;
+   uint32_tcontent_revision;
+   uint32_tfclk;
 };

 enum smu_table_id
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4a51de4ff162..df7b65360ac7 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -568,6 +568,9 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context 
*smu)
 smu->smu_table.boot_values.pp_table_id = 
v_3_3->pplib_pptable_id;
 }

+   smu->smu_table.boot_values.format_revision = header->format_revision;
+   smu->smu_table.boot_values.content_revision = header->content_revision;
+
 return 0;
 }

@@ -647,6 +650,24 @@ static int smu_v11_0_get_clk_info_from_vbios(struct 
smu_context *smu)
 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 
*)
 smu->smu_table.boot_values.dclk = 
le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 1;

+   if ((smu->smu_table.boot_values.format_revision == 3) &&
+   (smu->smu_table.boot_values.content_revision >= 2)) {
+   memset(, 0, sizeof(input));
+   input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
+   input.syspll_id = SMU11_SYSPLL1_2_ID;
+   input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+   index = 
get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+   getsmuclockinfo);
+
+   ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, 
index,
+   (uint32_t *));
+   if (ret)
+   return -EINVAL;
+
+   output = (struct atom_get_smu_clock_info_output_parameters_v3_1 
*)
+   smu->smu_table.boot_values.fclk = 
le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 1;
+   }
+
 return 0;
 }

--
2.22.0

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[PATCH] drm/amdgpu: correct ras error count type

[Guchun Chen]

Use unsigned long type for the same ras count variable.
This will avoid overflow on 64 bit system.

Change-Id: I011406d81bad69a65433b63960e1691c4959bbc5
Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 89c26bb0f05c..da337a2bab65 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -352,7 +352,7 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
 {
struct amdgpu_ctx *ctx;
struct amdgpu_ctx_mgr *mgr;
-   uint32_t ras_counter;
+   unsigned long ras_counter;
 
if (!fpriv)
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index 5f1b54c9bcdb..da808633732b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -49,8 +49,8 @@ struct amdgpu_ctx {
enum drm_sched_priority override_priority;
struct mutexlock;
atomic_tguilty;
-   uint32_tras_counter_ce;
-   uint32_tras_counter_ue;
+   unsigned long   ras_counter_ce;
+   unsigned long   ras_counter_ue;
 };
 
 struct amdgpu_ctx_mgr {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 50c13b02d234..df4b9ae39c5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -686,7 +686,7 @@ int amdgpu_ras_error_cure(struct amdgpu_device *adev,
 }
 
 /* get the total error counts on all IPs */
-int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
bool is_ce)
 {
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
@@ -694,7 +694,7 @@ int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
struct ras_err_data data = {0, 0};
 
if (!con)
-   return -EINVAL;
+   return 0;
 
list_for_each_entry(obj, >head, node) {
struct ras_query_if info = {
@@ -702,7 +702,7 @@ int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
};
 
if (amdgpu_ras_error_query(adev, ))
-   return -EINVAL;
+   return 0;
 
data.ce_count += info.ce_count;
data.ue_count += info.ue_count;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 2765f2dbb1e6..02a51e3dfa14 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -484,7 +484,7 @@ int amdgpu_ras_request_reset_on_boot(struct amdgpu_device 
*adev,
 void amdgpu_ras_resume(struct amdgpu_device *adev);
 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 
-int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
bool is_ce);
 
 /* error handling functions */
-- 
2.17.1

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RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

[Quan, Evan]

Ping..

From: Quan, Evan
Sent: Monday, August 19, 2019 1:27 PM
To: Feng, Kenneth ; Wang, Kevin(Yang) 
; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

Yes, the lowest settings for thermal controller is 0.

Regards
Evan
From: Feng, Kenneth mailto:kenneth.f...@amd.com>>
Sent: Monday, August 19, 2019 1:12 PM
To: Quan, Evan mailto:evan.q...@amd.com>>; Wang, Kevin(Yang) 
mailto:kevin1.w...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

Hi Evan,
So due to the below code, we don't get a chance to set -273.15, right?
+   low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
+   range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
+   range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);

From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Quan, 
Evan
Sent: Monday, August 19, 2019 10:16 AM
To: Wang, Kevin(Yang) mailto:kevin1.w...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

[CAUTION: External Email]
Comment inline

From: Wang, Kevin(Yang) mailto:kevin1.w...@amd.com>>
Sent: Friday, August 16, 2019 7:04 PM
To: Quan, Evan mailto:evan.q...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

Hi Evan,

the temperature min value should be 0, not -273 on smu11.
you can refrence window driver code or register spec.
output_ptr->operating_temperature_min_Limit = 0;
output_ptr->operating_temperature_max_Limit = 
ppt_info->software_shutdown_temp;
[Quan, Evan] There was a discussion over the min value(0 or -273.15) and we 
decided to use the later considering the OD case.
All the existing and coming ASICs should  follow this design.
and in smu11, the thermal control has a 8bit register to set min and max value, 
and the unit is temperature.
[Quan, Evan] That is still honored, no violation here.
so there is something wrong with this patch.

Best Regards,
Kevin

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Evan Quan mailto:evan.q...@amd.com>>
Sent: Friday, August 16, 2019 5:31 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Quan, Evan mailto:evan.q...@amd.com>>
Subject: [PATCH] drm/amd/powerplay: correct SW smu11 thermal range settings

Problems with current settings:
1. The min value was overrided to 0 on Vega20 & Navi10. While
   the expected should be -273.15 C.
2. The thermal min/max threshold was output in wrong unit on
   Navi10 & Arcturus. As TEMP_RANGE_MIN/MAX is already in
   millicelsius. And "*1000" in smu_v11_0_start_thermal_control
   makes the output wrongly.

Change-Id: I2f1866edd1baf264f521310343f492eaede26c33
Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 10 
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  6 +++
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c|  5 +-
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 51 +++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 20 +---
 5 files changed, 38 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 4060607fbb35..1a1f64a9e1e0 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -880,23 +880,14 @@ static int arcturus_force_clk_levels(struct smu_context 
*smu,
 return ret;
 }

-static const struct smu_temperature_range arcturus_thermal_policy[] =
-{
-   {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
-   { 12, 12, 12, 12, 12, 12, 12, 12, 
12},
-};
-
 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 struct smu_temperature_range 
*range)
 {
-
 PPTable_t *pptable = smu->smu_table.driver_pptable;

 if (!range)
 return -EINVAL;

-   memcpy(range, _thermal_policy[0], sizeof(struct 
smu_temperature_range));
-
 range->max = pptable->TedgeLimit *
 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
@@ -910,7 +901,6 @@ static int arcturus_get_thermal_temperature_range(struct 
smu_context *smu,
 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;

-
 return 0;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 

RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

[Quan, Evan]

Ping..

From: Quan, Evan
Sent: Friday, August 16, 2019 4:00 PM
To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

Since smu_get_atom_data_table() was already used in 
smu_v11_0_get_vbios_bootup_values(). We should get all our needed information 
at once.
Also, what smu_get_atom_data_table() does is to get the data table from vbios. 
It's a time and resource cost job.
I do not think it's a good idea to call it again just to get some information 
we should already know.

Regards,
Evan
From: Wang, Kevin(Yang) mailto:kevin1.w...@amd.com>>
Sent: Friday, August 16, 2019 3:10 PM
To: Quan, Evan mailto:evan.q...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

i think we can use a function to retrieve this information without storing it 
separately.
likes:  ret = smu_get_atom_data_table(smu, index, , , ,
  (uint8_t **));
because these information is a generic information from 
atom_common_table_header.
and other function don't care it except in smu_v11_0_get_clk_info_from_vbios.

Best Regards,
Kevin

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Evan Quan mailto:evan.q...@amd.com>>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Quan, Evan mailto:evan.q...@amd.com>>
Subject: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

This is available with firmwareinfo table v3.2 or later.

Change-Id: I223edf3c616b9e3e2527c752214fef5ab53d1cea
Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 21 +++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ca9b9ec39de8..2c16eb412954 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -222,6 +222,9 @@ struct smu_bios_boot_up_values
 uint16_tvdd_gfx;
 uint8_t cooling_id;
 uint32_tpp_table_id;
+   uint32_tformat_revision;
+   uint32_tcontent_revision;
+   uint32_tfclk;
 };

 enum smu_table_id
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4a51de4ff162..df7b65360ac7 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -568,6 +568,9 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context 
*smu)
 smu->smu_table.boot_values.pp_table_id = 
v_3_3->pplib_pptable_id;
 }

+   smu->smu_table.boot_values.format_revision = header->format_revision;
+   smu->smu_table.boot_values.content_revision = header->content_revision;
+
 return 0;
 }

@@ -647,6 +650,24 @@ static int smu_v11_0_get_clk_info_from_vbios(struct 
smu_context *smu)
 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 
*)
 smu->smu_table.boot_values.dclk = 
le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 1;

+   if ((smu->smu_table.boot_values.format_revision == 3) &&
+   (smu->smu_table.boot_values.content_revision >= 2)) {
+   memset(, 0, sizeof(input));
+   input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
+   input.syspll_id = SMU11_SYSPLL1_2_ID;
+   input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+   index = 
get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+   getsmuclockinfo);
+
+   ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, 
index,
+   (uint32_t *));
+   if (ret)
+   return -EINVAL;
+
+   output = (struct atom_get_smu_clock_info_output_parameters_v3_1 
*)
+   smu->smu_table.boot_values.fclk = 
le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 1;
+   }
+
 return 0;
 }

--
2.22.0

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RE: [PATCH] drm/amd/powerplay: fix variable type errors in smu_v11_0_setup_pptable

[Quan, Evan]

Please add the followings to the description part. With that added, the patch 
is Reviewed-by: Evan Quan 
"
This fixes the following static checker warning.
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:390 
smu_v11_0_setup_pptable()
warn: passing casted pointer '' to 'smu_get_atom_data_table()' 32 
vs 16.
"

> -Original Message-
> From: amd-gfx  On Behalf Of
> Wang, Kevin(Yang)
> Sent: Monday, August 19, 2019 11:47 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wang, Kevin(Yang) ;
> dan.carpen...@oracle.com
> Subject: [PATCH] drm/amd/powerplay: fix variable type errors in
> smu_v11_0_setup_pptable
> 
> fix size type errors, from uint32_t to uint16_t.
> it will cause only initializes the highest 16 bits in
> smu_get_atom_data_table function.
> 
> Signed-off-by: Kevin Wang 
> Reported-by: Dan Carpenter 
> ---
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index b69632fe856b..e9a022447ac1 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -368,6 +368,7 @@ static int smu_v11_0_setup_pptable(struct
> smu_context *smu)
>   const struct smc_firmware_header_v1_0 *hdr;
>   int ret, index;
>   uint32_t size;
> + uint16_t atom_table_size;
>   uint8_t frev, crev;
>   void *table;
>   uint16_t version_major, version_minor;
> @@ -395,10 +396,11 @@ static int smu_v11_0_setup_pptable(struct
> smu_context *smu)
>   index =
> get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
>   powerplayinfo);
> 
> - ret = smu_get_atom_data_table(smu, index, (uint16_t
> *), , ,
> + ret = smu_get_atom_data_table(smu, index,
> _table_size, , ,
> (uint8_t **));
>   if (ret)
>   return ret;
> + size = atom_table_size;
>   }
> 
>   if (!smu->smu_table.power_play_table)
> --
> 2.22.0
> 
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Re: linux-next: Tree for Aug 19 (amdgpu)

[Stephen Rothwell]

Hi all,

On Mon, 19 Aug 2019 18:34:41 -0700 Randy Dunlap  wrote:
>
> On 8/19/19 2:18 AM, Stephen Rothwell wrote:
> > Hi all,
> > 
> > Changes since 20190816:
> >   
> 
> on x86_64:
> 
> ../drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c: In function ‘amdgpu_exit’:
> ../drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:1471:2: error: implicit 
> declaration of function ‘mmu_notifier_synchronize’; did you mean 
> ‘__sync_synchronize’? [-Werror=implicit-function-declaration]
>   mmu_notifier_synchronize();
>   ^~~~
>   __sync_synchronize
> 
> 
> Full randconfig file is attached.

Caused by commit

  6832c9dc8358 ("hmm: use mmu_notifier_get/put for 'struct hmm'")

from the hmm tree.

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c need to include linux/mmu_notifier.h
-- 
Cheers,
Stephen Rothwell


pgpXlVOoZhM7h.pgp
Description: OpenPGP digital signature

Re: [PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors

[Francis, David]

>> Whenever a connector on an MST network is attached, detached, or
>> undergoes a modeset, the DSC configs for each stream on that
>> topology will be recalculated. This can change their required
>> bandwidth, requiring a full reprogramming, as though a modeset
>> was performed, even if that stream did not change timing.
>>
>> Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
>> for each crtc that shares a MST topology with that stream and
>> supports DSC, add that crtc (and all affected connectors and
>> planes) to the atomic state and set mode_changed on its state
>>
>> Cc: Leo Li 
>> Cc: Nicholas Kazlauskas 
>> Signed-off-by: David Francis 
>> ---
>>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 +++
>>   1 file changed, 80 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 145fd73025dc..8d5357aec5e8 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -6475,7 +6475,78 @@ static int do_aquire_global_lock(struct drm_device 
>> *dev,
>>
>>return ret < 0 ? ret : 0;
>>   }
>> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>> +static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, 
>> struct drm_crtc *crtc)
>> +{
>> + struct drm_connector *connector;
>> + struct drm_connector_state *conn_state;
>> + struct drm_connector_list_iter conn_iter;
>> + struct drm_crtc_state *new_crtc_state;
>> + struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
>> + int i, j, ret;
>> + struct drm_crtc *crtcs_affected[MAX_PIPES] = { 0 }; > +
>> + for_each_new_connector_in_state(state, connector, conn_state, i) {
>> + if (conn_state->crtc != crtc)
>> + continue;
>> +
>> + aconnector = to_amdgpu_dm_connector(connector);
>> + if (!aconnector->port)
>> + aconnector = NULL;
>> + else
>> + break;
>> + }
>> +
>> + if (!aconnector)
>> + return 0;
>> +
>> + i = 0;
>> + drm_connector_list_iter_begin(state->dev, _iter);
>
>I don't like that we're grabbing the global connector lock every single
>time any CRTC undergoes a modeset even for ASICs that don't support DSC.
>
>We do lock everything below in atomic check anyway for FULL updates but
>I'd like to avoid adding more code that does this if possible. Maybe a
>check at the start that only does this if the ASIC has DSC support would
>be OK.
>

Will do

>> + drm_for_each_connector_iter(connector, _iter) {
>> + if (!connector->state || !connector->state->crtc)
>> + continue;
>> +
>> + aconnector_to_add = to_amdgpu_dm_connector(connector);
>> + if (!aconnector_to_add->port)
>> + continue;
>> +
>> + if (aconnector_to_add->port->mgr != aconnector->port->mgr)
>> + continue;
>> +
>> + if (!aconnector_to_add->dc_sink)
>> + continue;
>> +
>> + if 
>> (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
>> + continue;
>>
>> + if (i >= MAX_PIPES)
>> + continue;
>> +
>> + crtcs_affected[i] = connector->state->crtc;
>
>Drop this crtcs_affected array and just perform the logic below right
>here. We don't really need two loops here, redundant calls to
>drm_atomic_get_crtc_state and the other helpers are fine.
>

Unfortunately, calling drm_atomic_get_crtc_state inside
drm_for_each_connector_iter causes a lockdep warning

>> + i++;
>> + }
>> + drm_connector_list_iter_end(_iter);
>> +
>> + for (j = 0; j < i; j++) {
>> + new_crtc_state = drm_atomic_get_crtc_state(state, 
>> crtcs_affected[j]);
>> + if (IS_ERR(new_crtc_state))
>> + return PTR_ERR(new_crtc_state);
>> +
>> + new_crtc_state->mode_changed = true;
>> +
>> + ret = drm_atomic_add_affected_connectors(state, 
>> crtcs_affected[j]);
>> + if (ret)
>> + return ret;
>> +
>> + ret = drm_atomic_add_affected_planes(state, crtcs_affected[j]);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +
>> +}
>> +#endif
>>   static void get_freesync_config_for_crtc(
>>struct dm_crtc_state *new_crtc_state,
>>struct dm_connector_state *new_con_state)
>> @@ -7178,6 +7249,15 @@ static int amdgpu_dm_atomic_check(struct drm_device 
>> *dev,
>>goto fail;
>>}
>>
>> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>> + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 
>> new_crtc_state, i) {
>> + if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
>> + ret = 

Re: [PATCH 07/14] drm/amd/display: Initialize DSC PPS variables to 0

[Kazlauskas, Nicholas]

On 8/19/19 11:50 AM, David Francis wrote:
> For DSC MST, sometimes monitors would break out
> in full-screen static. The issue traced back to the
> PPS generation code, where these variables were being used
> uninitialized and were picking up garbage.
> 
> memset to 0 to avoid this
> 
> Signed-off-by: David Francis 

Patches 1-5 and 7 are:

Reviewed-by: Nicholas Kazlauskas 

> ---
>   drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
>   drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c   | 3 +++
>   2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> index 35c5467e60e8..619ac48edd05 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> @@ -491,6 +491,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool 
> enable)
>   struct dsc_config dsc_cfg;
>   uint8_t dsc_packed_pps[128];
>   
> + memset(_cfg, 0, sizeof(dsc_cfg));
> + memset(dsc_packed_pps, 0, 128);
> +
>   /* Enable DSC hw block */
>   dsc_cfg.pic_width = stream->timing.h_addressable + 
> stream->timing.h_border_left + stream->timing.h_border_right;
>   dsc_cfg.pic_height = stream->timing.v_addressable + 
> stream->timing.v_border_top + stream->timing.v_border_bottom;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
> index 379c9e4ac63b..16debe6d89f2 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
> @@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct 
> display_stream_compressor *dsc, const str
>   struct dsc_reg_values dsc_reg_vals;
>   struct dsc_optc_config dsc_optc_cfg;
>   
> + memset(_reg_vals, 0, sizeof(dsc_reg_vals));
> + memset(_optc_cfg, 0, sizeof(dsc_optc_cfg));
> +
>   DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
>   dsc_config_log(dsc, dsc_cfg);
>   DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
> 

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Re: [PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot distribution

[Francis, David]

On 8/19/19 11:50 AM, David Francis wrote:
>> We were using drm helpers to convert a timing into its
>> bandwidth, its bandwidth into pbn, and its pbn into timeslots
>>
>> These helpers
>> -Did not take DSC timings into account
>> -Used the link rate and lane count of the link's aux device,
>>   which are not the same as the link's current cap
>> -Did not take FEC into account (FEC reduces the PBN per timeslot)
>>
>> Use the DC helpers (dc_bandwidth_in_kbps_from_timing,
>> dc_link_bandwidth_kbps) instead
>>
>> Cc: Jerry Zuo 
>> Signed-off-by: David Francis 
>
>Wouldn't this be a good candidate for shared DRM helpers or to modify
>the existing ones to support this usecase?
>
>Seems like this would be shared across drivers.
>
>Nicholas Kazlauskas
>

These functions use information which is not stored in drm structs but tracked 
in
a driver-specific way
 - Whether or not FEC is enabled
 - Whether or not DSC is enabled, and with what config
 - The current link setting
This could be shifted into drm helpers, but it would require functions with 
signatures like
drm_dp_calc_pbn_mode(clock, bpp, dsc_bpp)
and
drm_dp_find_vcpi_slots(mst_mgr, pbn, fec_enabled, lane_count, link_rate)
and each driver would need to convert their own structs into those fields
before calling these helpers.

Is that worth it?

>> ---
>>   .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 41 ---
>>   1 file changed, 8 insertions(+), 33 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> index 5f2c315b18ba..b32c0790399a 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> @@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
>>int slots = 0;
>>bool ret;
>>int clock;
>> - int bpp = 0;
>>int pbn = 0;
>> + int pbn_per_timeslot;
>>
>>aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
>>
>> @@ -205,40 +205,15 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
>>mst_port = aconnector->port;
>>
>>if (enable) {
>> - clock = stream->timing.pix_clk_100hz / 10;
>> -
>> - switch (stream->timing.display_color_depth) {
>> -
>> - case COLOR_DEPTH_666:
>> - bpp = 6;
>> - break;
>> - case COLOR_DEPTH_888:
>> - bpp = 8;
>> - break;
>> - case COLOR_DEPTH_101010:
>> - bpp = 10;
>> - break;
>> - case COLOR_DEPTH_121212:
>> - bpp = 12;
>> - break;
>> - case COLOR_DEPTH_141414:
>> - bpp = 14;
>> - break;
>> - case COLOR_DEPTH_161616:
>> - bpp = 16;
>> - break;
>> - default:
>> - ASSERT(bpp != 0);
>> - break;
>> - }
>> -
>> - bpp = bpp * 3;
>> -
>> - /* TODO need to know link rate */
>> + clock = dc_bandwidth_in_kbps_from_timing(>timing);
>>
>> - pbn = drm_dp_calc_pbn_mode(clock, bpp);
>> + /* dc_bandwidth_in_kbps_from_timing already takes bpp into 
>> account */
>> + pbn = drm_dp_calc_pbn_mode(clock, 1);
>>
>> - slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
>> + /* Convert kilobits per second / 64 (for 64 timeslots) to pbn 
>> (54/64 megabytes per second) */
>> + pbn_per_timeslot = dc_link_bandwidth_kbps(
>> + stream->link, 
>> dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54);
>> + slots = DIV_ROUND_UP(pbn, pbn_per_timeslot);
>>ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
>>
>>if (!ret)


From: Kazlauskas, Nicholas 
Sent: August 19, 2019 3:21 PM
To: Francis, David; dri-de...@lists.freedesktop.org; 
amd-gfx@lists.freedesktop.org
Cc: Zuo, Jerry
Subject: Re: [PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot 
distribution

On 8/19/19 11:50 AM, David Francis wrote:
> We were using drm helpers to convert a timing into its
> bandwidth, its bandwidth into pbn, and its pbn into timeslots
>
> These helpers
> -Did not take DSC timings into account
> -Used the link rate and lane count of the link's aux device,
>   which are not the same as the link's current cap
> -Did not take FEC into account (FEC reduces the PBN per timeslot)
>
> Use the DC helpers (dc_bandwidth_in_kbps_from_timing,
> dc_link_bandwidth_kbps) instead
>
> Cc: Jerry Zuo 
> Signed-off-by: David Francis 

Wouldn't this be a good candidate for shared DRM helpers or to modify
the existing ones to support this usecase?

Seems like this would be shared 

Re: [PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors

[Kazlauskas, Nicholas]

On 8/19/19 11:50 AM, David Francis wrote:
> Whenever a connector on an MST network is attached, detached, or
> undergoes a modeset, the DSC configs for each stream on that
> topology will be recalculated. This can change their required
> bandwidth, requiring a full reprogramming, as though a modeset
> was performed, even if that stream did not change timing.
> 
> Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
> for each crtc that shares a MST topology with that stream and
> supports DSC, add that crtc (and all affected connectors and
> planes) to the atomic state and set mode_changed on its state
> 
> Cc: Leo Li 
> Cc: Nicholas Kazlauskas 
> Signed-off-by: David Francis 
> ---
>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 +++
>   1 file changed, 80 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 145fd73025dc..8d5357aec5e8 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -6475,7 +6475,78 @@ static int do_aquire_global_lock(struct drm_device 
> *dev,
>   
>   return ret < 0 ? ret : 0;
>   }
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> +static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct 
> drm_crtc *crtc)
> +{
> + struct drm_connector *connector;
> + struct drm_connector_state *conn_state;
> + struct drm_connector_list_iter conn_iter;
> + struct drm_crtc_state *new_crtc_state;
> + struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
> + int i, j, ret;
> + struct drm_crtc *crtcs_affected[MAX_PIPES] = { 0 }; > +
> + for_each_new_connector_in_state(state, connector, conn_state, i) {
> + if (conn_state->crtc != crtc)
> + continue;
> +
> + aconnector = to_amdgpu_dm_connector(connector);
> + if (!aconnector->port)
> + aconnector = NULL;
> + else
> + break;
> + }
> +
> + if (!aconnector)
> + return 0;
> +
> + i = 0;
> + drm_connector_list_iter_begin(state->dev, _iter);

I don't like that we're grabbing the global connector lock every single 
time any CRTC undergoes a modeset even for ASICs that don't support DSC.

We do lock everything below in atomic check anyway for FULL updates but 
I'd like to avoid adding more code that does this if possible. Maybe a 
check at the start that only does this if the ASIC has DSC support would 
be OK.

> + drm_for_each_connector_iter(connector, _iter) {
> + if (!connector->state || !connector->state->crtc)
> + continue;
> +
> + aconnector_to_add = to_amdgpu_dm_connector(connector);
> + if (!aconnector_to_add->port)
> + continue;
> +
> + if (aconnector_to_add->port->mgr != aconnector->port->mgr)
> + continue;
> +
> + if (!aconnector_to_add->dc_sink)
> + continue;
> +
> + if 
> (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
> + continue;
>   
> + if (i >= MAX_PIPES)
> + continue;
> +
> + crtcs_affected[i] = connector->state->crtc;

Drop this crtcs_affected array and just perform the logic below right 
here. We don't really need two loops here, redundant calls to 
drm_atomic_get_crtc_state and the other helpers are fine.

> + i++;
> + }
> + drm_connector_list_iter_end(_iter);
> +
> + for (j = 0; j < i; j++) {
> + new_crtc_state = drm_atomic_get_crtc_state(state, 
> crtcs_affected[j]);
> + if (IS_ERR(new_crtc_state))
> + return PTR_ERR(new_crtc_state);
> +
> + new_crtc_state->mode_changed = true;
> +
> + ret = drm_atomic_add_affected_connectors(state, 
> crtcs_affected[j]);
> + if (ret)
> + return ret;
> +
> + ret = drm_atomic_add_affected_planes(state, crtcs_affected[j]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +
> +}
> +#endif
>   static void get_freesync_config_for_crtc(
>   struct dm_crtc_state *new_crtc_state,
>   struct dm_connector_state *new_con_state)
> @@ -7178,6 +7249,15 @@ static int amdgpu_dm_atomic_check(struct drm_device 
> *dev,
>   goto fail;
>   }
>   
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 
> new_crtc_state, i) {
> + if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
> + ret = add_affected_mst_dsc_crtcs(state, crtc);
> + if (ret)
> + goto fail;
> + }
> + }
> +#endif
>   /*
>* Add all primary and overlay planes on 

Re: [PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot distribution

[Kazlauskas, Nicholas]

On 8/19/19 11:50 AM, David Francis wrote:
> We were using drm helpers to convert a timing into its
> bandwidth, its bandwidth into pbn, and its pbn into timeslots
> 
> These helpers
> -Did not take DSC timings into account
> -Used the link rate and lane count of the link's aux device,
>   which are not the same as the link's current cap
> -Did not take FEC into account (FEC reduces the PBN per timeslot)
> 
> Use the DC helpers (dc_bandwidth_in_kbps_from_timing,
> dc_link_bandwidth_kbps) instead
> 
> Cc: Jerry Zuo 
> Signed-off-by: David Francis 

Wouldn't this be a good candidate for shared DRM helpers or to modify 
the existing ones to support this usecase?

Seems like this would be shared across drivers.

Nicholas Kazlauskas

> ---
>   .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 41 ---
>   1 file changed, 8 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index 5f2c315b18ba..b32c0790399a 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
>   int slots = 0;
>   bool ret;
>   int clock;
> - int bpp = 0;
>   int pbn = 0;
> + int pbn_per_timeslot;
>   
>   aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
>   
> @@ -205,40 +205,15 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
>   mst_port = aconnector->port;
>   
>   if (enable) {
> - clock = stream->timing.pix_clk_100hz / 10;
> -
> - switch (stream->timing.display_color_depth) {
> -
> - case COLOR_DEPTH_666:
> - bpp = 6;
> - break;
> - case COLOR_DEPTH_888:
> - bpp = 8;
> - break;
> - case COLOR_DEPTH_101010:
> - bpp = 10;
> - break;
> - case COLOR_DEPTH_121212:
> - bpp = 12;
> - break;
> - case COLOR_DEPTH_141414:
> - bpp = 14;
> - break;
> - case COLOR_DEPTH_161616:
> - bpp = 16;
> - break;
> - default:
> - ASSERT(bpp != 0);
> - break;
> - }
> -
> - bpp = bpp * 3;
> -
> - /* TODO need to know link rate */
> + clock = dc_bandwidth_in_kbps_from_timing(>timing);
>   
> - pbn = drm_dp_calc_pbn_mode(clock, bpp);
> + /* dc_bandwidth_in_kbps_from_timing already takes bpp into 
> account */
> + pbn = drm_dp_calc_pbn_mode(clock, 1);
>   
> - slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
> + /* Convert kilobits per second / 64 (for 64 timeslots) to pbn 
> (54/64 megabytes per second) */
> + pbn_per_timeslot = dc_link_bandwidth_kbps(
> + stream->link, 
> dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54);
> + slots = DIV_ROUND_UP(pbn, pbn_per_timeslot);
>   ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
>   
>   if (!ret)
> 

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Re: [PATCH 05/14] drm/amd/display: Enable SST DSC in DM

[Mikita Lipski]

Tested-by: Mikita Lipski 

Mikita Lipski

On 2019-08-19 11:50 a.m., David Francis wrote:
> In create_stream_for_sink, check for SST DP connectors
> 
> Parse DSC caps to DC format, then, if DSC is supported,
> compute the config
> 
> DSC hardware will be programmed by dc_commit_state
> 
> Cc: Mikita Lipski 
> Signed-off-by: David Francis 
> ---
>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ---
>   .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  4 ++-
>   2 files changed, 24 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 911fe78b47c1..84249057e181 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3576,6 +3576,10 @@ create_stream_for_sink(struct amdgpu_dm_connector 
> *aconnector,
>   bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
>   int mode_refresh;
>   int preferred_refresh = 0;
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> + struct dsc_dec_dpcd_caps dsc_caps;
> + uint32_t link_bandwidth_kbps;
> +#endif
>   
>   struct dc_sink *sink = NULL;
>   if (aconnector == NULL) {
> @@ -3648,17 +3652,23 @@ create_stream_for_sink(struct amdgpu_dm_connector 
> *aconnector,
>   , >base, con_state, old_stream);
>   
>   #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> - /* stream->timing.flags.DSC = 0; */
> -/*  */
> - /* if (aconnector->dc_link && */
> - /*  aconnector->dc_link->connector_signal == 
> SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */
> - /*  
> aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) 
> */
> - /*  if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */
> - /*  >dc_link->dpcd_caps.dsc_caps, */
> - /*  dc_link_bandwidth_kbps(aconnector->dc_link, 
> dc_link_get_link_cap(aconnector->dc_link)), */
> - /*  >timing, */
> - /*  >timing.dsc_cfg)) */
> - /*  stream->timing.flags.DSC = 1; */
> + stream->timing.flags.DSC = 0;
> +
> + if (aconnector->dc_link && sink->sink_signal == 
> SIGNAL_TYPE_DISPLAY_PORT) {
> + 
> dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
> +   
> aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
> +   _caps);
> + link_bandwidth_kbps = 
> dc_link_bandwidth_kbps(aconnector->dc_link,
> +  
> dc_link_get_link_cap(aconnector->dc_link));
> +
> + if (dsc_caps.is_dsc_supported)
> + if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
> +   _caps,
> +   link_bandwidth_kbps,
> +   >timing,
> +   >timing.dsc_cfg))
> + stream->timing.flags.DSC = 1;
> + }
>   #endif
>   
>   update_stream_scaling_settings(, dm_state, stream);
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index 7cf0573ab25f..5f2c315b18ba 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -549,7 +549,9 @@ bool dm_helpers_dp_write_dsc_enable(
>   bool enable
>   )
>   {
> - return false;
> + uint8_t enable_dsc = enable ? 1 : 0;
> +
> + return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, 
> _dsc, 1);
>   }
>   #endif
>   
> 
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[PATCH 13/14] drm/amd/display: MST DSC compute fair share

[David Francis]

If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network

Implement an algorithm to determine the correct DSC config
for each stream

The algorithm:
This
 [   ]  ( )
represents the range of bandwidths possible for a given stream.
The [] area represents the range of DSC configs, and the ()
represents no DSC. The bandwidth used increases from left to right.

First, try disabling DSC on all streams
 [  ]  (|)
 [ ](|)
Check this against the bandwidth limits of the link and each branch
(including each endpoint). If it passes, the job is done

Second, try maximum DSC compression on all streams
that support DSC
 [| ]( )
 [|] ( )
If this does not pass, then enabling this combination of streams
is impossible

Otherwise, divide the remaining bandwidth evenly amongst the streams
 [|  ] ( )
 [|  ]( )

If one or more of the streams reach minimum compression, evenly
divide the reamining bandwidth amongst the remaining streams
 [|] ( )
 [   |]   ( )
 [ |   ]   ( )
 [ |  ]  ( )

If all streams can reach minimum compression, disable compression
greedily
 [  |]  ( )
 [|]( )
 [ ](|)

Perform this algorithm on each full update, on each MST link
with at least one DSC stream on it

After the configs are computed, call
dcn20_add_dsc_to_stream_resource on each stream with DSC enabled.
It is only after all streams are created that we can know which
of them will need DSC.

Do all of this at the end of amdgpu atomic check.  If it fails,
fail check; This combination of timings cannot be supported.

Cc: Wenjing Liu 
Cc: Nikola Cornij 
Signed-off-by: David Francis 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   4 +
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 375 ++
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   4 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
 5 files changed, 388 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 84249057e181..145fd73025dc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7331,6 +7331,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+   if (!compute_mst_dsc_configs_for_state(dm_state->context))
+   goto fail;
+#endif
if (dc_validate_global_state(dc, dm_state->context, false) != 
DC_OK) {
ret = -EINVAL;
goto fail;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 58571844f6d5..0b6bfa093e83 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -38,6 +38,8 @@
 
 #include "i2caux_interface.h"
 
+#include "dc/dcn20/dcn20_resource.h"
+
 /* #define TRACE_DPCD */
 
 #ifdef TRACE_DPCD
@@ -548,3 +550,376 @@ void amdgpu_dm_initialize_dp_connector(struct 
amdgpu_display_manager *dm,
aconnector->connector_id);
 }
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+struct dsc_mst_fairness_params {
+   struct dc_crtc_timing *timing;
+   struct dc_sink *sink;
+   struct dc_dsc_bw_range bw_range;
+   bool compression_possible;
+   struct drm_dp_mst_port *port;
+};
+
+struct dsc_mst_fairness_vars {
+   int pbn;
+   bool dsc_enabled;
+   int bpp_x16;
+};
+
+static bool port_downstream_of_branch(struct drm_dp_mst_port *port,
+   struct drm_dp_mst_branch *branch)
+{
+   while (port->parent) {
+   if (port->parent == branch)
+   return true;
+
+   if (port->parent->port_parent)
+   port = port->parent->port_parent;
+   else
+   break;
+   }
+   return false;
+}
+
+static bool check_pbn_limit_on_branch(struct drm_dp_mst_branch *branch,
+   struct dsc_mst_fairness_params *params,
+   struct dsc_mst_fairness_vars *vars, int count)
+{
+   struct drm_dp_mst_port *port;
+   int i;
+   int pbn_limit = 0;
+   int pbn_used = 0;
+
+   list_for_each_entry(port, >ports, next) {
+   if (port->mstb)
+   if (!check_pbn_limit_on_branch(port->mstb, params, 
vars, count))
+   return false;
+
+   if (port->available_pbn > 

[PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors

[David Francis]

Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not change timing.

Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
for each crtc that shares a MST topology with that stream and
supports DSC, add that crtc (and all affected connectors and
planes) to the atomic state and set mode_changed on its state

Cc: Leo Li 
Cc: Nicholas Kazlauskas 
Signed-off-by: David Francis 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 +++
 1 file changed, 80 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 145fd73025dc..8d5357aec5e8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6475,7 +6475,78 @@ static int do_aquire_global_lock(struct drm_device *dev,
 
return ret < 0 ? ret : 0;
 }
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct 
drm_crtc *crtc)
+{
+   struct drm_connector *connector;
+   struct drm_connector_state *conn_state;
+   struct drm_connector_list_iter conn_iter;
+   struct drm_crtc_state *new_crtc_state;
+   struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
+   int i, j, ret;
+   struct drm_crtc *crtcs_affected[MAX_PIPES] = { 0 };
+
+   for_each_new_connector_in_state(state, connector, conn_state, i) {
+   if (conn_state->crtc != crtc)
+   continue;
+
+   aconnector = to_amdgpu_dm_connector(connector);
+   if (!aconnector->port)
+   aconnector = NULL;
+   else
+   break;
+   }
+
+   if (!aconnector)
+   return 0;
+
+   i = 0;
+   drm_connector_list_iter_begin(state->dev, _iter);
+   drm_for_each_connector_iter(connector, _iter) {
+   if (!connector->state || !connector->state->crtc)
+   continue;
+
+   aconnector_to_add = to_amdgpu_dm_connector(connector);
+   if (!aconnector_to_add->port)
+   continue;
+
+   if (aconnector_to_add->port->mgr != aconnector->port->mgr)
+   continue;
+
+   if (!aconnector_to_add->dc_sink)
+   continue;
+
+   if 
(!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
+   continue;
 
+   if (i >= MAX_PIPES)
+   continue;
+
+   crtcs_affected[i] = connector->state->crtc;
+   i++;
+   }
+   drm_connector_list_iter_end(_iter);
+
+   for (j = 0; j < i; j++) {
+   new_crtc_state = drm_atomic_get_crtc_state(state, 
crtcs_affected[j]);
+   if (IS_ERR(new_crtc_state))
+   return PTR_ERR(new_crtc_state);
+
+   new_crtc_state->mode_changed = true;
+
+   ret = drm_atomic_add_affected_connectors(state, 
crtcs_affected[j]);
+   if (ret)
+   return ret;
+
+   ret = drm_atomic_add_affected_planes(state, crtcs_affected[j]);
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+
+}
+#endif
 static void get_freesync_config_for_crtc(
struct dm_crtc_state *new_crtc_state,
struct dm_connector_state *new_con_state)
@@ -7178,6 +7249,15 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
goto fail;
}
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+   for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 
new_crtc_state, i) {
+   if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
+   ret = add_affected_mst_dsc_crtcs(state, crtc);
+   if (ret)
+   goto fail;
+   }
+   }
+#endif
/*
 * Add all primary and overlay planes on the CRTC to the state
 * whenever a plane is enabled to maintain correct z-ordering
-- 
2.17.1

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[PATCH 12/14] drm/amd/display: Write DSC enable to MST DPCD

[David Francis]

Rework the dm_helpers_write_dsc_enable callback to
handle the MST case

Depending on how DSC is done, the DP_DSC_ENABLE bit
needs to be set on a different point

For SST, use the link aux

For endpoint DSC over DP-to-DP peer devices,
use the output port

For peer device DSC over DP-to-DP peer devices,
use the upstream (peer) device

For DP-to-HDMI or virtual DP peer devices,
use the output port

For the Synaptix workaround, use the link aux

Cc: Wenjing Liu 
Cc: Nikola Cornij 
Signed-off-by: David Francis 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 30 ++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index b32c0790399a..3d5deeed8367 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -38,6 +38,7 @@
 #include "dc.h"
 #include "amdgpu_dm.h"
 #include "amdgpu_dm_irq.h"
+#include "amdgpu_dm_mst_types.h"
 
 #include "dm_helpers.h"
 
@@ -525,8 +526,35 @@ bool dm_helpers_dp_write_dsc_enable(
 )
 {
uint8_t enable_dsc = enable ? 1 : 0;
+   struct amdgpu_dm_connector *aconnector;
+
+   if (!stream)
+   return false;
+
+   if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+   aconnector = (struct amdgpu_dm_connector 
*)stream->dm_stream_context;
+
+   if (!aconnector || !aconnector->dc_sink)
+   return false;
+
+   if (!aconnector->dc_sink->sink_dsc_caps.is_virtual_dpcd_dsc)
+   return drm_dp_mst_dpcd_write(>port->aux,
+   DP_DSC_ENABLE, _dsc, 
1) >= 0;
+   else if (is_virtual_dpcd(aconnector->port->parent->port_parent))
+   return 
drm_dp_mst_dpcd_write(>port->parent->port_parent->aux,
+   DP_DSC_ENABLE, _dsc, 
1) >= 0;
+   else if (is_virtual_dpcd(aconnector->port))
+   return drm_dp_mst_dpcd_write(>port->aux,
+   DP_DSC_ENABLE, _dsc, 
1) >= 0;
+   else if (synaptix_workaround(aconnector))
+   return dm_helpers_dp_write_dpcd(ctx, stream->link,
+   DP_DSC_ENABLE, _dsc, 1);
+   }
+
+   if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT)
+   return dm_helpers_dp_write_dpcd(ctx, stream->link, 
DP_DSC_ENABLE, _dsc, 1);
 
-   return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, 
_dsc, 1);
+   return false;
 }
 #endif
 
-- 
2.17.1

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[PATCH 00/14] Display Stream Compression (DSC) for AMD Navi

[David Francis]

This patchset enables Display Stream Compression (DSC) on DP 
connectors on Navi ASICs, both SST and DSC.

8k60 and 4k144 support requires ODM combine, an AMD internal
feature that may be a bit buggy right now.

Patches 1 through 5 enable DSC for SST. Most of the work was
already done in the Navi promotion patches; this just hooks
it up to the atomic interface. The first two reverts are of temporary
changes to block off DSC. The third is of a commit that was
accidentally promoted twice. The fourth and last revert fixes a 
potential issue with ODM combine.

Patches 6 and 7 are fixes for bugs that would be exposed by 
MST DSC. One fix is with the MST code and the other in the DSC code.

Patches 8, 9, and 10 are small DRM changes required for DSC MST:
FEC, a new bit in the standard; some export definitions; and
a previously uninitialized variable.

Patches 11 through 14 are the DSC MST policy itself. This includes
the code for detecting and validating DSC capabilities, enabling
DSC over a link, computing the fair DSC configurations for
multiple DSC displays, and adding to atomic state crtcs that might 
need reprogramming due to DSC.

David Francis (14):
  Revert "drm/amd/display: skip dsc config for navi10 bring up"
  Revert "drm/amd/display: navi10 bring up skip dsc encoder config"
  Revert "drm/amd/display: add global master update lock for DCN2"
  Revert "drm/amd/display: Fix underscan not using proper scaling"
  drm/amd/display: Enable SST DSC in DM
  drm/amd/display: Use dc helpers to compute timeslot distribution
  drm/amd/display: Initialize DSC PPS variables to 0
  drm/dp-mst: Parse FEC capability on MST ports
  drm/dp-mst: Export symbols for dpcd read/write
  drm/dp-mst: Fill branch->num_ports
  drm/amd/display: Validate DSC caps on MST endpoints
  drm/amd/display: Write DSC enable to MST DPCD
  drm/amd/display: MST DSC compute fair share
  drm/amd/display: Trigger modesets on MST DSC connectors

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 116 +++-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  71 +--
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 498 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   5 +
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  12 +-
 .../drm/amd/display/dc/core/dc_link_hwss.c|   3 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |   3 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|   4 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  72 +--
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   3 -
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
 .../display/dc/dcn20/dcn20_stream_encoder.c   |   8 -
 .../amd/display/dc/inc/hw/timing_generator.h  |   2 -
 drivers/gpu/drm/drm_dp_mst_topology.c |   6 +
 include/drm/drm_dp_mst_helper.h   |   3 +
 16 files changed, 668 insertions(+), 146 deletions(-)

-- 
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[PATCH 10/14] drm/dp-mst: Fill branch->num_ports

[David Francis]

This field on drm_dp_mst_branch was never filled

Initialize it to zero when the list of ports is created.
When a port is added to the list, increment num_ports

Signed-off-by: David Francis 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 5a072571cb44..31b7213b6036 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -918,6 +918,7 @@ static struct drm_dp_mst_branch 
*drm_dp_add_mst_branch_device(u8 lct, u8 *rad)
INIT_LIST_HEAD(>ports);
kref_init(>topology_kref);
kref_init(>malloc_kref);
+   mstb->num_ports = 0;
return mstb;
 }
 
@@ -1672,6 +1673,7 @@ static void drm_dp_add_port(struct drm_dp_mst_branch 
*mstb,
mutex_lock(>mgr->lock);
drm_dp_mst_topology_get_port(port);
list_add(>next, >ports);
+   mstb->num_ports++;
mutex_unlock(>mgr->lock);
}
 
-- 
2.17.1

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[PATCH 11/14] drm/amd/display: Validate DSC caps on MST endpoints

[David Francis]

The first step in MST DSC is checking MST endpoints
to see how DSC can be enabled

Case 1: DP-to-DP peer device
if the branch immediately upstream has
 - PDT = DP_PEER_DEVICE_DP_MST_BRANCHING (2)
 - DPCD rev. >= DP 1.4
 - Exactly one input and one output
 - The output has PDT = DP_PEER_DEVICE_SST_SINK (3)

In this case, DSC could be possible either on the endpoint
or the peer device. Prefer the endpoint, which is possible if
 - The endpoint has DP_DSC_DECOMPRESSION_IS_SUPPORTED bit set
 - The endpoint has DP_FEC_CAPABLE bit set
 - The peer device has DSC_PASSTHROUGH_CAPABILITY bit set (from DP v2.0)

Otherwise, use the peer device

Case 2: DP-to-HDMI peer device
If the output port has
 - PDT = DP_PEER_DEVICE_DP_LEGACY_CONV (4)
 - DPCD rev. >= DP 1.4
 - LDPS = true
 - MCS = false

In this case, DSC can only be attempted on the peer device
(the output port)

Case 3: Virtual DP Sink (Internal Display Panel)
If the output port has
 - DPCD rev. >= DP 1.4
 - port_num >= 8

In this case, DSC can only be attempted on the peer device
(the output port)

Case 4: Synaptix Workaround
If the output has
 - link DPCD rev. >= DP 1.4
 - link branch_dev_id = 0x90CC24 (Synaptix)
 - There is exactly one branch device between the link and output

In this case, DSC can be attempted, but only using the *link*
aux device's caps. This is a quirk.

Test for these cases as modes are enumerated for an MST endpoint.
We cannot do this during link attach because the dc_sink object
will not have been created yet

If no DSC is attempted, zero the DSC caps

Cc: Wenjing Liu 
Cc: Nikola Cornij 
Signed-off-by: David Francis 
---
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 123 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   3 +
 2 files changed, 125 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 16218a202b59..58571844f6d5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -25,6 +25,7 @@
 
 #include 
 #include 
+#include 
 #include "dm_services.h"
 #include "amdgpu.h"
 #include "amdgpu_dm.h"
@@ -189,6 +190,120 @@ static const struct drm_connector_funcs 
dm_dp_mst_connector_funcs = {
.early_unregister = amdgpu_dm_mst_connector_early_unregister,
 };
 
+bool is_virtual_dpcd(struct drm_dp_mst_port *port)
+{
+   struct drm_dp_mst_port *downstream_port;
+
+   if (!port)
+   return false;
+
+   if (port->port_num >= 8 &&
+   port->dpcd_rev >= DP_DPCD_REV_14) {
+   /* Virtual DP Sink (Internal Display Panel) */
+   return true;
+   } else if (port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV &&
+   !port->mcs &&
+   port->ldps &&
+   port->dpcd_rev >= DP_DPCD_REV_14) {
+   /* DP-to-HDMI Protocol Converter */
+   return true;
+   } else if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
+   port->mstb &&
+   port->dpcd_rev >= DP_DPCD_REV_14) {
+   /* DP-to-DP */
+   if (port->mstb->num_ports == 2) {
+   list_for_each_entry(downstream_port, 
>mstb->ports, next) {
+   if (!downstream_port->input &&
+   downstream_port->pdt == 
DP_PEER_DEVICE_SST_SINK)
+   return true;
+   }
+   }
+   }
+   return false;
+}
+
+bool synaptix_workaround(struct amdgpu_dm_connector *aconnector)
+{
+   struct drm_dp_mst_port *port = aconnector->port;
+   struct dc_link *link = aconnector->dc_sink->link;
+   u8 down_stream_port_data;
+
+   if (port->mgr->mst_primary == port->parent &&
+   link->dpcd_caps.branch_dev_id == 0x90CC24 &&
+   link->dpcd_caps.dpcd_rev.raw >= DP_DPCD_REV_14) {
+   drm_dp_mst_dpcd_read(>aux, DP_DOWNSTREAMPORT_PRESENT, 
_stream_port_data, 1);
+   if ((down_stream_port_data & 7) != 3)
+   return true;
+   }
+   return false;
+}
+
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector 
*aconnector)
+{
+   u8 upstream_dsc_caps[16] = { 0 };
+   u8 endpoint_dsc_caps[16] = { 0 };
+   u8 endpoint_fec_caps = 0;
+   struct dc_sink *dc_sink = aconnector->dc_sink;
+   struct drm_dp_mst_port *output_port = aconnector->port;
+   struct drm_dp_mst_port *immediate_upstream_port;
+   struct drm_dp_mst_port *fec_port;
+
+   if (aconnector->port && aconnector->port->parent)
+   immediate_upstream_port = aconnector->port->parent->port_parent;
+   else
+   immediate_upstream_port = NULL;
+
+   fec_port = immediate_upstream_port;
+   

[PATCH 02/14] Revert "drm/amd/display: navi10 bring up skip dsc encoder config"

[David Francis]

This reverts commit 5f2fd347eeff7d4ce271920efd47baaa18fe968c.

Re-enable enc2_dp_set_dsc_config. This function caused warnings
due to missing register definitions. With the registers added,
this now works

Signed-off-by: David Francis 
Reviewed-by: Roman Li 
Reviewed-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c   | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 6d54942ab98b..a4e67286cdad 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -277,14 +277,6 @@ static void enc2_dp_set_dsc_config(struct stream_encoder 
*enc,
uint32_t dsc_slice_width)
 {
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
-   uint32_t dsc_value = 0;
-
-   dsc_value = REG_READ(DP_DSC_CNTL);
-
-   /* dsc disable skip */
-   if ((dsc_value & 0x3) == 0x0)
-   return;
-
 
REG_UPDATE_2(DP_DSC_CNTL,
DP_DSC_MODE, dsc_mode,
-- 
2.17.1

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[PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot distribution

[David Francis]

We were using drm helpers to convert a timing into its
bandwidth, its bandwidth into pbn, and its pbn into timeslots

These helpers
-Did not take DSC timings into account
-Used the link rate and lane count of the link's aux device,
 which are not the same as the link's current cap
-Did not take FEC into account (FEC reduces the PBN per timeslot)

Use the DC helpers (dc_bandwidth_in_kbps_from_timing,
dc_link_bandwidth_kbps) instead

Cc: Jerry Zuo 
Signed-off-by: David Francis 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 41 ---
 1 file changed, 8 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 5f2c315b18ba..b32c0790399a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
int slots = 0;
bool ret;
int clock;
-   int bpp = 0;
int pbn = 0;
+   int pbn_per_timeslot;
 
aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 
@@ -205,40 +205,15 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
mst_port = aconnector->port;
 
if (enable) {
-   clock = stream->timing.pix_clk_100hz / 10;
-
-   switch (stream->timing.display_color_depth) {
-
-   case COLOR_DEPTH_666:
-   bpp = 6;
-   break;
-   case COLOR_DEPTH_888:
-   bpp = 8;
-   break;
-   case COLOR_DEPTH_101010:
-   bpp = 10;
-   break;
-   case COLOR_DEPTH_121212:
-   bpp = 12;
-   break;
-   case COLOR_DEPTH_141414:
-   bpp = 14;
-   break;
-   case COLOR_DEPTH_161616:
-   bpp = 16;
-   break;
-   default:
-   ASSERT(bpp != 0);
-   break;
-   }
-
-   bpp = bpp * 3;
-
-   /* TODO need to know link rate */
+   clock = dc_bandwidth_in_kbps_from_timing(>timing);
 
-   pbn = drm_dp_calc_pbn_mode(clock, bpp);
+   /* dc_bandwidth_in_kbps_from_timing already takes bpp into 
account */
+   pbn = drm_dp_calc_pbn_mode(clock, 1);
 
-   slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
+   /* Convert kilobits per second / 64 (for 64 timeslots) to pbn 
(54/64 megabytes per second) */
+   pbn_per_timeslot = dc_link_bandwidth_kbps(
+   stream->link, 
dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54);
+   slots = DIV_ROUND_UP(pbn, pbn_per_timeslot);
ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
 
if (!ret)
-- 
2.17.1

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[PATCH 09/14] drm/dp-mst: Export symbols for dpcd read/write

[David Francis]

To use these functions in drm driver directories, they must be
exported

Signed-off-by: David Francis 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 53a0ad16e37b..5a072571cb44 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -1512,6 +1512,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
return drm_dp_send_dpcd_read(port->mgr, port,
 offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_read);
 
 /**
  * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
@@ -1535,6 +1536,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
return drm_dp_send_dpcd_write(port->mgr, port,
  offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_write);
 
 static void drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, u8 *guid)
 {
-- 
2.17.1

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[PATCH 08/14] drm/dp-mst: Parse FEC capability on MST ports

[David Francis]

As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.

The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)

That value is needed for FEC and DSC support

Store it on drm_dp_mst_port

Signed-off-by: David Francis 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
 include/drm/drm_dp_mst_helper.h   | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 398e7314ea8b..53a0ad16e37b 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -552,6 +552,7 @@ static bool 
drm_dp_sideband_parse_enum_path_resources_ack(struct drm_dp_sideband
 {
int idx = 1;
repmsg->u.path_resources.port_number = (raw->msg[idx] >> 4) & 0xf;
+   repmsg->u.path_resources.fec_capable = raw->msg[idx] & 0x1;
idx++;
if (idx > raw->curlen)
goto fail_len;
@@ -2180,6 +2181,7 @@ static int drm_dp_send_enum_path_resources(struct 
drm_dp_mst_topology_mgr *mgr,
DRM_DEBUG_KMS("enum path resources %d: %d %d\n", 
txmsg->reply.u.path_resources.port_number, 
txmsg->reply.u.path_resources.full_payload_bw_number,
   
txmsg->reply.u.path_resources.avail_payload_bw_number);
port->available_pbn = 
txmsg->reply.u.path_resources.avail_payload_bw_number;
+   port->fec_capable = 
txmsg->reply.u.path_resources.fec_capable;
}
}
 
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 2ba6253ea6d3..e1801781fff5 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -108,6 +108,8 @@ struct drm_dp_mst_port {
 * audio-capable.
 */
bool has_audio;
+
+   bool fec_capable;
 };
 
 /**
@@ -312,6 +314,7 @@ struct drm_dp_port_number_req {
 
 struct drm_dp_enum_path_resources_ack_reply {
u8 port_number;
+   bool fec_capable;
u16 full_payload_bw_number;
u16 avail_payload_bw_number;
 };
-- 
2.17.1

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[PATCH 05/14] drm/amd/display: Enable SST DSC in DM

[David Francis]

In create_stream_for_sink, check for SST DP connectors

Parse DSC caps to DC format, then, if DSC is supported,
compute the config

DSC hardware will be programmed by dc_commit_state

Cc: Mikita Lipski 
Signed-off-by: David Francis 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  4 ++-
 2 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 911fe78b47c1..84249057e181 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3576,6 +3576,10 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
int mode_refresh;
int preferred_refresh = 0;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+   struct dsc_dec_dpcd_caps dsc_caps;
+   uint32_t link_bandwidth_kbps;
+#endif
 
struct dc_sink *sink = NULL;
if (aconnector == NULL) {
@@ -3648,17 +3652,23 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
, >base, con_state, old_stream);
 
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-   /* stream->timing.flags.DSC = 0; */
-/*  */
-   /* if (aconnector->dc_link && */
-   /*  aconnector->dc_link->connector_signal == 
SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */
-   /*  
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */
-   /*  if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */
-   /*  >dc_link->dpcd_caps.dsc_caps, */
-   /*  dc_link_bandwidth_kbps(aconnector->dc_link, 
dc_link_get_link_cap(aconnector->dc_link)), */
-   /*  >timing, */
-   /*  >timing.dsc_cfg)) */
-   /*  stream->timing.flags.DSC = 1; */
+   stream->timing.flags.DSC = 0;
+
+   if (aconnector->dc_link && sink->sink_signal == 
SIGNAL_TYPE_DISPLAY_PORT) {
+   
dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
+ 
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
+ _caps);
+   link_bandwidth_kbps = 
dc_link_bandwidth_kbps(aconnector->dc_link,
+
dc_link_get_link_cap(aconnector->dc_link));
+
+   if (dsc_caps.is_dsc_supported)
+   if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
+ _caps,
+ link_bandwidth_kbps,
+ >timing,
+ >timing.dsc_cfg))
+   stream->timing.flags.DSC = 1;
+   }
 #endif
 
update_stream_scaling_settings(, dm_state, stream);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 7cf0573ab25f..5f2c315b18ba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -549,7 +549,9 @@ bool dm_helpers_dp_write_dsc_enable(
bool enable
 )
 {
-   return false;
+   uint8_t enable_dsc = enable ? 1 : 0;
+
+   return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, 
_dsc, 1);
 }
 #endif
 
-- 
2.17.1

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[PATCH 04/14] Revert "drm/amd/display: Fix underscan not using proper scaling"

[David Francis]

This reverts commit 80e80ec817f161560b4159608fb41bd289abede3.

This commit fixed an issue with underscan commits not updating all
needed timing values, but through various refactors it is no longer
necessary. It causes corruption on odm combine by
overwriting the halved h_active in the stream timing

Signed-off-by: David Francis 
Reviewed-by: Roman Li 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +---
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 77ac7f707ec5..1189e320062b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2127,7 +2127,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
enum surface_update_type update_type;
struct dc_state *context;
struct dc_context *dc_ctx = dc->ctx;
-   int i, j;
+   int i;
 
stream_status = dc_stream_get_status(stream);
context = dc->current_state;
@@ -2165,16 +2165,6 @@ void dc_commit_updates_for_stream(struct dc *dc,
 
copy_surface_update_to_plane(surface, _updates[i]);
 
-   if (update_type >= UPDATE_TYPE_MED) {
-   for (j = 0; j < dc->res_pool->pipe_count; j++) {
-   struct pipe_ctx *pipe_ctx = 
>res_ctx.pipe_ctx[j];
-
-   if (pipe_ctx->plane_state != surface)
-   continue;
-
-   resource_build_scaling_params(pipe_ctx);
-   }
-   }
}
 
copy_stream_update_to_stream(dc, context, stream, stream_update);
-- 
2.17.1

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[PATCH 07/14] drm/amd/display: Initialize DSC PPS variables to 0

[David Francis]

For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.

memset to 0 to avoid this

Signed-off-by: David Francis 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c   | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 35c5467e60e8..619ac48edd05 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -491,6 +491,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool 
enable)
struct dsc_config dsc_cfg;
uint8_t dsc_packed_pps[128];
 
+   memset(_cfg, 0, sizeof(dsc_cfg));
+   memset(dsc_packed_pps, 0, 128);
+
/* Enable DSC hw block */
dsc_cfg.pic_width = stream->timing.h_addressable + 
stream->timing.h_border_left + stream->timing.h_border_right;
dsc_cfg.pic_height = stream->timing.v_addressable + 
stream->timing.v_border_top + stream->timing.v_border_bottom;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 379c9e4ac63b..16debe6d89f2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct 
display_stream_compressor *dsc, const str
struct dsc_reg_values dsc_reg_vals;
struct dsc_optc_config dsc_optc_cfg;
 
+   memset(_reg_vals, 0, sizeof(dsc_reg_vals));
+   memset(_optc_cfg, 0, sizeof(dsc_optc_cfg));
+
DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
dsc_config_log(dsc, dsc_cfg);
DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
-- 
2.17.1

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[PATCH 03/14] Revert "drm/amd/display: add global master update lock for DCN2"

[David Francis]

This reverts commit 55a6f5bbcf00a49565946c0a9b8c716313dc6c05.

This commit was accidentally promoted twice

Signed-off-by: David Francis 
Reviewed-by: Roman Li 
Reviewed-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  4 --
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 63 +--
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |  3 -
 .../amd/display/dc/inc/hw/timing_generator.h  |  2 -
 4 files changed, 1 insertion(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fa8a73f6c8e3..e146d1d8d45e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -575,10 +575,6 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->stream->signal,
true);
 
-   if (pipe_ctx->stream_res.tg->funcs->setup_global_lock)
-   pipe_ctx->stream_res.tg->funcs->setup_global_lock(
-   pipe_ctx->stream_res.tg);
-
if (odm_pipe)
odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
odm_pipe->stream_res.opp,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 99070e93020b..2137e2be2140 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -333,65 +333,6 @@ void optc2_triplebuffer_unlock(struct timing_generator 
*optc)
 
 }
 
-
-void optc2_setup_global_lock(struct timing_generator *optc)
-{
-   struct optc *optc1 = DCN10TG_FROM_TG(optc);
-   uint32_t v_blank_start = 0;
-   uint32_t h_blank_start = 0, h_total = 0;
-
-   REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 1);
-
-   REG_SET(OTG_GLOBAL_CONTROL2, 0, DIG_UPDATE_LOCATION, 20);
-
-   REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, _blank_start);
-
-   REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, _blank_start);
-
-   REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, _total);
-   REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
-   MASTER_UPDATE_LOCK_DB_X,
-   h_blank_start - 200 - 1,
-   MASTER_UPDATE_LOCK_DB_Y,
-   v_blank_start - 1);
-}
-
-void optc2_lock_global(struct timing_generator *optc)
-{
-   struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-   REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
-
-   REG_SET(OTG_GLOBAL_CONTROL0, 0,
-   OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-   REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-   OTG_MASTER_UPDATE_LOCK, 1);
-
-   /* Should be fast, status does not update on maximus */
-   if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-   REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-   UPDATE_LOCK_STATUS, 1,
-   1, 10);
-}
-
-void optc2_lock(struct timing_generator *optc)
-{
-   struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-   REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
-
-   REG_SET(OTG_GLOBAL_CONTROL0, 0,
-   OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-   REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-   OTG_MASTER_UPDATE_LOCK, 1);
-
-   /* Should be fast, status does not update on maximus */
-   if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-   REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-   UPDATE_LOCK_STATUS, 1,
-   1, 10);
-}
-
 void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
 {
struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -486,10 +427,8 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
.triplebuffer_lock = optc2_triplebuffer_lock,
.triplebuffer_unlock = optc2_triplebuffer_unlock,
.disable_reset_trigger = optc1_disable_reset_trigger,
-   .lock = optc2_lock,
+   .lock = optc1_lock,
.unlock = optc1_unlock,
-   .lock_global = optc2_lock_global,
-   .setup_global_lock = optc2_setup_global_lock,
.lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
.lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
.enable_optc_clock = optc1_enable_optc_clock,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index 47cb4de1564c..32a58431fd09 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -106,9 +106,6 @@ void optc2_get_optc_source(struct timing_generator *optc,
 
 void optc2_triplebuffer_lock(struct timing_generator *optc);
 void optc2_triplebuffer_unlock(struct 

[PATCH 01/14] Revert "drm/amd/display: skip dsc config for navi10 bring up"

[David Francis]

This reverts commit 55ad81f3510ec1a1c19e6a4d8a6319812d07d256.

optc dsc config was causing warnings due to missing register
definitions. With the registers restored, the function can
be re-enabled

The reverted commit also disabled sanity checks and dsc
power gating. The sanity check warnings are not associated
with dsc, and power gating on dsc still has an issue on
non-dsc monitors where the dsc hardware block is never init
and so cannot respond to power gating requests. Therefore,
those are left as is

Signed-off-by: David Francis 
Reviewed-by: Roman Li 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index aedf9de1c947..99070e93020b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -191,15 +191,6 @@ void optc2_set_dsc_config(struct timing_generator *optc,
uint32_t dsc_slice_width)
 {
struct optc *optc1 = DCN10TG_FROM_TG(optc);
-   uint32_t data_format = 0;
-   /* skip if dsc mode is not changed */
-   data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL));
-
-   data_format = data_format & 0x30; /* bit5:4 */
-   data_format = data_format >> 4;
-
-   if (data_format == dsc_mode)
-   return;
 
REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
OPTC_DSC_MODE, dsc_mode);
-- 
2.17.1

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[PATCH] drm/amd/powerplay: fix variable type errors in smu_v11_0_setup_pptable

[Wang, Kevin(Yang)]

fix size type errors, from uint32_t to uint16_t.
it will cause only initializes the highest 16 bits in
smu_get_atom_data_table function.

Signed-off-by: Kevin Wang 
Reported-by: Dan Carpenter 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index b69632fe856b..e9a022447ac1 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -368,6 +368,7 @@ static int smu_v11_0_setup_pptable(struct smu_context *smu)
const struct smc_firmware_header_v1_0 *hdr;
int ret, index;
uint32_t size;
+   uint16_t atom_table_size;
uint8_t frev, crev;
void *table;
uint16_t version_major, version_minor;
@@ -395,10 +396,11 @@ static int smu_v11_0_setup_pptable(struct smu_context 
*smu)
index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
powerplayinfo);
 
-   ret = smu_get_atom_data_table(smu, index, (uint16_t *), 
, ,
+   ret = smu_get_atom_data_table(smu, index, _table_size, 
, ,
  (uint8_t **));
if (ret)
return ret;
+   size = atom_table_size;
}
 
if (!smu->smu_table.power_play_table)
-- 
2.22.0

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Re: [PATCH ARM] selftests, arm64: fix uninitialized symbol in tags_test.c

[Andrey Konovalov]

On Mon, Aug 19, 2019 at 5:39 PM Will Deacon  wrote:
>
> On Mon, Aug 19, 2019 at 05:16:37PM +0200, Andrey Konovalov wrote:
> > On Mon, Aug 19, 2019 at 5:03 PM Will Deacon  wrote:
> > >
> > > On Mon, Aug 19, 2019 at 03:14:42PM +0200, Andrey Konovalov wrote:
> > > > Fix tagged_ptr not being initialized when TBI is not enabled.
> > > >
> > > > Dan Carpenter 
> > >
> > > Guessing this was Reported-by, or has Dan introduced his own tag now? ;)
> >
> > Oops, yes, Reported-by :)
> >
> > >
> > > Got a link to the report?
> >
> > https://www.spinics.net/lists/linux-kselftest/msg09446.html
>
> Thanks, I'll fix up the commit message and push this out later on. If you
> get a chance, would you be able to look at the pending changes from
> Catalin[1], please?
>
> Will
>
> [1] https://lkml.kernel.org/r/20190815154403.16473-1-catalin.mari...@arm.com

Sure! I didn't realize some actioned is required from me on those.
I'll add my Acked-by's. Thanks!

Re: [PATCH ARM] selftests, arm64: fix uninitialized symbol in tags_test.c

[Will Deacon]

On Mon, Aug 19, 2019 at 05:16:37PM +0200, Andrey Konovalov wrote:
> On Mon, Aug 19, 2019 at 5:03 PM Will Deacon  wrote:
> >
> > On Mon, Aug 19, 2019 at 03:14:42PM +0200, Andrey Konovalov wrote:
> > > Fix tagged_ptr not being initialized when TBI is not enabled.
> > >
> > > Dan Carpenter 
> >
> > Guessing this was Reported-by, or has Dan introduced his own tag now? ;)
> 
> Oops, yes, Reported-by :)
> 
> >
> > Got a link to the report?
> 
> https://www.spinics.net/lists/linux-kselftest/msg09446.html

Thanks, I'll fix up the commit message and push this out later on. If you
get a chance, would you be able to look at the pending changes from
Catalin[1], please?

Will

[1] https://lkml.kernel.org/r/20190815154403.16473-1-catalin.mari...@arm.com

Re: [PATCH] drm/amd/powerplay: add smu_smc_read_sensor support for arcturus

[Alex Deucher]

On Fri, Aug 16, 2019 at 3:22 AM Wang, Kevin(Yang)  wrote:
>
> the bellow patch refine the sensor read sequence,
> but missed to add arcuturs support. (arcuturs_ppt.c)
>
> drm/amd/powerplay: change smu_read_sensor sequence in smu
>
> Signed-off-by: Kevin Wang 
> ---
>  drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index fcf623cf5d2c..850b2a1ef329 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -1012,6 +1012,9 @@ static int arcturus_read_sensor(struct smu_context *smu,
> PPTable_t *pptable = table_context->driver_pptable;
> int ret = 0;
>
> +   if(!data || !size)

Please add a space between if the if and the (.  E.g.,
if (!data || !size)

Alex

> +   return -EINVAL;
> +
> switch (sensor) {
> case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
> *(uint32_t *)data = pptable->FanMaximumRpm;
> @@ -1036,7 +1039,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
> *size = 4;
> break;
> default:
> -   return -EINVAL;
> +   ret = smu_smc_read_sensor(smu, sensor, data, size);
> }
>
> return ret;
> --
> 2.22.0
>
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Re: [bug report] drm/amd/powerplay: implement smc firmware v2.1 for smu11

[Wang, Kevin(Yang)]

Hi Dan,

Thank you for reporting this bug to me,
I will make a  fix patch as soon as possible, when patch ready after I send 
copies to you review,
thank you.

Best Regards,
Kevin

From: Dan Carpenter 
Sent: Monday, August 19, 2019 9:03 PM
To: Wang, Kevin(Yang) 
Cc: amd-gfx@lists.freedesktop.org 
Subject: [bug report] drm/amd/powerplay: implement smc firmware v2.1 for smu11

Hello Kevin Wang,

The patch b55c83a7438d: "drm/amd/powerplay: implement smc firmware
v2.1 for smu11" from Jun 21, 2019, leads to the following static
checker warning:

drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:390 
smu_v11_0_setup_pptable()
warn: passing casted pointer '' to 'smu_get_atom_data_table()' 32 
vs 16.

drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c
   357  static int smu_v11_0_setup_pptable(struct smu_context *smu)
   358  {
   359  struct amdgpu_device *adev = smu->adev;
   360  const struct smc_firmware_header_v1_0 *hdr;
   361  int ret, index;
   362  uint32_t size;
^

   363  uint8_t frev, crev;
   364  void *table;
   365  uint16_t version_major, version_minor;
   366
   367  hdr = (const struct smc_firmware_header_v1_0 *) 
adev->pm.fw->data;
   368  version_major = le16_to_cpu(hdr->header.header_version_major);
   369  version_minor = le16_to_cpu(hdr->header.header_version_minor);
   370  if (version_major == 2 && 
smu->smu_table.boot_values.pp_table_id > 0) {
   371  switch (version_minor) {
   372  case 0:
   373  ret = smu_v11_0_set_pptable_v2_0(smu, , 
);
   374  break;
   375  case 1:
   376  ret = smu_v11_0_set_pptable_v2_1(smu, , 
,
   377   
smu->smu_table.boot_values.pp_table_id);
   378  break;
   379  default:
   380  ret = -EINVAL;
   381  break;
   382  }
   383  if (ret)
   384  return ret;
   385
   386  } else {
   387  index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
   388  powerplayinfo);
   389
   390  ret = smu_get_atom_data_table(smu, index, (uint16_t 
*), , ,
  
^
This only initializes the highest 16 bits.

   391(uint8_t **));
   392  if (ret)
   393  return ret;
   394  }
   395
   396  if (!smu->smu_table.power_play_table)
   397  smu->smu_table.power_play_table = table;
   398  if (!smu->smu_table.power_play_table_size)
   399  smu->smu_table.power_play_table_size = size;
   400
   401  return 0;

regards,
dan carpenter
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Re: [PATCH ARM] selftests, arm64: fix uninitialized symbol in tags_test.c

[Andrey Konovalov]

On Mon, Aug 19, 2019 at 5:03 PM Will Deacon  wrote:
>
> On Mon, Aug 19, 2019 at 03:14:42PM +0200, Andrey Konovalov wrote:
> > Fix tagged_ptr not being initialized when TBI is not enabled.
> >
> > Dan Carpenter 
>
> Guessing this was Reported-by, or has Dan introduced his own tag now? ;)

Oops, yes, Reported-by :)

>
> Got a link to the report?

https://www.spinics.net/lists/linux-kselftest/msg09446.html

>
> Will

Re: [PATCH v7 0/9] drm: cec: convert DRM drivers to the new notifier API

[Hans Verkuil]

On 8/19/19 4:48 PM, Neil Armstrong wrote:
> Hi Dariusz, Hans,
> 
> I can apply the dw-hdmi patches if necessary.

I'd appreciate it if you can do that.

Thanks,

Hans

> 
> Neil
> 
> On 19/08/2019 11:38, Hans Verkuil wrote:
>> Hi all,
>>
>> The patches in this series can be applied independently from each other.
>>
>> If you maintain one of these drivers and you want to merge it for v5.4
>> yourself, then please do so and let me know. If you prefer I commit it
>> to drm-misc, then please review and (hopefully) Ack the patch.
>>
>> I would really like to get this in for v5.4 so I can get the userspace
>> bits in for v5.4 as well through the media subsystem.
>>
>> Dariusz, can you post a v7.1 for patch 5/9 fixing the typo?
>>
>> Thanks!
>>
>>  Hans
>>
>> On 8/14/19 12:44 PM, Dariusz Marcinkiewicz wrote:
>>> This series updates DRM drivers to use new CEC notifier API.
>>>
>>> Changes since v6:
>>> Made CEC notifiers' registration and de-registration symmetric
>>> in tda998x and dw-hdmi drivers. Also, accidentally dropped one
>>> patch in v6 (change to drm_dp_cec), brought it back now.
>>> Changes since v5:
>>> Fixed a warning about a missing comment for a new member of
>>> drm_dp_aux_cec struct. Sending to a wider audience,
>>> including maintainers of respective drivers.
>>> Changes since v4:
>>> Addressing review comments.
>>> Changes since v3:
>>> Updated adapter flags in dw-hdmi-cec.
>>> Changes since v2:
>>> Include all DRM patches from "cec: improve notifier support,
>>> add connector info connector info" series.
>>> Changes since v1:
>>> Those patches delay creation of notifiers until respective
>>> connectors are constructed. It seems that those patches, for a
>>> couple of drivers, by adding the delay, introduce a race between
>>> notifiers' creation and the IRQs handling threads - at least I
>>> don't see anything obvious in there that would explicitly forbid
>>> such races to occur. v2 adds a write barrier to make sure IRQ
>>> threads see the notifier once it is created (replacing the
>>> WRITE_ONCE I put in v1). The best thing to do here, I believe,
>>> would be not to have any synchronization and make sure that an IRQ
>>> only gets enabled after the notifier is created.
>>> Dariusz Marcinkiewicz (9):
>>>   drm_dp_cec: add connector info support.
>>>   drm/i915/intel_hdmi: use cec_notifier_conn_(un)register
>>>   dw-hdmi-cec: use cec_notifier_cec_adap_(un)register
>>>   tda9950: use cec_notifier_cec_adap_(un)register
>>>   drm: tda998x: use cec_notifier_conn_(un)register
>>>   drm: sti: use cec_notifier_conn_(un)register
>>>   drm: tegra: use cec_notifier_conn_(un)register
>>>   drm: dw-hdmi: use cec_notifier_conn_(un)register
>>>   drm: exynos: exynos_hdmi: use cec_notifier_conn_(un)register
>>>
>>>  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  2 +-
>>>  drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 13 +++---
>>>  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 46 +--
>>>  drivers/gpu/drm/drm_dp_cec.c  | 25 ++
>>>  drivers/gpu/drm/exynos/exynos_hdmi.c  | 31 +++--
>>>  drivers/gpu/drm/i2c/tda9950.c | 12 ++---
>>>  drivers/gpu/drm/i2c/tda998x_drv.c | 36 ++-
>>>  drivers/gpu/drm/i915/display/intel_dp.c   |  4 +-
>>>  drivers/gpu/drm/i915/display/intel_hdmi.c | 13 --
>>>  drivers/gpu/drm/nouveau/nouveau_connector.c   |  3 +-
>>>  drivers/gpu/drm/sti/sti_hdmi.c| 19 +---
>>>  drivers/gpu/drm/tegra/output.c| 28 ---
>>>  include/drm/drm_dp_helper.h   | 17 ---
>>>  13 files changed, 155 insertions(+), 94 deletions(-)
>>>
>>
> 

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Re: [PATCH ARM] selftests, arm64: fix uninitialized symbol in tags_test.c

[Will Deacon]

On Mon, Aug 19, 2019 at 03:14:42PM +0200, Andrey Konovalov wrote:
> Fix tagged_ptr not being initialized when TBI is not enabled.
> 
> Dan Carpenter 

Guessing this was Reported-by, or has Dan introduced his own tag now? ;)

Got a link to the report?

Will
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Re: [PATCH v7 0/9] drm: cec: convert DRM drivers to the new notifier API

[Neil Armstrong]

Hi Dariusz, Hans,

I can apply the dw-hdmi patches if necessary.

Neil

On 19/08/2019 11:38, Hans Verkuil wrote:
> Hi all,
> 
> The patches in this series can be applied independently from each other.
> 
> If you maintain one of these drivers and you want to merge it for v5.4
> yourself, then please do so and let me know. If you prefer I commit it
> to drm-misc, then please review and (hopefully) Ack the patch.
> 
> I would really like to get this in for v5.4 so I can get the userspace
> bits in for v5.4 as well through the media subsystem.
> 
> Dariusz, can you post a v7.1 for patch 5/9 fixing the typo?
> 
> Thanks!
> 
>   Hans
> 
> On 8/14/19 12:44 PM, Dariusz Marcinkiewicz wrote:
>> This series updates DRM drivers to use new CEC notifier API.
>>
>> Changes since v6:
>>  Made CEC notifiers' registration and de-registration symmetric
>>  in tda998x and dw-hdmi drivers. Also, accidentally dropped one
>>  patch in v6 (change to drm_dp_cec), brought it back now.
>> Changes since v5:
>> Fixed a warning about a missing comment for a new member of
>>  drm_dp_aux_cec struct. Sending to a wider audience,
>>  including maintainers of respective drivers.
>> Changes since v4:
>>  Addressing review comments.
>> Changes since v3:
>> Updated adapter flags in dw-hdmi-cec.
>> Changes since v2:
>>  Include all DRM patches from "cec: improve notifier support,
>>  add connector info connector info" series.
>> Changes since v1:
>>  Those patches delay creation of notifiers until respective
>>  connectors are constructed. It seems that those patches, for a
>>  couple of drivers, by adding the delay, introduce a race between
>>  notifiers' creation and the IRQs handling threads - at least I
>>  don't see anything obvious in there that would explicitly forbid
>>  such races to occur. v2 adds a write barrier to make sure IRQ
>>  threads see the notifier once it is created (replacing the
>>  WRITE_ONCE I put in v1). The best thing to do here, I believe,
>>  would be not to have any synchronization and make sure that an IRQ
>>  only gets enabled after the notifier is created.
>> Dariusz Marcinkiewicz (9):
>>   drm_dp_cec: add connector info support.
>>   drm/i915/intel_hdmi: use cec_notifier_conn_(un)register
>>   dw-hdmi-cec: use cec_notifier_cec_adap_(un)register
>>   tda9950: use cec_notifier_cec_adap_(un)register
>>   drm: tda998x: use cec_notifier_conn_(un)register
>>   drm: sti: use cec_notifier_conn_(un)register
>>   drm: tegra: use cec_notifier_conn_(un)register
>>   drm: dw-hdmi: use cec_notifier_conn_(un)register
>>   drm: exynos: exynos_hdmi: use cec_notifier_conn_(un)register
>>
>>  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  2 +-
>>  drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 13 +++---
>>  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 46 +--
>>  drivers/gpu/drm/drm_dp_cec.c  | 25 ++
>>  drivers/gpu/drm/exynos/exynos_hdmi.c  | 31 +++--
>>  drivers/gpu/drm/i2c/tda9950.c | 12 ++---
>>  drivers/gpu/drm/i2c/tda998x_drv.c | 36 ++-
>>  drivers/gpu/drm/i915/display/intel_dp.c   |  4 +-
>>  drivers/gpu/drm/i915/display/intel_hdmi.c | 13 --
>>  drivers/gpu/drm/nouveau/nouveau_connector.c   |  3 +-
>>  drivers/gpu/drm/sti/sti_hdmi.c| 19 +---
>>  drivers/gpu/drm/tegra/output.c| 28 ---
>>  include/drm/drm_dp_helper.h   | 17 ---
>>  13 files changed, 155 insertions(+), 94 deletions(-)
>>
> 

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[PATCH 26/36] drm/amd/display: Enable HW rotation

[Bhawanpreet Lakha]

From: Jaehyun Chung 

[Why] HW rotation is not enabled. Calculations for cursor rotation
are wrong for the values passed to set_cursor_position.

[How] Swap Src rect and height and vertically mirror surface for
the correct surface rotation direction. Cursor position is rotated
according to angle. Offset calculations are tweaked for non-rotated
cursor hotspot and width/height.

Signed-off-by: Jaehyun Chung 
Reviewed-by: Jun Lei 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  | 13 +++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 34 +++
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 18 +++---
 3 files changed, 60 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 23b2361cec62..d8b2da18db39 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -457,6 +457,19 @@ void dpp1_set_cursor_position(
int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
uint32_t cur_en = pos->enable ? 1 : 0;
 
+   // Cursor width/height and hotspots need to be rotated for offset 
calculation
+   if (param->rotation == ROTATION_ANGLE_90 || param->rotation == 
ROTATION_ANGLE_270) {
+   swap(width, height);
+   if (param->rotation == ROTATION_ANGLE_90) {
+   src_x_offset = pos->x - pos->y_hotspot - 
param->viewport.x;
+   src_y_offset = pos->y - pos->x_hotspot - 
param->viewport.y;
+   }
+   } else if (param->rotation == ROTATION_ANGLE_180) {
+   src_x_offset = pos->x - param->viewport.x;
+   src_y_offset = pos->y - param->viewport.y;
+   }
+
+
if (src_x_offset >= (int)param->viewport.width)
cur_en = 0;  /* not visible beyond right edge*/
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index bfd402bede94..004675db686d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2975,6 +2975,40 @@ static void dcn10_set_cursor_position(struct pipe_ctx 
*pipe_ctx)
== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
pos_cpy.enable = false;
 
+   // Swap axis and mirror horizontally
+   if (param.rotation == ROTATION_ANGLE_90) {
+   uint32_t temp_x = pos_cpy.x;
+   pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -
+   (pos_cpy.y - 
pipe_ctx->plane_res.scl_data.viewport.x) + 
pipe_ctx->plane_res.scl_data.viewport.x;
+   pos_cpy.y = temp_x;
+   }
+   // Swap axis and mirror vertically
+   else if (param.rotation == ROTATION_ANGLE_270) {
+   uint32_t temp_y = pos_cpy.y;
+   if (pos_cpy.x >  pipe_ctx->plane_res.scl_data.viewport.height) {
+   pos_cpy.x = pos_cpy.x - 
pipe_ctx->plane_res.scl_data.viewport.height;
+   pos_cpy.y = 
pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
+   } else {
+   pos_cpy.y = 2 * 
pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
+   }
+   pos_cpy.x = temp_y;
+   }
+   // Mirror horizontally and vertically
+   else if (param.rotation == ROTATION_ANGLE_180) {
+   if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + 
pipe_ctx->plane_res.scl_data.viewport.x) {
+   pos_cpy.x = 2 * 
pipe_ctx->plane_res.scl_data.viewport.width
+   - pos_cpy.x + 2 * 
pipe_ctx->plane_res.scl_data.viewport.x;
+   } else {
+   uint32_t temp_x = pos_cpy.x;
+   pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x 
- pos_cpy.x;
+   if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + 
(int)hubp->curs_attr.width
+   || pos_cpy.x <= 
(int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) {
+   pos_cpy.x = temp_x + 
pipe_ctx->plane_res.scl_data.viewport.width;
+   }
+   }
+   pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - 
pos_cpy.y;
+   }
+
hubp->funcs->set_cursor_position(hubp, _cpy, );
dpp->funcs->set_cursor_position(dpp, _cpy, , 
hubp->curs_attr.width, hubp->curs_attr.height);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index b4b384c7fa9b..69e2aae42394 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -945,6 +945,8 @@ void hubp2_cursor_set_position(
int src_y_offset = pos->y - 

[PATCH 34/36] drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL

[Bhawanpreet Lakha]

From: Joshua Aberback 

[Why]
The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the
embedded display. Currently we do not actually read this register's values,
so during power down we think that this display is already off, so we skip
calling into VBIOS to actually turn it off.

[How]
 - add relevant fields to shift / mask initialization

Signed-off-by: Joshua Aberback 
Reviewed-by: Charlene Liu 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 43 ---
 1 file changed, 17 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index f62eb2e43d7f..7d93babaa2fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -416,36 +416,34 @@ struct dce_hwseq_registers {
HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, 
mask_sh),\
HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
 
+#define HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)\
+   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
+   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
+   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
+   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+
 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## 
mask_sh, \
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, 
mask_sh),\
HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
-   HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
+   HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
+   HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 
 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
-   HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+   HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
+   HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 
 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 
 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
 
 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
@@ -453,18 +451,15 @@ struct dce_hwseq_registers {
SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
-   SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+   SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
 
 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
-   HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+   HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh),\
+   HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 
 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\
HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\
@@ -527,10 +522,7 @@ struct dce_hwseq_registers {
HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+   HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
@@ -591,8 

[PATCH 32/36] drm/amd/display: Use res_cap to acquire i2c instead of pipe count

[Bhawanpreet Lakha]

From: Derek Lai 

[Why]
We should be using the ddc_num from res_caps. As the
pipe count != number of i2c resources.

[How]
Use ddc_num from res_cap instead of pipe count.

Signed-off-by: Derek Lai 
Reviewed-by: Charlene Liu 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index caace5229826..0495a1b5dd74 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -22,6 +22,7 @@
  * Authors: AMD
  *
  */
+#include "resource.h"
 #include "dce_i2c.h"
 #include "dce_i2c_hw.h"
 #include "reg_helper.h"
@@ -387,7 +388,7 @@ struct dce_i2c_hw *acquire_i2c_hw_engine(
if (ddc->hw_info.hw_supported) {
enum gpio_ddc_line line = dal_ddc_get_line(ddc);
 
-   if (line < pool->pipe_count)
+   if (line < pool->res_cap->num_ddc)
dce_i2c_hw = pool->hw_i2cs[line];
}
 
-- 
2.17.1

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[PATCH 30/36] drm/amd/display: fix DML not calculating delivery time

[Bhawanpreet Lakha]

From: Jun Lei 

[why]
Calculating DCFCLK DS time requires calculating
delivery time for luma/chroma, but this value is
not calculated in DMLv2, it was inadvertently
removed when porting DMLv2

[how]
Add the calculation back

Signed-off-by: Jun Lei 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
---
 .../dc/dml/dcn20/display_mode_vba_20v2.c  | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 22455db54980..0fafd693ffb4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -1475,6 +1475,33 @@ static void 
dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
/ 
mode_lib->vba.ReturnBW;
 
mode_lib->vba.LastPixelOfLineExtraWatermark = 0;
+   for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
+   if (mode_lib->vba.VRatio[k] <= 1.0)
+   
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
+   (double) 
mode_lib->vba.SwathWidthY[k]
+   * 
mode_lib->vba.DPPPerPlane[k]
+   / 
mode_lib->vba.HRatio[k]
+   / 
mode_lib->vba.PixelClock[k];
+   else
+   
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
+   (double) 
mode_lib->vba.SwathWidthY[k]
+   / 
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
+   / 
mode_lib->vba.DPPCLK[k];
+
+   if (mode_lib->vba.BytePerPixelDETC[k] == 0)
+   
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0;
+   else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0)
+   
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
+   mode_lib->vba.SwathWidthY[k] / 
2.0
+   * 
mode_lib->vba.DPPPerPlane[k]
+   / 
(mode_lib->vba.HRatio[k] / 2.0)
+   / 
mode_lib->vba.PixelClock[k];
+   else
+   
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
+   mode_lib->vba.SwathWidthY[k] / 
2.0
+   / 
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
+   / 
mode_lib->vba.DPPCLK[k];
+   }
 
mode_lib->vba.UrgentExtraLatency = 
mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency
+ (mode_lib->vba.TotalActiveDPP * 
mode_lib->vba.PixelChunkSizeInKByte
-- 
2.17.1

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[PATCH 23/36] drm/amd/display: fix odm stream release

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin 

Need to memset all odm pipes when calling dc_remove_stream_from_ctx

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 65 +--
 1 file changed, 32 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 953ba4d02a1e..6e88cb0fffce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -,13 +,12 @@ struct pipe_ctx *resource_get_head_pipe_for_stream(
struct dc_stream_state *stream)
 {
int i;
+
for (i = 0; i < MAX_PIPES; i++) {
if (res_ctx->pipe_ctx[i].stream == stream
&& !res_ctx->pipe_ctx[i].top_pipe
-   && !res_ctx->pipe_ctx[i].prev_odm_pipe) {
+   && !res_ctx->pipe_ctx[i].prev_odm_pipe)
return _ctx->pipe_ctx[i];
-   break;
-   }
}
return NULL;
 }
@@ -1694,45 +1693,45 @@ enum dc_status dc_remove_stream_from_ctx(
 {
int i;
struct dc_context *dc_ctx = dc->ctx;
-   struct pipe_ctx *del_pipe = NULL;
+   struct pipe_ctx *del_pipe = 
resource_get_head_pipe_for_stream(_ctx->res_ctx, stream);
+   struct pipe_ctx *odm_pipe;
 
-   /* Release primary pipe */
-   for (i = 0; i < MAX_PIPES; i++) {
-   if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
-   !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
-   del_pipe = _ctx->res_ctx.pipe_ctx[i];
+   if (!del_pipe) {
+   DC_ERROR("Pipe not found for stream %p !\n", stream);
+   return DC_ERROR_UNEXPECTED;
+   }
 
-   ASSERT(del_pipe->stream_res.stream_enc);
-   update_stream_engine_usage(
-   _ctx->res_ctx,
-   dc->res_pool,
-   del_pipe->stream_res.stream_enc,
-   false);
+   odm_pipe = del_pipe->next_odm_pipe;
 
-   if (del_pipe->stream_res.audio)
-   update_audio_usage(
-   _ctx->res_ctx,
-   dc->res_pool,
-   del_pipe->stream_res.audio,
-   false);
+   /* Release primary pipe */
+   ASSERT(del_pipe->stream_res.stream_enc);
+   update_stream_engine_usage(
+   _ctx->res_ctx,
+   dc->res_pool,
+   del_pipe->stream_res.stream_enc,
+   false);
 
-   resource_unreference_clock_source(_ctx->res_ctx,
- dc->res_pool,
- 
del_pipe->clock_source);
+   if (del_pipe->stream_res.audio)
+   update_audio_usage(
+   _ctx->res_ctx,
+   dc->res_pool,
+   del_pipe->stream_res.audio,
+   false);
 
-   if (dc->res_pool->funcs->remove_stream_from_ctx)
-   dc->res_pool->funcs->remove_stream_from_ctx(dc, 
new_ctx, stream);
+   resource_unreference_clock_source(_ctx->res_ctx,
+ dc->res_pool,
+ del_pipe->clock_source);
 
-   memset(del_pipe, 0, sizeof(*del_pipe));
+   if (dc->res_pool->funcs->remove_stream_from_ctx)
+   dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, 
stream);
 
-   break;
-   }
-   }
+   while (odm_pipe) {
+   struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
 
-   if (!del_pipe) {
-   DC_ERROR("Pipe not found for stream %p !\n", stream);
-   return DC_ERROR_UNEXPECTED;
+   memset(odm_pipe, 0, sizeof(*odm_pipe));
+   odm_pipe = next_odm_pipe;
}
+   memset(del_pipe, 0, sizeof(*del_pipe));
 
for (i = 0; i < new_ctx->stream_count; i++)
if (new_ctx->streams[i] == stream)
-- 
2.17.1

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[PATCH 36/36] drm/amd/display: 3.2.48

[Bhawanpreet Lakha]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 239cb0952c61..8ff595e66a6c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.47"
+#define DC_VER "3.2.48"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 33/36] drm/amd/display: revert wait in pipelock

[Bhawanpreet Lakha]

From: Jun Lei 

[why]
Previous workaround to prevent a vsync flip to be converted
to immediate flip is no longer needed, and is risky because
there are cases where it can result in infinite loop.

[how]
Remove wait loop (which is potentially infinite) before locking
pipe

Signed-off-by: Jun Lei 
Reviewed-by: Charlene Liu 
Reviewed-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 ---
 1 file changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fb7a244eafca..69d600183db8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1107,17 +1107,6 @@ void dcn20_pipe_control_lock(
if (pipe->plane_state != NULL)
flip_immediate = pipe->plane_state->flip_immediate;
 
-   if (flip_immediate && lock) {
-   while 
(pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp)) {
-   udelay(1);
-   }
-
-   if (pipe->bottom_pipe != NULL)
-   while 
(pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
   {
-   udelay(1);
-   }
-   }
-
/* In flip immediate and pipe splitting case, we need to use GSL
 * for synchronization. Only do setup on locking and on flip type 
change.
 */
-- 
2.17.1

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[PATCH 35/36] drm/amd/display: flicking observed while installing driver on Navi10 CF

[Bhawanpreet Lakha]

From: hersen wu 

[WHY] value of dchub_ref_clock is decided by dchubbub global timer
settings which is programmed by vbios command table disp_init.
for multi-GPU case, vbios is posted only for primary GPU. without
vbios posted for the secondary GPU, value of dchub_ref_clock is not
set properly. this value will affect dcn bandwidth calcuation and
cause underflow. user will see screen flicking during driver
installation for dual GPU case.

[HOW] dc init_hw always call vbios command table disp_init to
make sure dchubbub global timer is configured and enable.

Signed-off-by: hersen wu 
Reviewed-by: Jun Lei 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  1 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 54 +--
 2 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 6e88cb0fffce..adbf2d4e1723 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -169,6 +169,7 @@ struct resource_pool *dc_create_resource_pool(struct dc  
*dc,
default:
break;
}
+
if (res_pool != NULL) {
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 3272da955b6d..5b9dd169a16f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1208,34 +1208,34 @@ static void dcn10_init_hw(struct dc *dc)
return;
}
 
-   if (!dcb->funcs->is_accelerated_mode(dcb)) {
-   dc->hwss.bios_golden_init(dc);
-   if (dc->ctx->dc_bios->fw_info_valid) {
-   res_pool->ref_clocks.xtalin_clock_inKhz =
-   
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
-
-   if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-   if (res_pool->dccg && res_pool->hubbub) {
-
-   
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
-   
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
-   
_pool->ref_clocks.dccg_ref_clock_inKhz);
-
-   
(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
-   
res_pool->ref_clocks.dccg_ref_clock_inKhz,
-   
_pool->ref_clocks.dchub_ref_clock_inKhz);
-   } else {
-   // Not all ASICs have DCCG sw component
-   
res_pool->ref_clocks.dccg_ref_clock_inKhz =
-   
res_pool->ref_clocks.xtalin_clock_inKhz;
-   
res_pool->ref_clocks.dchub_ref_clock_inKhz =
-   
res_pool->ref_clocks.xtalin_clock_inKhz;
-   }
-   }
-   } else
-   ASSERT_CRITICAL(false);
+   if (!dcb->funcs->is_accelerated_mode(dcb))
dc->hwss.disable_vga(dc->hwseq);
-   }
+
+   dc->hwss.bios_golden_init(dc);
+   if (dc->ctx->dc_bios->fw_info_valid) {
+   res_pool->ref_clocks.xtalin_clock_inKhz =
+   
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+
+   if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+   if (res_pool->dccg && res_pool->hubbub) {
+
+   
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+   
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+   
_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+   
(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+   
res_pool->ref_clocks.dccg_ref_clock_inKhz,
+   
_pool->ref_clocks.dchub_ref_clock_inKhz);
+   } else {
+   // Not all ASICs have DCCG sw component
+   res_pool->ref_clocks.dccg_ref_clock_inKhz =
+   
res_pool->ref_clocks.xtalin_clock_inKhz;
+   res_pool->ref_clocks.dchub_ref_clock_inKhz =
+   
res_pool->ref_clocks.xtalin_clock_inKhz;
+   }

[PATCH 29/36] drm/amd/display: MST topology debugfs

[Bhawanpreet Lakha]

From: David Francis 

DRM provides drm_dp_mst_dump_topology, which prints
useful information about MST devices

Hook this up to a debugfs file named amdgpu_mst_topology

Signed-off-by: David Francis 
Acked-by: Bhawanpreet Lakha 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 24 +++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 406129e67e79..97bbb934cc04 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1051,9 +1051,33 @@ static int target_backlight_read(struct seq_file *m, 
void *data)
return 0;
 }
 
+static int mst_topo(struct seq_file *m, void *unused)
+{
+   struct drm_info_node *node = (struct drm_info_node *)m->private;
+   struct drm_device *dev = node->minor->dev;
+   struct drm_connector *connector;
+   struct drm_connector_list_iter conn_iter;
+   struct amdgpu_dm_connector *aconnector;
+
+   drm_connector_list_iter_begin(dev, _iter);
+   drm_for_each_connector_iter(connector, _iter) {
+   if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+   continue;
+
+   aconnector = to_amdgpu_dm_connector(connector);
+
+   seq_printf(m, "\nMST topology for connector %d\n", 
aconnector->connector_id);
+   drm_dp_mst_dump_topology(m, >mst_mgr);
+   }
+   drm_connector_list_iter_end(_iter);
+
+   return 0;
+}
+
 static const struct drm_info_list amdgpu_dm_debugfs_list[] = {
{"amdgpu_current_backlight_pwm", _backlight_read},
{"amdgpu_target_backlight_pwm", _backlight_read},
+   {"amdgpu_mst_topology", _topo},
 };
 
 /*
-- 
2.17.1

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[PATCH 24/36] drm/amd/display: fix odm validation

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin 

Update bw validation to use prev and next odm pipe pointers
for populating dml inputs.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 40 +--
 1 file changed, 19 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index aa1342ccf8b4..477885816854 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1600,12 +1600,8 @@ static bool dcn20_split_stream_for_odm(
struct pipe_ctx *next_odm_pipe)
 {
int pipe_idx = next_odm_pipe->pipe_idx;
-   struct scaler_data *sd = _odm_pipe->plane_res.scl_data;
-   struct pipe_ctx *sec_next_pipe = next_odm_pipe->next_odm_pipe;
-   int new_width;
 
*next_odm_pipe = *prev_odm_pipe;
-   next_odm_pipe->next_odm_pipe = sec_next_pipe;
 
next_odm_pipe->pipe_idx = pipe_idx;
next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
@@ -1627,11 +1623,11 @@ static bool dcn20_split_stream_for_odm(
ASSERT(next_odm_pipe->top_pipe == NULL);
 
if (prev_odm_pipe->plane_state) {
+   struct scaler_data *sd = _odm_pipe->plane_res.scl_data;
+   int new_width;
+
/* HACTIVE halved for odm combine */
sd->h_active /= 2;
-   /* Copy scl_data to secondary pipe */
-   next_odm_pipe->plane_res.scl_data = *sd;
-
/* Calculate new vp and recout for left pipe */
/* Need at least 16 pixels width per side */
if (sd->recout.x + 16 >= sd->h_active)
@@ -1645,10 +1641,12 @@ static bool dcn20_split_stream_for_odm(
 
/* Calculate new vp and recout for right pipe */
sd = _odm_pipe->plane_res.scl_data;
-   new_width = sd->recout.width + sd->recout.x - sd->h_active;
+   /* HACTIVE halved for odm combine */
+   sd->h_active /= 2;
/* Need at least 16 pixels width per side */
if (new_width <= 16)
return false;
+   new_width = sd->recout.width + sd->recout.x - sd->h_active;
sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
sd->ratios.horz, sd->recout.width - new_width));
sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
@@ -1818,6 +1816,19 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].dout.dp_lanes = 4;
pipes[pipe_cnt].pipe.dest.vtotal_min = 
res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
pipes[pipe_cnt].pipe.dest.vtotal_max = 
res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
+   pipes[pipe_cnt].pipe.dest.odm_combine = 
res_ctx->pipe_ctx[i].prev_odm_pipe
+   || 
res_ctx->pipe_ctx[i].next_odm_pipe;
+   pipes[pipe_cnt].pipe.src.hsplit_grp = 
res_ctx->pipe_ctx[i].pipe_idx;
+   if (res_ctx->pipe_ctx[i].top_pipe && 
res_ctx->pipe_ctx[i].top_pipe->plane_state
+   == res_ctx->pipe_ctx[i].plane_state)
+   pipes[pipe_cnt].pipe.src.hsplit_grp = 
res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
+   else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
+   struct pipe_ctx *first_pipe = 
res_ctx->pipe_ctx[i].prev_odm_pipe;
+
+   while (first_pipe->prev_odm_pipe)
+   first_pipe = first_pipe->prev_odm_pipe;
+   pipes[pipe_cnt].pipe.src.hsplit_grp = 
first_pipe->pipe_idx;
+   }
 
switch (res_ctx->pipe_ctx[i].stream->signal) {
case SIGNAL_TYPE_DISPLAY_PORT_MST:
@@ -1870,7 +1881,6 @@ int dcn20_populate_dml_pipes_from_context(
break;
}
 
-
switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
case PIXEL_ENCODING_RGB:
case PIXEL_ENCODING_YCBCR444:
@@ -1892,10 +1902,6 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].dout.output_format = dm_444;
pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
}
-   pipes[pipe_cnt].pipe.src.hsplit_grp = 
res_ctx->pipe_ctx[i].pipe_idx;
-   if (res_ctx->pipe_ctx[i].top_pipe && 
res_ctx->pipe_ctx[i].top_pipe->plane_state
-   == res_ctx->pipe_ctx[i].plane_state)
-   pipes[pipe_cnt].pipe.src.hsplit_grp = 
res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
 
/* todo: default max for now, until there is logic reflecting 
this in dc*/
pipes[pipe_cnt].dout.output_bpc = 12;
@@ -1944,14 +1950,6 @@ int 

[PATCH 28/36] drm/amd/display: set av_mute in hw_init for HDMI

[Bhawanpreet Lakha]

From: Charlene Liu 

[Description]
OS will reserve HW state in UEFI mode.
Driver init_hw reset to RGB which caused HDMI green in YCbCr mode.
read HW blank_color based on acc_mode.

Signed-off-by: Charlene Liu 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
---
 .../amd/display/dc/dcn10/dcn10_link_encoder.c | 23 +++
 .../amd/display/dc/dcn10/dcn10_link_encoder.h |  2 ++
 .../amd/display/dc/dcn20/dcn20_link_encoder.c |  1 +
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  2 ++
 4 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index e4c7ecd87de7..4034f7787a35 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -86,6 +86,7 @@ static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
.disable_hpd = dcn10_link_encoder_disable_hpd,
.is_dig_enabled = dcn10_is_dig_enabled,
.get_dig_frontend = dcn10_get_dig_frontend,
+   .get_dig_mode = dcn10_get_dig_mode,
.destroy = dcn10_link_encoder_destroy
 };
 
@@ -1394,3 +1395,25 @@ void dcn10_aux_initialize(struct dcn10_link_encoder 
*enc10)
AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
AUX_RX_RECEIVE_WINDOW, 0);
 }
+
+enum signal_type dcn10_get_dig_mode(
+   struct link_encoder *enc)
+{
+   struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+   uint32_t value;
+   REG_GET(DIG_BE_CNTL, DIG_MODE, );
+   switch (value) {
+   case 1:
+   return SIGNAL_TYPE_DISPLAY_PORT;
+   case 2:
+   return SIGNAL_TYPE_DVI_SINGLE_LINK;
+   case 3:
+   return SIGNAL_TYPE_HDMI_TYPE_A;
+   case 5:
+   return SIGNAL_TYPE_DISPLAY_PORT_MST;
+   default:
+   return SIGNAL_TYPE_NONE;
+   }
+   return SIGNAL_TYPE_NONE;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index f3e57343417c..8bf5f0f2301d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -515,4 +515,6 @@ unsigned int dcn10_get_dig_frontend(struct link_encoder 
*enc);
 
 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
 
+enum signal_type dcn10_get_dig_mode(
+   struct link_encoder *enc);
 #endif /* __DC_LINK_ENCODER__DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
index f495582e9e87..e476f27aa3a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
@@ -341,6 +341,7 @@ static const struct link_encoder_funcs dcn20_link_enc_funcs 
= {
.fec_set_enable = enc2_fec_set_enable,
.fec_set_ready = enc2_fec_set_ready,
.fec_is_active = enc2_fec_is_active,
+   .get_dig_mode = dcn10_get_dig_mode,
.get_dig_frontend = dcn10_get_dig_frontend,
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 7001bfbd6681..abb4e4237fb6 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -184,6 +184,8 @@ struct link_encoder_funcs {
bool (*fec_is_active)(struct link_encoder *enc);
 #endif
bool (*is_in_alt_mode) (struct link_encoder *enc);
+   enum signal_type (*get_dig_mode)(
+   struct link_encoder *enc);
 };
 
 #endif /* LINK_ENCODER_H_ */
-- 
2.17.1

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[PATCH 12/36] drm/amd/display: Add VM page fault handle implementation

[Bhawanpreet Lakha]

From: Jaehyun Chung 

[How] Allocate memory for default page and program memory block addr
into default page addr register.

Signed-off-by: Jaehyun Chung 
Reviewed-by: Jun Lei 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h | 6 +-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 5 +
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 9 +++--
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c  | 1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h| 2 ++
 6 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3ef269f82478..6ee82ec6e28a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -423,6 +423,7 @@ struct dc_phy_addr_space_config {
} gart_config;
 
bool valid;
+   uint64_t page_table_default_page_addr;
 };
 
 struct dc_virtual_addr_space_config {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index 70e5d84fc69a..c8ae3023fda2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -119,6 +119,8 @@ struct dcn_hubbub_registers {
uint32_t DCN_VM_AGP_BOT;
uint32_t DCN_VM_AGP_TOP;
uint32_t DCN_VM_AGP_BASE;
+   uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
+   uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
 };
 
 /* set field name */
@@ -196,7 +198,9 @@ struct dcn_hubbub_registers {
type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
-   type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
+   type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
+   type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
+   type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB
 
 #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \
type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index f13e039f8ef4..b83c022e2c6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -380,6 +380,11 @@ int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
REG_SET(DCN_VM_AGP_BASE, 0,
AGP_BASE, pa_config->system_aperture.agp_base >> 24);
 
+   REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
+   DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 
(pa_config->page_table_default_page_addr >> 44) & 0xF);
+   REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
+   DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 
(pa_config->page_table_default_page_addr >> 12) & 0x);
+
if (pa_config->gart_config.page_table_start_addr != 
pa_config->gart_config.page_table_end_addr) {
phys_config.page_table_start_addr = 
pa_config->gart_config.page_table_start_addr >> 12;
phys_config.page_table_end_addr = 
pa_config->gart_config.page_table_end_addr >> 12;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
index caf7273ca240..0d0caa6de935 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
@@ -45,7 +45,10 @@
 #define HUBBUB_REG_LIST_DCN20(id)\
HUBBUB_REG_LIST_DCN20_COMMON(), \
HUBBUB_SR_WATERMARK_REG_LIST(), \
-   HUBBUB_VM_REG_LIST()
+   HUBBUB_VM_REG_LIST(),\
+   SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB),\
+   SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB)
+
 
 #define HUBBUB_MASK_SH_LIST_DCN20(mask_sh)\
HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
@@ -56,7 +59,9 @@
HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
-   HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
+   HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
+   HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 
DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \
+   HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 
DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh)
 
 struct dcn20_hubbub {
struct hubbub base;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 87ba8efc51ab..4a74a4fb3ab9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1508,6 +1508,7 @@ static int dcn20_init_sys_ctx(struct 

[PATCH 25/36] drm/amd/display: add Cursor Degamma logic for DCN2

[Bhawanpreet Lakha]

From: Bayan Zabihiyan 

[Why]
We need to have the ability to to tell us set degamma on the cursor.

[How]
Pass a flag down to register programming that tells us if the
current surface format needs cursor degamma.

Signed-off-by: Bayan Zabihiyan 
Reviewed-by: Krunoslav Kovac 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h   |  3 ++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |  3 ++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |  2 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c   | 10 +++---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h   |  2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h|  2 +-
 7 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 929c4eadc1dc..f35826d5d1e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -516,7 +516,8 @@ union dc_cursor_attribute_flags {
uint32_t INVERT_PIXEL_DATA:1;
uint32_t ZERO_EXPANSION:1;
uint32_t MIN_MAX_INVERT:1;
-   uint32_t RESERVED:25;
+   uint32_t ENABLE_CURSOR_DEGAMMA:1;
+   uint32_t RESERVED:24;
} bits;
uint32_t value;
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index b95ec73fcae3..23b2361cec62 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -426,8 +426,9 @@ void dpp1_cnv_setup (
 
 void dpp1_set_cursor_attributes(
struct dpp *dpp_base,
-   enum dc_cursor_color_format color_format)
+   struct dc_cursor_attributes *cursor_attributes)
 {
+   enum dc_cursor_color_format color_format = 
cursor_attributes->color_format;
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
 
REG_UPDATE_2(CURSOR0_CONTROL,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 8a5517eebb7c..e2c613611ac9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1368,7 +1368,7 @@ enum dcn10_input_csc_select {
 
 void dpp1_set_cursor_attributes(
struct dpp *dpp_base,
-   enum dc_cursor_color_format color_format);
+   struct dc_cursor_attributes *cursor_attributes);
 
 void dpp1_set_cursor_position(
struct dpp *dpp_base,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d9ce06b1d9c0..bfd402bede94 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2986,7 +2986,7 @@ static void dcn10_set_cursor_attribute(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
pipe_ctx->plane_res.hubp, attributes);
pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
-   pipe_ctx->plane_res.dpp, attributes->color_format);
+   pipe_ctx->plane_res.dpp, attributes);
 }
 
 static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index db311574f42f..2f5aade1e882 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -342,14 +342,18 @@ void dpp2_cnv_set_alpha_keyer(
 
 void dpp2_set_cursor_attributes(
struct dpp *dpp_base,
-   enum dc_cursor_color_format color_format)
+   struct dc_cursor_attributes *cursor_attributes)
 {
+   enum dc_cursor_color_format color_format = 
cursor_attributes->color_format;
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
int cur_rom_en = 0;
 
if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
-   color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
-   cur_rom_en = 1;
+   color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
+   if 
(cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
+   cur_rom_en = 1;
+   }
+   }
 
REG_UPDATE_3(CURSOR0_CONTROL,
CUR0_MODE, color_format,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
index 1f5d99a6d240..290b2854bd2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
@@ -676,7 +676,7 @@ void dscl2_calc_lb_num_partitions(
 
 void 

[PATCH 27/36] drm/amd/display: Add Logging for Gamma Related information

[Bhawanpreet Lakha]

From: Wyatt Wood 

[Why]
A recent bug showed that logging would be useful in debugging
various gamma issues.

[How]
Add logging in dc.
Fix formatting for easier graphing.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 12 ++--
 .../gpu/drm/amd/display/modules/color/color_gamma.c  |  4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 004675db686d..0e7d929c254c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1451,15 +1451,15 @@ static void log_tf(struct dc_context *ctx,
DC_LOG_ALL_TF_CHANNELS("Logging all channels...");
 
for (i = 0; i < hw_points_num; i++) {
-   DC_LOG_GAMMA("R %d %llu\n", i, tf->tf_pts.red[i].value);
-   DC_LOG_ALL_TF_CHANNELS("G %d, %llu\n", i, 
tf->tf_pts.green[i].value);
-   DC_LOG_ALL_TF_CHANNELS("B %d, %llu\n", i, 
tf->tf_pts.blue[i].value);
+   DC_LOG_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value);
+   DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, 
tf->tf_pts.green[i].value);
+   DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, 
tf->tf_pts.blue[i].value);
}
 
for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) {
-   DC_LOG_ALL_GAMMA("R %d %llu\n", i, tf->tf_pts.red[i].value);
-   DC_LOG_ALL_TF_CHANNELS("G %d %llu\n", i, 
tf->tf_pts.green[i].value);
-   DC_LOG_ALL_TF_CHANNELS("B %d %llu\n", i, 
tf->tf_pts.blue[i].value);
+   DC_LOG_ALL_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value);
+   DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, 
tf->tf_pts.green[i].value);
+   DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, 
tf->tf_pts.blue[i].value);
}
 }
 
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 8f78ea226dae..19475cf5ab72 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -99,10 +99,10 @@ void log_x_points_distribution(struct dal_logger *logger)
int i = 0;
 
if (logger != NULL) {
-   LOG_GAMMA_WRITE("]Log X Distribution\n");
+   LOG_GAMMA_WRITE("Log X Distribution\n");
 
for (i = 0; i < MAX_HW_POINTS; i++)
-   LOG_GAMMA_WRITE("]%llu\n", coordinates_x[i].x.value);
+   LOG_GAMMA_WRITE("%llu\n", coordinates_x[i].x.value);
}
 }
 
-- 
2.17.1

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[PATCH 22/36] drm/amd/display: fix dcn20 odm dpp programming

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin 

dcn20 requires special casing for odm.
This change treats odm as alternative to mpc tree on dcn20.

This is planned to be fixed in a future refactor

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 1 +
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 ++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e09c639685fc..ac55644247ca 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2023,6 +2023,7 @@ static void commit_planes_for_stream(struct dc *dc,
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
 
if (!pipe_ctx->top_pipe &&
+   !pipe_ctx->prev_odm_pipe &&
pipe_ctx->stream &&
pipe_ctx->stream == stream) {
struct dc_stream_status *stream_status = NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 31a985858bae..99733e1a8958 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1058,8 +1058,13 @@ static void dcn20_program_all_pipe_in_tree(
if (pipe_ctx->plane_state != NULL)
dcn20_program_pipe(dc, pipe_ctx, context);
 
-   if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
+   if (pipe_ctx->bottom_pipe != NULL) {
+   ASSERT(pipe_ctx->bottom_pipe != pipe_ctx);
dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, 
context);
+   } else if (pipe_ctx->next_odm_pipe != NULL) {
+   ASSERT(pipe_ctx->next_odm_pipe != pipe_ctx);
+   dcn20_program_all_pipe_in_tree(dc, pipe_ctx->next_odm_pipe, 
context);
+   }
 }
 
 void dcn20_pipe_control_lock_global(
-- 
2.17.1

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[PATCH 19/36] drm/amd/display: fix trigger not generated for freesync

[Bhawanpreet Lakha]

From: Yogesh Mohan Marimuthu 

[Why]
In newer hardware MANUAL_FLOW_CONTROL is not a trigger bit. Due to this
front porch is fixed and in these hardware freesync does not work.

[How]
Change the programming to generate a pulse so that the event will be
triggered, front porch will be cut short and freesync will work.

Signed-off-by: Yogesh Mohan Marimuthu 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index e5e5be63032b..e98e6bab4808 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -825,6 +825,9 @@ void optc1_program_manual_trigger(struct timing_generator 
*optc)
 
REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
MANUAL_FLOW_CONTROL, 1);
+
+   REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
+   MANUAL_FLOW_CONTROL, 0);
 }
 
 
-- 
2.17.1

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[PATCH 31/36] drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags

[Bhawanpreet Lakha]

From: Bayan Zabihiyan 

[Why]
Existing HW Features, HW Diags test requested that the
registers be exposed.

[How]
Add V_TOTAL_MID to existing DC structures.
Make sure values are passed down throughout DC
Add Register definition.
Program the additional registers
Add additional Logic for V_TOTAL_CONTROL.

Signed-off-by: Bayan Zabihiyan 
Reviewed-by: Charlene Liu 
Acked-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c |  4 +++-
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h |  2 ++
 .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c  |  3 ++-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c|  5 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c| 12 
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h|  8 
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c   |  2 ++
 .../gpu/drm/amd/display/dc/inc/hw/timing_generator.h |  2 ++
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h|  3 ++-
 9 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ac55644247ca..6904f1591ada 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -288,7 +288,9 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
dc->hwss.set_drr(,
1,
adjust->v_total_min,
-   adjust->v_total_max);
+   adjust->v_total_max,
+   adjust->v_total_mid,
+   adjust->v_total_mid_frame_num);
 
ret = true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index f35826d5d1e5..0b8700a8a94a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -757,6 +757,8 @@ struct crtc_trigger_info {
 struct dc_crtc_timing_adjust {
uint32_t v_total_min;
uint32_t v_total_max;
+   uint32_t v_total_mid;
+   uint32_t v_total_mid_frame_num;
 };
 
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index c2d026ba269f..c273490ddcab 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1716,7 +1716,8 @@ void dce110_set_safe_displaymarks(
  
**/
 
 static void set_drr(struct pipe_ctx **pipe_ctx,
-   int num_pipes, int vmin, int vmax)
+   int num_pipes, unsigned int vmin, unsigned int vmax,
+   unsigned int vmid, unsigned int vmid_frame_number)
 {
int i = 0;
struct drr_params params = {0};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0e7d929c254c..3272da955b6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2746,7 +2746,8 @@ static void dcn10_optimize_bandwidth(
 }
 
 static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
-   int num_pipes, int vmin, int vmax)
+   int num_pipes, unsigned int vmin, unsigned int vmax,
+   unsigned int vmid, unsigned int vmid_frame_number)
 {
int i = 0;
struct drr_params params = {0};
@@ -2755,6 +2756,8 @@ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
 
params.vertical_total_max = vmax;
params.vertical_total_min = vmin;
+   params.vertical_total_mid = vmid;
+   params.vertical_total_mid_frame_num = vmid_frame_number;
 
/* TODO: If multiple pipes are to be supported, you need
 * some GSL stuff. Static screen triggers may be programmed differently
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index e98e6bab4808..e74a07d03fde 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -850,6 +850,18 @@ void optc1_set_drr(
params->vertical_total_max > 0 &&
params->vertical_total_min > 0) {
 
+   if (params->vertical_total_mid != 0) {
+
+   REG_SET(OTG_V_TOTAL_MID, 0,
+   OTG_V_TOTAL_MID, params->vertical_total_mid - 
1);
+
+   REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
+   OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
+   OTG_VTOTAL_MID_FRAME_NUM,
+   

[PATCH 21/36] drm/amd/display: Fix number of slices not being checked for dsc

[Bhawanpreet Lakha]

From: Nikola Cornij 

[why]
num_slices_h was not being checked

[How]
Fix the typo and check num_slices_h

Signed-off-by: Nikola Cornij 
Reviewed-by: Harry Wentland 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index c4f861e6bd53..1b419407af94 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -322,7 +322,7 @@ static bool dsc_prepare_config(const struct dsc_config 
*dsc_cfg, struct dsc_reg_
dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));
ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && 
dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 
63.9375
 
-   if (!dsc_cfg->dc_dsc_cfg.num_slices_v || 
!dsc_cfg->dc_dsc_cfg.num_slices_v ||
+   if (!dsc_cfg->dc_dsc_cfg.num_slices_v || 
!dsc_cfg->dc_dsc_cfg.num_slices_h ||
!(dsc_cfg->dc_dsc_cfg.version_minor == 1 || 
dsc_cfg->dc_dsc_cfg.version_minor == 2) ||
!dsc_cfg->pic_width || !dsc_cfg->pic_height ||
!((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line 
buffer depth range:
-- 
2.17.1

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[PATCH 17/36] drm/amd/display: support spdif

[Bhawanpreet Lakha]

From: Charlene Liu 

[Description]
port spdif fix to staging:
 spdif hardwired to afmt inst 1.
 spdif func pointer
 spdif resource allocation (reserve last audio endpoint for spdif only)

Signed-off-by: Charlene Liu 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c   | 17 -
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c  |  4 ++--
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 1464f4c60089..953ba4d02a1e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -259,12 +259,10 @@ bool resource_construct(
DC_ERR("DC: failed to create audio!\n");
return false;
}
-
if (!aud->funcs->endpoint_valid(aud)) {
aud->funcs->destroy();
break;
}
-
pool->audios[i] = aud;
pool->audio_count++;
}
@@ -1618,24 +1616,25 @@ static struct audio *find_first_free_audio(
const struct resource_pool *pool,
enum engine_id id)
 {
-   int i;
-   for (i = 0; i < pool->audio_count; i++) {
+   int i, available_audio_count;
+
+   available_audio_count = pool->audio_count;
+
+   for (i = 0; i < available_audio_count; i++) {
if ((res_ctx->is_audio_acquired[i] == false) && 
(res_ctx->is_stream_enc_acquired[i] == true)) {
/*we have enough audio endpoint, find the matching 
inst*/
if (id != i)
continue;
-
return pool->audios[i];
}
}
 
-/* use engine id to find free audio */
-   if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == 
false)) {
+   /* use engine id to find free audio */
+   if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == 
false)) {
return pool->audios[id];
}
-
/*not found the matching one, first come first serve*/
-   for (i = 0; i < pool->audio_count; i++) {
+   for (i = 0; i < available_audio_count; i++) {
if (res_ctx->is_audio_acquired[i] == false) {
return pool->audios[i];
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index b7d63ca126df..bdcc3c8a6a91 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -611,6 +611,8 @@ void dce_aud_az_configure(
 
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
value);
+   DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, 
displayName %s: \n",
+   audio->inst, value, audio_info->display_name);
 
/*
*write the port ID:
@@ -920,7 +922,6 @@ static const struct audio_funcs funcs = {
.az_configure = dce_aud_az_configure,
.destroy = dce_aud_destroy,
 };
-
 void dce_aud_destroy(struct audio **audio)
 {
struct dce_audio *aud = DCE_AUD(*audio);
@@ -951,7 +952,6 @@ struct audio *dce_audio_create(
audio->regs = reg;
audio->shifts = shifts;
audio->masks = masks;
-
return >base;
 }
 
-- 
2.17.1

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[PATCH 13/36] drm/amd/display: cleaned up coding error in init_hw

[Bhawanpreet Lakha]

From: Martin Leung 

[why]
during a refactor a redundant code that has unknown behaviour was added.

[how]
removed old bad code

Fixes:  7b0b6ee982ab018ecce70f661e676d059bfe8270
drm/amd/display: Make init_hw and init_pipes generic for seamless boot

Signed-off-by: Martin Leung 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 11 ---
 1 file changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0e55df3db53c..d9ce06b1d9c0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1267,19 +1267,8 @@ static void dcn10_init_hw(struct dc *dc)
 */
if (dcb->funcs->is_accelerated_mode(dcb) || 
dc->config.power_down_display_on_boot) {
dc->hwss.init_pipes(dc, dc->current_state);
-   for (i = 0; i < res_pool->pipe_count; i++) {
-   struct hubp *hubp = res_pool->hubps[i];
-   struct dpp *dpp = res_pool->dpps[i];
-
-   hubp->funcs->hubp_init(hubp);
-   res_pool->opps[i]->mpc_tree_params.opp_id = 
res_pool->opps[i]->inst;
-   dc->hwss.plane_atomic_power_down(dc, dpp, hubp);
-   }
-
-   apply_DEGVIDCN10_253_wa(dc);
}
 
-
for (i = 0; i < res_pool->audio_count; i++) {
struct audio *audio = res_pool->audios[i];
 
-- 
2.17.1

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[PATCH 15/36] drm/amd/display: 3.2.47

[Bhawanpreet Lakha]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 6ee82ec6e28a..239cb0952c61 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.46"
+#define DC_VER "3.2.47"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 16/36] drm/amd/display: Refactoring VTEM

[Bhawanpreet Lakha]

From: Ahmad Othman 

[Why]
Video Timing Extended Metadata packet (VTEM) is not
specific to freesync. So move it out of freesync module

[How]
- Moved VTEM from freesync module to info_packet module
- Created new structure for VTEM parameters that can be used for VRR
and FVA

Signed-off-by: Ahmad Othman 
Reviewed-by: Chris Park 
Acked-by: Ahmad Othman 
Acked-by: Bhawanpreet Lakha 
---
 .../amd/display/modules/freesync/freesync.c   | 276 --
 .../amd/display/modules/inc/mod_freesync.h|   2 +
 .../amd/display/modules/inc/mod_info_packet.h |   2 +-
 .../display/modules/info_packet/info_packet.c |  88 ++
 4 files changed, 148 insertions(+), 220 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 000a9db9dad8..107d81ea689b 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -50,93 +50,6 @@ struct core_freesync {
struct dc *dc;
 };
 
-void setFieldWithMask(unsigned char *dest, unsigned int mask, unsigned int 
value)
-{
-   unsigned int shift = 0;
-
-   if (!mask || !dest)
-   return;
-
-   while (!((mask >> shift) & 1))
-   shift++;
-
-   //reset
-   *dest = *dest & ~mask;
-   //set
-   //dont let value span past mask
-   value = value & (mask >> shift);
-   //insert value
-   *dest = *dest | (value << shift);
-}
-
-// VTEM Byte Offset
-#define VRR_VTEM_PB0   0
-#define VRR_VTEM_PB1   1
-#define VRR_VTEM_PB2   2
-#define VRR_VTEM_PB3   3
-#define VRR_VTEM_PB4   4
-#define VRR_VTEM_PB5   5
-#define VRR_VTEM_PB6   6
-
-#define VRR_VTEM_MD0   7
-#define VRR_VTEM_MD1   8
-#define VRR_VTEM_MD2   9
-#define VRR_VTEM_MD3   10
-
-
-// VTEM Byte Masks
-//PB0
-#define MASK__VRR_VTEM_PB0__RESERVED0  0x01
-#define MASK__VRR_VTEM_PB0__SYNC   0x02
-#define MASK__VRR_VTEM_PB0__VFR0x04
-#define MASK__VRR_VTEM_PB0__AFR0x08
-#define MASK__VRR_VTEM_PB0__DS_TYPE0x30
-   //0: Periodic pseudo-static EM Data Set
-   //1: Periodic dynamic EM Data Set
-   //2: Unique EM Data Set
-   //3: Reserved
-#define MASK__VRR_VTEM_PB0__END0x40
-#define MASK__VRR_VTEM_PB0__NEW0x80
-
-//PB1
-#define MASK__VRR_VTEM_PB1__RESERVED1 0xFF
-
-//PB2
-#define MASK__VRR_VTEM_PB2__ORGANIZATION_ID 0xFF
-   //0: This is a Vendor Specific EM Data Set
-   //1: This EM Data Set is defined by This Specification (HDMI 2.1 
r102.clean)
-   //2: This EM Data Set is defined by CTA-861-G
-   //3: This EM Data Set is defined by VESA
-//PB3
-#define MASK__VRR_VTEM_PB3__DATA_SET_TAG_MSB0xFF
-//PB4
-#define MASK__VRR_VTEM_PB4__DATA_SET_TAG_LSB0xFF
-//PB5
-#define MASK__VRR_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF
-//PB6
-#define MASK__VRR_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF
-
-
-
-//PB7-27 (20 bytes):
-//PB7 = MD0
-#define MASK__VRR_VTEM_MD0__VRR_EN 0x01
-#define MASK__VRR_VTEM_MD0__M_CONST0x02
-#define MASK__VRR_VTEM_MD0__RESERVED2  0x0C
-#define MASK__VRR_VTEM_MD0__FVA_FACTOR_M1  0xF0
-
-//MD1
-#define MASK__VRR_VTEM_MD1__BASE_VFRONT0xFF
-
-//MD2
-#define MASK__VRR_VTEM_MD2__BASE_REFRESH_RATE_98  0x03
-#define MASK__VRR_VTEM_MD2__RB0x04
-#define MASK__VRR_VTEM_MD2__RESERVED3 0xF8
-
-//MD3
-#define MASK__VRR_VTEM_MD3__BASE_REFRESH_RATE_07  0xFF
-
-
 #define MOD_FREESYNC_TO_CORE(mod_freesync)\
container_of(mod_freesync, struct core_freesync, public)
 
@@ -572,22 +485,64 @@ bool mod_freesync_get_v_position(struct mod_freesync 
*mod_freesync,
return false;
 }
 
-static void build_vrr_infopacket_header_vtem(enum signal_type signal,
+static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr,
struct dc_info_packet *infopacket)
 {
-   // HEADER
-
-   // HB0, HB1, HB2 indicates PacketType VTEMPacket
-   infopacket->hb0 = 0x7F;
-   infopacket->hb1 = 0xC0;
-   infopacket->hb2 = 0x00; //sequence_index
-
-   setFieldWithMask(>sb[VRR_VTEM_PB0], 
MASK__VRR_VTEM_PB0__VFR, 1);
-   setFieldWithMask(>sb[VRR_VTEM_PB2], 
MASK__VRR_VTEM_PB2__ORGANIZATION_ID, 1);
-   setFieldWithMask(>sb[VRR_VTEM_PB3], 
MASK__VRR_VTEM_PB3__DATA_SET_TAG_MSB, 0);
-   setFieldWithMask(>sb[VRR_VTEM_PB4], 
MASK__VRR_VTEM_PB4__DATA_SET_TAG_LSB, 1);
-   setFieldWithMask(>sb[VRR_VTEM_PB5], 
MASK__VRR_VTEM_PB5__DATA_SET_LENGTH_MSB, 0);
-   setFieldWithMask(>sb[VRR_VTEM_PB6], 
MASK__VRR_VTEM_PB6__DATA_SET_LENGTH_LSB, 4);
+   /* PB1 = 0x1A (24bit AMD IEEE OUI (0x1A) - Byte 0) */
+   infopacket->sb[1] = 0x1A;
+
+   /* PB2 = 0x00 (24bit AMD IEEE OUI (0x1A) - Byte 1) */
+   infopacket->sb[2] = 0x00;
+
+   /* PB3 = 0x00 (24bit AMD IEEE OUI (0x1A) - Byte 2) */
+   infopacket->sb[3] = 0x00;
+
+   /* PB4 = 

[PATCH 14/36] drm/amd/display: remove unused function

[Bhawanpreet Lakha]

From: Qingqing Zhuo 

[Why]
This function is not being used, it was left in
when introducing DCN2

[How]
Remove the function

Signed-off-by: Qingqing Zhuo 
Reviewed-by: Eric Bernstein 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 1 -
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h  | 5 -
 2 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
index d9e7c711a71c..40164ed015ea 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
@@ -332,7 +332,6 @@ static struct opp_funcs dcn20_opp_funcs = {
.opp_set_disp_pattern_generator = 
opp2_set_disp_pattern_generator,
.dpg_is_blanked = opp2_dpg_is_blanked,
.opp_dpg_set_blank_color = opp2_dpg_set_blank_color,
-   .opp_convert_pti = NULL,
.opp_destroy = opp1_destroy,
.opp_program_left_edge_extra_pixel = 
opp2_program_left_edge_extra_pixel,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 5d8a7b6f..957e9047381a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -316,11 +316,6 @@ struct opp_funcs {
bool (*dpg_is_blanked)(
struct output_pixel_processor *opp);
 
-   void (*opp_convert_pti)(
-   struct output_pixel_processor *opp,
-   bool enable,
-   bool polarity);
-
void (*opp_dpg_set_blank_color)(
struct output_pixel_processor *opp,
const struct tg_color *color);
-- 
2.17.1

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[PATCH 18/36] drm/amd/display: fix stuck test pattern on right half of display

[Bhawanpreet Lakha]

From: Zi Yu Liao 

[why]
With visual confirm enabled, displays where ODM combine is enabled
has a test pattern stuck on the right half of the display even
though the display is unblanked.

[how]
Add a condition to not show the colour ramp test pattern when the
display is unblanked.

Signed-off-by: Zi Yu Liao 
Reviewed-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 4a74a4fb3ab9..31a985858bae 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -892,7 +892,7 @@ void dcn20_blank_pixel_data(
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = 
odm_pipe->next_odm_pipe) {
odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
odm_pipe->stream_res.opp,
-   dc->debug.visual_confirm != 
VISUAL_CONFIRM_DISABLE ?
+   dc->debug.visual_confirm != 
VISUAL_CONFIRM_DISABLE && blank ?

CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
stream->timing.display_color_depth,
_color,
-- 
2.17.1

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[PATCH 20/36] drm/amd/display: fix odm pipe copy

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin 

ODM next and prev pipe were missing from dc_copy_state

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Nikola Cornij 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2b5299e40d66..e09c639685fc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1227,6 +1227,12 @@ struct dc_state *dc_copy_state(struct dc_state *src_ctx)
if (cur_pipe->bottom_pipe)
cur_pipe->bottom_pipe = 
_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
 
+   if (cur_pipe->prev_odm_pipe)
+   cur_pipe->prev_odm_pipe =  
_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
+
+   if (cur_pipe->next_odm_pipe)
+   cur_pipe->next_odm_pipe = 
_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
+
}
 
for (i = 0; i < new_ctx->stream_count; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 40067403b043..f5742719b5d9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3188,7 +3188,7 @@ bool dc_link_dp_set_test_pattern(
memset(_pattern, 0, sizeof(training_pattern));
 
for (i = 0; i < MAX_PIPES; i++) {
-   if (pipes[i].stream->link == link) {
+   if (pipes[i].stream->link == link && !pipes[i].top_pipe && 
!pipes[i].prev_odm_pipe) {
pipe_ctx = [i];
break;
}
-- 
2.17.1

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[PATCH 10/36] drm/amd/display: Zero-out dsc init regs

[Bhawanpreet Lakha]

From: Nikola Cornij 

[why]
Before a statically allocated PPS data structure, that did
get zeroed-out at startup, had been re-used for making packed PPS
SDP. With S3 fix, using a non-initialized PPS data structure was
introduced, while wrongly assuming it'd get initialized before it's
populated. As a consequence 'vbr_enable' and perhaps some other
fields are left uninitialized when making packed PPS SDP. This can
affect 'simple_422' as well because of the way PPS SDP packing is
done (the fields are not masked first, only shifted). The behavior
will be different, depending on the content of uninitialized data.

[how]
Zero-out PPS data structure at initialization time before it's
populated

Fixes:  3b87378c604e929015385e5cc76d0bbd55c05347
drm/amd/display: Set DSC before DIG front-end is connected to its 
back-end

Signed-off-by: Nikola Cornij 
Reviewed-by: Wenjing Liu 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 379c9e4ac63b..c4f861e6bd53 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -447,6 +447,8 @@ static void dsc_init_reg_values(struct dsc_reg_values 
*reg_vals)
 {
int i;
 
+   memset(reg_vals, 0, sizeof(struct dsc_reg_values));
+
/* Non-PPS values */
reg_vals->dsc_clock_enable= 1;
reg_vals->dsc_clock_gating_disable= 0;
-- 
2.17.1

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[PATCH 11/36] drm/amd/display: refactor Device ID for external chips

[Bhawanpreet Lakha]

From: Qingqing Zhuo 

IEEE OUI will now be used while referring to certain vendors.
instead of normal index

Signed-off-by: Qingqing Zhuo 
Reviewed-by: Charlene Liu 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  2 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 21 ++-
 .../amd/display/include/ddc_service_types.h   | 10 +
 3 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 94064d8ce303..7fd2d1358f1b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -292,7 +292,7 @@ static uint32_t defer_delay_converter_wa(
 {
struct dc_link *link = ddc->link;
 
-   if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_4 &&
+   if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
!memcmp(link->dpcd_caps.branch_dev_name,
DP_DVI_CONVERTER_ID_4,
sizeof(link->dpcd_caps.branch_dev_name)))
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2aa44b28b673..40067403b043 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2684,13 +2684,13 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, 
uint8_t *dpcd_data,
 
if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
switch (link->dpcd_caps.branch_dev_id) {
-   /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
+   /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power 
down
 * all internal circuits including AUX communication preventing
 * reading DPCD table and EDID (spec violation).
 * Encoder will skip DP RX power down on disable_output to
 * keep receiver powered all the time.*/
-   case DP_BRANCH_DEVICE_ID_1:
-   case DP_BRANCH_DEVICE_ID_4:
+   case DP_BRANCH_DEVICE_ID_0010FA:
+   case DP_BRANCH_DEVICE_ID_0080E1:
link->wa_flags.dp_keep_receiver_powered = true;
break;
 
@@ -3394,7 +3394,13 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link 
*link)
if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
 
switch (link->dpcd_caps.branch_dev_id) {
-   case DP_BRANCH_DEVICE_ID_2:
+   case DP_BRANCH_DEVICE_ID_0022B9:
+   /* alternate scrambler reset is required for Travis
+* for the case when external chip does not
+* provide sink device id, alternate scrambler
+* scheme will  be overriden later by querying
+* Encoder features
+*/
if (strncmp(
link->dpcd_caps.branch_dev_name,
DP_VGA_LVDS_CONVERTER_ID_2,
@@ -3404,7 +3410,12 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link 
*link)
return DP_PANEL_MODE_SPECIAL;
}
break;
-   case DP_BRANCH_DEVICE_ID_3:
+   case DP_BRANCH_DEVICE_ID_1A:
+   /* alternate scrambler reset is required for Travis
+* for the case when external chip does not provide
+* sink device id, alternate scrambler scheme will
+* be overriden later by querying Encoder feature
+*/
if (strncmp(link->dpcd_caps.branch_dev_name,
DP_VGA_LVDS_CONVERTER_ID_3,
sizeof(
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h 
b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index d968956a10cd..18961707db23 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -25,10 +25,12 @@
 #ifndef __DAL_DDC_SERVICE_TYPES_H__
 #define __DAL_DDC_SERVICE_TYPES_H__
 
-#define DP_BRANCH_DEVICE_ID_1 0x0010FA
-#define DP_BRANCH_DEVICE_ID_2 0x0022B9
-#define DP_BRANCH_DEVICE_ID_3 0x1A
-#define DP_BRANCH_DEVICE_ID_4 0x0080e1
+/* 0010FA dongles (ST Micro) external converter chip id */
+#define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA
+/* 0022B9 external converter chip id */
+#define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9
+#define DP_BRANCH_DEVICE_ID_1A 0x1A
+#define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1
 
 enum ddc_result {
DDC_RESULT_UNKNOWN = 0,
-- 
2.17.1

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[PATCH 07/36] drm/amd/display: set Hratio and VRatio in dml

[Bhawanpreet Lakha]

From: Ilya Bakoulin 

Set the writeback Hratio and Vratio in dml.

Signed-off-by: Ilya Bakoulin 
Reviewed-by: Charlene Liu 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index bd634dce6f3a..65cf4edddaff 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -466,6 +466,10 @@ static void fetch_pipe_params(struct display_mode_lib 
*mode_lib)
dout->wb.wb_dst_width;

mode_lib->vba.WritebackDestinationHeight[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_dst_height;
+   
mode_lib->vba.WritebackHRatio[mode_lib->vba.NumberOfActivePlanes] =
+   dout->wb.wb_hratio;
+   
mode_lib->vba.WritebackVRatio[mode_lib->vba.NumberOfActivePlanes] =
+   dout->wb.wb_vratio;

mode_lib->vba.WritebackPixelFormat[mode_lib->vba.NumberOfActivePlanes] =
(enum source_format_class) 
(dout->wb.wb_pixel_format);

mode_lib->vba.WritebackHTaps[mode_lib->vba.NumberOfActivePlanes] =
-- 
2.17.1

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[PATCH 09/36] drm/amd/display: Implement voltage limitation stub

[Bhawanpreet Lakha]

From: Joseph Gravenor 

add new function to get the voltage at the end of
dcn_validate_bandwidth, to check against the
highest voltage we allow.

Created a stub to allow for optimizations

Signed-off-by: Joseph Gravenor 
Reviewed-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
Acked-by: Sun peng Li 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 061c6e3a3088..383f4f8db8f4 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -705,6 +705,13 @@ static void hack_bounding_box(struct dcn_bw_internal_vars 
*v,
hack_force_pipe_split(v, 
context->streams[0]->timing.pix_clk_100hz);
 }
 
+
+unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev)
+{
+   /* we are ok with all levels */
+   return 4;
+}
+
 bool dcn_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
@@ -732,6 +739,7 @@ bool dcn_validate_bandwidth(
 
memset(v, 0, sizeof(*v));
kernel_fpu_begin();
+
v->sr_exit_time = dc->dcn_soc->sr_exit_time;
v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
v->urgent_latency = dc->dcn_soc->urgent_latency;
@@ -1268,7 +1276,7 @@ bool dcn_validate_bandwidth(
PERFORMANCE_TRACE_END();
BW_VAL_TRACE_FINISH();
 
-   if (bw_limit_pass && v->voltage_level != 5)
+   if (bw_limit_pass && v->voltage_level <= 
get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev))
return true;
else
return false;
-- 
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[PATCH 05/36] drm/amd/display: load iram for abm 2.3

[Bhawanpreet Lakha]

From: Josip Pavic 

[Why]
ABM 2.3 firmware expects information in iRAM that differs from previous
versions of ABM, so a mechanism is required to provide it with that
information.

[How]
Extend the existing iRAM definition to include parameters added by
ABM 2.3, and load it if DMCU is running ABM 2.3.

Signed-off-by: Josip Pavic 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
---
 .../amd/display/modules/power/power_helpers.c | 121 --
 1 file changed, 109 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index b3810b864676..05e2be856037 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -66,6 +66,39 @@ static const unsigned char 
abm_config[abm_defines_max_config][abm_defines_max_le
 {   3,  6,  10, 12  }, /* Alt 
#3  - Super aggressiveness */
 };
 
+struct abm_parameters {
+   unsigned char min_reduction;
+   unsigned char max_reduction;
+   unsigned char bright_pos_gain;
+   unsigned char dark_pos_gain;
+   unsigned char brightness_gain;
+   unsigned char contrast_factor;
+   unsigned char deviation_gain;
+   unsigned char min_knee;
+   unsigned char max_knee;
+};
+
+static const struct abm_parameters abm_settings_config0[abm_defines_max_level] 
= {
+//  min_red  max_red  bright_pos  dark_pos  brightness_gain  contrast  
deviation  min_knee  max_knee
+   {0xff,   0xbf,0x20,   0x00, 0xff,0x99, 
0xb3,  0x40, 0xE0},
+   {0xff,   0x85,0x20,   0x00, 0xff,0x90, 
0xa8,  0x40, 0xE0},
+   {0xff,   0x40,0x20,   0x00, 0xff,0x90, 
0x68,  0x40, 0xE0},
+   {0x82,   0x4d,0x20,   0x00, 0x00,0x90, 
0xb3,  0x70, 0x70},
+};
+
+static const struct abm_parameters abm_settings_config1[abm_defines_max_level] 
= {
+//  min_red  max_red  bright_pos  dark_pos  brightness_gain  contrast  
deviation  min_knee  max_knee
+   {0xf0,   0xd9,0x20,   0x00, 0x00,0xa8, 
0xb3,  0x70, 0x70},
+   {0xcd,   0xa5,0x20,   0x00, 0x00,0xa8, 
0xb3,  0x70, 0x70},
+   {0x99,   0x65,0x20,   0x00, 0x00,0xa8, 
0xb3,  0x70, 0x70},
+   {0x82,   0x4d,0x20,   0x00, 0x00,0xa8, 
0xb3,  0x70, 0x70},
+};
+
+static const struct abm_parameters * const abm_settings[] = {
+   abm_settings_config0,
+   abm_settings_config1,
+};
+
 #define NUM_AMBI_LEVEL5
 #define NUM_AGGR_LEVEL4
 #define NUM_POWER_FN_SEGS 8
@@ -131,11 +164,13 @@ struct iram_table_v_2_2 {
uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];  /* 0x16 
U0.8 */
uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];/* 0x2a 
U2.6 */
uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];  /* 0x3e 
U2.6 */
-   uint8_t hybridFactor[NUM_AGGR_LEVEL];   
/* 0x52 U0.8 */
-   uint8_t contrastFactor[NUM_AGGR_LEVEL]; 
/* 0x56 U0.8 */
+   uint8_t hybrid_factor[NUM_AGGR_LEVEL];  
/* 0x52 U0.8 */
+   uint8_t contrast_factor[NUM_AGGR_LEVEL];
/* 0x56 U0.8 */
uint8_t deviation_gain[NUM_AGGR_LEVEL]; 
/* 0x5a U0.8 */
uint8_t iir_curve[NUM_AMBI_LEVEL];  
/* 0x5e U0.8 */
-   uint8_t pad[29];
/* 0x63 U0.8 */
+   uint8_t min_knee[NUM_AGGR_LEVEL];   
/* 0x63 U0.8 */
+   uint8_t max_knee[NUM_AGGR_LEVEL];   
/* 0x67 U0.8 */
+   uint8_t pad[21];
/* 0x6b U0.8 */
 
/* parameters for crgb conversion */
uint16_t crgb_thresh[NUM_POWER_FN_SEGS];
/* 0x80 U3.13 */
@@ -501,15 +536,72 @@ void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, 
struct dmcu_iram_parame
ram_table->dark_pos_gain[4][2] = 0x00;
ram_table->dark_pos_gain[4][3] = 0x00;
 
-   ram_table->hybridFactor[0] = 0xff;
-   ram_table->hybridFactor[1] = 0xff;
-   ram_table->hybridFactor[2] = 0xff;
-   ram_table->hybridFactor[3] = 0xc0;
+   ram_table->hybrid_factor[0] = 0xff;
+   ram_table->hybrid_factor[1] = 0xff;
+   ram_table->hybrid_factor[2] = 0xff;
+   ram_table->hybrid_factor[3] = 0xc0;
 
-   

[PATCH 06/36] drm/amd/display: fix dp stream enable

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin 

A previous odm change broke stream enable by always setting
n_multiply as if odm was on.

This fixes the check for odm by making sure opp count is >1
rather than not 0.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c  | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index aee624371728..87ba8efc51ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1585,10 +1585,10 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
params.link_settings.link_rate = link_settings->link_rate;
 
if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
-   if (optc1_is_two_pixels_per_containter(>timing) || 
params.opp_cnt)
+   if (optc1_is_two_pixels_per_containter(>timing) || 
params.opp_cnt > 1)
params.timing.pix_clk_100hz /= 2;
pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
-   pipe_ctx->stream_res.stream_enc, 
params.opp_cnt);
+   pipe_ctx->stream_res.stream_enc, params.opp_cnt 
> 1);

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc,
 );
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 488fb5c71dd0..2ed3b561ebbd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -466,7 +466,7 @@ void enc2_stream_encoder_dp_unblank(
uint64_t m_vid_l = n_vid;
 
/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
-   if (is_two_pixels_per_containter(>timing) || 
param->opp_cnt) {
+   if (is_two_pixels_per_containter(>timing) || 
param->opp_cnt > 1) {
/*this logic should be the same in 
get_pixel_clock_parameters() */
n_multiply = 1;
}
-- 
2.17.1

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[PATCH 08/36] drm/amd/display: add null checks before logging

[Bhawanpreet Lakha]

From: Wyatt Wood 

Adding NULL checks to various parameters in log_tf, to avoid
nullptr errors

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
Acked-by: Nikola Cornij 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f6f20050e389..0e55df3db53c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1502,9 +1502,12 @@ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
} else
dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, 
OPP_REGAMMA_BYPASS);
 
-   log_tf(stream->ctx,
-   stream->out_transfer_func,
-   dpp->regamma_params.hw_points_num);
+   if (stream != NULL && stream->ctx != NULL &&
+   stream->out_transfer_func != NULL) {
+   log_tf(stream->ctx,
+   stream->out_transfer_func,
+   dpp->regamma_params.hw_points_num);
+   }
 
return true;
 }
-- 
2.17.1

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[PATCH 03/36] drm/amd/display: fix audio endpoint not getting disabled issue

[Bhawanpreet Lakha]

From: Su Sung Chung 

[Why]
Disable_audio_stream gets enum option as a paramenter which will decide
if we free acquired resources or not. However checks for the option is
guarded by the other condition which check if audio stream is getting
diabled more than once. With both conditions combined, if we attempt to
disable audio stream twice in a row, first with keep and second with
free as an option, we will never free any resources, which will make
system think there is audio endpoint connected even after we plug out
the device

[How]
Get rid of option as parameter to disable_audio_stream and move the part
of the code that free acquired resources to outside where to keep or to
free resources is actually determined

Signed-off-by: Su Sung Chung 
Reviewed-by: Jun Lei 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  6 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  4 +-
 .../drm/amd/display/dc/core/dc_link_hwss.c|  4 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   | 40 +++
 .../display/dc/dce110/dce110_hw_sequencer.h   |  4 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 20 --
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 24 ---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|  2 +-
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  7 +---
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  5 +--
 10 files changed, 74 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 62d5f454f824..2b5299e40d66 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1915,7 +1915,11 @@ static void commit_planes_do_stream_update(struct dc *dc,
dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
 
if (*stream_update->dpms_off) {
-   core_link_disable_stream(pipe_ctx, 
KEEP_ACQUIRED_RESOURCE);
+   core_link_disable_stream(pipe_ctx);
+   /* for dpms, keep acquired resources*/
+   if (pipe_ctx->stream_res.audio && 
!dc->debug.az_endpoint_mute_only)
+   
pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
+
dc->hwss.optimize_bandwidth(dc, 
dc->current_state);
} else {
if (!dc->optimize_seamless_boot)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 78c4d07253bb..cb909197b76f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2806,7 +2806,7 @@ void core_link_enable_stream(
 #endif
 }
 
-void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
 {
struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;
@@ -2841,7 +2841,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, 
int option)
write_i2c_redriver_setting(pipe_ctx, false);
}
}
-   core_dc->hwss.disable_stream(pipe_ctx, option);
+   core_dc->hwss.disable_stream(pipe_ctx);
 
disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index fe9a4e4b9d1f..79438c4f1e20 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -289,7 +289,9 @@ void dp_retrain_link_dp_test(struct dc_link *link,
 
dp_receiver_power_ctrl(link, false);
 
-   link->dc->hwss.disable_stream([i], 
KEEP_ACQUIRED_RESOURCE);
+   link->dc->hwss.disable_stream([i]);
+   if (([i])->stream_res.audio && 
!link->dc->debug.az_endpoint_mute_only)
+   
([i])->stream_res.audio->funcs->az_disable(([i])->stream_res.audio);
 
link->link_enc->funcs->disable_output(
link->link_enc,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2693404cab1a..c2d026ba269f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -978,7 +978,7 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
}
 }
 
-void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
+void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
 {

[PATCH 00/36] DC Patches 19 Aug 2019

[Bhawanpreet Lakha]

Summary Of Changes
*ODM fixes
*Gamma logging
*DSC fixes

Ahmad Othman (1):
  drm/amd/display: Refactoring VTEM

Anthony Koo (2):
  drm/amd/display: 3.2.47
  drm/amd/display: 3.2.48

Bayan Zabihiyan (2):
  drm/amd/display: add Cursor Degamma logic for DCN2
  drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags

Charlene Liu (2):
  drm/amd/display: support spdif
  drm/amd/display: set av_mute in hw_init for HDMI

David Francis (1):
  drm/amd/display: MST topology debugfs

Derek Lai (1):
  drm/amd/display: Use res_cap to acquire i2c instead of pipe count

Dmytro Laktyushkin (6):
  drm/amd/display: re structure odm to allow 4 to 1 support
  drm/amd/display: fix dp stream enable
  drm/amd/display: fix odm pipe copy
  drm/amd/display: fix dcn20 odm dpp programming
  drm/amd/display: fix odm stream release
  drm/amd/display: fix odm validation

Ilya Bakoulin (1):
  drm/amd/display: set Hratio and VRatio in dml

Jaehyun Chung (2):
  drm/amd/display: Add VM page fault handle implementation
  drm/amd/display: Enable HW rotation

Joseph Gravenor (1):
  drm/amd/display: Implement voltage limitation stub

Joshua Aberback (1):
  drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL

Josip Pavic (1):
  drm/amd/display: load iram for abm 2.3

Julian Parkin (1):
  drm/amd/display: Delete dead code in command_table_helper

Jun Lei (2):
  drm/amd/display: fix DML not calculating delivery time
  drm/amd/display: revert wait in pipelock

Martin Leung (1):
  drm/amd/display: cleaned up coding error in init_hw

Nikola Cornij (2):
  drm/amd/display: Zero-out dsc init regs
  drm/amd/display: Fix number of slices not being checked for dsc

Qingqing Zhuo (2):
  drm/amd/display: refactor Device ID for external chips
  drm/amd/display: remove unused function

Su Sung Chung (1):
  drm/amd/display: fix audio endpoint not getting disabled issue

Wyatt Wood (2):
  drm/amd/display: add null checks before logging
  drm/amd/display: Add Logging for Gamma Related information

Yogesh Mohan Marimuthu (1):
  drm/amd/display: fix trigger not generated for freesync

Zi Yu Liao (2):
  drm/amd/display: fix MPO HUBP underflow with Scatter Gather
  drm/amd/display: fix stuck test pattern on right half of display

hersen wu (1):
  drm/amd/display: flicking observed while installing driver on Navi10
CF

 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  24 ++
 .../bios/dce110/command_table_helper_dce110.c |  36 +--
 .../dce112/command_table_helper2_dce112.c |  36 +--
 .../bios/dce112/command_table_helper_dce112.c |  36 +--
 .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  |  10 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  27 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |   4 +-
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |   2 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  56 ++--
 .../drm/amd/display/dc/core/dc_link_hwss.c|  40 +--
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 231 ++-
 drivers/gpu/drm/amd/display/dc/dc.h   |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |   5 +-
 .../gpu/drm/amd/display/dc/dce/dce_audio.c|   4 +-
 .../gpu/drm/amd/display/dc/dce/dce_hwseq.h|  43 ++-
 .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c   |   3 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  50 ++--
 .../display/dc/dce110/dce110_hw_sequencer.h   |   4 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  |  16 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h  |   2 +-
 .../drm/amd/display/dc/dcn10/dcn10_hubbub.h   |   6 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 149 ++
 .../amd/display/dc/dcn10/dcn10_link_encoder.c |  23 ++
 .../amd/display/dc/dcn10/dcn10_link_encoder.h |   2 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |  15 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   8 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c  |  10 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h  |   2 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |   4 +-
 .../drm/amd/display/dc/dcn20/dcn20_hubbub.c   |   5 +
 .../drm/amd/display/dc/dcn20/dcn20_hubbub.h   |   9 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |  18 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 140 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|   2 +-
 .../amd/display/dc/dcn20/dcn20_link_encoder.c |   1 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c  |   1 -
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 268 ++---
 .../display/dc/dcn20/dcn20_stream_encoder.c   |   2 +-
 .../dc/dml/dcn20/display_mode_vba_20v2.c  |  27 ++
 .../drm/amd/display/dc/dml/display_mode_vba.c |   4 +
 .../gpu/drm/amd/display/dc/inc/core_types.h   |   9 +-
 .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |   2 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   |   2 +-
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |   2 +
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h   |   5 -
 .../amd/display/dc/inc/hw/stream_encoder.h|   2 +-
 .../amd/display/dc/inc/hw/timing_generator.h  |   2 +
 

[PATCH 01/36] drm/amd/display: re structure odm to allow 4 to 1 support

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin 

Currently odm is handled using top_bottom pipe by special casing
the differing opps to differentiate from mpc combine.

Since top/bottom pipe list was made to track mpc muxing this creates
difficulties in adding a 4 pipe odm case support.

Rather than continue using mpc combine list, this change reworks odm
to use it's own linked list to keep track of odm combine pipes. This
also opens up options for using mpo with odm, if a practical use case
is ever found.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  10 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  33 ++-
 .../drm/amd/display/dc/core/dc_link_hwss.c|  36 +--
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 150 ---
 .../display/dc/dce110/dce110_hw_sequencer.c   |   7 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   2 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  90 ---
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 244 --
 .../display/dc/dcn20/dcn20_stream_encoder.c   |   2 +-
 .../gpu/drm/amd/display/dc/inc/core_types.h   |   2 +
 .../amd/display/dc/inc/hw/stream_encoder.h|   2 +-
 drivers/gpu/drm/amd/display/dc/inc/resource.h |   3 -
 12 files changed, 316 insertions(+), 265 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 77ac7f707ec5..62d5f454f824 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1857,9 +1857,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
 
-   if (!pipe_ctx->top_pipe &&
-   pipe_ctx->stream &&
-   pipe_ctx->stream == stream) {
+   if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && 
pipe_ctx->stream == stream) {
 
if (stream_update->periodic_interrupt0 &&
dc->hwss.setup_periodic_interrupt)
@@ -1885,7 +1883,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
 
if (stream_update->dither_option) {
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
-   struct pipe_ctx *odm_pipe = 
dc_res_get_odm_bottom_pipe(pipe_ctx);
+   struct pipe_ctx *odm_pipe = 
pipe_ctx->next_odm_pipe;
 #endif

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

_ctx->stream->bit_depth_params);
@@ -1893,10 +1891,12 @@ static void commit_planes_do_stream_update(struct dc 
*dc,
>bit_depth_params,
>clamping);
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
-   if (odm_pipe)
+   while (odm_pipe) {

odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,

>bit_depth_params,
>clamping);
+   odm_pipe = odm_pipe->next_odm_pipe;
+   }
 #endif
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2e87942b3e9c..2aa44b28b673 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3095,14 +3095,19 @@ static void set_crtc_test_pattern(struct dc_link *link,
controller_test_pattern, color_depth);
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
else if (opp->funcs->opp_set_disp_pattern_generator) {
-   struct pipe_ctx *bot_odm_pipe = 
dc_res_get_odm_bottom_pipe(pipe_ctx);
+   struct pipe_ctx *odm_pipe;
+   int opp_cnt = 1;
 
-   if (bot_odm_pipe) {
-   struct output_pixel_processor *bot_opp = 
bot_odm_pipe->stream_res.opp;
+   for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; 
odm_pipe = odm_pipe->next_odm_pipe)
+   opp_cnt++;
 
-   
bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, );
-   width /= 2;
-   
bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp,
+   width /= opp_cnt;
+
+   for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; 
odm_pipe = odm_pipe->next_odm_pipe) {
+   struct output_pixel_processor *odm_opp = 
odm_pipe->stream_res.opp;
+
+   

[PATCH 02/36] drm/amd/display: Delete dead code in command_table_helper

[Bhawanpreet Lakha]

From: Julian Parkin 

[Why]
dig_encoder_sel_to_atom will always return zero on any ASIC version
past DCE80 since programming of the FE selection is handled by
driver, but the translation code was left in the function, making
it look like a coding error.

[How]
Remove code that has no effect, and replace with a comment describing
why it returns zero.

Signed-off-by: Julian Parkin 
Reviewed-by: Wenjing Liu 
Acked-by: Bhawanpreet Lakha 
---
 .../bios/dce110/command_table_helper_dce110.c | 36 +++
 .../dce112/command_table_helper2_dce112.c | 36 +++
 .../bios/dce112/command_table_helper_dce112.c | 36 +++
 3 files changed, 12 insertions(+), 96 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c 
b/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
index ca24154468c7..11bf247bb180 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
@@ -153,38 +153,10 @@ static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
 
 static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
 {
-   uint8_t atom_dig_encoder_sel = 0;
-
-   switch (id) {
-   case ENGINE_ID_DIGA:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
-   break;
-   case ENGINE_ID_DIGB:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
-   break;
-   case ENGINE_ID_DIGC:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
-   break;
-   case ENGINE_ID_DIGD:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
-   break;
-   case ENGINE_ID_DIGE:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
-   break;
-   case ENGINE_ID_DIGF:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
-   break;
-   case ENGINE_ID_DIGG:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
-   break;
-   case ENGINE_ID_UNKNOWN:
-/* No DIG_FRONT is associated to DIG_BACKEND */
-   atom_dig_encoder_sel = 0;
-   break;
-   default:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
-   break;
-   }
+   /* On any ASIC after DCE80, we manually program the DIG_FE
+* selection (see connect_dig_be_to_fe function of the link
+* encoder), so translation should always return 0 (no FE).
+*/
 
return 0;
 }
diff --git 
a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c 
b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
index 0237ae575068..755b6e33140a 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
@@ -150,38 +150,10 @@ static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
 
 static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
 {
-   uint8_t atom_dig_encoder_sel = 0;
-
-   switch (id) {
-   case ENGINE_ID_DIGA:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
-   break;
-   case ENGINE_ID_DIGB:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
-   break;
-   case ENGINE_ID_DIGC:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
-   break;
-   case ENGINE_ID_DIGD:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
-   break;
-   case ENGINE_ID_DIGE:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
-   break;
-   case ENGINE_ID_DIGF:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
-   break;
-   case ENGINE_ID_DIGG:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
-   break;
-   case ENGINE_ID_UNKNOWN:
-   /* No DIG_FRONT is associated to DIG_BACKEND */
-   atom_dig_encoder_sel = 0;
-   break;
-   default:
-   atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
-   break;
-   }
+   /* On any ASIC after DCE80, we manually program the DIG_FE
+* selection (see connect_dig_be_to_fe function of the link
+* encoder), so translation should always return 0 (no FE).
+*/
 
return 0;
 }
diff --git 
a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c 
b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
index 452034f83e4c..06b4f7fa4a50 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
@@ -150,38 +150,10 @@ static uint8_t 

[PATCH 04/36] drm/amd/display: fix MPO HUBP underflow with Scatter Gather

[Bhawanpreet Lakha]

From: Zi Yu Liao 

[why]
With Scatter Gather enabled, HUBP underflows during MPO enabled video
playback. hubp_init has a register write that fixes this problem, but
the register is cleared when HUBP gets power gated.

[how]
Make a call to hubp_init during enable_plane, so that the fix can
be applied after HUBP powers back on again.

Signed-off-by: Zi Yu Liao 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 687d670fbd5d..aee624371728 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -938,6 +938,9 @@ void dcn20_enable_plane(
/* enable DCFCLK current DCHUB */

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
 
+   /* initialize HUBP on power up */
+   pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
+
/* make sure OPP_PIPE_CLOCK_EN = 1 */
pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
pipe_ctx->stream_res.opp,
-- 
2.17.1

___
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Re: [PATCH ARM] selftests, arm64: fix uninitialized symbol in tags_test.c

[Andrey Konovalov]

On Mon, Aug 19, 2019 at 3:14 PM Andrey Konovalov  wrote:
>
> Fix tagged_ptr not being initialized when TBI is not enabled.
>
> Dan Carpenter 
> Signed-off-by: Andrey Konovalov 
> ---
>  tools/testing/selftests/arm64/tags_test.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/tools/testing/selftests/arm64/tags_test.c 
> b/tools/testing/selftests/arm64/tags_test.c
> index 22a1b266e373..5701163460ef 100644
> --- a/tools/testing/selftests/arm64/tags_test.c
> +++ b/tools/testing/selftests/arm64/tags_test.c
> @@ -14,15 +14,17 @@
>  int main(void)
>  {
> static int tbi_enabled = 0;
> -   struct utsname *ptr, *tagged_ptr;
> +   unsigned long tag = 0;
> +   struct utsname *ptr;
> int err;
>
> if (prctl(PR_SET_TAGGED_ADDR_CTRL, PR_TAGGED_ADDR_ENABLE, 0, 0, 0) == 
> 0)
> tbi_enabled = 1;
> ptr = (struct utsname *)malloc(sizeof(*ptr));
> if (tbi_enabled)
> -   tagged_ptr = (struct utsname *)SET_TAG(ptr, 0x42);
> -   err = uname(tagged_ptr);
> +   tag = 0x42;
> +   ptr = (struct utsname *)SET_TAG(ptr, tag);
> +   err = uname(ptr);
> free(ptr);
>
> return err;
> --
> 2.23.0.rc1.153.gdeed80330f-goog
>

Hi Will,

This is supposed to go on top of the TBI related patches that you have
added to the arm tree.

Thanks!

[PATCH ARM] selftests, arm64: fix uninitialized symbol in tags_test.c

[Andrey Konovalov]

Fix tagged_ptr not being initialized when TBI is not enabled.

Dan Carpenter 
Signed-off-by: Andrey Konovalov 
---
 tools/testing/selftests/arm64/tags_test.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/arm64/tags_test.c 
b/tools/testing/selftests/arm64/tags_test.c
index 22a1b266e373..5701163460ef 100644
--- a/tools/testing/selftests/arm64/tags_test.c
+++ b/tools/testing/selftests/arm64/tags_test.c
@@ -14,15 +14,17 @@
 int main(void)
 {
static int tbi_enabled = 0;
-   struct utsname *ptr, *tagged_ptr;
+   unsigned long tag = 0;
+   struct utsname *ptr;
int err;
 
if (prctl(PR_SET_TAGGED_ADDR_CTRL, PR_TAGGED_ADDR_ENABLE, 0, 0, 0) == 0)
tbi_enabled = 1;
ptr = (struct utsname *)malloc(sizeof(*ptr));
if (tbi_enabled)
-   tagged_ptr = (struct utsname *)SET_TAG(ptr, 0x42);
-   err = uname(tagged_ptr);
+   tag = 0x42;
+   ptr = (struct utsname *)SET_TAG(ptr, tag);
+   err = uname(ptr);
free(ptr);
 
return err;
-- 
2.23.0.rc1.153.gdeed80330f-goog

Re: [PATCH] drm/amdgpu: Fix a typo in the include header guard of 'navi12_ip_offset.h'

[Alex Deucher]

Applied.  thanks!

Alex

On Sun, Aug 18, 2019 at 9:33 PM Yuan, Xiaojie  wrote:
>
> Reviewed-by: Xiaojie Yuan 
>
> Xiaojie
>
> > On Aug 19, 2019, at 12:00 AM, Christophe JAILLET 
> >  wrote:
> >
> > '_navi10_ip_offset_HEADER' is already used in 'navi10_ip_offset.h', so use
> > '_navi12_ip_offset_HEADER' instead here.
> >
> > Signed-off-by: Christophe JAILLET 
> > ---
> > drivers/gpu/drm/amd/include/navi12_ip_offset.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/include/navi12_ip_offset.h 
> > b/drivers/gpu/drm/amd/include/navi12_ip_offset.h
> > index 229e8fddfcc1..6c2cc6296c06 100644
> > --- a/drivers/gpu/drm/amd/include/navi12_ip_offset.h
> > +++ b/drivers/gpu/drm/amd/include/navi12_ip_offset.h
> > @@ -18,8 +18,8 @@
> >  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> >  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
> > SOFTWARE.
> >  */
> > -#ifndef _navi10_ip_offset_HEADER
> > -#define _navi10_ip_offset_HEADER
> > +#ifndef _navi12_ip_offset_HEADER
> > +#define _navi12_ip_offset_HEADER
> >
> > #define MAX_INSTANCE   7
> > #define MAX_SEGMENT5
> > --
> > 2.20.1
> >
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[bug report] drm/amd/powerplay: implement smc firmware v2.1 for smu11

[Dan Carpenter]

Hello Kevin Wang,

The patch b55c83a7438d: "drm/amd/powerplay: implement smc firmware
v2.1 for smu11" from Jun 21, 2019, leads to the following static
checker warning:

drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:390 
smu_v11_0_setup_pptable()
warn: passing casted pointer '' to 'smu_get_atom_data_table()' 32 
vs 16.

drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c
   357  static int smu_v11_0_setup_pptable(struct smu_context *smu)
   358  {
   359  struct amdgpu_device *adev = smu->adev;
   360  const struct smc_firmware_header_v1_0 *hdr;
   361  int ret, index;
   362  uint32_t size;
^

   363  uint8_t frev, crev;
   364  void *table;
   365  uint16_t version_major, version_minor;
   366  
   367  hdr = (const struct smc_firmware_header_v1_0 *) 
adev->pm.fw->data;
   368  version_major = le16_to_cpu(hdr->header.header_version_major);
   369  version_minor = le16_to_cpu(hdr->header.header_version_minor);
   370  if (version_major == 2 && 
smu->smu_table.boot_values.pp_table_id > 0) {
   371  switch (version_minor) {
   372  case 0:
   373  ret = smu_v11_0_set_pptable_v2_0(smu, , 
);
   374  break;
   375  case 1:
   376  ret = smu_v11_0_set_pptable_v2_1(smu, , 
,
   377   
smu->smu_table.boot_values.pp_table_id);
   378  break;
   379  default:
   380  ret = -EINVAL;
   381  break;
   382  }
   383  if (ret)
   384  return ret;
   385  
   386  } else {
   387  index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
   388  powerplayinfo);
   389  
   390  ret = smu_get_atom_data_table(smu, index, (uint16_t 
*), , ,
  
^
This only initializes the highest 16 bits.

   391(uint8_t **));
   392  if (ret)
   393  return ret;
   394  }
   395  
   396  if (!smu->smu_table.power_play_table)
   397  smu->smu_table.power_play_table = table;
   398  if (!smu->smu_table.power_play_table_size)
   399  smu->smu_table.power_play_table_size = size;
   400  
   401  return 0;

regards,
dan carpenter
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Re: [PATCH v7 0/9] drm: cec: convert DRM drivers to the new notifier API

[Dariusz Marcinkiewicz]

On Mon, Aug 19, 2019 at 11:38 AM Hans Verkuil  wrote:
>
> Hi all,
>
Hi Hans.
> The patches in this series can be applied independently from each other.
>
> If you maintain one of these drivers and you want to merge it for v5.4
> yourself, then please do so and let me know. If you prefer I commit it
> to drm-misc, then please review and (hopefully) Ack the patch.
>
> I would really like to get this in for v5.4 so I can get the userspace
> bits in for v5.4 as well through the media subsystem.
>
> Dariusz, can you post a v7.1 for patch 5/9 fixing the typo?
>
Done.

I think it would be good to test v7 changes to dw-hdmi and tda998x on
a real hardware. Hans, do you think you would be able to test those?

Thank you.
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Re: [PATCH v7 0/9] drm: cec: convert DRM drivers to the new notifier API

[Hans Verkuil]

On 8/19/19 1:28 PM, Dariusz Marcinkiewicz wrote:
> On Mon, Aug 19, 2019 at 11:38 AM Hans Verkuil  
> wrote:
>>
>> Hi all,
>>
> Hi Hans.
>> The patches in this series can be applied independently from each other.
>>
>> If you maintain one of these drivers and you want to merge it for v5.4
>> yourself, then please do so and let me know. If you prefer I commit it
>> to drm-misc, then please review and (hopefully) Ack the patch.
>>
>> I would really like to get this in for v5.4 so I can get the userspace
>> bits in for v5.4 as well through the media subsystem.
>>
>> Dariusz, can you post a v7.1 for patch 5/9 fixing the typo?
>>
> Done.
> 
> I think it would be good to test v7 changes to dw-hdmi and tda998x on
> a real hardware. Hans, do you think you would be able to test those?
> 
> Thank you.
> 

I'll try to do this for dw-hdmi today, but the tda998x testing will have to wait
until next week.

Regards,

Hans
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[bug report] drm/amd/display: add set and get clock for testing purposes

[Dan Carpenter]

Hello Charlene Liu,

This is a semi-automatic email about new static checker warnings.

The patch 925f566cb7ae: "drm/amd/display: add set and get clock for
testing purposes" from Jun 27, 2019, leads to the following Smatch
complaint:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:3230 
dcn10_set_clock()
error: we previously assumed 'dc->clk_mgr' could be null (see line 3226)

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c
  3225  
  3226  if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
^^
Check for NULL

  3227  
dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
  3228  context, clock_type, 
_cfg);

This is indented a bit too far.

  3229  
  3230  if (!dc->clk_mgr->funcs->get_clock)
 ^
This will oops if ->clk_mgr is NULL

  3231  return DC_FAIL_UNSUPPORTED_1;
  3232  

regards,
dan carpenter
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Re: [PATCH 1/3] amd/amdgpu: add Arcturus vf DID support

[Christian König]

Am 16.08.19 um 10:59 schrieb Frank.Min:

Change-Id: I7153153785fdd54a10ebc47e778e06982edc79d7
Signed-off-by: Frank.Min 


Can't judge if the values are correct, but feel free to add an Acked-by: 
Christian König  to the first two patches.



---
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 0e8c165..3890ba2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -999,6 +999,7 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
{0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
{0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
+   {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
/* Navi10 */
{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},


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Re: 答复: 答复: [PATCH 3/3] amd/amdgpu: seperate sriov fb aperture setting

[Koenig, Christian]

> As I point out. For SRIOV, amdgpu_gmc_agp_location() would not be called, so 
> the value calculation would not be valid.
Yeah, that is a good point. The values are zero initialized, but that is 
probably not correct in this moment.

agp_start should be set to 0x and agp_end to 0x0, that are also 
the values the hardware uses to disable the AGP bar.

> Would you please give more info why we need the AGP except for the zfb?
Actually quite a bunch of things. In general we use it to access 
uncached system memory from VMID0 to avoid reprogramming the GART all 
the time.

This in turn is used mostly by the SDMA for keeping page table copies in 
system memory, but can also be used by things like scanout from system 
memory on APUs.

I don't think we have any use case for SRIOV, so disabling the feature 
should be fine.

Regards,
Christian.

Am 19.08.19 um 12:24 schrieb Min, Frank:
> Hi Christian,
> As I point out. For SRIOV, amdgpu_gmc_agp_location() would not be called, so 
> the value calculation would not be valid. Would you please give more info why 
> we need the AGP except for the zfb?
>
> For another, whether you review the other patches?
>
> Best Regards,
> Frank
>
> -邮件原件-
> 发件人: Koenig, Christian 
> 发送时间: 2019年8月19日 15:21
> 收件人: Min, Frank ; amd-gfx@lists.freedesktop.org
> 主题: Re: 答复: [PATCH 3/3] amd/amdgpu: seperate sriov fb aperture setting
>
> Yeah, I thought so.
>
> In this case we don't need this patch or is there anything I'm still missing?
>
> The use of min/max here is exactly to avoid having a SRIOV dependency here.
>
> Regards,
> Christian.
>
> Am 19.08.19 um 09:17 schrieb Min, Frank:
>> Hi Christian,
>> Thanks for your review.
>> For SRIOV, amdgpu_gmc_agp_location() would not be called, since it do not 
>> use AGP. Also there is no need to use the min and max to judge which range 
>> is correct for using.
>>
>> Best Regards,
>> Frank
>>
>> -邮件原件-
>> 发件人: Christian König 
>> 发送时间: 2019年8月19日 15:07
>> 收件人: Min, Frank ; amd-gfx@lists.freedesktop.org
>> 主题: Re: [PATCH 3/3] amd/amdgpu: seperate sriov fb aperture setting
>>
>> Am 16.08.19 um 10:59 schrieb Frank.Min:
>>> sriov would not use agp, so seperate the fb aperture setting.
>> That won't work correctly. This way we don't program the AGP space into the 
>> hardware any more, but would still try to use it.
>>
>> We rather need to adjust the amdgpu_gmc_agp_location() function or it's 
>> caller to not assign an AGP space in the first place.
>>
>> Christian.
>>
>>> Change-Id: I1372cd355326731a31361bff13d79e12121b8651
>>> Signed-off-by: Frank.Min 
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 39 
>>> 
>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 12 +-
>>> drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c  | 27 +++---
>>> 3 files changed, 49 insertions(+), 29 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>> index 6ce37ce..ec78c8b 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>> @@ -75,23 +75,32 @@ static void 
>>> gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
>>> WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 
>>> 24);
>>> WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >>
>>> 24);
>>> 
>>> -   /* Program the system aperture low logical page number. */
>>> -   WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
>>> -min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
>>> +   if (amdgpu_sriov_vf(adev)) {
>>> +   /* Program the system aperture low logical page number. */
>>> +   WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
>>> +adev->gmc.fb_start >> 18);
>>> 
>>> -   if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
>>> -   /*
>>> -* Raven2 has a HW issue that it is unable to use the vram which
>>> -* is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
>>> -* workaround that increase system aperture high address (add 1)
>>> -* to get rid of the VM fault and hardware hang.
>>> -*/
>>> WREG32_SOC15_RLC(GC, 0, 
>>> mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
>>> -max((adev->gmc.fb_end >> 18) + 0x1,
>>> -adev->gmc.agp_end >> 18));
>>> -   else
>>> -   WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
>>> -max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
>>> +adev->gmc.fb_end >> 18);
>>> +   } else {
>>> +   /* Program the system aperture low logical page number. */
>>> +   WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
>>> +min(adev->gmc.fb_start, adev->gmc.agp_start) >> 
>>> 18);
>>> +
>>> +   

答复: 答复: [PATCH 3/3] amd/amdgpu: seperate sriov fb aperture setting

[Min, Frank]

Hi Christian,
As I point out. For SRIOV, amdgpu_gmc_agp_location() would not be called, so 
the value calculation would not be valid. Would you please give more info why 
we need the AGP except for the zfb?

For another, whether you review the other patches?

Best Regards,
Frank

-邮件原件-
发件人: Koenig, Christian  
发送时间: 2019年8月19日 15:21
收件人: Min, Frank ; amd-gfx@lists.freedesktop.org
主题: Re: 答复: [PATCH 3/3] amd/amdgpu: seperate sriov fb aperture setting

Yeah, I thought so.

In this case we don't need this patch or is there anything I'm still missing?

The use of min/max here is exactly to avoid having a SRIOV dependency here.

Regards,
Christian.

Am 19.08.19 um 09:17 schrieb Min, Frank:
> Hi Christian,
> Thanks for your review.
> For SRIOV, amdgpu_gmc_agp_location() would not be called, since it do not use 
> AGP. Also there is no need to use the min and max to judge which range is 
> correct for using.
>
> Best Regards,
> Frank
>
> -邮件原件-
> 发件人: Christian König 
> 发送时间: 2019年8月19日 15:07
> 收件人: Min, Frank ; amd-gfx@lists.freedesktop.org
> 主题: Re: [PATCH 3/3] amd/amdgpu: seperate sriov fb aperture setting
>
> Am 16.08.19 um 10:59 schrieb Frank.Min:
>> sriov would not use agp, so seperate the fb aperture setting.
> That won't work correctly. This way we don't program the AGP space into the 
> hardware any more, but would still try to use it.
>
> We rather need to adjust the amdgpu_gmc_agp_location() function or it's 
> caller to not assign an AGP space in the first place.
>
> Christian.
>
>> Change-Id: I1372cd355326731a31361bff13d79e12121b8651
>> Signed-off-by: Frank.Min 
>> ---
>>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 39 
>> 
>>drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 12 +-
>>drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c  | 27 +++---
>>3 files changed, 49 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> index 6ce37ce..ec78c8b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> @@ -75,23 +75,32 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct 
>> amdgpu_device *adev)
>>  WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
>>  WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 
>> 24);
>>
>> -/* Program the system aperture low logical page number. */
>> -WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
>> - min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
>> +if (amdgpu_sriov_vf(adev)) {
>> +/* Program the system aperture low logical page number. */
>> +WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
>> + adev->gmc.fb_start >> 18);
>>
>> -if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
>> -/*
>> - * Raven2 has a HW issue that it is unable to use the vram which
>> - * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
>> - * workaround that increase system aperture high address (add 1)
>> - * to get rid of the VM fault and hardware hang.
>> - */
>>  WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
>> - max((adev->gmc.fb_end >> 18) + 0x1,
>> - adev->gmc.agp_end >> 18));
>> -else
>> -WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
>> - max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
>> + adev->gmc.fb_end >> 18);
>> +} else {
>> +/* Program the system aperture low logical page number. */
>> +WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
>> + min(adev->gmc.fb_start, adev->gmc.agp_start) >> 
>> 18);
>> +
>> +if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
>> +/*
>> + * Raven2 has a HW issue that it is unable to use the 
>> vram which
>> + * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here 
>> is the
>> + * workaround that increase system aperture high 
>> address (add 1)
>> + * to get rid of the VM fault and hardware hang.
>> + */
>> +WREG32_SOC15_RLC(GC, 0, 
>> mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
>> + max((adev->gmc.fb_end >> 18) + 0x1,
>> + adev->gmc.agp_end >> 18));
>> +else
>> +WREG32_SOC15_RLC(GC, 0, 
>> mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
>> + max(adev->gmc.fb_end, adev->gmc.agp_end) 
>> >> 18);
>> +}
>>
>>  /* Set default page address. */
>>  value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start diff 
>> 

Re: [PATCH v7 0/9] drm: cec: convert DRM drivers to the new notifier API

[Hans Verkuil]

Hi all,

The patches in this series can be applied independently from each other.

If you maintain one of these drivers and you want to merge it for v5.4
yourself, then please do so and let me know. If you prefer I commit it
to drm-misc, then please review and (hopefully) Ack the patch.

I would really like to get this in for v5.4 so I can get the userspace
bits in for v5.4 as well through the media subsystem.

Dariusz, can you post a v7.1 for patch 5/9 fixing the typo?

Thanks!

Hans

On 8/14/19 12:44 PM, Dariusz Marcinkiewicz wrote:
> This series updates DRM drivers to use new CEC notifier API.
> 
> Changes since v6:
>   Made CEC notifiers' registration and de-registration symmetric
>   in tda998x and dw-hdmi drivers. Also, accidentally dropped one
>   patch in v6 (change to drm_dp_cec), brought it back now.
> Changes since v5:
> Fixed a warning about a missing comment for a new member of
>   drm_dp_aux_cec struct. Sending to a wider audience,
>   including maintainers of respective drivers.
> Changes since v4:
>   Addressing review comments.
> Changes since v3:
> Updated adapter flags in dw-hdmi-cec.
> Changes since v2:
>   Include all DRM patches from "cec: improve notifier support,
>   add connector info connector info" series.
> Changes since v1:
>   Those patches delay creation of notifiers until respective
>   connectors are constructed. It seems that those patches, for a
>   couple of drivers, by adding the delay, introduce a race between
>   notifiers' creation and the IRQs handling threads - at least I
>   don't see anything obvious in there that would explicitly forbid
>   such races to occur. v2 adds a write barrier to make sure IRQ
>   threads see the notifier once it is created (replacing the
>   WRITE_ONCE I put in v1). The best thing to do here, I believe,
>   would be not to have any synchronization and make sure that an IRQ
>   only gets enabled after the notifier is created.
> Dariusz Marcinkiewicz (9):
>   drm_dp_cec: add connector info support.
>   drm/i915/intel_hdmi: use cec_notifier_conn_(un)register
>   dw-hdmi-cec: use cec_notifier_cec_adap_(un)register
>   tda9950: use cec_notifier_cec_adap_(un)register
>   drm: tda998x: use cec_notifier_conn_(un)register
>   drm: sti: use cec_notifier_conn_(un)register
>   drm: tegra: use cec_notifier_conn_(un)register
>   drm: dw-hdmi: use cec_notifier_conn_(un)register
>   drm: exynos: exynos_hdmi: use cec_notifier_conn_(un)register
> 
>  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  2 +-
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 13 +++---
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 46 +--
>  drivers/gpu/drm/drm_dp_cec.c  | 25 ++
>  drivers/gpu/drm/exynos/exynos_hdmi.c  | 31 +++--
>  drivers/gpu/drm/i2c/tda9950.c | 12 ++---
>  drivers/gpu/drm/i2c/tda998x_drv.c | 36 ++-
>  drivers/gpu/drm/i915/display/intel_dp.c   |  4 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 13 --
>  drivers/gpu/drm/nouveau/nouveau_connector.c   |  3 +-
>  drivers/gpu/drm/sti/sti_hdmi.c| 19 +---
>  drivers/gpu/drm/tegra/output.c| 28 ---
>  include/drm/drm_dp_helper.h   | 17 ---
>  13 files changed, 155 insertions(+), 94 deletions(-)
> 

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RE: [PATCH libdrm] amdgpu: add mmhub ras inject unit test

[Chen, Guchun]

Hi Christian,

Appreciate your concern and suggestion!
I am fine to remove the external file and move all test configurations into C 
code.
I will prepare patches to address this later.

Regards,
Guchun

-Original Message-
From: Koenig, Christian  
Sent: Monday, August 19, 2019 4:42 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Zhang, 
Hawking ; Li, Dennis ; Cui, Flora 
; Zhou1, Tao 
Cc: Li, Candice 
Subject: Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test

Hi Guchun,

yeah, I mean the requirement is perfectly valid and yes I agree that we should 
probably extend the command line parameters in this case.

The main problem is not the additional external library requirement, but rather 
that we need an external file additional to amdgpu_test.

See the test binary should be self containing in the sense that you only need 
the binary and nothing else so that we can give it QA or other testers.

Regards,
Christian.

Am 19.08.19 um 10:09 schrieb Chen, Guchun:
> Hi Christian,
>
> Yes, we already have functionality to select one specific test from the 
> command line, but that command line is limited.
>
> It only allows user to select one general test, like ras test, but inside ras 
> test, it has the enable/disable/error inject test respectively. Now what we 
> are talking about is exactly the inject test. We support plenty of ras inject 
> test in submodules like GFX, UMC, MMHUB. So without a command extension, when 
> we run RAS error inject test, we will see all inject tests in different sub 
> IP blocks are performed. My previous concern is the experience is not good if 
> user wants to run one special ras inject test in sub block like UMC. However, 
> I had one offline discussion with Hawking just now. We are now fine to 
> maintain the test configuration in C code for upstream. This will keep 
> amdgpu_test not depending on other external libraries.
>
> Regards,
> Guchun
>
> -Original Message-
> From: Koenig, Christian 
> Sent: Monday, August 19, 2019 3:53 PM
> To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; 
> Zhang, Hawking ; Li, Dennis 
> ; Cui, Flora ; Zhou1, Tao 
> 
> Cc: Li, Candice 
> Subject: Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test
>
> Hi Guchun,
>
>> Put all tests in c code, and extend the args when running amdgpu_test, which 
>> will allow user can run special RAS test.
> Ah! Sounds like we have just a misunderstanding here. As far as I know we 
> already have the functionality to select only specific tests to run from the 
> command line of amdgpu_test.
>
> That's actually the background reason why we use the CUnit framework.
>
> I haven't used that functionality in a long time, could be that it is broken 
> or something. But at least in theory it should be there.
>
> Regards,
> Christian.
>
> Am 19.08.19 um 09:48 schrieb Chen, Guchun:
>> Hi Christian,
>>
>> Thanks for your suggestion.
>> Regarding the configuration file moving to test/amdgpu, I am fine with this.
>>
>> But reg putting all the tests in C code, though it looks like the unit test 
>> can stay self containing, but without one independent configuration file, 
>> user will find it's inconvenient when performing the tests.
>> For example, if we move all RAS inject tests into C code, however, if the 
>> user only cares the RAS unit test in certain module/submodule test, he/she 
>> would not like to see inject tests in all modules run after launching 
>> amdgpu_test, so it's not friendly to user.
>> Anyway, your suggestion still makes sense, as amdgpu_test should get rid of 
>> other external packages except CUnit framework.
>>
>> So we still the balance between above two cases:
>> 1. Make amdgpu_test self containing without dependency on other external 
>> packages.
>> 2. Allow user can configure the tests when running amdgpu_test.
>>
>> Then the possible solutions I can illustrate are:
>> 1. Still keep one configuration file, but not in json format. It’s a normal 
>> configuration file, we will add code in amdgpu_test to parse the 
>> configuration file, and remove all json APIs.
>> 2. Put all tests in c code, and extend the args when running amdgpu_test, 
>> which will allow user can run special RAS test.
>>
>> I am opened to above two solutions or other missed ones.
>>
>> Regards,
>> Guchun
>>
>> -Original Message-
>> From: Koenig, Christian 
>> Sent: Monday, August 19, 2019 3:14 PM
>> To: Chen, Guchun ; 
>> amd-gfx@lists.freedesktop.org; Zhang, Hawking 
>> ; Li, Dennis ; Cui, Flora 
>> ; Zhou1, Tao 
>> Cc: Li, Candice 
>> Subject: Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test
>>
>> Hi Guchun,
>>
>> in this case this is a bit awkward implemented.
>>
>> See the files in the data directory are for installation together with the 
>> libdrm library and NOT for the unit tests. Please move the file to 
>> tests/amdgpu instead.
>>
>> I would also re-consider this approach since we intentionally use the CUnit 
>> framework to avoid dependencies on external libraries 

Re: [PATCH] drm/amdgpu/psp: move TMR to cpu invisible vram region

[Koenig, Christian]

OH, STOP!  Good that we talked about that because that would have caused quite 
a bunch of trouble.

The case in amdgpu_ttm_init() would break, we intentionally reserve memory at 
the beginning of the visible space here to avoid problem switching between 
VBIOS and KMS.

I suggest to first add a dummy pointer to amdgpu_ttm_init() to fix this before 
you apply this patch.

Regards,
Christian.

Am 19.08.19 um 10:16 schrieb Yin, Tianci (Rico):
Thanks very much Christian!

I scanned the whole code, only two functions pass in NULL cpu_addr,
amdgpu_ttm_init() and gfx_v9_0_ngg_create_buf(),
but the related BOs are not further mapped for cpu access.
so I think this change is safe.



From: Christian König 

Sent: Monday, August 19, 2019 16:07
To: Yin, Tianci (Rico) ; 
amd-gfx@lists.freedesktop.org 

Cc: Xiao, Jack ; Yuan, Xiaojie 
; Zhang, Hawking 

Subject: Re: [PATCH] drm/amdgpu/psp: move TMR to cpu invisible vram region

Am 19.08.19 um 10:05 schrieb Tianci Yin:
> From: "Tianci.Yin" 
>
> so that more visible vram can be available for umd.
>
> Signed-off-by: Tianci.Yin 

Assuming that you checked that we don't have other users who are using
amdgpu_bo_create_kernel() without a CPU pointer this patch is
Reviewed-by: Christian König 
.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 4 ++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h| 1 -
>   3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 1059771..0476790 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -246,8 +246,9 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
>bp.size = size;
>bp.byte_align = align;
>bp.domain = domain;
> - bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
> - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> + bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
> + : AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
> + bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
>bp.type = ttm_bo_type_kernel;
>bp.resv = NULL;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 7715c0d..5e7fbbe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -264,7 +264,7 @@ static int psp_tmr_init(struct psp_context *psp)
>
>ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
>  AMDGPU_GEM_DOMAIN_VRAM,
> -   >tmr_bo, >tmr_mc_addr, 
> >tmr_buf);
> +   >tmr_bo, >tmr_mc_addr, NULL);
>
>return ret;
>   }
> @@ -1215,7 +1215,7 @@ static int psp_hw_fini(void *handle)
>
>psp_ring_destroy(psp, PSP_RING_TYPE__KM);
>
> - amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, >tmr_buf);
> + amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, NULL);
>amdgpu_bo_free_kernel(>fw_pri_bo,
>  >fw_pri_mc_addr, >fw_pri_buf);
>amdgpu_bo_free_kernel(>fence_buf_bo,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> index 0029fa2..48b057d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> @@ -172,7 +172,6 @@ struct psp_context
>/* tmr buffer */
>struct amdgpu_bo*tmr_bo;
>uint64_ttmr_mc_addr;
> - void*tmr_buf;
>
>/* asd firmware and buffer */
>const struct firmware   *asd_fw;


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Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test

[Koenig, Christian]

Hi Guchun,

yeah, I mean the requirement is perfectly valid and yes I agree that we 
should probably extend the command line parameters in this case.

The main problem is not the additional external library requirement, but 
rather that we need an external file additional to amdgpu_test.

See the test binary should be self containing in the sense that you only 
need the binary and nothing else so that we can give it QA or other testers.

Regards,
Christian.

Am 19.08.19 um 10:09 schrieb Chen, Guchun:
> Hi Christian,
>
> Yes, we already have functionality to select one specific test from the 
> command line, but that command line is limited.
>
> It only allows user to select one general test, like ras test, but inside ras 
> test, it has the enable/disable/error inject test respectively. Now what we 
> are talking about is exactly the inject test. We support plenty of ras inject 
> test in submodules like GFX, UMC, MMHUB. So without a command extension, when 
> we run RAS error inject test, we will see all inject tests in different sub 
> IP blocks are performed. My previous concern is the experience is not good if 
> user wants to run one special ras inject test in sub block like UMC. However, 
> I had one offline discussion with Hawking just now. We are now fine to 
> maintain the test configuration in C code for upstream. This will keep 
> amdgpu_test not depending on other external libraries.
>
> Regards,
> Guchun
>
> -Original Message-
> From: Koenig, Christian 
> Sent: Monday, August 19, 2019 3:53 PM
> To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Zhang, 
> Hawking ; Li, Dennis ; Cui, Flora 
> ; Zhou1, Tao 
> Cc: Li, Candice 
> Subject: Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test
>
> Hi Guchun,
>
>> Put all tests in c code, and extend the args when running amdgpu_test, which 
>> will allow user can run special RAS test.
> Ah! Sounds like we have just a misunderstanding here. As far as I know we 
> already have the functionality to select only specific tests to run from the 
> command line of amdgpu_test.
>
> That's actually the background reason why we use the CUnit framework.
>
> I haven't used that functionality in a long time, could be that it is broken 
> or something. But at least in theory it should be there.
>
> Regards,
> Christian.
>
> Am 19.08.19 um 09:48 schrieb Chen, Guchun:
>> Hi Christian,
>>
>> Thanks for your suggestion.
>> Regarding the configuration file moving to test/amdgpu, I am fine with this.
>>
>> But reg putting all the tests in C code, though it looks like the unit test 
>> can stay self containing, but without one independent configuration file, 
>> user will find it's inconvenient when performing the tests.
>> For example, if we move all RAS inject tests into C code, however, if the 
>> user only cares the RAS unit test in certain module/submodule test, he/she 
>> would not like to see inject tests in all modules run after launching 
>> amdgpu_test, so it's not friendly to user.
>> Anyway, your suggestion still makes sense, as amdgpu_test should get rid of 
>> other external packages except CUnit framework.
>>
>> So we still the balance between above two cases:
>> 1. Make amdgpu_test self containing without dependency on other external 
>> packages.
>> 2. Allow user can configure the tests when running amdgpu_test.
>>
>> Then the possible solutions I can illustrate are:
>> 1. Still keep one configuration file, but not in json format. It’s a normal 
>> configuration file, we will add code in amdgpu_test to parse the 
>> configuration file, and remove all json APIs.
>> 2. Put all tests in c code, and extend the args when running amdgpu_test, 
>> which will allow user can run special RAS test.
>>
>> I am opened to above two solutions or other missed ones.
>>
>> Regards,
>> Guchun
>>
>> -Original Message-
>> From: Koenig, Christian 
>> Sent: Monday, August 19, 2019 3:14 PM
>> To: Chen, Guchun ; amd-gfx@lists.freedesktop.org;
>> Zhang, Hawking ; Li, Dennis
>> ; Cui, Flora ; Zhou1, Tao
>> 
>> Cc: Li, Candice 
>> Subject: Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test
>>
>> Hi Guchun,
>>
>> in this case this is a bit awkward implemented.
>>
>> See the files in the data directory are for installation together with the 
>> libdrm library and NOT for the unit tests. Please move the file to 
>> tests/amdgpu instead.
>>
>> I would also re-consider this approach since we intentionally use the CUnit 
>> framework to avoid dependencies on external libraries like json and external 
>> files.
>>
>> We should probably better configure the tests directly in the C code so that 
>> the unit test stays self containing.
>>
>> Regards,
>> Christian.
>>
>> Am 19.08.19 um 05:16 schrieb Chen, Guchun:
>>> Hi Christian,
>>>
>>> Yes, we added one configuration file named "amdgpu_ras.json" for RAS inject 
>>> unit test to drm master branch.
>>> This unit test will be maintained to illustrate all the RAS tests we 
>>> absolutely support in IP 

Re: [PATCH] drm/amdgpu/psp: move TMR to cpu invisible vram region

[Yin, Tianci (Rico)]

Thanks very much Christian!

I scanned the whole code, only two functions pass in NULL cpu_addr,
amdgpu_ttm_init() and gfx_v9_0_ngg_create_buf(),
but the related BOs are not further mapped for cpu access.
so I think this change is safe.



From: Christian König 
Sent: Monday, August 19, 2019 16:07
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org 

Cc: Xiao, Jack ; Yuan, Xiaojie ; 
Zhang, Hawking 
Subject: Re: [PATCH] drm/amdgpu/psp: move TMR to cpu invisible vram region

Am 19.08.19 um 10:05 schrieb Tianci Yin:
> From: "Tianci.Yin" 
>
> so that more visible vram can be available for umd.
>
> Signed-off-by: Tianci.Yin 

Assuming that you checked that we don't have other users who are using
amdgpu_bo_create_kernel() without a CPU pointer this patch is
Reviewed-by: Christian König .

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 4 ++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h| 1 -
>   3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 1059771..0476790 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -246,8 +246,9 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
>bp.size = size;
>bp.byte_align = align;
>bp.domain = domain;
> - bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
> - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> + bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
> + : AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
> + bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
>bp.type = ttm_bo_type_kernel;
>bp.resv = NULL;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 7715c0d..5e7fbbe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -264,7 +264,7 @@ static int psp_tmr_init(struct psp_context *psp)
>
>ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
>  AMDGPU_GEM_DOMAIN_VRAM,
> -   >tmr_bo, >tmr_mc_addr, 
> >tmr_buf);
> +   >tmr_bo, >tmr_mc_addr, NULL);
>
>return ret;
>   }
> @@ -1215,7 +1215,7 @@ static int psp_hw_fini(void *handle)
>
>psp_ring_destroy(psp, PSP_RING_TYPE__KM);
>
> - amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, >tmr_buf);
> + amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, NULL);
>amdgpu_bo_free_kernel(>fw_pri_bo,
>  >fw_pri_mc_addr, >fw_pri_buf);
>amdgpu_bo_free_kernel(>fence_buf_bo,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> index 0029fa2..48b057d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> @@ -172,7 +172,6 @@ struct psp_context
>/* tmr buffer */
>struct amdgpu_bo*tmr_bo;
>uint64_ttmr_mc_addr;
> - void*tmr_buf;
>
>/* asd firmware and buffer */
>const struct firmware   *asd_fw;

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RE: [PATCH libdrm] amdgpu: add mmhub ras inject unit test

[Chen, Guchun]

Hi Christian,

Yes, we already have functionality to select one specific test from the command 
line, but that command line is limited.

It only allows user to select one general test, like ras test, but inside ras 
test, it has the enable/disable/error inject test respectively. Now what we are 
talking about is exactly the inject test. We support plenty of ras inject test 
in submodules like GFX, UMC, MMHUB. So without a command extension, when we run 
RAS error inject test, we will see all inject tests in different sub IP blocks 
are performed. My previous concern is the experience is not good if user wants 
to run one special ras inject test in sub block like UMC. However, I had one 
offline discussion with Hawking just now. We are now fine to maintain the test 
configuration in C code for upstream. This will keep amdgpu_test not depending 
on other external libraries.

Regards,
Guchun

-Original Message-
From: Koenig, Christian  
Sent: Monday, August 19, 2019 3:53 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Zhang, 
Hawking ; Li, Dennis ; Cui, Flora 
; Zhou1, Tao 
Cc: Li, Candice 
Subject: Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test

Hi Guchun,

> Put all tests in c code, and extend the args when running amdgpu_test, which 
> will allow user can run special RAS test.
Ah! Sounds like we have just a misunderstanding here. As far as I know we 
already have the functionality to select only specific tests to run from the 
command line of amdgpu_test.

That's actually the background reason why we use the CUnit framework.

I haven't used that functionality in a long time, could be that it is broken or 
something. But at least in theory it should be there.

Regards,
Christian.

Am 19.08.19 um 09:48 schrieb Chen, Guchun:
> Hi Christian,
>
> Thanks for your suggestion.
> Regarding the configuration file moving to test/amdgpu, I am fine with this.
>
> But reg putting all the tests in C code, though it looks like the unit test 
> can stay self containing, but without one independent configuration file, 
> user will find it's inconvenient when performing the tests.
> For example, if we move all RAS inject tests into C code, however, if the 
> user only cares the RAS unit test in certain module/submodule test, he/she 
> would not like to see inject tests in all modules run after launching 
> amdgpu_test, so it's not friendly to user.
> Anyway, your suggestion still makes sense, as amdgpu_test should get rid of 
> other external packages except CUnit framework.
>
> So we still the balance between above two cases:
> 1. Make amdgpu_test self containing without dependency on other external 
> packages.
> 2. Allow user can configure the tests when running amdgpu_test.
>
> Then the possible solutions I can illustrate are:
> 1. Still keep one configuration file, but not in json format. It’s a normal 
> configuration file, we will add code in amdgpu_test to parse the 
> configuration file, and remove all json APIs.
> 2. Put all tests in c code, and extend the args when running amdgpu_test, 
> which will allow user can run special RAS test.
>
> I am opened to above two solutions or other missed ones.
>
> Regards,
> Guchun
>
> -Original Message-
> From: Koenig, Christian 
> Sent: Monday, August 19, 2019 3:14 PM
> To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; 
> Zhang, Hawking ; Li, Dennis 
> ; Cui, Flora ; Zhou1, Tao 
> 
> Cc: Li, Candice 
> Subject: Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test
>
> Hi Guchun,
>
> in this case this is a bit awkward implemented.
>
> See the files in the data directory are for installation together with the 
> libdrm library and NOT for the unit tests. Please move the file to 
> tests/amdgpu instead.
>
> I would also re-consider this approach since we intentionally use the CUnit 
> framework to avoid dependencies on external libraries like json and external 
> files.
>
> We should probably better configure the tests directly in the C code so that 
> the unit test stays self containing.
>
> Regards,
> Christian.
>
> Am 19.08.19 um 05:16 schrieb Chen, Guchun:
>> Hi Christian,
>>
>> Yes, we added one configuration file named "amdgpu_ras.json" for RAS inject 
>> unit test to drm master branch.
>> This unit test will be maintained to illustrate all the RAS tests we 
>> absolutely support in IP modules/submodules.
>>
>> Regards,
>> Guchun
>>
>> -Original Message-
>> From: Christian König 
>> Sent: Friday, August 16, 2019 7:12 PM
>> To: Chen, Guchun ; 
>> amd-gfx@lists.freedesktop.org; Zhang, Hawking 
>> ; Li, Dennis ; Cui, Flora 
>> ; Zhou1, Tao 
>> Cc: Li, Candice 
>> Subject: Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test
>>
>> Well this doesn't look like C to me. Did we added a configuration file for 
>> the ras unit tests or something like that?
>>
>> Christian.
>>
>> Am 16.08.19 um 13:04 schrieb Guchun Chen:
>>> Change-Id: Ia76b95162f5f6f419f70b53ef443bceaf2e092e0
>>> Signed-off-by: Guchun Chen 
>>> ---
>>> 

Re: [PATCH] drm/amdgpu/psp: move TMR to cpu invisible vram region

[Christian König]

Am 19.08.19 um 10:05 schrieb Tianci Yin:

From: "Tianci.Yin" 

so that more visible vram can be available for umd.

Signed-off-by: Tianci.Yin 


Assuming that you checked that we don't have other users who are using 
amdgpu_bo_create_kernel() without a CPU pointer this patch is 
Reviewed-by: Christian König .



---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h| 1 -
  3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1059771..0476790 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -246,8 +246,9 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
bp.size = size;
bp.byte_align = align;
bp.domain = domain;
-   bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-   AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+   bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
+   : AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
+   bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

index 7715c0d..5e7fbbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -264,7 +264,7 @@ static int psp_tmr_init(struct psp_context *psp)
  
  	ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,

  AMDGPU_GEM_DOMAIN_VRAM,
- >tmr_bo, >tmr_mc_addr, 
>tmr_buf);
+ >tmr_bo, >tmr_mc_addr, NULL);
  
  	return ret;

  }
@@ -1215,7 +1215,7 @@ static int psp_hw_fini(void *handle)
  
  	psp_ring_destroy(psp, PSP_RING_TYPE__KM);
  
-	amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, >tmr_buf);

+   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, NULL);
amdgpu_bo_free_kernel(>fw_pri_bo,
  >fw_pri_mc_addr, >fw_pri_buf);
amdgpu_bo_free_kernel(>fence_buf_bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 0029fa2..48b057d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -172,7 +172,6 @@ struct psp_context
/* tmr buffer */
struct amdgpu_bo*tmr_bo;
uint64_ttmr_mc_addr;
-   void*tmr_buf;
  
  	/* asd firmware and buffer */

const struct firmware   *asd_fw;


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[PATCH] drm/amdgpu/psp: move TMR to cpu invisible vram region

[Tianci Yin]

From: "Tianci.Yin" 

so that more visible vram can be available for umd.

Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h| 1 -
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1059771..0476790 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -246,8 +246,9 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
bp.size = size;
bp.byte_align = align;
bp.domain = domain;
-   bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-   AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+   bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
+   : AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
+   bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 7715c0d..5e7fbbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -264,7 +264,7 @@ static int psp_tmr_init(struct psp_context *psp)
 
ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
  AMDGPU_GEM_DOMAIN_VRAM,
- >tmr_bo, >tmr_mc_addr, 
>tmr_buf);
+ >tmr_bo, >tmr_mc_addr, NULL);
 
return ret;
 }
@@ -1215,7 +1215,7 @@ static int psp_hw_fini(void *handle)
 
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 
-   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, >tmr_buf);
+   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, NULL);
amdgpu_bo_free_kernel(>fw_pri_bo,
  >fw_pri_mc_addr, >fw_pri_buf);
amdgpu_bo_free_kernel(>fence_buf_bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 0029fa2..48b057d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -172,7 +172,6 @@ struct psp_context
/* tmr buffer */
struct amdgpu_bo*tmr_bo;
uint64_ttmr_mc_addr;
-   void*tmr_buf;
 
/* asd firmware and buffer */
const struct firmware   *asd_fw;
-- 
2.7.4

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Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test

[Koenig, Christian]

Hi Guchun,

> Put all tests in c code, and extend the args when running amdgpu_test, which 
> will allow user can run special RAS test.
Ah! Sounds like we have just a misunderstanding here. As far as I know 
we already have the functionality to select only specific tests to run 
from the command line of amdgpu_test.

That's actually the background reason why we use the CUnit framework.

I haven't used that functionality in a long time, could be that it is 
broken or something. But at least in theory it should be there.

Regards,
Christian.

Am 19.08.19 um 09:48 schrieb Chen, Guchun:
> Hi Christian,
>
> Thanks for your suggestion.
> Regarding the configuration file moving to test/amdgpu, I am fine with this.
>
> But reg putting all the tests in C code, though it looks like the unit test 
> can stay self containing, but without one independent configuration file, 
> user will find it's inconvenient when performing the tests.
> For example, if we move all RAS inject tests into C code, however, if the 
> user only cares the RAS unit test in certain module/submodule test, he/she 
> would not like to see inject tests in all modules run after launching 
> amdgpu_test, so it's not friendly to user.
> Anyway, your suggestion still makes sense, as amdgpu_test should get rid of 
> other external packages except CUnit framework.
>
> So we still the balance between above two cases:
> 1. Make amdgpu_test self containing without dependency on other external 
> packages.
> 2. Allow user can configure the tests when running amdgpu_test.
>
> Then the possible solutions I can illustrate are:
> 1. Still keep one configuration file, but not in json format. It’s a normal 
> configuration file, we will add code in amdgpu_test to parse the 
> configuration file, and remove all json APIs.
> 2. Put all tests in c code, and extend the args when running amdgpu_test, 
> which will allow user can run special RAS test.
>
> I am opened to above two solutions or other missed ones.
>
> Regards,
> Guchun
>
> -Original Message-
> From: Koenig, Christian 
> Sent: Monday, August 19, 2019 3:14 PM
> To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Zhang, 
> Hawking ; Li, Dennis ; Cui, Flora 
> ; Zhou1, Tao 
> Cc: Li, Candice 
> Subject: Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test
>
> Hi Guchun,
>
> in this case this is a bit awkward implemented.
>
> See the files in the data directory are for installation together with the 
> libdrm library and NOT for the unit tests. Please move the file to 
> tests/amdgpu instead.
>
> I would also re-consider this approach since we intentionally use the CUnit 
> framework to avoid dependencies on external libraries like json and external 
> files.
>
> We should probably better configure the tests directly in the C code so that 
> the unit test stays self containing.
>
> Regards,
> Christian.
>
> Am 19.08.19 um 05:16 schrieb Chen, Guchun:
>> Hi Christian,
>>
>> Yes, we added one configuration file named "amdgpu_ras.json" for RAS inject 
>> unit test to drm master branch.
>> This unit test will be maintained to illustrate all the RAS tests we 
>> absolutely support in IP modules/submodules.
>>
>> Regards,
>> Guchun
>>
>> -Original Message-
>> From: Christian König 
>> Sent: Friday, August 16, 2019 7:12 PM
>> To: Chen, Guchun ; amd-gfx@lists.freedesktop.org;
>> Zhang, Hawking ; Li, Dennis
>> ; Cui, Flora ; Zhou1, Tao
>> 
>> Cc: Li, Candice 
>> Subject: Re: [PATCH libdrm] amdgpu: add mmhub ras inject unit test
>>
>> Well this doesn't look like C to me. Did we added a configuration file for 
>> the ras unit tests or something like that?
>>
>> Christian.
>>
>> Am 16.08.19 um 13:04 schrieb Guchun Chen:
>>> Change-Id: Ia76b95162f5f6f419f70b53ef443bceaf2e092e0
>>> Signed-off-by: Guchun Chen 
>>> ---
>>> data/amdgpu_ras.json | 10 ++
>>> 1 file changed, 10 insertions(+)
>>>
>>> diff --git a/data/amdgpu_ras.json b/data/amdgpu_ras.json index
>>> 26fd9465..484f12f2 100644
>>> --- a/data/amdgpu_ras.json
>>> +++ b/data/amdgpu_ras.json
>>> @@ -121,6 +121,9 @@
>>> "utc_atcl2_cache_4k_bank": 111
>>> }
>>> },
>>> +"mmhub": {
>>> +"index": 3
>>> +},
>>> },
>>> "type": {
>>> "parity": 1,
>>> @@ -263,5 +266,12 @@
>>> "address": 0,
>>> "value": 0
>>> },
>>> +{
>>> +"name": "ras_mmhub.1.0",
>>> +"block": "mmhub",
>>> +"type": "single_correctable",
>>> +"address": 0,
>>> +"value": 0
>>> +},
>>> ]
>>> }

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