RE: [PATCH] drm/amdgpu: Navi12 SRIOV VF doesn't load TOC
Reviewed-by: Emily Deng
>-Original Message-
>From: Zhao, Jiange
>Sent: Thursday, September 12, 2019 1:22 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Nieto, David M ; Deng, Emily
>; Koenig, Christian ;
>Zhao, Jiange
>Subject: [PATCH] drm/amdgpu: Navi12 SRIOV VF doesn't load TOC
>
>From: Jiange Zhao
>
>In SRIOV case, the autoload sequence is the same
>
>as bare metal, except VF won't load TOC.
>
>Signed-off-by: Jiange Zhao
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>index f90a0cd12827..762c97ce8251 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>@@ -253,7 +253,8 @@ static int psp_tmr_init(struct psp_context *psp)
>
> /* For ASICs support RLC autoload, psp will parse the toc
>* and calculate the total size of TMR needed */
>- if (psp->toc_start_addr &&
>+ if (!amdgpu_sriov_vf(psp->adev) &&
>+ psp->toc_start_addr &&
> psp->toc_bin_size &&
> psp->fw_pri_buf) {
> ret = psp_load_toc(psp, _size);
>@@ -1305,9 +1306,6 @@ int psp_rlc_autoload_start(struct psp_context *psp)
> int ret;
> struct psp_gfx_cmd_resp *cmd;
>
>- if (amdgpu_sriov_vf(psp->adev))
>- return 0;
>-
> cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
> if (!cmd)
> return -ENOMEM;
>--
>2.20.1
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[PATCH] drm/amdgpu: Navi12 SRIOV VF doesn't load TOC
From: Jiange Zhao
In SRIOV case, the autoload sequence is the same
as bare metal, except VF won't load TOC.
Signed-off-by: Jiange Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index f90a0cd12827..762c97ce8251 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -253,7 +253,8 @@ static int psp_tmr_init(struct psp_context *psp)
/* For ASICs support RLC autoload, psp will parse the toc
* and calculate the total size of TMR needed */
- if (psp->toc_start_addr &&
+ if (!amdgpu_sriov_vf(psp->adev) &&
+ psp->toc_start_addr &&
psp->toc_bin_size &&
psp->fw_pri_buf) {
ret = psp_load_toc(psp, _size);
@@ -1305,9 +1306,6 @@ int psp_rlc_autoload_start(struct psp_context *psp)
int ret;
struct psp_gfx_cmd_resp *cmd;
- if (amdgpu_sriov_vf(psp->adev))
- return 0;
-
cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
if (!cmd)
return -ENOMEM;
--
2.20.1
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RE: [PATCH] drm/amdgpu: For Navi12 SRIOV VF, register mailbox functions
Reviewed-by: Emily Deng
>-Original Message-
>From: Zhao, Jiange
>Sent: Wednesday, September 11, 2019 6:25 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Nieto, David M ; Deng, Emily
>; Koenig, Christian ;
>Zhao, Jiange
>Subject: [PATCH] drm/amdgpu: For Navi12 SRIOV VF, register mailbox
>functions
>
>From: Jiange Zhao
>
>Mailbox functions and interrupts are only for Navi12 VF.
>
>Register functions and irqs during initialization.
>
>Signed-off-by: Jiange Zhao
>---
> drivers/gpu/drm/amd/amdgpu/nv.c | 19 +++
> 1 file changed, 19 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>b/drivers/gpu/drm/amd/amdgpu/nv.c index a61f43c0c9df..4c24672be12a
>100644
>--- a/drivers/gpu/drm/amd/amdgpu/nv.c
>+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>@@ -53,6 +53,7 @@
> #include "vcn_v2_0.h"
> #include "dce_virtual.h"
> #include "mes_v10_1.h"
>+#include "mxgpu_nv.h"
>
> static const struct amd_ip_funcs nv_common_ip_funcs;
>
>@@ -426,6 +427,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
>
> adev->nbio.funcs->detect_hw_virt(adev);
>
>+ if (amdgpu_sriov_vf(adev))
>+ adev->virt.ops = _nv_virt_ops;
>+
> switch (adev->asic_type) {
> case CHIP_NAVI10:
> case CHIP_NAVI14:
>@@ -666,16 +670,31 @@ static int nv_common_early_init(void *handle)
> return -EINVAL;
> }
>
>+ if (amdgpu_sriov_vf(adev)) {
>+ amdgpu_virt_init_setting(adev);
>+ xgpu_nv_mailbox_set_irq_funcs(adev);
>+ }
>+
> return 0;
> }
>
> static int nv_common_late_init(void *handle) {
>+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+
>+ if (amdgpu_sriov_vf(adev))
>+ xgpu_nv_mailbox_get_irq(adev);
>+
> return 0;
> }
>
> static int nv_common_sw_init(void *handle) {
>+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+
>+ if (amdgpu_sriov_vf(adev))
>+ xgpu_nv_mailbox_add_irq_id(adev);
>+
> return 0;
> }
>
>--
>2.20.1
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RE: [PATCH] drm/amd/amdgpu: power up sdma_v4 for resume back period
Thanks review and originally want emphasize the sequence only needed at sdma v4 case. Thanks, Prike > -Original Message- > From: Quan, Evan > Sent: Thursday, September 12, 2019 10:20 AM > To: Liang, Prike ; amd-gfx@lists.freedesktop.org > Cc: Feng, Kenneth ; Huang, Ray > ; Liu, Aaron > Subject: RE: [PATCH] drm/amd/amdgpu: power up sdma_v4 for resume back > period > > It's better to say "sdma engine" or just "sdma" instead of "sdma_v4". > Anyway, the patch is reviewed-by: Evan Quan > > -Original Message- > From: Liang, Prike > Sent: Thursday, September 12, 2019 9:59 AM > To: amd-gfx@lists.freedesktop.org > Cc: Quan, Evan ; Feng, Kenneth > ; Huang, Ray ; Liu, Aaron > ; Liang, Prike > Subject: [PATCH] drm/amd/amdgpu: power up sdma_v4 for resume back > period > > The sdma_v4 should be ungated when the IP resume back, otherwise it will > hang up and resume time out error. > > Signed-off-by: Prike Liang > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 2 +- > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 ++ > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++ > 3 files changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c > index 357e45f..2632652 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c > @@ -951,6 +951,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct > amdgpu_device *adev, uint32_t block > case AMD_IP_BLOCK_TYPE_UVD: > case AMD_IP_BLOCK_TYPE_VCN: > case AMD_IP_BLOCK_TYPE_VCE: > + case AMD_IP_BLOCK_TYPE_SDMA: > if (swsmu) > ret = smu_dpm_set_power_gate(>smu, > block_type, gate); > else > @@ -959,7 +960,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct > amdgpu_device *adev, uint32_t block > break; > case AMD_IP_BLOCK_TYPE_GMC: > case AMD_IP_BLOCK_TYPE_ACP: > - case AMD_IP_BLOCK_TYPE_SDMA: > ret = ((adev)->powerplay.pp_funcs- > >set_powergating_by_smu( > (adev)->powerplay.pp_handle, block_type, > gate)); > break; > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > index d019b85..b536f04 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > @@ -1801,8 +1801,9 @@ static int sdma_v4_0_hw_init(void *handle) > int r; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > - if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs > && > - adev->powerplay.pp_funcs- > >set_powergating_by_smu) > + if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs > && > + adev->powerplay.pp_funcs- > >set_powergating_by_smu) || > + adev->asic_type == CHIP_RENOIR) > amdgpu_dpm_set_powergating_by_smu(adev, > AMD_IP_BLOCK_TYPE_SDMA, false); > > if (!amdgpu_sriov_vf(adev)) > @@ -1829,8 +1830,9 @@ static int sdma_v4_0_hw_fini(void *handle) > sdma_v4_0_ctx_switch_enable(adev, false); > sdma_v4_0_enable(adev, false); > > - if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs > - && adev->powerplay.pp_funcs- > >set_powergating_by_smu) > + if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs > + && adev->powerplay.pp_funcs- > >set_powergating_by_smu) || > + adev->asic_type == CHIP_RENOIR) > amdgpu_dpm_set_powergating_by_smu(adev, > AMD_IP_BLOCK_TYPE_SDMA, true); > > return 0; > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > index e18bfce..a5fca51 100644 > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > @@ -400,6 +400,9 @@ int smu_dpm_set_power_gate(struct smu_context > *smu, uint32_t block_type, > case AMD_IP_BLOCK_TYPE_GFX: > ret = smu_gfx_off_control(smu, gate); > break; > + case AMD_IP_BLOCK_TYPE_SDMA: > + ret = smu_powergate_sdma(smu, gate); > + break; > default: > break; > } > -- > 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amd/powerplay: check SMU engine readiness before proceeding on S3 resume
Series is:
Reviewed-by: Alex Deucher
On Wed, Sep 11, 2019 at 7:50 AM Quan, Evan wrote:
>
> This is especially needed for non-psp loading way.
>
> Change-Id: I1e523168ed4892c34c8cbb66077c3f9288dd8006
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 28 ++
> 1 file changed, 23 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 25f3c9e1b404..95969c98a108 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1213,11 +1213,10 @@ static int smu_free_memory_pool(struct smu_context
> *smu)
> return ret;
> }
>
> -static int smu_hw_init(void *handle)
> +static int smu_start_smc_engine(struct smu_context *smu)
> {
> - int ret;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> - struct smu_context *smu = >smu;
> + struct amdgpu_device *adev = smu->adev;
> + int ret = 0;
>
> if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> if (adev->asic_type < CHIP_NAVI10) {
> @@ -1228,8 +1227,21 @@ static int smu_hw_init(void *handle)
> }
>
> ret = smu_check_fw_status(smu);
> + if (ret)
> + pr_err("SMC is not ready\n");
> +
> + return ret;
> +}
> +
> +static int smu_hw_init(void *handle)
> +{
> + int ret;
> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct smu_context *smu = >smu;
> +
> + ret = smu_start_smc_engine(smu);
> if (ret) {
> - pr_err("SMC firmware status is not correct\n");
> + pr_err("SMU is not ready yet!\n");
> return ret;
> }
>
> @@ -1389,6 +1401,12 @@ static int smu_resume(void *handle)
>
> mutex_lock(>mutex);
>
> + ret = smu_start_smc_engine(smu);
> + if (ret) {
> + pr_err("SMU is not ready yet!\n");
> + return ret;
> + }
> +
> ret = smu_smc_table_hw_init(smu, false);
> if (ret)
> goto failed;
> --
> 2.23.0
>
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Re: [PATCH] drm/amdgpu: fix build error without CONFIG_HSA_AMD (V2)
On 2019-09-11 2:52 a.m., S, Shirish wrote:
> If CONFIG_HSA_AMD is not set, build fails:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.o: In function
> `amdgpu_device_ip_early_init':
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626: undefined reference to
> `sched_policy'
>
> Use CONFIG_HSA_AMD to guard this.
>
> Fixes: 1abb680ad371 ("drm/amdgpu: disable gfxoff while use no H/W scheduling
> policy")
>
> V2: declare sched_policy in amdgpu.h and remove changes in amdgpu_device.c
Which branch is this for. V1 of this patch was already submitted to
amd-staging-drm-next. So unless you're planning to revert v1 and submit
v2, I was expecting to see a change that fixes up the previous patch,
rather than a patch that replaces it.
Regards,
Felix
>
> Signed-off-by: Shirish S
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 1030cb3..6ff02bb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -169,7 +169,11 @@ extern int amdgpu_discovery;
> extern int amdgpu_mes;
> extern int amdgpu_noretry;
> extern int amdgpu_force_asic_type;
> +#ifdef CONFIG_HSA_AMD
> extern int sched_policy;
> +#else
> +static const int sched_policy = KFD_SCHED_POLICY_HWS;
> +#endif
>
> #ifdef CONFIG_DRM_AMDGPU_SI
> extern int amdgpu_si_support;
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Re: [PATCH] drm/amdgpu: Fix mutex lock from atomic context.
That not what I meant. Let's say you handled one bad page interrupt and as a result have one bad page reserved. Now unrelated gfx ring timeout happens which triggers GPU reset and VRAM loss. When you come back from reset amdgpu_ras_reserve_bad_pages will be called but since last_reserved == data_count the bad page will not be reserved again, maybe we should just set data->last_reserved to 0 again if VRAM was lost during ASIC reset... Andrey From: Chen, Guchun Sent: 11 September 2019 21:53:03 To: Grodzovsky, Andrey; Zhou1, Tao; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: RE: [PATCH] drm/amdgpu: Fix mutex lock from atomic context. Comment inline. Regards, Guchun -Original Message- From: Grodzovsky, Andrey Sent: Wednesday, September 11, 2019 10:41 PM To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org Cc: Chen, Guchun ; Deucher, Alexander Subject: Re: [PATCH] drm/amdgpu: Fix mutex lock from atomic context. On second though this will break what about reserving bad pages when resetting GPU for non RAS error reason such as manual reset ,S3 or ring timeout, (amdgpu_ras_resume->amdgpu_ras_reset_gpu) so i will keep the code as is. Another possible issue in existing code - looks like no reservation will take place in those case even now as amdgpu_ras_reserve_bad_pages data->last_reserved will be equal to data->count , no ? Looks like for this case you need to add flag to FORCE reservation for all pages from 0 to data->counnt. [Guchun]Yes, last_reserved is not updated any more, unless we unload our driver. So it maybe always equal to data->count, then no new bad page will be reserved. I see we have one eeprom reset by user, can we put this last_reserved clean operation to user in the same stack as well? Andrey On 9/11/19 10:19 AM, Andrey Grodzovsky wrote: > I like this much more, I will relocate to > amdgpu_umc_process_ras_data_cb an push. > > Andrey > > On 9/10/19 11:08 PM, Zhou1, Tao wrote: >> amdgpu_ras_reserve_bad_pages is only used by umc block, so another >> approach is to move it into amdgpu_umc_process_ras_data_cb. >> Anyway, either way is OK and the patch is: >> >> Reviewed-by: Tao Zhou >> >>> -Original Message- >>> From: Andrey Grodzovsky >>> Sent: 2019年9月11日 3:41 >>> To: amd-gfx@lists.freedesktop.org >>> Cc: Chen, Guchun ; Zhou1, Tao >>> ; Deucher, Alexander ; >>> Grodzovsky, Andrey >>> Subject: [PATCH] drm/amdgpu: Fix mutex lock from atomic context. >>> >>> Problem: >>> amdgpu_ras_reserve_bad_pages was moved to amdgpu_ras_reset_gpu >>> because writing to EEPROM during ASIC reset was unstable. >>> But for ERREVENT_ATHUB_INTERRUPT amdgpu_ras_reset_gpu is called >>> directly from ISR context and so locking is not allowed. Also it's >>> irrelevant for this partilcular interrupt as this is generic RAS >>> interrupt and not memory errors specific. >>> >>> Fix: >>> Avoid calling amdgpu_ras_reserve_bad_pages if not in task context. >>> >>> Signed-off-by: Andrey Grodzovsky >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 4 +++- >>> 1 file changed, 3 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> index 012034d..dd5da3c 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> @@ -504,7 +504,9 @@ static inline int amdgpu_ras_reset_gpu(struct >>> amdgpu_device *adev, >>> /* save bad page to eeprom before gpu reset, >>>* i2c may be unstable in gpu reset >>>*/ >>> -amdgpu_ras_reserve_bad_pages(adev); >>> +if (in_task()) >>> +amdgpu_ras_reserve_bad_pages(adev); >>> + >>> if (atomic_cmpxchg(>in_recovery, 0, 1) == 0) >>> schedule_work(>recovery_work); >>> return 0; >>> -- >>> 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: Fix mutex lock from atomic context.
Comment inline. Regards, Guchun -Original Message- From: Grodzovsky, Andrey Sent: Wednesday, September 11, 2019 10:41 PM To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org Cc: Chen, Guchun ; Deucher, Alexander Subject: Re: [PATCH] drm/amdgpu: Fix mutex lock from atomic context. On second though this will break what about reserving bad pages when resetting GPU for non RAS error reason such as manual reset ,S3 or ring timeout, (amdgpu_ras_resume->amdgpu_ras_reset_gpu) so i will keep the code as is. Another possible issue in existing code - looks like no reservation will take place in those case even now as amdgpu_ras_reserve_bad_pages data->last_reserved will be equal to data->count , no ? Looks like for this case you need to add flag to FORCE reservation for all pages from 0 to data->counnt. [Guchun]Yes, last_reserved is not updated any more, unless we unload our driver. So it maybe always equal to data->count, then no new bad page will be reserved. I see we have one eeprom reset by user, can we put this last_reserved clean operation to user in the same stack as well? Andrey On 9/11/19 10:19 AM, Andrey Grodzovsky wrote: > I like this much more, I will relocate to > amdgpu_umc_process_ras_data_cb an push. > > Andrey > > On 9/10/19 11:08 PM, Zhou1, Tao wrote: >> amdgpu_ras_reserve_bad_pages is only used by umc block, so another >> approach is to move it into amdgpu_umc_process_ras_data_cb. >> Anyway, either way is OK and the patch is: >> >> Reviewed-by: Tao Zhou >> >>> -Original Message- >>> From: Andrey Grodzovsky >>> Sent: 2019年9月11日 3:41 >>> To: amd-gfx@lists.freedesktop.org >>> Cc: Chen, Guchun ; Zhou1, Tao >>> ; Deucher, Alexander ; >>> Grodzovsky, Andrey >>> Subject: [PATCH] drm/amdgpu: Fix mutex lock from atomic context. >>> >>> Problem: >>> amdgpu_ras_reserve_bad_pages was moved to amdgpu_ras_reset_gpu >>> because writing to EEPROM during ASIC reset was unstable. >>> But for ERREVENT_ATHUB_INTERRUPT amdgpu_ras_reset_gpu is called >>> directly from ISR context and so locking is not allowed. Also it's >>> irrelevant for this partilcular interrupt as this is generic RAS >>> interrupt and not memory errors specific. >>> >>> Fix: >>> Avoid calling amdgpu_ras_reserve_bad_pages if not in task context. >>> >>> Signed-off-by: Andrey Grodzovsky >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 4 +++- >>> 1 file changed, 3 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> index 012034d..dd5da3c 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> @@ -504,7 +504,9 @@ static inline int amdgpu_ras_reset_gpu(struct >>> amdgpu_device *adev, >>> /* save bad page to eeprom before gpu reset, >>> * i2c may be unstable in gpu reset >>> */ >>> - amdgpu_ras_reserve_bad_pages(adev); >>> + if (in_task()) >>> + amdgpu_ras_reserve_bad_pages(adev); >>> + >>> if (atomic_cmpxchg(>in_recovery, 0, 1) == 0) >>> schedule_work(>recovery_work); >>> return 0; >>> -- >>> 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: Navi10/12 VF doesn't support SMU
From: Jiange Zhao In SRIOV case, SMU and powerplay are handled in HV. VF shouldn't have control over SMU and powerplay. Signed-off-by: Jiange Zhao --- drivers/gpu/drm/amd/amdgpu/nv.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 4c24672be12a..fb097aa089da 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -438,7 +438,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _ih_ip_block); amdgpu_device_ip_block_add(adev, _v11_0_ip_block); if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && - is_support_sw_smu(adev)) + is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _v11_0_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _virtual_ip_block); @@ -449,7 +449,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _v10_0_ip_block); amdgpu_device_ip_block_add(adev, _v5_0_ip_block); if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && - is_support_sw_smu(adev)) + is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _v11_0_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); if (adev->enable_mes) @@ -461,7 +461,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _ih_ip_block); amdgpu_device_ip_block_add(adev, _v11_0_ip_block); if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && - is_support_sw_smu(adev)) + is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _v11_0_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _virtual_ip_block); @@ -472,7 +472,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _v10_0_ip_block); amdgpu_device_ip_block_add(adev, _v5_0_ip_block); if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && - is_support_sw_smu(adev)) + is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _v11_0_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/amdgpu: power up sdma_v4 for resume back period
The sdma_v4 should be ungated when the IP resume back, otherwise it will hang up and resume time out error. Signed-off-by: Prike Liang --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 ++ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++ 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 357e45f..2632652 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -951,6 +951,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block case AMD_IP_BLOCK_TYPE_UVD: case AMD_IP_BLOCK_TYPE_VCN: case AMD_IP_BLOCK_TYPE_VCE: + case AMD_IP_BLOCK_TYPE_SDMA: if (swsmu) ret = smu_dpm_set_power_gate(>smu, block_type, gate); else @@ -959,7 +960,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block break; case AMD_IP_BLOCK_TYPE_GMC: case AMD_IP_BLOCK_TYPE_ACP: - case AMD_IP_BLOCK_TYPE_SDMA: ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( (adev)->powerplay.pp_handle, block_type, gate)); break; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index d019b85..b536f04 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1801,8 +1801,9 @@ static int sdma_v4_0_hw_init(void *handle) int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->set_powergating_by_smu) + if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && + adev->powerplay.pp_funcs->set_powergating_by_smu) || + adev->asic_type == CHIP_RENOIR) amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); if (!amdgpu_sriov_vf(adev)) @@ -1829,8 +1830,9 @@ static int sdma_v4_0_hw_fini(void *handle) sdma_v4_0_ctx_switch_enable(adev, false); sdma_v4_0_enable(adev, false); - if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs - && adev->powerplay.pp_funcs->set_powergating_by_smu) + if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs + && adev->powerplay.pp_funcs->set_powergating_by_smu) || + adev->asic_type == CHIP_RENOIR) amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); return 0; diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index e18bfce..a5fca51 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -400,6 +400,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, case AMD_IP_BLOCK_TYPE_GFX: ret = smu_gfx_off_control(smu, gate); break; + case AMD_IP_BLOCK_TYPE_SDMA: + ret = smu_powergate_sdma(smu, gate); + break; default: break; } -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/amdgpu: power up sdma_v4 for resume back period
It's better to say "sdma engine" or just "sdma" instead of "sdma_v4". Anyway, the patch is reviewed-by: Evan Quan -Original Message- From: Liang, Prike Sent: Thursday, September 12, 2019 9:59 AM To: amd-gfx@lists.freedesktop.org Cc: Quan, Evan ; Feng, Kenneth ; Huang, Ray ; Liu, Aaron ; Liang, Prike Subject: [PATCH] drm/amd/amdgpu: power up sdma_v4 for resume back period The sdma_v4 should be ungated when the IP resume back, otherwise it will hang up and resume time out error. Signed-off-by: Prike Liang --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 ++ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++ 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 357e45f..2632652 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -951,6 +951,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block case AMD_IP_BLOCK_TYPE_UVD: case AMD_IP_BLOCK_TYPE_VCN: case AMD_IP_BLOCK_TYPE_VCE: + case AMD_IP_BLOCK_TYPE_SDMA: if (swsmu) ret = smu_dpm_set_power_gate(>smu, block_type, gate); else @@ -959,7 +960,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block break; case AMD_IP_BLOCK_TYPE_GMC: case AMD_IP_BLOCK_TYPE_ACP: - case AMD_IP_BLOCK_TYPE_SDMA: ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( (adev)->powerplay.pp_handle, block_type, gate)); break; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index d019b85..b536f04 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1801,8 +1801,9 @@ static int sdma_v4_0_hw_init(void *handle) int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->set_powergating_by_smu) + if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && + adev->powerplay.pp_funcs->set_powergating_by_smu) || + adev->asic_type == CHIP_RENOIR) amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); if (!amdgpu_sriov_vf(adev)) @@ -1829,8 +1830,9 @@ static int sdma_v4_0_hw_fini(void *handle) sdma_v4_0_ctx_switch_enable(adev, false); sdma_v4_0_enable(adev, false); - if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs - && adev->powerplay.pp_funcs->set_powergating_by_smu) + if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs + && adev->powerplay.pp_funcs->set_powergating_by_smu) || + adev->asic_type == CHIP_RENOIR) amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); return 0; diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index e18bfce..a5fca51 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -400,6 +400,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, case AMD_IP_BLOCK_TYPE_GFX: ret = smu_gfx_off_control(smu, gate); break; + case AMD_IP_BLOCK_TYPE_SDMA: + ret = smu_powergate_sdma(smu, gate); + break; default: break; } -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/connector: Allow max possible encoders to attach to a connector
From: Dhinakaran Pandiyan
Currently we restrict the number of encoders that can be linked to
a connector to 3, increase it to match the maximum number of encoders
that can be initialized(32).
To more effiently do that lets switch from an array of encoder ids to
bitmask.
v2: Fixing missed return on amdgpu_dm_connector_to_encoder()
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc: Alex Deucher
Cc: dri-de...@lists.freedesktop.org
Cc: intel-...@lists.freedesktop.org
Cc: nouv...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
.../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 ---
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 5 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++-
drivers/gpu/drm/drm_client_modeset.c | 3 +-
drivers/gpu/drm/drm_connector.c | 40 +++
drivers/gpu/drm/drm_probe_helper.c| 3 +-
drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_connector.c | 7 ++--
drivers/gpu/drm/radeon/radeon_connectors.c| 27 +
include/drm/drm_connector.h | 18 -
11 files changed, 55 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index ece55c8fa673..d8729285f731 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -217,11 +217,10 @@ amdgpu_connector_update_scratch_regs(struct drm_connector
*connector,
struct drm_encoder *encoder;
const struct drm_connector_helper_funcs *connector_funcs =
connector->helper_private;
bool connected;
- int i;
best_encoder = connector_funcs->best_encoder(connector);
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if ((encoder == best_encoder) && (status ==
connector_status_connected))
connected = true;
else
@@ -236,9 +235,8 @@ amdgpu_connector_find_encoder(struct drm_connector
*connector,
int encoder_type)
{
struct drm_encoder *encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if (encoder->encoder_type == encoder_type)
return encoder;
}
@@ -347,10 +345,9 @@ static struct drm_encoder *
amdgpu_connector_best_single_encoder(struct drm_connector *connector)
{
struct drm_encoder *encoder;
- int i;
/* pick the first one */
- drm_connector_for_each_possible_encoder(connector, encoder, i)
+ drm_connector_for_each_possible_encoder(connector, encoder)
return encoder;
return NULL;
@@ -1065,9 +1062,8 @@ amdgpu_connector_dvi_detect(struct drm_connector
*connector, bool force)
/* find analog encoder */
if (amdgpu_connector->dac_load_detect) {
struct drm_encoder *encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
continue;
@@ -1117,9 +1113,8 @@ amdgpu_connector_dvi_encoder(struct drm_connector
*connector)
{
struct amdgpu_connector *amdgpu_connector =
to_amdgpu_connector(connector);
struct drm_encoder *encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
if (amdgpu_connector->use_digital == true) {
if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
return encoder;
@@ -1134,7 +1129,7 @@ amdgpu_connector_dvi_encoder(struct drm_connector
*connector)
/* then check use digitial */
/* pick the first one */
- drm_connector_for_each_possible_encoder(connector, encoder, i)
+ drm_connector_for_each_possible_encoder(connector, encoder)
return encoder;
return NULL;
@@ -1271,9 +1266,8 @@ u16
amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn
{
struct drm_encoder *encoder;
struct amdgpu_encoder *amdgpu_encoder;
- int i;
- drm_connector_for_each_possible_encoder(connector, encoder, i) {
+ drm_connector_for_each_possible_encoder(connector, encoder) {
amdgpu_encoder =
[PATCH 4/4] mm/hmm/test: add self tests for HMM
Add self tests for HMM.
Signed-off-by: Ralph Campbell
---
MAINTAINERS|3 +
drivers/char/Kconfig | 11 +
drivers/char/Makefile |1 +
drivers/char/hmm_dmirror.c | 1504
include/Kbuild |1 +
include/uapi/linux/hmm_dmirror.h | 74 ++
tools/testing/selftests/vm/.gitignore |1 +
tools/testing/selftests/vm/Makefile|3 +
tools/testing/selftests/vm/config |3 +
tools/testing/selftests/vm/hmm-tests.c | 1304
tools/testing/selftests/vm/run_vmtests | 16 +
tools/testing/selftests/vm/test_hmm.sh | 105 ++
12 files changed, 3026 insertions(+)
create mode 100644 drivers/char/hmm_dmirror.c
create mode 100644 include/uapi/linux/hmm_dmirror.h
create mode 100644 tools/testing/selftests/vm/hmm-tests.c
create mode 100755 tools/testing/selftests/vm/test_hmm.sh
diff --git a/MAINTAINERS b/MAINTAINERS
index 43604d6ab96c..8ab242d91876 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7318,8 +7318,11 @@ M: Jérôme Glisse
L: linux...@kvack.org
S: Maintained
F: mm/hmm*
+F: drivers/char/hmm*
F: include/linux/hmm*
+F: include/uapi/linux/hmm*
F: Documentation/vm/hmm.rst
+F: tools/testing/selftests/vm/*hmm*
HOST AP DRIVER
M: Jouni Malinen
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 3e866885a405..b4ad868ead63 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -557,6 +557,17 @@ config ADI
and SSM (Silicon Secured Memory). Intended consumers of this
driver include crash and makedumpfile.
+config HMM_DMIRROR
+ tristate "HMM driver for testing Heterogeneous Memory Management"
+ depends on HMM_MIRROR
+ depends on DEVICE_PRIVATE
+ help
+ This is a pseudo device driver solely for testing HMM.
+ Say Y here if you want to build the HMM test driver.
+ Doing so will allow you to run tools/testing/selftest/vm/hmm-tests.
+
+ If in doubt, say "N".
+
endmenu
config RANDOM_TRUST_CPU
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index fbea7dd12932..c9ddd8e550c5 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -54,3 +54,4 @@ js-rtc-y = rtc.o
obj-$(CONFIG_XILLYBUS) += xillybus/
obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o
obj-$(CONFIG_ADI) += adi.o
+obj-$(CONFIG_HMM_DMIRROR) += hmm_dmirror.o
diff --git a/drivers/char/hmm_dmirror.c b/drivers/char/hmm_dmirror.c
new file mode 100644
index ..ccb4e03a03b5
--- /dev/null
+++ b/drivers/char/hmm_dmirror.c
@@ -0,0 +1,1504 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Authors: Jérôme Glisse
+ */
+/*
+ * This is a driver to exercice the HMM (heterogeneous memory management)
+ * mirror and zone device private memory migration APIs of the kernel.
+ * Userspace programs can register with the driver to mirror their own address
+ * space and can use the device to read/write any valid virtual address.
+ *
+ * In some ways it can also serve as an example driver for people wanting to
use
+ * HMM inside their own device driver.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define DMIRROR_NDEVICES 2
+#define DMIRROR_RANGE_FAULT_TIMEOUT1000
+#define DEVMEM_CHUNK_SIZE (256 * 1024 * 1024U)
+#define DEVMEM_CHUNKS_RESERVE 16
+
+static const struct dev_pagemap_ops dmirror_devmem_ops;
+static dev_t dmirror_dev;
+static struct platform_device *dmirror_platform_devices[DMIRROR_NDEVICES];
+static struct page *dmirror_zero_page;
+
+struct dmirror_device;
+
+struct dmirror_bounce {
+ void*ptr;
+ unsigned long size;
+ unsigned long addr;
+ unsigned long cpages;
+};
+
+#define DPT_SHIFT PAGE_SHIFT
+#define DPT_VALID (1UL << 0)
+#define DPT_WRITE (1UL << 1)
+#define DPT_DPAGE (1UL << 2)
+#define DPT_ZPAGE 0x20UL
+
+const uint64_t dmirror_hmm_flags[HMM_PFN_FLAG_MAX] = {
+ [HMM_PFN_VALID] = DPT_VALID,
+ [HMM_PFN_WRITE] = DPT_WRITE,
+ [HMM_PFN_DEVICE_PRIVATE] = DPT_DPAGE,
+};
+
+static const uint64_t dmirror_hmm_values[HMM_PFN_VALUE_MAX] = {
+
[PATCH 2/4] mm/hmm: allow snapshot of the special zero page
Allow hmm_range_fault() to return success (0) when the CPU pagetable
entry points to the special shared zero page.
The caller can then handle the zero page by possibly clearing device
private memory instead of DMAing a zero page.
Signed-off-by: Ralph Campbell
Cc: "Jérôme Glisse"
Cc: Jason Gunthorpe
Cc: Christoph Hellwig
---
mm/hmm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mm/hmm.c b/mm/hmm.c
index 06041d4399ff..7217912bef13 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -532,7 +532,7 @@ static int hmm_vma_handle_pte(struct mm_walk *walk,
unsigned long addr,
return -EBUSY;
} else if (IS_ENABLED(CONFIG_ARCH_HAS_PTE_SPECIAL) && pte_special(pte))
{
*pfn = range->values[HMM_PFN_SPECIAL];
- return -EFAULT;
+ return is_zero_pfn(pte_pfn(pte)) ? 0 : -EFAULT;
}
*pfn = hmm_device_entry_from_pfn(range, pte_pfn(pte)) | cpu_flags;
--
2.20.1
[PATCH 3/4] mm/hmm: allow hmm_range_fault() of mmap(PROT_NONE)
Allow hmm_range_fault() to return success (0) when the range has no access
(!(vma->vm_flags & VM_READ)). The range->pfns[] array will be filled with
range->values[HMM_PFN_NONE] in this case.
This allows the caller to get a snapshot of a range without having to
lookup the vma before calling hmm_range_fault().
If the call to hmm_range_fault() is not a snapshot, the caller can still
check that pfns have the desired access permissions.
Signed-off-by: Ralph Campbell
Cc: "Jérôme Glisse"
Cc: Jason Gunthorpe
Cc: Christoph Hellwig
---
mm/hmm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/mm/hmm.c b/mm/hmm.c
index 7217912bef13..16c834e5d1c0 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -795,7 +795,9 @@ static int hmm_vma_walk_test(unsigned long start,
*/
if (!(vma->vm_flags & VM_READ)) {
(void) hmm_pfns_fill(start, end, range, HMM_PFN_NONE);
- return -EPERM;
+
+ /* Skip this vma and continue processing the next vma. */
+ return 1;
}
return 0;
--
2.20.1
[PATCH 1/4] mm/hmm: make full use of walk_page_range()
hmm_range_fault() calls find_vma() and walk_page_range() in a loop.
This is unnecessary duplication since walk_page_range() calls find_vma()
in a loop already.
Simplify hmm_range_fault() by defining a walk_test() callback function
to filter unhandled vmas.
This also fixes a bug where hmm_range_fault() was not checking
start >= vma->vm_start before checking vma->vm_flags so hmm_range_fault()
could return an error based on the wrong vma for the requested range.
Signed-off-by: Ralph Campbell
Cc: "Jérôme Glisse"
Cc: Jason Gunthorpe
Cc: Christoph Hellwig
---
mm/hmm.c | 113 ---
1 file changed, 50 insertions(+), 63 deletions(-)
diff --git a/mm/hmm.c b/mm/hmm.c
index 902f5fa6bf93..06041d4399ff 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -252,18 +252,17 @@ static int hmm_vma_do_fault(struct mm_walk *walk,
unsigned long addr,
return -EFAULT;
}
-static int hmm_pfns_bad(unsigned long addr,
- unsigned long end,
- struct mm_walk *walk)
+static int hmm_pfns_fill(unsigned long addr,
+unsigned long end,
+struct hmm_range *range,
+enum hmm_pfn_value_e value)
{
- struct hmm_vma_walk *hmm_vma_walk = walk->private;
- struct hmm_range *range = hmm_vma_walk->range;
uint64_t *pfns = range->pfns;
unsigned long i;
i = (addr - range->start) >> PAGE_SHIFT;
for (; addr < end; addr += PAGE_SIZE, i++)
- pfns[i] = range->values[HMM_PFN_ERROR];
+ pfns[i] = range->values[value];
return 0;
}
@@ -584,7 +583,7 @@ static int hmm_vma_walk_pmd(pmd_t *pmdp,
}
return 0;
} else if (!pmd_present(pmd))
- return hmm_pfns_bad(start, end, walk);
+ return hmm_pfns_fill(start, end, range, HMM_PFN_ERROR);
if (pmd_devmap(pmd) || pmd_trans_huge(pmd)) {
/*
@@ -612,7 +611,7 @@ static int hmm_vma_walk_pmd(pmd_t *pmdp,
* recover.
*/
if (pmd_bad(pmd))
- return hmm_pfns_bad(start, end, walk);
+ return hmm_pfns_fill(start, end, range, HMM_PFN_ERROR);
ptep = pte_offset_map(pmdp, addr);
i = (addr - range->start) >> PAGE_SHIFT;
@@ -770,13 +769,36 @@ static int hmm_vma_walk_hugetlb_entry(pte_t *pte,
unsigned long hmask,
#define hmm_vma_walk_hugetlb_entry NULL
#endif /* CONFIG_HUGETLB_PAGE */
-static void hmm_pfns_clear(struct hmm_range *range,
- uint64_t *pfns,
- unsigned long addr,
- unsigned long end)
+static int hmm_vma_walk_test(unsigned long start,
+unsigned long end,
+struct mm_walk *walk)
{
- for (; addr < end; addr += PAGE_SIZE, pfns++)
- *pfns = range->values[HMM_PFN_NONE];
+ struct hmm_vma_walk *hmm_vma_walk = walk->private;
+ struct hmm_range *range = hmm_vma_walk->range;
+ struct vm_area_struct *vma = walk->vma;
+
+ /* If range is no longer valid, force retry. */
+ if (!range->valid)
+ return -EBUSY;
+
+ /*
+* Skip vma ranges that don't have struct page backing them or
+* map I/O devices directly.
+*/
+ if (vma->vm_flags & (VM_IO | VM_PFNMAP | VM_MIXEDMAP))
+ return -EFAULT;
+
+ /*
+* If the vma does not allow read access, then assume that it does not
+* allow write access either. HMM does not support architectures
+* that allow write without read.
+*/
+ if (!(vma->vm_flags & VM_READ)) {
+ (void) hmm_pfns_fill(start, end, range, HMM_PFN_NONE);
+ return -EPERM;
+ }
+
+ return 0;
}
/*
@@ -857,6 +879,7 @@ static const struct mm_walk_ops hmm_walk_ops = {
.pmd_entry = hmm_vma_walk_pmd,
.pte_hole = hmm_vma_walk_hole,
.hugetlb_entry = hmm_vma_walk_hugetlb_entry,
+ .test_walk = hmm_vma_walk_test,
};
/**
@@ -889,63 +912,27 @@ static const struct mm_walk_ops hmm_walk_ops = {
*/
long hmm_range_fault(struct hmm_range *range, unsigned int flags)
{
- const unsigned long device_vma = VM_IO | VM_PFNMAP | VM_MIXEDMAP;
- unsigned long start = range->start, end;
- struct hmm_vma_walk hmm_vma_walk;
+ unsigned long start = range->start;
+ struct hmm_vma_walk hmm_vma_walk = {
+ .range = range,
+ .last = start,
+ .flags = flags,
+ };
struct hmm *hmm = range->hmm;
- struct vm_area_struct *vma;
int ret;
lockdep_assert_held(>mmu_notifier.mm->mmap_sem);
do {
- /* If range is no longer valid force retry. */
- if (!range->valid)
- return -EBUSY;
-
- vma = find_vma(hmm->mmu_notifier.mm,
[PATCH 0/4] HMM tests and minor fixes
These changes are based on Jason's latest hmm branch. Patch 1 was previously posted here [1] but was dropped from the orginal series. Hopefully, the tests will reduce concerns about edge conditions. I'm sure more tests could be usefully added but I thought this was a good starting point. [1] https://lore.kernel.org/linux-mm/20190726005650.2566-6-rcampb...@nvidia.com/ Ralph Campbell (4): mm/hmm: make full use of walk_page_range() mm/hmm: allow snapshot of the special zero page mm/hmm: allow hmm_range_fault() of mmap(PROT_NONE) mm/hmm/test: add self tests for HMM MAINTAINERS|3 + drivers/char/Kconfig | 11 + drivers/char/Makefile |1 + drivers/char/hmm_dmirror.c | 1504 include/Kbuild |1 + include/uapi/linux/hmm_dmirror.h | 74 ++ mm/hmm.c | 117 +- tools/testing/selftests/vm/.gitignore |1 + tools/testing/selftests/vm/Makefile|3 + tools/testing/selftests/vm/config |3 + tools/testing/selftests/vm/hmm-tests.c | 1304 tools/testing/selftests/vm/run_vmtests | 16 + tools/testing/selftests/vm/test_hmm.sh | 105 ++ 13 files changed, 3079 insertions(+), 64 deletions(-) create mode 100644 drivers/char/hmm_dmirror.c create mode 100644 include/uapi/linux/hmm_dmirror.h create mode 100644 tools/testing/selftests/vm/hmm-tests.c create mode 100755 tools/testing/selftests/vm/test_hmm.sh -- 2.20.1
[Regression] 5.3-rc8 suspending from X broken with amdgpu
Hello, I am testing latest rc8/Linus git tree on my new Acer Nitro 5 (AN515-43-R8BF) Laptop. The box has an Ryzen7 3750H APU+RX 560x hybrid GPU(s). Suspending ( closing the Lid ) from tty without X up is working fine, however with X running doing the same does not work. The display remains black. It seems to be triggered from .. dcn10_hw_sequencer.c:932 dcn10_verify_allow_pstate_change_high.cold+0xc/0x229 [amdgpu] The dmesg is way to big to post there so I uploaded it: dmesg: http://crazy.dev.frugalware.org/Nitro5/dmesg.one.txt lspci: http://crazy.dev.frugalware.org/Nitro5/lspci.nnvv.txt http://crazy.dev.frugalware.org/Nitro5/lspci.txt config: http://crazy.dev.frugalware.org/Nitro5/config.nitro5-5.3-r8git I didn't tested any other rcX kernels so I cannot tell if all are affected, but 5.2.x kernels are working fine on this box. The dirty state of the build is because this patch, which fixes the NVME device on that box: https://lkml.org/lkml/2019/9/11/569 If you need more infos please let me know. Also I can test any kind patches. Best Regards, Gabriel C
Re: [PATCH 22/25] drm/amd/display: 3.4.51.1
Looks like the subject is wrong for this and patch 20: s/3.4/3.2/ Will modify before merge. Leo On 2019-09-10 9:54 a.m., sunpeng...@amd.com wrote: > From: Aric Cyr > > Signed-off-by: Aric Cyr > Acked-by: Leo Li > --- > drivers/gpu/drm/amd/display/dc/dc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dc.h > b/drivers/gpu/drm/amd/display/dc/dc.h > index 7c19ac71b424..3ecc42987b05 100644 > --- a/drivers/gpu/drm/amd/display/dc/dc.h > +++ b/drivers/gpu/drm/amd/display/dc/dc.h > @@ -39,7 +39,7 @@ > #include "inc/hw/dmcu.h" > #include "dml/display_mode_lib.h" > > -#define DC_VER "3.2.51" > +#define DC_VER "3.2.51.1" > > #define MAX_SURFACES 3 > #define MAX_PLANES 6 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/radeon: Bail earlier when radeon.cik_/si_support=0 is passed
> -Original Message- > From: Hans de Goede > Sent: Tuesday, September 10, 2019 5:36 AM > To: Michel Dänzer ; Deucher, Alexander > ; Koenig, Christian > ; Zhou, David(ChunMing) > > Cc: David Airlie ; dri-de...@lists.freedesktop.org; amd- > g...@lists.freedesktop.org; Daniel Vetter > Subject: Re: [PATCH] drm/radeon: Bail earlier when > radeon.cik_/si_support=0 is passed > > Hi, > > On 9/10/19 9:50 AM, Michel Dänzer wrote: > > On 2019-09-07 10:32 p.m., Hans de Goede wrote: > >> Bail from the pci_driver probe function instead of from the > >> drm_driver load function. > >> > >> This avoid /dev/dri/card0 temporarily getting registered and then > >> unregistered again, sending unwanted add / remove udev events to > >> userspace. > >> > >> Specifically this avoids triggering the (userspace) bug fixed by this > >> plymouth merge-request: > >> https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59 > >> > >> Note that despite that being an userspace bug, not sending > >> unnecessary udev events is a good idea in general. > >> > >> BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490 > >> Signed-off-by: Hans de Goede > > > > Reviewed-by: Michel Dänzer > > Thank you for the review. I've drm push rights, but I guess that radeon/amd > GPU patches are collected by someone @AMD, so I do not need to / should > not push this myself, right? I'll pick this up later this week when I get home from travel. Thanks! Alex > > > amdgpu should be changed correspondingly as well. > > Good point. I'm currently travelling (@plumbers) I can do this when I'm back > home, but feel free to beat me to it (if you do please Cc me to avoid double > work). > > Regards, > > Hans ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Fix mutex lock from atomic context.
On second though this will break what about reserving bad pages when resetting GPU for non RAS error reason such as manual reset ,S3 or ring timeout, (amdgpu_ras_resume->amdgpu_ras_reset_gpu) so i will keep the code as is. Another possible issue in existing code - looks like no reservation will take place in those case even now as amdgpu_ras_reserve_bad_pages data->last_reserved will be equal to data->count , no ? Looks like for this case you need to add flag to FORCE reservation for all pages from 0 to data->counnt. Andrey On 9/11/19 10:19 AM, Andrey Grodzovsky wrote: > I like this much more, I will relocate to > amdgpu_umc_process_ras_data_cb an push. > > Andrey > > On 9/10/19 11:08 PM, Zhou1, Tao wrote: >> amdgpu_ras_reserve_bad_pages is only used by umc block, so another >> approach is to move it into amdgpu_umc_process_ras_data_cb. >> Anyway, either way is OK and the patch is: >> >> Reviewed-by: Tao Zhou >> >>> -Original Message- >>> From: Andrey Grodzovsky >>> Sent: 2019年9月11日 3:41 >>> To: amd-gfx@lists.freedesktop.org >>> Cc: Chen, Guchun ; Zhou1, Tao >>> ; Deucher, Alexander >>> ; Grodzovsky, Andrey >>> >>> Subject: [PATCH] drm/amdgpu: Fix mutex lock from atomic context. >>> >>> Problem: >>> amdgpu_ras_reserve_bad_pages was moved to amdgpu_ras_reset_gpu >>> because writing to EEPROM during ASIC reset was unstable. >>> But for ERREVENT_ATHUB_INTERRUPT amdgpu_ras_reset_gpu is called >>> directly from ISR context and so locking is not allowed. Also it's >>> irrelevant for >>> this partilcular interrupt as this is generic RAS interrupt and not >>> memory >>> errors specific. >>> >>> Fix: >>> Avoid calling amdgpu_ras_reserve_bad_pages if not in task context. >>> >>> Signed-off-by: Andrey Grodzovsky >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 4 +++- >>> 1 file changed, 3 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> index 012034d..dd5da3c 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >>> @@ -504,7 +504,9 @@ static inline int amdgpu_ras_reset_gpu(struct >>> amdgpu_device *adev, >>> /* save bad page to eeprom before gpu reset, >>> * i2c may be unstable in gpu reset >>> */ >>> - amdgpu_ras_reserve_bad_pages(adev); >>> + if (in_task()) >>> + amdgpu_ras_reserve_bad_pages(adev); >>> + >>> if (atomic_cmpxchg(>in_recovery, 0, 1) == 0) >>> schedule_work(>recovery_work); >>> return 0; >>> -- >>> 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Fix mutex lock from atomic context.
I like this much more, I will relocate to amdgpu_umc_process_ras_data_cb an push. Andrey On 9/10/19 11:08 PM, Zhou1, Tao wrote: > amdgpu_ras_reserve_bad_pages is only used by umc block, so another approach > is to move it into amdgpu_umc_process_ras_data_cb. > Anyway, either way is OK and the patch is: > > Reviewed-by: Tao Zhou > >> -Original Message- >> From: Andrey Grodzovsky >> Sent: 2019年9月11日 3:41 >> To: amd-gfx@lists.freedesktop.org >> Cc: Chen, Guchun ; Zhou1, Tao >> ; Deucher, Alexander >> ; Grodzovsky, Andrey >> >> Subject: [PATCH] drm/amdgpu: Fix mutex lock from atomic context. >> >> Problem: >> amdgpu_ras_reserve_bad_pages was moved to amdgpu_ras_reset_gpu >> because writing to EEPROM during ASIC reset was unstable. >> But for ERREVENT_ATHUB_INTERRUPT amdgpu_ras_reset_gpu is called >> directly from ISR context and so locking is not allowed. Also it's >> irrelevant for >> this partilcular interrupt as this is generic RAS interrupt and not memory >> errors specific. >> >> Fix: >> Avoid calling amdgpu_ras_reserve_bad_pages if not in task context. >> >> Signed-off-by: Andrey Grodzovsky >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >> index 012034d..dd5da3c 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h >> @@ -504,7 +504,9 @@ static inline int amdgpu_ras_reset_gpu(struct >> amdgpu_device *adev, >> /* save bad page to eeprom before gpu reset, >> * i2c may be unstable in gpu reset >> */ >> -amdgpu_ras_reserve_bad_pages(adev); >> +if (in_task()) >> +amdgpu_ras_reserve_bad_pages(adev); >> + >> if (atomic_cmpxchg(>in_recovery, 0, 1) == 0) >> schedule_work(>recovery_work); >> return 0; >> -- >> 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 00/20] HDCP 1.4 Content Protection
On 2019-09-10 3:05 p.m., Bhawanpreet Lakha wrote: > This patch set introduces HDCP 1.4 capability to Asics starting with > Raven(DCN 1.0). > > This only introduces the ability to authenticate and encrypt the link. These > patches by themselves don't constitute a complete and compliant > HDCP content protection solution but are a requirement for such a solution. > > NOTE: The 7 patches by Ramalingam have already been merged to drm-misc > but are required to apply the HDCP patches on amd-staging-drm-next > Is there any change from the previous set that was sent on August 29? Please mark patches as v2 (git format-patch -v2) and note what changed in the patch description like so: v2: - did one change to the patch - changed something else Harry > Bhawanpreet Lakha (13): > drm/amdgpu: psp HDCP init > drm/amdgpu: psp DTM init > drm/amd/display: Add HDCP module > drm/amd/display: add PSP block to verify hdcp steps > drm/amd/display: Update hdcp display config > drm/amd/display: Create amdgpu_dm_hdcp > drm/amd/display: Create dpcd and i2c packing functions > drm/amd/display: Initialize HDCP work queue > drm/amd/display: Handle Content protection property changes > drm/amd/display: handle DP cpirq > drm/amd/display: Update CP property based on HW query > drm/amd/display: only enable HDCP for DCN+ > drm/amd/display: Add hdcp to Kconfig > > Ramalingam C (7): > drm: move content protection property to mode_config > drm: generic fn converting be24 to cpu and vice versa > drm: revocation check at drm subsystem > drm/hdcp: gathering hdcp related code into drm_hdcp.c > drm: Add Content protection type property > drm: uevent for connector status change > drm/hdcp: update content protection property with uevent > > Documentation/gpu/drm-kms-helpers.rst | 6 + > drivers/gpu/drm/Makefile | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 343 ++- > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 32 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 6 + > drivers/gpu/drm/amd/amdgpu/psp_v10_0.c| 40 +- > drivers/gpu/drm/amd/display/Kconfig | 8 + > drivers/gpu/drm/amd/display/Makefile | 7 + > .../gpu/drm/amd/display/amdgpu_dm/Makefile| 4 + > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 135 + > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 + > .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 342 +++ > .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h| 66 +++ > drivers/gpu/drm/amd/display/dc/Makefile | 4 + > drivers/gpu/drm/amd/display/dc/core/dc.c | 10 + > drivers/gpu/drm/amd/display/dc/core/dc_link.c | 31 + > drivers/gpu/drm/amd/display/dc/dc.h | 5 + > drivers/gpu/drm/amd/display/dc/dc_types.h | 7 + > drivers/gpu/drm/amd/display/dc/dm_cp_psp.h| 49 ++ > drivers/gpu/drm/amd/display/dc/hdcp/Makefile | 28 + > .../gpu/drm/amd/display/dc/hdcp/hdcp_msg.c| 324 +++ > .../gpu/drm/amd/display/dc/inc/core_types.h | 4 +- > .../gpu/drm/amd/display/include/hdcp_types.h | 96 > .../gpu/drm/amd/display/modules/hdcp/Makefile | 32 ++ > .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 426 ++ > .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 442 +++ > .../display/modules/hdcp/hdcp1_execution.c| 531 ++ > .../display/modules/hdcp/hdcp1_transition.c | 307 ++ > .../drm/amd/display/modules/hdcp/hdcp_ddc.c | 305 ++ > .../drm/amd/display/modules/hdcp/hdcp_log.c | 163 ++ > .../drm/amd/display/modules/hdcp/hdcp_log.h | 139 + > .../drm/amd/display/modules/hdcp/hdcp_psp.c | 328 +++ > .../drm/amd/display/modules/hdcp/hdcp_psp.h | 272 + > .../drm/amd/display/modules/inc/mod_hdcp.h| 289 ++ > drivers/gpu/drm/drm_atomic_uapi.c | 8 +- > drivers/gpu/drm/drm_connector.c | 111 ++-- > drivers/gpu/drm/drm_hdcp.c| 448 +++ > drivers/gpu/drm/drm_internal.h| 4 + > drivers/gpu/drm/drm_sysfs.c | 37 ++ > drivers/gpu/drm/i915/intel_hdcp.c | 9 +- > drivers/misc/mei/hdcp/mei_hdcp.c | 2 +- > include/drm/drm_connector.h | 15 +- > include/drm/drm_hdcp.h| 38 +- > include/drm/drm_mode_config.h | 12 + > include/drm/drm_sysfs.h | 5 +- > 45 files changed, 5407 insertions(+), 68 deletions(-) > create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c > create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h > create mode 100644 drivers/gpu/drm/amd/display/dc/dm_cp_psp.h > create mode 100644 drivers/gpu/drm/amd/display/dc/hdcp/Makefile > create mode 100644 drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c > create mode 100644 drivers/gpu/drm/amd/display/include/hdcp_types.h >
Re: [PATCH 14/14] drm/amdgpu: set TMZ bits in PTEs for secure bo (v2)
Am 11.09.19 um 13:50 schrieb Huang, Ray:
> From: Alex Deucher
>
> If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED), the TMZ bits
> of
> PTEs that belongs that bo should be set. Then psp is able to protect the pages
> of this bo to avoid the access from an "untrust" domain such as CPU.
>
> v1: design and draft the skeletion of tmz bits setting on PTEs (Alex)
> v2: return failure once create secure bo on no-tmz platform (Ray)
>
> Signed-off-by: Alex Deucher
> Reviewed-by: Huang Rui
> Signed-off-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 5 +
> 3 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 22eab74..5332104 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -222,7 +222,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
> *data,
> AMDGPU_GEM_CREATE_CPU_GTT_USWC |
> AMDGPU_GEM_CREATE_VRAM_CLEARED |
> AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
> - AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
> + AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
> + AMDGPU_GEM_CREATE_ENCRYPTED))
>
> return -EINVAL;
>
> @@ -230,6 +231,11 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
> *data,
> if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
> return -EINVAL;
>
> + if (!adev->tmz.enabled && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
> + DRM_ERROR("Cannot allocate secure buffer while tmz is
> disabled\n");
> + return -EINVAL;
> + }
> +
> /* create a gem object to contain this object in */
> if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
> AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
> @@ -251,6 +257,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
> *data,
> resv = vm->root.base.bo->tbo.resv;
> }
>
> + if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
> + /* XXX: pad out alignment to meet TMZ requirements */
> + }
> +
> r = amdgpu_gem_object_create(adev, size, args->in.alignment,
>(u32)(0x & args->in.domains),
>flags, ttm_bo_type_device, resv, );
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> index 5a3c177..286e2e2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> @@ -224,6 +224,16 @@ static inline bool amdgpu_bo_explicit_sync(struct
> amdgpu_bo *bo)
> return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
> }
>
> +/**
> + * amdgpu_bo_encrypted - return whether the bo is encrypted
> + */
> +static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
> +{
> + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> +
> + return adev->tmz.enabled && (bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED);
Checking the adev->tmz.enabled flags should be dropped here.
> +}
> +
> bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
> void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 3663655..8f00bb2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1434,6 +1434,8 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
> uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg
> *mem)
> {
> uint64_t flags = 0;
> + struct ttm_buffer_object *tbo = ttm_mem_reg_to_bo(mem);
> + struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
That's a clear NAK. The function is not necessarily called with
>mem, which is also the reason why this function doesn't gets the BO
as parameter.
Christian.
>
> if (mem && mem->mem_type != TTM_PL_SYSTEM)
> flags |= AMDGPU_PTE_VALID;
> @@ -1444,6 +1446,9 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm,
> struct ttm_mem_reg *mem)
> if (ttm->caching_state == tt_cached)
> flags |= AMDGPU_PTE_SNOOPED;
> }
> + if (amdgpu_bo_encrypted(abo)) {
> + flags |= AMDGPU_PTE_TMZ;
> + }
>
> return flags;
> }
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Re: [PATCH 00/14] drm/amdgpu: introduce secure buffer object support (trusted memory zone)
Patches #1-#4, #8, #9 are Reviewed-by: Christian König Patches #10, #11 are Acked-by: Christian König Patches #7 and the resulting workaround in patch #13 are a clear NAK. The ttm_mem_reg can't be used like this to get back to the ttm_bo object. Going to reply separately on patch #14 regarding this. Regards, Christian. Am 11.09.19 um 13:50 schrieb Huang, Ray: > Hi all, > > These series of patches introduce a feature to support secure buffer object. > The Trusted Memory Zone (TMZ) is a method to protect the contents being > written > to and read from memory. We use TMZ hardware memory protection scheme to > implement the secure buffer object support. > > TMZ is the page-level protection that hardware will detect the TMZ bit in the > page table entry to set the current page is encrypted. With this hardware > feature, we design a BO-level protection in kernel driver to provide a new > flag > AMDGPU_GEM_CREATE_ENCRYPTED to gem create ioctl to libdrm for the secure > buffer > allocation. And also provide the AMDGPU_CTX_ALLOC_FLAGS_SECURE to indicate the > context is trusted or not. If the BO is secure, then the data is encrypted, > only > the trusted IP blocks such as gfx, sdma, vcn are able to decrypt. CPU as the > un-trusted IP are unable to read the secure buffer. > > We will submit the new secure context interface later for libdrm, and create a > new test suite to verify the security feature in the libdrm unit tests. > > Suite id = 11: Name 'Security Tests status: ENABLED' > Test id 1: Name: 'allocate secure buffer test status: ENABLED' > Test id 2: Name: 'graphics command submission under secure context status: > ENABLED' > > Thanks, > Ray > > Alex Deucher (4): >drm/amdgpu: add UAPI for creating encrypted buffers >drm/amdgpu: add UAPI for creating secure contexts (v2) >drm/amdgpu: define the TMZ bit for the PTE >drm/amdgpu: set TMZ bits in PTEs for secure bo (v2) > > Huang Rui (10): >drm/amdgpu: add tmz feature parameter (v2) >drm/amdgpu: add amdgpu_tmz data structure >drm/amdgpu: add function to check tmz capability (v4) >drm/ttm: add helper to get buffer object with ttm_mem_reg >drm/amdgpu: revise the function to allocate secure context (v2) >drm/amdgpu: add tmz bit in frame control packet >drm/amdgpu: expand the emit tmz interface with trusted flag >drm/amdgpu: expand the context control interface with trust flag >drm/amdgpu: set trusted mode while the job is under secure context > (v2) >drm/amdgpu: modify the method to use mem under buffer object for > amdgpu_ttm_tt_pte_flags > > drivers/gpu/drm/amd/amdgpu/Makefile| 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 - > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 19 +--- > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 11 +++ > drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++- > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 +-- > drivers/gpu/drm/amd/amdgpu/amdgpu_job.h| 2 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 9 +++--- > drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c| 49 > ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h| 39 > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 23 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++ > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 20 +--- > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 +- > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 +++--- > drivers/gpu/drm/amd/amdgpu/nvd.h | 1 + > drivers/gpu/drm/amd/amdgpu/soc15d.h| 1 + > include/drm/ttm/ttm_bo_driver.h| 13 > include/uapi/drm/amdgpu_drm.h | 9 +- > 25 files changed, 230 insertions(+), 34 deletions(-) > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 01/14] drm/amdgpu: add UAPI for creating encrypted buffers
From: Alex Deucher
Add a flag to the GEM_CREATE ioctl to create encrypted buffers.
Buffers with this flag set will be created with the TMZ bit set
in the PTEs or engines accessing them. This is required in order
to properly access the data from the engines.
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
---
include/uapi/drm/amdgpu_drm.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index f3ad429..f90b453 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -135,6 +135,11 @@ extern "C" {
* releasing the memory
*/
#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
+/* Flag that BO will be encrypted and that the TMZ bit should be
+ * set in the PTEs when mapping this buffer via GPUVM or
+ * accessing it with various hw blocks
+ */
+#define AMDGPU_GEM_CREATE_ENCRYPTED(1 << 10)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
--
2.7.4
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[PATCH 14/14] drm/amdgpu: set TMZ bits in PTEs for secure bo (v2)
From: Alex Deucher
If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED), the TMZ bits of
PTEs that belongs that bo should be set. Then psp is able to protect the pages
of this bo to avoid the access from an "untrust" domain such as CPU.
v1: design and draft the skeletion of tmz bits setting on PTEs (Alex)
v2: return failure once create secure bo on no-tmz platform (Ray)
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 5 +
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 22eab74..5332104 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -222,7 +222,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
AMDGPU_GEM_CREATE_CPU_GTT_USWC |
AMDGPU_GEM_CREATE_VRAM_CLEARED |
AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
- AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
+ AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
+ AMDGPU_GEM_CREATE_ENCRYPTED))
return -EINVAL;
@@ -230,6 +231,11 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
return -EINVAL;
+ if (!adev->tmz.enabled && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
+ DRM_ERROR("Cannot allocate secure buffer while tmz is
disabled\n");
+ return -EINVAL;
+ }
+
/* create a gem object to contain this object in */
if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
@@ -251,6 +257,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
resv = vm->root.base.bo->tbo.resv;
}
+ if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
+ /* XXX: pad out alignment to meet TMZ requirements */
+ }
+
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
(u32)(0x & args->in.domains),
flags, ttm_bo_type_device, resv, );
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 5a3c177..286e2e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -224,6 +224,16 @@ static inline bool amdgpu_bo_explicit_sync(struct
amdgpu_bo *bo)
return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
}
+/**
+ * amdgpu_bo_encrypted - return whether the bo is encrypted
+ */
+static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
+{
+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
+ return adev->tmz.enabled && (bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED);
+}
+
bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 3663655..8f00bb2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1434,6 +1434,8 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
{
uint64_t flags = 0;
+ struct ttm_buffer_object *tbo = ttm_mem_reg_to_bo(mem);
+ struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
if (mem && mem->mem_type != TTM_PL_SYSTEM)
flags |= AMDGPU_PTE_VALID;
@@ -1444,6 +1446,9 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm,
struct ttm_mem_reg *mem)
if (ttm->caching_state == tt_cached)
flags |= AMDGPU_PTE_SNOOPED;
}
+ if (amdgpu_bo_encrypted(abo)) {
+ flags |= AMDGPU_PTE_TMZ;
+ }
return flags;
}
--
2.7.4
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[PATCH 00/14] drm/amdgpu: introduce secure buffer object support (trusted memory zone)
Hi all, These series of patches introduce a feature to support secure buffer object. The Trusted Memory Zone (TMZ) is a method to protect the contents being written to and read from memory. We use TMZ hardware memory protection scheme to implement the secure buffer object support. TMZ is the page-level protection that hardware will detect the TMZ bit in the page table entry to set the current page is encrypted. With this hardware feature, we design a BO-level protection in kernel driver to provide a new flag AMDGPU_GEM_CREATE_ENCRYPTED to gem create ioctl to libdrm for the secure buffer allocation. And also provide the AMDGPU_CTX_ALLOC_FLAGS_SECURE to indicate the context is trusted or not. If the BO is secure, then the data is encrypted, only the trusted IP blocks such as gfx, sdma, vcn are able to decrypt. CPU as the un-trusted IP are unable to read the secure buffer. We will submit the new secure context interface later for libdrm, and create a new test suite to verify the security feature in the libdrm unit tests. Suite id = 11: Name 'Security Tests status: ENABLED' Test id 1: Name: 'allocate secure buffer test status: ENABLED' Test id 2: Name: 'graphics command submission under secure context status: ENABLED' Thanks, Ray Alex Deucher (4): drm/amdgpu: add UAPI for creating encrypted buffers drm/amdgpu: add UAPI for creating secure contexts (v2) drm/amdgpu: define the TMZ bit for the PTE drm/amdgpu: set TMZ bits in PTEs for secure bo (v2) Huang Rui (10): drm/amdgpu: add tmz feature parameter (v2) drm/amdgpu: add amdgpu_tmz data structure drm/amdgpu: add function to check tmz capability (v4) drm/ttm: add helper to get buffer object with ttm_mem_reg drm/amdgpu: revise the function to allocate secure context (v2) drm/amdgpu: add tmz bit in frame control packet drm/amdgpu: expand the emit tmz interface with trusted flag drm/amdgpu: expand the context control interface with trust flag drm/amdgpu: set trusted mode while the job is under secure context (v2) drm/amdgpu: modify the method to use mem under buffer object for amdgpu_ttm_tt_pte_flags drivers/gpu/drm/amd/amdgpu/Makefile| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 19 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 11 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_job.h| 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 9 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c| 49 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h| 39 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 23 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 20 +--- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 +++--- drivers/gpu/drm/amd/amdgpu/nvd.h | 1 + drivers/gpu/drm/amd/amdgpu/soc15d.h| 1 + include/drm/ttm/ttm_bo_driver.h| 13 include/uapi/drm/amdgpu_drm.h | 9 +- 25 files changed, 230 insertions(+), 34 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/14] drm/amdgpu: add tmz bit in frame control packet
This patch adds tmz bit in frame control pm4 packet, and it will used in future. Signed-off-by: Huang Rui Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nvd.h| 1 + drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h index 1de9846..f3d8771 100644 --- a/drivers/gpu/drm/amd/amdgpu/nvd.h +++ b/drivers/gpu/drm/amd/amdgpu/nvd.h @@ -306,6 +306,7 @@ #definePACKET3_GET_LOD_STATS 0x8E #definePACKET3_DRAW_MULTI_PREAMBLE 0x8F #definePACKET3_FRAME_CONTROL 0x90 +# define FRAME_TMZ(1 << 0) # define FRAME_CMD(x) ((x) << 28) /* * x=0: tmz_begin diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h index edfe508..295d68c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h @@ -286,6 +286,7 @@ #definePACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 #definePACKET3_SWITCH_BUFFER 0x8B #define PACKET3_FRAME_CONTROL 0x90 +# define FRAME_TMZ(1 << 0) # define FRAME_CMD(x) ((x) << 28) /* * x=0: tmz_begin -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/14] drm/amdgpu: modify the method to use mem under buffer object for amdgpu_ttm_tt_pte_flags
amdgpu_ttm_tt_pte_flags will be used for updating tmz bits while the bo is
secure, so we need pass the ttm_mem_reg under a buffer object.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c05638c..3663655 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1117,8 +1117,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
} else {
/* allocate GART space */
- tmp = bo->mem;
- tmp.mm_node = NULL;
+ tmp = bo->mem; /* cache bo->mem */
+ bo->mem.mm_node = NULL;
placement.num_placement = 1;
placement.placement =
placement.num_busy_placement = 1;
@@ -1128,23 +1128,25 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
TTM_PL_FLAG_TT;
- r = ttm_bo_mem_space(bo, , , );
- if (unlikely(r))
+ r = ttm_bo_mem_space(bo, , >mem, );
+ if (unlikely(r)) {
+ bo->mem = tmp;
return r;
+ }
/* compute PTE flags for this buffer object */
- flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, );
+ flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, >mem);
/* Bind pages */
- gtt->offset = (u64)tmp.start << PAGE_SHIFT;
+ gtt->offset = (u64)bo->mem.start << PAGE_SHIFT;
r = amdgpu_ttm_gart_bind(adev, bo, flags);
if (unlikely(r)) {
+ bo->mem = tmp;
ttm_bo_mem_put(bo, );
return r;
}
- ttm_bo_mem_put(bo, >mem);
- bo->mem = tmp;
+ ttm_bo_mem_put(bo, );
}
bo->offset = (bo->mem.start << PAGE_SHIFT) +
--
2.7.4
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[PATCH 08/14] drm/amdgpu: revise the function to allocate secure context (v2)
The is_secure flag will indicate the current conext is protected or not.
v2: while user mode asks to create a context, but if tmz is disabled, it should
return failure.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 19 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 1 +
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 45a30aa..ae28aec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -72,7 +72,8 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp,
static int amdgpu_ctx_init(struct amdgpu_device *adev,
enum drm_sched_priority priority,
struct drm_file *filp,
- struct amdgpu_ctx *ctx)
+ struct amdgpu_ctx *ctx,
+ uint32_t flags)
{
unsigned num_entities = amdgpu_ctx_total_num_entities();
unsigned i, j, k;
@@ -121,6 +122,9 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
ctx->init_priority = priority;
ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
+ if (flags & AMDGPU_CTX_ALLOC_FLAGS_SECURE)
+ ctx->is_secure = true;
+
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
@@ -253,7 +257,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
struct amdgpu_fpriv *fpriv,
struct drm_file *filp,
enum drm_sched_priority priority,
- uint32_t *id)
+ uint32_t *id, uint32_t flags)
{
struct amdgpu_ctx_mgr *mgr = >ctx_mgr;
struct amdgpu_ctx *ctx;
@@ -272,7 +276,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
}
*id = (uint32_t)r;
- r = amdgpu_ctx_init(adev, priority, filp, ctx);
+ r = amdgpu_ctx_init(adev, priority, filp, ctx, flags);
if (r) {
idr_remove(>ctx_handles, *id);
*id = 0;
@@ -407,6 +411,12 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_fpriv *fpriv = filp->driver_priv;
+ if (!adev->tmz.enabled &&
+ (args->in.flags & AMDGPU_CTX_ALLOC_FLAGS_SECURE)) {
+ DRM_ERROR("Cannot allocate secure context while tmz is
disabled\n");
+ return -EINVAL;
+ }
+
r = 0;
id = args->in.ctx_id;
priority = amdgpu_to_sched_priority(args->in.priority);
@@ -418,7 +428,8 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
switch (args->in.op) {
case AMDGPU_CTX_OP_ALLOC_CTX:
- r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, );
+ r = amdgpu_ctx_alloc(adev, fpriv, filp, priority,
+, args->in.flags);
args->out.alloc.ctx_id = id;
break;
case AMDGPU_CTX_OP_FREE_CTX:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index da80863..aa8642b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -45,6 +45,7 @@ struct amdgpu_ctx {
struct dma_fence**fences;
struct amdgpu_ctx_entity*entities[AMDGPU_HW_IP_NUM];
boolpreamble_presented;
+ boolis_secure;
enum drm_sched_priority init_priority;
enum drm_sched_priority override_priority;
struct mutexlock;
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/14] drm/amdgpu: set trusted mode while the job is under secure context (v2)
While user mode submit a command with secure context, we should set the command
buffer with trusted mode.
v2: fix the null job pointer while in vmid 0 submission.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 ++
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 51f3db0..60e7b79 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1252,6 +1252,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
p->ctx->preamble_presented = true;
}
+ job->secure = p->ctx->is_secure;
cs->out.handle = seq;
job->uf_sequence = seq;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index e1dc229..cb9b650 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -210,7 +210,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
if (job && ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
- amdgpu_ring_emit_cntxcntl(ring, status, false);
+ amdgpu_ring_emit_cntxcntl(ring, status, job->secure);
}
for (i = 0; i < num_ibs; ++i) {
@@ -229,7 +229,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
}
if (ring->funcs->emit_tmz)
- amdgpu_ring_emit_tmz(ring, false, false);
+ amdgpu_ring_emit_tmz(ring, false, job ? job->secure : false);
#ifdef CONFIG_X86_64
if (!(adev->flags & AMD_IS_APU))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index dc7ee93..59f1dbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -63,6 +63,8 @@ struct amdgpu_job {
uint64_tuf_addr;
uint64_tuf_sequence;
+ /* the job is under secure context */
+ boolsecure;
};
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/14] drm/amdgpu: expand the context control interface with trust flag
This patch expands the context control function to support trusted flag while we
want to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 5 +++--
7 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 54741ba..e1dc229 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -210,7 +210,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
if (job && ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
- amdgpu_ring_emit_cntxcntl(ring, status);
+ amdgpu_ring_emit_cntxcntl(ring, status, false);
}
for (i = 0; i < num_ibs; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 34aa63a..5134d0d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -158,7 +158,8 @@ struct amdgpu_ring_funcs {
void (*begin_use)(struct amdgpu_ring *ring);
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
- void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
+ void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags,
+ bool trusted);
void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
@@ -242,7 +243,7 @@ struct amdgpu_ring {
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as)
(r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
-#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
+#define amdgpu_ring_emit_cntxcntl(r, d, s) (r)->funcs->emit_cntxcntl((r), (d),
(s))
#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r),
(d), (v), (m))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 18f741b..06698c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4514,7 +4514,9 @@ static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring
*ring)
amdgpu_ring_write(ring, 0);
}
-static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t
flags)
+static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+uint32_t flags,
+bool trusted)
{
uint32_t dw2 = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 8c27c30..b4af1b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2972,7 +2972,8 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct
amdgpu_device *adev)
return clock;
}
-static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags,
+ bool trusted)
{
if (flags & AMDGPU_HAVE_CTX_SWITCH)
gfx_v6_0_ring_emit_vgt_flush(ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 48796b68..c08f5c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2309,7 +2309,8 @@ static void gfx_v7_0_ring_emit_ib_compute(struct
amdgpu_ring *ring,
amdgpu_ring_write(ring, control);
}
-static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags,
+ bool trusted)
{
uint32_t dw2 = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 98e5aa8..d3a23fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6393,7 +6393,8 @@ static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, 0);
[PATCH 06/14] drm/amdgpu: add function to check tmz capability (v4)
Add a function to check tmz capability with kernel parameter and ASIC type.
v2: use a per device tmz variable instead of global amdgpu_tmz.
v3: refine the comments for the function. (Luben)
v4: add amdgpu_tmz.c/h for future use.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c| 49 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h| 3 ++
4 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 91369c8..270ce82 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o
amdgpu_vm_cpu.o \
amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o amdgpu_ras_eeprom.o
amdgpu_nbio.o \
- amdgpu_umc.o smu_v11_0_i2c.o
+ amdgpu_umc.o smu_v11_0_i2c.o amdgpu_tmz.o
amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2535db2..e376fe5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -63,6 +63,7 @@
#include "amdgpu_xgmi.h"
#include "amdgpu_ras.h"
#include "amdgpu_pmu.h"
+#include "amdgpu_tmz.h"
#include
@@ -1032,6 +1033,8 @@ static int amdgpu_device_check_arguments(struct
amdgpu_device *adev)
adev->firmware.load_type = amdgpu_ucode_get_load_type(adev,
amdgpu_fw_load_type);
+ adev->tmz.enabled = amdgpu_is_tmz(adev);
+
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
new file mode 100644
index 000..14a5500
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+#include "amdgpu.h"
+#include "amdgpu_tmz.h"
+
+
+/**
+ * amdgpu_is_tmz - validate trust memory zone
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Return true if @dev supports trusted memory zones (TMZ), and return false if
+ * @dev does not support TMZ.
+ */
+bool amdgpu_is_tmz(struct amdgpu_device *adev)
+{
+ if (!amdgpu_tmz)
+ return false;
+
+ if (adev->asic_type < CHIP_RAVEN || adev->asic_type == CHIP_ARCTURUS) {
+ dev_warn(adev->dev, "doesn't support trusted memory zones
(TMZ)\n");
+ return false;
+ }
+
+ dev_info(adev->dev, "TMZ feature is enabled\n");
+
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
index 24bbbc2..28e0517 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
@@ -33,4 +33,7 @@ struct amdgpu_tmz {
boolenabled;
};
+
+extern bool amdgpu_is_tmz(struct amdgpu_device *adev);
+
#endif
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 10/14] drm/amdgpu: expand the emit tmz interface with trusted flag
This patch expands the emit_tmz function to support trusted flag while we want
to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 16
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 13 ++---
4 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 6882eeb..54741ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -229,7 +229,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
}
if (ring->funcs->emit_tmz)
- amdgpu_ring_emit_tmz(ring, false);
+ amdgpu_ring_emit_tmz(ring, false, false);
#ifdef CONFIG_X86_64
if (!(adev->flags & AMD_IS_APU))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 930316e..34aa63a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -166,7 +166,7 @@ struct amdgpu_ring_funcs {
void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
uint32_t reg0, uint32_t reg1,
uint32_t ref, uint32_t mask);
- void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
+ void (*emit_tmz)(struct amdgpu_ring *ring, bool start, bool trusted);
/* priority functions */
void (*set_priority) (struct amdgpu_ring *ring,
enum drm_sched_priority priority);
@@ -247,7 +247,7 @@ struct amdgpu_ring {
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r),
(d), (v), (m))
#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m)
(r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
-#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
+#define amdgpu_ring_emit_tmz(r, b, s) (r)->funcs->emit_tmz((r), (b), (s))
#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a2f4ff1..18f741b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -243,7 +243,8 @@ static int gfx_v10_0_rlc_backdoor_autoload_enable(struct
amdgpu_device *adev);
static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device
*adev);
static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
-static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
+static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
+ bool trusted);
static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t
queue_mask)
{
@@ -4521,7 +4522,7 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct
amdgpu_ring *ring, uint32_t flag
gfx_v10_0_ring_emit_ce_meta(ring,
flags & AMDGPU_IB_PREEMPTED ? true : false);
- gfx_v10_0_ring_emit_tmz(ring, true);
+ gfx_v10_0_ring_emit_tmz(ring, true, false);
dw2 |= 0x8000; /* set load_enable otherwise this package is just
NOPs */
if (flags & AMDGPU_HAVE_CTX_SWITCH) {
@@ -4679,10 +4680,17 @@ static void gfx_v10_0_ring_emit_de_meta(struct
amdgpu_ring *ring, bool resume)
sizeof(de_payload) >> 2);
}
-static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
+static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
+ bool trusted)
{
amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
- amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
+ /*
+* cmd = 0: frame begin
+* cmd = 1: frame end
+*/
+ amdgpu_ring_write(ring,
+ ((ring->adev->tmz.enabled && trusted) ? FRAME_TMZ : 0)
+ | FRAME_CMD(start ? 0 : 1));
}
static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 90348fb29..fa264d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5240,10 +5240,17 @@ static void gfx_v9_0_ring_emit_de_meta(struct
amdgpu_ring *ring)
amdgpu_ring_write_multiple(ring, (void *)_payload,
[PATCH 02/14] drm/amdgpu: add UAPI for creating secure contexts (v2)
From: Alex Deucher
Add a flag for when allocating a context to flag it as
secure. The kernel driver will use this flag to determine
whether a rendering context is secure or not so that the
engine can be transitioned between secure or unsecure
or the work can be submitted to a secure queue depending
on the IP.
v2: the flag will be used for security, so remove the comment (Ray)
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Huang Rui
---
include/uapi/drm/amdgpu_drm.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index f90b453..7aab4e1 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -207,6 +207,9 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_OP_QUERY_STATE 3
#define AMDGPU_CTX_OP_QUERY_STATE2 4
+/* Flag the context as secure */
+#define AMDGPU_CTX_ALLOC_FLAGS_SECURE (1 << 0)
+
/* GPU reset status */
#define AMDGPU_CTX_NO_RESET0
/* this the context caused it */
@@ -241,7 +244,6 @@ union drm_amdgpu_bo_list {
struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */
__u32 op;
- /** For future use, no flags defined so far */
__u32 flags;
__u32 ctx_id;
/** AMDGPU_CTX_PRIORITY_* */
--
2.7.4
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[PATCH 07/14] drm/ttm: add helper to get buffer object with ttm_mem_reg
This patch is to add a helper to get corresponding buffer object with a pointer
to a struct ttm_mem_reg.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
include/drm/ttm/ttm_bo_driver.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index d69121c..264e6c3 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -786,6 +786,19 @@ static inline void ttm_bo_unreserve(struct
ttm_buffer_object *bo)
reservation_object_unlock(bo->resv);
}
+/**
+ * ttm_mem_reg_to_bo
+ *
+ * @mem: A pointer to a struct ttm_mem_reg.
+ *
+ * Returns corresponding buffer object of the @mem.
+ */
+static inline
+struct ttm_buffer_object *ttm_mem_reg_to_bo(struct ttm_mem_reg *mem)
+{
+ return container_of(mem, struct ttm_buffer_object, mem);
+}
+
/*
* ttm_bo_util.c
*/
--
2.7.4
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[PATCH 04/14] drm/amdgpu: add tmz feature parameter (v2)
This patch adds tmz parameter to enable/disable the feature in the amdgpu kernel
module. Nomally, by default, it should be auto (rely on the hardware
capability).
But right now, it need to set "off" to avoid breaking other developers'
work because it's not totally completed.
Will set "auto" till the feature is stable and completely verified.
v2: add "auto" option for future use.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a1516a3..930643c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -172,6 +172,7 @@ extern int amdgpu_force_asic_type;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
#endif
+extern int amdgpu_tmz;
#ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6978d17..606f1d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -145,6 +145,7 @@ int amdgpu_discovery = -1;
int amdgpu_mes = 0;
int amdgpu_noretry = 1;
int amdgpu_force_asic_type = -1;
+int amdgpu_tmz = 0;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -752,6 +753,16 @@ uint amdgpu_dm_abm_level = 0;
MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight
reduction level) ");
module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
+/**
+ * DOC: tmz (int)
+ * Trust Memory Zone (TMZ) is a method to protect the contents being written to
+ * and read from memory.
+ *
+ * The default value: 0 (off). TODO: change to auto till it is completed.
+ */
+MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 =
on)");
+module_param_named(tmz, amdgpu_tmz, int, 0444);
+
static const struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
--
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[PATCH 1/2] drm/amd/powerplay: properly set mp1 state for SW SMU suspend/reset routine
Set mp1 state properly for SW SMU suspend/reset routine.
Change-Id: I458d09e79bba2613bb85099938648782ff91b97a
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 10 ++---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 40 +++
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 2 +
3 files changed, 47 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c8697b5ef1d0..5fe539f80009 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2217,16 +2217,16 @@ static int amdgpu_device_ip_suspend_phase2(struct
amdgpu_device *adev)
/* handle putting the SMC in the appropriate state */
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
if (is_support_sw_smu(adev)) {
- /* todo */
+ r = smu_set_mp1_state(>smu,
adev->mp1_state);
} else if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->set_mp1_state) {
r = adev->powerplay.pp_funcs->set_mp1_state(
adev->powerplay.pp_handle,
adev->mp1_state);
- if (r) {
- DRM_ERROR("SMC failed to set mp1 state
%d, %d\n",
- adev->mp1_state, r);
- }
+ }
+ if (r) {
+ DRM_ERROR("SMC failed to set mp1 state %d,
%d\n",
+ adev->mp1_state, r);
}
}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f13e134be42e..25f3c9e1b404 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1796,6 +1796,46 @@ int smu_force_clk_levels(struct smu_context *smu,
return ret;
}
+int smu_set_mp1_state(struct smu_context *smu,
+ enum pp_mp1_state mp1_state)
+{
+ uint16_t msg;
+ int ret;
+
+ /*
+* The SMC is not fully ready. That may be
+* expected as the IP may be masked.
+* So, just return without error.
+*/
+ if (!smu->pm_enabled)
+ return 0;
+
+ switch (mp1_state) {
+ case PP_MP1_STATE_SHUTDOWN:
+ msg = SMU_MSG_PrepareMp1ForShutdown;
+ break;
+ case PP_MP1_STATE_UNLOAD:
+ msg = SMU_MSG_PrepareMp1ForUnload;
+ break;
+ case PP_MP1_STATE_RESET:
+ msg = SMU_MSG_PrepareMp1ForReset;
+ break;
+ case PP_MP1_STATE_NONE:
+ default:
+ return 0;
+ }
+
+ /* some asics may not support those messages */
+ if (smu_msg_get_index(smu, msg) < 0)
+ return 0;
+
+ ret = smu_send_smc_msg(smu, msg);
+ if (ret)
+ pr_err("[PrepareMp1] Failed!\n");
+
+ return ret;
+}
+
const struct amd_ip_funcs smu_ip_funcs = {
.name = "smu",
.early_init = smu_early_init,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 3de88d084615..16df09be6a9f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -903,5 +903,7 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu,
uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask);
+int smu_set_mp1_state(struct smu_context *smu,
+ enum pp_mp1_state mp1_state);
#endif
--
2.23.0
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[PATCH 05/14] drm/amdgpu: add amdgpu_tmz data structure
This patch to add amdgpu_tmz structure which stores all tmz related fields.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h | 36 +
2 files changed, 41 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 930643c..697e8e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -89,6 +89,7 @@
#include "amdgpu_mes.h"
#include "amdgpu_umc.h"
#include "amdgpu_mmhub.h"
+#include "amdgpu_tmz.h"
#define MAX_GPU_INSTANCE 16
@@ -916,6 +917,9 @@ struct amdgpu_device {
boolenable_mes;
struct amdgpu_mes mes;
+ /* tmz */
+ struct amdgpu_tmz tmz;
+
struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
int num_ip_blocks;
struct mutexmn_lock;
@@ -927,7 +931,7 @@ struct amdgpu_device {
atomic64_t gart_pin_size;
/* soc15 register offset based on ip, instance and segment */
- uint32_t*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
+ uint32_t*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
const struct amdgpu_df_funcs*df_funcs;
const struct amdgpu_mmhub_funcs *mmhub_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
new file mode 100644
index 000..24bbbc2
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __AMDGPU_TMZ_H__
+#define __AMDGPU_TMZ_H__
+
+#include "amdgpu.h"
+
+/*
+ * Trust memory zone stuff
+ */
+struct amdgpu_tmz {
+ boolenabled;
+};
+
+#endif
--
2.7.4
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[PATCH 2/2] drm/amd/powerplay: check SMU engine readiness before proceeding on S3 resume
This is especially needed for non-psp loading way.
Change-Id: I1e523168ed4892c34c8cbb66077c3f9288dd8006
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 28 ++
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 25f3c9e1b404..95969c98a108 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1213,11 +1213,10 @@ static int smu_free_memory_pool(struct smu_context *smu)
return ret;
}
-static int smu_hw_init(void *handle)
+static int smu_start_smc_engine(struct smu_context *smu)
{
- int ret;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- struct smu_context *smu = >smu;
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
if (adev->asic_type < CHIP_NAVI10) {
@@ -1228,8 +1227,21 @@ static int smu_hw_init(void *handle)
}
ret = smu_check_fw_status(smu);
+ if (ret)
+ pr_err("SMC is not ready\n");
+
+ return ret;
+}
+
+static int smu_hw_init(void *handle)
+{
+ int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct smu_context *smu = >smu;
+
+ ret = smu_start_smc_engine(smu);
if (ret) {
- pr_err("SMC firmware status is not correct\n");
+ pr_err("SMU is not ready yet!\n");
return ret;
}
@@ -1389,6 +1401,12 @@ static int smu_resume(void *handle)
mutex_lock(>mutex);
+ ret = smu_start_smc_engine(smu);
+ if (ret) {
+ pr_err("SMU is not ready yet!\n");
+ return ret;
+ }
+
ret = smu_smc_table_hw_init(smu, false);
if (ret)
goto failed;
--
2.23.0
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[PATCH 03/14] drm/amdgpu: define the TMZ bit for the PTE
From: Alex Deucher Define the TMZ (encryption) bit in the page table entry (PTE) for Raven and newer asics. Signed-off-by: Alex Deucher Reviewed-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 3352a87..4b5d283 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -53,6 +53,9 @@ struct amdgpu_bo_list_entry; #define AMDGPU_PTE_SYSTEM (1ULL << 1) #define AMDGPU_PTE_SNOOPED (1ULL << 2) +/* RV+ */ +#define AMDGPU_PTE_TMZ (1ULL << 3) + /* VI only */ #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: For Navi12 SRIOV VF, register mailbox functions
From: Jiange Zhao
Mailbox functions and interrupts are only for Navi12 VF.
Register functions and irqs during initialization.
Signed-off-by: Jiange Zhao
---
drivers/gpu/drm/amd/amdgpu/nv.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a61f43c0c9df..4c24672be12a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -53,6 +53,7 @@
#include "vcn_v2_0.h"
#include "dce_virtual.h"
#include "mes_v10_1.h"
+#include "mxgpu_nv.h"
static const struct amd_ip_funcs nv_common_ip_funcs;
@@ -426,6 +427,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
adev->nbio.funcs->detect_hw_virt(adev);
+ if (amdgpu_sriov_vf(adev))
+ adev->virt.ops = _nv_virt_ops;
+
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
@@ -666,16 +670,31 @@ static int nv_common_early_init(void *handle)
return -EINVAL;
}
+ if (amdgpu_sriov_vf(adev)) {
+ amdgpu_virt_init_setting(adev);
+ xgpu_nv_mailbox_set_irq_funcs(adev);
+ }
+
return 0;
}
static int nv_common_late_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (amdgpu_sriov_vf(adev))
+ xgpu_nv_mailbox_get_irq(adev);
+
return 0;
}
static int nv_common_sw_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (amdgpu_sriov_vf(adev))
+ xgpu_nv_mailbox_add_irq_id(adev);
+
return 0;
}
--
2.20.1
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[PATCH] drm/amdgpu: get gpu info from ip discovery table
except soc_bounding_box which is not integrated in discovery table yet
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 13bd6a6bd8aa..70e0f24d37a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1474,6 +1474,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
(const struct gpu_info_firmware_v1_0
*)(adev->firmware.gpu_info_fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
+ goto parse_soc_bounding_box;
+
adev->gfx.config.max_shader_engines =
le32_to_cpu(gpu_info_fw->gc_num_se);
adev->gfx.config.max_cu_per_sh =
le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
adev->gfx.config.max_sh_per_se =
le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
@@ -1501,7 +1504,13 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
adev->gfx.config.num_packer_per_sc =
le32_to_cpu(gpu_info_fw->num_packer_per_sc);
}
+
+parse_soc_bounding_box:
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ /*
+* soc bounding box info is not integrated in disocovery table,
+* we always need to parse it from gpu info firmware.
+*/
if (hdr->version_minor == 2) {
const struct gpu_info_firmware_v1_2 *gpu_info_fw =
(const struct gpu_info_firmware_v1_2
*)(adev->firmware.gpu_info_fw->data +
@@ -1618,6 +1627,9 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
if (r)
return r;
+ if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
+ amdgpu_discovery_get_gfx_info(adev);
+
amdgpu_amdkfd_device_probe(adev);
if (amdgpu_sriov_vf(adev)) {
--
2.20.1
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Re: [PATCH 9/9] drm/amdgpu: add graceful VM fault handling v2
Am 10.09.19 um 15:30 schrieb Zeng, Oak:
>
> Regards,
> Oak
>
> -Original Message-
> From: Koenig, Christian
> Sent: Monday, September 9, 2019 1:14 PM
> To: Zeng, Oak ; Kuehling, Felix ;
> amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 9/9] drm/amdgpu: add graceful VM fault handling v2
>
>> Well first of all we are not in interrupt context here, this is handled by a
>> work item or otherwise we couldn't do all the locking.
> This is called from amdgpu_irq_handler. I think this is interrupt context.
No, that's incorrect. Only the primary interrupt ring is handled in
interrupt context. Ring 1 and 2 are handled with a work item.
> This is also the reason why we use spin lock instead of other sleepable
> lock like a semaphore.
Well we do have a sleep-able lock here to make it possible to update
page tables and directories.
That's also the reason why we protect the call with in !in_interrupt().
Regards,
Christian.
>
>> But even in interrupt context another CPU can easily destroy the VM when we
>> just handle a stale fault or the process was killed.
> Agree with this point.
>
> So this extra double checking is strictly necessary.
>
> Regards,
> Christian.
>
> Am 09.09.19 um 16:08 schrieb Zeng, Oak:
>> Is looking up vm twice necessary? I think we are in interrupt context, is it
>> possible that the user space application can be switched in between? My
>> understanding is, if user space application is can't kick in during
>> interrupt handling, application shouldn't have chance to exit (then their vm
>> being destroyed).
>>
>> Regards,
>> Oak
>>
>> -Original Message-
>> From: amd-gfx On Behalf Of
>> Christian König
>> Sent: Monday, September 9, 2019 8:08 AM
>> To: Kuehling, Felix ;
>> amd-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH 9/9] drm/amdgpu: add graceful VM fault handling v2
>>
>> Am 05.09.19 um 00:47 schrieb Kuehling, Felix:
>>> On 2019-09-04 11:02 a.m., Christian König wrote:
Next step towards HMM support. For now just silence the retry fault
and optionally redirect the request to the dummy page.
v2: make sure the VM is not destroyed while we handle the fault.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 74 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++
3 files changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 951608fc1925..410d89966a66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -3142,3 +3142,77 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
}
}
}
+
+/**
+ * amdgpu_vm_handle_fault - graceful handling of VM faults.
+ * @adev: amdgpu device pointer
+ * @pasid: PASID of the VM
+ * @addr: Address of the fault
+ *
+ * Try to gracefully handle a VM fault. Return true if the fault
+was handled and
+ * shouldn't be reported any more.
+ */
+bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, unsigned int
pasid,
+ uint64_t addr)
+{
+ struct amdgpu_ring *ring = >sdma.instance[0].page;
+ struct amdgpu_bo *root;
+ uint64_t value, flags;
+ struct amdgpu_vm *vm;
+ long r;
+
+ if (!ring->sched.ready)
+ return false;
+
+ spin_lock(>vm_manager.pasid_lock);
+ vm = idr_find(>vm_manager.pasid_idr, pasid);
+ if (vm)
+ root = amdgpu_bo_ref(vm->root.base.bo);
+ else
+ root = NULL;
+ spin_unlock(>vm_manager.pasid_lock);
+
+ if (!root)
+ return false;
+
+ r = amdgpu_bo_reserve(root, true);
+ if (r)
+ goto error_unref;
+
+ spin_lock(>vm_manager.pasid_lock);
+ vm = idr_find(>vm_manager.pasid_idr, pasid);
+ spin_unlock(>vm_manager.pasid_lock);
>>> I think this deserves a comment. If I understand it correctly, you're
>>> looking up the vm twice so that you have the VM root reservation to
>>> protect against user-after-free. Otherwise the vm pointer is only
>>> valid as long as you're holding the spin-lock.
>>>
>>>
+
+ if (!vm || vm->root.base.bo != root)
>>> The check of vm->root.base.bo should probably still be under the
>>> spin_lock. Because you're not sure yet it's the right VM, you can't
>>> rely on the reservation here to prevent use-after-free.
>> Good point, going to fix that.
>>
+ goto error_unlock;
+
+ addr /= AMDGPU_GPU_PAGE_SIZE;
+ flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
+ AMDGPU_PTE_SYSTEM;
+
+ if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
+ /* Redirect the access to the dummy page */
Re: [PATCH] drm/radeon: Bail earlier when radeon.cik_/si_support=0 is passed
On 2019-09-10 11:36 a.m., Hans de Goede wrote: > On 9/10/19 9:50 AM, Michel Dänzer wrote: >> On 2019-09-07 10:32 p.m., Hans de Goede wrote: >>> Bail from the pci_driver probe function instead of from the drm_driver >>> load function. >>> >>> This avoid /dev/dri/card0 temporarily getting registered and then >>> unregistered again, sending unwanted add / remove udev events to >>> userspace. >>> >>> Specifically this avoids triggering the (userspace) bug fixed by this >>> plymouth merge-request: >>> https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59 >>> >>> Note that despite that being an userspace bug, not sending unnecessary >>> udev events is a good idea in general. >>> >>> BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490 >>> Signed-off-by: Hans de Goede >> >> Reviewed-by: Michel Dänzer > > Thank you for the review. I've drm push rights, but I guess that radeon/amd > GPU patches are collected by someone @AMD, so I do not need to / should not > push this myself, right? I think so, unless one of the driver maintainers says otherwise. >> amdgpu should be changed correspondingly as well. > > Good point. I'm currently travelling (@plumbers) I can do this when I'm > back home, > but feel free to beat me to it (if you do please Cc me to avoid double > work). I'm happy to leave it to you, if you don't mind. -- Earthling Michel Dänzer | https://redhat.com Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: Add SRIOV mailbox backend for Navi1x
Reviewed-by: Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of
>jia...@amd.com
>Sent: Monday, September 9, 2019 6:37 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Zhao, Jiange
>Subject: [PATCH] drm/amdgpu: Add SRIOV mailbox backend for Navi1x
>
>From: Jiange Zhao
>
>Mimic the ones for Vega10, add mailbox backend for Navi1x
>
>Signed-off-by: Jiange Zhao
>---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 380
>++ drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
>| 41 +++
> 3 files changed, 422 insertions(+), 1 deletion(-) create mode 100644
>drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
>b/drivers/gpu/drm/amd/amdgpu/Makefile
>index 84614a71bb4d..43dc4aa18930 100644
>--- a/drivers/gpu/drm/amd/amdgpu/Makefile
>+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
>@@ -68,7 +68,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o
>gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce amdgpu-y += \
> vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o
>nbio_v7_0.o vega10_reg_init.o \
> vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o
>navi14_reg_init.o \
>- arct_reg_init.o navi12_reg_init.o
>+ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o
>
> # add DF block
> amdgpu-y += \
>diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
>b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
>new file mode 100644
>index ..0d8767eb7a70
>--- /dev/null
>+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
>@@ -0,0 +1,380 @@
>+/*
>+ * Copyright 2014 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person
>+obtaining a
>+ * copy of this software and associated documentation files (the
>+"Software"),
>+ * to deal in the Software without restriction, including without
>+limitation
>+ * the rights to use, copy, modify, merge, publish, distribute,
>+sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom
>+the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be
>+included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>+EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>+MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
>EVENT
>+SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>+DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>+OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
>THE USE
>+OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include "amdgpu.h"
>+#include "nbio/nbio_2_3_offset.h"
>+#include "nbio/nbio_2_3_sh_mask.h"
>+#include "gc/gc_10_1_0_offset.h"
>+#include "gc/gc_10_1_0_sh_mask.h"
>+#include "soc15.h"
>+#include "navi10_ih.h"
>+#include "soc15_common.h"
>+#include "mxgpu_nv.h"
>+#include "mxgpu_ai.h"
>+
>+static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev) {
>+ WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); }
>+
>+static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool
>+val) {
>+ WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); }
>+
>+/*
>+ * this peek_msg could *only* be called in IRQ routine becuase in IRQ
>+routine
>+ * RCV_MSG_VALID filed of BIF_BX_PF_MAILBOX_CONTROL must already be
>set
>+to 1
>+ * by host.
>+ *
>+ * if called no in IRQ routine, this peek_msg cannot guaranteed to
>+return the
>+ * correct value since it doesn't return the RCV_DW0 under the case
>+that
>+ * RCV_MSG_VALID is set by host.
>+ */
>+static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device
>+*adev) {
>+ return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
>+
> mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0));
>+}
>+
>+
>+static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev,
>+ enum idh_event event)
>+{
>+ u32 reg;
>+
>+ reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
>+
>mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0));
>+ if (reg != event)
>+ return -ENOENT;
>+
>+ xgpu_nv_mailbox_send_ack(adev);
>+
>+ return 0;
>+}
>+
>+static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev) {
>+ return RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2; }
>+
>+static int xgpu_nv_poll_ack(struct amdgpu_device *adev) {
>+ int timeout = NV_MAILBOX_POLL_ACK_TIMEDOUT;
>+ u8 reg;
>+
>+ do {
>+ reg = RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE);
>+ if (reg & 2)
>+ return 0;
>+
>+ mdelay(5);
>+ timeout -= 5;
>+ } while (timeout > 1);
>+
>+ pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n",
>+NV_MAILBOX_POLL_ACK_TIMEDOUT);
>+
>+ return -ETIME;
>+}
>+
>+static int
Re: [PATCH] drm/radeon: Bail earlier when radeon.cik_/si_support=0 is passed
Hi, On 9/10/19 9:50 AM, Michel Dänzer wrote: On 2019-09-07 10:32 p.m., Hans de Goede wrote: Bail from the pci_driver probe function instead of from the drm_driver load function. This avoid /dev/dri/card0 temporarily getting registered and then unregistered again, sending unwanted add / remove udev events to userspace. Specifically this avoids triggering the (userspace) bug fixed by this plymouth merge-request: https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59 Note that despite that being an userspace bug, not sending unnecessary udev events is a good idea in general. BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490 Signed-off-by: Hans de Goede Reviewed-by: Michel Dänzer Thank you for the review. I've drm push rights, but I guess that radeon/amd GPU patches are collected by someone @AMD, so I do not need to / should not push this myself, right? amdgpu should be changed correspondingly as well. Good point. I'm currently travelling (@plumbers) I can do this when I'm back home, but feel free to beat me to it (if you do please Cc me to avoid double work). Regards, Hans ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
?????? ?????? ?????? ?????? Bug: amdgpu drm driver cause process into Disk sleep state
I'm leaving out for some days. Thanks very much for your detailed answer. Best Regards. Yanhua -- -- ??: "Koenig, Christian"; : 2019??9??6??(??) 7:23 ??: "yanhua"<78666...@qq.com>;"amd-gfx"; : "Deucher, Alexander"; : Re: ?? ?? ?? Bug: amdgpu drm driver cause process into Disk sleep state Are there anything I have missed ? Yeah, unfortunately quite a bunch of things. The fact that arm64 doesn't support the PCIe NoSnoop TLP attribute is only the tip of the iceberg. You need a full "recent" driver stack, e.g. not older than a few month till a year, for this to work. And not only the kernel, but also recent userspace components. Maybe that's something you could first, e.g. install a recent version of Mesa and/or tell Mesa to not use the SDMA at all. But since you are running into an SDMA lockup with a kernel triggered page table update I see little chance that this work. The only other alternative I can see is the DKMS package of the pro-driver. With that one you might be able to compile the recent driver for an older kernel version. But I can't guarantee at all that this actually works on ARM64. Sorry that I don't have better news for you, Christian. Am 05.09.19 um 03:36 schrieb yanhua: Hi, Christian, I noticed that you said 'amdgpu is known to not work on arm64 until very recently'.I found the CPU related commit with drm is "drm: disable uncached DMA optimization for ARM and arm64". @@ -47,6 +47,24 @@ static inline bool drm_arch_can_wc_memory(void) return false; #elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3) return false; +#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) + /* +* The DRM driver stack is designed to work with cache coherent devices +* only, but permits an optimization to be enabled in some cases, where +* for some buffers, both the CPU and the GPU use uncached mappings, +* removing the need for DMA snooping and allocation in the CPU caches. +* +* The use of uncached GPU mappings relies on the correct implementation +* of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU +* will use cached mappings nonetheless. On x86 platforms, this does not +* seem to matter, as uncached CPU mappings will snoop the caches in any +* case. However, on ARM and arm64, enabling this optimization on a +* platform where NoSnoop is ignored results in loss of coherency, which +* breaks correct operation of the device. Since we have no way of +* detecting whether NoSnoop works or not, just disable this +* optimization entirely for ARM and arm64. +*/ + return false; #else return true; #endif The real effect is to in amdgpu_object.c if (!drm_arch_can_wc_memory()) bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; And we have AMDGPU_GEM_CREATE_CPU_GTT_USWC turned off in our 4.19.36 kernel, So I think this is not the cause of my bug. Are there anything I have missed ? I had suggest the machine supplier to use a more newer kernel such as 5.2.2, But they failed to do so after some try. We also backport a series patches from newer kernel. But still we get the bad ring timeout. We have dived into the amdgpu drm driver a long time, bu it is really difficult for me, especially the hardware related ring timeout. -- Yanhua -- -- ??: "Koenig, Christian"; : 2019??9??3??(??) 9:19 ??: "yanhua"<78666...@qq.com>;"amd-gfx"; : "Deucher, Alexander"; : Re: ?? ?? Bug: amdgpu drm driver cause process into Disk sleep state This is just a GPU lock, please open up a bug report on freedesktop.org and attach the full dmesg and which version of Mesa you are using. Regards, Christian. Am 03.09.19 um 15:16 schrieb 7879: Yes, with dmesg|grep drm , I get following. 348571.880718] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma1 timeout, signaled seq=24423862, emitted seq=24423865 -- -- ??: "Koenig, Christian"; : 2019??9??3??(??) 9:07 ??: ""<78666...@qq.com>;"amd-gfx"; : "Deucher, Alexander"; : Re: ?? Bug: amdgpu drm driver cause process into Disk sleep state Well that looks like the hardware got stuck. Do you get something in the locks about a timeout on the SDMA ring? Regards, Christian. Am 03.09.19 um 14:50 schrieb 7879: Hi Christian, Sometimes the thread blocked disk sleeping in call to amdgpu_sa_bo_new. following is the stack trace. it seems the sa bo is used up , so the caller blocked waiting someone to free sa resources. D 206833 227656
Re: [PATCH] Fix Xorg abort on exit in RHEL 7.7+
Hi Slava,
xf86-video-amdgpu patches are submitted & reviewed as GitLab merge
requests now. Please log into your GitLab account, click the "Fork"
button on https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu ,
push the change to a new branch of your resulting personal GitLab
project, and click on the URL in "git push"'s output to create an MR.
Thanks,
On 2019-09-10 9:47 p.m., Grigorev, Slava wrote:
> RHEL adds an extra LeaveVT calls to xf86CrtcCloseScreen when they build X
> server
> for the purpose to drop drm master.
>
> Signed-off-by: Slava Grigorev
> ---
> src/amdgpu_kms.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
> index 3280972..9efc482 100644
> --- a/src/amdgpu_kms.c
> +++ b/src/amdgpu_kms.c
> @@ -2285,7 +2285,9 @@ void AMDGPULeaveVT_KMS(ScrnInfoPtr pScrn)
> struct drmmode_fb *black_fb =
>
> amdgpu_pixmap_get_fb(black_scanout.pixmap);
>
> - amdgpu_pixmap_clear(black_scanout.pixmap);
> + if (!dixPrivateKeyRegistered(rrPrivKey))
> +
> amdgpu_pixmap_clear(black_scanout.pixmap);
> +
> amdgpu_glamor_finish(pScrn);
>
> for (i = 0; i < xf86_config->num_crtc; i++) {
>
--
Earthling Michel Dänzer | https://redhat.com
Libre software enthusiast | Mesa and X developer
___
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RE: [PATCH] drm/amdgpu: Fix mutex lock from atomic context.
Also it's irrelevant for this partilcular interrupt as this is generic RAS interrupt and not memory errors specific. [Guchun]One typo, it should be "particular", not " partilcular". With that fixed, the patch is: Reviewed-by: Guchun Chen -Original Message- From: Andrey Grodzovsky Sent: Wednesday, September 11, 2019 3:41 AM To: amd-gfx@lists.freedesktop.org Cc: Chen, Guchun ; Zhou1, Tao ; Deucher, Alexander ; Grodzovsky, Andrey Subject: [PATCH] drm/amdgpu: Fix mutex lock from atomic context. Problem: amdgpu_ras_reserve_bad_pages was moved to amdgpu_ras_reset_gpu because writing to EEPROM during ASIC reset was unstable. But for ERREVENT_ATHUB_INTERRUPT amdgpu_ras_reset_gpu is called directly from ISR context and so locking is not allowed. Also it's irrelevant for this partilcular interrupt as this is generic RAS interrupt and not memory errors specific. [Guchun]One typo, it should be "particular", not " partilcular". With that fixed, the patch is: Reviewed-by: Guchun Chen Fix: Avoid calling amdgpu_ras_reserve_bad_pages if not in task context. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 012034d..dd5da3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -504,7 +504,9 @@ static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev, /* save bad page to eeprom before gpu reset, * i2c may be unstable in gpu reset */ - amdgpu_ras_reserve_bad_pages(adev); + if (in_task()) + amdgpu_ras_reserve_bad_pages(adev); + if (atomic_cmpxchg(>in_recovery, 0, 1) == 0) schedule_work(>recovery_work); return 0; -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: fix build error without CONFIG_HSA_AMD
Agree, have sent V2.
My patch was actually in line to already up streamed patch:
https://lkml.org/lkml/2019/8/26/201
Regards,
Shirish S
-Original Message-
From: Kuehling, Felix
Sent: Wednesday, September 11, 2019 9:09 AM
To: Huang, Ray ; S, Shirish ; Deucher,
Alexander ; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: fix build error without CONFIG_HSA_AMD
This is pretty ugly. See a suggestion inline.
On 2019-09-10 4:12 a.m., Huang, Ray wrote:
>> -Original Message-
>> From: S, Shirish
>> Sent: Tuesday, September 10, 2019 3:54 PM
>> To: Deucher, Alexander ; Koenig, Christian
>> ; Huang, Ray
>> Cc: amd-gfx@lists.freedesktop.org; S, Shirish
>> Subject: [PATCH] drm/amdgpu: fix build error without CONFIG_HSA_AMD
>>
>> If CONFIG_HSA_AMD is not set, build fails:
>>
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.o: In function
>> `amdgpu_device_ip_early_init':
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626: undefined reference
>> to `sched_policy'
>>
>> Use CONFIG_HSA_AMD to guard this.
>>
>> Fixes: 1abb680ad371 ("drm/amdgpu: disable gfxoff while use no H/W
>> scheduling policy")
>>
>> Signed-off-by: Shirish S
> + Felix for his awareness.
>
> Reviewed-by: Huang Rui
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
>> 2 files changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 1030cb30720c..a1516a3ae9a8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -169,7 +169,9 @@ extern int amdgpu_discovery; extern int
>> amdgpu_mes; extern int amdgpu_noretry; extern int
>> amdgpu_force_asic_type;
>> +#ifdef CONFIG_HSA_AMD
>> extern int sched_policy;
#else
static const int sched_policy = KFD_SCHED_POLICY_HWS; #endif
This way you don't need another set of ugly #ifdefs in amdgpu_device.c.
Regards,
Felix
>> +#endif
>>
>> #ifdef CONFIG_DRM_AMDGPU_SI
>> extern int amdgpu_si_support;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index bd423dd64e18..2535db27f821 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -1623,7 +1623,11 @@ static int amdgpu_device_ip_early_init(struct
>> amdgpu_device *adev)
>> }
>>
>> adev->pm.pp_feature = amdgpu_pp_feature_mask;
>> -if (amdgpu_sriov_vf(adev) || sched_policy ==
>> KFD_SCHED_POLICY_NO_HWS)
>> +if (amdgpu_sriov_vf(adev)
>> +#ifdef CONFIG_HSA_AMD
>> +|| sched_policy == KFD_SCHED_POLICY_NO_HWS
>> +#endif
>> +)
>> adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>>
>> for (i = 0; i < adev->num_ip_blocks; i++) {
>> --
>> 2.20.1
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[PATCH] drm/amdgpu: fix build error without CONFIG_HSA_AMD (V2)
If CONFIG_HSA_AMD is not set, build fails:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.o: In function
`amdgpu_device_ip_early_init':
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626: undefined reference to
`sched_policy'
Use CONFIG_HSA_AMD to guard this.
Fixes: 1abb680ad371 ("drm/amdgpu: disable gfxoff while use no H/W scheduling
policy")
V2: declare sched_policy in amdgpu.h and remove changes in amdgpu_device.c
Signed-off-by: Shirish S
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1030cb3..6ff02bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -169,7 +169,11 @@ extern int amdgpu_discovery;
extern int amdgpu_mes;
extern int amdgpu_noretry;
extern int amdgpu_force_asic_type;
+#ifdef CONFIG_HSA_AMD
extern int sched_policy;
+#else
+static const int sched_policy = KFD_SCHED_POLICY_HWS;
+#endif
#ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support;
--
2.7.4
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