[PATCH] drm/amd/display: prevent memory leak

[Navid Emamdoost]

In dcn*_create_resource_pool the allocated memory should be released if
construct pool fails.

Signed-off-by: Navid Emamdoost 
---
 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 1 +
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 1 +
 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 1 +
 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c   | 1 +
 5 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index afc61055eca1..1787b9bf800a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -1091,6 +1091,7 @@ struct resource_pool *dce100_create_resource_pool(
if (construct(num_virtual_links, dc, pool))
return >base;
 
+   kfree(pool);
BREAK_TO_DEBUGGER();
return NULL;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index c66fe170e1e8..318e9c2e2ca8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1462,6 +1462,7 @@ struct resource_pool *dce110_create_resource_pool(
if (construct(num_virtual_links, dc, pool, asic_id))
return >base;
 
+   kfree(pool);
BREAK_TO_DEBUGGER();
return NULL;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 3ac4c7e73050..3199d493d13b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1338,6 +1338,7 @@ struct resource_pool *dce112_create_resource_pool(
if (construct(num_virtual_links, dc, pool))
return >base;
 
+   kfree(pool);
BREAK_TO_DEBUGGER();
return NULL;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 7d08154e9662..bb497f43f6eb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -1203,6 +1203,7 @@ struct resource_pool *dce120_create_resource_pool(
if (construct(num_virtual_links, dc, pool))
return >base;
 
+   kfree(pool);
BREAK_TO_DEBUGGER();
return NULL;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 5a89e462e7cc..59305e411a66 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1570,6 +1570,7 @@ struct resource_pool *dcn10_create_resource_pool(
if (construct(init_data->num_virtual_links, dc, pool))
return >base;
 
+   kfree(pool);
BREAK_TO_DEBUGGER();
return NULL;
 }
-- 
2.17.1

Re: [PATCH] drm/amdgpu: return tcc_disabled_mask to userspace

[Alex Deucher]

On Tue, Sep 24, 2019 at 6:29 PM Marek Olšák  wrote:
>
> From: Marek Olšák 
>
> UMDs need this for correct programming of harvested chips.
>
> Signed-off-by: Marek Olšák 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  3 ++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 ++
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 11 +++
>  include/uapi/drm/amdgpu_drm.h   |  2 ++
>  5 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index f82d634cf3f9..b70b30378c20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -75,23 +75,24 @@
>   * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
>   * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
>   * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
>   * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
>   * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
>   * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
>   * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
>   * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
>   * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
>   * - 3.34.0 - Non-DC can flip correctly between buffers with different 
> pitches
> + * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
>   */
>  #define KMS_DRIVER_MAJOR   3
> -#define KMS_DRIVER_MINOR   34
> +#define KMS_DRIVER_MINOR   35
>  #define KMS_DRIVER_PATCHLEVEL  0
>
>  #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
>
>  int amdgpu_vram_limit = 0;
>  int amdgpu_vis_vram_limit = 0;
>  int amdgpu_gart_size = -1; /* auto */
>  int amdgpu_gtt_size = -1; /* auto */
>  int amdgpu_moverate = -1; /* auto */
>  int amdgpu_benchmarking = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 59c5464c96be..88dccff41dff 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -158,20 +158,21 @@ struct amdgpu_gfx_config {
> struct amdgpu_rb_config 
> rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
>
> /* gfx configure feature */
> uint32_t double_offchip_lds_buf;
> /* cached value of DB_DEBUG2 */
> uint32_t db_debug2;
> /* gfx10 specific config */
> uint32_t num_sc_per_sh;
> uint32_t num_packer_per_sc;
> uint32_t pa_sc_tile_steering_override;
> +   uint64_t tcc_disabled_mask;
>  };
>
>  struct amdgpu_cu_info {
> uint32_t simd_per_cu;
> uint32_t max_waves_per_simd;
> uint32_t wave_front_size;
> uint32_t max_scratch_slots_per_cu;
> uint32_t lds_size;
>
> /* total active CU number */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 91f5aaf99861..7356efe7e2d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -775,20 +775,22 @@ static int amdgpu_info_ioctl(struct drm_device *dev, 
> void *data, struct drm_file
> dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
> dev_info.num_tcc_blocks = 
> adev->gfx.config.max_texture_channel_caches;
> dev_info.gs_vgt_table_depth = 
> adev->gfx.config.gs_vgt_table_depth;
> dev_info.gs_prim_buffer_depth = 
> adev->gfx.config.gs_prim_buffer_depth;
> dev_info.max_gs_waves_per_vgt = 
> adev->gfx.config.max_gs_threads;
>
> if (adev->family >= AMDGPU_FAMILY_NV)
> dev_info.pa_sc_tile_steering_override =
> adev->gfx.config.pa_sc_tile_steering_override;
>
> +   dev_info.tcc_disabled_mask = 
> adev->gfx.config.tcc_disabled_mask;
> +
> return copy_to_user(out, _info,
> min((size_t)size, sizeof(dev_info))) ? 
> -EFAULT : 0;
> }
> case AMDGPU_INFO_VCE_CLOCK_TABLE: {
> unsigned i;
> struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
> struct amd_vce_state *vce_state;
>
> for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
> vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index cfc0952f6175..ca01643fa0c8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -1684,31 +1684,42 @@ static void gfx_v10_0_tcp_harvest(struct 
> amdgpu_device *adev)
> tmp |= (gcrd_targets_disable_tcp & 
> gcrd_targets_disable_mask);
> WREG32_SOC15(GC, 0, 
> 

[PATCH] drm/amdkfd: Add NAVI12 support from kfd side

[Liu, Shaoyun]

Add device info for both navi12 PF and VF

Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f329b82..270389b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -387,6 +387,24 @@ static const struct kfd_device_info navi10_device_info = {
.num_sdma_queues_per_engine = 8,
 };
 
+static const struct kfd_device_info navi12_device_info = {
+   .asic_family = CHIP_NAVI10,
+   .asic_name = "navi12",
+   .max_pasid_bits = 16,
+   .max_no_of_hqd  = 24,
+   .doorbell_size  = 8,
+   .ih_ring_entry_size = 8 * sizeof(uint32_t),
+   .event_interrupt_class = _interrupt_class_v9,
+   .num_of_watch_points = 4,
+   .mqd_size_aligned = MQD_SIZE_ALIGNED,
+   .needs_iommu_device = false,
+   .supports_cwsr = true,
+   .needs_pci_atomics = false,
+   .num_sdma_engines = 2,
+   .num_xgmi_sdma_engines = 0,
+   .num_sdma_queues_per_engine = 8,
+};
+
 static const struct kfd_device_info navi14_device_info = {
.asic_family = CHIP_NAVI14,
.asic_name = "navi14",
@@ -425,6 +443,7 @@ static const struct kfd_device_info 
*kfd_supported_devices[][2] = {
[CHIP_RENOIR] = {_device_info, NULL},
[CHIP_ARCTURUS] = {_device_info, _device_info},
[CHIP_NAVI10] = {_device_info, NULL},
+   [CHIP_NAVI12] = {_device_info, _device_info},
[CHIP_NAVI14] = {_device_info, NULL},
 };
 
-- 
2.7.4

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Re: [PATCH] drm/amdkfd: Add NAVI12 support from kfd side

[Zhao, Yong]

If Navi12 is the same as Navi10, then you can easily add the KFD support first, 
as it only involves a couple of lines because of recent simplification. Then 
have this patch next.

Regards,
Yong

From: Liu, Shaoyun 
Sent: Tuesday, September 24, 2019 6:28 PM
To: Zhao, Yong ; amd-gfx@lists.freedesktop.org 

Subject: Re: [PATCH] drm/amdkfd: Add NAVI12 support from kfd side


I will push to drm-next branch . After check the code again , this change will 
cause  issue in the  kfd since CHIP_NAVI12  not added  in other place where 
check the device_info->asic_family  in kfd code .  I think it's better just set 
the  family ID as CHIP_NAVI10  since there is no difference from the kfd side 
for NAVI10, NAVI12 andNAVI14.  I will send  another review .


Regards

shaoyun.liu


On 2019-09-24 6:17 p.m., Zhao, Yong wrote:
Reviewed-by: Yong Zhao 

Make sure to push to the new 5.3 branch.

Yong


From: amd-gfx 

 on behalf of Liu, Shaoyun 
Sent: Tuesday, September 24, 2019 6:16 PM
To: amd-gfx@lists.freedesktop.org 

Cc: Liu, Shaoyun 
Subject: [PATCH] drm/amdkfd: Add NAVI12 support from kfd side

Add device info for both navi12 PF and VF

Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f329b82..edfbae5c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -387,6 +387,24 @@ static const struct kfd_device_info navi10_device_info = {
 .num_sdma_queues_per_engine = 8,
 };

+static const struct kfd_device_info navi12_device_info = {
+   .asic_family = CHIP_NAVI12,
+   .asic_name = "navi12",
+   .max_pasid_bits = 16,
+   .max_no_of_hqd  = 24,
+   .doorbell_size  = 8,
+   .ih_ring_entry_size = 8 * sizeof(uint32_t),
+   .event_interrupt_class = _interrupt_class_v9,
+   .num_of_watch_points = 4,
+   .mqd_size_aligned = MQD_SIZE_ALIGNED,
+   .needs_iommu_device = false,
+   .supports_cwsr = true,
+   .needs_pci_atomics = false,
+   .num_sdma_engines = 2,
+   .num_xgmi_sdma_engines = 0,
+   .num_sdma_queues_per_engine = 8,
+};
+
 static const struct kfd_device_info navi14_device_info = {
 .asic_family = CHIP_NAVI14,
 .asic_name = "navi14",
@@ -425,6 +443,7 @@ static const struct kfd_device_info 
*kfd_supported_devices[][2] = {
 [CHIP_RENOIR] = {_device_info, NULL},
 [CHIP_ARCTURUS] = {_device_info, _device_info},
 [CHIP_NAVI10] = {_device_info, NULL},
+   [CHIP_NAVI12] = {_device_info, _device_info},
 [CHIP_NAVI14] = {_device_info, NULL},
 };

--
2.7.4

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[PATCH libdrm] include: update amdgpu_drm.h

[Marek Olšák]

From: Marek Olšák 

---
 include/drm/amdgpu_drm.h | 26 +++---
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 015bd9f4..bbdad866 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -121,20 +121,24 @@ extern "C" {
 /* Flag that allocating the BO should use linear VRAM */
 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS  (1 << 5)
 /* Flag that BO is always valid in this VM */
 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID  (1 << 6)
 /* Flag that BO sharing will be explicitly synchronized */
 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC(1 << 7)
 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
  * for the second page onward should be set to NC.
  */
 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
+/* Flag that BO may contain sensitive data that must be wiped before
+ * releasing the memory
+ */
+#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
 
 struct drm_amdgpu_gem_create_in  {
/** the requested memory size */
__u64 bo_size;
/** physical start_addr alignment in bytes for some HW requirements */
__u64 alignment;
/** the requested memory domains */
__u64 domains;
/** allocation flags */
__u64 domain_flags;
@@ -197,45 +201,49 @@ union drm_amdgpu_bo_list {
 
 /* GPU reset status */
 #define AMDGPU_CTX_NO_RESET0
 /* this the context caused it */
 #define AMDGPU_CTX_GUILTY_RESET1
 /* some other context caused it */
 #define AMDGPU_CTX_INNOCENT_RESET  2
 /* unknown cause */
 #define AMDGPU_CTX_UNKNOWN_RESET   3
 
-/* indicate gpu reset occurred after ctx created */
+/* indicate gpu reset occured after ctx created */
 #define AMDGPU_CTX_QUERY2_FLAGS_RESET(1<<0)
-/* indicate vram lost occurred after ctx created */
+/* indicate vram lost occured after ctx created */
 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
 /* indicate some job from this context once cause gpu hang */
 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
 /* indicate some errors are detected by RAS */
 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE   (1<<3)
 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE   (1<<4)
 
 /* Context priority level */
 #define AMDGPU_CTX_PRIORITY_UNSET   -2048
 #define AMDGPU_CTX_PRIORITY_VERY_LOW-1023
 #define AMDGPU_CTX_PRIORITY_LOW -512
 #define AMDGPU_CTX_PRIORITY_NORMAL  0
-/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
+/*
+ * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
+ * CAP_SYS_NICE or DRM_MASTER
+*/
 #define AMDGPU_CTX_PRIORITY_HIGH512
 #define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023
 
 struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */
__u32   op;
/** For future use, no flags defined so far */
__u32   flags;
__u32   ctx_id;
+   /** AMDGPU_CTX_PRIORITY_* */
__s32   priority;
 };
 
 union drm_amdgpu_ctx_out {
struct {
__u32   ctx_id;
__u32   _pad;
} alloc;
 
struct {
@@ -274,20 +282,21 @@ union drm_amdgpu_vm {
 };
 
 /* sched ioctl */
 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE  1
 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE  2
 
 struct drm_amdgpu_sched_in {
/* AMDGPU_SCHED_OP_* */
__u32   op;
__u32   fd;
+   /** AMDGPU_CTX_PRIORITY_* */
__s32   priority;
__u32   ctx_id;
 };
 
 union drm_amdgpu_sched {
struct drm_amdgpu_sched_in in;
 };
 
 /*
  * This is not a reliable API and you should expect it to fail for any
@@ -484,20 +493,22 @@ struct drm_amdgpu_gem_op {
 /* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
 #define AMDGPU_VM_MTYPE_DEFAULT(0 << 5)
 /* Use NC MTYPE instead of default MTYPE */
 #define AMDGPU_VM_MTYPE_NC (1 << 5)
 /* Use WC MTYPE instead of default MTYPE */
 #define AMDGPU_VM_MTYPE_WC (2 << 5)
 /* Use CC MTYPE instead of default MTYPE */
 #define AMDGPU_VM_MTYPE_CC (3 << 5)
 /* Use UC MTYPE instead of default MTYPE */
 #define AMDGPU_VM_MTYPE_UC (4 << 5)
+/* Use RW MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_RW (5 << 5)
 
 struct drm_amdgpu_gem_va {
/** GEM object handle */
__u32 handle;
__u32 _pad;
/** AMDGPU_VA_OP_* */
__u32 operation;
/** AMDGPU_VM_PAGE_* */
__u32 flags;
/** va address to assign . Must be correctly aligned.*/
@@ -604,26 +615,25 @@ struct drm_amdgpu_cs_chunk_dep {
 struct drm_amdgpu_cs_chunk_fence {
__u32 handle;
__u32 offset;
 };
 
 struct drm_amdgpu_cs_chunk_sem {
__u32 handle;
 };
 
 struct drm_amdgpu_cs_chunk_syncobj {
-   __u32 handle;
-   __u32 flags;
-   __u64 point;
+   __u32 handle;
+   __u32 flags;
+   

[PATCH] drm/amdgpu: return tcc_disabled_mask to userspace

[Marek Olšák]

From: Marek Olšák 

UMDs need this for correct programming of harvested chips.

Signed-off-by: Marek Olšák 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 11 +++
 include/uapi/drm/amdgpu_drm.h   |  2 ++
 5 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index f82d634cf3f9..b70b30378c20 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -75,23 +75,24 @@
  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
  * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
  * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
  * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
  * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
  * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
  * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
  * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
+ * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
  */
 #define KMS_DRIVER_MAJOR   3
-#define KMS_DRIVER_MINOR   34
+#define KMS_DRIVER_MINOR   35
 #define KMS_DRIVER_PATCHLEVEL  0
 
 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
 
 int amdgpu_vram_limit = 0;
 int amdgpu_vis_vram_limit = 0;
 int amdgpu_gart_size = -1; /* auto */
 int amdgpu_gtt_size = -1; /* auto */
 int amdgpu_moverate = -1; /* auto */
 int amdgpu_benchmarking = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 59c5464c96be..88dccff41dff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -158,20 +158,21 @@ struct amdgpu_gfx_config {
struct amdgpu_rb_config 
rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
 
/* gfx configure feature */
uint32_t double_offchip_lds_buf;
/* cached value of DB_DEBUG2 */
uint32_t db_debug2;
/* gfx10 specific config */
uint32_t num_sc_per_sh;
uint32_t num_packer_per_sc;
uint32_t pa_sc_tile_steering_override;
+   uint64_t tcc_disabled_mask;
 };
 
 struct amdgpu_cu_info {
uint32_t simd_per_cu;
uint32_t max_waves_per_simd;
uint32_t wave_front_size;
uint32_t max_scratch_slots_per_cu;
uint32_t lds_size;
 
/* total active CU number */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 91f5aaf99861..7356efe7e2d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -775,20 +775,22 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
dev_info.num_tcc_blocks = 
adev->gfx.config.max_texture_channel_caches;
dev_info.gs_vgt_table_depth = 
adev->gfx.config.gs_vgt_table_depth;
dev_info.gs_prim_buffer_depth = 
adev->gfx.config.gs_prim_buffer_depth;
dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 
if (adev->family >= AMDGPU_FAMILY_NV)
dev_info.pa_sc_tile_steering_override =
adev->gfx.config.pa_sc_tile_steering_override;
 
+   dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
+
return copy_to_user(out, _info,
min((size_t)size, sizeof(dev_info))) ? 
-EFAULT : 0;
}
case AMDGPU_INFO_VCE_CLOCK_TABLE: {
unsigned i;
struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
struct amd_vce_state *vce_state;
 
for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index cfc0952f6175..ca01643fa0c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1684,31 +1684,42 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device 
*adev)
tmp |= (gcrd_targets_disable_tcp & 
gcrd_targets_disable_mask);
WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, 
tmp);
}
}
 
gfx_v10_0_select_se_sh(adev, 0x, 0x, 
0x);
mutex_unlock(>grbm_idx_mutex);
}
 }
 
+static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
+{

Re: [PATCH] drm/amdkfd: Add NAVI12 support from kfd side

[Liu, Shaoyun]

I will push to drm-next branch . After check the code again , this change will 
cause  issue in the  kfd since CHIP_NAVI12  not added  in other place where 
check the device_info->asic_family  in kfd code .  I think it's better just set 
the  family ID as CHIP_NAVI10  since there is no difference from the kfd side 
for NAVI10, NAVI12 andNAVI14.  I will send  another review .


Regards

shaoyun.liu


On 2019-09-24 6:17 p.m., Zhao, Yong wrote:
Reviewed-by: Yong Zhao 

Make sure to push to the new 5.3 branch.

Yong


From: amd-gfx 

 on behalf of Liu, Shaoyun 
Sent: Tuesday, September 24, 2019 6:16 PM
To: amd-gfx@lists.freedesktop.org 

Cc: Liu, Shaoyun 
Subject: [PATCH] drm/amdkfd: Add NAVI12 support from kfd side

Add device info for both navi12 PF and VF

Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f329b82..edfbae5c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -387,6 +387,24 @@ static const struct kfd_device_info navi10_device_info = {
 .num_sdma_queues_per_engine = 8,
 };

+static const struct kfd_device_info navi12_device_info = {
+   .asic_family = CHIP_NAVI12,
+   .asic_name = "navi12",
+   .max_pasid_bits = 16,
+   .max_no_of_hqd  = 24,
+   .doorbell_size  = 8,
+   .ih_ring_entry_size = 8 * sizeof(uint32_t),
+   .event_interrupt_class = _interrupt_class_v9,
+   .num_of_watch_points = 4,
+   .mqd_size_aligned = MQD_SIZE_ALIGNED,
+   .needs_iommu_device = false,
+   .supports_cwsr = true,
+   .needs_pci_atomics = false,
+   .num_sdma_engines = 2,
+   .num_xgmi_sdma_engines = 0,
+   .num_sdma_queues_per_engine = 8,
+};
+
 static const struct kfd_device_info navi14_device_info = {
 .asic_family = CHIP_NAVI14,
 .asic_name = "navi14",
@@ -425,6 +443,7 @@ static const struct kfd_device_info 
*kfd_supported_devices[][2] = {
 [CHIP_RENOIR] = {_device_info, NULL},
 [CHIP_ARCTURUS] = {_device_info, _device_info},
 [CHIP_NAVI10] = {_device_info, NULL},
+   [CHIP_NAVI12] = {_device_info, _device_info},
 [CHIP_NAVI14] = {_device_info, NULL},
 };

--
2.7.4

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Re: [PATCH] drm/amdkfd: Add NAVI12 support from kfd side

[Zhao, Yong]

Reviewed-by: Yong Zhao 

Make sure to push to the new 5.3 branch.

Yong


From: amd-gfx  on behalf of Liu, Shaoyun 

Sent: Tuesday, September 24, 2019 6:16 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Liu, Shaoyun 
Subject: [PATCH] drm/amdkfd: Add NAVI12 support from kfd side

Add device info for both navi12 PF and VF

Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f329b82..edfbae5c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -387,6 +387,24 @@ static const struct kfd_device_info navi10_device_info = {
 .num_sdma_queues_per_engine = 8,
 };

+static const struct kfd_device_info navi12_device_info = {
+   .asic_family = CHIP_NAVI12,
+   .asic_name = "navi12",
+   .max_pasid_bits = 16,
+   .max_no_of_hqd  = 24,
+   .doorbell_size  = 8,
+   .ih_ring_entry_size = 8 * sizeof(uint32_t),
+   .event_interrupt_class = _interrupt_class_v9,
+   .num_of_watch_points = 4,
+   .mqd_size_aligned = MQD_SIZE_ALIGNED,
+   .needs_iommu_device = false,
+   .supports_cwsr = true,
+   .needs_pci_atomics = false,
+   .num_sdma_engines = 2,
+   .num_xgmi_sdma_engines = 0,
+   .num_sdma_queues_per_engine = 8,
+};
+
 static const struct kfd_device_info navi14_device_info = {
 .asic_family = CHIP_NAVI14,
 .asic_name = "navi14",
@@ -425,6 +443,7 @@ static const struct kfd_device_info 
*kfd_supported_devices[][2] = {
 [CHIP_RENOIR] = {_device_info, NULL},
 [CHIP_ARCTURUS] = {_device_info, _device_info},
 [CHIP_NAVI10] = {_device_info, NULL},
+   [CHIP_NAVI12] = {_device_info, _device_info},
 [CHIP_NAVI14] = {_device_info, NULL},
 };

--
2.7.4

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[PATCH] drm/amdkfd: Add NAVI12 support from kfd side

[Liu, Shaoyun]

Add device info for both navi12 PF and VF

Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f329b82..edfbae5c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -387,6 +387,24 @@ static const struct kfd_device_info navi10_device_info = {
.num_sdma_queues_per_engine = 8,
 };
 
+static const struct kfd_device_info navi12_device_info = {
+   .asic_family = CHIP_NAVI12,
+   .asic_name = "navi12",
+   .max_pasid_bits = 16,
+   .max_no_of_hqd  = 24,
+   .doorbell_size  = 8,
+   .ih_ring_entry_size = 8 * sizeof(uint32_t),
+   .event_interrupt_class = _interrupt_class_v9,
+   .num_of_watch_points = 4,
+   .mqd_size_aligned = MQD_SIZE_ALIGNED,
+   .needs_iommu_device = false,
+   .supports_cwsr = true,
+   .needs_pci_atomics = false,
+   .num_sdma_engines = 2,
+   .num_xgmi_sdma_engines = 0,
+   .num_sdma_queues_per_engine = 8,
+};
+
 static const struct kfd_device_info navi14_device_info = {
.asic_family = CHIP_NAVI14,
.asic_name = "navi14",
@@ -425,6 +443,7 @@ static const struct kfd_device_info 
*kfd_supported_devices[][2] = {
[CHIP_RENOIR] = {_device_info, NULL},
[CHIP_ARCTURUS] = {_device_info, _device_info},
[CHIP_NAVI10] = {_device_info, NULL},
+   [CHIP_NAVI12] = {_device_info, _device_info},
[CHIP_NAVI14] = {_device_info, NULL},
 };
 
-- 
2.7.4

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[PATCH] drm/amdgpu: Add NAVI12 support from kfd side

[Liu, Shaoyun]

Add device info for both navi12 PF and VF

Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f329b82..edfbae5c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -387,6 +387,24 @@ static const struct kfd_device_info navi10_device_info = {
.num_sdma_queues_per_engine = 8,
 };
 
+static const struct kfd_device_info navi12_device_info = {
+   .asic_family = CHIP_NAVI12,
+   .asic_name = "navi12",
+   .max_pasid_bits = 16,
+   .max_no_of_hqd  = 24,
+   .doorbell_size  = 8,
+   .ih_ring_entry_size = 8 * sizeof(uint32_t),
+   .event_interrupt_class = _interrupt_class_v9,
+   .num_of_watch_points = 4,
+   .mqd_size_aligned = MQD_SIZE_ALIGNED,
+   .needs_iommu_device = false,
+   .supports_cwsr = true,
+   .needs_pci_atomics = false,
+   .num_sdma_engines = 2,
+   .num_xgmi_sdma_engines = 0,
+   .num_sdma_queues_per_engine = 8,
+};
+
 static const struct kfd_device_info navi14_device_info = {
.asic_family = CHIP_NAVI14,
.asic_name = "navi14",
@@ -425,6 +443,7 @@ static const struct kfd_device_info 
*kfd_supported_devices[][2] = {
[CHIP_RENOIR] = {_device_info, NULL},
[CHIP_ARCTURUS] = {_device_info, _device_info},
[CHIP_NAVI10] = {_device_info, NULL},
+   [CHIP_NAVI12] = {_device_info, _device_info},
[CHIP_NAVI14] = {_device_info, NULL},
 };
 
-- 
2.7.4

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Re: [PATCH v2 3/4] device_cgroup: Export devcgroup_check_permission

[Roman Gushchin]

On Tue, Sep 24, 2019 at 03:54:47PM +, Kasiviswanathan, Harish wrote:
> Hi Tejun,
> 
> Can you please review this? You and Roman acked this patch before. It will be 
> great if I can Reviewed-by, so that I can upstream this through Alex 
> Deucher's amd-staging-drm-next and Dave Airlie's drm-next trees
> 
> Thanks,
> Harish

Hello, Harish!

If it can help, please, feel free to use
Reviewed-by: Roman Gushchin 

Thanks!

> 
> 
> -Original Message-
> From: Kasiviswanathan, Harish  
> Sent: Monday, September 16, 2019 2:06 PM
> To: t...@kernel.org; Deucher, Alexander ; 
> airl...@redhat.com
> Cc: cgro...@vger.kernel.org; amd-gfx@lists.freedesktop.org; Kasiviswanathan, 
> Harish 
> Subject: [PATCH v2 3/4] device_cgroup: Export devcgroup_check_permission
> 
> For AMD compute (amdkfd) driver.
> 
> All AMD compute devices are exported via single device node /dev/kfd. As
> a result devices cannot be controlled individually using device cgroup.
> 
> AMD compute devices will rely on its graphics counterpart that exposes
> /dev/dri/renderN node for each device. For each task (based on its
> cgroup), KFD driver will check if /dev/dri/renderN node is accessible
> before exposing it.
> 
> Change-Id: I9ae283df550b2c122d67870b0cfa316bfbf3b614
> Acked-by: Felix Kuehling 
> Acked-by: Tejun Heo 
> Acked-by: Roman Gushchin 
> Signed-off-by: Harish Kasiviswanathan 
> ---
>  include/linux/device_cgroup.h | 19 ---
>  security/device_cgroup.c  | 15 +--
>  2 files changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/include/linux/device_cgroup.h b/include/linux/device_cgroup.h
> index 8557efe096dc..fa35b52e0002 100644
> --- a/include/linux/device_cgroup.h
> +++ b/include/linux/device_cgroup.h
> @@ -12,26 +12,15 @@
>  #define DEVCG_DEV_ALL   4  /* this represents all devices */
>  
>  #ifdef CONFIG_CGROUP_DEVICE
> -extern int __devcgroup_check_permission(short type, u32 major, u32 minor,
> - short access);
> +int devcgroup_check_permission(short type, u32 major, u32 minor,
> +short access);
>  #else
> -static inline int __devcgroup_check_permission(short type, u32 major, u32 
> minor,
> -short access)
> +static inline int devcgroup_check_permission(short type, u32 major, u32 
> minor,
> +  short access)
>  { return 0; }
>  #endif
>  
>  #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF)
> -static inline int devcgroup_check_permission(short type, u32 major, u32 
> minor,
> -  short access)
> -{
> - int rc = BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type, major, minor, access);
> -
> - if (rc)
> - return -EPERM;
> -
> - return __devcgroup_check_permission(type, major, minor, access);
> -}
> -
>  static inline int devcgroup_inode_permission(struct inode *inode, int mask)
>  {
>   short type, access = 0;
> diff --git a/security/device_cgroup.c b/security/device_cgroup.c
> index dc28914fa72e..04dd29bf7f06 100644
> --- a/security/device_cgroup.c
> +++ b/security/device_cgroup.c
> @@ -801,8 +801,8 @@ struct cgroup_subsys devices_cgrp_subsys = {
>   *
>   * returns 0 on success, -EPERM case the operation is not permitted
>   */
> -int __devcgroup_check_permission(short type, u32 major, u32 minor,
> -  short access)
> +static int __devcgroup_check_permission(short type, u32 major, u32 minor,
> + short access)
>  {
>   struct dev_cgroup *dev_cgroup;
>   bool rc;
> @@ -824,3 +824,14 @@ int __devcgroup_check_permission(short type, u32 major, 
> u32 minor,
>  
>   return 0;
>  }
> +
> +int devcgroup_check_permission(short type, u32 major, u32 minor, short 
> access)
> +{
> + int rc = BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type, major, minor, access);
> +
> + if (rc)
> + return -EPERM;
> +
> + return __devcgroup_check_permission(type, major, minor, access);
> +}
> +EXPORT_SYMBOL(devcgroup_check_permission);
> -- 
> 2.17.1
> 
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Re: [PATCH v2 8/9] drm/amdgpu: use drm_debug_enabled() to check for debug categories

[Alex Deucher]

On Tue, Sep 24, 2019 at 9:00 AM Jani Nikula  wrote:
>
> Allow better abstraction of the drm_debug global variable in the
> future. No functional changes.
>
> Cc: Alex Deucher 
> Cc: Christian König 
> Cc: David (ChunMing) Zhou 
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Jani Nikula 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 
> b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> index 4a5951036927..5f17bd4899e2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> @@ -234,7 +234,7 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter 
> *control,
> DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
>  (uint16_t)address, numbytes);
>
> -   if (drm_debug & DRM_UT_DRIVER) {
> +   if (drm_debug_enabled(DRM_UT_DRIVER)) {
> print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
>16, 1, data, numbytes, false);
> }
> @@ -388,7 +388,7 @@ static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter 
> *control,
> DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
>   (uint16_t)address, bytes_received);
>
> -   if (drm_debug & DRM_UT_DRIVER) {
> +   if (drm_debug_enabled(DRM_UT_DRIVER)) {
> print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
>16, 1, data, bytes_received, false);
> }
> --
> 2.20.1
>
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[PATCH AUTOSEL 4.9 14/19] drm/amdgpu/si: fix ASIC tests

[Sasha Levin]

From: Jean Delvare 

[ Upstream commit 77efe48a729588527afb4d5811b9e0acb29f5e51 ]

Comparing adev->family with CHIP constants is not correct.
adev->family can only be compared with AMDGPU_FAMILY constants and
adev->asic_type is the struct member to compare with CHIP constants.
They are separate identification spaces.

Signed-off-by: Jean Delvare 
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: "David (ChunMing) Zhou" 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/si.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 327bdf13e8bc8..b0beb5e537bcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1606,7 +1606,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
 
-   if ((adev->family != CHIP_OLAND) && (adev->family != 
CHIP_HAINAN)) {
+   if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type 
!= CHIP_HAINAN)) {
orig = data = 
si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
data &= ~PLL_RAMP_UP_TIME_0_MASK;
if (orig != data)
@@ -1655,14 +1655,14 @@ static void si_program_aspm(struct amdgpu_device *adev)
 
orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
-   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type 
== CHIP_HAINAN))
data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
 
orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
-   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type 
== CHIP_HAINAN))
data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
-- 
2.20.1

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[PATCH AUTOSEL 4.4 02/14] gpu: drm: radeon: Fix a possible null-pointer dereference in radeon_connector_set_property()

[Sasha Levin]

From: Jia-Ju Bai 

[ Upstream commit f3eb9b8f67bc28783eddc142ad805ebdc53d6339 ]

In radeon_connector_set_property(), there is an if statement on line 743
to check whether connector->encoder is NULL:
if (connector->encoder)

When connector->encoder is NULL, it is used on line 755:
if (connector->encoder->crtc)

Thus, a possible null-pointer dereference may occur.

To fix this bug, connector->encoder is checked before being used.

This bug is found by a static analysis tool STCheck written by us.

Signed-off-by: Jia-Ju Bai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index c6bf378534f83..bebcef2ce6b88 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -758,7 +758,7 @@ static int radeon_connector_set_property(struct 
drm_connector *connector, struct
 
radeon_encoder->output_csc = val;
 
-   if (connector->encoder->crtc) {
+   if (connector->encoder && connector->encoder->crtc) {
struct drm_crtc *crtc  = connector->encoder->crtc;
const struct drm_crtc_helper_funcs *crtc_funcs = 
crtc->helper_private;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-- 
2.20.1

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[PATCH AUTOSEL 4.9 04/19] gpu: drm: radeon: Fix a possible null-pointer dereference in radeon_connector_set_property()

[Sasha Levin]

From: Jia-Ju Bai 

[ Upstream commit f3eb9b8f67bc28783eddc142ad805ebdc53d6339 ]

In radeon_connector_set_property(), there is an if statement on line 743
to check whether connector->encoder is NULL:
if (connector->encoder)

When connector->encoder is NULL, it is used on line 755:
if (connector->encoder->crtc)

Thus, a possible null-pointer dereference may occur.

To fix this bug, connector->encoder is checked before being used.

This bug is found by a static analysis tool STCheck written by us.

Signed-off-by: Jia-Ju Bai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index c5e1aa5f1d8ea..efa875120071a 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -764,7 +764,7 @@ static int radeon_connector_set_property(struct 
drm_connector *connector, struct
 
radeon_encoder->output_csc = val;
 
-   if (connector->encoder->crtc) {
+   if (connector->encoder && connector->encoder->crtc) {
struct drm_crtc *crtc  = connector->encoder->crtc;
const struct drm_crtc_helper_funcs *crtc_funcs = 
crtc->helper_private;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-- 
2.20.1

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[PATCH AUTOSEL 4.9 03/19] drm/radeon: Fix EEH during kexec

[Sasha Levin]

From: KyleMahlkuch 

[ Upstream commit 6f7fe9a93e6c09bf988c5059403f5f88e17e21e6 ]

During kexec some adapters hit an EEH since they are not properly
shut down in the radeon_pci_shutdown() function. Adding
radeon_suspend_kms() fixes this issue.

Signed-off-by: KyleMahlkuch 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_drv.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index 30bd4a6a9d466..3ccf5b28b326e 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -366,11 +366,19 @@ radeon_pci_remove(struct pci_dev *pdev)
 static void
 radeon_pci_shutdown(struct pci_dev *pdev)
 {
+   struct drm_device *ddev = pci_get_drvdata(pdev);
+
/* if we are running in a VM, make sure the device
 * torn down properly on reboot/shutdown
 */
if (radeon_device_is_virtual())
radeon_pci_remove(pdev);
+
+   /* Some adapters need to be suspended before a
+   * shutdown occurs in order to prevent an error
+   * during kexec.
+   */
+   radeon_suspend_kms(ddev, true, true, false);
 }
 
 static int radeon_pmops_suspend(struct device *dev)
-- 
2.20.1

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[PATCH AUTOSEL 4.9 07/19] drm/amd/powerplay/smu7: enforce minimal VBITimeout (v2)

[Sasha Levin]

From: Ahzo 

[ Upstream commit f659bb6dae58c113805f92822e4c16ddd3156b79 ]

This fixes screen corruption/flickering on 75 Hz displays.

v2: make print statement debug only (Alex)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102646
Reviewed-by: Evan Quan 
Signed-off-by: Ahzo 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 3907439417e76..c0db3b57dfe58 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3739,6 +3739,11 @@ int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
 
data->frame_time_x2 = frame_time_in_us * 2 / 100;
 
+   if (data->frame_time_x2 < 280) {
+   pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", 
__func__, data->frame_time_x2);
+   data->frame_time_x2 = 280;
+   }
+
display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
 
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
ixCG_DISPLAY_GAP_CNTL2, display_gap2);
-- 
2.20.1

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[PATCH AUTOSEL 4.14 22/28] drm/amdgpu/si: fix ASIC tests

[Sasha Levin]

From: Jean Delvare 

[ Upstream commit 77efe48a729588527afb4d5811b9e0acb29f5e51 ]

Comparing adev->family with CHIP constants is not correct.
adev->family can only be compared with AMDGPU_FAMILY constants and
adev->asic_type is the struct member to compare with CHIP constants.
They are separate identification spaces.

Signed-off-by: Jean Delvare 
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: "David (ChunMing) Zhou" 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/si.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 40520a968eaca..28eea8317e87d 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1783,7 +1783,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
 
-   if ((adev->family != CHIP_OLAND) && (adev->family != 
CHIP_HAINAN)) {
+   if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type 
!= CHIP_HAINAN)) {
orig = data = 
si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
data &= ~PLL_RAMP_UP_TIME_0_MASK;
if (orig != data)
@@ -1832,14 +1832,14 @@ static void si_program_aspm(struct amdgpu_device *adev)
 
orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
-   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type 
== CHIP_HAINAN))
data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
 
orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
-   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type 
== CHIP_HAINAN))
data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
-- 
2.20.1

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[PATCH AUTOSEL 4.14 11/28] drm/amd/powerplay/smu7: enforce minimal VBITimeout (v2)

[Sasha Levin]

From: Ahzo 

[ Upstream commit f659bb6dae58c113805f92822e4c16ddd3156b79 ]

This fixes screen corruption/flickering on 75 Hz displays.

v2: make print statement debug only (Alex)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102646
Reviewed-by: Evan Quan 
Signed-off-by: Ahzo 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 336fdd8c7db08..61141bc3edfe9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3972,6 +3972,11 @@ static int smu7_program_display_gap(struct pp_hwmgr 
*hwmgr)
 
data->frame_time_x2 = frame_time_in_us * 2 / 100;
 
+   if (data->frame_time_x2 < 280) {
+   pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", 
__func__, data->frame_time_x2);
+   data->frame_time_x2 = 280;
+   }
+
display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
 
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
ixCG_DISPLAY_GAP_CNTL2, display_gap2);
-- 
2.20.1

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[PATCH AUTOSEL 4.14 06/28] drm/radeon: Fix EEH during kexec

[Sasha Levin]

From: KyleMahlkuch 

[ Upstream commit 6f7fe9a93e6c09bf988c5059403f5f88e17e21e6 ]

During kexec some adapters hit an EEH since they are not properly
shut down in the radeon_pci_shutdown() function. Adding
radeon_suspend_kms() fixes this issue.

Signed-off-by: KyleMahlkuch 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_drv.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index f4becad0a78c0..54d97dd5780a1 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -368,11 +368,19 @@ radeon_pci_remove(struct pci_dev *pdev)
 static void
 radeon_pci_shutdown(struct pci_dev *pdev)
 {
+   struct drm_device *ddev = pci_get_drvdata(pdev);
+
/* if we are running in a VM, make sure the device
 * torn down properly on reboot/shutdown
 */
if (radeon_device_is_virtual())
radeon_pci_remove(pdev);
+
+   /* Some adapters need to be suspended before a
+   * shutdown occurs in order to prevent an error
+   * during kexec.
+   */
+   radeon_suspend_kms(ddev, true, true, false);
 }
 
 static int radeon_pmops_suspend(struct device *dev)
-- 
2.20.1

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[PATCH AUTOSEL 4.14 07/28] gpu: drm: radeon: Fix a possible null-pointer dereference in radeon_connector_set_property()

[Sasha Levin]

From: Jia-Ju Bai 

[ Upstream commit f3eb9b8f67bc28783eddc142ad805ebdc53d6339 ]

In radeon_connector_set_property(), there is an if statement on line 743
to check whether connector->encoder is NULL:
if (connector->encoder)

When connector->encoder is NULL, it is used on line 755:
if (connector->encoder->crtc)

Thus, a possible null-pointer dereference may occur.

To fix this bug, connector->encoder is checked before being used.

This bug is found by a static analysis tool STCheck written by us.

Signed-off-by: Jia-Ju Bai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 337d3a1c2a409..48f752cf7a920 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -764,7 +764,7 @@ static int radeon_connector_set_property(struct 
drm_connector *connector, struct
 
radeon_encoder->output_csc = val;
 
-   if (connector->encoder->crtc) {
+   if (connector->encoder && connector->encoder->crtc) {
struct drm_crtc *crtc  = connector->encoder->crtc;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
-- 
2.20.1

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[PATCH AUTOSEL 4.19 35/50] drm/amd/display: support spdif

[Sasha Levin]

From: Charlene Liu 

[ Upstream commit b5a41620bb88efb9fb31a4fa5e652e3d5bead7d4 ]

[Description]
port spdif fix to staging:
 spdif hardwired to afmt inst 1.
 spdif func pointer
 spdif resource allocation (reserve last audio endpoint for spdif only)

Signed-off-by: Charlene Liu 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c   | 17 -
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c  |  4 ++--
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index f0d68aa7c8fcc..d440b28ee43fb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -229,12 +229,10 @@ bool resource_construct(
DC_ERR("DC: failed to create audio!\n");
return false;
}
-
if (!aud->funcs->endpoint_valid(aud)) {
aud->funcs->destroy();
break;
}
-
pool->audios[i] = aud;
pool->audio_count++;
}
@@ -1703,24 +1701,25 @@ static struct audio *find_first_free_audio(
const struct resource_pool *pool,
enum engine_id id)
 {
-   int i;
-   for (i = 0; i < pool->audio_count; i++) {
+   int i, available_audio_count;
+
+   available_audio_count = pool->audio_count;
+
+   for (i = 0; i < available_audio_count; i++) {
if ((res_ctx->is_audio_acquired[i] == false) && 
(res_ctx->is_stream_enc_acquired[i] == true)) {
/*we have enough audio endpoint, find the matching 
inst*/
if (id != i)
continue;
-
return pool->audios[i];
}
}
 
-/* use engine id to find free audio */
-   if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == 
false)) {
+   /* use engine id to find free audio */
+   if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == 
false)) {
return pool->audios[id];
}
-
/*not found the matching one, first come first serve*/
-   for (i = 0; i < pool->audio_count; i++) {
+   for (i = 0; i < available_audio_count; i++) {
if (res_ctx->is_audio_acquired[i] == false) {
return pool->audios[i];
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 7f6d724686f1a..abb559ce64085 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -611,6 +611,8 @@ void dce_aud_az_configure(
 
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
value);
+   DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, 
displayName %s: \n",
+   audio->inst, value, audio_info->display_name);
 
/*
*write the port ID:
@@ -922,7 +924,6 @@ static const struct audio_funcs funcs = {
.az_configure = dce_aud_az_configure,
.destroy = dce_aud_destroy,
 };
-
 void dce_aud_destroy(struct audio **audio)
 {
struct dce_audio *aud = DCE_AUD(*audio);
@@ -953,7 +954,6 @@ struct audio *dce_audio_create(
audio->regs = reg;
audio->shifts = shifts;
audio->masks = masks;
-
return >base;
 }
 
-- 
2.20.1

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[PATCH AUTOSEL 4.19 36/50] drm/amdgpu/si: fix ASIC tests

[Sasha Levin]

From: Jean Delvare 

[ Upstream commit 77efe48a729588527afb4d5811b9e0acb29f5e51 ]

Comparing adev->family with CHIP constants is not correct.
adev->family can only be compared with AMDGPU_FAMILY constants and
adev->asic_type is the struct member to compare with CHIP constants.
They are separate identification spaces.

Signed-off-by: Jean Delvare 
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: "David (ChunMing) Zhou" 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/si.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index c364ef94cc366..77c9f4d8668ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1813,7 +1813,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
 
-   if ((adev->family != CHIP_OLAND) && (adev->family != 
CHIP_HAINAN)) {
+   if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type 
!= CHIP_HAINAN)) {
orig = data = 
si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
data &= ~PLL_RAMP_UP_TIME_0_MASK;
if (orig != data)
@@ -1862,14 +1862,14 @@ static void si_program_aspm(struct amdgpu_device *adev)
 
orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
-   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type 
== CHIP_HAINAN))
data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
 
orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
-   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type 
== CHIP_HAINAN))
data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
-- 
2.20.1

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[PATCH AUTOSEL 4.19 10/50] gpu: drm: radeon: Fix a possible null-pointer dereference in radeon_connector_set_property()

[Sasha Levin]

From: Jia-Ju Bai 

[ Upstream commit f3eb9b8f67bc28783eddc142ad805ebdc53d6339 ]

In radeon_connector_set_property(), there is an if statement on line 743
to check whether connector->encoder is NULL:
if (connector->encoder)

When connector->encoder is NULL, it is used on line 755:
if (connector->encoder->crtc)

Thus, a possible null-pointer dereference may occur.

To fix this bug, connector->encoder is checked before being used.

This bug is found by a static analysis tool STCheck written by us.

Signed-off-by: Jia-Ju Bai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 414642e5b7a31..de656f5553839 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -751,7 +751,7 @@ static int radeon_connector_set_property(struct 
drm_connector *connector, struct
 
radeon_encoder->output_csc = val;
 
-   if (connector->encoder->crtc) {
+   if (connector->encoder && connector->encoder->crtc) {
struct drm_crtc *crtc  = connector->encoder->crtc;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
-- 
2.20.1

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[PATCH AUTOSEL 4.19 16/50] drm/amd/display: reprogram VM config when system resume

[Sasha Levin]

From: Lewis Huang 

[ Upstream commit e5382701c3520b3ed66169a6e4aa6ce5df8c56e0 ]

[Why]
The vm config will be clear to 0 when system enter S4. It will
cause hubbub didn't know how to fetch data when system resume.
The flip always pending because earliest_inuse_address and
request_address are different.

[How]
Reprogram VM config when system resume

Signed-off-by: Lewis Huang 
Reviewed-by: Jun Lei 
Acked-by: Eric Yang 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f4b89d1ea6f6f..2b2efe443c36d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1585,6 +1585,14 @@ void dc_set_power_state(
dc_resource_state_construct(dc, dc->current_state);
 
dc->hwss.init_hw(dc);
+
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+   if (dc->hwss.init_sys_ctx != NULL &&
+   dc->vm_pa_config.valid) {
+   dc->hwss.init_sys_ctx(dc->hwseq, dc, >vm_pa_config);
+   }
+#endif
+
break;
default:
 
-- 
2.20.1

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[PATCH AUTOSEL 4.19 18/50] drm/amd/powerplay/smu7: enforce minimal VBITimeout (v2)

[Sasha Levin]

From: Ahzo 

[ Upstream commit f659bb6dae58c113805f92822e4c16ddd3156b79 ]

This fixes screen corruption/flickering on 75 Hz displays.

v2: make print statement debug only (Alex)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102646
Reviewed-by: Evan Quan 
Signed-off-by: Ahzo 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b52ccab428a9e..c7c505095402d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4052,6 +4052,11 @@ static int smu7_program_display_gap(struct pp_hwmgr 
*hwmgr)
 
data->frame_time_x2 = frame_time_in_us * 2 / 100;
 
+   if (data->frame_time_x2 < 280) {
+   pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", 
__func__, data->frame_time_x2);
+   data->frame_time_x2 = 280;
+   }
+
display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
 
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
ixCG_DISPLAY_GAP_CNTL2, display_gap2);
-- 
2.20.1

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[PATCH AUTOSEL 4.19 15/50] drm/amd/display: fix issue where 252-255 values are clipped

[Sasha Levin]

From: Anthony Koo 

[ Upstream commit 1cbcfc975164f397b449efb17f59d81a703090db ]

[Why]
When endpoint is at the boundary of a region, such as at 2^0=1
we find that the last segment has a sharp slope and some points
are clipped at the top.

[How]
If end point is 1, which is exactly at the 2^0 region boundary, we
need to program an additional region beyond this point.

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 5d95a997fd9f9..f8904f73f57b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -292,9 +292,10 @@ bool cm_helper_translate_curve_to_hw_format(
seg_distr[7] = 4;
seg_distr[8] = 4;
seg_distr[9] = 4;
+   seg_distr[10] = 1;
 
region_start = -10;
-   region_end = 0;
+   region_end = 1;
}
 
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
-- 
2.20.1

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[PATCH AUTOSEL 4.19 09/50] drm/radeon: Fix EEH during kexec

[Sasha Levin]

From: KyleMahlkuch 

[ Upstream commit 6f7fe9a93e6c09bf988c5059403f5f88e17e21e6 ]

During kexec some adapters hit an EEH since they are not properly
shut down in the radeon_pci_shutdown() function. Adding
radeon_suspend_kms() fixes this issue.

Signed-off-by: KyleMahlkuch 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_drv.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index 2a7977a23b31c..25b5407c74b5a 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -364,11 +364,19 @@ radeon_pci_remove(struct pci_dev *pdev)
 static void
 radeon_pci_shutdown(struct pci_dev *pdev)
 {
+   struct drm_device *ddev = pci_get_drvdata(pdev);
+
/* if we are running in a VM, make sure the device
 * torn down properly on reboot/shutdown
 */
if (radeon_device_is_virtual())
radeon_pci_remove(pdev);
+
+   /* Some adapters need to be suspended before a
+   * shutdown occurs in order to prevent an error
+   * during kexec.
+   */
+   radeon_suspend_kms(ddev, true, true, false);
 }
 
 static int radeon_pmops_suspend(struct device *dev)
-- 
2.20.1

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[PATCH AUTOSEL 5.2 49/70] drm/amdgpu/si: fix ASIC tests

[Sasha Levin]

From: Jean Delvare 

[ Upstream commit 77efe48a729588527afb4d5811b9e0acb29f5e51 ]

Comparing adev->family with CHIP constants is not correct.
adev->family can only be compared with AMDGPU_FAMILY constants and
adev->asic_type is the struct member to compare with CHIP constants.
They are separate identification spaces.

Signed-off-by: Jean Delvare 
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: "David (ChunMing) Zhou" 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/si.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 9d8df68893b9d..1e34dfc143556 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1867,7 +1867,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
 
-   if ((adev->family != CHIP_OLAND) && (adev->family != 
CHIP_HAINAN)) {
+   if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type 
!= CHIP_HAINAN)) {
orig = data = 
si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
data &= ~PLL_RAMP_UP_TIME_0_MASK;
if (orig != data)
@@ -1916,14 +1916,14 @@ static void si_program_aspm(struct amdgpu_device *adev)
 
orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
-   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type 
== CHIP_HAINAN))
data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
 
orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
-   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type 
== CHIP_HAINAN))
data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
-- 
2.20.1

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[PATCH AUTOSEL 5.2 47/70] drm/amd/display: support spdif

[Sasha Levin]

From: Charlene Liu 

[ Upstream commit b5a41620bb88efb9fb31a4fa5e652e3d5bead7d4 ]

[Description]
port spdif fix to staging:
 spdif hardwired to afmt inst 1.
 spdif func pointer
 spdif resource allocation (reserve last audio endpoint for spdif only)

Signed-off-by: Charlene Liu 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c   | 17 -
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c  |  4 ++--
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index b459ce056b609..c404b5e930f04 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -261,12 +261,10 @@ bool resource_construct(
DC_ERR("DC: failed to create audio!\n");
return false;
}
-
if (!aud->funcs->endpoint_valid(aud)) {
aud->funcs->destroy();
break;
}
-
pool->audios[i] = aud;
pool->audio_count++;
}
@@ -1692,24 +1690,25 @@ static struct audio *find_first_free_audio(
const struct resource_pool *pool,
enum engine_id id)
 {
-   int i;
-   for (i = 0; i < pool->audio_count; i++) {
+   int i, available_audio_count;
+
+   available_audio_count = pool->audio_count;
+
+   for (i = 0; i < available_audio_count; i++) {
if ((res_ctx->is_audio_acquired[i] == false) && 
(res_ctx->is_stream_enc_acquired[i] == true)) {
/*we have enough audio endpoint, find the matching 
inst*/
if (id != i)
continue;
-
return pool->audios[i];
}
}
 
-/* use engine id to find free audio */
-   if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == 
false)) {
+   /* use engine id to find free audio */
+   if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == 
false)) {
return pool->audios[id];
}
-
/*not found the matching one, first come first serve*/
-   for (i = 0; i < pool->audio_count; i++) {
+   for (i = 0; i < available_audio_count; i++) {
if (res_ctx->is_audio_acquired[i] == false) {
return pool->audios[i];
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 7f6d724686f1a..abb559ce64085 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -611,6 +611,8 @@ void dce_aud_az_configure(
 
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
value);
+   DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, 
displayName %s: \n",
+   audio->inst, value, audio_info->display_name);
 
/*
*write the port ID:
@@ -922,7 +924,6 @@ static const struct audio_funcs funcs = {
.az_configure = dce_aud_az_configure,
.destroy = dce_aud_destroy,
 };
-
 void dce_aud_destroy(struct audio **audio)
 {
struct dce_audio *aud = DCE_AUD(*audio);
@@ -953,7 +954,6 @@ struct audio *dce_audio_create(
audio->regs = reg;
audio->shifts = shifts;
audio->masks = masks;
-
return >base;
 }
 
-- 
2.20.1

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[PATCH AUTOSEL 5.2 26/70] drm/amd/powerplay/smu7: enforce minimal VBITimeout (v2)

[Sasha Levin]

From: Ahzo 

[ Upstream commit f659bb6dae58c113805f92822e4c16ddd3156b79 ]

This fixes screen corruption/flickering on 75 Hz displays.

v2: make print statement debug only (Alex)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102646
Reviewed-by: Evan Quan 
Signed-off-by: Ahzo 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 048757e8f4949..d1919d343cce4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4064,6 +4064,11 @@ static int smu7_program_display_gap(struct pp_hwmgr 
*hwmgr)
 
data->frame_time_x2 = frame_time_in_us * 2 / 100;
 
+   if (data->frame_time_x2 < 280) {
+   pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", 
__func__, data->frame_time_x2);
+   data->frame_time_x2 = 280;
+   }
+
display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
 
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
ixCG_DISPLAY_GAP_CNTL2, display_gap2);
-- 
2.20.1

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[PATCH AUTOSEL 5.2 24/70] drm/amd/display: reprogram VM config when system resume

[Sasha Levin]

From: Lewis Huang 

[ Upstream commit e5382701c3520b3ed66169a6e4aa6ce5df8c56e0 ]

[Why]
The vm config will be clear to 0 when system enter S4. It will
cause hubbub didn't know how to fetch data when system resume.
The flip always pending because earliest_inuse_address and
request_address are different.

[How]
Reprogram VM config when system resume

Signed-off-by: Lewis Huang 
Reviewed-by: Jun Lei 
Acked-by: Eric Yang 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0a7adc2925e35..191f5757ded1f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2016,6 +2016,14 @@ void dc_set_power_state(
dc_resource_state_construct(dc, dc->current_state);
 
dc->hwss.init_hw(dc);
+
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+   if (dc->hwss.init_sys_ctx != NULL &&
+   dc->vm_pa_config.valid) {
+   dc->hwss.init_sys_ctx(dc->hwseq, dc, >vm_pa_config);
+   }
+#endif
+
break;
default:
ASSERT(dc->current_state->stream_count == 0);
-- 
2.20.1

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[PATCH AUTOSEL 5.2 22/70] drm/amd/display: fix issue where 252-255 values are clipped

[Sasha Levin]

From: Anthony Koo 

[ Upstream commit 1cbcfc975164f397b449efb17f59d81a703090db ]

[Why]
When endpoint is at the boundary of a region, such as at 2^0=1
we find that the last segment has a sharp slope and some points
are clipped at the top.

[How]
If end point is 1, which is exactly at the 2^0 region boundary, we
need to program an additional region beyond this point.

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 7469333a2c8a5..8166fdbacd732 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -357,9 +357,10 @@ bool cm_helper_translate_curve_to_hw_format(
seg_distr[7] = 4;
seg_distr[8] = 4;
seg_distr[9] = 4;
+   seg_distr[10] = 1;
 
region_start = -10;
-   region_end = 0;
+   region_end = 1;
}
 
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
-- 
2.20.1

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[PATCH AUTOSEL 5.2 15/70] gpu: drm: radeon: Fix a possible null-pointer dereference in radeon_connector_set_property()

[Sasha Levin]

From: Jia-Ju Bai 

[ Upstream commit f3eb9b8f67bc28783eddc142ad805ebdc53d6339 ]

In radeon_connector_set_property(), there is an if statement on line 743
to check whether connector->encoder is NULL:
if (connector->encoder)

When connector->encoder is NULL, it is used on line 755:
if (connector->encoder->crtc)

Thus, a possible null-pointer dereference may occur.

To fix this bug, connector->encoder is checked before being used.

This bug is found by a static analysis tool STCheck written by us.

Signed-off-by: Jia-Ju Bai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index de1745adb..c7f2e073a82fd 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -752,7 +752,7 @@ static int radeon_connector_set_property(struct 
drm_connector *connector, struct
 
radeon_encoder->output_csc = val;
 
-   if (connector->encoder->crtc) {
+   if (connector->encoder && connector->encoder->crtc) {
struct drm_crtc *crtc  = connector->encoder->crtc;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
-- 
2.20.1

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[PATCH AUTOSEL 5.2 23/70] drm/amd/display: Fix frames_to_insert math

[Sasha Levin]

From: Bayan Zabihiyan 

[ Upstream commit a463b263032f7c98c5912207db43be1aa34a6438 ]

[Why]
The math on deciding on how many
"frames to insert" sometimes sent us over the max refresh rate.
Also integer overflow can occur if we have high refresh rates.

[How]
Instead of clipping the  frame duration such that it doesn’t go below the min,
just remove a frame from the number of frames to insert. +
Use unsigned long long for intermediate calculations to prevent
integer overflow.

Signed-off-by: Bayan Zabihiyan 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../amd/display/modules/freesync/freesync.c   | 27 ---
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 19b1eaebe4840..000a9db9dad82 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -433,6 +433,12 @@ static void apply_below_the_range(struct core_freesync 
*core_freesync,
/* Either we've calculated the number of frames to insert,
 * or we need to insert min duration frames
 */
+   if (last_render_time_in_us / frames_to_insert <
+   in_out_vrr->min_duration_in_us){
+   frames_to_insert -= (frames_to_insert > 1) ?
+   1 : 0;
+   }
+
if (frames_to_insert > 0)
inserted_frame_duration_in_us = last_render_time_in_us /
frames_to_insert;
@@ -885,8 +891,8 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
struct core_freesync *core_freesync = NULL;
unsigned long long nominal_field_rate_in_uhz = 0;
unsigned int refresh_range = 0;
-   unsigned int min_refresh_in_uhz = 0;
-   unsigned int max_refresh_in_uhz = 0;
+   unsigned long long min_refresh_in_uhz = 0;
+   unsigned long long max_refresh_in_uhz = 0;
 
if (mod_freesync == NULL)
return;
@@ -913,7 +919,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
min_refresh_in_uhz = nominal_field_rate_in_uhz;
 
if (!vrr_settings_require_update(core_freesync,
-   in_config, min_refresh_in_uhz, max_refresh_in_uhz,
+   in_config, (unsigned int)min_refresh_in_uhz, (unsigned 
int)max_refresh_in_uhz,
in_out_vrr))
return;
 
@@ -929,15 +935,15 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
return;
 
} else {
-   in_out_vrr->min_refresh_in_uhz = min_refresh_in_uhz;
+   in_out_vrr->min_refresh_in_uhz = (unsigned 
int)min_refresh_in_uhz;
in_out_vrr->max_duration_in_us =
calc_duration_in_us_from_refresh_in_uhz(
-   min_refresh_in_uhz);
+   (unsigned 
int)min_refresh_in_uhz);
 
-   in_out_vrr->max_refresh_in_uhz = max_refresh_in_uhz;
+   in_out_vrr->max_refresh_in_uhz = (unsigned 
int)max_refresh_in_uhz;
in_out_vrr->min_duration_in_us =
calc_duration_in_us_from_refresh_in_uhz(
-   max_refresh_in_uhz);
+   (unsigned 
int)max_refresh_in_uhz);
 
refresh_range = in_out_vrr->max_refresh_in_uhz -
in_out_vrr->min_refresh_in_uhz;
@@ -948,17 +954,18 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
in_out_vrr->fixed.ramping_active = in_config->ramping;
 
in_out_vrr->btr.btr_enabled = in_config->btr;
+
if (in_out_vrr->max_refresh_in_uhz <
2 * in_out_vrr->min_refresh_in_uhz)
in_out_vrr->btr.btr_enabled = false;
+
in_out_vrr->btr.btr_active = false;
in_out_vrr->btr.inserted_duration_in_us = 0;
in_out_vrr->btr.frames_to_insert = 0;
in_out_vrr->btr.frame_counter = 0;
in_out_vrr->btr.mid_point_in_us =
-   in_out_vrr->min_duration_in_us +
-   (in_out_vrr->max_duration_in_us -
-   in_out_vrr->min_duration_in_us) / 2;
+   (in_out_vrr->min_duration_in_us +
+in_out_vrr->max_duration_in_us) / 2;
 
if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
in_out_vrr->adjust.v_total_min = stream->timing.v_total;
-- 
2.20.1

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[PATCH AUTOSEL 5.2 14/70] drm/radeon: Fix EEH during kexec

[Sasha Levin]

From: KyleMahlkuch 

[ Upstream commit 6f7fe9a93e6c09bf988c5059403f5f88e17e21e6 ]

During kexec some adapters hit an EEH since they are not properly
shut down in the radeon_pci_shutdown() function. Adding
radeon_suspend_kms() fixes this issue.

Signed-off-by: KyleMahlkuch 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_drv.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index 2e96c886392bd..60ee51edd7823 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -344,11 +344,19 @@ radeon_pci_remove(struct pci_dev *pdev)
 static void
 radeon_pci_shutdown(struct pci_dev *pdev)
 {
+   struct drm_device *ddev = pci_get_drvdata(pdev);
+
/* if we are running in a VM, make sure the device
 * torn down properly on reboot/shutdown
 */
if (radeon_device_is_virtual())
radeon_pci_remove(pdev);
+
+   /* Some adapters need to be suspended before a
+   * shutdown occurs in order to prevent an error
+   * during kexec.
+   */
+   radeon_suspend_kms(ddev, true, true, false);
 }
 
 static int radeon_pmops_suspend(struct device *dev)
-- 
2.20.1

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[PATCH AUTOSEL 5.2 07/70] drm/amd/display: add monitor patch to add T7 delay

[Sasha Levin]

From: Anthony Koo 

[ Upstream commit 88eac241a1fc500ce5274a09ddc4bd5fc2b5adb6 ]

[Why]
Specifically to one panel,
TCON is able to accept active video signal quickly, but
the Source Driver requires 2-3 frames of extra time.

It is a Panel issue since TCON needs to take care of
all Sink requirements including Source Driver. But in
this case it does not.

Customer is asking to add fixed T7 delay as panel
workaround.

[How]
Add monitor specific patch to add T7 delay

Signed-off-by: Anthony Koo 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 
 drivers/gpu/drm/amd/display/dc/dc_types.h  | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index b0dea759cd860..8aecf044e2ae8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -154,6 +154,10 @@ bool edp_receiver_ready_T7(struct dc_link *link)
break;
udelay(25); //MAx T7 is 50ms
} while (++tries < 300);
+
+   if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)
+   udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 
1000);
+
return result;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 6c2a3d9a4c2e7..283082666be51 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -202,6 +202,7 @@ struct dc_panel_patch {
unsigned int dppowerup_delay;
unsigned int extra_t12_ms;
unsigned int extra_delay_backlight_off;
+   unsigned int extra_t7_ms;
 };
 
 struct dc_edid_caps {
-- 
2.20.1

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[PATCH AUTOSEL 5.2 13/70] drm/amdgpu: Fix hard hang for S/G display BOs.

[Sasha Levin]

From: Andrey Grodzovsky 

[ Upstream commit e4c4073b0139d055d43a9568690fc560aab4fa5c ]

HW requires for caching to be unset for scanout BO
mappings when the BO placement is in GTT memory.
Usually the flag to unset is passed from user mode
but for FB mode this was missing.

v2:
Keep all BO placement logic in amdgpu_display_supported_domains

Suggested-by: Alex Deucher 
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Alex Deucher 
Tested-by: Shirish S 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 7 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index e476092188392..bf0c61baa05c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -137,14 +137,14 @@ static int amdgpufb_create_pinned_object(struct 
amdgpu_fbdev *rfbdev,
mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
  fb_tiled);
domain = amdgpu_display_supported_domains(adev);
-
height = ALIGN(mode_cmd->height, 8);
size = mode_cmd->pitches[0] * height;
aligned_size = ALIGN(size, PAGE_SIZE);
ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-  AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
-  AMDGPU_GEM_CREATE_VRAM_CLEARED,
+  AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+  AMDGPU_GEM_CREATE_VRAM_CLEARED|
+  AMDGPU_GEM_CREATE_CPU_GTT_USWC,
   ttm_bo_type_kernel, NULL, );
if (ret) {
pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
@@ -166,7 +166,6 @@ static int amdgpufb_create_pinned_object(struct 
amdgpu_fbdev *rfbdev,
dev_err(adev->dev, "FB failed to set tiling flags\n");
}
 
-
ret = amdgpu_bo_pin(abo, domain);
if (ret) {
amdgpu_bo_unreserve(abo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index d4fcf54754646..6fc77ac814d8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -746,7 +746,8 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
struct amdgpu_device *adev = dev->dev_private;
struct drm_gem_object *gobj;
uint32_t handle;
-   u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+   AMDGPU_GEM_CREATE_CPU_GTT_USWC;
u32 domain;
int r;
 
-- 
2.20.1

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[PATCH AUTOSEL 5.3 65/87] drm/amdgpu/si: fix ASIC tests

[Sasha Levin]

From: Jean Delvare 

[ Upstream commit 77efe48a729588527afb4d5811b9e0acb29f5e51 ]

Comparing adev->family with CHIP constants is not correct.
adev->family can only be compared with AMDGPU_FAMILY constants and
adev->asic_type is the struct member to compare with CHIP constants.
They are separate identification spaces.

Signed-off-by: Jean Delvare 
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: "David (ChunMing) Zhou" 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/si.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 4d74453f3cfbd..602397016b641 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1881,7 +1881,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
 
-   if ((adev->family != CHIP_OLAND) && (adev->family != 
CHIP_HAINAN)) {
+   if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type 
!= CHIP_HAINAN)) {
orig = data = 
si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
data &= ~PLL_RAMP_UP_TIME_0_MASK;
if (orig != data)
@@ -1930,14 +1930,14 @@ static void si_program_aspm(struct amdgpu_device *adev)
 
orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
-   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type 
== CHIP_HAINAN))
data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
 
orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
data &= ~LS2_EXIT_TIME_MASK;
-   if ((adev->family == CHIP_OLAND) || (adev->family == 
CHIP_HAINAN))
+   if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type 
== CHIP_HAINAN))
data |= LS2_EXIT_TIME(5);
if (orig != data)
si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
-- 
2.20.1

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[PATCH AUTOSEL 5.3 62/87] drm/amd/display: fix trigger not generated for freesync

[Sasha Levin]

From: Yogesh Mohan Marimuthu 

[ Upstream commit 1e7f100ce8c0640634b794604880d9204480c9f1 ]

[Why]
In newer hardware MANUAL_FLOW_CONTROL is not a trigger bit. Due to this
front porch is fixed and in these hardware freesync does not work.

[How]
Change the programming to generate a pulse so that the event will be
triggered, front porch will be cut short and freesync will work.

Signed-off-by: Yogesh Mohan Marimuthu 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index a546c2bc9129c..e365f2dd7f9a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -824,6 +824,9 @@ void optc1_program_manual_trigger(struct timing_generator 
*optc)
 
REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
MANUAL_FLOW_CONTROL, 1);
+
+   REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
+   MANUAL_FLOW_CONTROL, 0);
 }
 
 
-- 
2.20.1

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[PATCH AUTOSEL 5.3 61/87] drm/amd/display: fix MPO HUBP underflow with Scatter Gather

[Sasha Levin]

From: Zi Yu Liao 

[ Upstream commit 89cb5614736b9b5d3b833ca2237d10da6b4b0395 ]

[why]
With Scatter Gather enabled, HUBP underflows during MPO enabled video
playback. hubp_init has a register write that fixes this problem, but
the register is cleared when HUBP gets power gated.

[how]
Make a call to hubp_init during enable_plane, so that the fix can
be applied after HUBP powers back on again.

Signed-off-by: Zi Yu Liao 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index f8abe98a576be..8fdb53a44bfb3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1110,6 +1110,9 @@ void dcn20_enable_plane(
/* enable DCFCLK current DCHUB */

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
 
+   /* initialize HUBP on power up */
+   pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
+
/* make sure OPP_PIPE_CLOCK_EN = 1 */
pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
pipe_ctx->stream_res.opp,
-- 
2.20.1

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[PATCH AUTOSEL 5.3 60/87] drm/amd/powerpaly: fix navi series custom peak level value error

[Sasha Levin]

From: Kevin Wang 

[ Upstream commit 706feb26f890e1b8297b5d14975160de361edf4f ]

fix other navi asic set peak performance level error.
because the navi10_ppt.c will handle navi12 14 asic,
it will use navi10 peak value to set other asic, it is not correct.

after patch:
only navi10 use custom peak value, other asic will used default value.

Signed-off-by: Kevin Wang 
Reviewed-by: Evan Quan 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index b81c7e715dc94..9aaf2deff6e94 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1627,6 +1627,10 @@ static int navi10_set_peak_clock_by_device(struct 
smu_context *smu)
 static int navi10_set_performance_level(struct smu_context *smu, enum 
amd_dpm_forced_level level)
 {
int ret = 0;
+   struct amdgpu_device *adev = smu->adev;
+
+   if (adev->asic_type != CHIP_NAVI10)
+   return -EINVAL;
 
switch (level) {
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
-- 
2.20.1

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[PATCH AUTOSEL 5.3 59/87] drm/amd/display: support spdif

[Sasha Levin]

From: Charlene Liu 

[ Upstream commit b5a41620bb88efb9fb31a4fa5e652e3d5bead7d4 ]

[Description]
port spdif fix to staging:
 spdif hardwired to afmt inst 1.
 spdif func pointer
 spdif resource allocation (reserve last audio endpoint for spdif only)

Signed-off-by: Charlene Liu 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c   | 17 -
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c  |  4 ++--
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 2ceaab4fb5deb..68db60e4caf32 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -265,12 +265,10 @@ bool resource_construct(
DC_ERR("DC: failed to create audio!\n");
return false;
}
-
if (!aud->funcs->endpoint_valid(aud)) {
aud->funcs->destroy();
break;
}
-
pool->audios[i] = aud;
pool->audio_count++;
}
@@ -1659,24 +1657,25 @@ static struct audio *find_first_free_audio(
const struct resource_pool *pool,
enum engine_id id)
 {
-   int i;
-   for (i = 0; i < pool->audio_count; i++) {
+   int i, available_audio_count;
+
+   available_audio_count = pool->audio_count;
+
+   for (i = 0; i < available_audio_count; i++) {
if ((res_ctx->is_audio_acquired[i] == false) && 
(res_ctx->is_stream_enc_acquired[i] == true)) {
/*we have enough audio endpoint, find the matching 
inst*/
if (id != i)
continue;
-
return pool->audios[i];
}
}
 
-/* use engine id to find free audio */
-   if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == 
false)) {
+   /* use engine id to find free audio */
+   if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == 
false)) {
return pool->audios[id];
}
-
/*not found the matching one, first come first serve*/
-   for (i = 0; i < pool->audio_count; i++) {
+   for (i = 0; i < available_audio_count; i++) {
if (res_ctx->is_audio_acquired[i] == false) {
return pool->audios[i];
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 4a10a5d22c90b..5de9623bdf66b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -613,6 +613,8 @@ void dce_aud_az_configure(
 
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
value);
+   DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, 
displayName %s: \n",
+   audio->inst, value, audio_info->display_name);
 
/*
*write the port ID:
@@ -922,7 +924,6 @@ static const struct audio_funcs funcs = {
.az_configure = dce_aud_az_configure,
.destroy = dce_aud_destroy,
 };
-
 void dce_aud_destroy(struct audio **audio)
 {
struct dce_audio *aud = DCE_AUD(*audio);
@@ -953,7 +954,6 @@ struct audio *dce_audio_create(
audio->regs = reg;
audio->shifts = shifts;
audio->masks = masks;
-
return >base;
 }
 
-- 
2.20.1

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[PATCH AUTOSEL 5.3 53/87] drm/amdgpu/sdma5: fix number of sdma5 trap irq types for navi1x

[Sasha Levin]

From: Xiaojie Yuan 

[ Upstream commit 9e48495017342c5d445b25eedd86d6fd884a6496 ]

v2: set num_types based on num_instances

navi1x has 2 sdma engines but commit
"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
engines with following logic:

(enable irq for sdma0) * 1 time
(enable irq for sdma1) * 1 time
(disable irq for sdma1) * 6 times

as a result, after gpu reset, interrupt for sdma1 is lost.

Signed-off-by: Xiaojie Yuan 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 3747c3f1f0cc8..15c371fac469e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1583,7 +1583,8 @@ static const struct amdgpu_irq_src_funcs 
sdma_v5_0_illegal_inst_irq_funcs = {
 
 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-   adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
+   adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
+   adev->sdma.num_instances;
adev->sdma.trap_irq.funcs = _v5_0_trap_irq_funcs;
adev->sdma.illegal_inst_irq.funcs = _v5_0_illegal_inst_irq_funcs;
 }
-- 
2.20.1

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[PATCH AUTOSEL 5.3 21/87] drm/radeon: Fix EEH during kexec

[Sasha Levin]

From: KyleMahlkuch 

[ Upstream commit 6f7fe9a93e6c09bf988c5059403f5f88e17e21e6 ]

During kexec some adapters hit an EEH since they are not properly
shut down in the radeon_pci_shutdown() function. Adding
radeon_suspend_kms() fixes this issue.

Signed-off-by: KyleMahlkuch 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_drv.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index a6cbe11f79c61..15d7bebe17294 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -349,11 +349,19 @@ radeon_pci_remove(struct pci_dev *pdev)
 static void
 radeon_pci_shutdown(struct pci_dev *pdev)
 {
+   struct drm_device *ddev = pci_get_drvdata(pdev);
+
/* if we are running in a VM, make sure the device
 * torn down properly on reboot/shutdown
 */
if (radeon_device_is_virtual())
radeon_pci_remove(pdev);
+
+   /* Some adapters need to be suspended before a
+   * shutdown occurs in order to prevent an error
+   * during kexec.
+   */
+   radeon_suspend_kms(ddev, true, true, false);
 }
 
 static int radeon_pmops_suspend(struct device *dev)
-- 
2.20.1

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[PATCH AUTOSEL 5.3 22/87] gpu: drm: radeon: Fix a possible null-pointer dereference in radeon_connector_set_property()

[Sasha Levin]

From: Jia-Ju Bai 

[ Upstream commit f3eb9b8f67bc28783eddc142ad805ebdc53d6339 ]

In radeon_connector_set_property(), there is an if statement on line 743
to check whether connector->encoder is NULL:
if (connector->encoder)

When connector->encoder is NULL, it is used on line 755:
if (connector->encoder->crtc)

Thus, a possible null-pointer dereference may occur.

To fix this bug, connector->encoder is checked before being used.

This bug is found by a static analysis tool STCheck written by us.

Signed-off-by: Jia-Ju Bai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index c60d1a44d22a2..b684cd719612b 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -752,7 +752,7 @@ static int radeon_connector_set_property(struct 
drm_connector *connector, struct
 
radeon_encoder->output_csc = val;
 
-   if (connector->encoder->crtc) {
+   if (connector->encoder && connector->encoder->crtc) {
struct drm_crtc *crtc  = connector->encoder->crtc;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
-- 
2.20.1

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[PATCH AUTOSEL 5.3 30/87] drm/amd/display: fix issue where 252-255 values are clipped

[Sasha Levin]

From: Anthony Koo 

[ Upstream commit 1cbcfc975164f397b449efb17f59d81a703090db ]

[Why]
When endpoint is at the boundary of a region, such as at 2^0=1
we find that the last segment has a sharp slope and some points
are clipped at the top.

[How]
If end point is 1, which is exactly at the 2^0 region boundary, we
need to program an additional region beyond this point.

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 7469333a2c8a5..8166fdbacd732 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -357,9 +357,10 @@ bool cm_helper_translate_curve_to_hw_format(
seg_distr[7] = 4;
seg_distr[8] = 4;
seg_distr[9] = 4;
+   seg_distr[10] = 1;
 
region_start = -10;
-   region_end = 0;
+   region_end = 1;
}
 
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
-- 
2.20.1

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[PATCH AUTOSEL 5.3 35/87] drm/amd/powerplay/smu7: enforce minimal VBITimeout (v2)

[Sasha Levin]

From: Ahzo 

[ Upstream commit f659bb6dae58c113805f92822e4c16ddd3156b79 ]

This fixes screen corruption/flickering on 75 Hz displays.

v2: make print statement debug only (Alex)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102646
Reviewed-by: Evan Quan 
Signed-off-by: Ahzo 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 487aeee1cf8a5..3c1084de5d59f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4068,6 +4068,11 @@ static int smu7_program_display_gap(struct pp_hwmgr 
*hwmgr)
 
data->frame_time_x2 = frame_time_in_us * 2 / 100;
 
+   if (data->frame_time_x2 < 280) {
+   pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", 
__func__, data->frame_time_x2);
+   data->frame_time_x2 = 280;
+   }
+
display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
 
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
ixCG_DISPLAY_GAP_CNTL2, display_gap2);
-- 
2.20.1

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[PATCH AUTOSEL 5.3 33/87] drm/amd/display: Register VUPDATE_NO_LOCK interrupts for DCN2

[Sasha Levin]

From: Nicholas Kazlauskas 

[ Upstream commit e40837afb9b011757e17e9f71d97853ca574bcff ]

[Why]
These are needed to send back DRM vblank events in the case where VRR
is on. Without the interrupt enabled we're deferring the events into the
vblank queue and userspace is left waiting forever to get back the
events they need.

Found using igt@kms_vrr - the test fails immediately due to vblank
timeout.

[How]
Register them the same way we're handling it for DCN1.

This fixes igt@kms_vrr for DCN2.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: David Francis 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../display/dc/irq/dcn20/irq_service_dcn20.c  | 28 ---
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c 
b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
index 3cc0f2a1f77cc..5db29bf582d31 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
@@ -167,6 +167,11 @@ static const struct irq_source_info_funcs 
vblank_irq_info_funcs = {
.ack = NULL
 };
 
+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
+   .set = NULL,
+   .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -221,12 +226,15 @@ static const struct irq_source_info_funcs 
vblank_irq_info_funcs = {
.funcs = _irq_info_funcs\
}
 
-#define vupdate_int_entry(reg_num)\
+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
+ */
+#define vupdate_no_lock_int_entry(reg_num)\
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
IRQ_REG_ENTRY(OTG, reg_num,\
-   OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
-   OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
-   .funcs = _irq_info_funcs\
+   OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
+   OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
+   .funcs = _no_lock_irq_info_funcs\
}
 
 #define vblank_int_entry(reg_num)\
@@ -333,12 +341,12 @@ irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
dc_underflow_int_entry(6),
[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
-   vupdate_int_entry(0),
-   vupdate_int_entry(1),
-   vupdate_int_entry(2),
-   vupdate_int_entry(3),
-   vupdate_int_entry(4),
-   vupdate_int_entry(5),
+   vupdate_no_lock_int_entry(0),
+   vupdate_no_lock_int_entry(1),
+   vupdate_no_lock_int_entry(2),
+   vupdate_no_lock_int_entry(3),
+   vupdate_no_lock_int_entry(4),
+   vupdate_no_lock_int_entry(5),
vblank_int_entry(0),
vblank_int_entry(1),
vblank_int_entry(2),
-- 
2.20.1

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[PATCH AUTOSEL 5.3 32/87] drm/amd/display: reprogram VM config when system resume

[Sasha Levin]

From: Lewis Huang 

[ Upstream commit e5382701c3520b3ed66169a6e4aa6ce5df8c56e0 ]

[Why]
The vm config will be clear to 0 when system enter S4. It will
cause hubbub didn't know how to fetch data when system resume.
The flip always pending because earliest_inuse_address and
request_address are different.

[How]
Reprogram VM config when system resume

Signed-off-by: Lewis Huang 
Reviewed-by: Jun Lei 
Acked-by: Eric Yang 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index cbc480a333764..730f97ba8dbbe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2187,6 +2187,14 @@ void dc_set_power_state(
dc_resource_state_construct(dc, dc->current_state);
 
dc->hwss.init_hw(dc);
+
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+   if (dc->hwss.init_sys_ctx != NULL &&
+   dc->vm_pa_config.valid) {
+   dc->hwss.init_sys_ctx(dc->hwseq, dc, >vm_pa_config);
+   }
+#endif
+
break;
default:
ASSERT(dc->current_state->stream_count == 0);
-- 
2.20.1

[PATCH AUTOSEL 5.3 31/87] drm/amd/display: Fix frames_to_insert math

[Sasha Levin]

From: Bayan Zabihiyan 

[ Upstream commit a463b263032f7c98c5912207db43be1aa34a6438 ]

[Why]
The math on deciding on how many
"frames to insert" sometimes sent us over the max refresh rate.
Also integer overflow can occur if we have high refresh rates.

[How]
Instead of clipping the  frame duration such that it doesn’t go below the min,
just remove a frame from the number of frames to insert. +
Use unsigned long long for intermediate calculations to prevent
integer overflow.

Signed-off-by: Bayan Zabihiyan 
Reviewed-by: Aric Cyr 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../amd/display/modules/freesync/freesync.c   | 27 ---
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 7c20171a3b6da..a53666ff6cf89 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -435,6 +435,12 @@ static void apply_below_the_range(struct core_freesync 
*core_freesync,
/* Either we've calculated the number of frames to insert,
 * or we need to insert min duration frames
 */
+   if (last_render_time_in_us / frames_to_insert <
+   in_out_vrr->min_duration_in_us){
+   frames_to_insert -= (frames_to_insert > 1) ?
+   1 : 0;
+   }
+
if (frames_to_insert > 0)
inserted_frame_duration_in_us = last_render_time_in_us /
frames_to_insert;
@@ -887,8 +893,8 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
struct core_freesync *core_freesync = NULL;
unsigned long long nominal_field_rate_in_uhz = 0;
unsigned int refresh_range = 0;
-   unsigned int min_refresh_in_uhz = 0;
-   unsigned int max_refresh_in_uhz = 0;
+   unsigned long long min_refresh_in_uhz = 0;
+   unsigned long long max_refresh_in_uhz = 0;
 
if (mod_freesync == NULL)
return;
@@ -915,7 +921,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
min_refresh_in_uhz = nominal_field_rate_in_uhz;
 
if (!vrr_settings_require_update(core_freesync,
-   in_config, min_refresh_in_uhz, max_refresh_in_uhz,
+   in_config, (unsigned int)min_refresh_in_uhz, (unsigned 
int)max_refresh_in_uhz,
in_out_vrr))
return;
 
@@ -931,15 +937,15 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
return;
 
} else {
-   in_out_vrr->min_refresh_in_uhz = min_refresh_in_uhz;
+   in_out_vrr->min_refresh_in_uhz = (unsigned 
int)min_refresh_in_uhz;
in_out_vrr->max_duration_in_us =
calc_duration_in_us_from_refresh_in_uhz(
-   min_refresh_in_uhz);
+   (unsigned 
int)min_refresh_in_uhz);
 
-   in_out_vrr->max_refresh_in_uhz = max_refresh_in_uhz;
+   in_out_vrr->max_refresh_in_uhz = (unsigned 
int)max_refresh_in_uhz;
in_out_vrr->min_duration_in_us =
calc_duration_in_us_from_refresh_in_uhz(
-   max_refresh_in_uhz);
+   (unsigned 
int)max_refresh_in_uhz);
 
refresh_range = in_out_vrr->max_refresh_in_uhz -
in_out_vrr->min_refresh_in_uhz;
@@ -950,17 +956,18 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
in_out_vrr->fixed.ramping_active = in_config->ramping;
 
in_out_vrr->btr.btr_enabled = in_config->btr;
+
if (in_out_vrr->max_refresh_in_uhz <
2 * in_out_vrr->min_refresh_in_uhz)
in_out_vrr->btr.btr_enabled = false;
+
in_out_vrr->btr.btr_active = false;
in_out_vrr->btr.inserted_duration_in_us = 0;
in_out_vrr->btr.frames_to_insert = 0;
in_out_vrr->btr.frame_counter = 0;
in_out_vrr->btr.mid_point_in_us =
-   in_out_vrr->min_duration_in_us +
-   (in_out_vrr->max_duration_in_us -
-   in_out_vrr->min_duration_in_us) / 2;
+   (in_out_vrr->min_duration_in_us +
+in_out_vrr->max_duration_in_us) / 2;
 
if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
in_out_vrr->adjust.v_total_min = stream->timing.v_total;
-- 
2.20.1

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[PATCH AUTOSEL 5.3 20/87] drm/amd/display: Use proper enum conversion functions

[Sasha Levin]

From: Nathan Chancellor 

[ Upstream commit d196bbbc28fab82624f7686f8b0da8e8644b6e6a ]

clang warns:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:336:8:
warning: implicit conversion from enumeration type 'enum smu_clk_type'
to different enumeration type 'enum amd_pp_clock_type'
[-Wenum-conversion]
dc_to_smu_clock_type(clk_type),
^~~
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:421:14:
warning: implicit conversion from enumeration type 'enum
amd_pp_clock_type' to different enumeration type 'enum smu_clk_type'
[-Wenum-conversion]
dc_to_pp_clock_type(clk_type),
^~

There are functions to properly convert between all of these types, use
them so there are no longer any warnings.

Fixes: a43913ea50a5 ("drm/amd/powerplay: add function 
get_clock_by_type_with_latency for navi10")
Fixes: e5e4e22391c2 ("drm/amd/powerplay: add interface to get clock by type 
with latency for display (v2)")
Link: https://github.com/ClangBuiltLinux/linux/issues/586
Signed-off-by: Nathan Chancellor 
Reviewed-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 592fa499c9f86..9594c154664fc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -334,7 +334,7 @@ bool dm_pp_get_clock_levels_by_type(
}
} else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {
if (smu_get_clock_by_type(>smu,
- dc_to_smu_clock_type(clk_type),
+ dc_to_pp_clock_type(clk_type),
  _clks)) {
get_default_clock_levels(clk_type, dc_clks);
return true;
@@ -419,7 +419,7 @@ bool dm_pp_get_clock_levels_by_type_with_latency(
return false;
} else if (adev->smu.ppt_funcs && 
adev->smu.ppt_funcs->get_clock_by_type_with_latency) {
if (smu_get_clock_by_type_with_latency(>smu,
-  
dc_to_pp_clock_type(clk_type),
+  
dc_to_smu_clock_type(clk_type),
   _clks))
return false;
}
-- 
2.20.1

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[PATCH AUTOSEL 5.3 12/87] drm/amd/display: Copy GSL groups when committing a new context

[Sasha Levin]

From: Nicholas Kazlauskas 

[ Upstream commit 21ffcc94d5b3dc024fedac700f1e7f9dacf4ab4f ]

[Why]
DC configures the GSL group for the pipe when pipe_split is enabled
and we're switching flip types (buffered <-> immediate flip) on DCN2.

In order to record what GSL group the pipe is using DC stores it in
the pipe's stream_res. DM is not aware of this internal grouping, nor
is DC resource.

So when DM creates a dc_state context and passes it to DC the current
GSL group is lost - DM never knew about it in the first place.

After 3 immediate flips we run out of GSL groups and we're no longer
able to correctly perform *any* flip for multi-pipe scenarios.

[How]
The gsl_group needs to be copied to the new context.

DM has no insight into GSL grouping and could even potentially create
a brand new context without referencing current hardware state. So this
makes the most sense to have happen in DC.

There are two places where DC can apply a new context:
- dc_commit_state
- dc_commit_updates_for_stream

But what's shared between both of these is apply_ctx_for_surface.

This logic only matters for DCN2, so it can be placed in
dcn20_apply_ctx_for_surface. Before doing any locking (where the GSL
group is setup) we can copy over the GSL groups before committing the
new context.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Hersen Wu 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 2627e0a98a96a..f8abe98a576be 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1319,6 +1319,18 @@ static void dcn20_apply_ctx_for_surface(
if (!top_pipe_to_program)
return;
 
+   /* Carry over GSL groups in case the context is changing. */
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
+   struct pipe_ctx *old_pipe_ctx =
+   >current_state->res_ctx.pipe_ctx[i];
+
+   if (pipe_ctx->stream == stream &&
+   pipe_ctx->stream == old_pipe_ctx->stream)
+   pipe_ctx->stream_res.gsl_group =
+   old_pipe_ctx->stream_res.gsl_group;
+   }
+
tg = top_pipe_to_program->stream_res.tg;
 
interdependent_update = top_pipe_to_program->plane_state &&
-- 
2.20.1

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[PATCH AUTOSEL 5.3 08/87] drm/amd/display: add monitor patch to add T7 delay

[Sasha Levin]

From: Anthony Koo 

[ Upstream commit 88eac241a1fc500ce5274a09ddc4bd5fc2b5adb6 ]

[Why]
Specifically to one panel,
TCON is able to accept active video signal quickly, but
the Source Driver requires 2-3 frames of extra time.

It is a Panel issue since TCON needs to take care of
all Sink requirements including Source Driver. But in
this case it does not.

Customer is asking to add fixed T7 delay as panel
workaround.

[How]
Add monitor specific patch to add T7 delay

Signed-off-by: Anthony Koo 
Reviewed-by: Charlene Liu 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 
 drivers/gpu/drm/amd/display/dc/dc_types.h  | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 2d019e1f61352..a9135764e5806 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -160,6 +160,10 @@ bool edp_receiver_ready_T7(struct dc_link *link)
break;
udelay(25); //MAx T7 is 50ms
} while (++tries < 300);
+
+   if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)
+   udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 
1000);
+
return result;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 6eabb6491a3df..ce6d73d21ccae 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -202,6 +202,7 @@ struct dc_panel_patch {
unsigned int dppowerup_delay;
unsigned int extra_t12_ms;
unsigned int extra_delay_backlight_off;
+   unsigned int extra_t7_ms;
 };
 
 struct dc_edid_caps {
-- 
2.20.1

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[PATCH AUTOSEL 5.3 11/87] drm/amd/display: Clear FEC_READY shadow register if DPCD write fails

[Sasha Levin]

From: Nikola Cornij 

[ Upstream commit d68a74541735e030dea56f72746cd26d19986f41 ]

[why]
As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow
register should be cleared and the internal FEC stat should be set to
'not ready'. This is to make sure HW settings will be consistent with
FEC_READY state on the RX.

Signed-off-by: Nikola Cornij 
Reviewed-by: Joshua Aberback 
Acked-by: Chris Park 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2c7aaed907b91..0bf85a7a2cd31 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3033,6 +3033,8 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
link_enc->funcs->fec_set_ready(link_enc, true);
link->fec_state = dc_link_fec_ready;
} else {
+   
link->link_enc->funcs->fec_set_ready(link->link_enc, false);
+   link->fec_state = dc_link_fec_not_ready;
dm_error("dpcd write failed to set fec_ready");
}
} else if (link->fec_state == dc_link_fec_ready && !ready) {
-- 
2.20.1

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[PATCH AUTOSEL 5.3 10/87] drm/amd/display: fix not calling ppsmu to trigger PME

[Sasha Levin]

From: Su Sung Chung 

[ Upstream commit 18b401874aee10c80b5745c9b93280dae5a59809 ]

[why]
dcn20_clk_mgr_construct was not initializing pp_smu, and PME call gets
filtered out by the null check

[how]
initialize pp_smu dcn20_clk_mgr_construct

Signed-off-by: Su Sung Chung 
Reviewed-by: Eric Yang 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 50bfb5921de07..2ab0f97719b5a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -348,6 +348,8 @@ void dcn20_clk_mgr_construct(
 
clk_mgr->base.dprefclk_khz = 70; // 700 MHz planned if VCO is 3.85 
GHz, will be retrieved
 
+   clk_mgr->pp_smu = pp_smu;
+
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
clk_mgr->dentist_vco_freq_khz = 385;
-- 
2.20.1

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[PATCH AUTOSEL 5.3 09/87] drm/amd/display: Power-gate all DSCs at driver init time

[Sasha Levin]

From: Nikola Cornij 

[ Upstream commit 75c35000235f3662f2810e9a59b0c8eed045432e ]

[why]
DSC should be powered-on only on as-needed basis, i.e. if the mode
requires it

[how]
Loop over all the DSCs at driver init time and power-gate each

Signed-off-by: Nikola Cornij 
Reviewed-by: Nevenko Stupar 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index d810c8940129b..2627e0a98a96a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -585,6 +585,10 @@ static void dcn20_init_hw(struct dc *dc)
}
}
 
+   /* Power gate DSCs */
+   for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+   dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+
/* Blank pixel data with OPP DPG */
for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
struct timing_generator *tg = 
dc->res_pool->timing_generators[i];
-- 
2.20.1

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RE: [PATCH v2 3/4] device_cgroup: Export devcgroup_check_permission

[Kasiviswanathan, Harish]

Hi Tejun,

Can you please review this? You and Roman acked this patch before. It will be 
great if I can Reviewed-by, so that I can upstream this through Alex Deucher's 
amd-staging-drm-next and Dave Airlie's drm-next trees

Thanks,
Harish


-Original Message-
From: Kasiviswanathan, Harish  
Sent: Monday, September 16, 2019 2:06 PM
To: t...@kernel.org; Deucher, Alexander ; 
airl...@redhat.com
Cc: cgro...@vger.kernel.org; amd-gfx@lists.freedesktop.org; Kasiviswanathan, 
Harish 
Subject: [PATCH v2 3/4] device_cgroup: Export devcgroup_check_permission

For AMD compute (amdkfd) driver.

All AMD compute devices are exported via single device node /dev/kfd. As
a result devices cannot be controlled individually using device cgroup.

AMD compute devices will rely on its graphics counterpart that exposes
/dev/dri/renderN node for each device. For each task (based on its
cgroup), KFD driver will check if /dev/dri/renderN node is accessible
before exposing it.

Change-Id: I9ae283df550b2c122d67870b0cfa316bfbf3b614
Acked-by: Felix Kuehling 
Acked-by: Tejun Heo 
Acked-by: Roman Gushchin 
Signed-off-by: Harish Kasiviswanathan 
---
 include/linux/device_cgroup.h | 19 ---
 security/device_cgroup.c  | 15 +--
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/include/linux/device_cgroup.h b/include/linux/device_cgroup.h
index 8557efe096dc..fa35b52e0002 100644
--- a/include/linux/device_cgroup.h
+++ b/include/linux/device_cgroup.h
@@ -12,26 +12,15 @@
 #define DEVCG_DEV_ALL   4  /* this represents all devices */
 
 #ifdef CONFIG_CGROUP_DEVICE
-extern int __devcgroup_check_permission(short type, u32 major, u32 minor,
-   short access);
+int devcgroup_check_permission(short type, u32 major, u32 minor,
+  short access);
 #else
-static inline int __devcgroup_check_permission(short type, u32 major, u32 
minor,
-  short access)
+static inline int devcgroup_check_permission(short type, u32 major, u32 minor,
+short access)
 { return 0; }
 #endif
 
 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF)
-static inline int devcgroup_check_permission(short type, u32 major, u32 minor,
-short access)
-{
-   int rc = BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type, major, minor, access);
-
-   if (rc)
-   return -EPERM;
-
-   return __devcgroup_check_permission(type, major, minor, access);
-}
-
 static inline int devcgroup_inode_permission(struct inode *inode, int mask)
 {
short type, access = 0;
diff --git a/security/device_cgroup.c b/security/device_cgroup.c
index dc28914fa72e..04dd29bf7f06 100644
--- a/security/device_cgroup.c
+++ b/security/device_cgroup.c
@@ -801,8 +801,8 @@ struct cgroup_subsys devices_cgrp_subsys = {
  *
  * returns 0 on success, -EPERM case the operation is not permitted
  */
-int __devcgroup_check_permission(short type, u32 major, u32 minor,
-short access)
+static int __devcgroup_check_permission(short type, u32 major, u32 minor,
+   short access)
 {
struct dev_cgroup *dev_cgroup;
bool rc;
@@ -824,3 +824,14 @@ int __devcgroup_check_permission(short type, u32 major, 
u32 minor,
 
return 0;
 }
+
+int devcgroup_check_permission(short type, u32 major, u32 minor, short access)
+{
+   int rc = BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type, major, minor, access);
+
+   if (rc)
+   return -EPERM;
+
+   return __devcgroup_check_permission(type, major, minor, access);
+}
+EXPORT_SYMBOL(devcgroup_check_permission);
-- 
2.17.1

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Re: [PATCH] drm/amdgpu/display: include slab.h in dcn21_resource.c

[Harry Wentland]

On 2019-09-23 5:54 p.m., Alex Deucher wrote:
> On Mon, Sep 23, 2019 at 5:14 PM Harry Wentland  wrote:
>>
>> On 2019-09-23 4:58 p.m., Alex Deucher wrote:
>>> It's apparently needed in some configurations.
>>
>> Curious which config fails and what compiler errors we get... Sounds
>> like our includes are messed up somewhere.
> 
> Not sure exactly:
> https://lkml.org/lkml/2019/9/20/998
> 

Just noticed the other dcnXY_resource.c files have that as well.

Reviewed-by: Harry Wentland 

Harry

> Alex
> 
>>
>> Harry
>>
>>>
>>> Signed-off-by: Alex Deucher 
>>> ---
>>>  drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
>>> b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>>> index 3ca5139f1273..de182185fe1f 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>>> @@ -23,6 +23,8 @@
>>>   *
>>>   */
>>>
>>> +#include 
>>> +
>>>  #include "dm_services.h"
>>>  #include "dc.h"
>>>
>>>
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[PATCH v2 0/9] drm/print: add and use drm_debug_enabled()

[Jani Nikula]

Hi all, v2 of [1], a little refactoring around drm_debug access to
abstract it better. There shouldn't be any functional changes.

I'd appreciate acks for merging the lot via drm-misc. If there are any
objections to that, we'll need to postpone the last patch until
everything has been merged and converted in drm-next.

BR,
Jani.

Cc: Eric Engestrom 
Cc: Alex Deucher 
Cc: Christian König 
Cc: David (ChunMing) Zhou 
Cc: amd-gfx@lists.freedesktop.org
Cc: Ben Skeggs 
Cc: nouv...@lists.freedesktop.org
Cc: Rob Clark 
Cc: Sean Paul 
Cc: linux-arm-...@vger.kernel.org
Cc: freedr...@lists.freedesktop.org
Cc: Francisco Jerez 
Cc: Lucas Stach 
Cc: Russell King 
Cc: Christian Gmeiner 
Cc: etna...@lists.freedesktop.org


[1] cover.1568375189.git.jani.nikula@intel.com">http://mid.mail-archive.com/cover.1568375189.git.jani.nikula@intel.com

Jani Nikula (9):
  drm/print: move drm_debug variable to drm_print.[ch]
  drm/print: add drm_debug_enabled()
  drm/etnaviv: use drm_debug_enabled() to check for debug categories
  drm/i2c/sil164: use drm_debug_enabled() to check for debug categories
  drm/i915: use drm_debug_enabled() to check for debug categories
  drm/msm: use drm_debug_enabled() to check for debug categories
  drm/nouveau: use drm_debug_enabled() to check for debug categories
  drm/amdgpu: use drm_debug_enabled() to check for debug categories
  drm/print: rename drm_debug to __drm_debug to discourage use

 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c   |  4 ++--
 drivers/gpu/drm/drm_atomic_uapi.c|  2 +-
 drivers/gpu/drm/drm_dp_mst_topology.c|  6 ++---
 drivers/gpu/drm/drm_drv.c| 17 ---
 drivers/gpu/drm/drm_edid.c   |  2 +-
 drivers/gpu/drm/drm_edid_load.c  |  2 +-
 drivers/gpu/drm/drm_mipi_dbi.c   |  4 ++--
 drivers/gpu/drm/drm_print.c  | 23 ++--
 drivers/gpu/drm/drm_vblank.c |  6 ++---
 drivers/gpu/drm/etnaviv/etnaviv_buffer.c |  8 +++
 drivers/gpu/drm/i2c/sil164_drv.c |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c |  4 ++--
 drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
 drivers/gpu/drm/i915/i915_drv.c  |  2 +-
 drivers/gpu/drm/i915/i915_gem.h  |  2 +-
 drivers/gpu/drm/i915/i915_utils.c|  2 +-
 drivers/gpu/drm/i915/intel_pm.c  |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h  |  4 ++--
 drivers/gpu/drm/nouveau/dispnv50/disp.h  |  4 ++--
 drivers/gpu/drm/nouveau/nouveau_drv.h|  4 ++--
 include/drm/drm_drv.h|  2 --
 include/drm/drm_print.h  |  8 +++
 22 files changed, 60 insertions(+), 52 deletions(-)

-- 
2.20.1

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[PATCH v2 8/9] drm/amdgpu: use drm_debug_enabled() to check for debug categories

[Jani Nikula]

Allow better abstraction of the drm_debug global variable in the
future. No functional changes.

Cc: Alex Deucher 
Cc: Christian König 
Cc: David (ChunMing) Zhou 
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 
b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
index 4a5951036927..5f17bd4899e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
@@ -234,7 +234,7 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter 
*control,
DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
 (uint16_t)address, numbytes);
 
-   if (drm_debug & DRM_UT_DRIVER) {
+   if (drm_debug_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
   16, 1, data, numbytes, false);
}
@@ -388,7 +388,7 @@ static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter 
*control,
DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
  (uint16_t)address, bytes_received);
 
-   if (drm_debug & DRM_UT_DRIVER) {
+   if (drm_debug_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
   16, 1, data, bytes_received, false);
}
-- 
2.20.1

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Re: [PATCH] drm/amdgpu: fix an UMC hw arbitrator bug(v2)

[Alex Deucher]

On Tue, Sep 24, 2019 at 4:09 AM Monk Liu  wrote:
>
> issue:
> the UMC6 h/w bug is that when MCLK is doing the switch
> in the middle of a page access being preempted by high
> priority client (e.g. DISPLAY) then UMC and the mclk switch
> would stuck there due to deadlock
>
> how:
> fixed by disabling auto PreChg for UMC to avoid high
> priority client preempting other client's access on
> the same page, thus the deadlock could be avoided
>
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/Makefile |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  7 +++
>  drivers/gpu/drm/amd/amdgpu/umc_v6_0.c   | 37 
> +
>  drivers/gpu/drm/amd/amdgpu/umc_v6_0.h   | 31 +++
>  5 files changed, 77 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_0.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index c3cd271..508e93c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -84,7 +84,7 @@ amdgpu-y += \
>
>  # add UMC block
>  amdgpu-y += \
> -   umc_v6_1.o
> +   umc_v6_1.o umc_v6_0.o
>
>  # add IH block
>  amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> index 3ec36d9..17d3ec1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
> @@ -63,6 +63,7 @@ struct amdgpu_umc_funcs {
> void (*enable_umc_index_mode)(struct amdgpu_device *adev,
> uint32_t umc_instance);
> void (*disable_umc_index_mode)(struct amdgpu_device *adev);
> +   void (*patch_for_umc)(struct amdgpu_device *adev);

Maybe something like init_registers as the callback name to better
match other IP callbacks like nbio.  With that fixed:
Reviewed-by: Alex Deucher 

>  };
>
>  struct amdgpu_umc {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 6102dea..7047d8f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -51,6 +51,7 @@
>  #include "gfxhub_v1_1.h"
>  #include "mmhub_v9_4.h"
>  #include "umc_v6_1.h"
> +#include "umc_v6_0.h"
>
>  #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
>
> @@ -696,6 +697,9 @@ static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device 
> *adev)
>  static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
>  {
> switch (adev->asic_type) {
> +   case CHIP_VEGA10:
> +   adev->umc.funcs = _v6_0_funcs;
> +   break;
> case CHIP_VEGA20:
> adev->umc.max_ras_err_cnt_per_query = 
> UMC_V6_1_TOTAL_CHANNEL_NUM;
> adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
> @@ -1302,6 +1306,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device 
> *adev)
> for (i = 0; i < adev->num_vmhubs; ++i)
> gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
>
> +   if (adev->umc.funcs && adev->umc.funcs->patch_for_umc)
> +   adev->umc.funcs->patch_for_umc(adev);
> +
> DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
>  (unsigned)(adev->gmc.gart_size >> 20),
>  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
> diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
> new file mode 100644
> index 000..ab04420
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
> @@ -0,0 +1,37 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +#include "umc_v6_0.h"
> +#include "amdgpu.h"
> +
> +static void umc_v6_0_patch(struct 

Re: [PATCH] drm7amdgpu: once more fix amdgpu_bo_create_kernel_at

[Alex Deucher]

On Tue, Sep 24, 2019 at 7:56 AM Christian König
 wrote:
>
> When CPU access is needed we should tell that to
> amdgpu_bo_create_reserved() or otherwise the access is denied later on.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 12d2adcdf14e..f10b6175e20c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -369,7 +369,7 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
> size = ALIGN(size, PAGE_SIZE);
>
> r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
> - NULL, NULL);
> + NULL, cpu_addr);
> if (r)
> return r;
>
> @@ -377,12 +377,15 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device 
> *adev,
>  * Remove the original mem node and create a new one at the request
>  * position.
>  */
> +   if (cpu_addr)
> +   amdgpu_bo_kunmap(*bo_ptr);
> +
> +   ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
> +
> for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
> (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
> (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
> }
> -
> -   ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
> r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
>  &(*bo_ptr)->tbo.mem, );
> if (r)
> --
> 2.14.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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[PATCH] drm7amdgpu: once more fix amdgpu_bo_create_kernel_at

[Christian König]

When CPU access is needed we should tell that to
amdgpu_bo_create_reserved() or otherwise the access is denied later on.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 12d2adcdf14e..f10b6175e20c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -369,7 +369,7 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
size = ALIGN(size, PAGE_SIZE);
 
r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
- NULL, NULL);
+ NULL, cpu_addr);
if (r)
return r;
 
@@ -377,12 +377,15 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
 * Remove the original mem node and create a new one at the request
 * position.
 */
+   if (cpu_addr)
+   amdgpu_bo_kunmap(*bo_ptr);
+
+   ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
+
for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
(*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
(*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
}
-
-   ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
 &(*bo_ptr)->tbo.mem, );
if (r)
-- 
2.14.1

___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 14/14] drm/amdgpu: set TMZ bits in PTEs for secure bo (v2)

[Koenig, Christian]

Am 24.09.19 um 13:48 schrieb Huang, Ray:
>> -Original Message-
>> From: Koenig, Christian 
>> Sent: Thursday, September 12, 2019 7:49 PM
>> To: Huang, Ray 
>> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>> Deucher, Alexander ; Tuikov, Luben
>> ; Liu, Aaron 
>> Subject: Re: [PATCH 14/14] drm/amdgpu: set TMZ bits in PTEs for secure bo
>> (v2)
>>
>> Am 12.09.19 um 12:27 schrieb Huang, Ray:
>>> On Wed, Sep 11, 2019 at 08:13:19PM +0800, Koenig, Christian wrote:
 Am 11.09.19 um 13:50 schrieb Huang, Ray:
> From: Alex Deucher 
>
> If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED),
>> the
> TMZ bits of PTEs that belongs that bo should be set. Then psp is
> able to protect the pages of this bo to avoid the access from an "untrust"
>> domain such as CPU.
> v1: design and draft the skeletion of tmz bits setting on PTEs
> (Alex)
> v2: return failure once create secure bo on no-tmz platform  (Ray)
>
> Signed-off-by: Alex Deucher 
> Reviewed-by: Huang Rui 
> Signed-off-by: Huang Rui 
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  5 +
> 3 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 22eab74..5332104 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -222,7 +222,8 @@ int amdgpu_gem_create_ioctl(struct drm_device
>> *dev, void *data,
> AMDGPU_GEM_CREATE_CPU_GTT_USWC |
> AMDGPU_GEM_CREATE_VRAM_CLEARED |
> AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
> -   AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
> +   AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
> +   AMDGPU_GEM_CREATE_ENCRYPTED))
>
>   return -EINVAL;
>
> @@ -230,6 +231,11 @@ int amdgpu_gem_create_ioctl(struct
>> drm_device *dev, void *data,
>   if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
>   return -EINVAL;
>
> + if (!adev->tmz.enabled && (flags &
>> AMDGPU_GEM_CREATE_ENCRYPTED)) {
> + DRM_ERROR("Cannot allocate secure buffer while tmz is
>> disabled\n");
> + return -EINVAL;
> + }
> +
>   /* create a gem object to contain this object in */
>   if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
>   AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))
>> { @@ -251,6
> +257,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev,
>> void *data,
>   resv = vm->root.base.bo->tbo.resv;
>   }
>
> + if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
> + /* XXX: pad out alignment to meet TMZ requirements */
> + }
> +
>   r = amdgpu_gem_object_create(adev, size, args->in.alignment,
>(u32)(0x & 
> args->in.domains),
>flags, ttm_bo_type_device, resv, 
> );
>> diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> index 5a3c177..286e2e2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> @@ -224,6 +224,16 @@ static inline bool
>> amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
>   return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
> }
>
> +/**
> + * amdgpu_bo_encrypted - return whether the bo is encrypted  */
> +static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) {
> + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> +
> + return adev->tmz.enabled && (bo->flags &
> +AMDGPU_GEM_CREATE_ENCRYPTED);
 Checking the adev->tmz.enabled flags should be dropped here.

>>> That's fine. BO should be validated while it is created.
>>>
>>> But if the BO is created by vmid 0, is this checking needed?
>>>
> +}
> +
> bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
> void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo,
>> u32
> domain);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 3663655..8f00bb2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1434,6 +1434,8 @@ bool amdgpu_ttm_tt_is_readonly(struct
>> ttm_tt *ttm)
> uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct
>> ttm_mem_reg *mem)
> {
>   uint64_t flags = 0;
> + struct ttm_buffer_object *tbo = ttm_mem_reg_to_bo(mem);
> + struct 

RE: [PATCH 14/14] drm/amdgpu: set TMZ bits in PTEs for secure bo (v2)

[Huang, Ray]

> -Original Message-
> From: Koenig, Christian 
> Sent: Thursday, September 12, 2019 7:49 PM
> To: Huang, Ray 
> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> Deucher, Alexander ; Tuikov, Luben
> ; Liu, Aaron 
> Subject: Re: [PATCH 14/14] drm/amdgpu: set TMZ bits in PTEs for secure bo
> (v2)
> 
> Am 12.09.19 um 12:27 schrieb Huang, Ray:
> > On Wed, Sep 11, 2019 at 08:13:19PM +0800, Koenig, Christian wrote:
> >> Am 11.09.19 um 13:50 schrieb Huang, Ray:
> >>> From: Alex Deucher 
> >>>
> >>> If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED),
> the
> >>> TMZ bits of PTEs that belongs that bo should be set. Then psp is
> >>> able to protect the pages of this bo to avoid the access from an "untrust"
> domain such as CPU.
> >>>
> >>> v1: design and draft the skeletion of tmz bits setting on PTEs
> >>> (Alex)
> >>> v2: return failure once create secure bo on no-tmz platform  (Ray)
> >>>
> >>> Signed-off-by: Alex Deucher 
> >>> Reviewed-by: Huang Rui 
> >>> Signed-off-by: Huang Rui 
> >>> ---
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 12 +++-
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 ++
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  5 +
> >>>3 files changed, 26 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> index 22eab74..5332104 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> >>> @@ -222,7 +222,8 @@ int amdgpu_gem_create_ioctl(struct drm_device
> *dev, void *data,
> >>> AMDGPU_GEM_CREATE_CPU_GTT_USWC |
> >>> AMDGPU_GEM_CREATE_VRAM_CLEARED |
> >>> AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
> >>> -   AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
> >>> +   AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
> >>> +   AMDGPU_GEM_CREATE_ENCRYPTED))
> >>>
> >>>   return -EINVAL;
> >>>
> >>> @@ -230,6 +231,11 @@ int amdgpu_gem_create_ioctl(struct
> drm_device *dev, void *data,
> >>>   if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
> >>>   return -EINVAL;
> >>>
> >>> + if (!adev->tmz.enabled && (flags &
> AMDGPU_GEM_CREATE_ENCRYPTED)) {
> >>> + DRM_ERROR("Cannot allocate secure buffer while tmz is
> disabled\n");
> >>> + return -EINVAL;
> >>> + }
> >>> +
> >>>   /* create a gem object to contain this object in */
> >>>   if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
> >>>   AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))
> { @@ -251,6
> >>> +257,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev,
> void *data,
> >>>   resv = vm->root.base.bo->tbo.resv;
> >>>   }
> >>>
> >>> + if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
> >>> + /* XXX: pad out alignment to meet TMZ requirements */
> >>> + }
> >>> +
> >>>   r = amdgpu_gem_object_create(adev, size, args->in.alignment,
> >>>(u32)(0x & 
> >>> args->in.domains),
> >>>flags, ttm_bo_type_device, resv, 
> >>> );
> diff --git
> >>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> >>> index 5a3c177..286e2e2 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> >>> @@ -224,6 +224,16 @@ static inline bool
> amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
> >>>   return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
> >>>}
> >>>
> >>> +/**
> >>> + * amdgpu_bo_encrypted - return whether the bo is encrypted  */
> >>> +static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) {
> >>> + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> >>> +
> >>> + return adev->tmz.enabled && (bo->flags &
> >>> +AMDGPU_GEM_CREATE_ENCRYPTED);
> >> Checking the adev->tmz.enabled flags should be dropped here.
> >>
> > That's fine. BO should be validated while it is created.
> >
> > But if the BO is created by vmid 0, is this checking needed?
> >
> >>> +}
> >>> +
> >>>bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
> >>>void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo,
> u32
> >>> domain);
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >>> index 3663655..8f00bb2 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >>> @@ -1434,6 +1434,8 @@ bool amdgpu_ttm_tt_is_readonly(struct
> ttm_tt *ttm)
> >>>uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct
> ttm_mem_reg *mem)
> >>>{
> >>>   uint64_t flags = 0;
> >>> + struct ttm_buffer_object *tbo = ttm_mem_reg_to_bo(mem);
> >>> + struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
> >> That's a clear NAK. The 

Re: [PATCH 2/2] drm/amdgpu/atomfirmware: simplify the interface to get vram info

[Yuan, Xiaojie]

Series is Reviewed-by: Xiaojie Yuan 

BR,
Xiaojie


From: amd-gfx  on behalf of Alex Deucher 

Sent: Tuesday, September 24, 2019 4:35 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdgpu/atomfirmware: simplify the interface to get 
vram info

fetch both the vram type and width in one function call.  This
avoids having to parse the same data table twice to get the two
pieces of data.

Signed-off-by: Alex Deucher 
---
 .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 34 +
 .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h  |  4 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 21 +++-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 49 ++-
 4 files changed, 37 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 9feccec2ea5d..19913c39588b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -169,9 +169,8 @@ static int convert_atom_mem_type_to_vram_type(struct 
amdgpu_device *adev,
return vram_type;
 }

-static int
-amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
- int *vram_width, int *vram_type)
+int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ int *vram_width, int *vram_type)
 {
struct amdgpu_mode_info *mode_info = >mode_info;
int index, i = 0;
@@ -185,7 +184,6 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device 
*adev,
u32 mem_channel_width;
u32 module_id;

-
if (adev->flags & AMD_IS_APU)
index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
integratedsysteminfo);
@@ -261,34 +259,6 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device 
*adev,
return 0;
 }

-/*
- * Return vram width from integrated system info table, if available,
- * or 0 if not.
- */
-int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
-{
-   int vram_width = 0, vram_type = 0;
-   int r = amdgpu_atomfirmware_get_vram_info(adev, _width, 
_type);
-   if (r)
-   return 0;
-
-   return vram_width;
-}
-
-/*
- * Return vram type from either integrated system info table
- * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
- */
-int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
-{
-   int vram_width = 0, vram_type = 0;
-   int r = amdgpu_atomfirmware_get_vram_info(adev, _width, 
_type);
-   if (r)
-   return 0;
-
-   return vram_type;
-}
-
 /*
  * Return true if vbios enabled ecc by default, if umc info table is available
  * or false if ecc is not enabled or umc info table is not available
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
index 5ec6f92f353c..82819f03e444 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
@@ -29,8 +29,8 @@
 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device 
*adev);
 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
-int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
-int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev);
+int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ int *vram_width, int *vram_type);
 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 0a11d78d1fb2..cb3f61873baa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -539,17 +539,6 @@ static void gmc_v10_0_vram_gtt_location(struct 
amdgpu_device *adev,
  */
 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 {
-   int chansize, numchan;
-
-   if (!amdgpu_emu_mode)
-   adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
-   else {
-   /* hard code vram_width for emulation */
-   chansize = 128;
-   numchan = 1;
-   adev->gmc.vram_width = numchan * chansize;
-   }
-
/* Could aper size report 0 ? */
adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
@@ -635,7 +624,7 @@ static unsigned gmc_v10_0_get_vbios_fb_size(struct 
amdgpu_device *adev)

 static int gmc_v10_0_sw_init(void *handle)
 {
-   int r;
+   int r, vram_width = 

RE: [PATCH] drm/amdgpu/psp: silence response status warning

[Xu, Feifei]

Reviewed-by: Feifei Xu 

-Original Message-
From: amd-gfx  On Behalf Of S, Shirish
Sent: Tuesday, September 24, 2019 5:18 PM
To: Deucher, Alexander ; Koenig, Christian 
; Huang, Ray ; Zhang, Hawking 

Cc: amd-gfx@lists.freedesktop.org; S, Shirish 
Subject: [PATCH] drm/amdgpu/psp: silence response status warning

log the response status related error to the driver's debug log since  psp 
response status is not 0 even though there was no problem while the command was 
submitted.

This warning misleads, hence this change.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 76c59d5..37ffed5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -170,7 +170,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
if (ucode)
DRM_WARN("failed to load ucode id (%d) ",
  ucode->ucode_id);
-   DRM_WARN("psp command (0x%X) failed and response status is 
(0x%X)\n",
+   DRM_DEBUG_DRIVER("psp command (0x%X) failed and response status 
is 
+(0x%X)\n",
 psp->cmd_buf_mem->cmd_id,
 psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
if (!timeout) {
--
2.7.4

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[PATCH] drm/amdgpu/psp: silence response status warning

[S, Shirish]

log the response status related error to the driver's
debug log since  psp response status is not 0 even though
there was no problem while the command was submitted.

This warning misleads, hence this change.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 76c59d5..37ffed5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -170,7 +170,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
if (ucode)
DRM_WARN("failed to load ucode id (%d) ",
  ucode->ucode_id);
-   DRM_WARN("psp command (0x%X) failed and response status is 
(0x%X)\n",
+   DRM_DEBUG_DRIVER("psp command (0x%X) failed and response status 
is (0x%X)\n",
 psp->cmd_buf_mem->cmd_id,
 psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
if (!timeout) {
-- 
2.7.4

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[PATCH] drm/amdgpu: fix an UMC hw arbitrator bug(v2)

[Monk Liu]

issue:
the UMC6 h/w bug is that when MCLK is doing the switch
in the middle of a page access being preempted by high
priority client (e.g. DISPLAY) then UMC and the mclk switch
would stuck there due to deadlock

how:
fixed by disabling auto PreChg for UMC to avoid high
priority client preempting other client's access on
the same page, thus the deadlock could be avoided

Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/Makefile |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  7 +++
 drivers/gpu/drm/amd/amdgpu/umc_v6_0.c   | 37 +
 drivers/gpu/drm/amd/amdgpu/umc_v6_0.h   | 31 +++
 5 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c3cd271..508e93c 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -84,7 +84,7 @@ amdgpu-y += \
 
 # add UMC block
 amdgpu-y += \
-   umc_v6_1.o
+   umc_v6_1.o umc_v6_0.o
 
 # add IH block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index 3ec36d9..17d3ec1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -63,6 +63,7 @@ struct amdgpu_umc_funcs {
void (*enable_umc_index_mode)(struct amdgpu_device *adev,
uint32_t umc_instance);
void (*disable_umc_index_mode)(struct amdgpu_device *adev);
+   void (*patch_for_umc)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_umc {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 6102dea..7047d8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -51,6 +51,7 @@
 #include "gfxhub_v1_1.h"
 #include "mmhub_v9_4.h"
 #include "umc_v6_1.h"
+#include "umc_v6_0.h"
 
 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
 
@@ -696,6 +697,9 @@ static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device 
*adev)
 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
 {
switch (adev->asic_type) {
+   case CHIP_VEGA10:
+   adev->umc.funcs = _v6_0_funcs;
+   break;
case CHIP_VEGA20:
adev->umc.max_ras_err_cnt_per_query = 
UMC_V6_1_TOTAL_CHANNEL_NUM;
adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
@@ -1302,6 +1306,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device 
*adev)
for (i = 0; i < adev->num_vmhubs; ++i)
gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
 
+   if (adev->umc.funcs && adev->umc.funcs->patch_for_umc)
+   adev->umc.funcs->patch_for_umc(adev);
+
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 (unsigned)(adev->gmc.gart_size >> 20),
 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
new file mode 100644
index 000..ab04420
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "umc_v6_0.h"
+#include "amdgpu.h"
+
+static void umc_v6_0_patch(struct amdgpu_device *adev)
+{
+   unsigned i,j;
+
+   for (i = 0; i < 4; i++)
+   for (j = 0; j < 4; j++)
+   WREG32((i*0x10 + 0x5010c + j*0x2000)/4, 0x1002);
+}
+
+const struct amdgpu_umc_funcs umc_v6_0_funcs = {
+   .patch_for_umc = umc_v6_0_patch,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_0.h 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.h
new file mode 100644
index 000..109f1a5

RE: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' workaround for navi12

[Quan, Evan]

Sure. Free to add my RB with that.

-Original Message-
From: Yuan, Xiaojie  
Sent: Tuesday, September 24, 2019 3:20 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xiao, Jack ; 
Yin, Tianci (Rico) 
Subject: Re: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' 
workaround for navi12

Thanks Evan. Since we currently has only once place to check 'is navi series', 
I'd prefer not to put into a macro until we have another place to check that. 
Does the change below looks good to you?

-   adev->asic_type > CHIP_NAVI14 ||
+   !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12) 
||

BR,
Xiaojie


From: Quan, Evan 
Sent: Tuesday, September 24, 2019 11:18 AM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking; Xiao, Jack; Yin, Tianci (Rico)
Subject: RE: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' 
workaround for navi12

A small nitpick: if this workaround is needed for all NAVi ASICs, can we make a 
macro for this?
e.g.  #define ASIC_IS_NAVI_SERIES(adev)   (adev->asic_type >= 
CHIP_NAVI10 && adev->asic_type <= NAVI12)

Then we can use
if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
-   adev->asic_type > CHIP_NAVI14 ||
+   !ASIC_IS_NAVI_SERIES(adev) ||
adev->in_gpu_reset) {

-Original Message-
From: Yuan, Xiaojie 
Sent: Tuesday, September 24, 2019 11:01 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xiao, Jack ; 
Yin, Tianci (Rico) ; Quan, Evan ; Yuan, 
Xiaojie 
Subject: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' 
workaround for navi12

when gfxoff is enabled, sdma hangs while entering desktop without this 
workaround

Signed-off-by: Xiaojie Yuan 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index ed1c3b883f6a..0304ca8fe723 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -291,7 +291,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,

if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
-   adev->asic_type > CHIP_NAVI14 ||
+   adev->asic_type > CHIP_NAVI12 ||
adev->in_gpu_reset) {
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
mutex_unlock(>mman.gtt_window_lock);
--
2.20.1

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Re: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' workaround for navi12

[Yuan, Xiaojie]

Thanks Evan. Since we currently has only once place to check 'is navi series', 
I'd prefer not to put into a macro until we have another place to check that. 
Does the change below looks good to you?

-   adev->asic_type > CHIP_NAVI14 ||
+   !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12) 
||

BR,
Xiaojie


From: Quan, Evan 
Sent: Tuesday, September 24, 2019 11:18 AM
To: Yuan, Xiaojie; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking; Xiao, Jack; Yin, Tianci (Rico)
Subject: RE: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' 
workaround for navi12

A small nitpick: if this workaround is needed for all NAVi ASICs, can we make a 
macro for this?
e.g.  #define ASIC_IS_NAVI_SERIES(adev)   (adev->asic_type >= 
CHIP_NAVI10 && adev->asic_type <= NAVI12)

Then we can use
if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
-   adev->asic_type > CHIP_NAVI14 ||
+   !ASIC_IS_NAVI_SERIES(adev) ||
adev->in_gpu_reset) {

-Original Message-
From: Yuan, Xiaojie 
Sent: Tuesday, September 24, 2019 11:01 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xiao, Jack ; 
Yin, Tianci (Rico) ; Quan, Evan ; Yuan, 
Xiaojie 
Subject: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' 
workaround for navi12

when gfxoff is enabled, sdma hangs while entering desktop without this 
workaround

Signed-off-by: Xiaojie Yuan 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index ed1c3b883f6a..0304ca8fe723 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -291,7 +291,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,

if (!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready ||
-   adev->asic_type > CHIP_NAVI14 ||
+   adev->asic_type > CHIP_NAVI12 ||
adev->in_gpu_reset) {
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
mutex_unlock(>mman.gtt_window_lock);
--
2.20.1

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RE: [PATCH 4/5] drm/amd/powerplay: add the interfaces for getting and setting profiling dpm clock level

[Liang, Prike]

From: Wang, Kevin(Yang) 
Sent: Monday, September 23, 2019 5:29 PM
To: Liang, Prike ; amd-gfx@lists.freedesktop.org
Cc: arron@amd.com; Huang, Ray ; Quan, Evan 
; Feng, Kenneth 
Subject: Re: [PATCH 4/5] drm/amd/powerplay: add the interfaces for getting and 
setting profiling dpm clock level

comment inline.

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Liang, Prike mailto:prike.li...@amd.com>>
Sent: Monday, September 23, 2019 4:43 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: arron@amd.com 
mailto:arron@amd.com>>; Huang, Ray 
mailto:ray.hu...@amd.com>>; Liang, Prike 
mailto:prike.li...@amd.com>>; Quan, Evan 
mailto:evan.q...@amd.com>>; Feng, Kenneth 
mailto:kenneth.f...@amd.com>>
Subject: [PATCH 4/5] drm/amd/powerplay: add the interfaces for getting and 
setting profiling dpm clock level

implement get_profiling_clk_mask and force_clk_levels for forcing dpm clk to 
limit value.

Signed-off-by: Prike Liang mailto:prike.li...@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 83 ++
 1 file changed, 83 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index f87aa56..c6aae1c 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -392,6 +392,87 @@ static int renoir_get_workload_type(struct smu_context 
*smu, uint32_t profile)
 return pplib_workload;
 }

+static int renoir_get_profiling_clk_mask(struct smu_context *smu,
+enum amd_dpm_forced_level level,
+uint32_t *sclk_mask,
+uint32_t *mclk_mask,
+uint32_t *soc_mask)
+{
+
+   if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
+   if (sclk_mask)
+   *sclk_mask = 0;
+   } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
+   if (mclk_mask)
+   *mclk_mask = 0;
+   } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+   if(sclk_mask)
+   /* The sclk as gfxclk and has three level about 
max/min/current */
+   *sclk_mask = 3 - 1;
[kevin]:
you should return the max level not current level.
[Prike] Yeah, the clause will return max dpm level index.
+
+   if(mclk_mask)
+   *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
+
+   if(soc_mask)
+   *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
+   }
+
+   return 0;
+}
+
+static int renoir_force_clk_levels(struct smu_context *smu,
+  enum smu_clk_type clk_type, uint32_t mask)
+{
+
+   int ret = 0 ;
+   uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq 
= 0;
+   DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+
+   soft_min_level = mask ? (ffs(mask) - 1) : 0;
+   soft_max_level = mask ? (fls(mask) - 1) : 0;
+
+   switch (clk_type) {
+   case SMU_GFXCLK:
+   case SMU_SCLK:
+   ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, _freq, 
_freq);
+   if (ret)
+   return ret;
+   ret = smu_send_smc_msg_with_param(smu, 
SMU_MSG_SetSoftMaxGfxClk, max_freq);
+   if (ret)
+   return ret;
+   ret = smu_send_smc_msg_with_param(smu, 
SMU_MSG_SetHardMinGfxClk, min_freq);
+   if (ret)
+   return ret;
+   break;
+   case SMU_SOCCLK:
+   GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq);
+   GET_DPM_CUR_FREQ(clk_table, clk_type, soft_max_level, max_freq);
+   ret = smu_send_smc_msg_with_param(smu, 
SMU_MSG_SetSoftMaxSocclkByFreq, max_freq);
+   if (ret)
+   return ret;
+   ret = smu_send_smc_msg_with_param(smu, 
SMU_MSG_SetHardMinSocclkByFreq, min_freq);
+   if (ret)
+   return ret;
+   break;
+   case SMU_MCLK:
+   case SMU_FCLK:
+   GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq);
+   GET_DPM_CUR_FREQ(clk_table, clk_type, soft_max_level, max_freq);
+   ret = smu_send_smc_msg_with_param(smu, 
SMU_MSG_SetSoftMaxFclkByFreq, max_freq);
+   if (ret)
+   return ret;
+   ret = smu_send_smc_msg_with_param(smu, 
SMU_MSG_SetHardMinFclkByFreq, min_freq);
+   if (ret)
+   return ret;
+
[kevin]:
after remove this blank line,
Reviewed-by: Kevin Wang mailto:kevin1.w...@amd.com>>
+   break;
+   default:
+   break;
+   }
+
+   return ret;