Re: [03/14] drm/amd/display: Add execution and transition states for HDCP2.2
On Thu, Nov 07, 2019 at 10:56:17AM -0500, Bhawanpreet Lakha wrote:
> The module works like a state machine
>
> +-+
> --> | Execution.c | --
> | +-+ |
> | V
> ++ ++ +--+
> | DM |->| Hdcp.c | < | Transition.c |
> ++<-++ +--+
>
> This patch adds the execution and transition files for 2.2
>
> Extension to "40a702d427 drm/amd/display: Add HDCP module" for 2.2
>
> Signed-off-by: Bhawanpreet Lakha
The version of this patch in linux-next, 51466b3fd272 ("drm/amd/display:
Add execution and transition states for HDCP2.2") causes the following
error on arm32:
arm-linux-gnueabi-ld:
drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.o: in function
`locality_check':
hdcp2_execution.c:(.text+0xd2c): undefined reference to `__bad_udelay'
arm-linux-gnueabi-ld:
drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.o: in function
`poll_l_prime_available':
hdcp2_execution.c:(.text+0xe64): undefined reference to `__bad_udelay'
There is a limit of 2000us delays on arm:
https://elixir.bootlin.com/linux/v5.3.12/source/arch/arm/include/asm/delay.h#L60
If this function doesn't run in an atomic context, I assume msleep
should work.
Cheers,
Nathan
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[PATCH] drm/amd/powerplay: remove redundant assignment to variables HiSidd and LoSidd
From: Colin Ian King
The variables HiSidd and LoSidd are being initialized with values that
are never read and are being updated a little later with a new value.
The initialization is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 15590fd86ef4..868e2d5f6e62 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -653,8 +653,8 @@ static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct
pp_hwmgr *hwmgr)
static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
{
struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
- uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
- uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
+ uint16_t HiSidd;
+ uint16_t LoSidd;
struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
--
2.24.0
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[PATCH] drm/amd/display: Reduce HDMI pixel encoding if max clock is exceeded
For high-res (8K) or HFR (4K120) displays, using uncompressed pixel
formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the
"interesting" modes would be disabled, leaving only low-res or low
framerate modes.
This change lowers the pixel encoding to 4:2:2 or 4:2:0 if the max TMDS
clock is exceeded. Verified that 8K30 and 4K120 are now available and
working with a Samsung Q900R over an HDMI 2.0b link from a Radeon 5700.
Signed-off-by: Thomas Anderson
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++-
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4139f129eafb..a507a6f04c82 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3269,13 +3269,15 @@ static void reduce_mode_colour_depth(struct
dc_crtc_timing *timing_out)
timing_out->display_color_depth--;
}
-static void adjust_colour_depth_from_display_info(struct dc_crtc_timing
*timing_out,
- const struct drm_display_info
*info)
+static void adjust_timing_from_display_info(
+ struct dc_crtc_timing *timing_out,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode_in)
{
int normalized_clk;
- if (timing_out->display_color_depth <= COLOR_DEPTH_888)
+ if (timing_out->display_color_depth < COLOR_DEPTH_888)
return;
- do {
+ while (timing_out->display_color_depth > COLOR_DEPTH_888) {
normalized_clk = timing_out->pix_clk_100hz / 10;
/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
@@ -3297,9 +3299,23 @@ static void adjust_colour_depth_from_display_info(struct
dc_crtc_timing *timing_
if (normalized_clk <= info->max_tmds_clock)
return;
reduce_mode_colour_depth(timing_out);
+ }
- } while (timing_out->display_color_depth > COLOR_DEPTH_888);
-
+ /* The color depth is 888 and cannot be reduced any further, but the
+* clock would still exceed the max tmds clock. Try reducing the pixel
+* encoding next.
+*/
+ if (timing_out->pixel_encoding == PIXEL_ENCODING_RGB ||
+ timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
+ /* YCBCR422 is always supported. */
+ timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR422;
+ normalized_clk = (timing_out->pix_clk_100hz * 3) / 40;
+ if (normalized_clk <= info->max_tmds_clock)
+ return;
+ }
+ /* YCBCR420 may only be supported on specific modes. */
+ if (drm_mode_is_420_also(info, mode_in))
+ timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
}
static void fill_stream_properties_from_drm_display_mode(
@@ -3366,7 +3382,7 @@ static void fill_stream_properties_from_drm_display_mode(
stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
- adjust_colour_depth_from_display_info(timing_out, info);
+ adjust_timing_from_display_info(timing_out, info, mode_in);
}
static void fill_audio_info(struct audio_info *audio_info,
--
2.24.0.432.g9d3f5f5b63-goog
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[PATCH] drm/radeon: remove redundant assignment to variable ret
From: Colin Ian King
The variable ret is being initialized with a value that is never
read and it is being updated later with a new value. The
initialization is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/radeon/si_dpm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 8148a7883de4..346315b3eebe 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -5899,7 +5899,7 @@ static int
si_patch_single_dependency_table_based_on_leakage(struct radeon_devic
static int si_patch_dependency_tables_based_on_leakage(struct radeon_device
*rdev)
{
- int ret = 0;
+ int ret;
ret = si_patch_single_dependency_table_based_on_leakage(rdev,
>pm.dpm.dyn_state.vddc_dependency_on_sclk);
--
2.24.0
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Re: [PATCH 0/4] add runtime pm support for AMD display audio
On Fri, 22 Nov 2019 22:43:49 +0100, Alex Deucher wrote: > > These patches were originally part of a larger set of patches > to enabled runtime pm support on the GPU side[1]. However, the > patches are useful on their own there are really no dependencies, > other than the fact that you need both for runtime pm to kick in > on the GPU side. The GPU side will be landing for 5.6; I'd like > to land the audio side as well. Do you mean that these can go into 5.5-rc1, or they need waiting until 5.5-rc1 release? I guess these won't break things even without the runtime PM support in GPU side, as the ELD notification is done via audio component, so I'm fine to apply them at any time. thanks, Takashi > > Thanks, > > Alex > > [1]: https://patchwork.freedesktop.org/series/67885/ > > Alex Deucher (4): > ALSA: hda/hdmi - fix vgaswitcheroo detection for AMD > ALSA: hda/hdmi - Add new pci ids for AMD GPU display audio > ALSA: hda/hdmi - enable runtime pm for newer AMD display audio > ALSA: hda/hdmi - enable automatic runtime pm for AMD HDMI codecs by > default > > sound/pci/hda/hda_intel.c | 80 +++--- > sound/pci/hda/patch_hdmi.c | 1 + > 2 files changed, 76 insertions(+), 5 deletions(-) > > -- > 2.23.0 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
