Re: KASAN: use-after-free Read in vgem_gem_dumb_create

[Dan Carpenter]

I don't totally understand the stack trace but I do see a double free
bug.

drivers/gpu/drm/vgem/vgem_drv.c
   186  static struct drm_gem_object *vgem_gem_create(struct drm_device *dev,
   187struct drm_file *file,
   188unsigned int *handle,
   189unsigned long size)
   190  {
   191  struct drm_vgem_gem_object *obj;
   192  int ret;
   193  
   194  obj = __vgem_gem_create(dev, size);

obj->base.handle_count is zero.

   195  if (IS_ERR(obj))
   196  return ERR_CAST(obj);
   197  
   198  ret = drm_gem_handle_create(file, >base, handle);

We bump it +1 and then the error handling calls
drm_gem_object_handle_put_unlocked(obj);
which calls drm_gem_object_put_unlocked(); which frees obj.


   199  drm_gem_object_put_unlocked(>base);

So this is a double free.  Could someone check my thinking and send
a patch?  It's just a one liner.  Otherwise I can send it on Monday.

   200  if (ret)
   201  return ERR_PTR(ret);
   202  
   203  return >base;
   204  }

regards,
dan carpenter
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RE: [Patch v2 3/4] drm/amdkfd: refactor runtime pm for baco

[Zeng, Oak]

[AMD Official Use Only - Internal Distribution Only]

Patch 1,2,3 work for me. See one comment inline, otherwise Reviewed-by: Oak 
Zeng 

Regards,
Oak

-Original Message-
From: amd-gfx  On Behalf Of Rajneesh 
Bhardwaj
Sent: Friday, January 31, 2020 10:37 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kuehling, Felix 
; Bhardwaj, Rajneesh 
Subject: [Patch v2 3/4] drm/amdkfd: refactor runtime pm for baco

So far the kfd driver implemented same routines for runtime and system wide 
suspend and resume (s2idle or mem). During system wide suspend the kfd aquires 
an atomic lock that prevents any more user processes to create queues and 
interact with kfd driver and amd gpu. This mechanism created problem when 
amdgpu device is runtime suspended with BACO enabled. Any application that 
relies on kfd driver fails to load because the driver reports a locked kfd 
device since gpu is runtime suspended.

However, in an ideal case, when gpu is runtime  suspended the kfd driver should 
be able to:

 - auto resume amdgpu driver whenever a client requests compute service
 - prevent runtime suspend for amdgpu  while kfd is in use

This change refactors the amdgpu and amdkfd drivers to support BACO and runtime 
power management.

Signed-off-by: Rajneesh Bhardwaj 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 12 +++---  
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |  8 ++--  
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 +-
 drivers/gpu/drm/amd/amdkfd/kfd_device.c| 29 +--
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_process.c   | 43 --
 6 files changed, 70 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 8609287620ea..314c4a2a0354 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -178,18 +178,18 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);  }
 
-void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
+void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
 {
if (adev->kfd.dev)
-   kgd2kfd_suspend(adev->kfd.dev);
+   kgd2kfd_suspend(adev->kfd.dev, run_pm);
 }
 
-int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
+int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
 {
int r = 0;
 
if (adev->kfd.dev)
-   r = kgd2kfd_resume(adev->kfd.dev);
+   r = kgd2kfd_resume(adev->kfd.dev, run_pm);
 
return r;
 }
@@ -713,11 +713,11 @@ void kgd2kfd_exit(void)  {  }
 
-void kgd2kfd_suspend(struct kfd_dev *kfd)
+void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
 {
 }
 
-int kgd2kfd_resume(struct kfd_dev *kfd)
+int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
 {
return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 47b0f2957d1f..9e8db702d878 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -122,8 +122,8 @@ struct amdkfd_process_info {  int amdgpu_amdkfd_init(void); 
 void amdgpu_amdkfd_fini(void);
 
-void amdgpu_amdkfd_suspend(struct amdgpu_device *adev); -int 
amdgpu_amdkfd_resume(struct amdgpu_device *adev);
+void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm); 
+int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
const void *ih_ring_entry);
 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); @@ -249,8 +249,8 
@@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 struct drm_device *ddev,
 const struct kgd2kfd_shared_resources *gpu_resources); 
 void kgd2kfd_device_exit(struct kfd_dev *kfd); -void kgd2kfd_suspend(struct 
kfd_dev *kfd); -int kgd2kfd_resume(struct kfd_dev *kfd);
+void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); int 
+kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
 int kgd2kfd_pre_reset(struct kfd_dev *kfd);  int kgd2kfd_post_reset(struct 
kfd_dev *kfd);  void kgd2kfd_interrupt(struct kfd_dev *kfd, const void 
*ih_ring_entry); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5030a09babb8..43843e6c4bcd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3311,7 +3311,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
fbcon)
}
}
 
-   amdgpu_amdkfd_suspend(adev);
+   amdgpu_amdkfd_suspend(adev, !fbcon);
 
amdgpu_ras_suspend(adev);
 
@@ -3395,7 +3395,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
fbcon)
}
}
}
-   r = amdgpu_amdkfd_resume(adev);
+   r = 

[Patch v2 3/4] drm/amdkfd: refactor runtime pm for baco

[Rajneesh Bhardwaj]

So far the kfd driver implemented same routines for runtime and system
wide suspend and resume (s2idle or mem). During system wide suspend the
kfd aquires an atomic lock that prevents any more user processes to
create queues and interact with kfd driver and amd gpu. This mechanism
created problem when amdgpu device is runtime suspended with BACO
enabled. Any application that relies on kfd driver fails to load because
the driver reports a locked kfd device since gpu is runtime suspended.

However, in an ideal case, when gpu is runtime  suspended the kfd driver
should be able to:

 - auto resume amdgpu driver whenever a client requests compute service
 - prevent runtime suspend for amdgpu  while kfd is in use

This change refactors the amdgpu and amdkfd drivers to support BACO and
runtime power management.

Signed-off-by: Rajneesh Bhardwaj 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 12 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |  8 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 +-
 drivers/gpu/drm/amd/amdkfd/kfd_device.c| 29 +--
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_process.c   | 43 --
 6 files changed, 70 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 8609287620ea..314c4a2a0354 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -178,18 +178,18 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
 }
 
-void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
+void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
 {
if (adev->kfd.dev)
-   kgd2kfd_suspend(adev->kfd.dev);
+   kgd2kfd_suspend(adev->kfd.dev, run_pm);
 }
 
-int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
+int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
 {
int r = 0;
 
if (adev->kfd.dev)
-   r = kgd2kfd_resume(adev->kfd.dev);
+   r = kgd2kfd_resume(adev->kfd.dev, run_pm);
 
return r;
 }
@@ -713,11 +713,11 @@ void kgd2kfd_exit(void)
 {
 }
 
-void kgd2kfd_suspend(struct kfd_dev *kfd)
+void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
 {
 }
 
-int kgd2kfd_resume(struct kfd_dev *kfd)
+int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
 {
return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 47b0f2957d1f..9e8db702d878 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -122,8 +122,8 @@ struct amdkfd_process_info {
 int amdgpu_amdkfd_init(void);
 void amdgpu_amdkfd_fini(void);
 
-void amdgpu_amdkfd_suspend(struct amdgpu_device *adev);
-int amdgpu_amdkfd_resume(struct amdgpu_device *adev);
+void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
+int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
const void *ih_ring_entry);
 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
@@ -249,8 +249,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 struct drm_device *ddev,
 const struct kgd2kfd_shared_resources *gpu_resources);
 void kgd2kfd_device_exit(struct kfd_dev *kfd);
-void kgd2kfd_suspend(struct kfd_dev *kfd);
-int kgd2kfd_resume(struct kfd_dev *kfd);
+void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
+int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
 int kgd2kfd_pre_reset(struct kfd_dev *kfd);
 int kgd2kfd_post_reset(struct kfd_dev *kfd);
 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5030a09babb8..43843e6c4bcd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3311,7 +3311,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
fbcon)
}
}
 
-   amdgpu_amdkfd_suspend(adev);
+   amdgpu_amdkfd_suspend(adev, !fbcon);
 
amdgpu_ras_suspend(adev);
 
@@ -3395,7 +3395,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
fbcon)
}
}
}
-   r = amdgpu_amdkfd_resume(adev);
+   r = amdgpu_amdkfd_resume(adev, !fbcon);
if (r)
return r;
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 798ad1c8f799..42ee9ea5c45a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -732,7 +732,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 void kgd2kfd_device_exit(struct kfd_dev *kfd)
 {
if (kfd->init_complete) 

[Patch v2 0/4] Enable BACO with KFD

[Rajneesh Bhardwaj]

Changes in v2:
 * Rebased on latest amd-staging-drm-next
 * Addressed review comments from Felix, Oak and Alex for v1
 * Removed 60 second hack for auto-suspend delay and simplified the
   logic
 * Dropped kfd debugfs patch
 * Folded in Alex's patch from this series to enable and test with kfd.
   https://patchwork.freedesktop.org/series/67885/ also fixed a
   checkpatch warning.

Link to v1: https://www.spinics.net/lists/amd-gfx/msg44551.html

This series aims to enable BACO by default on supported AMD platforms
and ensures that the AMD Kernel Fusion Driver can co-exist with this
feature when the GPU devices are runtime suspended and firmware pushes
the envelop to save more power with BACO entry sequence. Current
approach makes sure that if KFD is using GPU services for compute, it
won't let AMDGPU driver suspend and if the AMDGPU driver is already
runtime suspended with GPUs in deep power saving mode with BACO, the KFD
driver wakes up the AMDGPU and then starts the compute workload
execution.

This series has been tested with a single GPU (fiji), Dual GPUs (fiji
and fiji/tonga) and seems to work fine with kfdtest. Also tested system
wide suspend to mem and suspend to idle and with this series and it
worked fine.

Alex Deucher (1):
  drm/amdgpu/runpm: enable runpm on baco capable VI+ asics

Rajneesh Bhardwaj (3):
  drm/amdgpu: Fix missing error check in suspend
  drm/amdkfd: show warning when kfd is locked
  drm/amdkfd: refactor runtime pm for baco

 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 12 
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |  8 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  3 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  8 --
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c   |  2 ++
 drivers/gpu/drm/amd/amdkfd/kfd_device.c| 29 +++
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_process.c   | 33 --
 9 files changed, 71 insertions(+), 29 deletions(-)

-- 
2.17.1

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[Patch v2 4/4] drm/amdgpu/runpm: enable runpm on baco capable VI+ asics

[Rajneesh Bhardwaj]

From: Alex Deucher 

Seems to work reliably on VI+.

[rajneesh] Picked https://patchwork.freedesktop.org/patch/335402/ to
enable runtime pm with baco for kfd. Also fixed a checkpatch warning and
dropped below patch from previous series in favor of Alex's patch.
https://www.spinics.net/lists/amd-gfx/msg44552.html

Reviewed-and-tested-by: Rajneesh Bhardwaj 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 3a0ea9096498..f4c039f8815c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -170,10 +170,14 @@ int amdgpu_driver_load_kms(struct drm_device *dev, 
unsigned long flags)
}
 
if (amdgpu_device_supports_boco(dev) &&
-   (amdgpu_runtime_pm != 0)) /* enable runpm by default */
+   (amdgpu_runtime_pm != 0)) /* enable runpm by default for boco */
adev->runpm = true;
else if (amdgpu_device_supports_baco(dev) &&
-(amdgpu_runtime_pm > 0)) /* enable runpm if runpm=1 */
+(amdgpu_runtime_pm != 0) &&
+(adev->asic_type >= CHIP_TOPAZ)) /* enable runpm on VI+ */
+   adev->runpm = true;
+   else if (amdgpu_device_supports_baco(dev) &&
+(amdgpu_runtime_pm > 0))  /* enable runpm if runpm=1 on CI */
adev->runpm = true;
 
/* Call ACPI methods: require modeset init
-- 
2.17.1

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[Patch v2 1/4] drm/amdgpu: Fix missing error check in suspend

[Rajneesh Bhardwaj]

amdgpu_device_suspend might return an error code since it can be called
from both runtime and system suspend flows. Add the missing return code
in case of a failure.

Reviewed-by: Alex Deucher 
Signed-off-by: Rajneesh Bhardwaj 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index f28d040de3ce..0026ff56542c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1235,6 +1235,9 @@ static int amdgpu_pmops_runtime_suspend(struct device 
*dev)
drm_kms_helper_poll_disable(drm_dev);
 
ret = amdgpu_device_suspend(drm_dev, false);
+   if (ret)
+   return ret;
+
if (amdgpu_device_supports_boco(drm_dev)) {
/* Only need to handle PCI state in the driver for ATPX
 * PCI core handles it for _PR3.
-- 
2.17.1

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[Patch v2 2/4] drm/amdkfd: show warning when kfd is locked

[Rajneesh Bhardwaj]

During system suspend the kfd driver aquires a lock that prohibits
further kfd actions unless the gpu is resumed. This adds some info which
can be useful while debugging.

Signed-off-by: Rajneesh Bhardwaj 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 275f79ab0900..86b919d82129 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -127,6 +127,8 @@ static int kfd_open(struct inode *inode, struct file *filep)
return PTR_ERR(process);
 
if (kfd_is_locked()) {
+   dev_dbg(kfd_device, "kfd is locked!\n"
+   "process %d unreferenced", process->pasid);
kfd_unref_process(process);
return -EAGAIN;
}
-- 
2.17.1

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[PATCH 33/33] drm/amd/display: turn off the mst hub before we do detection

[Bhawanpreet Lakha]

From: Joseph Gravenor 

[why]
not turning off the mst hub before detection on reboot
causes us to not be able to light up displays with mst hook

[how]
on hw init, see if any displays are lit up. if so, turn them off

Signed-off-by: Joseph Gravenor 
Reviewed-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 22 +--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0225f8d8bb82..42fcfee2c31b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -48,8 +48,8 @@
 #include "dc_link_dp.h"
 #include "dccg.h"
 #include "clk_mgr.h"
-
-
+#include "link_hwss.h"
+#include "dpcd_defs.h"
 #include "dsc.h"
 
 #define DC_LOGGER_INIT(logger)
@@ -1322,6 +1322,24 @@ void dcn10_init_hw(struct dc *dc)
if (hws->funcs.dsc_pg_control != NULL)
hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, 
false);
 
+   /* we want to turn off all dp displays before doing detection */
+   if (dc->config.power_down_display_on_boot) {
+   uint8_t dpcd_power_state = '\0';
+   enum dc_status status = DC_ERROR_UNEXPECTED;
+
+   for (i = 0; i < dc->link_count; i++) {
+   if (dc->links[i]->connector_signal != 
SIGNAL_TYPE_DISPLAY_PORT) {
+   continue;
+   }
+   /* if any of the displays are lit up turn them off */
+   status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+_power_state, 
sizeof(dpcd_power_state));
+   if (status == DC_OK && dpcd_power_state == 
DP_POWER_STATE_D0) {
+   dp_receiver_power_ctrl(dc->links[i], false);
+   }
+   }
+   }
+
/* If taking control over from VBIOS, we may want to optimize our first
 * mode set, so we need to skip powering down pipes until we know which
 * pipes we want to use.
-- 
2.17.1

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[PATCH 23/33] drm/amd/display: Check hyperV flag in DC.

[Bhawanpreet Lakha]

From: Yongqiang Sun 

[Why]
hyperV flag should be passed from dm to DC, and override the
nv12 flip workaround flag.

[How]
Add flag to phy address config struct and pass the value in dm.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dc.h| 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
index f2b39ec35c89..64cf24a9ab08 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
@@ -47,6 +47,9 @@ int dc_setup_system_context(struct dc *dc, struct 
dc_phy_addr_space_config *pa_c
 */
memcpy(>vm_pa_config, pa_config, sizeof(struct 
dc_phy_addr_space_config));
dc->vm_pa_config.valid = true;
+
+   if (pa_config->is_hvm_enabled == 0)
+   dc->debug.nv12_iflip_vm_wa = false;
}
 
return num_vmids;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7be2023f1a66..6f94906968b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -453,6 +453,7 @@ struct dc_phy_addr_space_config {
} gart_config;
 
bool valid;
+   bool is_hvm_enabled;
uint64_t page_table_default_page_addr;
 };
 
-- 
2.17.1

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[PATCH 20/33] drm/amd/display: Check engine is not NULL before acquiring

[Bhawanpreet Lakha]

From: Aric Cyr 

[Why]
Engine can be NULL in some cases, so we must not acquire it.

[How]
Check for NULL engine before acquiring.

Signed-off-by: Aric Cyr 
Reviewed-by: Harry Wentland 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index f1a5d2c6aa37..68c4049cbc2a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -400,7 +400,7 @@ static bool acquire(
 {
enum gpio_result result;
 
-   if (!is_engine_available(engine))
+   if ((engine == NULL) || !is_engine_available(engine))
return false;
 
result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
-- 
2.17.1

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[PATCH 16/33] drm/amd/display: remove early break in interdependent_lock

[Bhawanpreet Lakha]

From: Roman Li 

[Why]
The break in apply_ctx_interdependent_lock() may potentially
lead to early break from the loop leaving update plane unlocked

[How]
Remove break

Signed-off-by: Roman Li 
Reviewed-by: Anthony Koo 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2208282ea6cb..7fdd82b7708a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -778,7 +778,6 @@ void apply_ctx_interdependent_lock(struct dc *dc, struct 
dc_state *context, stru
if (!pipe_ctx->top_pipe &&
(pipe_ctx->plane_state || 
old_pipe_ctx->plane_state))
dc->hwss.pipe_control_lock(dc, 
pipe_ctx, lock);
-   break;
}
}
}
-- 
2.17.1

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[PATCH 30/33] drm/amd/display: linux enable oled panel support dc part

[Bhawanpreet Lakha]

From: Hersen Wu 

[Why] old panel has been enabled for window driver but not linux.

[How] enable oled panel support for linux. this patch is dc part.

Signed-off-by: Hersen Wu 
Reviewed-by: Harry Wentland 
Reviewed-by: Hersen Wu 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  32 +++-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 168 ++
 drivers/gpu/drm/amd/display/dc/dc.h   |  14 ++
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  34 
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  16 ++
 .../display/dc/dce110/dce110_hw_sequencer.c   |  14 ++
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   2 +
 7 files changed, 279 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fe50747692ec..bed57051f04d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -599,6 +599,9 @@ static bool detect_dp(
 
if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
+
+   dpcd_set_source_specific_data(link);
+
if (!detect_dp_sink_caps(link))
return false;
 
@@ -769,8 +772,16 @@ static bool dc_link_detect_helper(struct dc_link *link,
 
if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
link->connector_signal == SIGNAL_TYPE_EDP) &&
-   link->local_sink)
+   link->local_sink) {
+
+   // need to re-write OUI and brightness in resume case
+   if (link->connector_signal == SIGNAL_TYPE_EDP) {
+   dpcd_set_source_specific_data(link);
+   dc_link_set_default_brightness_aux(link); //TODO: use 
cached
+   }
+
return true;
+   }
 
if (false == dc_link_detect_sink(link, _connection_type)) {
BREAK_TO_DEBUGGER();
@@ -818,6 +829,10 @@ static bool dc_link_detect_helper(struct dc_link *link,
}
 
case SIGNAL_TYPE_EDP: {
+   read_current_link_settings_on_detect(link);
+
+   dpcd_set_source_specific_data(link);
+
detect_edp_sink_caps(link);
read_current_link_settings_on_detect(link);
sink_caps.transaction_type = 
DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
@@ -1492,6 +1507,7 @@ static enum dc_status enable_link_dp(
bool fec_enable;
int i;
bool apply_seamless_boot_optimization = false;
+   uint32_t bl_oled_enable_delay = 50; // in ms
 
// check for seamless boot
for (i = 0; i < state->stream_count; i++) {
@@ -1515,6 +1531,9 @@ static enum dc_status enable_link_dp(
if (state->clk_mgr && !apply_seamless_boot_optimization)
state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, 
false);
 
+   // during mode switch we do DP_SET_POWER off then on, and OUI is lost
+   dpcd_set_source_specific_data(link);
+
skip_video_pattern = true;
 
if (link_settings.link_rate == LINK_RATE_LOW)
@@ -1538,6 +1557,17 @@ static enum dc_status enable_link_dp(
fec_enable = true;
 
dp_set_fec_enable(link, fec_enable);
+
+   // during mode set we do DP_SET_POWER off then on, aux writes are lost
+   if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
+   link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
+   link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
+   dc_link_set_default_brightness_aux(link); // TODO: use cached 
if known
+   if (link->dpcd_sink_ext_caps.bits.oled == 1)
+   msleep(bl_oled_enable_delay);
+   dc_link_backlight_enable_aux(link, true);
+   }
+
return status;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 07b9aa1d01af..c5b45d17e8cd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -20,6 +20,14 @@
 
 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
 
+#define DP_SOURCE_TABLE_REVISION   0x310
+#define DP_SOURCE_PAYLOAD_SIZE 0x311
+#define DP_SOURCE_SINK_CAP 0x317
+#define DP_SOURCE_BACKLIGHT_LEVEL  0x320
+#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK0x326
+#define DP_SOURCE_BACKLIGHT_CONTROL0x32E
+#define DP_SOURCE_BACKLIGHT_ENABLE 0x32F
+
 /* maximum pre emphasis level allowed for each voltage swing level*/
 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
PRE_EMPHASIS_LEVEL3,
@@ -3166,6 +3174,23 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, 
uint8_t *dpcd_data,

[PATCH 03/33] drm/amd/display: remove invalid dc_is_hw_initialized function

[Bhawanpreet Lakha]

From: Joseph Gravenor 

[why/how]
We found out that the register we read actually gets reset by SMU
after we loose power, meaning this always returns true

Signed-off-by: Joseph Gravenor 
Reviewed-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 6 --
 drivers/gpu/drm/amd/display/dc/dc.h  | 1 -
 2 files changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 04441dbcba76..073172e53b5b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1318,12 +1318,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state 
*context)
return (result == DC_OK);
 }
 
-bool dc_is_hw_initialized(struct dc *dc)
-{
-   struct dc_bios *dcb = dc->ctx->dc_bios;
-   return dcb->funcs->is_accelerated_mode(dcb);
-}
-
 bool dc_post_update_surfaces_to_stream(struct dc *dc)
 {
int i;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 8ff25b5dd2f6..e8d126890d7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1075,7 +1075,6 @@ unsigned int dc_get_current_backlight_pwm(struct dc *dc);
 unsigned int dc_get_target_backlight_pwm(struct dc *dc);
 
 bool dc_is_dmcu_initialized(struct dc *dc);
-bool dc_is_hw_initialized(struct dc *dc);
 
 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, 
uint32_t clk_khz, uint32_t stepping);
 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct 
dc_clock_config *clock_cfg);
-- 
2.17.1

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[PATCH 26/33] drm/amd/display: Limit minimum DPPCLK to 100MHz.

[Bhawanpreet Lakha]

From: Yongqiang Sun 

[Why]
Underflow is observed when plug in a 4K@60 monitor with
1366x768 eDP due to DPPCLK is too low.

[How]
Limit minimum DPPCLK to 100MHz.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 8ecb98c29eb9..5d82ec1f1ce5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -151,6 +151,12 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, 
clk_mgr_base->clks.dcfclk_deep_sleep_khz);
}
 
+   // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch 
to plus 4K monitor underflow.
+   if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+   if (new_clocks->dppclk_khz < 10)
+   new_clocks->dppclk_khz = 10;
+   }
+
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, 
clk_mgr->base.clks.dppclk_khz)) {
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
dpp_clock_lowered = true;
-- 
2.17.1

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[PATCH 32/33] drm/amd/display: Add initialitions for PLL2 clock source

[Bhawanpreet Lakha]

From: Isabel Zhang 

[Why]
Starting from 14nm, the PLL is built into the PHY and the PLL is mapped
to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not
initialized. This causes DP to HDMI dongle to not light up the display.

[How]
Initializations added for PLL2 when creating resources.

Signed-off-by: Isabel Zhang 
Reviewed-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 5f6fb16f16e5..e7076b0d7afb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -60,6 +60,7 @@
 #include "dcn20/dcn20_dccg.h"
 #include "dcn21_hubbub.h"
 #include "dcn10/dcn10_resource.h"
+#include "dce110/dce110_resource.h"
 
 #include "dcn20/dcn20_dwb.h"
 #include "dcn20/dcn20_mmhubbub.h"
@@ -889,6 +890,7 @@ static const struct dc_debug_options debug_defaults_diags = 
{
 enum dcn20_clk_src_array_id {
DCN20_CLK_SRC_PLL0,
DCN20_CLK_SRC_PLL1,
+   DCN20_CLK_SRC_PLL2,
DCN20_CLK_SRC_TOTAL_DCN21
 };
 
@@ -1803,6 +1805,10 @@ static bool dcn21_resource_construct(
dcn21_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL1,
_src_regs[1], false);
+   pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
+   dcn21_clock_source_create(ctx, ctx->dc_bios,
+   CLOCK_SOURCE_COMBO_PHY_PLL2,
+   _src_regs[2], false);
 
pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
 
-- 
2.17.1

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[PATCH 08/33] drm/amd/display: Fix various issues found by compiler warning as errors

[Bhawanpreet Lakha]

From: Eric Bernstein 

[Why]
Diagnostics team reported various issues found when enabling warnings as errors

[How]
Fix implicit conversions

Signed-off-by: Eric Bernstein 
Reviewed-by: Aric Cyr 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c  | 2 +-
 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h   | 3 +--
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8ff0f5b7104b..07b9aa1d01af 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3681,7 +3681,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
struct pipe_ctx *odm_pipe;
enum controller_dp_color_space controller_color_space;
int opp_cnt = 1;
-   int count;
+   uint16_t count = 0;
 
switch (test_pattern_color_space) {
case DP_TEST_PATTERN_COLOR_SPACE_RGB:
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 658f81e757e9..1f5446321112 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -189,7 +189,7 @@ struct _vcs_dpi_ip_params_st {
unsigned int min_vblank_lines;
unsigned int dppclk_delay_subtotal;
unsigned int dispclk_delay_subtotal;
-   unsigned int dcfclk_cstate_latency;
+   double dcfclk_cstate_latency;
unsigned int dppclk_delay_scl;
unsigned int dppclk_delay_scl_lb_only;
unsigned int dppclk_delay_cnvc_formatter;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index 459f95f52486..f30ab4916242 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -25,16 +25,15 @@
 #ifndef __DC_DWBC_H__
 #define __DC_DWBC_H__
 
+#include "dal_types.h"
 #include "dc_hw_types.h"
 
-
 #define DWB_SW_V2  1
 #define DWB_MCIF_BUF_COUNT 4
 
 /* forward declaration of mcif_wb struct */
 struct mcif_wb;
 
-enum dce_version;
 
 enum dwb_sw_version {
dwb_ver_1_0 = 1,
-- 
2.17.1

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[PATCH 28/33] drm/amd/display: Add DMUB tracebuffer debugfs

[Bhawanpreet Lakha]

From: Nicholas Kazlauskas 

[Why]
The DMUB tracebuffer is useful for understanding DMCUB execution state.

[How]
Add a "show" attribute debugfs so we can loop through the buffer
and print the entries.

The structs for the entry format are defined in the debugfs since
the tracebuffer header no longer exists in the DMUB service.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Hersen Wu 
Acked-by: Bhawanpreet Lakha 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 61 +++
 1 file changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index f81d3439ee8c..ead5c05eec92 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -32,6 +32,19 @@
 #include "amdgpu_dm.h"
 #include "amdgpu_dm_debugfs.h"
 #include "dm_helpers.h"
+#include "dmub/inc/dmub_srv.h"
+
+struct dmub_debugfs_trace_header {
+   uint32_t entry_count;
+   uint32_t reserved[3];
+};
+
+struct dmub_debugfs_trace_entry {
+   uint32_t trace_code;
+   uint32_t tick_count;
+   uint32_t param0;
+   uint32_t param1;
+};
 
 /* function description
  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
@@ -675,6 +688,50 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct 
file *f, const char __us
return bytes_from_user;
 }
 
+/**
+ * Returns the DMCUB tracebuffer contents.
+ * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
+ */
+static int dmub_tracebuffer_show(struct seq_file *m, void *data)
+{
+   struct amdgpu_device *adev = m->private;
+   struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
+   struct dmub_debugfs_trace_entry *entries;
+   uint8_t *tbuf_base;
+   uint32_t tbuf_size, max_entries, num_entries, i;
+
+   if (!fb_info)
+   return 0;
+
+   tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
+   if (!tbuf_base)
+   return 0;
+
+   tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
+   max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
+ sizeof(struct dmub_debugfs_trace_entry);
+
+   num_entries =
+   ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
+
+   num_entries = min(num_entries, max_entries);
+
+   entries = (struct dmub_debugfs_trace_entry
+  *)(tbuf_base +
+ sizeof(struct dmub_debugfs_trace_header));
+
+   for (i = 0; i < num_entries; ++i) {
+   struct dmub_debugfs_trace_entry *entry = [i];
+
+   seq_printf(m,
+  "trace_code=%u tick_count=%u param0=%u param1=%u\n",
+  entry->trace_code, entry->tick_count, entry->param0,
+  entry->param1);
+   }
+
+   return 0;
+}
+
 /*
  * Returns the current and maximum output bpc for the connector.
  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc
@@ -880,6 +937,7 @@ static ssize_t dp_dpcd_data_read(struct file *f, char 
__user *buf,
return read_size - r;
 }
 
+DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
 DEFINE_SHOW_ATTRIBUTE(output_bpc);
 DEFINE_SHOW_ATTRIBUTE(vrr_range);
 
@@ -1188,5 +1246,8 @@ int dtn_debugfs_init(struct amdgpu_device *adev)
debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
   _confirm_fops);
 
+   debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
+  adev, _tracebuffer_fops);
+
return 0;
 }
-- 
2.17.1

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[PATCH 31/33] drm/amd/display: fix workaround for incorrect double buffer register for DLG ADL and TTU

[Bhawanpreet Lakha]

From: Tony Cheng 

[Why]
these registers should have been double buffered. SW workaround we will have SW 
program the more aggressive (lower) values
whenever we are upating this register, so we will not have underflow at expense 
of less optimzal request pattern.

[How]
there is a driver bug where we don't check for 0, which is uninitialzed HW 
default.  since 0 is smaller than any value we need to program,
driver end up with not programming these registers

Signed-off-by: Tony Cheng 
Reviewed-by: Yongqiang Sun 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 35 +--
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
index cf09b9335728..aa7b0e7eb945 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
@@ -79,32 +79,47 @@ void apply_DEDCN21_142_wa_for_hostvm_deadline(
struct _vcs_dpi_display_dlg_regs_st *dlg_attr)
 {
struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
-   uint32_t cur_value;
+   uint32_t refcyc_per_vm_group_vblank;
+   uint32_t refcyc_per_vm_req_vblank;
+   uint32_t refcyc_per_vm_group_flip;
+   uint32_t refcyc_per_vm_req_flip;
+   const uint32_t uninitialized_hw_default = 0;
 
-   REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, _value);
-   if (cur_value > dlg_attr->refcyc_per_vm_group_vblank)
+   REG_GET(VBLANK_PARAMETERS_5,
+   REFCYC_PER_VM_GROUP_VBLANK, 
_per_vm_group_vblank);
+
+   if (refcyc_per_vm_group_vblank == uninitialized_hw_default ||
+   refcyc_per_vm_group_vblank > 
dlg_attr->refcyc_per_vm_group_vblank)
REG_SET(VBLANK_PARAMETERS_5, 0,
REFCYC_PER_VM_GROUP_VBLANK, 
dlg_attr->refcyc_per_vm_group_vblank);
 
REG_GET(VBLANK_PARAMETERS_6,
-   REFCYC_PER_VM_REQ_VBLANK,
-   _value);
-   if (cur_value > dlg_attr->refcyc_per_vm_req_vblank)
+   REFCYC_PER_VM_REQ_VBLANK, _per_vm_req_vblank);
+
+   if (refcyc_per_vm_req_vblank == uninitialized_hw_default ||
+   refcyc_per_vm_req_vblank > 
dlg_attr->refcyc_per_vm_req_vblank)
REG_SET(VBLANK_PARAMETERS_6, 0,
REFCYC_PER_VM_REQ_VBLANK, 
dlg_attr->refcyc_per_vm_req_vblank);
 
-   REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, _value);
-   if (cur_value > dlg_attr->refcyc_per_vm_group_flip)
+   REG_GET(FLIP_PARAMETERS_3,
+   REFCYC_PER_VM_GROUP_FLIP, _per_vm_group_flip);
+
+   if (refcyc_per_vm_group_flip == uninitialized_hw_default ||
+   refcyc_per_vm_group_flip > 
dlg_attr->refcyc_per_vm_group_flip)
REG_SET(FLIP_PARAMETERS_3, 0,
REFCYC_PER_VM_GROUP_FLIP, 
dlg_attr->refcyc_per_vm_group_flip);
 
-   REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, _value);
-   if (cur_value > dlg_attr->refcyc_per_vm_req_flip)
+   REG_GET(FLIP_PARAMETERS_4,
+   REFCYC_PER_VM_REQ_FLIP, _per_vm_req_flip);
+
+   if (refcyc_per_vm_req_flip == uninitialized_hw_default ||
+   refcyc_per_vm_req_flip > 
dlg_attr->refcyc_per_vm_req_flip)
REG_SET(FLIP_PARAMETERS_4, 0,
REFCYC_PER_VM_REQ_FLIP, 
dlg_attr->refcyc_per_vm_req_flip);
 
REG_SET(FLIP_PARAMETERS_5, 0,
REFCYC_PER_PTE_GROUP_FLIP_C, 
dlg_attr->refcyc_per_pte_group_flip_c);
+
REG_SET(FLIP_PARAMETERS_6, 0,
REFCYC_PER_META_CHUNK_FLIP_C, 
dlg_attr->refcyc_per_meta_chunk_flip_c);
 }
-- 
2.17.1

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[PATCH 11/33] drm/amd/display: Added locking for atomic update stream and update planes

[Bhawanpreet Lakha]

From: Anthony Koo 

[Why]
Screen flickering when HDR switches between FP16 and ARGB2101010

[How]
Moved pipe_control_lock so stream update and plane update occur atomically

Signed-off-by: Anthony Koo 
Signed-off-by: Lucy Li 
Reviewed-by: Aric Cyr 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  87 +++
 .../display/dc/dce110/dce110_hw_sequencer.c   |  23 +---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  32 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   4 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   1 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 101 --
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|   4 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   2 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   2 +-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   4 +-
 10 files changed, 125 insertions(+), 135 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c9c7cf00976f..2208282ea6cb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -761,6 +761,29 @@ static bool disable_all_writeback_pipes_for_stream(
return true;
 }
 
+void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, 
struct dc_stream_state *stream, bool lock)
+{
+   int i = 0;
+
+   /* Checks if interdependent update function pointer is NULL or not, 
takes care of DCE110 case */
+   if (dc->hwss.interdependent_update_lock)
+   dc->hwss.interdependent_update_lock(dc, context, lock);
+   else {
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   struct pipe_ctx *pipe_ctx = 
>res_ctx.pipe_ctx[i];
+   struct pipe_ctx *old_pipe_ctx = 
>current_state->res_ctx.pipe_ctx[i];
+
+   // Copied conditions that were previously in 
dce110_apply_ctx_for_surface
+   if (stream == pipe_ctx->stream) {
+   if (!pipe_ctx->top_pipe &&
+   (pipe_ctx->plane_state || 
old_pipe_ctx->plane_state))
+   dc->hwss.pipe_control_lock(dc, 
pipe_ctx, lock);
+   break;
+   }
+   }
+   }
+}
+
 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 {
int i, j;
@@ -786,12 +809,17 @@ static void disable_dangling_plane(struct dc *dc, struct 
dc_state *context)
if (should_disable && old_stream) {
dc_rem_all_planes_for_stream(dc, old_stream, 
dangling_context);
disable_all_writeback_pipes_for_stream(dc, old_stream, 
dangling_context);
+
if (dc->hwss.apply_ctx_for_surface) {
+   apply_ctx_interdependent_lock(dc, 
dc->current_state, old_stream, true);
dc->hwss.apply_ctx_for_surface(dc, old_stream, 
0, dangling_context);
+   apply_ctx_interdependent_lock(dc, 
dc->current_state, old_stream, false);
dc->hwss.post_unlock_program_front_end(dc, 
dangling_context);
}
if (dc->hwss.program_front_end_for_ctx) {
+   dc->hwss.interdependent_update_lock(dc, 
dc->current_state, true);
dc->hwss.program_front_end_for_ctx(dc, 
dangling_context);
+   dc->hwss.interdependent_update_lock(dc, 
dc->current_state, false);
dc->hwss.post_unlock_program_front_end(dc, 
dangling_context);
}
}
@@ -1214,17 +1242,19 @@ static enum dc_status dc_commit_state_no_check(struct 
dc *dc, struct dc_state *c
/* re-program planes for existing stream, in case we need to
 * free up plane resource for later use
 */
-   if (dc->hwss.apply_ctx_for_surface)
+   if (dc->hwss.apply_ctx_for_surface) {
for (i = 0; i < context->stream_count; i++) {
if (context->streams[i]->mode_changed)
continue;
-
+   apply_ctx_interdependent_lock(dc, context, 
context->streams[i], true);
dc->hwss.apply_ctx_for_surface(
dc, context->streams[i],
context->stream_status[i].plane_count,
context); /* use new pipe config in new context 
*/
+   apply_ctx_interdependent_lock(dc, context, 
context->streams[i], false);
dc->hwss.post_unlock_program_front_end(dc, context);
}
+   }
 
/* Program hardware */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1244,10 +1274,11 @@ static enum 

[PATCH 07/33] drm/amd/display: Indicate dsc updates explicitly

[Bhawanpreet Lakha]

From: Anthony Koo 

[Why]
DSC updates only set type to FULL UPDATE, but doesn't
flag the change

[How]
Add DSC flag update flag

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 19 ---
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  1 +
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 738ba91220df..c9c7cf00976f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1738,14 +1738,15 @@ static enum surface_update_type 
check_update_surfaces_for_stream(
 
if (stream_update->wb_update)
su_flags->bits.wb_update = 1;
+
+   if (stream_update->dsc_config)
+   su_flags->bits.dsc_changed = 1;
+
if (su_flags->raw != 0)
overall_type = UPDATE_TYPE_FULL;
 
if (stream_update->output_csc_transform || 
stream_update->output_color_space)
su_flags->bits.out_csc = 1;
-
-   if (stream_update->dsc_config)
-   overall_type = UPDATE_TYPE_FULL;
}
 
for (i = 0 ; i < surface_count; i++) {
@@ -1780,8 +1781,11 @@ enum surface_update_type 
dc_check_update_surfaces_for_stream(
 
type = check_update_surfaces_for_stream(dc, updates, surface_count, 
stream_update, stream_status);
if (type == UPDATE_TYPE_FULL) {
-   if (stream_update)
+   if (stream_update) {
+   uint32_t dsc_changed = 
stream_update->stream->update_flags.bits.dsc_changed;
stream_update->stream->update_flags.raw = 0x;
+   stream_update->stream->update_flags.bits.dsc_changed = 
dsc_changed;
+   }
for (i = 0; i < surface_count; i++)
updates[i].surface->update_flags.raw = 0x;
}
@@ -2097,14 +2101,15 @@ static void commit_planes_do_stream_update(struct dc 
*dc,
}
}
 
+   /* Full fe update*/
+   if (update_type == UPDATE_TYPE_FAST)
+   continue;
+
if (stream_update->dsc_config && 
dc->hwss.pipe_control_lock_global) {
dc->hwss.pipe_control_lock_global(dc, pipe_ctx, 
true);
dp_update_dsc_config(pipe_ctx);
dc->hwss.pipe_control_lock_global(dc, pipe_ctx, 
false);
}
-   /* Full fe update*/
-   if (update_type == UPDATE_TYPE_FAST)
-   continue;
 
if (stream_update->dpms_off) {
dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 92096de79dec..a5c7ef47b8d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -118,6 +118,7 @@ union stream_update_flags {
uint32_t dpms_off:1;
uint32_t gamut_remap:1;
uint32_t wb_update:1;
+   uint32_t dsc_changed : 1;
} bits;
 
uint32_t raw;
-- 
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[PATCH 19/33] drm/amd/display: Use dcfclk to populate watermark ranges

[Bhawanpreet Lakha]

From: Sung Lee 

[WHY & HOW]
Previously drain clk was unconstrained and fill clk was constrained on fclk.
We want to change it to fill clk unconstrained and drain clock constrained
to dcfclk.

Signed-off-by: Sung Lee 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c  | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 7ae4c06232dd..034a5852a416 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -412,19 +412,19 @@ void build_watermark_ranges(struct clk_bw_params 
*bw_params, struct pp_smu_wm_ra
 
ranges->reader_wm_sets[num_valid_sets].wm_inst = 
bw_params->wm_table.entries[i].wm_inst;
ranges->reader_wm_sets[num_valid_sets].wm_type = 
bw_params->wm_table.entries[i].wm_type;
-   /* We will not select WM based on dcfclk, so leave it as 
unconstrained */
-   ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
-   ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
-   /* fclk wil be used to select WM*/
+   /* We will not select WM based on fclk, so leave it as 
unconstrained */
+   ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+   ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = 
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+   /* dcfclk wil be used to select WM*/
 
if (ranges->reader_wm_sets[num_valid_sets].wm_type == 
WM_TYPE_PSTATE_CHG) {
if (i == 0)
-   
ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0;
+   
ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0;
else {
/* add 1 to make it non-overlapping with next 
lvl */
-   
ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 
bw_params->clk_table.entries[i - 1].fclk_mhz + 1;
+   
ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
-   ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz 
= bw_params->clk_table.entries[i].fclk_mhz;
+   
ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = 
bw_params->clk_table.entries[i].dcfclk_mhz;
 
} else {
/* unconstrained for memory retraining */
-- 
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[PATCH 18/33] drm/amd/display: add stream_enc_inst for PSP HDCP inst use

[Bhawanpreet Lakha]

From: Charlene Liu 

[why]
new HW engine mapping requirment use in PSP
[how]
report stream_enc_inst

Signed-off-by: Charlene Liu 
Reviewed-by: Wenjing Liu 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c   | 3 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 1 +
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h  | 1 +
 5 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 41184e593f85..fe50747692ec 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2922,7 +2922,8 @@ static void update_psp_stream_config(struct pipe_ctx 
*pipe_ctx, bool dpms_off)
memset(, 0, sizeof(config));
 
config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
-   config.stream_enc_inst = (uint8_t) 
pipe_ctx->stream_res.stream_enc->id;
+   /*stream_enc_inst*/
+   config.stream_enc_inst = (uint8_t) 
pipe_ctx->stream_res.stream_enc->stream_enc_inst;
config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
config.dpms_off = dpms_off;
config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index a0eb9e533a61..cd80d8249d14 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2034,7 +2034,7 @@ enum dc_status resource_map_pool_resources(
for (i = 0; i < context->stream_count; i++)
if (context->streams[i] == stream) {
context->stream_status[i].primary_otg_inst = 
pipe_ctx->stream_res.tg->inst;
-   context->stream_status[i].stream_enc_inst = 
pipe_ctx->stream_res.stream_enc->id;
+   context->stream_status[i].stream_enc_inst = 
pipe_ctx->stream_res.stream_enc->stream_enc_inst;
context->stream_status[i].audio_inst =
pipe_ctx->stream_res.audio ? 
pipe_ctx->stream_res.audio->inst : -1;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 376c4264d295..7eba9333c328 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -1667,5 +1667,6 @@ void dcn10_stream_encoder_construct(
enc1->regs = regs;
enc1->se_shift = se_shift;
enc1->se_mask = se_mask;
+   enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 9b70a1e7b962..99a7ef6ab878 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -616,5 +616,6 @@ void dcn20_stream_encoder_construct(
enc1->regs = regs;
enc1->se_shift = se_shift;
enc1->se_mask = se_mask;
+   enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 351b387ad606..ac6523c0828e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -103,6 +103,7 @@ struct stream_encoder {
struct dc_context *ctx;
struct dc_bios *bp;
enum engine_id id;
+   uint32_t stream_enc_inst;
 };
 
 struct enc_state {
-- 
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[PATCH 09/33] drm/amd/display: Add GPINT handler interface

[Bhawanpreet Lakha]

From: Nicholas Kazlauskas 

[Why]
The General Purpose Interrupt is used on the DMCUB to pass lightweight
commands via a register to the DMCUB.

This is limited to 32-bit command and 32-bit response.

This will be used for shutting down the firmware in a clean manner.

[How]
Add the command IDs and the data register to correctly format
the commands.

Add the interface functions to dmub_srv for sending and receiving the
commands.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dmub/inc/dmub_gpint_cmd.h | 68 +++
 .../gpu/drm/amd/display/dmub/inc/dmub_srv.h   | 48 +
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 22 ++
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h |  9 +++
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 50 ++
 5 files changed, 197 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h
new file mode 100644
index ..5398ed6b35d1
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DMUB_GPINT_CMD_H_
+#define _DMUB_GPINT_CMD_H_
+
+#include "dmub_types.h"
+
+/**
+ * The register format for sending a command via the GPINT.
+ */
+union dmub_gpint_data_register {
+   struct {
+   uint32_t param : 16;
+   uint32_t command_code : 12;
+   uint32_t status : 4;
+   } bits;
+   uint32_t all;
+};
+
+/**
+ * The shifts and masks below may alternatively be used to format and read
+ * the command register bits.
+ */
+
+#define DMUB_GPINT_DATA_PARAM_MASK 0x
+#define DMUB_GPINT_DATA_PARAM_SHIFT 0
+
+#define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
+#define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
+
+#define DMUB_GPINT_DATA_STATUS_MASK 0xF
+#define DMUB_GPINT_DATA_STATUS_SHIFT 28
+
+/*
+ * Command IDs should be treated as stable ABI.
+ * Do not reuse or modify IDs.
+ */
+
+enum dmub_gpint_command {
+   DMUB_GPINT__INVALID_COMMAND = 0,
+   DMUB_GPINT__GET_FW_VERSION = 1,
+   DMUB_GPINT__STOP_FW = 2,
+};
+
+#endif /* _DMUB_GPINT_CMD_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
index f8917594036a..e619fa9cf53a 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
@@ -66,6 +66,7 @@
 
 #include "dmub_types.h"
 #include "dmub_cmd.h"
+#include "dmub_gpint_cmd.h"
 #include "dmub_rb.h"
 
 #if defined(__cplusplus)
@@ -262,6 +263,14 @@ struct dmub_srv_hw_funcs {
bool (*is_phy_init)(struct dmub_srv *dmub);
 
bool (*is_auto_load_done)(struct dmub_srv *dmub);
+
+   void (*set_gpint)(struct dmub_srv *dmub,
+ union dmub_gpint_data_register reg);
+
+   bool (*is_gpint_acked)(struct dmub_srv *dmub,
+  union dmub_gpint_data_register reg);
+
+   uint32_t (*get_gpint_response)(struct dmub_srv *dmub);
 };
 
 /**
@@ -516,6 +525,45 @@ enum dmub_status dmub_srv_wait_for_phy_init(struct 
dmub_srv *dmub,
 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
uint32_t timeout_us);
 
+/**
+ * dmub_srv_send_gpint_command() - Sends a GPINT based command.
+ * @dmub: the dmub service
+ * @command_code: the command code to send
+ * @param: the command parameter to send
+ * @timeout_us: the maximum number of microseconds to wait
+ *
+ * Sends a command via the general purpose interrupt (GPINT).
+ * Waits for the number of microseconds specified by timeout_us
+ * for the command ACK before returning.
+ *
+ * Can be called after software 

[PATCH 24/33] drm/amd/display: Add wm ranges to clk_mgr

[Bhawanpreet Lakha]

From: Sung Lee 

[WHY & HOW]
Having watermark ranges saved inside clk_mgr to be
available for debug at all times would be useful.
Add it to the clk_mgr_internal struct for reference.
Only populated for Renoir, unused for other asics.

Signed-off-by: Sung Lee 
Reviewed-by: Yongqiang Sun 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 5 ++---
 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   | 2 ++
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 034a5852a416..8ecb98c29eb9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -459,16 +459,15 @@ void build_watermark_ranges(struct clk_bw_params 
*bw_params, struct pp_smu_wm_ra
 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 {
struct dc_debug_options *debug = _mgr_base->ctx->dc->debug;
-   struct pp_smu_wm_range_sets ranges = {0};
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;
 
if (!debug->disable_pplib_wm_range) {
-   build_watermark_ranges(clk_mgr_base->bw_params, );
+   build_watermark_ranges(clk_mgr_base->bw_params, 
_mgr_base->ranges);
 
/* Notify PP Lib/SMU which Watermarks to use for which clock 
ranges */
if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
-   
pp_smu->rn_funcs.set_wm_ranges(_smu->rn_funcs.pp_smu, );
+   
pp_smu->rn_funcs.set_wm_ranges(_smu->rn_funcs.pp_smu, _mgr_base->ranges);
}
 
 }
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index ac530c057ddd..ce65678c03b2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -27,6 +27,7 @@
 #define __DAL_CLK_MGR_H__
 
 #include "dc.h"
+#include "dm_pp_smu.h"
 
 #define DCN_MINIMUM_DISPCLK_Khz 10
 #define DCN_MINIMUM_DPPCLK_Khz 10
@@ -193,6 +194,7 @@ struct clk_mgr {
int dentist_vco_freq_khz;
struct clk_state_registers_and_bypass boot_snapshot;
struct clk_bw_params *bw_params;
+   struct pp_smu_wm_range_sets ranges;
 };
 
 /* forward declarations */
-- 
2.17.1

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[PATCH 00/33] DC Patches 31 Jan 2020

[Bhawanpreet Lakha]

Summary Of Changes
*DMCUB changes
*psr frame calculation fix
*fix compile warnings
*refactor front end programing
*enable OLED support in DC

Anthony Koo (3):
  drm/amd/display: Split program front end part that occur outside lock
  drm/amd/display: Indicate dsc updates explicitly
  drm/amd/display: Added locking for atomic update stream and update
planes

Aric Cyr (5):
  drm/amd/display: Fix GSL acquire
  drm/amd/display: remove unused variable
  drm/amd/display: 3.2.70
  drm/amd/display: Check engine is not NULL before acquiring
  drm/amd/display: 3.2.71

Charlene Liu (1):
  drm/amd/display: add stream_enc_inst for PSP HDCP inst use

David Galiffi (1):
  drm/amd/display: Use uint64_t logger_mask instead of uint32_t

Eric Bernstein (1):
  drm/amd/display: Fix various issues found by compiler warning as
errors

Eric Yang (1):
  drm/amd/display: fix inputting clk lvl into dml for RN

George Shen (1):
  drm/amd/display: Move USB-C workaround to after parameter variables
are set

Hersen Wu (1):
  drm/amd/display: linux enable oled panel support dc part

Isabel Zhang (1):
  drm/amd/display: Add initialitions for PLL2 clock source

Jing Zhou (1):
  drm/amd/display: external monitor abm enabled in modern standby

Joseph Gravenor (2):
  drm/amd/display: remove invalid dc_is_hw_initialized function
  drm/amd/display: turn off the mst hub before we do detection

Nicholas Kazlauskas (3):
  drm/amd/display: Add GPINT handler interface
  drm/amd/display: Wait for clean shutdown in DMCUB reset
  drm/amd/display: Add DMUB tracebuffer debugfs

Peikang Zhang (2):
  drm/amd/display: dc_get_vmid_use_vector() crashes when get called
  drm/amd/display: Update hubbub description comment

Roman Li (2):
  drm/amd/display: Fix psr static frames calculation
  drm/amd/display: remove early break in interdependent_lock

Sung Lee (3):
  drm/amd/display: Do not set optimized_require to false after plane
disable
  drm/amd/display: Use dcfclk to populate watermark ranges
  drm/amd/display: Add wm ranges to clk_mgr

Tony Cheng (1):
  drm/amd/display: fix workaround for incorrect double buffer register
for DLG ADL and TTU

Wenjing Liu (1):
  drm/amd/display: decouple global lock out of pipe control lock

Wyatt Wood (1):
  drm/amd/display: Add set psr version message

Yongqiang Sun (2):
  drm/amd/display: Check hyperV flag in DC.
  drm/amd/display: Limit minimum DPPCLK to 100MHz.

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   5 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  61 ++
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |  25 ++-
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 149 ++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  41 +++-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 189 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   2 +-
 .../drm/amd/display/dc/core/dc_vm_helper.c|   5 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |  22 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  34 
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  16 ++
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   1 +
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |   2 +-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  62 --
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |   9 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  43 ++--
 .../drm/amd/display/dc/dcn10/dcn10_hubbub.c   |  63 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  93 ++---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   7 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   2 +
 .../display/dc/dcn10/dcn10_stream_encoder.c   |   1 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  90 +++--
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|   7 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   3 +-
 .../display/dc/dcn20/dcn20_stream_encoder.c   |   1 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c |  35 +++-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   3 +-
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 171 
 .../amd/display/dc/dml/display_mode_structs.h |   5 +-
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   2 +
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |   2 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h   |   3 +-
 .../amd/display/dc/inc/hw/stream_encoder.h|   1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   6 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  10 +-
 .../drm/amd/display/dmub/inc/dmub_cmd_dal.h   |   4 +-
 .../drm/amd/display/dmub/inc/dmub_gpint_cmd.h |  74 +++
 .../gpu/drm/amd/display/dmub/inc/dmub_srv.h   |  48 +
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c |  58 ++
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h |   9 +
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |  50 +
 41 files changed, 1074 insertions(+), 340 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h

-- 
2.17.1

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[PATCH 27/33] drm/amd/display: 3.2.71

[Bhawanpreet Lakha]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index c489a863f108..e52a469b4672 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.70"
+#define DC_VER "3.2.71"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 25/33] drm/amd/display: Use uint64_t logger_mask instead of uint32_t

[Bhawanpreet Lakha]

From: David Galiffi 

[WHY]
enum dc_log_type has more than 32 entries. User cannot set larger entries,
like LOG_DSC. Logs from LOG_GAMMA_DEBUG where being printed even though
flag was not enabled, because dal_logger_should_log check erroneously
passed.

[HOW]
Change struct dal_logger.mask and struct dc_init_data.mask to uint64_t.

Signed-off-by: David Galiffi 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 6f94906968b3..c489a863f108 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -566,7 +566,8 @@ struct dc_init_data {
struct dc_reg_helper_state *dmub_offload;
 
struct dc_config flags;
-   uint32_t log_mask;
+   uint64_t log_mask;
+
/**
 * gpu_info FW provided soc bounding box struct or 0 if not
 * available in FW
-- 
2.17.1

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[PATCH 14/33] drm/amd/display: 3.2.70

[Bhawanpreet Lakha]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index d00b72df469a..7be2023f1a66 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.69"
+#define DC_VER "3.2.70"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 06/33] drm/amd/display: Split program front end part that occur outside lock

[Bhawanpreet Lakha]

From: Anthony Koo 

[Why]
Eventually want to lock at a higher level in stack.
To do this, we need to be able to isolate the parts that need to be done
after pipe unlock.

[How]
Split out programming that is done post unlock.

Signed-off-by: Anthony Koo 
Reviewed-by: Aric Cyr 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 24 +---
 .../display/dc/dce110/dce110_hw_sequencer.c   |  6 +++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 39 ---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  3 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |  1 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 11 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|  3 ++
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |  1 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |  1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  2 +
 10 files changed, 79 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 073172e53b5b..738ba91220df 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -786,11 +786,15 @@ static void disable_dangling_plane(struct dc *dc, struct 
dc_state *context)
if (should_disable && old_stream) {
dc_rem_all_planes_for_stream(dc, old_stream, 
dangling_context);
disable_all_writeback_pipes_for_stream(dc, old_stream, 
dangling_context);
-   if (dc->hwss.apply_ctx_for_surface)
+   if (dc->hwss.apply_ctx_for_surface) {
dc->hwss.apply_ctx_for_surface(dc, old_stream, 
0, dangling_context);
+   dc->hwss.post_unlock_program_front_end(dc, 
dangling_context);
+   }
+   if (dc->hwss.program_front_end_for_ctx) {
+   dc->hwss.program_front_end_for_ctx(dc, 
dangling_context);
+   dc->hwss.post_unlock_program_front_end(dc, 
dangling_context);
+   }
}
-   if (dc->hwss.program_front_end_for_ctx)
-   dc->hwss.program_front_end_for_ctx(dc, 
dangling_context);
}
 
current_ctx = dc->current_state;
@@ -1219,6 +1223,7 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
dc, context->streams[i],
context->stream_status[i].plane_count,
context); /* use new pipe config in new context 
*/
+   dc->hwss.post_unlock_program_front_end(dc, context);
}
 
/* Program hardware */
@@ -1238,19 +1243,24 @@ static enum dc_status dc_commit_state_no_check(struct 
dc *dc, struct dc_state *c
}
 
/* Program all planes within new context*/
-   if (dc->hwss.program_front_end_for_ctx)
+   if (dc->hwss.program_front_end_for_ctx) {
dc->hwss.program_front_end_for_ctx(dc, context);
+   dc->hwss.post_unlock_program_front_end(dc, context);
+   }
+
for (i = 0; i < context->stream_count; i++) {
const struct dc_link *link = context->streams[i]->link;
 
if (!context->streams[i]->mode_changed)
continue;
 
-   if (dc->hwss.apply_ctx_for_surface)
+   if (dc->hwss.apply_ctx_for_surface) {
dc->hwss.apply_ctx_for_surface(
dc, context->streams[i],
context->stream_status[i].plane_count,
context);
+   dc->hwss.post_unlock_program_front_end(dc, context);
+   }
 
/*
 * enable stereo
@@ -2183,6 +2193,7 @@ static void commit_planes_for_stream(struct dc *dc,
if (dc->hwss.program_front_end_for_ctx)
dc->hwss.program_front_end_for_ctx(dc, context);
 
+   dc->hwss.post_unlock_program_front_end(dc, context);
return;
}
 
@@ -2315,6 +2326,9 @@ static void commit_planes_for_stream(struct dc *dc,
dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
}
 
+   if (update_type != UPDATE_TYPE_FAST)
+   dc->hwss.post_unlock_program_front_end(dc, context);
+
// Fire manual trigger only when bottom plane is flipped
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 5b689273ff44..a961b94aefd9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ 

[PATCH 22/33] drm/amd/display: fix inputting clk lvl into dml for RN

[Bhawanpreet Lakha]

From: Eric Yang 

[Why]
Previous logic is only good for 15W parts. Other configuration
need a smarter logic to match clk levels with pp table in the fuse.

[How]
Cache all 8 DPM level's clock data, find lvl that match each pstate
in the pp table and build input into DML base on that

Signed-off-by: Eric Yang 
Signed-off-by: Sung Lee 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 165 +-
 .../amd/display/dc/dml/display_mode_structs.h |   3 +-
 2 files changed, 127 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 0d506d30d6b6..5f6fb16f16e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -162,10 +162,10 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.clock_limits = {
{
.state = 0,
-   .dcfclk_mhz = 304.0,
-   .fabricclk_mhz = 600.0,
-   .dispclk_mhz = 618.0,
-   .dppclk_mhz = 440.0,
+   .dcfclk_mhz = 400.0,
+   .fabricclk_mhz = 400.0,
+   .dispclk_mhz = 600.0,
+   .dppclk_mhz = 400.00,
.phyclk_mhz = 600.0,
.socclk_mhz = 278.0,
.dscclk_mhz = 205.67,
@@ -173,10 +173,10 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
},
{
.state = 1,
-   .dcfclk_mhz = 304.0,
-   .fabricclk_mhz = 600.0,
-   .dispclk_mhz = 618.0,
-   .dppclk_mhz = 618.0,
+   .dcfclk_mhz = 464.52,
+   .fabricclk_mhz = 800.0,
+   .dispclk_mhz = 654.55,
+   .dppclk_mhz = 626.09,
.phyclk_mhz = 600.0,
.socclk_mhz = 278.0,
.dscclk_mhz = 205.67,
@@ -184,32 +184,65 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
},
{
.state = 2,
-   .dcfclk_mhz = 608.0,
-   .fabricclk_mhz = 1066.0,
-   .dispclk_mhz = 888.0,
-   .dppclk_mhz = 888.0,
-   .phyclk_mhz = 810.0,
+   .dcfclk_mhz = 514.29,
+   .fabricclk_mhz = 933.0,
+   .dispclk_mhz = 757.89,
+   .dppclk_mhz = 685.71,
+   .phyclk_mhz = 600.0,
.socclk_mhz = 278.0,
.dscclk_mhz = 287.67,
-   .dram_speed_mts = 2133.0,
+   .dram_speed_mts = 1866.0,
},
{
.state = 3,
-   .dcfclk_mhz = 676.0,
-   .fabricclk_mhz = 1600.0,
-   .dispclk_mhz = 1015.0,
-   .dppclk_mhz = 1015.0,
-   .phyclk_mhz = 810.0,
+   .dcfclk_mhz = 576.00,
+   .fabricclk_mhz = 1067.0,
+   .dispclk_mhz = 847.06,
+   .dppclk_mhz = 757.89,
+   .phyclk_mhz = 600.0,
.socclk_mhz = 715.0,
.dscclk_mhz = 318.334,
-   .dram_speed_mts = 4266.0,
+   .dram_speed_mts = 2134.0,
},
{
.state = 4,
-   .dcfclk_mhz = 810.0,
+   .dcfclk_mhz = 626.09,
+   .fabricclk_mhz = 1200.0,
+   .dispclk_mhz = 900.00,
+   .dppclk_mhz = 847.06,
+   .phyclk_mhz = 810.0,
+   .socclk_mhz = 953.0,
+   .dscclk_mhz = 489.0,
+   .dram_speed_mts = 2400.0,
+   },
+   {
+   .state = 5,
+   .dcfclk_mhz = 685.71,
+   .fabricclk_mhz = 1333.0,
+   

[PATCH 17/33] drm/amd/display: Update hubbub description comment

[Bhawanpreet Lakha]

From: Peikang Zhang 

Description for DCHUBBUB_TEST_DEBUG_DATA is changed to avoid any future 
confusions.

Signed-off-by: Peikang Zhang 
Reviewed-by: Aric Cyr 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/dcn10/dcn10_hubbub.c   | 63 +--
 1 file changed, 3 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index f36a0d8cedfe..870735deaca7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -147,8 +147,9 @@ bool hubbub1_verify_allow_pstate_change_high(
forced_pstate_allow = false;
}
 
-   /* RV2:
-* dchubbubdebugind, at: 0xB
+   /* The following table only applies to DCN1 and DCN2,
+* for newer DCNs, need to consult with HW IP folks to read RTL
+* HUBBUB:DCHUBBUB_TEST_ARB_DEBUG10 DCHUBBUBDEBUGIND:0xB
 * description
 * 0: Pipe0 Plane0 Allow Pstate Change
 * 1: Pipe0 Plane1 Allow Pstate Change
@@ -181,64 +182,6 @@ bool hubbub1_verify_allow_pstate_change_high(
 * 28:WB0 Allow Pstate Change
 * 29:WB1 Allow Pstate Change
 * 30:Arbiter's allow_pstate_change
-* 31:SOC pstate change request"
-*/
-   /*DCN2.x:
-   HUBBUB:DCHUBBUB_TEST_ARB_DEBUG10 DCHUBBUBDEBUGIND:0xB
-   0: Pipe0 Plane0 Allow P-state Change
-   1: Pipe0 Plane1 Allow P-state Change
-   2: Pipe0 Cursor0 Allow P-state Change
-   3: Pipe0 Cursor1 Allow P-state Change
-   4: Pipe1 Plane0 Allow P-state Change
-   5: Pipe1 Plane1 Allow P-state Change
-   6: Pipe1 Cursor0 Allow P-state Change
-   7: Pipe1 Cursor1 Allow P-state Change
-   8: Pipe2 Plane0 Allow P-state Change
-   9: Pipe2 Plane1 Allow P-state Change
-   10: Pipe2 Cursor0 Allow P-state Change
-   11: Pipe2 Cursor1 Allow P-state Change
-   12: Pipe3 Plane0 Allow P-state Change
-   13: Pipe3 Plane1 Allow P-state Change
-   14: Pipe3 Cursor0 Allow P-state Change
-   15: Pipe3 Cursor1 Allow P-state Change
-   16: Pipe4 Plane0 Allow P-state Change
-   17: Pipe4 Plane1 Allow P-state Change
-   18: Pipe4 Cursor0 Allow P-state Change
-   19: Pipe4 Cursor1 Allow P-state Change
-   20: Pipe5 Plane0 Allow P-state Change
-   21: Pipe5 Plane1 Allow P-state Change
-   22: Pipe5 Cursor0 Allow P-state Change
-   23: Pipe5 Cursor1 Allow P-state Change
-   24: Pipe6 Plane0 Allow P-state Change
-   25: Pipe6 Plane1 Allow P-state Change
-   26: Pipe6 Cursor0 Allow P-state Change
-   27: Pipe6 Cursor1 Allow P-state Change
-   28: WB0 Allow P-state Change
-   29: WB1 Allow P-state Change
-   30: Arbiter`s Allow P-state Change
-   31: SOC P-state Change request
-   */
-   /* RV1:
-* dchubbubdebugind, at: 0x7
-* description "3-0:   Pipe0 cursor0 QOS
-* 7-4:   Pipe1 cursor0 QOS
-* 11-8:  Pipe2 cursor0 QOS
-* 15-12: Pipe3 cursor0 QOS
-* 16:Pipe0 Plane0 Allow Pstate Change
-* 17:Pipe1 Plane0 Allow Pstate Change
-* 18:Pipe2 Plane0 Allow Pstate Change
-* 19:Pipe3 Plane0 Allow Pstate Change
-* 20:Pipe0 Plane1 Allow Pstate Change
-* 21:Pipe1 Plane1 Allow Pstate Change
-* 22:Pipe2 Plane1 Allow Pstate Change
-* 23:Pipe3 Plane1 Allow Pstate Change
-* 24:Pipe0 cursor0 Allow Pstate Change
-* 25:Pipe1 cursor0 Allow Pstate Change
-* 26:Pipe2 cursor0 Allow Pstate Change
-* 27:Pipe3 cursor0 Allow Pstate Change
-* 28:WB0 Allow Pstate Change
-* 29:WB1 Allow Pstate Change
-* 30:Arbiter's allow_pstate_change
 * 31:SOC pstate change request
 */
 
-- 
2.17.1

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[PATCH 05/33] drm/amd/display: Do not set optimized_require to false after plane disable

[Bhawanpreet Lakha]

From: Sung Lee 

[WHY]
The optimized_require flag is needed to set watermarks and clocks lower
in certain conditions. This flag is set to true and then set to false
while programming front end in dcn20.

[HOW]
Do not set the flag to false while disabling plane.

Signed-off-by: Sung Lee 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index cfbbaffa8654..a444fed94184 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -572,7 +572,6 @@ void dcn20_plane_atomic_disable(struct dc *dc, struct 
pipe_ctx *pipe_ctx)
dpp->funcs->dpp_dppclk_control(dpp, false, false);
 
hubp->power_gated = true;
-   dc->optimized_required = false; /* We're powering off, no need to 
optimize */
 
hws->funcs.plane_atomic_power_down(dc,
pipe_ctx->plane_res.dpp,
-- 
2.17.1

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[PATCH 04/33] drm/amd/display: Fix psr static frames calculation

[Bhawanpreet Lakha]

From: Roman Li 

[Why]
Driver crash with psr feature enabled due to divide-by-zero error.
This is a regression after rework to calculate static screen frame
number entry time.

[How]
Correct order of operations to avoid divide-by-zero.

Signed-off-by: Roman Li 
Reviewed-by: Zhan Liu 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7f6d3b0f9efc..6786d34f7d04 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8497,7 +8497,6 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
/* Calculate number of static frames before generating interrupt to
 * enter PSR.
 */
-   unsigned int frame_time_microsec = 100 / vsync_rate_hz;
// Init fail safe of 2 frames static
unsigned int num_frames_static = 2;
 
@@ -8512,8 +8511,10 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
 * Calculate number of frames such that at least 30 ms of time has
 * passed.
 */
-   if (vsync_rate_hz != 0)
+   if (vsync_rate_hz != 0) {
+   unsigned int frame_time_microsec = 100 / vsync_rate_hz;
num_frames_static = (3 / frame_time_microsec) + 1;
+   }
 
params.triggers.cursor_update = true;
params.triggers.overlay_update = true;
-- 
2.17.1

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[PATCH 29/33] drm/amd/display: external monitor abm enabled in modern standby

[Bhawanpreet Lakha]

From: Jing Zhou 

[why]
Resume from modern standby, edp stream disabled
but abm keep enabled. External monitor select OTG
source 0 which ABM enabled.
[how]
Disable abm before disable crtc when reset path
mode not call core link disable stream.

Signed-off-by: Jing Zhou 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 4 
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7fc559acffcd..0225f8d8bb82 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -901,6 +901,10 @@ static void dcn10_reset_back_end_for_pipe(
 * parent pipe.
 */
if (pipe_ctx->top_pipe == NULL) {
+
+   if (pipe_ctx->stream_res.abm)
+   
pipe_ctx->stream_res.abm->funcs->set_abm_immediate_disable(pipe_ctx->stream_res.abm);
+

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, 
false);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 52ef4d333112..b9ec40a31f5c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2011,6 +2011,10 @@ static void dcn20_reset_back_end_for_pipe(
 * parent pipe.
 */
if (pipe_ctx->top_pipe == NULL) {
+
+   if (pipe_ctx->stream_res.abm)
+   
pipe_ctx->stream_res.abm->funcs->set_abm_immediate_disable(pipe_ctx->stream_res.abm);
+

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, 
false);
-- 
2.17.1

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[PATCH 10/33] drm/amd/display: Wait for clean shutdown in DMCUB reset

[Bhawanpreet Lakha]

From: Nicholas Kazlauskas 

[Why]
The DMCUB may be currently executing commands when the reset is
triggered.

Before issuing a reset we should first wait for the DMCUB to finish
its work.

[How]
Send the GPINT command for halting the firmware before reset.

Get the ack for the command then wait for the scratch register to
become the correct value.

We want this to take under ~40us or so at most before we force reset
to cover PHY delay sequence max time.

Each register read will be at least ~1-3us so don't bother using udelay.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dmub/inc/dmub_gpint_cmd.h |  6 
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 36 +++
 2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h
index 5398ed6b35d1..e13685917dab 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_gpint_cmd.h
@@ -65,4 +65,10 @@ enum dmub_gpint_command {
DMUB_GPINT__STOP_FW = 2,
 };
 
+/**
+ * Command responses.
+ */
+
+#define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
+
 #endif /* _DMUB_GPINT_CMD_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 7c1604c2221c..479f17bb3800 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -77,6 +77,42 @@ static inline void dmub_dcn20_translate_addr(const union 
dmub_addr *addr_in,
 
 void dmub_dcn20_reset(struct dmub_srv *dmub)
 {
+   union dmub_gpint_data_register cmd;
+   const uint32_t timeout = 30;
+   uint32_t in_reset, scratch, i;
+
+   REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, _reset);
+
+   if (in_reset == 0) {
+   cmd.bits.status = 1;
+   cmd.bits.command_code = DMUB_GPINT__STOP_FW;
+   cmd.bits.param = 0;
+
+   dmub->hw_funcs.set_gpint(dmub, cmd);
+
+   /**
+* Timeout covers both the ACK and the wait
+* for remaining work to finish.
+*
+* This is mostly bound by the PHY disable sequence.
+* Each register check will be greater than 1us, so
+* don't bother using udelay.
+*/
+
+   for (i = 0; i < timeout; ++i) {
+   if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
+   break;
+   }
+
+   for (i = 0; i < timeout; ++i) {
+   scratch = dmub->hw_funcs.get_gpint_response(dmub);
+   if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
+   break;
+   }
+
+   /* Force reset in case we timed out, DMCUB is likely hung. */
+   }
+
REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
-- 
2.17.1

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[PATCH 21/33] drm/amd/display: decouple global lock out of pipe control lock

[Bhawanpreet Lakha]

From: Wenjing Liu 

[why]
hwss should not guess what type of pipe lock is needed.
The caller of the lock function should know
the right type of pipe lock.
Decouple the setup of global lock outside of pipe control lock
logic.

Signed-off-by: Wenjing Liu 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 20 ++
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 27 ---
 2 files changed, 20 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7fdd82b7708a..40878b86a05d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2220,6 +2220,11 @@ static void commit_planes_for_stream(struct dc *dc,
}
}
 
+   if ((update_type != UPDATE_TYPE_FAST) && 
stream->update_flags.bits.dsc_changed)
+   if 
(top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable)
+   
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
+   top_pipe_to_program->stream_res.tg);
+
if ((update_type != UPDATE_TYPE_FAST) && 
dc->hwss.interdependent_update_lock)
dc->hwss.interdependent_update_lock(dc, context, true);
else
@@ -2377,6 +2382,21 @@ static void commit_planes_for_stream(struct dc *dc,
else
dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
 
+   if ((update_type != UPDATE_TYPE_FAST) && 
stream->update_flags.bits.dsc_changed)
+   if 
(top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
+   
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
+   top_pipe_to_program->stream_res.tg,
+   CRTC_STATE_VACTIVE);
+   
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
+   top_pipe_to_program->stream_res.tg,
+   CRTC_STATE_VBLANK);
+   
top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
+   top_pipe_to_program->stream_res.tg,
+   CRTC_STATE_VACTIVE);
+   
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
+   top_pipe_to_program->stream_res.tg);
+   }
+
if (update_type != UPDATE_TYPE_FAST)
dc->hwss.post_unlock_program_front_end(dc, context);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 9713f452debf..52ef4d333112 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1094,7 +1094,6 @@ void dcn20_pipe_control_lock(
bool lock)
 {
bool flip_immediate = false;
-   bool dig_update_required = false;
 
/* use TG master update lock to lock everything on the TG
 * therefore only top pipe need to lock
@@ -1132,19 +1131,6 @@ void dcn20_pipe_control_lock(
(!flip_immediate && pipe->stream_res.gsl_group > 0))
dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
 
-   if (pipe->stream && pipe->stream->update_flags.bits.dsc_changed)
-   dig_update_required = true;
-
-   /* Need double buffer lock mode in order to synchronize front end pipe
-* updates with dig updates.
-*/
-   if (dig_update_required) {
-   if (lock) {
-   pipe->stream_res.tg->funcs->lock_doublebuffer_enable(
-   pipe->stream_res.tg);
-   }
-   }
-
if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) 
{
if (lock)

pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
@@ -1156,19 +1142,6 @@ void dcn20_pipe_control_lock(
else
pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
}
-
-   if (dig_update_required) {
-   if (!lock) {
-   
pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
-   CRTC_STATE_VACTIVE);
-   
pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
-   CRTC_STATE_VBLANK);
-   
pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
-   CRTC_STATE_VACTIVE);
-   pipe->stream_res.tg->funcs->lock_doublebuffer_disable(
-   pipe->stream_res.tg);
-   }
-   }
 }
 
 static void 

[PATCH 02/33] drm/amd/display: Move USB-C workaround to after parameter variables are set

[Bhawanpreet Lakha]

From: George Shen 

[Why]
The call to dp_enable_link_phy are using default/invalid values for clock id
and link settings.

[How]
Move workaround code to after its parameter variables are determined.

Signed-off-by: George Shen 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index cb731c1d30b1..8ff0f5b7104b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1892,6 +1892,16 @@ bool dp_verify_link_cap(
/* disable PHY done possible by BIOS, will be done by driver itself */
dp_disable_link_phy(link, link->connector_signal);
 
+   dp_cs_id = get_clock_source_id(link);
+
+   /* link training starts with the maximum common settings
+* supported by both sink and ASIC.
+*/
+   initial_link_settings = get_common_supported_link_settings(
+   *known_limit_link_setting,
+   max_link_cap);
+   cur_link_setting = initial_link_settings;
+
/* Temporary Renoir-specific workaround for SWDEV-215184;
 * PHY will sometimes be in bad state on hotplugging display from 
certain USB-C dongle,
 * so add extra cycle of enabling and disabling the PHY before first 
link training.
@@ -1902,15 +1912,6 @@ bool dp_verify_link_cap(
dp_disable_link_phy(link, link->connector_signal);
}
 
-   dp_cs_id = get_clock_source_id(link);
-
-   /* link training starts with the maximum common settings
-* supported by both sink and ASIC.
-*/
-   initial_link_settings = get_common_supported_link_settings(
-   *known_limit_link_setting,
-   max_link_cap);
-   cur_link_setting = initial_link_settings;
do {
skip_video_pattern = true;
 
-- 
2.17.1

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[PATCH 12/33] drm/amd/display: Fix GSL acquire

[Bhawanpreet Lakha]

From: Aric Cyr 

[Why]
After locking refactor GSL is not acquired properly
resulting in immediate flip issues.

[How]
Do not copy old GSL state anymore since GSL is acquired
earlier now.

Signed-off-by: Aric Cyr 
Reviewed-by: Anthony Koo 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 129a91e8f250..9713f452debf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1562,12 +1562,6 @@ void dcn20_program_front_end_for_ctx(
}
}
 
-   /* Carry over GSL groups in case the context is changing. */
-   for (i = 0; i < dc->res_pool->pipe_count; i++)
-   if (context->res_ctx.pipe_ctx[i].stream == 
dc->current_state->res_ctx.pipe_ctx[i].stream)
-   context->res_ctx.pipe_ctx[i].stream_res.gsl_group =
-   
dc->current_state->res_ctx.pipe_ctx[i].stream_res.gsl_group;
-
/* Set pipe update flags and lock pipes */
for (i = 0; i < dc->res_pool->pipe_count; i++)

dcn20_detect_pipe_changes(>current_state->res_ctx.pipe_ctx[i],
-- 
2.17.1

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[PATCH 13/33] drm/amd/display: remove unused variable

[Bhawanpreet Lakha]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index e8d126890d7e..d00b72df469a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -682,7 +682,6 @@ struct dc_3dlut {
struct kref refcount;
struct tetrahedral_params lut_3d;
struct fixed31_32 hdr_multiplier;
-   bool initialized; /*remove after diag fix*/
union dc_3dlut_state state;
struct dc_context *ctx;
 };
-- 
2.17.1

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[PATCH 15/33] drm/amd/display: dc_get_vmid_use_vector() crashes when get called

[Bhawanpreet Lakha]

From: Peikang Zhang 

[Why]
int i can go out of boundary which will cause crash

[How]
Fixed the maximum value of i to avoid i going out of boundary

Signed-off-by: Peikang Zhang 
Reviewed-by: Jun Lei 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
index a96d8de9380e..f2b39ec35c89 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
@@ -62,7 +62,7 @@ int dc_get_vmid_use_vector(struct dc *dc)
int i;
int in_use = 0;
 
-   for (i = 0; i < dc->vm_helper->num_vmid; i++)
+   for (i = 0; i < MAX_HUBP; i++)
in_use |= dc->vm_helper->hubp_vmid_usage[i].vmid_usage[0]
| dc->vm_helper->hubp_vmid_usage[i].vmid_usage[1];
return in_use;
-- 
2.17.1

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[PATCH 01/33] drm/amd/display: Add set psr version message

[Bhawanpreet Lakha]

From: Wyatt Wood 

[Why]
Must know psr version during runtime.

[How]
Add set psr version message structures.

Signed-off-by: Wyatt Wood 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  6 +-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 62 +--
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  9 +--
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 10 +--
 .../drm/amd/display/dmub/inc/dmub_cmd_dal.h   |  4 +-
 5 files changed, 57 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a09119c10d7c..41184e593f85 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2401,7 +2401,7 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, 
bool allow_active, bool
struct dmub_psr *psr = dc->res_pool->psr;
 
if ((psr != NULL) && link->psr_feature_enabled)
-   psr->funcs->set_psr_enable(psr, allow_active);
+   psr->funcs->psr_enable(psr, allow_active);
else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && 
link->psr_feature_enabled)
dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
 
@@ -2417,7 +2417,7 @@ bool dc_link_get_psr_state(const struct dc_link *link, 
uint32_t *psr_state)
struct dmub_psr *psr = dc->res_pool->psr;
 
if (psr != NULL && link->psr_feature_enabled)
-   psr->funcs->get_psr_state(psr_state);
+   psr->funcs->psr_get_state(psr_state);
else if (dmcu != NULL && link->psr_feature_enabled)
dmcu->funcs->get_psr_state(dmcu, psr_state);
 
@@ -2589,7 +2589,7 @@ bool dc_link_setup_psr(struct dc_link *link,
psr_context->frame_delay = 0;
 
if (psr)
-   link->psr_feature_enabled = psr->funcs->setup_psr(psr, link, 
psr_context);
+   link->psr_feature_enabled = psr->funcs->psr_copy_settings(psr, 
link, psr_context);
else
link->psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, 
psr_context);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 225955ec6d39..bdf80b09277e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -36,16 +36,39 @@
 /**
  * Get PSR state from firmware.
  */
-static void dmub_get_psr_state(uint32_t *psr_state)
+static void dmub_psr_get_state(uint32_t *psr_state)
 {
// Not yet implemented
// Trigger GPINT interrupt from firmware
 }
 
+static void dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state 
*stream)
+{
+   //stream->psr_version;
+   union dmub_rb_cmd cmd;
+   struct dc_context *dc = dmub->ctx;
+
+   cmd.psr_set_version.header.type = DMUB_CMD__PSR;
+   cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION;
+
+   if (stream->psr_version == 0x0)
+   return;
+   else if (stream->psr_version == 0x1)
+   cmd.psr_set_version.psr_set_version_data.version = 
PSR_VERSION_1;
+   else if (stream->psr_version == 0x2)
+   cmd.psr_set_version.psr_set_version_data.version = 
PSR_VERSION_2;
+
+   cmd.psr_enable.header.payload_bytes = sizeof(struct 
dmub_cmd_psr_set_version_data);
+
+   dc_dmub_srv_cmd_queue(dc->dmub_srv, _enable.header);
+   dc_dmub_srv_cmd_execute(dc->dmub_srv);
+   dc_dmub_srv_wait_idle(dc->dmub_srv);
+}
+
 /**
  * Enable/Disable PSR.
  */
-static void dmub_set_psr_enable(struct dmub_psr *dmub, bool enable)
+static void dmub_psr_enable(struct dmub_psr *dmub, bool enable)
 {
union dmub_rb_cmd cmd;
struct dc_context *dc = dmub->ctx;
@@ -67,13 +90,13 @@ static void dmub_set_psr_enable(struct dmub_psr *dmub, bool 
enable)
 /**
  * Set PSR level.
  */
-static void dmub_set_psr_level(struct dmub_psr *dmub, uint16_t psr_level)
+static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level)
 {
union dmub_rb_cmd cmd;
uint32_t psr_state = 0;
struct dc_context *dc = dmub->ctx;
 
-   dmub_get_psr_state(_state);
+   dmub_psr_get_state(_state);
 
if (psr_state == 0)
return;
@@ -91,7 +114,7 @@ static void dmub_set_psr_level(struct dmub_psr *dmub, 
uint16_t psr_level)
 /**
  * Setup PSR by programming phy registers and sending psr hw context values to 
firmware.
  */
-static bool dmub_setup_psr(struct dmub_psr *dmub,
+static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
struct dc_link *link,
struct psr_context *psr_context)
 {
@@ -104,18 +127,16 @@ static bool dmub_setup_psr(struct dmub_psr *dmub,
 
for (int i = 0; i < MAX_PIPES; i++) {
if (res_ctx &&
-   res_ctx->pipe_ctx[i].stream &&
-   

Re: Asking for Direction

[Josh Fuhs]

Thanks. I can confirm kernel 5.5rc7 improves things significantly. I'll post 
this to the various channels I've asked in.

Josh

‐‐‐ Original Message ‐‐‐
On Friday, January 31, 2020 2:05 PM, Deucher, Alexander 
 wrote:

> [AMD Official Use Only - Internal Distribution Only]
>
> Please make sure your kernel has this patch:
>
> commit 46203a508f64b4bfa150a9d25eab1dc891e7e650
> Author: Alex Deucher 
> Date:   Tue Oct 29 17:14:15 2019 -0400
>
> drm/amdgpu/gmc10: properly set BANK_SELECT and FRAGMENT_SIZE
>
> These were not aligned for optimal performance for GPUVM.
>
> Acked-by: Christian König 
> Reviewed-by: Tianci Yin 
> Signed-off-by: Alex Deucher 
>
> Alex
>
> ---
>
> From: amd-gfx  on behalf of Josh Fuhs 
> 
> Sent: Friday, January 31, 2020 12:48 PM
> To: amd-gfx@lists.freedesktop.org 
> Subject: Asking for Direction
>
> Hi all,
>
> I am trying to use a Radeon RX 5700XT via OpenCL with kernel 5.3.0 (I have 
> also tried kernel 5.3.18) on Ubuntu 18.04. I have noticed that this 
> combination is much slower than expected. I'm trying to find out why, and how 
> to fix it.
>
> If I'm in the wrong place to ask, would you be able to point me in the right 
> direction?
>
> If this is a known outstanding problem, a reference to a bug or something 
> else that would let me dig into it would be great.
>
> Thanks
>
> Josh Fuhs___
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Re: [PATCH V5] drm: Add support for DP 1.4 Compliance edid corruption test

[Harry Wentland]

On 2020-01-31 3:24 p.m., Jerry (Fangzhi) Zuo wrote:
> Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
> real CRC value of the last edid data block, and write it back.
> Current edid CRC calculates routine adds the last CRC byte,
> and check if non-zero.
> 
> This behavior is not accurate; actually, we need to return
> the actual CRC value when corruption is detected.
> This commit changes this issue by returning the calculated CRC,
> and initiate the required sequence.
> 
> Change since v5
> - Obtain real CRC value before dumping bad edid
> 
> Change since v4
> - Fix for CI.CHECKPATCH
> 
> Change since v3
> - Fix a minor typo.
> 
> Change since v2
> - Rewrite checksum computation routine to avoid duplicated code.
> - Rename to avoid confusion.
> 
> Change since v1
> - Have separate routine for returning real CRC.
> 
> Signed-off-by: Jerry (Fangzhi) Zuo 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/drm_dp_helper.c | 35 +
>  drivers/gpu/drm/drm_edid.c  | 23 ++
>  include/drm/drm_connector.h |  6 ++
>  include/drm/drm_dp_helper.h |  3 +++
>  4 files changed, 63 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index f629fc5494a4..18b285fa1a42 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -351,6 +351,41 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
>  }
>  EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
>  
> +/**
> + * drm_dp_send_real_edid_checksum() - send back real edid checksum value
> + * @aux: DisplayPort AUX channel
> + * @real_edid_checksum: real edid checksum for the last block
> + *
> + * Returns true on success
> + */
> +bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
> +u8 real_edid_checksum)
> +{
> + u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
> +
> + drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, _test_req, 1);
> + auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
> +
> + drm_dp_dpcd_read(aux, DP_TEST_REQUEST, _edid_read, 1);
> + link_edid_read &= DP_TEST_LINK_EDID_READ;
> +
> + if (!auto_test_req || !link_edid_read) {
> + DRM_DEBUG_KMS("Source DUT does not support TEST_EDID_READ\n");
> + return false;
> + }
> +
> + drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, _test_req, 1);
> +
> + /* send back checksum for the last edid extension block data */
> + drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, _edid_checksum, 1);
> +
> + test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
> + drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, _resp, 1);
> +
> + return true;
> +}
> +EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
> +
>  /**
>   * drm_dp_downstream_max_clock() - extract branch device max
>   * pixel rate for legacy VGA
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 99769d6c9f84..f064e75fb4c5 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -1590,11 +1590,22 @@ static int validate_displayid(u8 *displayid, int 
> length, int idx);
>  static int drm_edid_block_checksum(const u8 *raw_edid)
>  {
>   int i;
> - u8 csum = 0;
> - for (i = 0; i < EDID_LENGTH; i++)
> + u8 csum = 0, crc = 0;
> +
> + for (i = 0; i < EDID_LENGTH - 1; i++)
>   csum += raw_edid[i];
>  
> - return csum;
> + crc = 0x100 - csum;
> +
> + return crc;
> +}
> +
> +static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 
> real_checksum)
> +{
> + if (raw_edid[EDID_LENGTH - 1] != real_checksum)
> + return true;
> + else
> + return false;
>  }
>  
>  static bool drm_edid_is_zero(const u8 *in_edid, int length)
> @@ -1652,7 +1663,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool 
> print_bad_edid,
>   }
>  
>   csum = drm_edid_block_checksum(raw_edid);
> - if (csum) {
> + if (drm_edid_block_checksum_diff(raw_edid, csum)) {
>   if (edid_corrupt)
>   *edid_corrupt = true;
>  
> @@ -1793,6 +1804,10 @@ static void connector_bad_edid(struct drm_connector 
> *connector,
>  u8 *edid, int num_blocks)
>  {
>   int i;
> + u8 num_of_ext = edid[0x7e];
> +
> + /* Calculate real checksum for the last edid extension block data */
> + connector->real_edid_checksum = drm_edid_block_checksum(edid + 
> num_of_ext * EDID_LENGTH);
>  
>   if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
>   return;
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 2113500b4075..b3815371c271 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -1357,6 +1357,12 @@ struct drm_connector {
>* rev1.1 4.2.2.6
>*/
>   bool edid_corrupt;
> + 

[PATCH V5] drm: Add support for DP 1.4 Compliance edid corruption test

[Jerry (Fangzhi) Zuo]

Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
real CRC value of the last edid data block, and write it back.
Current edid CRC calculates routine adds the last CRC byte,
and check if non-zero.

This behavior is not accurate; actually, we need to return
the actual CRC value when corruption is detected.
This commit changes this issue by returning the calculated CRC,
and initiate the required sequence.

Change since v5
- Obtain real CRC value before dumping bad edid

Change since v4
- Fix for CI.CHECKPATCH

Change since v3
- Fix a minor typo.

Change since v2
- Rewrite checksum computation routine to avoid duplicated code.
- Rename to avoid confusion.

Change since v1
- Have separate routine for returning real CRC.

Signed-off-by: Jerry (Fangzhi) Zuo 
---
 drivers/gpu/drm/drm_dp_helper.c | 35 +
 drivers/gpu/drm/drm_edid.c  | 23 ++
 include/drm/drm_connector.h |  6 ++
 include/drm/drm_dp_helper.h |  3 +++
 4 files changed, 63 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f629fc5494a4..18b285fa1a42 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -351,6 +351,41 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
 }
 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
 
+/**
+ * drm_dp_send_real_edid_checksum() - send back real edid checksum value
+ * @aux: DisplayPort AUX channel
+ * @real_edid_checksum: real edid checksum for the last block
+ *
+ * Returns true on success
+ */
+bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
+u8 real_edid_checksum)
+{
+   u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
+
+   drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, _test_req, 1);
+   auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
+
+   drm_dp_dpcd_read(aux, DP_TEST_REQUEST, _edid_read, 1);
+   link_edid_read &= DP_TEST_LINK_EDID_READ;
+
+   if (!auto_test_req || !link_edid_read) {
+   DRM_DEBUG_KMS("Source DUT does not support TEST_EDID_READ\n");
+   return false;
+   }
+
+   drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, _test_req, 1);
+
+   /* send back checksum for the last edid extension block data */
+   drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, _edid_checksum, 1);
+
+   test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
+   drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, _resp, 1);
+
+   return true;
+}
+EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
+
 /**
  * drm_dp_downstream_max_clock() - extract branch device max
  * pixel rate for legacy VGA
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 99769d6c9f84..f064e75fb4c5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1590,11 +1590,22 @@ static int validate_displayid(u8 *displayid, int 
length, int idx);
 static int drm_edid_block_checksum(const u8 *raw_edid)
 {
int i;
-   u8 csum = 0;
-   for (i = 0; i < EDID_LENGTH; i++)
+   u8 csum = 0, crc = 0;
+
+   for (i = 0; i < EDID_LENGTH - 1; i++)
csum += raw_edid[i];
 
-   return csum;
+   crc = 0x100 - csum;
+
+   return crc;
+}
+
+static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
+{
+   if (raw_edid[EDID_LENGTH - 1] != real_checksum)
+   return true;
+   else
+   return false;
 }
 
 static bool drm_edid_is_zero(const u8 *in_edid, int length)
@@ -1652,7 +1663,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool 
print_bad_edid,
}
 
csum = drm_edid_block_checksum(raw_edid);
-   if (csum) {
+   if (drm_edid_block_checksum_diff(raw_edid, csum)) {
if (edid_corrupt)
*edid_corrupt = true;
 
@@ -1793,6 +1804,10 @@ static void connector_bad_edid(struct drm_connector 
*connector,
   u8 *edid, int num_blocks)
 {
int i;
+   u8 num_of_ext = edid[0x7e];
+
+   /* Calculate real checksum for the last edid extension block data */
+   connector->real_edid_checksum = drm_edid_block_checksum(edid + 
num_of_ext * EDID_LENGTH);
 
if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
return;
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 2113500b4075..b3815371c271 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1357,6 +1357,12 @@ struct drm_connector {
 * rev1.1 4.2.2.6
 */
bool edid_corrupt;
+   /**
+* @real_edid_checksum: real edid checksum for corrupted edid block.
+* Required in Displayport 1.4 compliance testing
+* rev1.1 4.2.2.6
+*/
+   u8 real_edid_checksum;
 
/** @debugfs_entry: debugfs directory for this connector */

Re: [PATCH v2] drm/amdkfd: Add queue information to sysfs

[Felix Kuehling]

On 2020-01-31 1:47 p.m., Lin, Amber wrote:

[AMD Official Use Only - Internal Distribution Only]

It doesn't apply to this one because
1. It only has one set of attribute (dma32 or highmem) using the kobj_type, so it can set 
the default_attrs. In my case, I have multiple queues/QIDs that share the same kobj_type 
while each of them has their own attrs located in "struct queue". I can't 
assign default_attrs to a specific one like ttm_memory.c does in the global section.


That's because you use container_of to find the queue that the 
attributes belong to. Instead you could use container_of to find the 
queue that the kobj belongs to. So instead of dynamically allocating the 
kobj, it would be a member of queue. Then you could use the default_attrs.


Regards,
  Felix



2. I also looked into kobj_attribute see if I can simply use sysfs_create_group 
(instead of sysfs_create_file three times) like how KFD implements DF and 
topology perf. The challenge is it needs a pre-declared attrs set but in my 
case, queues are created dynamically so I can't pre-declare them unless I can 
predict the number of queues. Attr sets for DF and perf are both a fixed 
number. They both declare the attr sets in global data before the function 
calls sysfs_create_group while I can't do that in this case due to queues are 
dynamically generated.

Thanks for the two inline comments. I'll fix them and submit again.

Regards,
Amber

-Original Message-
From: Kuehling, Felix 
Sent: Friday, January 31, 2020 12:06 PM
To: Lin, Amber ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/amdkfd: Add queue information to sysfs

You could save yourself the trouble of manually adding and removed individual 
sysfs files by setting the default_attrs in the kobj_type.
See ttm_memory.c for an example how this is done.

More comments inline.

On 2020-01-31 8:45 a.m., Amber Lin wrote:

Provide compute queues information in sysfs under /sys/class/kfd/kfd/proc.
The format is /sys/class/kfd/kfd/proc//queues//XX where
XX are size, type, and gpuid three files to represent queue size,
queue type, and the GPU this queue uses.  folder and files
underneath are generated when a queue is created. They are removed
when the queue is destroyed.

Signed-off-by: Amber Lin 
---
   drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  9 ++
   drivers/gpu/drm/amd/amdkfd/kfd_process.c   | 96 
++
   .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  2 +
   3 files changed, 107 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index c0b0def..cb2d2d7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -503,6 +503,12 @@ struct queue {
struct kfd_process  *process;
struct kfd_dev  *device;
void *gws;
+
+   /* procfs */
+   struct kobject *kobj_qid;
+   struct attribute attr_size;
+   struct attribute attr_type;
+   struct attribute attr_gpuid;
   };
   
   /*

@@ -730,6 +736,7 @@ struct kfd_process {
   
   	/* Kobj for our procfs */

struct kobject *kobj;
+   struct kobject *kobj_queues;
struct attribute attr_pasid;
   };
   
@@ -836,6 +843,8 @@ extern struct device *kfd_device;

   /* KFD's procfs */
   void kfd_procfs_init(void);
   void kfd_procfs_shutdown(void);
+int kfd_procfs_add_queue(struct queue *q); void
+kfd_procfs_del_queue(struct queue *q);
   
   /* Topology */

   int kfd_topology_init(void);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 25b90f7..78ca037 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -132,6 +132,94 @@ void kfd_procfs_shutdown(void)
}
   }
   
+static int kfd_procfs_add_file(const char *name, struct kobject *kobj,

+  struct attribute *attr)
+{
+   int ret;
+
+   attr->name = name;
+   attr->mode = KFD_SYSFS_FILE_MODE;
+   sysfs_attr_init(attr);
+   ret = sysfs_create_file(kobj, attr);
+   if (ret)
+   pr_warn("Creating %s file failed", name);
+   return ret;
+}
+
+static ssize_t kfd_procfs_queue_show(struct kobject *kobj,
+struct attribute *attr, char *buffer) {
+   if (!strcmp(attr->name, "size")) {
+   struct queue *q = container_of(attr, struct queue, attr_size);
+   return snprintf(buffer, PAGE_SIZE, "%llu",
+   q->properties.queue_size);
+   } else if (!strcmp(attr->name, "type")) {
+   struct queue *q = container_of(attr, struct queue, attr_type);
+   return snprintf(buffer, PAGE_SIZE, "%d", q->properties.type);
+   } else if (!strcmp(attr->name, "gpuid")) {
+   struct queue *q = container_of(attr, struct queue, attr_gpuid);
+   return snprintf(buffer, PAGE_SIZE, "%u", 

Re: Asking for Direction

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Please make sure your kernel has this patch:

commit 46203a508f64b4bfa150a9d25eab1dc891e7e650
Author: Alex Deucher 
Date:   Tue Oct 29 17:14:15 2019 -0400

drm/amdgpu/gmc10: properly set BANK_SELECT and FRAGMENT_SIZE

These were not aligned for optimal performance for GPUVM.

Acked-by: Christian König 
Reviewed-by: Tianci Yin 
Signed-off-by: Alex Deucher 

Alex

From: amd-gfx  on behalf of Josh Fuhs 

Sent: Friday, January 31, 2020 12:48 PM
To: amd-gfx@lists.freedesktop.org 
Subject: Asking for Direction

Hi all,

I am trying to use a Radeon RX 5700XT via OpenCL with kernel 5.3.0 (I have also 
tried kernel 5.3.18) on Ubuntu 18.04. I have noticed that this combination is 
much slower than expected. I'm trying to find out why, and how to fix it.

If I'm in the wrong place to ask, would you be able to point me in the right 
direction?



If this is a known outstanding problem, a reference to a bug or something else 
that would let me dig into it would be great.

Thanks

Josh Fuhs
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RE: [PATCH v2] drm/amdkfd: Add queue information to sysfs

[Lin, Amber]

[AMD Official Use Only - Internal Distribution Only]

It doesn't apply to this one because
1. It only has one set of attribute (dma32 or highmem) using the kobj_type, so 
it can set the default_attrs. In my case, I have multiple queues/QIDs that 
share the same kobj_type while each of them has their own attrs located in 
"struct queue". I can't assign default_attrs to a specific one like 
ttm_memory.c does in the global section.
2. I also looked into kobj_attribute see if I can simply use sysfs_create_group 
(instead of sysfs_create_file three times) like how KFD implements DF and 
topology perf. The challenge is it needs a pre-declared attrs set but in my 
case, queues are created dynamically so I can't pre-declare them unless I can 
predict the number of queues. Attr sets for DF and perf are both a fixed 
number. They both declare the attr sets in global data before the function 
calls sysfs_create_group while I can't do that in this case due to queues are 
dynamically generated.

Thanks for the two inline comments. I'll fix them and submit again.

Regards,
Amber

-Original Message-
From: Kuehling, Felix  
Sent: Friday, January 31, 2020 12:06 PM
To: Lin, Amber ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/amdkfd: Add queue information to sysfs

You could save yourself the trouble of manually adding and removed individual 
sysfs files by setting the default_attrs in the kobj_type. 
See ttm_memory.c for an example how this is done.

More comments inline.

On 2020-01-31 8:45 a.m., Amber Lin wrote:
> Provide compute queues information in sysfs under /sys/class/kfd/kfd/proc.
> The format is /sys/class/kfd/kfd/proc//queues//XX where 
> XX are size, type, and gpuid three files to represent queue size, 
> queue type, and the GPU this queue uses.  folder and files 
> underneath are generated when a queue is created. They are removed 
> when the queue is destroyed.
>
> Signed-off-by: Amber Lin 
> ---
>   drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  9 ++
>   drivers/gpu/drm/amd/amdkfd/kfd_process.c   | 96 
> ++
>   .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  2 +
>   3 files changed, 107 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
> b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> index c0b0def..cb2d2d7 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> @@ -503,6 +503,12 @@ struct queue {
>   struct kfd_process  *process;
>   struct kfd_dev  *device;
>   void *gws;
> +
> + /* procfs */
> + struct kobject *kobj_qid;
> + struct attribute attr_size;
> + struct attribute attr_type;
> + struct attribute attr_gpuid;
>   };
>   
>   /*
> @@ -730,6 +736,7 @@ struct kfd_process {
>   
>   /* Kobj for our procfs */
>   struct kobject *kobj;
> + struct kobject *kobj_queues;
>   struct attribute attr_pasid;
>   };
>   
> @@ -836,6 +843,8 @@ extern struct device *kfd_device;
>   /* KFD's procfs */
>   void kfd_procfs_init(void);
>   void kfd_procfs_shutdown(void);
> +int kfd_procfs_add_queue(struct queue *q); void 
> +kfd_procfs_del_queue(struct queue *q);
>   
>   /* Topology */
>   int kfd_topology_init(void);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> index 25b90f7..78ca037 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -132,6 +132,94 @@ void kfd_procfs_shutdown(void)
>   }
>   }
>   
> +static int kfd_procfs_add_file(const char *name, struct kobject *kobj,
> +struct attribute *attr)
> +{
> + int ret;
> +
> + attr->name = name;
> + attr->mode = KFD_SYSFS_FILE_MODE;
> + sysfs_attr_init(attr);
> + ret = sysfs_create_file(kobj, attr);
> + if (ret)
> + pr_warn("Creating %s file failed", name);
> + return ret;
> +}
> +
> +static ssize_t kfd_procfs_queue_show(struct kobject *kobj,
> +  struct attribute *attr, char *buffer) {
> + if (!strcmp(attr->name, "size")) {
> + struct queue *q = container_of(attr, struct queue, attr_size);
> + return snprintf(buffer, PAGE_SIZE, "%llu",
> + q->properties.queue_size);
> + } else if (!strcmp(attr->name, "type")) {
> + struct queue *q = container_of(attr, struct queue, attr_type);
> + return snprintf(buffer, PAGE_SIZE, "%d", q->properties.type);
> + } else if (!strcmp(attr->name, "gpuid")) {
> + struct queue *q = container_of(attr, struct queue, attr_gpuid);
> + return snprintf(buffer, PAGE_SIZE, "%u", q->device->id);
> + } else
> + pr_err("Invalid attribute");
> +
> + return 0;
> +}
> +
> +static const struct sysfs_ops procfs_queue_ops = {
> + .show = kfd_procfs_queue_show,
> +};
> +
> +static struct kobj_type procfs_queue_type = {
> + 

Asking for Direction

[Josh Fuhs]

Hi all,

I am trying to use a Radeon RX 5700XT via OpenCL with kernel 5.3.0 (I have also 
tried kernel 5.3.18) on Ubuntu 18.04. I have noticed that this combination is 
much slower than expected. I'm trying to find out why, and how to fix it.

If I'm in the wrong place to ask, would you be able to point me in the right 
direction?

If this is a known outstanding problem, a reference to a bug or something else 
that would let me dig into it would be great.

Thanks

Josh Fuhs___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2] drm/amdkfd: Add queue information to sysfs

[Felix Kuehling]

You could save yourself the trouble of manually adding and removed 
individual sysfs files by setting the default_attrs in the kobj_type. 
See ttm_memory.c for an example how this is done.


More comments inline.

On 2020-01-31 8:45 a.m., Amber Lin wrote:

Provide compute queues information in sysfs under /sys/class/kfd/kfd/proc.
The format is /sys/class/kfd/kfd/proc//queues//XX where
XX are size, type, and gpuid three files to represent queue size, queue
type, and the GPU this queue uses.  folder and files underneath
are generated when a queue is created. They are removed when the queue is
destroyed.

Signed-off-by: Amber Lin 
---
  drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  9 ++
  drivers/gpu/drm/amd/amdkfd/kfd_process.c   | 96 ++
  .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  2 +
  3 files changed, 107 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index c0b0def..cb2d2d7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -503,6 +503,12 @@ struct queue {
struct kfd_process  *process;
struct kfd_dev  *device;
void *gws;
+
+   /* procfs */
+   struct kobject *kobj_qid;
+   struct attribute attr_size;
+   struct attribute attr_type;
+   struct attribute attr_gpuid;
  };
  
  /*

@@ -730,6 +736,7 @@ struct kfd_process {
  
  	/* Kobj for our procfs */

struct kobject *kobj;
+   struct kobject *kobj_queues;
struct attribute attr_pasid;
  };
  
@@ -836,6 +843,8 @@ extern struct device *kfd_device;

  /* KFD's procfs */
  void kfd_procfs_init(void);
  void kfd_procfs_shutdown(void);
+int kfd_procfs_add_queue(struct queue *q);
+void kfd_procfs_del_queue(struct queue *q);
  
  /* Topology */

  int kfd_topology_init(void);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 25b90f7..78ca037 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -132,6 +132,94 @@ void kfd_procfs_shutdown(void)
}
  }
  
+static int kfd_procfs_add_file(const char *name, struct kobject *kobj,

+  struct attribute *attr)
+{
+   int ret;
+
+   attr->name = name;
+   attr->mode = KFD_SYSFS_FILE_MODE;
+   sysfs_attr_init(attr);
+   ret = sysfs_create_file(kobj, attr);
+   if (ret)
+   pr_warn("Creating %s file failed", name);
+   return ret;
+}
+
+static ssize_t kfd_procfs_queue_show(struct kobject *kobj,
+struct attribute *attr, char *buffer)
+{
+   if (!strcmp(attr->name, "size")) {
+   struct queue *q = container_of(attr, struct queue, attr_size);
+   return snprintf(buffer, PAGE_SIZE, "%llu",
+   q->properties.queue_size);
+   } else if (!strcmp(attr->name, "type")) {
+   struct queue *q = container_of(attr, struct queue, attr_type);
+   return snprintf(buffer, PAGE_SIZE, "%d", q->properties.type);
+   } else if (!strcmp(attr->name, "gpuid")) {
+   struct queue *q = container_of(attr, struct queue, attr_gpuid);
+   return snprintf(buffer, PAGE_SIZE, "%u", q->device->id);
+   } else
+   pr_err("Invalid attribute");
+
+   return 0;
+}
+
+static const struct sysfs_ops procfs_queue_ops = {
+   .show = kfd_procfs_queue_show,
+};
+
+static struct kobj_type procfs_queue_type = {
+   .release = kfd_procfs_kobj_release,
+   .sysfs_ops = _queue_ops,
+};
+
+int kfd_procfs_add_queue(struct queue *q)
+{
+   struct kfd_process *proc;
+   int ret;
+
+   if (!q || !q->process)
+   return -EINVAL;
+   proc = q->process;
+
+   /* Create proc//queues/ folder*/
+   if (!proc->kobj_queues)
+   return -EFAULT;
+   if (q->kobj_qid)
+   return -EEXIST;
+   q->kobj_qid = kfd_alloc_struct(q->kobj_qid);
+   if (!q->kobj_qid)
+   return -ENOMEM;
+   ret = kobject_init_and_add(q->kobj_qid, _queue_type,
+   proc->kobj_queues, "%u", q->properties.queue_id);
+   if (ret < 0) {
+   pr_warn("Creating proc//queues/%u failed",
+   q->properties.queue_id);


After kobject_init_and_add fails, you must call kobject_put to avoid 
memory leaks.




+   return ret;
+   }
+
+   /* Create proc//queues//XX files */
+   kfd_procfs_add_file("size", q->kobj_qid, >attr_size);
+   kfd_procfs_add_file("type", q->kobj_qid, >attr_type);
+   kfd_procfs_add_file("gpuid", q->kobj_qid, >attr_gpuid);
+
+   return 0;
+}
+
+void kfd_procfs_del_queue(struct queue *q)
+{
+   if (!q || !q->process)
+   return;


You need to check q->obj_qid too, in case kfd_procfs_add_queue failed.

Regards,
  Felix


+
+   

RE: [PATCH] drm/amd/display: Fix a typo when computing dsc configuration

[Liu, Zhan]

> -Original Message-
> From: amd-gfx  On Behalf Of
> mikita.lip...@amd.com
> Sent: 2020/January/31, Friday 10:00 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Lipski, Mikita
> ; Wentland, Harry 
> Subject: [PATCH] drm/amd/display: Fix a typo when computing dsc
> configuration
> 
> From: Mikita Lipski 

Reviewed-by: Zhan Liu 

> 
> [why]
> Remove a backslash symbol accidentally left in increase bpp function when
> computing mst dsc configuration.
> 
> Signed-off-by: Mikita Lipski 
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git
> a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 96b391e4b3e7..5672f7765919 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -632,7 +632,7 @@ static void increase_dsc_bpp(struct
> drm_atomic_state *state,
>   if (drm_dp_atomic_find_vcpi_slots(state,
> 
> params[next_index].port->mgr,
> 
> params[next_index].port,
> -
> vars[next_index].pbn,\
> +
> vars[next_index].pbn,
> 
> dm_mst_get_pbn_divider(dc_link)) < 0)
>   return;
>   if (!drm_dp_mst_atomic_check(state)) {
> --
> 2.17.1
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org

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[PATCH] drm/amd/display: Fix a typo when computing dsc configuration

[mikita.lipski]

From: Mikita Lipski 

[why]
Remove a backslash symbol accidentally left in increase bpp function
when computing mst dsc configuration.

Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 96b391e4b3e7..5672f7765919 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -632,7 +632,7 @@ static void increase_dsc_bpp(struct drm_atomic_state *state,
if (drm_dp_atomic_find_vcpi_slots(state,
  
params[next_index].port->mgr,
  
params[next_index].port,
- vars[next_index].pbn,\
+ vars[next_index].pbn,
  
dm_mst_get_pbn_divider(dc_link)) < 0)
return;
if (!drm_dp_mst_atomic_check(state)) {
-- 
2.17.1

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[PATCH v2] drm/amdkfd: Add queue information to sysfs

[Amber Lin]

Provide compute queues information in sysfs under /sys/class/kfd/kfd/proc.
The format is /sys/class/kfd/kfd/proc//queues//XX where
XX are size, type, and gpuid three files to represent queue size, queue
type, and the GPU this queue uses.  folder and files underneath
are generated when a queue is created. They are removed when the queue is
destroyed.

Signed-off-by: Amber Lin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h  |  9 ++
 drivers/gpu/drm/amd/amdkfd/kfd_process.c   | 96 ++
 .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  2 +
 3 files changed, 107 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index c0b0def..cb2d2d7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -503,6 +503,12 @@ struct queue {
struct kfd_process  *process;
struct kfd_dev  *device;
void *gws;
+
+   /* procfs */
+   struct kobject *kobj_qid;
+   struct attribute attr_size;
+   struct attribute attr_type;
+   struct attribute attr_gpuid;
 };
 
 /*
@@ -730,6 +736,7 @@ struct kfd_process {
 
/* Kobj for our procfs */
struct kobject *kobj;
+   struct kobject *kobj_queues;
struct attribute attr_pasid;
 };
 
@@ -836,6 +843,8 @@ extern struct device *kfd_device;
 /* KFD's procfs */
 void kfd_procfs_init(void);
 void kfd_procfs_shutdown(void);
+int kfd_procfs_add_queue(struct queue *q);
+void kfd_procfs_del_queue(struct queue *q);
 
 /* Topology */
 int kfd_topology_init(void);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 25b90f7..78ca037 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -132,6 +132,94 @@ void kfd_procfs_shutdown(void)
}
 }
 
+static int kfd_procfs_add_file(const char *name, struct kobject *kobj,
+  struct attribute *attr)
+{
+   int ret;
+
+   attr->name = name;
+   attr->mode = KFD_SYSFS_FILE_MODE;
+   sysfs_attr_init(attr);
+   ret = sysfs_create_file(kobj, attr);
+   if (ret)
+   pr_warn("Creating %s file failed", name);
+   return ret;
+}
+
+static ssize_t kfd_procfs_queue_show(struct kobject *kobj,
+struct attribute *attr, char *buffer)
+{
+   if (!strcmp(attr->name, "size")) {
+   struct queue *q = container_of(attr, struct queue, attr_size);
+   return snprintf(buffer, PAGE_SIZE, "%llu",
+   q->properties.queue_size);
+   } else if (!strcmp(attr->name, "type")) {
+   struct queue *q = container_of(attr, struct queue, attr_type);
+   return snprintf(buffer, PAGE_SIZE, "%d", q->properties.type);
+   } else if (!strcmp(attr->name, "gpuid")) {
+   struct queue *q = container_of(attr, struct queue, attr_gpuid);
+   return snprintf(buffer, PAGE_SIZE, "%u", q->device->id);
+   } else
+   pr_err("Invalid attribute");
+
+   return 0;
+}
+
+static const struct sysfs_ops procfs_queue_ops = {
+   .show = kfd_procfs_queue_show,
+};
+
+static struct kobj_type procfs_queue_type = {
+   .release = kfd_procfs_kobj_release,
+   .sysfs_ops = _queue_ops,
+};
+
+int kfd_procfs_add_queue(struct queue *q)
+{
+   struct kfd_process *proc;
+   int ret;
+
+   if (!q || !q->process)
+   return -EINVAL;
+   proc = q->process;
+
+   /* Create proc//queues/ folder*/
+   if (!proc->kobj_queues)
+   return -EFAULT;
+   if (q->kobj_qid)
+   return -EEXIST;
+   q->kobj_qid = kfd_alloc_struct(q->kobj_qid);
+   if (!q->kobj_qid)
+   return -ENOMEM;
+   ret = kobject_init_and_add(q->kobj_qid, _queue_type,
+   proc->kobj_queues, "%u", q->properties.queue_id);
+   if (ret < 0) {
+   pr_warn("Creating proc//queues/%u failed",
+   q->properties.queue_id);
+   return ret;
+   }
+
+   /* Create proc//queues//XX files */
+   kfd_procfs_add_file("size", q->kobj_qid, >attr_size);
+   kfd_procfs_add_file("type", q->kobj_qid, >attr_type);
+   kfd_procfs_add_file("gpuid", q->kobj_qid, >attr_gpuid);
+
+   return 0;
+}
+
+void kfd_procfs_del_queue(struct queue *q)
+{
+   if (!q || !q->process)
+   return;
+
+   sysfs_remove_file(q->kobj_qid, >attr_size);
+   sysfs_remove_file(q->kobj_qid, >attr_type);
+   sysfs_remove_file(q->kobj_qid, >attr_gpuid);
+   kobject_del(q->kobj_qid);
+   kobject_put(q->kobj_qid);
+   q->kobj_qid = NULL;
+}
+
 int kfd_process_create_wq(void)
 {
if (!kfd_process_wq)
@@ -323,6 +411,11 @@ struct kfd_process *kfd_create_process(struct file *filep)
if (ret)
pr_warn("Creating pasid for 

Re: [PATCH 1/5] drm/amdgpu: fix braces in amdgpu_vm_update_ptes

[Christian König]

Am 30.01.20 um 23:11 schrieb Felix Kuehling:


On 2020-01-30 7:49, Christian König wrote:

For the root PD mask can be 0x as well which would
overrun to 0 if we don't cast it before we add one.

You're fixing parentheses, not braces.

Parentheses: ()
Brackets: []
Braces: {}


Yeah, I can't remember which is what in English. Need to double check 
that next time.




With the title fixed, this patch is

Reviewed-by: Felix Kuehling 


Thanks for the review,
Christian.





Signed-off-by: Christian König 
Tested-by: Tom St Denis 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index 5cb182231f5d..4ba6a5e5d094 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1487,7 +1487,7 @@ static int amdgpu_vm_update_ptes(struct 
amdgpu_vm_update_params *params,

  incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
  mask = amdgpu_vm_entries_mask(adev, cursor.level);
  pe_start = ((cursor.pfn >> shift) & mask) * 8;
-    entry_end = (uint64_t)(mask + 1) << shift;
+    entry_end = ((uint64_t)mask + 1) << shift;
  entry_end += cursor.pfn & ~(entry_end - 1);
  entry_end = min(entry_end, end);


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[PATCH] drm/amd/display: Possible divide by zero in set_speed()

[Dan Carpenter]

If "speed" is zero then we use it as a divisor to find "prescale".  It's
better to move the check for zero to the very start of the function.

Fixes: 9eeec26a1339 ("drm/amd/display: Refine i2c frequency calculating 
sequence")
Signed-off-by: Dan Carpenter 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 23 ---
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 066188ba7949..24adec407972 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -267,6 +267,9 @@ static void set_speed(
uint32_t xtal_ref_div = 0;
uint32_t prescale = 0;
 
+   if (speed == 0)
+   return;
+
REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, _ref_div);
 
if (xtal_ref_div == 0)
@@ -274,17 +277,15 @@ static void set_speed(
 
prescale = ((dce_i2c_hw->reference_frequency * 2) / xtal_ref_div) / 
speed;
 
-   if (speed) {
-   if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
-   REG_UPDATE_N(SPEED, 3,
-FN(DC_I2C_DDC1_SPEED, 
DC_I2C_DDC1_PRESCALE), prescale,
-FN(DC_I2C_DDC1_SPEED, 
DC_I2C_DDC1_THRESHOLD), 2,
-FN(DC_I2C_DDC1_SPEED, 
DC_I2C_DDC1_START_STOP_TIMING_CNTL), speed > 50 ? 2:1);
-   else
-   REG_UPDATE_N(SPEED, 2,
-FN(DC_I2C_DDC1_SPEED, 
DC_I2C_DDC1_PRESCALE), prescale,
-FN(DC_I2C_DDC1_SPEED, 
DC_I2C_DDC1_THRESHOLD), 2);
-   }
+   if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
+   REG_UPDATE_N(SPEED, 3,
+FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), 
prescale,
+FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2,
+FN(DC_I2C_DDC1_SPEED, 
DC_I2C_DDC1_START_STOP_TIMING_CNTL), speed > 50 ? 2:1);
+   else
+   REG_UPDATE_N(SPEED, 2,
+FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), 
prescale,
+FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2);
 }
 
 static bool setup_engine(
-- 
2.11.0

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Re: Suspecting corrupted VBIOS after update of AMDGPU on AMD7870

[Jacob Hrbek]

*Hello Zhan,*

Here is it:
https://gist.githubusercontent.com/Kreyren/e35587d8710e63e511e69d8653fd996b/raw/628df1c76ff99adab1d2161e6a20f631de101d5c/gistfile1.txt

Note that I'm updating previous gists with new findings (
https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7).

If relevant i'm also getting these 'Green dots' at the initialization of
bios (https://linx.li/s/8j3poh2z.png).
These dots are not present anywhere else and were not present before said
update.

*Thanks,*
- Jacob Hrbek

On Thu, Jan 30, 2020 at 8:10 PM Liu, Zhan  wrote:

> Hi Jacob,
>
>
>
> Thant you for your bug reporting.
>
>
>
> I saw you attached xorg.log, which is great. Could you also grab dmesg.log
> via SSH?
>
>
>
> Thanks,
>
> Zhan
>
>
>
>
>
> *From:* amd-gfx  *On Behalf Of *Jacob
> Hrbek
> *Sent:* 2020/January/30, Thursday 12:18 PM
> *To:* amd-gfx@lists.freedesktop.org
> *Subject:* Suspecting corrupted VBIOS after update of AMDGPU on AMD7870
>
>
>
> *Hello,*
>
> I believe that system update that included amdgpu on debian testing (but i
> am on LFS) corrupted my VBIOS on AMD7870 (+- 4 hours after the update the
> GPU using AMDGPU/Radeon drivers resulted in no output).
>
> i'm sending this email to inform about possible bug with my findings on
> https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7
> 
> and i would appreciate any help in excluding VBIOS corruption from the
> diagnostics.
>
> *Thanks,*
>
> - Jacob Hrbek
>
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Re: Suspecting corrupted VBIOS after update of AMDGPU on AMD7870

[Jacob Hrbek]

I'm sorry for the wrong link, this one should work
https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7

I've manually compiled kernel-5.5 which results in this dmesg -
https://gist.githubusercontent.com/Kreyren/2fa75d30e0632d73311a13c2e872cfe6/raw/78d367f890eb64026e64597091a2a2f40bdbe46a/gistfile1.txt

If relevant i've used this config
https://gist.githubusercontent.com/Kreyren/7b20ad875ca42381d4a0a8e5b1b26a2c/raw/171747682e49fe28cb653b2e45ee42390ca59338/gistfile1.txt
(grabbed from debian)

Regards,
- Jacob Hrbek


On Fri, Jan 31, 2020 at 2:57 AM Liu, Zhan  wrote:

> Okay I see. From your attached dmesg.log, issue comes from here:
>
>
>
> [   26.265638] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0
> timeout, signaled seq=1, emitted seq=2
>
> [   26.265764] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process
> information: process  pid 0 thread  pid 0
>
> [   26.265771] [drm] GPU recovery disabled.
>
>
>
> There was a very similar issue that’s recently fixed and merged in 5.5
> kernel. I’ve noticed that you are using 5.4 kernel, so you can give 5.5 a
> spin to see what happens.
>
>
>
> As for these “Green Dots” at BIOS initialization stage, the main amdgpu
> driver was not loaded yet, so it shouldn’t related to amdgpu.
>
>
>
> BTW, your new findings (
> https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7) gives
> me 404. Please fix the link. Good luck!
>
>
>
> Warm regards,
>
> Zhan
>
>
>
>
>
>
>
> *From:* Jacob Hrbek 
> *Sent:* 2020/January/30, Thursday 5:55 PM
> *To:* Liu, Zhan ; amd-gfx@lists.freedesktop.org
> *Subject:* Re: Suspecting corrupted VBIOS after update of AMDGPU on
> AMD7870
>
>
>
> *Hello Zhan,*
>
> Here is it:
>
> https://gist.githubusercontent.com/Kreyren/e35587d8710e63e511e69d8653fd996b/raw/628df1c76ff99adab1d2161e6a20f631de101d5c/gistfile1.txt
> 
>
>
>
> Note that I'm updating previous gists with new findings (
> https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7).
> 
>
>
>
> If relevant i'm also getting these 'Green dots' at the initialization of
> bios (https://linx.li/s/8j3poh2z.png
> 
> ).
> These dots are not present anywhere else and were not present before said
> update.
>
>
>
> *Thanks,*
>
> - Jacob Hrbek
>
>
>
> On Thu, Jan 30, 2020 at 8:10 PM Liu, Zhan  wrote:
>
> Hi Jacob,
>
>
>
> Thant you for your bug reporting.
>
>
>
> I saw you attached xorg.log, which is great. Could you also grab dmesg.log
> via SSH?
>
>
>
> Thanks,
>
> Zhan
>
>
>
>
>
> *From:* amd-gfx  *On Behalf Of *Jacob
> Hrbek
> *Sent:* 2020/January/30, Thursday 12:18 PM
> *To:* amd-gfx@lists.freedesktop.org
> *Subject:* Suspecting corrupted VBIOS after update of AMDGPU on AMD7870
>
>
>
> *Hello,*
>
> I believe that system update that included amdgpu on debian testing (but i
> am on LFS) corrupted my VBIOS on AMD7870 (+- 4 hours after the update the
> GPU using AMDGPU/Radeon drivers resulted in no output).
>
> i'm sending this email to inform about possible bug with my findings on
> https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7
> 
> and i would appreciate any help in excluding VBIOS corruption from the
> diagnostics.
>
> *Thanks,*
>
> - Jacob Hrbek
>
>
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