Re: [PATCH 3/4] mm: simplify device private page handling in hmm_range_fault

[Ralph Campbell]

On 3/19/20 5:14 PM, Jason Gunthorpe wrote:

On Tue, Mar 17, 2020 at 04:14:31PM -0700, Ralph Campbell wrote:


+static int dmirror_fault(struct dmirror *dmirror, unsigned long start,
+unsigned long end, bool write)
+{
+   struct mm_struct *mm = dmirror->mm;
+   unsigned long addr;
+   uint64_t pfns[64];
+   struct hmm_range range = {
+   .notifier = >notifier,
+   .pfns = pfns,
+   .flags = dmirror_hmm_flags,
+   .values = dmirror_hmm_values,
+   .pfn_shift = DPT_SHIFT,
+   .pfn_flags_mask = ~(dmirror_hmm_flags[HMM_PFN_VALID] |
+   dmirror_hmm_flags[HMM_PFN_WRITE]),


Since pfns is not initialized pfn_flags_mask should be 0.


Good point.


+   .default_flags = dmirror_hmm_flags[HMM_PFN_VALID] |
+   (write ? dmirror_hmm_flags[HMM_PFN_WRITE] : 0),
+   .dev_private_owner = dmirror->mdevice,
+   };
+   int ret = 0;



+static int dmirror_snapshot(struct dmirror *dmirror,
+   struct hmm_dmirror_cmd *cmd)
+{
+   struct mm_struct *mm = dmirror->mm;
+   unsigned long start, end;
+   unsigned long size = cmd->npages << PAGE_SHIFT;
+   unsigned long addr;
+   unsigned long next;
+   uint64_t pfns[64];
+   unsigned char perm[64];
+   char __user *uptr;
+   struct hmm_range range = {
+   .pfns = pfns,
+   .flags = dmirror_hmm_flags,
+   .values = dmirror_hmm_values,
+   .pfn_shift = DPT_SHIFT,
+   .pfn_flags_mask = ~0ULL,


Same here, especially since this is snapshot

Jason


Actually, snapshot ignores pfn_flags_mask and default_flags.
In hmm_pte_need_fault(), HMM_FAULT_SNAPSHOT is checked and returns early before
checking pfn_flags_mask and default_flags since no faults are being requested.

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[PATCH] drm/amdgpu: infinite retries fix from UTLC1 RB SDMA

[Alex Sierra]

[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB.

[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Arcturus.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 21 +
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fc664ec6b5fd..09c08906046f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -115,17 +115,21 @@ static const struct soc15_reg_golden 
golden_settings_sdma_4[] = {
 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 
0x00104002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831d07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 
0x00104002),
-   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002)
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
 };
 
 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 
0x00104001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831d07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 
0x00104001),
-   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001)
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
 };
 
 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
@@ -174,6 +178,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma0_4_2[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 
0xfffd, 0x0001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 
0xfff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x03ff, 
0x03c0),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
 };
 
 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
@@ -203,6 +208,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma1_4_2[] = {
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 
0xfffd, 0x0001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 
0xfff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x03ff, 
0x03c0),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
 };
 
 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
@@ -222,27 +228,35 @@ static const struct soc15_reg_golden 
golden_settings_sdma_arct[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 

[PATCH 1/6] drm/amdgpu: ih doorbell size of range changed for nbio v7.4

[Alex Sierra]

[Why]
nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per 
register.

[How]
Change ih doorbell size from 2 to 4. This means two Dwords per ring.
Current configuration uses two ih rings.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 149d386590df..263dbb1f92ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -185,7 +185,7 @@ static void nbio_v7_4_ih_doorbell_range(struct 
amdgpu_device *adev,
 
if (use_doorbell) {
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
-   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 2);
+   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 4);
} else
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 0);
 
-- 
2.17.1

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[PATCH 2/4] drm/amdgpu: add macro to get proper ih ring register offset

[Alex Sierra]

This macro calculates the IH ring register offset based on
the three ring numbers and asic type.
The parameters needed are the register's name without the prefix mmIH
and the ring number taken from RING0, RING1 or RING2 macros.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 407c6093c2ec..5bd9bc37fadf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -34,6 +34,11 @@
 #include "vega10_ih.h"
 
 #define MAX_REARM_RETRY 10
+#define RING0 0
+#define RING1 (RING0 + 4)
+#define RING2 (RING1 + 4)
+
+#define mmIH_RING_REG(reg, ring) (SOC15_REG_OFFSET(OSSSYS, 0, mmIH_##reg) + 
(ring) * adev->irq.ring_stride)
 
 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
 
-- 
2.17.1

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[PATCH 4/4] drm/amdgpu: reroute VMC and UMD to IH ring 1 for arcturus

[Alex Sierra]

[Why]
Due Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.
It also facilitates the recovery page process, since it's already
running from a process context.

[How]
Setting IH_CLIENT_CFG_DATA for VMC and UMD IH clients.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 8d41b4c27205..95abbf67ead9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -210,6 +210,24 @@ static uint32_t vega10_ih_doorbell_rptr(struct 
amdgpu_ih_ring *ih)
return ih_doorbell_rtpr;
 }
 
+static void vega10_ih_reroute_ih(struct amdgpu_device *adev)
+{
+   uint32_t tmp;
+
+   /* Reroute to IH ring 1 for VMC */
+   WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
+   tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+   WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
+
+   /* Reroute IH ring 1 for UMC */
+   WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
+   tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+   WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
+}
+
 /**
  * vega10_ih_irq_init - init and enable the interrupt ring
  *
@@ -251,6 +269,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
WREG32(mmIH_RING_REG(RB_CNTL, RING0), ih_rb_cntl);
}
 
+   if (adev->asic_type == CHIP_ARCTURUS) {
+   vega10_ih_reroute_ih(adev);
+   }
+
if ((adev->asic_type == CHIP_ARCTURUS &&
 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
adev->asic_type == CHIP_RENOIR) {
-- 
2.17.1

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[PATCH 3/4] drm/amdgpu: replace rd/wr IH ring registers using mmIH_RING_REG macro

[Alex Sierra]

[Why]
Replace the way reads and writes are done to the IH ring registers at the 
vega10_ih.
This is due to different IH ring registers offset between Vega10 and Arcturus.

[How]
mmIH_RING_REG macro is used to calculate the register address first. Then 
RREG32 and WREG32 macros
are used to directly write/read into the register.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 121 +
 1 file changed, 61 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 5bd9bc37fadf..8d41b4c27205 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -51,7 +51,7 @@ static void vega10_ih_set_interrupt_funcs(struct 
amdgpu_device *adev);
  */
 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
 {
-   u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
+   u32 ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL, RING0));
 
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
@@ -61,12 +61,12 @@ static void vega10_ih_enable_interrupts(struct 
amdgpu_device *adev)
return;
}
} else {
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
+   WREG32(mmIH_RING_REG(RB_CNTL, RING0), ih_rb_cntl);
}
adev->irq.ih.enabled = true;
 
if (adev->irq.ih1.ring_size) {
-   ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+   ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL_RING1, RING1));
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
   RB_ENABLE, 1);
if (amdgpu_sriov_vf(adev)) {
@@ -76,13 +76,13 @@ static void vega10_ih_enable_interrupts(struct 
amdgpu_device *adev)
return;
}
} else {
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   WREG32(mmIH_RING_REG(RB_CNTL_RING1, RING1), ih_rb_cntl);
}
adev->irq.ih1.enabled = true;
}
 
if (adev->irq.ih2.ring_size) {
-   ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+   ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL_RING2, RING2));
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
   RB_ENABLE, 1);
if (amdgpu_sriov_vf(adev)) {
@@ -92,7 +92,7 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device 
*adev)
return;
}
} else {
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   WREG32(mmIH_RING_REG(RB_CNTL_RING2, RING2), ih_rb_cntl);
}
adev->irq.ih2.enabled = true;
}
@@ -107,7 +107,7 @@ static void vega10_ih_enable_interrupts(struct 
amdgpu_device *adev)
  */
 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
 {
-   u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
+   u32 ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL, RING0));
 
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
@@ -117,17 +117,17 @@ static void vega10_ih_disable_interrupts(struct 
amdgpu_device *adev)
return;
}
} else {
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
+   WREG32(mmIH_RING_REG(RB_CNTL, RING0), ih_rb_cntl);
}
 
/* set rptr, wptr to 0 */
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
+   WREG32(mmIH_RING_REG(RB_RPTR, RING0), 0);
+   WREG32(mmIH_RING_REG(RB_WPTR, RING0), 0);
adev->irq.ih.enabled = false;
adev->irq.ih.rptr = 0;
 
if (adev->irq.ih1.ring_size) {
-   ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+   ih_rb_cntl = RREG32(mmIH_RING_REG(RB_CNTL_RING1, RING1));
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
   RB_ENABLE, 0);
if (amdgpu_sriov_vf(adev)) {
@@ -137,17 +137,17 @@ static void vega10_ih_disable_interrupts(struct 
amdgpu_device *adev)
return;
}
} else {
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   WREG32(mmIH_RING_REG(RB_CNTL_RING1, RING1), ih_rb_cntl);
}
/* set rptr, wptr to 0 */
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
-   WREG32_SOC15(OSSSYS, 0, 

[PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

[Alex Sierra]

Arcturus and vega10 share the same vega10_ih, however both
have different register offsets at the ih ring section.
This variable is used to help calculate ih ring register addresses
from the osssys, that corresponds to the current asic type.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 5ed4227f304b..fa384ae9a9bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -279,6 +279,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
amdgpu_hotplug_work_func);
}
 
+   if (adev->asic_type == CHIP_ARCTURUS)
+   adev->irq.ring_stride = 1;
+   else
+   adev->irq.ring_stride = 0;
INIT_WORK(>irq.ih1_work, amdgpu_irq_handle_ih1);
INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index c718e94a55c9..1ec5b735cd9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -97,6 +97,7 @@ struct amdgpu_irq {
struct irq_domain   *domain; /* GPU irq controller domain */
unsignedvirq[AMDGPU_MAX_IRQ_SRC_ID];
uint32_tsrbm_soft_reset;
+   unsignedring_stride;
 };
 
 void amdgpu_irq_disable_all(struct amdgpu_device *adev);
-- 
2.17.1

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[pull] amdgpu 5.6 fixes

[Alex Deucher]

Hi Dave, Daniel,

This just adds Mario's pageflip fix on top of yesterday's 5.6 pull.

The following changes since commit a3c33e7a4a116f8715c0ef0e668e6aeff009c762:

  drm/amdgpu: fix typo for vcn2.5/jpeg2.5 idle check (2020-03-18 18:21:57 -0400)

are available in the Git repository at:

  git://people.freedesktop.org/~agd5f/linux tags/amd-drm-fixes-5.6-2020-03-19

for you to fetch changes up to eb916a5a93a64c182b0a8f43886aa6bb4c3e52b0:

  drm/amd/display: Fix pageflip event race condition for DCN. (2020-03-19 
16:18:45 -0400)


amd-drm-fixes-5.6-2020-03-19:

amdgpu:
- Pageflip fix


Mario Kleiner (1):
  drm/amd/display: Fix pageflip event race condition for DCN.

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)
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Re: [PATCH 1/2] drm/amdgpu: cleanup amdgpu_ttm_copy_mem_to_mem and amdgpu_map_buffer

[Felix Kuehling]

That looks like a nice cleanup. Some nit-picks inline ...

On 2020-03-19 9:41, Christian König wrote:

Cleanup amdgpu_ttm_copy_mem_to_mem by using fewer variables
for the same value.

Rename amdgpu_map_buffer to amdgpu_ttm_map_buffer, move it
to avoid the forward decleration, cleanup by moving the map
decission into the function and add some documentation.

No functional change.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 244 
  1 file changed, 118 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 665db2353a78..2b5974268e63 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -62,12 +62,6 @@
  
  #define AMDGPU_TTM_VRAM_MAX_DW_READ	(size_t)128
  
-static int amdgpu_map_buffer(struct ttm_buffer_object *bo,

-struct ttm_mem_reg *mem, unsigned num_pages,
-uint64_t offset, unsigned window,
-struct amdgpu_ring *ring, bool tmz,
-uint64_t *addr);
-
  static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t 
flags)
  {
return 0;
@@ -293,6 +287,92 @@ static struct drm_mm_node *amdgpu_find_mm_node(struct 
ttm_mem_reg *mem,
return mm_node;
  }
  
+/**

+ * amdgpu_ttm_map_buffer - Map memory into the GART windows
+ * @bo: buffer object to map
+ * @mem: memory object to map


Missing documentation for @mm_node.



+ * @num_pages: number of pages to map
+ * @offset: offset into @mem where to start
+ * @windows: which GART window to use


@window (no s)



+ * @ring: DMA ring to use for the copy
+ * @tmz: if we should setup a TMZ enabled mapping
+ * @addr: resulting address inside the MC address space
+ *
+ * Setup one of the GART windows to access a specific piece of memory.


... or return the physical address for local memory.



+ */
+static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
+struct ttm_mem_reg *mem,
+struct drm_mm_node *mm_node,
+unsigned num_pages, uint64_t offset,
+unsigned window, struct amdgpu_ring *ring,
+bool tmz, uint64_t *addr)
+{
+   struct ttm_dma_tt *dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
+   struct amdgpu_device *adev = ring->adev;
+   struct amdgpu_job *job;
+   unsigned num_dw, num_bytes;
+   dma_addr_t *dma_address;
+   struct dma_fence *fence;
+   uint64_t src_addr, dst_addr;
+   uint64_t flags;
+   int r;
+
+   BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
+  AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
+
+   /* Map only what can't be accessed directly */
+   if (mem->start != AMDGPU_BO_INVALID_OFFSET) {
+   *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
+   return 0;
+   }
+
+   *addr = adev->gmc.gart_start;
+   *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
+   AMDGPU_GPU_PAGE_SIZE;
+   *addr += offset & ~PAGE_MASK;
+
+   num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
+   num_bytes = num_pages * 8;
+
+   r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, );
+   if (r)
+   return r;
+
+   src_addr = num_dw * 4;
+   src_addr += job->ibs[0].gpu_addr;
+
+   dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+   dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
+   amdgpu_emit_copy_buffer(adev, >ibs[0], src_addr,
+   dst_addr, num_bytes, false);
+
+   amdgpu_ring_pad_ib(ring, >ibs[0]);
+   WARN_ON(job->ibs[0].length_dw > num_dw);
+
+   dma_address = >dma_address[offset >> PAGE_SHIFT];
+   flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
+   if (tmz)
+   flags |= AMDGPU_PTE_TMZ;
+
+   r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
+   >ibs[0].ptr[num_dw]);
+   if (r)
+   goto error_free;
+
+   r = amdgpu_job_submit(job, >mman.entity,
+ AMDGPU_FENCE_OWNER_UNDEFINED, );
+   if (r)
+   goto error_free;
+
+   dma_fence_put(fence);
+
+   return r;
+
+error_free:
+   amdgpu_job_free(job);
+   return r;
+}
+
  /**
   * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
   * @adev: amdgpu device
@@ -315,14 +395,14 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
   struct dma_resv *resv,
   struct dma_fence **f)
  {
+   const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
+   AMDGPU_GPU_PAGE_SIZE);
+
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+   uint64_t src_node_size, 

Re: [PATCH] Remove stable HAINAN board from max_sclk override check in radeon and amdgpu modules

[Alex Deucher]

On Tue, Mar 17, 2020 at 9:50 AM Yassine Oudjana
 wrote:
>
> Signed-off-by: Yassine Oudjana 

Applied.  Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/si_dpm.c | 1 -
>  drivers/gpu/drm/radeon/si_dpm.c | 1 -
>  2 files changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c 
> b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> index 4cb4c891120b..0860e85a2d35 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> @@ -3439,7 +3439,6 @@ static void si_apply_state_adjust_rules(struct 
> amdgpu_device *adev,
>
> if (adev->asic_type == CHIP_HAINAN) {
> if ((adev->pdev->revision == 0x81) ||
> -   (adev->pdev->revision == 0x83) ||
> (adev->pdev->revision == 0xC3) ||
> (adev->pdev->device == 0x6664) ||
> (adev->pdev->device == 0x6665) ||
> diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
> index 05e8b4d0af3f..2cb85dbe728f 100644
> --- a/drivers/gpu/drm/radeon/si_dpm.c
> +++ b/drivers/gpu/drm/radeon/si_dpm.c
> @@ -2979,7 +2979,6 @@ static void si_apply_state_adjust_rules(struct 
> radeon_device *rdev,
>
> if (rdev->family == CHIP_HAINAN) {
> if ((rdev->pdev->revision == 0x81) ||
> -   (rdev->pdev->revision == 0x83) ||
> (rdev->pdev->revision == 0xC3) ||
> (rdev->pdev->device == 0x6664) ||
> (rdev->pdev->device == 0x6665) ||
> --
> 2.25.1
>
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Re: ensure device private pages have an owner v2

[Jason Gunthorpe]

On Thu, Mar 19, 2020 at 08:16:33AM +0100, Christoph Hellwig wrote:
> On Wed, Mar 18, 2020 at 09:28:49PM -0300, Jason Gunthorpe wrote:
> > > Changes since v1:
> > >  - split out the pgmap->owner addition into a separate patch
> > >  - check pgmap->owner is set for device private mappings
> > >  - rename the dev_private_owner field in struct migrate_vma to src_owner
> > >  - refuse to migrate private pages if src_owner is not set
> > >  - keep the non-fault device private handling in hmm_range_fault
> > 
> > I'm happy enough to take this, did you have plans for a v3?
> 
> I think the only open question is if merging 3 and 4 might make sense.
> It's up to you if you want it resent that way or not.

Okay, I kept it as is and elaborated the commit messages a bit based
on the discussion

It doesn't seem like the changes outside hmm are significant enough to
need more acks

Thanks,
Jason
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Re: [PATCH 3/4] mm: simplify device private page handling in hmm_range_fault

[Jason Gunthorpe]

On Tue, Mar 17, 2020 at 04:14:31PM -0700, Ralph Campbell wrote:
> 
> On 3/17/20 5:59 AM, Christoph Hellwig wrote:
> > On Tue, Mar 17, 2020 at 09:47:55AM -0300, Jason Gunthorpe wrote:
> > > I've been using v7 of Ralph's tester and it is working well - it has
> > > DEVICE_PRIVATE support so I think it can test this flow too. Ralph are
> > > you able?
> > > 
> > > This hunk seems trivial enough to me, can we include it now?
> > 
> > I can send a separate patch for it once the tester covers it.  I don't
> > want to add it to the original patch as it is a significant behavior
> > change compared to the existing code.
> > 
> 
> Attached is an updated version of my HMM tests based on linux-5.6.0-rc6.
> I ran this OK with Jason's 8+1 HMM patches, Christoph's 1-5 misc HMM clean 
> ups,
> and Christoph's 1-4 device private page changes applied.

I'd like to get this to mergable, it looks pretty good now, but I have
no idea about selftests - and I'm struggling to even compile the tools
dir

> diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
> index 69def4a9df00..4d22ce7879a7 100644
> +++ b/lib/Kconfig.debug
> @@ -2162,6 +2162,18 @@ config TEST_MEMINIT
>  
> If unsure, say N.
>  
> +config TEST_HMM
> + tristate "Test HMM (Heterogeneous Memory Management)"
> + depends on DEVICE_PRIVATE
> + select HMM_MIRROR
> +select MMU_NOTIFIER

extra spaces

In general I wonder if it even makes sense that DEVICE_PRIVATE is user
selectable?

> +static int dmirror_fops_open(struct inode *inode, struct file *filp)
> +{
> + struct cdev *cdev = inode->i_cdev;
> + struct dmirror *dmirror;
> + int ret;
> +
> + /* Mirror this process address space */
> + dmirror = kzalloc(sizeof(*dmirror), GFP_KERNEL);
> + if (dmirror == NULL)
> + return -ENOMEM;
> +
> + dmirror->mdevice = container_of(cdev, struct dmirror_device, cdevice);
> + mutex_init(>mutex);
> + xa_init(>pt);
> +
> + ret = mmu_interval_notifier_insert(>notifier, current->mm,
> + 0, ULONG_MAX & PAGE_MASK, _min_ops);
> + if (ret) {
> + kfree(dmirror);
> + return ret;
> + }
> +
> + /* Pairs with the mmdrop() in dmirror_fops_release(). */
> + mmgrab(current->mm);
> + dmirror->mm = current->mm;

The notifier holds a mmgrab, no need for another one

> + /* Only the first open registers the address space. */
> + filp->private_data = dmirror;

Not sure what this comment means

> +static inline struct dmirror_device *dmirror_page_to_device(struct page 
> *page)
> +
> +{
> + struct dmirror_chunk *devmem;
> +
> + devmem = container_of(page->pgmap, struct dmirror_chunk, pagemap);
> + return devmem->mdevice;
> +}

extra devmem var is not really needed

> +
> +static bool dmirror_device_is_mine(struct dmirror_device *mdevice,
> +struct page *page)
> +{
> + if (!is_zone_device_page(page))
> + return false;
> + return page->pgmap->ops == _devmem_ops &&
> + dmirror_page_to_device(page) == mdevice;
> +}

Use new owner stuff, right? Actually this is redunant now, the check
should be just WARN_ON pageowner != self owner

> +static int dmirror_do_fault(struct dmirror *dmirror, struct hmm_range *range)
> +{
> + uint64_t *pfns = range->pfns;
> + unsigned long pfn;
> +
> + for (pfn = (range->start >> PAGE_SHIFT);
> +  pfn < (range->end >> PAGE_SHIFT);
> +  pfn++, pfns++) {
> + struct page *page;
> + void *entry;
> +
> + /*
> +  * HMM_PFN_ERROR is returned if it is accessing invalid memory
> +  * either because of memory error (hardware detected memory
> +  * corruption) or more likely because of truncate on mmap
> +  * file.
> +  */
> + if (*pfns == range->values[HMM_PFN_ERROR])
> + return -EFAULT;

Unless that snapshot is use hmm_range_fault() never returns success
and sets PFN_ERROR, so this should be a WARN_ON

> + if (!(*pfns & range->flags[HMM_PFN_VALID]))
> + return -EFAULT;

Same with valid.

> + page = hmm_device_entry_to_page(range, *pfns);
> + /* We asked for pages to be populated but check anyway. */
> + if (!page)
> + return -EFAULT;

WARN_ON

> + if (is_zone_device_page(page)) {
> + /*
> +  * TODO: need a way to ask HMM to fault foreign zone
> +  * device private pages.
> +  */
> + if (!dmirror_device_is_mine(dmirror->mdevice, page))
> + continue;

Actually re

> +static bool dmirror_interval_invalidate(struct mmu_interval_notifier *mni,
> + const struct mmu_notifier_range *range,
> + unsigned long cur_seq)
> +{
> + struct 

RE: [PATCH] drm/amdkfd: Provide SMI events watch

[Lin, Amber]

[AMD Public Use]

Hi Alex,

https://github.com/RadeonOpenCompute/rocm_smi_lib will use this interface. 
Those functions will be added to this library:

/* Get a handler for watching events */
rsmi_status_t rsmi_event_init(rsmi_event_handle_t *handle);
/* Register events for the device using the handler from init */
rsmi_status_t rsmi_event_register(uint32_t dv_ind, uint32_t events,
rsmi_event_handle_t *handle);
/* Wait for events. If one of the events happens, a success is returned with
 * with details in data.
 */
rsmi_status_t rsmi_event_wait(rsmi_event_handle_t handle, uint32_t timeout_ms,
rsmi_event_data_t *data);
/* Stop watching events */
rsmi_status_t rsmi_event_free(rsmi_event_handle_t handle);

I add the ioctl to /dev/kfd with a debate if it should be in /dev/dri/card* or 
/dev/dri/renderD* instead. The first event to report is VM fault in this patch. 
Other events like RAS errors, PCIe errors, GPU reset… etc will be added for the 
system admin to diagnose the system health. I see this as a system feature so I 
use /dev/kfd. I’ll like to hear if people think differently. Thanks.

Regards,
Amber

-Original Message-
From: Alex Deucher  
Sent: Tuesday, March 17, 2020 3:03 PM
To: Lin, Amber 
Cc: amd-gfx list 
Subject: Re: [PATCH] drm/amdkfd: Provide SMI events watch

On Tue, Mar 17, 2020 at 1:57 PM Amber Lin  wrote:
>
> When the compute is malfunctioning or performance drops, the system 
> admin will use SMI (System Management Interface) tool to 
> monitor/diagnostic what went wrong. This patch provides an event watch 
> interface for the user space to register events they are interested. 
> After the event is registered, the user can use annoymous file 
> descriptor's pull function with wait-time specified to wait for the 
> event to happen. Once the event happens, the user can use read() to 
> retrieve information related to the event.
>
> VM fault event is done in this patch.
>
> Signed-off-by: Amber Lin 

Can you provide a link to the userspace tools that make use of this interface?

Thanks,

Alex

> ---
>  drivers/gpu/drm/amd/amdkfd/Makefile  |   3 +-
>  drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c |   2 +
>  drivers/gpu/drm/amd/amdkfd/kfd_chardev.c |  38 ++
>  drivers/gpu/drm/amd/amdkfd/kfd_device.c  |   1 +
>  drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c  |   2 +
>  drivers/gpu/drm/amd/amdkfd/kfd_priv.h|  10 ++
>  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c  | 143 
> +++
>  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h  |  41 +++
>  include/uapi/linux/kfd_ioctl.h   |  27 -
>  9 files changed, 265 insertions(+), 2 deletions(-)  create mode 
> 100644 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
>  create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile 
> b/drivers/gpu/drm/amd/amdkfd/Makefile
> index 6147462..cc98b4a 100644
> --- a/drivers/gpu/drm/amd/amdkfd/Makefile
> +++ b/drivers/gpu/drm/amd/amdkfd/Makefile
> @@ -53,7 +53,8 @@ AMDKFD_FILES  := $(AMDKFD_PATH)/kfd_module.o \
> $(AMDKFD_PATH)/kfd_int_process_v9.o \
> $(AMDKFD_PATH)/kfd_dbgdev.o \
> $(AMDKFD_PATH)/kfd_dbgmgr.o \
> -   $(AMDKFD_PATH)/kfd_crat.o
> +   $(AMDKFD_PATH)/kfd_crat.o \
> +   $(AMDKFD_PATH)/kfd_smi_events.o
>
>  ifneq ($(CONFIG_AMD_IOMMU_V2),)
>  AMDKFD_FILES += $(AMDKFD_PATH)/kfd_iommu.o diff --git 
> a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c 
> b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
> index 9f59ba9..24b4717 100644
> --- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
> +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
> @@ -24,6 +24,7 @@
>  #include "kfd_events.h"
>  #include "cik_int.h"
>  #include "amdgpu_amdkfd.h"
> +#include "kfd_smi_events.h"
>
>  static bool cik_event_interrupt_isr(struct kfd_dev *dev,
> const uint32_t *ih_ring_entry, 
> @@ -107,6 +108,7 @@ static void cik_event_interrupt_wq(struct kfd_dev *dev,
> ihre->source_id == CIK_INTSRC_GFX_MEM_PROT_FAULT) {
> struct kfd_vm_fault_info info;
>
> +   kfd_smi_event_update_vmfault(dev, pasid);
> kfd_process_vm_fault(dev->dqm, pasid);
>
> memset(, 0, sizeof(info)); diff --git 
> a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> index f8fa03a..8e92956 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> @@ -39,6 +39,7 @@
>  #include "kfd_device_queue_manager.h"
>  #include "kfd_dbgmgr.h"
>  #include "amdgpu_amdkfd.h"
> +#include "kfd_smi_events.h"
>
>  static long kfd_ioctl(struct file *, unsigned int, unsigned long);  
> static int kfd_open(struct inode *, struct file *); @@ -1243,6 
> +1244,40 @@ static int 

[pull] amdgpu, scheduler drm-next-5.7

[Alex Deucher]

Hi Dave, Daniel,

Last round of stuff for 5.7.  Mostly bug fixes.

The following changes since commit 69ddce0970d9d1de63bed9c24eefa0814db29a5a:

  Merge tag 'amd-drm-next-5.7-2020-03-10' of 
git://people.freedesktop.org/~agd5f/linux into drm-next (2020-03-13 09:09:11 
+1000)

are available in the Git repository at:

  git://people.freedesktop.org/~agd5f/linux tags/amd-drm-next-5.7-2020-03-19

for you to fetch changes up to 8cd296082cd9c2adfa5c772154780b21e990a92a:

  drm: amd: fix spelling mistake "shoudn't" -> "shouldn't" (2020-03-19 00:03:05 
-0400)


amd-drm-next-5.7-2020-03-19:

amdgpu:
- SR-IOV fixes
- RAS fixes
- Fallthrough cleanups
- Kconfig fix for ACP
- Fix load balancing with VCN
- DC fixes
- GPU reset fixes
- Various cleanups

scheduler:
- Revert job distribution optimization
- Add a helper to pick the least loaded scheduler


Andrey Grodzovsky (1):
  drm/amdgpu: Move EEPROM I2C adapter to amdgpu_device

Charlene Liu (1):
  drm/amd/display: guard DPPHY_Internal_ctrl

Colin Ian King (1):
  drm: amd: fix spelling mistake "shoudn't" -> "shouldn't"

Dan Carpenter (3):
  drm/amd/display: clean up a condition in dmub_psr_copy_settings()
  drm/amdgpu/display: clean up some indenting
  drm/amd/display: Possible divide by zero in set_speed()

Dennis Li (1):
  drm/amdgpu: add codes to clear AccVGPR for arcturus

Dmytro Laktyushkin (2):
  drm/amd/display: fix split threshold w/a to work with mpo
  drm/amd/display: add on demand pipe merge logic for dcn2+

Evan Quan (1):
  drm/amdgpu: add fbdev suspend/resume on gpu reset

Guchun Chen (1):
  drm/amdgpu: update ras capability's query based on mem ecc configuration

Hawking Zhang (1):
  drm/amdgpu: check GFX RAS capability before reset counters

Hersen Wu (1):
  drm/amd/display: update connector->display_info after read edid

Isabel Zhang (1):
  drm/amd/display: Remove redundant hdcp display state

Jack Zhang (1):
  drm/amdgpu/sriov refine vcn_v2_5_early_init func

James Zhu (3):
  drm/amdgpu: fix typo for vcn1 idle check
  drm/amdgpu: fix typo for vcn2/jpeg2 idle check
  drm/amdgpu: fix typo for vcn2.5/jpeg2.5 idle check

Jerry (Fangzhi) Zuo (1):
  drm/amd/display: Fix test pattern color space inconsistency for Linux

Joe Perches (4):
  AMD DISPLAY CORE: Use fallthrough;
  AMD POWERPLAY: Use fallthrough;
  drm/amd/powerplay: Move fallthrough; into containing #ifdef/#endif
  AMD KFD: Use fallthrough;

John Clements (2):
  drm/amdgpu: resolve failed error inject msg
  amd/powerplay: arcturus baco reset disable all features

Kevin Wang (1):
  drm/amdgpu/swsmu: clean up unused header in swsmu

Lucas Stach (1):
  drm/scheduler: fix inconsistent locking of job_list_lock

Lyude Paul (1):
  drm/amdgpu: Stop using the DRIVER debugging flag for vblank debugging 
messages

Mario Kleiner (1):
  drm/amd/display: Add link_rate quirk for Apple 15" MBP 2017

Martin Tsai (1):
  drm/amd/display: differentiate vsc sdp colorimetry use criteria between 
MST and SST

Monk Liu (1):
  drm/amdgpu: revise RLCG access path

Nathan Chancellor (1):
  drm/amdgpu: Remove unnecessary variable shadow in gfx_v9_0_rlcg_wreg

Nicholas Kazlauskas (2):
  drm/amd/display: Pass triplebuffer surface flip flags down to plane state
  drm/amd/display: Explicitly disable triplebuffer flips

Nikola Cornij (1):
  drm/amd/display: Remove connect DIG FE to its BE during timing programming

Nirmoy Das (3):
  drm/amdgpu: fix switch-case indentation
  drm/sched: implement and export drm_sched_pick_best
  drm/amdgpu: disable gpu_sched load balancer for vcn jobs

Randy Dunlap (1):
  drm: amd/acp: fix broken menu structure

Robert Beckett (1):
  drm/sched: add run job trace

Roman Li (1):
  drm/amd/display: Remove PSR dependency on swizzle mode

Stanley.Yang (3):
  drm/amdgpu: use amdgpu_ras.h in amdgpu_debugfs.c
  drm/amd/display: fix typos for dcn20_funcs and dcn21_funcs struct
  drm/amdgpu: fix warning in ras_debugfs_create_all()

Sung Lee (2):
  drm/amd/display: Revert "DCN2.x Do not program DPPCLK if same value"
  drm/amd/display: Program self refresh control register on boot

Tom St Denis (1):
  drm/amd/amdgpu: Fix GPR read from debugfs (v2)

Wenjing Liu (1):
  drm/amd/display: remove magic numbers in hdcp_ddc

Wyatt Wood (3):
  drm/amd/display: Set disable_dmcu flag properly per asic
  drm/amd/display: Fallback to dmcub for psr when dmcu is disabled
  drm/amd/display: Allocate scratch space for DMUB CW7

Yintian Tao (1):
  drm/amdgpu: miss PRT case when bo update

Yongqiang Sun (3):
  drm/amd/display: workaround for HDMI hotplug in DPMSOFF state
  drm/amd/display: combine watermark change and clock change for update 
clocks.
  drm/amd/display: DPP DTO isn't 

Re: [PATCH v1 0/3] drm: drm_encoder_init() => drm_encoder_init_funcs()

[Sam Ravnborg]

On Thu, Mar 19, 2020 at 03:19:54PM +0100, Sam Ravnborg wrote:
> On Fri, Mar 13, 2020 at 09:17:41PM +0100, Sam Ravnborg wrote:
> > Thomas Zimmermann had made a nice patch-set that introduced
> > drm_simple_encoder_init() which is already present in drm-misc-next.
> > 
> > While looking at this it was suddenly obvious to me that
> > this was functionalty that really should be included in drm_encoder.c
> > The case where the core could handle the callback is pretty
> > common and not part of the simple pipe line.
> > 
> > So after some dialog on dri-devel the conclusion was to go for
> > a change like this:
> > 
> > drm_encoder_init_funcs() for all users that specified a
> > drm_encoder_funcs to extend the functionality.
> > 
> > drm_encoder_init() for all users that did not
> > need to extend the basic functionality with
> > drm_encoder_funcs.
> > 
> > A similar approach with a _funcs() prefix is used elsewhere in drm/
> > 
> > This required a rename of the existing users, and
> > a follow-up patch that moves drm_simple_encoder_init()
> > to drm_encoder.c
> > 
> > Patches 3 in this set demonstrate the use of drm_encoder_init().
> > There are many more drivers that can be converted as Thomas
> > has already demonstrated.
> > 
> > This is all based on work done by Thomas Zimmermann,
> > I just wanted to implement my suggestion so
> > we could select the best way forward.
> > 
> > Note: Daniel Vetter has hinted the approach implemented
> > here smelled like middle-layer.
> > IMO this is not so, it is just a way to handle cleanup
> > for the simple cases.
> 
> We discussed this patch-set briefly on irc.
Just to clarify, we in this context was Daniel Vetter & me.

Sam

> With the upcoming drmm_ changes and such this is bad timing..
> And in the end this may be pointless code-chrunch.
> 
> Patch-set shelfed for now - may re-visit it later.
> 
>   Sam
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Re: [PATCH 1/2] drm/amdgpu: infinite retries fix from UTLC1 RB SDMA

[philip yang]

Can we do similar setting for vg10 to fix infinite retry?

Philip

On 2020-03-18 7:38 p.m., Alex Sierra wrote:

[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB.

[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Arcturus.

Change-Id: I8a6d9b89ea115fb51ff694493c88b8972d6248a5
Signed-off-by: Alex Sierra 
---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 11 +--
  1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fc664ec6b5fd..94328162b6f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -222,27 +222,35 @@ static const struct soc15_reg_golden 
golden_settings_sdma_arct[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x773f, 
0x4002),
-   SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002)
+   SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0x, 
0x00010001)
  };
  
  static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {

@@ -2011,7 +2019,6 @@ static int sdma_v4_0_process_trap_irq(struct 
amdgpu_device *adev,
  struct amdgpu_iv_entry *entry)
  {
uint32_t instance;
-
DRM_DEBUG("IH: SDMA trap\n");
instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
switch (entry->ring_id) {

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Re: [PATCH] Enable reading FRU chip via I2C v3

[Andrey Grodzovsky]

Looks good to me.

Reviewed-by: Andrey Grodzovsky 

Andrey

On 3/19/20 10:16 AM, Kent Russell wrote:

Allow for reading of information like manufacturer, product number
and serial number from the FRU chip. Report the serial number as
the new sysfs file serial_number. Note that this only works on
server cards, as consumer cards do not feature the FRU chip, which
contains this information.

v2: Add documentation to amdgpu.rst, add helper functions,
 rename functions for consistency, fix bad starting offset
v3: Remove testing definitions

Signed-off-by: Kent Russell 
---
  Documentation/gpu/amdgpu.rst  |  24 +++
  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   5 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  90 +++
  .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 143 ++
  .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h|  29 
  6 files changed, 292 insertions(+), 1 deletion(-)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 0efede580039..d9ea09ec8e24 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -202,3 +202,27 @@ busy_percent
  
  .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

 :doc: busy_percent
+
+GPU Product Information
+===
+
+Information about the GPU can be obtained on certain cards
+via sysfs
+
+product_name
+
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+   :doc: product_name
+
+product_number
+--
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+   :doc: product_name
+
+serial_number
+-
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+   :doc: serial_number
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c2bbcdd9c875..210d57a4afc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o 
amdgpu_vm_cpu.o \
amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
-   amdgpu_umc.o smu_v11_0_i2c.o
+   amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o
  
  amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index 87c2523076af..7dd74253e7b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -979,6 +979,11 @@ struct amdgpu_device {
  
  	boolpm_sysfs_en;

boolucode_sysfs_en;
+
+   /* Chip product information */
+   charproduct_number[16];
+   charproduct_name[32];
+   charserial[16];
  };
  
  static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 729565f79cfe..80a654326190 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -64,6 +64,7 @@
  #include "amdgpu_xgmi.h"
  #include "amdgpu_ras.h"
  #include "amdgpu_pmu.h"
+#include "amdgpu_fru_eeprom.h"
  
  #include 

  #include 
@@ -137,6 +138,72 @@ static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
  
  static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
  
+/**

+ * DOC: product_name
+ *
+ * The amdgpu driver provides a sysfs API for reporting the product name
+ * for the device
+ * The file serial_number is used for this and returns the product name
+ * as returned from the FRU.
+ * NOTE: This is only available for certain server cards
+ */
+
+static ssize_t amdgpu_device_get_product_name(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name);
+}
+
+static DEVICE_ATTR(product_name, S_IRUGO,
+   amdgpu_device_get_product_name, NULL);
+
+/**
+ * DOC: product_number
+ *
+ * The amdgpu driver provides a sysfs API for reporting the part number
+ * for the device
+ * The file serial_number is used for this and returns the part number
+ * as returned from the FRU.
+ * NOTE: This is only available for certain server cards
+ */
+
+static ssize_t amdgpu_device_get_product_number(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct 

Re: [PATCH v1 0/3] drm: drm_encoder_init() => drm_encoder_init_funcs()

[Sam Ravnborg]

On Fri, Mar 13, 2020 at 09:17:41PM +0100, Sam Ravnborg wrote:
> Thomas Zimmermann had made a nice patch-set that introduced
> drm_simple_encoder_init() which is already present in drm-misc-next.
> 
> While looking at this it was suddenly obvious to me that
> this was functionalty that really should be included in drm_encoder.c
> The case where the core could handle the callback is pretty
> common and not part of the simple pipe line.
> 
> So after some dialog on dri-devel the conclusion was to go for
> a change like this:
> 
> drm_encoder_init_funcs() for all users that specified a
> drm_encoder_funcs to extend the functionality.
> 
> drm_encoder_init() for all users that did not
> need to extend the basic functionality with
> drm_encoder_funcs.
> 
> A similar approach with a _funcs() prefix is used elsewhere in drm/
> 
> This required a rename of the existing users, and
> a follow-up patch that moves drm_simple_encoder_init()
> to drm_encoder.c
> 
> Patches 3 in this set demonstrate the use of drm_encoder_init().
> There are many more drivers that can be converted as Thomas
> has already demonstrated.
> 
> This is all based on work done by Thomas Zimmermann,
> I just wanted to implement my suggestion so
> we could select the best way forward.
> 
> Note: Daniel Vetter has hinted the approach implemented
> here smelled like middle-layer.
> IMO this is not so, it is just a way to handle cleanup
> for the simple cases.

We discussed this patch-set briefly on irc.
With the upcoming drmm_ changes and such this is bad timing..
And in the end this may be pointless code-chrunch.

Patch-set shelfed for now - may re-visit it later.

Sam
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[PATCH] Enable reading FRU chip via I2C v3

[Kent Russell]

Allow for reading of information like manufacturer, product number
and serial number from the FRU chip. Report the serial number as
the new sysfs file serial_number. Note that this only works on
server cards, as consumer cards do not feature the FRU chip, which
contains this information.

v2: Add documentation to amdgpu.rst, add helper functions,
rename functions for consistency, fix bad starting offset
v3: Remove testing definitions

Signed-off-by: Kent Russell 
---
 Documentation/gpu/amdgpu.rst  |  24 +++
 drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  90 +++
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 143 ++
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h|  29 
 6 files changed, 292 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 0efede580039..d9ea09ec8e24 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -202,3 +202,27 @@ busy_percent
 
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
:doc: busy_percent
+
+GPU Product Information
+===
+
+Information about the GPU can be obtained on certain cards
+via sysfs
+
+product_name
+
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+   :doc: product_name
+
+product_number
+--
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+   :doc: product_name
+
+serial_number
+-
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+   :doc: serial_number
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c2bbcdd9c875..210d57a4afc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o 
amdgpu_vm_cpu.o \
amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
-   amdgpu_umc.o smu_v11_0_i2c.o
+   amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o
 
 amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 87c2523076af..7dd74253e7b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -979,6 +979,11 @@ struct amdgpu_device {
 
boolpm_sysfs_en;
boolucode_sysfs_en;
+
+   /* Chip product information */
+   charproduct_number[16];
+   charproduct_name[32];
+   charserial[16];
 };
 
 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 729565f79cfe..80a654326190 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -64,6 +64,7 @@
 #include "amdgpu_xgmi.h"
 #include "amdgpu_ras.h"
 #include "amdgpu_pmu.h"
+#include "amdgpu_fru_eeprom.h"
 
 #include 
 #include 
@@ -137,6 +138,72 @@ static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
 
 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 
+/**
+ * DOC: product_name
+ *
+ * The amdgpu driver provides a sysfs API for reporting the product name
+ * for the device
+ * The file serial_number is used for this and returns the product name
+ * as returned from the FRU.
+ * NOTE: This is only available for certain server cards
+ */
+
+static ssize_t amdgpu_device_get_product_name(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name);
+}
+
+static DEVICE_ATTR(product_name, S_IRUGO,
+   amdgpu_device_get_product_name, NULL);
+
+/**
+ * DOC: product_number
+ *
+ * The amdgpu driver provides a sysfs API for reporting the part number
+ * for the device
+ * The file serial_number is used for this and returns the part number
+ * as returned from the FRU.
+ * NOTE: This is only available for certain server cards
+ */
+
+static ssize_t amdgpu_device_get_product_number(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number);
+}
+
+static 

[PATCH] Enable reading FRU chip via I2C v2

[Kent Russell]

Allow for reading of information like manufacturer, product number
and serial number from the FRU chip. Report the serial number as
the new sysfs file serial_number. Note that this only works on
server cards, as consumer cards do not feature the FRU chip, which
contains this information.

v2: Add documentation to amdgpu.rst, add helper functions,
rename functions for consistency, fix bad starting offset

Signed-off-by: Kent Russell 
---
 Documentation/gpu/amdgpu.rst  |  24 +++
 drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  90 +++
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 145 ++
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h|  29 
 6 files changed, 294 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 0efede580039..d9ea09ec8e24 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -202,3 +202,27 @@ busy_percent
 
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
:doc: busy_percent
+
+GPU Product Information
+===
+
+Information about the GPU can be obtained on certain cards
+via sysfs
+
+product_name
+
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+   :doc: product_name
+
+product_number
+--
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+   :doc: product_name
+
+serial_number
+-
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+   :doc: serial_number
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c2bbcdd9c875..210d57a4afc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o 
amdgpu_vm_cpu.o \
amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
-   amdgpu_umc.o smu_v11_0_i2c.o
+   amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o
 
 amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 87c2523076af..7dd74253e7b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -979,6 +979,11 @@ struct amdgpu_device {
 
boolpm_sysfs_en;
boolucode_sysfs_en;
+
+   /* Chip product information */
+   charproduct_number[16];
+   charproduct_name[32];
+   charserial[16];
 };
 
 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 729565f79cfe..80a654326190 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -64,6 +64,7 @@
 #include "amdgpu_xgmi.h"
 #include "amdgpu_ras.h"
 #include "amdgpu_pmu.h"
+#include "amdgpu_fru_eeprom.h"
 
 #include 
 #include 
@@ -137,6 +138,72 @@ static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
 
 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 
+/**
+ * DOC: product_name
+ *
+ * The amdgpu driver provides a sysfs API for reporting the product name
+ * for the device
+ * The file serial_number is used for this and returns the product name
+ * as returned from the FRU.
+ * NOTE: This is only available for certain server cards
+ */
+
+static ssize_t amdgpu_device_get_product_name(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name);
+}
+
+static DEVICE_ATTR(product_name, S_IRUGO,
+   amdgpu_device_get_product_name, NULL);
+
+/**
+ * DOC: product_number
+ *
+ * The amdgpu driver provides a sysfs API for reporting the part number
+ * for the device
+ * The file serial_number is used for this and returns the part number
+ * as returned from the FRU.
+ * NOTE: This is only available for certain server cards
+ */
+
+static ssize_t amdgpu_device_get_product_number(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+
+   return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number);
+}
+
+static DEVICE_ATTR(product_number, S_IRUGO,
+  

Re: [PATCH 2/2] drm/amdgpu: ih doorbell size of range changed for nbio v7.4

[Alex Deucher]

On Wed, Mar 18, 2020 at 7:38 PM Alex Sierra  wrote:
>
> [Why]
> nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per 
> register.
>
> [How]
> Change ih doorbell size from 2 to 4. This means two Dwords per ring.
> Current configuration uses two ih rings.
>
> Change-Id: Iae28c22dd6e650f56286bfa0d9e002a8562fa855
> Signed-off-by: Alex Sierra 

Series is:
Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index 149d386590df..263dbb1f92ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -185,7 +185,7 @@ static void nbio_v7_4_ih_doorbell_range(struct 
> amdgpu_device *adev,
>
> if (use_doorbell) {
> ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
> BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
> -   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
> BIF_IH_DOORBELL_RANGE, SIZE, 2);
> +   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
> BIF_IH_DOORBELL_RANGE, SIZE, 4);
> } else
> ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
> BIF_IH_DOORBELL_RANGE, SIZE, 0);
>
> --
> 2.17.1
>
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[PATCH 1/2] drm/amdgpu: cleanup amdgpu_ttm_copy_mem_to_mem and amdgpu_map_buffer

[Christian König]

Cleanup amdgpu_ttm_copy_mem_to_mem by using fewer variables
for the same value.

Rename amdgpu_map_buffer to amdgpu_ttm_map_buffer, move it
to avoid the forward decleration, cleanup by moving the map
decission into the function and add some documentation.

No functional change.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 244 
 1 file changed, 118 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 665db2353a78..2b5974268e63 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -62,12 +62,6 @@
 
 #define AMDGPU_TTM_VRAM_MAX_DW_READ(size_t)128
 
-static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
-struct ttm_mem_reg *mem, unsigned num_pages,
-uint64_t offset, unsigned window,
-struct amdgpu_ring *ring, bool tmz,
-uint64_t *addr);
-
 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 {
return 0;
@@ -293,6 +287,92 @@ static struct drm_mm_node *amdgpu_find_mm_node(struct 
ttm_mem_reg *mem,
return mm_node;
 }
 
+/**
+ * amdgpu_ttm_map_buffer - Map memory into the GART windows
+ * @bo: buffer object to map
+ * @mem: memory object to map
+ * @num_pages: number of pages to map
+ * @offset: offset into @mem where to start
+ * @windows: which GART window to use
+ * @ring: DMA ring to use for the copy
+ * @tmz: if we should setup a TMZ enabled mapping
+ * @addr: resulting address inside the MC address space
+ *
+ * Setup one of the GART windows to access a specific piece of memory.
+ */
+static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
+struct ttm_mem_reg *mem,
+struct drm_mm_node *mm_node,
+unsigned num_pages, uint64_t offset,
+unsigned window, struct amdgpu_ring *ring,
+bool tmz, uint64_t *addr)
+{
+   struct ttm_dma_tt *dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
+   struct amdgpu_device *adev = ring->adev;
+   struct amdgpu_job *job;
+   unsigned num_dw, num_bytes;
+   dma_addr_t *dma_address;
+   struct dma_fence *fence;
+   uint64_t src_addr, dst_addr;
+   uint64_t flags;
+   int r;
+
+   BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
+  AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
+
+   /* Map only what can't be accessed directly */
+   if (mem->start != AMDGPU_BO_INVALID_OFFSET) {
+   *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
+   return 0;
+   }
+
+   *addr = adev->gmc.gart_start;
+   *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
+   AMDGPU_GPU_PAGE_SIZE;
+   *addr += offset & ~PAGE_MASK;
+
+   num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
+   num_bytes = num_pages * 8;
+
+   r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, );
+   if (r)
+   return r;
+
+   src_addr = num_dw * 4;
+   src_addr += job->ibs[0].gpu_addr;
+
+   dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+   dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
+   amdgpu_emit_copy_buffer(adev, >ibs[0], src_addr,
+   dst_addr, num_bytes, false);
+
+   amdgpu_ring_pad_ib(ring, >ibs[0]);
+   WARN_ON(job->ibs[0].length_dw > num_dw);
+
+   dma_address = >dma_address[offset >> PAGE_SHIFT];
+   flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
+   if (tmz)
+   flags |= AMDGPU_PTE_TMZ;
+
+   r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
+   >ibs[0].ptr[num_dw]);
+   if (r)
+   goto error_free;
+
+   r = amdgpu_job_submit(job, >mman.entity,
+ AMDGPU_FENCE_OWNER_UNDEFINED, );
+   if (r)
+   goto error_free;
+
+   dma_fence_put(fence);
+
+   return r;
+
+error_free:
+   amdgpu_job_free(job);
+   return r;
+}
+
 /**
  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
  * @adev: amdgpu device
@@ -315,14 +395,14 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
   struct dma_resv *resv,
   struct dma_fence **f)
 {
+   const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
+   AMDGPU_GPU_PAGE_SIZE);
+
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+   uint64_t src_node_size, dst_node_size;
struct drm_mm_node *src_mm, *dst_mm;
-   uint64_t src_node_start, dst_node_start, src_node_size,
-dst_node_size, src_page_offset, dst_page_offset;
struct dma_fence *fence = NULL;

[PATCH 2/2] drm/amdgpu: add full TMZ support into amdgpu_ttm_map_buffer

[Christian König]

This should allow us to also support VRAM->GTT moves.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 36 +++--
 1 file changed, 28 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2b5974268e63..c7ed4e2f8460 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -307,21 +307,21 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object 
*bo,
 unsigned window, struct amdgpu_ring *ring,
 bool tmz, uint64_t *addr)
 {
-   struct ttm_dma_tt *dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
struct amdgpu_device *adev = ring->adev;
struct amdgpu_job *job;
unsigned num_dw, num_bytes;
-   dma_addr_t *dma_address;
struct dma_fence *fence;
uint64_t src_addr, dst_addr;
+   void *cpu_addr;
uint64_t flags;
+   unsigned int i;
int r;
 
BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
   AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 
/* Map only what can't be accessed directly */
-   if (mem->start != AMDGPU_BO_INVALID_OFFSET) {
+   if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
*addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
return 0;
}
@@ -349,15 +349,35 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object 
*bo,
amdgpu_ring_pad_ib(ring, >ibs[0]);
WARN_ON(job->ibs[0].length_dw > num_dw);
 
-   dma_address = >dma_address[offset >> PAGE_SHIFT];
flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
if (tmz)
flags |= AMDGPU_PTE_TMZ;
 
-   r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
-   >ibs[0].ptr[num_dw]);
-   if (r)
-   goto error_free;
+   cpu_addr = >ibs[0].ptr[num_dw];
+
+   if (mem->mem_type == TTM_PL_TT) {
+   struct ttm_dma_tt *dma;
+   dma_addr_t *dma_address;
+
+   dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
+   dma_address = >dma_address[offset >> PAGE_SHIFT];
+   r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
+   cpu_addr);
+   if (r)
+   goto error_free;
+   } else {
+   dma_addr_t dma_address;
+
+   dma_address = (mm_node->start << PAGE_SHIFT) + offset;
+   for (i = 0; i < num_pages; ++i) {
+   r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
+   _address, flags, cpu_addr);
+   if (r)
+   goto error_free;
+
+   dma_address += PAGE_SIZE;
+   }
+   }
 
r = amdgpu_job_submit(job, >mman.entity,
  AMDGPU_FENCE_OWNER_UNDEFINED, );
-- 
2.17.1

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Re: [PATCH] drm/amdkfd: fix the wrong no space return while acquires packet buffer

[Huang Rui]

On Thu, Mar 19, 2020 at 07:42:04PM +0800, Pan, Xinhui wrote:
> 
> 
> > 2020年3月19日 18:51，Huang Rui  写道：
> > 
> > The queue buffer index starts from position 0, so the available buffer size
> > which starts from position 0 to rptr should be "rptr" index value. While the
> > packet_size_in_dwords == rptr, the available buffer is just good enough.
> > 
> > Signed-off-by: Huang Rui 
> > ---
> > drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c 
> > b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
> > index bae7064..4667c8f 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
> > @@ -263,7 +263,7 @@ int kq_acquire_packet_buffer(struct kernel_queue *kq,
> > /* make sure after rolling back to position 0, there is
> >  * still enough space.
> >  */
> > -   if (packet_size_in_dwords >= rptr)
> > +   if (packet_size_in_dwords > rptr)
> 
> rptr should always be > wptr unless ring is empty.
> 
> say, rptr is 4, packet_size_in_dwords is 4. Then wptr changes from 0 to 4, 
> that is illegal.
> 

Hey, xinhui, yes. :-)

See the comment "we can only use up to queue_size_dword - 1 dwords", that
we cannot use the whole packet slots in the queue, it's to differentiate
empty and full cases.

Thanks,
Ray

> 
> > goto err_no_space;
> > 
> > /* fill nops, roll back and start at position 0 */
> > -- 
> > 2.7.4
> > 
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Re: ensure device private pages have an owner v2

[Jason Gunthorpe]

On Thu, Mar 19, 2020 at 08:16:33AM +0100, Christoph Hellwig wrote:
> On Wed, Mar 18, 2020 at 09:28:49PM -0300, Jason Gunthorpe wrote:
> > > Changes since v1:
> > >  - split out the pgmap->owner addition into a separate patch
> > >  - check pgmap->owner is set for device private mappings
> > >  - rename the dev_private_owner field in struct migrate_vma to src_owner
> > >  - refuse to migrate private pages if src_owner is not set
> > >  - keep the non-fault device private handling in hmm_range_fault
> > 
> > I'm happy enough to take this, did you have plans for a v3?
> 
> I think the only open question is if merging 3 and 4 might make sense.
> It's up to you if you want it resent that way or not.

Now that I understand that amdgpu doesn't set the 'do not return
device_private pages' flag, I think the split is fine, I'll grab it as
is then today

Thanks,
Jason
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Re: [PATCH] drm/amdkfd: fix the wrong no space return while acquires packet buffer

[Pan, Xinhui]

> 2020年3月19日 18:51，Huang Rui  写道：
> 
> The queue buffer index starts from position 0, so the available buffer size
> which starts from position 0 to rptr should be "rptr" index value. While the
> packet_size_in_dwords == rptr, the available buffer is just good enough.
> 
> Signed-off-by: Huang Rui 
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
> index bae7064..4667c8f 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
> @@ -263,7 +263,7 @@ int kq_acquire_packet_buffer(struct kernel_queue *kq,
>   /* make sure after rolling back to position 0, there is
>* still enough space.
>*/
> - if (packet_size_in_dwords >= rptr)
> + if (packet_size_in_dwords > rptr)

rptr should always be > wptr unless ring is empty.

say, rptr is 4, packet_size_in_dwords is 4. Then wptr changes from 0 to 4, that 
is illegal.


>   goto err_no_space;
> 
>   /* fill nops, roll back and start at position 0 */
> -- 
> 2.7.4
> 
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[PATCH] drm/amdkfd: fix the wrong no space return while acquires packet buffer

[Huang Rui]

The queue buffer index starts from position 0, so the available buffer size
which starts from position 0 to rptr should be "rptr" index value. While the
packet_size_in_dwords == rptr, the available buffer is just good enough.

Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index bae7064..4667c8f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -263,7 +263,7 @@ int kq_acquire_packet_buffer(struct kernel_queue *kq,
/* make sure after rolling back to position 0, there is
 * still enough space.
 */
-   if (packet_size_in_dwords >= rptr)
+   if (packet_size_in_dwords > rptr)
goto err_no_space;
 
/* fill nops, roll back and start at position 0 */
-- 
2.7.4

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[PATCH] drm/amd/powerplay: correct the bootup power source for Navi1X

[Evan Quan]

PMFW may boots those ASICs with DC mode. Need to set it back
to AC mode.

Change-Id: I56ffd0e747f778aa013da43a8693ddfb5da31e3c
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 15 +++
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  1 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 16 
 drivers/gpu/drm/amd/powerplay/smu_internal.h   |  3 +++
 4 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 3f05921056ec..64041d90ddee 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1144,6 +1144,21 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
}
}
}
+
+   if (adev->asic_type >= CHIP_NAVI10 &&
+   adev->asic_type <= CHIP_NAVI12) {
+   /*
+* For Navi1X, manually switch it to AC mode as PMFW
+* may boot it with DC mode.
+* TODO: should check whether we are indeed under AC
+* mode before doing this.
+*/
+   ret = smu_set_power_source(smu, SMU_POWER_SOURCE_AC);
+   if (ret) {
+   pr_err("Failed to switch to AC mode!\n");
+   return ret;
+   }
+   }
}
if (adev->asic_type != CHIP_ARCTURUS) {
ret = smu_notify_display_change(smu);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 657a6f17e91f..323e7e61493b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -570,6 +570,7 @@ struct pptable_funcs {
int (*override_pcie_parameters)(struct smu_context *smu);
uint32_t (*get_pptable_power_limit)(struct smu_context *smu);
int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);
+   int (*set_power_source)(struct smu_context *smu, enum 
smu_power_src_type power_src);
 };
 
 int smu_load_microcode(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index d66dfa7410b6..45d46c38f7ca 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -2275,6 +2275,21 @@ static int 
navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
return navi10_dummy_pstate_control(smu, true);
 }
 
+static int navi10_set_power_source(struct smu_context *smu,
+  enum smu_power_src_type power_src)
+{
+   int pwr_source;
+
+   pwr_source = navi10_get_pwr_src_index(smu, (uint32_t)power_src);
+   if (pwr_source < 0)
+   return -EINVAL;
+
+   return smu_send_smc_msg_with_param(smu,
+   SMU_MSG_NotifyPowerSource,
+   pwr_source,
+   NULL);
+}
+
 static const struct pptable_funcs navi10_ppt_funcs = {
.tables_init = navi10_tables_init,
.alloc_dpm_context = navi10_allocate_dpm_context,
@@ -2369,6 +2384,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_pptable_power_limit = navi10_get_pptable_power_limit,
.run_btc = navi10_run_btc,
.disable_umc_cdr_12gbps_workaround = 
navi10_disable_umc_cdr_12gbps_workaround,
+   .set_power_source = navi10_set_power_source,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h 
b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 6900877de845..40c35bcc5a0a 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -211,4 +211,7 @@ static inline int smu_send_smc_msg(struct smu_context *smu, 
enum smu_message_typ
 #define smu_disable_umc_cdr_12gbps_workaround(smu) \
((smu)->ppt_funcs->disable_umc_cdr_12gbps_workaround ? 
(smu)->ppt_funcs->disable_umc_cdr_12gbps_workaround((smu)) : 0)
 
+#define smu_set_power_source(smu, power_src) \
+   ((smu)->ppt_funcs->set_power_source ? 
(smu)->ppt_funcs->set_power_source((smu), (power_src)) : 0)
+
 #endif
-- 
2.25.1

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Re: ensure device private pages have an owner v2

[Christoph Hellwig]

On Wed, Mar 18, 2020 at 09:28:49PM -0300, Jason Gunthorpe wrote:
> > Changes since v1:
> >  - split out the pgmap->owner addition into a separate patch
> >  - check pgmap->owner is set for device private mappings
> >  - rename the dev_private_owner field in struct migrate_vma to src_owner
> >  - refuse to migrate private pages if src_owner is not set
> >  - keep the non-fault device private handling in hmm_range_fault
> 
> I'm happy enough to take this, did you have plans for a v3?

I think the only open question is if merging 3 and 4 might make sense.
It's up to you if you want it resent that way or not.
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RE: [PATCH 2/8] drm/amdgpu: create new files for arcturus ih

[Zhang, Hawking]

[AMD Public Use]

The register offset of IH_RB_RING1|RING2 register group is the major 
differences between osssys 4.0 and osssys 4.2. Other than that, 4.2 share the 
same registers as 4.0. So just centralize ih ring1 and ring2 related functions 
into a separated file, and invoke ih ring1 and ring2 function from vega10_ih 
function call for Arcturus.

Regards,
Hawking
From: amd-gfx  On Behalf Of Deucher, 
Alexander
Sent: Thursday, March 19, 2020 09:35
To: Kuehling, Felix ; Sierra Guiza, Alejandro (Alex) 
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/8] drm/amdgpu: create new files for arcturus ih


[AMD Public Use]

if we have been using vega10_ih all along for arcturus, presumably the register 
map is close enough.  I'd suggest either adding whatever new stuff you need to 
vega10_ih.c or navi10_ih.c.  No need to add a completely new one for a small 
change like this.

Alex

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Felix Kuehling 
mailto:felix.kuehl...@amd.com>>
Sent: Wednesday, March 18, 2020 7:33 PM
To: Sierra Guiza, Alejandro (Alex) 
mailto:alex.sie...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Subject: Re: [PATCH 2/8] drm/amdgpu: create new files for arcturus ih

How much overlap is there between arcturus_ih and nave10_ih? Given that
they both use the same register map, could they share the same driver
code with only minor differences?

If they're almost the same, maybe you could rename navi10_ih.[ch] to
osssys_v5_0.[ch] and use it for both navi10 and arcturus.

Regards,
   Felix

On 2020-03-18 18:51, Alex Sierra wrote:
> [Why]
> Arcturus uses osssys v4.2. This shares the same register map as
> osssys v5.0.
>
> [How]
> Copy vega10_ih into new arcturus_ih source and header files.
> Replace osssys include file with v5.0.0 on arcturus_ih.c source.
>
> Change-Id: I5215f32f477adb6a30acef6e8add9f8e5bb041ef
> Signed-off-by: Alex Sierra mailto:alex.sie...@amd.com>>
> ---
>   drivers/gpu/drm/amd/amdgpu/arcturus_ih.c | 766 +++
>   drivers/gpu/drm/amd/amdgpu/arcturus_ih.h |  30 +
>   2 files changed, 796 insertions(+)
>   create mode 100644 drivers/gpu/drm/amd/amdgpu/arcturus_ih.c
>   create mode 100644 drivers/gpu/drm/amd/amdgpu/arcturus_ih.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/arcturus_ih.c 
> b/drivers/gpu/drm/amd/amdgpu/arcturus_ih.c
> new file mode 100644
> index ..21bb5be40921
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/arcturus_ih.c
> @@ -0,0 +1,766 @@
> +/*
> + * Copyright 2020 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include 
> +
> +#include "amdgpu.h"
> +#include "amdgpu_ih.h"
> +#include "soc15.h"
> +
> +#include "oss/osssys_5_0_0_offset.h"
> +#include "oss/osssys_5_0_0_sh_mask.h"
> +
> +#include "soc15_common.h"
> +#include "arcturus_ih.h"
> +
> +#define MAX_REARM_RETRY 10
> +
> +static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
> +
> +/**
> + * vega10_ih_enable_interrupts - Enable the interrupt ring buffer
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * Enable the interrupt ring buffer (VEGA10).
> + */
> +static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
> +{
> + u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
> +
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
> + if (amdgpu_sriov_vf(adev)) {
> + if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL, 
> ih_rb_cntl)) {
> + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> + }
> + adev->irq.ih.enabled = true;
> +
> 

RE: [PATCH] drm/amdgpu: protect RAS sysfs during GPU reset

[Zhang, Hawking]

[AMD Public Use]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
From: Clements, John 
Sent: Thursday, March 19, 2020 00:43
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: protect RAS sysfs during GPU reset


[AMD Public Use]

Submitting patch for review to protect RAS sysfs access' during a RAS event and 
to clear the MMHub EDC registers early on in a BACO reset
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RE: [PATCH] drm/amdgpu: protect RAS sysfs during GPU reset

[Zhang, Hawking]

[AMD Public Use]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
From: Clements, John 
Sent: Thursday, March 19, 2020 00:43
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: protect RAS sysfs during GPU reset


[AMD Public Use]

Submitting patch for review to protect RAS sysfs access' during a RAS event and 
to clear the MMHub EDC registers early on in a BACO reset
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RE: [PATCH] drm/amdgpu/sriov : Don't resume RLCG for SRIOV guest

[Zhang, Hawking]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Liu, Shaoyun  
Sent: Thursday, March 19, 2020 05:30
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking 
Subject: RE: [PATCH] drm/amdgpu/sriov : Don't resume RLCG for SRIOV guest

[AMD Official Use Only - Internal Distribution Only]

ping

-Original Message-
From: Liu, Shaoyun  
Sent: Tuesday, March 17, 2020 12:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun 
Subject: [PATCH] drm/amdgpu/sriov : Don't resume RLCG for SRIOV guest

RLCG is enabled by host driver, no need to enable it in guest for none-PSP load 
path

Change-Id: I2f313743bf3d492f06aaef07224da6eda3878a28
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d1cdcb4..e134bb2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1940,6 +1940,11 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device 
*adev)
if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
gfx_v10_0_rlc_enable_srm(adev);
} else {
+   if (amdgpu_sriov_vf(adev)) {
+   gfx_v10_0_init_csb(adev);
+   return 0;
+   }
+
adev->gfx.rlc.funcs->stop(adev);
 
/* disable CG */
-- 
2.7.4
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