[PATCH v2 hmm 3/9] mm/hmm: remove unused code and tidy comments

[Jason Gunthorpe]

From: Jason Gunthorpe 

Delete several functions that are never called, fix some desync between
comments and structure content, toss the now out of date top of file
header, and move one function only used by hmm.c into hmm.c

Reviewed-by: Christoph Hellwig 
Signed-off-by: Jason Gunthorpe 
---
 include/linux/hmm.h | 104 +---
 mm/hmm.c|  24 +++---
 2 files changed, 19 insertions(+), 109 deletions(-)

diff --git a/include/linux/hmm.h b/include/linux/hmm.h
index bb6be4428633a8..daee6508a3f609 100644
--- a/include/linux/hmm.h
+++ b/include/linux/hmm.h
@@ -3,58 +3,8 @@
  * Copyright 2013 Red Hat Inc.
  *
  * Authors: Jérôme Glisse 
- */
-/*
- * Heterogeneous Memory Management (HMM)
- *
- * See Documentation/vm/hmm.rst for reasons and overview of what HMM is and it
- * is for. Here we focus on the HMM API description, with some explanation of
- * the underlying implementation.
- *
- * Short description: HMM provides a set of helpers to share a virtual address
- * space between CPU and a device, so that the device can access any valid
- * address of the process (while still obeying memory protection). HMM also
- * provides helpers to migrate process memory to device memory, and back. Each
- * set of functionality (address space mirroring, and migration to and from
- * device memory) can be used independently of the other.
- *
- *
- * HMM address space mirroring API:
- *
- * Use HMM address space mirroring if you want to mirror a range of the CPU
- * page tables of a process into a device page table. Here, "mirror" means 
"keep
- * synchronized". Prerequisites: the device must provide the ability to write-
- * protect its page tables (at PAGE_SIZE granularity), and must be able to
- * recover from the resulting potential page faults.
  *
- * HMM guarantees that at any point in time, a given virtual address points to
- * either the same memory in both CPU and device page tables (that is: CPU and
- * device page tables each point to the same pages), or that one page table 
(CPU
- * or device) points to no entry, while the other still points to the old page
- * for the address. The latter case happens when the CPU page table update
- * happens first, and then the update is mirrored over to the device page 
table.
- * This does not cause any issue, because the CPU page table cannot start
- * pointing to a new page until the device page table is invalidated.
- *
- * HMM uses mmu_notifiers to monitor the CPU page tables, and forwards any
- * updates to each device driver that has registered a mirror. It also provides
- * some API calls to help with taking a snapshot of the CPU page table, and to
- * synchronize with any updates that might happen concurrently.
- *
- *
- * HMM migration to and from device memory:
- *
- * HMM provides a set of helpers to hotplug device memory as ZONE_DEVICE, with
- * a new MEMORY_DEVICE_PRIVATE type. This provides a struct page for each page
- * of the device memory, and allows the device driver to manage its memory
- * using those struct pages. Having struct pages for device memory makes
- * migration easier. Because that memory is not addressable by the CPU it must
- * never be pinned to the device; in other words, any CPU page fault can always
- * cause the device memory to be migrated (copied/moved) back to regular 
memory.
- *
- * A new migrate helper (migrate_vma()) has been added (see mm/migrate.c) that
- * allows use of a device DMA engine to perform the copy operation between
- * regular system memory and device memory.
+ * See Documentation/vm/hmm.rst for reasons and overview of what HMM is.
  */
 #ifndef LINUX_HMM_H
 #define LINUX_HMM_H
@@ -120,9 +70,6 @@ enum hmm_pfn_value_e {
  *
  * @notifier: a mmu_interval_notifier that includes the start/end
  * @notifier_seq: result of mmu_interval_read_begin()
- * @hmm: the core HMM structure this range is active against
- * @vma: the vm area struct for the range
- * @list: all range lock are on a list
  * @start: range virtual start address (inclusive)
  * @end: range virtual end address (exclusive)
  * @pfns: array of pfns (big enough for the range)
@@ -130,8 +77,7 @@ enum hmm_pfn_value_e {
  * @values: pfn value for some special case (none, special, error, ...)
  * @default_flags: default flags for the range (write, read, ... see hmm doc)
  * @pfn_flags_mask: allows to mask pfn flags so that only default_flags matter
- * @pfn_shifts: pfn shift value (should be <= PAGE_SHIFT)
- * @valid: pfns array did not change since it has been fill by an HMM function
+ * @pfn_shift: pfn shift value (should be <= PAGE_SHIFT)
  * @dev_private_owner: owner of device private pages
  */
 struct hmm_range {
@@ -171,52 +117,6 @@ static inline struct page *hmm_device_entry_to_page(const 
struct hmm_range *rang
return pfn_to_page(entry >> range->pfn_shift);
 }
 
-/*
- * hmm_device_entry_to_pfn() - return pfn value store in a device entry
- * @range: range use to decode device entry value
- * 

[PATCH v3 hmm 0/9] Small hmm_range_fault() cleanups

[Jason Gunthorpe]

From: Jason Gunthorpe 

This is v3 with some minor adjustments made.

We are at the end of the dev cycle, and as nothing major has come up I'll push
this toward linux-next to get some coverage and decide next week what goes
this cycle.

v3 changes:
 - Keep NEED_WRITE_FAULT and NEED_FAULT separate (CH)
 - Use CH's vesion of hmm_can_fault and drop the inline
v2: https://lore.kernel.org/r/20200324011457.2817-1-...@ziepe.ca
v1: https://lore.kernel.org/r/20200320164905.21722-1-...@ziepe.ca

Thanks to everyone who looked on this,
Jason

Jason Gunthorpe (9):
  mm/hmm: remove pgmap checking for devmap pages
  mm/hmm: return the fault type from hmm_pte_need_fault()
  mm/hmm: remove unused code and tidy comments
  mm/hmm: remove HMM_FAULT_SNAPSHOT
  mm/hmm: remove the CONFIG_TRANSPARENT_HUGEPAGE #ifdef
  mm/hmm: use device_private_entry_to_pfn()
  mm/hmm: do not unconditionally set pfns when returning EBUSY
  mm/hmm: do not set pfns when returning an error code
  mm/hmm: return error for non-vma snapshots

 Documentation/vm/hmm.rst|  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |   2 +-
 drivers/gpu/drm/nouveau/nouveau_svm.c   |   2 +-
 include/linux/hmm.h | 109 +
 mm/hmm.c| 307 +---
 5 files changed, 128 insertions(+), 304 deletions(-)

-- 
2.25.2

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[PATCH v2 hmm 5/9] mm/hmm: remove the CONFIG_TRANSPARENT_HUGEPAGE #ifdef

[Jason Gunthorpe]

From: Jason Gunthorpe 

This code can be compiled when CONFIG_TRANSPARENT_HUGEPAGE is off, so
remove the ifdef.

The function is only ever called under

   if (pmd_devmap(pmd) || pmd_trans_huge(pmd))

Which is statically false if !CONFIG_TRANSPARENT_HUGEPAGE, so the compiler
reliably eliminates all of this code.

Reviewed-by: Ralph Campbell 
Reviewed-by: Christoph Hellwig 
Tested-by: Ralph Campbell 
Signed-off-by: Jason Gunthorpe 
---
 mm/hmm.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index 8dbd9e1d0308b4..3a71ec72b0a42f 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -193,7 +193,6 @@ static inline uint64_t pmd_to_hmm_pfn_flags(struct 
hmm_range *range, pmd_t pmd)
range->flags[HMM_PFN_VALID];
 }
 
-#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 static int hmm_vma_handle_pmd(struct mm_walk *walk, unsigned long addr,
unsigned long end, uint64_t *pfns, pmd_t pmd)
 {
@@ -216,11 +215,6 @@ static int hmm_vma_handle_pmd(struct mm_walk *walk, 
unsigned long addr,
hmm_vma_walk->last = end;
return 0;
 }
-#else /* CONFIG_TRANSPARENT_HUGEPAGE */
-/* stub to allow the code below to compile */
-int hmm_vma_handle_pmd(struct mm_walk *walk, unsigned long addr,
-   unsigned long end, uint64_t *pfns, pmd_t pmd);
-#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 
 static inline bool hmm_is_device_private_entry(struct hmm_range *range,
swp_entry_t entry)
-- 
2.25.2

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[PATCH v2 hmm 8/9] mm/hmm: do not set pfns when returning an error code

[Jason Gunthorpe]

From: Jason Gunthorpe 

Most places that return an error code, like -EFAULT, do not set
HMM_PFN_ERROR, only two places do this.

Resolve this inconsistency by never setting the pfns on an error
exit. This doesn't seem like a worthwhile thing to do anyhow.

If for some reason it becomes important, it makes more sense to directly
return the address of the failing page rather than have the caller scan
for the HMM_PFN_ERROR.

No caller inspects the pnfs output array if hmm_range_fault() fails.

Reviewed-by: Christoph Hellwig 
Signed-off-by: Jason Gunthorpe 
---
 mm/hmm.c | 18 +++---
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index dc826898979bc5..e875d9ef0968fd 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -77,17 +77,14 @@ static int hmm_vma_fault(unsigned long addr, unsigned long 
end,
 unsigned int required_fault, struct mm_walk *walk)
 {
struct hmm_vma_walk *hmm_vma_walk = walk->private;
-   struct hmm_range *range = hmm_vma_walk->range;
struct vm_area_struct *vma = walk->vma;
-   uint64_t *pfns = range->pfns;
-   unsigned long i = (addr - range->start) >> PAGE_SHIFT;
unsigned int fault_flags = FAULT_FLAG_REMOTE;
 
WARN_ON_ONCE(!required_fault);
hmm_vma_walk->last = addr;
 
if (!vma)
-   goto out_error;
+   return -EFAULT;
 
if (required_fault & HMM_NEED_WRITE_FAULT) {
if (!(vma->vm_flags & VM_WRITE))
@@ -95,15 +92,10 @@ static int hmm_vma_fault(unsigned long addr, unsigned long 
end,
fault_flags |= FAULT_FLAG_WRITE;
}
 
-   for (; addr < end; addr += PAGE_SIZE, i++)
+   for (; addr < end; addr += PAGE_SIZE)
if (handle_mm_fault(vma, addr, fault_flags) & VM_FAULT_ERROR)
-   goto out_error;
-
+   return -EFAULT;
return -EBUSY;
-
-out_error:
-   pfns[i] = range->values[HMM_PFN_ERROR];
-   return -EFAULT;
 }
 
 static unsigned int hmm_pte_need_fault(const struct hmm_vma_walk *hmm_vma_walk,
@@ -286,7 +278,6 @@ static int hmm_vma_handle_pte(struct mm_walk *walk, 
unsigned long addr,
 
/* Report error for everything else */
pte_unmap(ptep);
-   *pfn = range->values[HMM_PFN_ERROR];
return -EFAULT;
}
 
@@ -572,9 +563,6 @@ static const struct mm_walk_ops hmm_walk_ops = {
  *
  * This is similar to get_user_pages(), except that it can read the page tables
  * without mutating them (ie causing faults).
- *
- * On error, for one virtual address in the range, the function will mark the
- * corresponding HMM pfn entry with an error flag.
  */
 long hmm_range_fault(struct hmm_range *range)
 {
-- 
2.25.2

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[PATCH v2 hmm 1/9] mm/hmm: remove pgmap checking for devmap pages

[Jason Gunthorpe]

From: Jason Gunthorpe 

The checking boils down to some racy check if the pagemap is still
available or not. Instead of checking this, rely entirely on the
notifiers, if a pagemap is destroyed then all pages that belong to it must
be removed from the tables and the notifiers triggered.

Reviewed-by: Ralph Campbell 
Reviewed-by: Christoph Hellwig 
Tested-by: Ralph Campbell 
Signed-off-by: Jason Gunthorpe 
---
 mm/hmm.c | 50 ++
 1 file changed, 2 insertions(+), 48 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index a491d9aaafe45d..3a2610e0713329 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -28,7 +28,6 @@
 
 struct hmm_vma_walk {
struct hmm_range*range;
-   struct dev_pagemap  *pgmap;
unsigned long   last;
unsigned intflags;
 };
@@ -196,19 +195,8 @@ static int hmm_vma_handle_pmd(struct mm_walk *walk, 
unsigned long addr,
return hmm_vma_fault(addr, end, fault, write_fault, walk);
 
pfn = pmd_pfn(pmd) + ((addr & ~PMD_MASK) >> PAGE_SHIFT);
-   for (i = 0; addr < end; addr += PAGE_SIZE, i++, pfn++) {
-   if (pmd_devmap(pmd)) {
-   hmm_vma_walk->pgmap = get_dev_pagemap(pfn,
- hmm_vma_walk->pgmap);
-   if (unlikely(!hmm_vma_walk->pgmap))
-   return -EBUSY;
-   }
+   for (i = 0; addr < end; addr += PAGE_SIZE, i++, pfn++)
pfns[i] = hmm_device_entry_from_pfn(range, pfn) | cpu_flags;
-   }
-   if (hmm_vma_walk->pgmap) {
-   put_dev_pagemap(hmm_vma_walk->pgmap);
-   hmm_vma_walk->pgmap = NULL;
-   }
hmm_vma_walk->last = end;
return 0;
 }
@@ -300,15 +288,6 @@ static int hmm_vma_handle_pte(struct mm_walk *walk, 
unsigned long addr,
if (fault || write_fault)
goto fault;
 
-   if (pte_devmap(pte)) {
-   hmm_vma_walk->pgmap = get_dev_pagemap(pte_pfn(pte),
- hmm_vma_walk->pgmap);
-   if (unlikely(!hmm_vma_walk->pgmap)) {
-   pte_unmap(ptep);
-   return -EBUSY;
-   }
-   }
-
/*
 * Since each architecture defines a struct page for the zero page, just
 * fall through and treat it like a normal page.
@@ -328,10 +307,6 @@ static int hmm_vma_handle_pte(struct mm_walk *walk, 
unsigned long addr,
return 0;
 
 fault:
-   if (hmm_vma_walk->pgmap) {
-   put_dev_pagemap(hmm_vma_walk->pgmap);
-   hmm_vma_walk->pgmap = NULL;
-   }
pte_unmap(ptep);
/* Fault any virtual address we were asked to fault */
return hmm_vma_fault(addr, end, fault, write_fault, walk);
@@ -418,16 +393,6 @@ static int hmm_vma_walk_pmd(pmd_t *pmdp,
return r;
}
}
-   if (hmm_vma_walk->pgmap) {
-   /*
-* We do put_dev_pagemap() here and not in hmm_vma_handle_pte()
-* so that we can leverage get_dev_pagemap() optimization which
-* will not re-take a reference on a pgmap if we already have
-* one.
-*/
-   put_dev_pagemap(hmm_vma_walk->pgmap);
-   hmm_vma_walk->pgmap = NULL;
-   }
pte_unmap(ptep - 1);
 
hmm_vma_walk->last = addr;
@@ -491,20 +456,9 @@ static int hmm_vma_walk_pud(pud_t *pudp, unsigned long 
start, unsigned long end,
}
 
pfn = pud_pfn(pud) + ((addr & ~PUD_MASK) >> PAGE_SHIFT);
-   for (i = 0; i < npages; ++i, ++pfn) {
-   hmm_vma_walk->pgmap = get_dev_pagemap(pfn,
- hmm_vma_walk->pgmap);
-   if (unlikely(!hmm_vma_walk->pgmap)) {
-   ret = -EBUSY;
-   goto out_unlock;
-   }
+   for (i = 0; i < npages; ++i, ++pfn)
pfns[i] = hmm_device_entry_from_pfn(range, pfn) |
  cpu_flags;
-   }
-   if (hmm_vma_walk->pgmap) {
-   put_dev_pagemap(hmm_vma_walk->pgmap);
-   hmm_vma_walk->pgmap = NULL;
-   }
hmm_vma_walk->last = end;
goto out_unlock;
}
-- 
2.25.2

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[PATCH v2 hmm 2/9] mm/hmm: return the fault type from hmm_pte_need_fault()

[Jason Gunthorpe]

From: Jason Gunthorpe 

Using two bools instead of flags return is not necessary and leads to
bugs. Returning a value is easier for the compiler to check and easier to
pass around the code flow.

Convert the two bools into flags and push the change to all callers.

Signed-off-by: Jason Gunthorpe 
---
 mm/hmm.c | 183 ---
 1 file changed, 81 insertions(+), 102 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index 3a2610e0713329..d208ddd351066f 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -32,6 +32,12 @@ struct hmm_vma_walk {
unsigned intflags;
 };
 
+enum {
+   HMM_NEED_FAULT = 1 << 0,
+   HMM_NEED_WRITE_FAULT = 1 << 1,
+   HMM_NEED_ALL_BITS = HMM_NEED_FAULT | HMM_NEED_WRITE_FAULT,
+};
+
 static int hmm_pfns_fill(unsigned long addr, unsigned long end,
struct hmm_range *range, enum hmm_pfn_value_e value)
 {
@@ -49,8 +55,7 @@ static int hmm_pfns_fill(unsigned long addr, unsigned long 
end,
  * hmm_vma_fault() - fault in a range lacking valid pmd or pte(s)
  * @addr: range virtual start address (inclusive)
  * @end: range virtual end address (exclusive)
- * @fault: should we fault or not ?
- * @write_fault: write fault ?
+ * @required_fault: HMM_NEED_* flags
  * @walk: mm_walk structure
  * Return: -EBUSY after page fault, or page fault error
  *
@@ -58,8 +63,7 @@ static int hmm_pfns_fill(unsigned long addr, unsigned long 
end,
  * or whenever there is no page directory covering the virtual address range.
  */
 static int hmm_vma_fault(unsigned long addr, unsigned long end,
- bool fault, bool write_fault,
- struct mm_walk *walk)
+unsigned int required_fault, struct mm_walk *walk)
 {
struct hmm_vma_walk *hmm_vma_walk = walk->private;
struct hmm_range *range = hmm_vma_walk->range;
@@ -68,13 +72,13 @@ static int hmm_vma_fault(unsigned long addr, unsigned long 
end,
unsigned long i = (addr - range->start) >> PAGE_SHIFT;
unsigned int fault_flags = FAULT_FLAG_REMOTE;
 
-   WARN_ON_ONCE(!fault && !write_fault);
+   WARN_ON_ONCE(!required_fault);
hmm_vma_walk->last = addr;
 
if (!vma)
goto out_error;
 
-   if (write_fault) {
+   if (required_fault & HMM_NEED_WRITE_FAULT) {
if (!(vma->vm_flags & VM_WRITE))
return -EPERM;
fault_flags |= FAULT_FLAG_WRITE;
@@ -91,14 +95,13 @@ static int hmm_vma_fault(unsigned long addr, unsigned long 
end,
return -EFAULT;
 }
 
-static inline void hmm_pte_need_fault(const struct hmm_vma_walk *hmm_vma_walk,
- uint64_t pfns, uint64_t cpu_flags,
- bool *fault, bool *write_fault)
+static unsigned int hmm_pte_need_fault(const struct hmm_vma_walk *hmm_vma_walk,
+  uint64_t pfns, uint64_t cpu_flags)
 {
struct hmm_range *range = hmm_vma_walk->range;
 
if (hmm_vma_walk->flags & HMM_FAULT_SNAPSHOT)
-   return;
+   return 0;
 
/*
 * So we not only consider the individual per page request we also
@@ -114,37 +117,37 @@ static inline void hmm_pte_need_fault(const struct 
hmm_vma_walk *hmm_vma_walk,
 
/* We aren't ask to do anything ... */
if (!(pfns & range->flags[HMM_PFN_VALID]))
-   return;
+   return 0;
 
-   /* If CPU page table is not valid then we need to fault */
-   *fault = !(cpu_flags & range->flags[HMM_PFN_VALID]);
/* Need to write fault ? */
if ((pfns & range->flags[HMM_PFN_WRITE]) &&
-   !(cpu_flags & range->flags[HMM_PFN_WRITE])) {
-   *write_fault = true;
-   *fault = true;
-   }
+   !(cpu_flags & range->flags[HMM_PFN_WRITE]))
+   return HMM_NEED_FAULT | HMM_NEED_WRITE_FAULT;
+
+   /* If CPU page table is not valid then we need to fault */
+   if (!(cpu_flags & range->flags[HMM_PFN_VALID]))
+   return HMM_NEED_FAULT;
+   return 0;
 }
 
-static void hmm_range_need_fault(const struct hmm_vma_walk *hmm_vma_walk,
-const uint64_t *pfns, unsigned long npages,
-uint64_t cpu_flags, bool *fault,
-bool *write_fault)
+static unsigned int
+hmm_range_need_fault(const struct hmm_vma_walk *hmm_vma_walk,
+const uint64_t *pfns, unsigned long npages,
+uint64_t cpu_flags)
 {
+   unsigned int required_fault = 0;
unsigned long i;
 
-   if (hmm_vma_walk->flags & HMM_FAULT_SNAPSHOT) {
-   *fault = *write_fault = false;
-   return;
-   }
+   if (hmm_vma_walk->flags & HMM_FAULT_SNAPSHOT)
+   return 0;
 
-   *fault = *write_fault = false;
for (i = 0; i < npages; ++i) {
-   

[PATCH v2 hmm 6/9] mm/hmm: use device_private_entry_to_pfn()

[Jason Gunthorpe]

From: Jason Gunthorpe 

swp_offset() should not be called directly, the wrappers are supposed to
abstract away the encoding of the device_private specific information in
the swap entry.

Reviewed-by: Ralph Campbell 
Reviewed-by: Christoph Hellwig 
Tested-by: Ralph Campbell 
Signed-off-by: Jason Gunthorpe 
---
 mm/hmm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index 3a71ec72b0a42f..3303686bf16d24 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -261,7 +261,7 @@ static int hmm_vma_handle_pte(struct mm_walk *walk, 
unsigned long addr,
 */
if (hmm_is_device_private_entry(range, entry)) {
*pfn = hmm_device_entry_from_pfn(range,
-   swp_offset(entry));
+   device_private_entry_to_pfn(entry));
*pfn |= range->flags[HMM_PFN_VALID];
if (is_write_device_private_entry(entry))
*pfn |= range->flags[HMM_PFN_WRITE];
-- 
2.25.2

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[PATCH v2 hmm 7/9] mm/hmm: do not unconditionally set pfns when returning EBUSY

[Jason Gunthorpe]

From: Jason Gunthorpe 

In hmm_vma_handle_pte() and hmm_vma_walk_hugetlb_entry() if fault happens
then -EBUSY will be returned and the pfns input flags will have been
destroyed.

For hmm_vma_handle_pte() set HMM_PFN_NONE only on the success returns that
don't otherwise store to pfns.

For hmm_vma_walk_hugetlb_entry() all exit paths already set pfns, so
remove the redundant store.

Fixes: 2aee09d8c116 ("mm/hmm: change hmm_vma_fault() to allow write fault on 
page basis")
Reviewed-by: Christoph Hellwig 
Signed-off-by: Jason Gunthorpe 
---
 mm/hmm.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index 3303686bf16d24..dc826898979bc5 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -244,11 +244,11 @@ static int hmm_vma_handle_pte(struct mm_walk *walk, 
unsigned long addr,
pte_t pte = *ptep;
uint64_t orig_pfn = *pfn;
 
-   *pfn = range->values[HMM_PFN_NONE];
if (pte_none(pte)) {
required_fault = hmm_pte_need_fault(hmm_vma_walk, orig_pfn, 0);
if (required_fault)
goto fault;
+   *pfn = range->values[HMM_PFN_NONE];
return 0;
}
 
@@ -269,8 +269,10 @@ static int hmm_vma_handle_pte(struct mm_walk *walk, 
unsigned long addr,
}
 
required_fault = hmm_pte_need_fault(hmm_vma_walk, orig_pfn, 0);
-   if (!required_fault)
+   if (!required_fault) {
+   *pfn = range->values[HMM_PFN_NONE];
return 0;
+   }
 
if (!non_swap_entry(entry))
goto fault;
@@ -488,7 +490,6 @@ static int hmm_vma_walk_hugetlb_entry(pte_t *pte, unsigned 
long hmask,
 
i = (start - range->start) >> PAGE_SHIFT;
orig_pfn = range->pfns[i];
-   range->pfns[i] = range->values[HMM_PFN_NONE];
cpu_flags = pte_to_hmm_pfn_flags(range, entry);
required_fault = hmm_pte_need_fault(hmm_vma_walk, orig_pfn, cpu_flags);
if (required_fault) {
-- 
2.25.2

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[PATCH v2 hmm 9/9] mm/hmm: return error for non-vma snapshots

[Jason Gunthorpe]

From: Jason Gunthorpe 

The pagewalker does not call most ops with NULL vma, those are all routed
to hmm_vma_walk_hole() via ops->pte_hole instead.

Thus hmm_vma_fault() is only called with a NULL vma from
hmm_vma_walk_hole(), so hoist the NULL vma check to there.

Now it is clear that snapshotting with no vma is a HMM_PFN_ERROR as
without a vma we have no path to call hmm_vma_fault().

Reviewed-by: Christoph Hellwig 
Signed-off-by: Jason Gunthorpe 
---
 mm/hmm.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index e875d9ef0968fd..31d0f68689c32b 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -83,9 +83,6 @@ static int hmm_vma_fault(unsigned long addr, unsigned long 
end,
WARN_ON_ONCE(!required_fault);
hmm_vma_walk->last = addr;
 
-   if (!vma)
-   return -EFAULT;
-
if (required_fault & HMM_NEED_WRITE_FAULT) {
if (!(vma->vm_flags & VM_WRITE))
return -EPERM;
@@ -170,6 +167,11 @@ static int hmm_vma_walk_hole(unsigned long addr, unsigned 
long end,
npages = (end - addr) >> PAGE_SHIFT;
pfns = >pfns[i];
required_fault = hmm_range_need_fault(hmm_vma_walk, pfns, npages, 0);
+   if (!walk->vma) {
+   if (required_fault)
+   return -EFAULT;
+   return hmm_pfns_fill(addr, end, range, HMM_PFN_ERROR);
+   }
if (required_fault)
return hmm_vma_fault(addr, end, required_fault, walk);
hmm_vma_walk->last = addr;
-- 
2.25.2

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[PATCH v2 hmm 4/9] mm/hmm: remove HMM_FAULT_SNAPSHOT

[Jason Gunthorpe]

From: Jason Gunthorpe 

Now that flags are handled on a fine-grained per-page basis this global
flag is redundant and has a confusing overlap with the pfn_flags_mask and
default_flags.

Normalize the HMM_FAULT_SNAPSHOT behavior into one place. Callers needing
the SNAPSHOT behavior should set a pfn_flags_mask and default_flags that
always results in a cleared HMM_PFN_VALID. Then no pages will be faulted,
and HMM_FAULT_SNAPSHOT is not a special flow that overrides the masking
mechanism.

As this is the last flag, also remove the flags argument. If future flags
are needed they can be part of the struct hmm_range function arguments.

Signed-off-by: Jason Gunthorpe 
---
 Documentation/vm/hmm.rst| 12 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 +-
 drivers/gpu/drm/nouveau/nouveau_svm.c   |  2 +-
 include/linux/hmm.h |  5 +
 mm/hmm.c| 17 +
 5 files changed, 17 insertions(+), 21 deletions(-)

diff --git a/Documentation/vm/hmm.rst b/Documentation/vm/hmm.rst
index 95fec596836262..4e3e9362afeb10 100644
--- a/Documentation/vm/hmm.rst
+++ b/Documentation/vm/hmm.rst
@@ -161,13 +161,11 @@ device must complete the update before the driver 
callback returns.
 When the device driver wants to populate a range of virtual addresses, it can
 use::
 
-  long hmm_range_fault(struct hmm_range *range, unsigned int flags);
+  long hmm_range_fault(struct hmm_range *range);
 
-With the HMM_RANGE_SNAPSHOT flag, it will only fetch present CPU page table
-entries and will not trigger a page fault on missing or non-present entries.
-Without that flag, it does trigger a page fault on missing or read-only entries
-if write access is requested (see below). Page faults use the generic mm page
-fault code path just like a CPU page fault.
+It will trigger a page fault on missing or read-only entries if write access is
+requested (see below). Page faults use the generic mm page fault code path just
+like a CPU page fault.
 
 Both functions copy CPU page table entries into their pfns array argument. Each
 entry in that array corresponds to an address in the virtual range. HMM
@@ -197,7 +195,7 @@ The usage pattern is::
  again:
   range.notifier_seq = mmu_interval_read_begin(_sub);
   down_read(>mmap_sem);
-  ret = hmm_range_fault(, HMM_RANGE_SNAPSHOT);
+  ret = hmm_range_fault();
   if (ret) {
   up_read(>mmap_sem);
   if (ret == -EBUSY)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 90821ce5e6cad0..c520290709371b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -856,7 +856,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
struct page **pages)
range->notifier_seq = mmu_interval_read_begin(>notifier);
 
down_read(>mmap_sem);
-   r = hmm_range_fault(range, 0);
+   r = hmm_range_fault(range);
up_read(>mmap_sem);
if (unlikely(r <= 0)) {
/*
diff --git a/drivers/gpu/drm/nouveau/nouveau_svm.c 
b/drivers/gpu/drm/nouveau/nouveau_svm.c
index 39c731a99937c6..e3797b2d4d1759 100644
--- a/drivers/gpu/drm/nouveau/nouveau_svm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_svm.c
@@ -540,7 +540,7 @@ static int nouveau_range_fault(struct nouveau_svmm *svmm,
range.default_flags = 0;
range.pfn_flags_mask = -1UL;
down_read(>mmap_sem);
-   ret = hmm_range_fault(, 0);
+   ret = hmm_range_fault();
up_read(>mmap_sem);
if (ret <= 0) {
if (ret == 0 || ret == -EBUSY)
diff --git a/include/linux/hmm.h b/include/linux/hmm.h
index daee6508a3f609..7475051100c782 100644
--- a/include/linux/hmm.h
+++ b/include/linux/hmm.h
@@ -117,13 +117,10 @@ static inline struct page *hmm_device_entry_to_page(const 
struct hmm_range *rang
return pfn_to_page(entry >> range->pfn_shift);
 }
 
-/* Don't fault in missing PTEs, just snapshot the current state. */
-#define HMM_FAULT_SNAPSHOT (1 << 1)
-
 /*
  * Please see Documentation/vm/hmm.rst for how to use the range API.
  */
-long hmm_range_fault(struct hmm_range *range, unsigned int flags);
+long hmm_range_fault(struct hmm_range *range);
 
 /*
  * HMM_RANGE_DEFAULT_TIMEOUT - default timeout (ms) when waiting for a range
diff --git a/mm/hmm.c b/mm/hmm.c
index 136de474221d77..8dbd9e1d0308b4 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -29,7 +29,6 @@
 struct hmm_vma_walk {
struct hmm_range*range;
unsigned long   last;
-   unsigned intflags;
 };
 
 enum {
@@ -112,9 +111,6 @@ static unsigned int hmm_pte_need_fault(const struct 
hmm_vma_walk *hmm_vma_walk,
 {
struct hmm_range *range = hmm_vma_walk->range;
 
-   if (hmm_vma_walk->flags & HMM_FAULT_SNAPSHOT)
-   return 0;
-
/*
 * So we not only consider the individual per page 

Re: [PATCH 4/4] drm/amdgpu: replace ih ip block for vega20 and arcturus

[Felix Kuehling]

On 2020-03-27 15:37, Alex Sierra wrote:

[Why]
Vega20 and Arcturus asics use oss 5.0 version.

[How]
Replace ih ip block by navi10 for vega20 and arcturus.

Signed-off-by: Alex Sierra 


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdgpu/soc15.c | 15 +++
  1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index a8c90d83a9ee..9bd965e88bd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -62,6 +62,7 @@
  #include "nbio_v7_0.h"
  #include "nbio_v7_4.h"
  #include "vega10_ih.h"
+#include "navi10_ih.h"
  #include "sdma_v4_0.h"
  #include "uvd_v7_0.h"
  #include "vce_v4_0.h"
@@ -731,9 +732,15 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
else
amdgpu_device_ip_block_add(adev, 
_v3_1_ip_block);
}
-   amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   if (adev->asic_type == CHIP_VEGA20)
+   amdgpu_device_ip_block_add(adev, 
_ih_ip_block);
+   else
+   amdgpu_device_ip_block_add(adev, 
_ih_ip_block);
} else {
-   amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   if (adev->asic_type == CHIP_VEGA20)
+   amdgpu_device_ip_block_add(adev, 
_ih_ip_block);
+   else
+   amdgpu_device_ip_block_add(adev, 
_ih_ip_block);
if (likely(adev->firmware.load_type == 
AMDGPU_FW_LOAD_PSP)) {
if (adev->asic_type == CHIP_VEGA20)
amdgpu_device_ip_block_add(adev, 
_v11_0_ip_block);
@@ -784,9 +791,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev)) {
if (likely(adev->firmware.load_type == 
AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev, 
_v11_0_ip_block);
-   amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _ih_ip_block);
} else {
-   amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _ih_ip_block);
if (likely(adev->firmware.load_type == 
AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev, 
_v11_0_ip_block);
}

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Re: [PATCH] drm/amdgpu: ih doorbell size of range changed for nbio v7.4

[Felix Kuehling]

On 2020-03-27 15:32, Alex Sierra wrote:

[Why]
nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per 
register.

[How]
Change ih doorbell size from 2 to 4. This means two Dwords per ring.
Current configuration uses two ih rings.

Signed-off-by: Alex Sierra 
Acked-by: Alex Deucher 


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 41c53c149852..72bdd06ed508 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -185,7 +185,7 @@ static void nbio_v7_4_ih_doorbell_range(struct 
amdgpu_device *adev,
  
  	if (use_doorbell) {

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
-   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 2);
+   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 4);
} else
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 0);
  

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Re: [PATCH] drm/amdgpu: infinite retries fix from UTLC1 RB SDMA

[Felix Kuehling]

On 2020-03-27 15:31, Alex Sierra wrote:

[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB.

[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Vega10, Vega12,
Vega20 and Arcturus.

Signed-off-by: Alex Sierra 
Acked-by: Alex Deucher 


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 +---
  1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 646e43c205b8..55ae4e6c4939 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -115,17 +115,21 @@ static const struct soc15_reg_golden 
golden_settings_sdma_4[] = {
  static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 
0x00104002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831d07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 
0x00104002),
-   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002)
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
  };
  
  static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 
0x00104001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831d07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 
0x00104001),
-   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001)
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
  };
  
  static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {

@@ -174,6 +178,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma0_4_2[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 
0xfffd, 0x0001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 
0xfff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x03ff, 
0x03c0),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
  };
  
  static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {

@@ -203,6 +208,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma1_4_2[] = {
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 
0xfffd, 0x0001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 
0xfff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x03ff, 
0x03c0),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
  };
  
  static const struct soc15_reg_golden golden_settings_sdma_rv1[] =

@@ -222,27 +228,35 @@ static const struct soc15_reg_golden 
golden_settings_sdma_arct[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x773f, 
0x4002),

[PATCH 4/4] drm/amdgpu: replace ih ip block for vega20 and arcturus

[Alex Sierra]

[Why]
Vega20 and Arcturus asics use oss 5.0 version.

[How]
Replace ih ip block by navi10 for vega20 and arcturus.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 15 +++
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index a8c90d83a9ee..9bd965e88bd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -62,6 +62,7 @@
 #include "nbio_v7_0.h"
 #include "nbio_v7_4.h"
 #include "vega10_ih.h"
+#include "navi10_ih.h"
 #include "sdma_v4_0.h"
 #include "uvd_v7_0.h"
 #include "vce_v4_0.h"
@@ -731,9 +732,15 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
else
amdgpu_device_ip_block_add(adev, 
_v3_1_ip_block);
}
-   amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   if (adev->asic_type == CHIP_VEGA20)
+   amdgpu_device_ip_block_add(adev, 
_ih_ip_block);
+   else
+   amdgpu_device_ip_block_add(adev, 
_ih_ip_block);
} else {
-   amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   if (adev->asic_type == CHIP_VEGA20)
+   amdgpu_device_ip_block_add(adev, 
_ih_ip_block);
+   else
+   amdgpu_device_ip_block_add(adev, 
_ih_ip_block);
if (likely(adev->firmware.load_type == 
AMDGPU_FW_LOAD_PSP)) {
if (adev->asic_type == CHIP_VEGA20)
amdgpu_device_ip_block_add(adev, 
_v11_0_ip_block);
@@ -784,9 +791,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev)) {
if (likely(adev->firmware.load_type == 
AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev, 
_v11_0_ip_block);
-   amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _ih_ip_block);
} else {
-   amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   amdgpu_device_ip_block_add(adev, _ih_ip_block);
if (likely(adev->firmware.load_type == 
AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev, 
_v11_0_ip_block);
}
-- 
2.17.1

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[PATCH 3/4] drm/amdgpu: reroute VMC and UMD to IH ring 1 for oss v5

[Alex Sierra]

[Why]
Due Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.
It also facilitates the recovery page process, since it's already
running from a process context.
This is valid for Arcturus and future Navi generation GPUs.

[How]
Setting IH_CLIENT_CFG_DATA for VMC and UMD IH clients.

Signed-off-by: Alex Sierra 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 4ce42635787a..6fca5206833d 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -205,6 +205,24 @@ static uint32_t navi10_ih_doorbell_rptr(struct 
amdgpu_ih_ring *ih)
return ih_doorbell_rtpr;
 }
 
+static void navi10_ih_reroute_ih(struct amdgpu_device *adev)
+{
+   uint32_t tmp;
+
+   /* Reroute to IH ring 1 for VMC */
+   WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
+   tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+   WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
+
+   /* Reroute IH ring 1 for UMC */
+   WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
+   tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+   WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
+}
+
 /**
  * navi10_ih_irq_init - init and enable the interrupt ring
  *
@@ -243,6 +261,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
} else {
WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
}
+   navi10_ih_reroute_ih(adev);
 
if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
if (ih->use_bus_addr) {
-- 
2.17.1

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[PATCH 2/4] drm/amdgpu: call psp to program ih cntl in SR-IOV for Navi

[Alex Sierra]

call psp to program ih cntl in SR-IOV if supported on Navi and Arcturus.

Signed-off-by: Alex Sierra 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 90 +++---
 1 file changed, 80 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 0c0ba572d7a3..4ce42635787a 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -49,14 +49,30 @@ static void navi10_ih_enable_interrupts(struct 
amdgpu_device *adev)
 
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
+   if (amdgpu_sriov_vf(adev)) {
+   if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL, 
ih_rb_cntl)) {
+   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
+   }
+
adev->irq.ih.enabled = true;
 
if (adev->irq.ih1.ring_size) {
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
   RB_ENABLE, 1);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   if (amdgpu_sriov_vf(adev)) {
+   if (psp_reg_program(>psp, 
PSP_REG_IH_RB_CNTL_RING1,
+   ih_rb_cntl)) {
+   DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   }
adev->irq.ih1.enabled = true;
}
 
@@ -64,7 +80,15 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device 
*adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
   RB_ENABLE, 1);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   if (amdgpu_sriov_vf(adev)) {
+   if (psp_reg_program(>psp, 
PSP_REG_IH_RB_CNTL_RING2,
+   ih_rb_cntl)) {
+   DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   }
adev->irq.ih2.enabled = true;
}
 }
@@ -82,7 +106,15 @@ static void navi10_ih_disable_interrupts(struct 
amdgpu_device *adev)
 
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
+   if (amdgpu_sriov_vf(adev)) {
+   if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL, 
ih_rb_cntl)) {
+   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
+   }
+
/* set rptr, wptr to 0 */
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
@@ -93,7 +125,15 @@ static void navi10_ih_disable_interrupts(struct 
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
   RB_ENABLE, 0);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   if (amdgpu_sriov_vf(adev)) {
+   if (psp_reg_program(>psp, 
PSP_REG_IH_RB_CNTL_RING1,
+   ih_rb_cntl)) {
+   DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   }
/* set rptr, wptr to 0 */
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
@@ -105,7 +145,15 @@ static void navi10_ih_disable_interrupts(struct 
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
   RB_ENABLE, 0);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+  

[PATCH] drm/amdgpu: ih doorbell size of range changed for nbio v7.4

[Alex Sierra]

[Why]
nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per 
register.

[How]
Change ih doorbell size from 2 to 4. This means two Dwords per ring.
Current configuration uses two ih rings.

Signed-off-by: Alex Sierra 
Acked-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 41c53c149852..72bdd06ed508 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -185,7 +185,7 @@ static void nbio_v7_4_ih_doorbell_range(struct 
amdgpu_device *adev,
 
if (use_doorbell) {
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
-   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 2);
+   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 4);
} else
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 0);
 
-- 
2.17.1

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[PATCH] drm/amdgpu: infinite retries fix from UTLC1 RB SDMA

[Alex Sierra]

[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB.

[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Vega10, Vega12,
Vega20 and Arcturus.

Signed-off-by: Alex Sierra 
Acked-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 646e43c205b8..55ae4e6c4939 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -115,17 +115,21 @@ static const struct soc15_reg_golden 
golden_settings_sdma_4[] = {
 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 
0x00104002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831d07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 
0x00104002),
-   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002)
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
 };
 
 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 
0x00104001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831d07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 
0x00104001),
-   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001)
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
 };
 
 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
@@ -174,6 +178,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma0_4_2[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 
0xfffd, 0x0001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 
0xfff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x03ff, 
0x03c0),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
 };
 
 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
@@ -203,6 +208,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma1_4_2[] = {
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 
0xfffd, 0x0001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 
0xfff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x03ff, 
0x03c0),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
 };
 
 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
@@ -222,27 +228,35 @@ static const struct soc15_reg_golden 
golden_settings_sdma_arct[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   

Re: [PATCH 6/6] drm/radeon: convert to use i2c_new_client_device()

[Sam Ravnborg]

On Fri, Mar 27, 2020 at 04:45:09PM +0100, Wolfram Sang wrote:
> 
> > > > > Move away from the deprecated API.
> > > > >
> > > > > Signed-off-by: Wolfram Sang 
> > > >
> > > > patches 1,6, are:
> > > > Acked-by: Alex Deucher 
> > > Should we commit all to drm-misc-next?
> > 
> > I'm fine to see it go through whatever tree makes sense.
> 
> I'd suggest drm-misc-next to minimize merge conflicts. But I can take it
> via I2C tree, too, if desired.

If no-one else speaks up until tomorrow I will land them in
drm-misc-next.
Just wanted to make sure it was OK.

Sam
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Re: [PATCH 6/6] drm/radeon: convert to use i2c_new_client_device()

[Wolfram Sang]

> > > > Move away from the deprecated API.
> > > >
> > > > Signed-off-by: Wolfram Sang 
> > >
> > > patches 1,6, are:
> > > Acked-by: Alex Deucher 
> > Should we commit all to drm-misc-next?
> 
> I'm fine to see it go through whatever tree makes sense.

I'd suggest drm-misc-next to minimize merge conflicts. But I can take it
via I2C tree, too, if desired.



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Re: [PATCH 6/6] drm/radeon: convert to use i2c_new_client_device()

[Alex Deucher]

On Fri, Mar 27, 2020 at 11:25 AM Sam Ravnborg  wrote:
>
> On Fri, Mar 27, 2020 at 10:25:16AM -0400, Alex Deucher wrote:
> > On Thu, Mar 26, 2020 at 5:35 PM Wolfram Sang
> >  wrote:
> > >
> > > Move away from the deprecated API.
> > >
> > > Signed-off-by: Wolfram Sang 
> >
> > patches 1,6, are:
> > Acked-by: Alex Deucher 
> Should we commit all to drm-misc-next?

I'm fine to see it go through whatever tree makes sense.

Alex


>
> Sam
>
>
> >
> > > ---
> > >  drivers/gpu/drm/radeon/radeon_atombios.c | 4 ++--
> > >  drivers/gpu/drm/radeon/radeon_combios.c  | 4 ++--
> > >  2 files changed, 4 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
> > > b/drivers/gpu/drm/radeon/radeon_atombios.c
> > > index 848ef68d9086..5d2591725189 100644
> > > --- a/drivers/gpu/drm/radeon/radeon_atombios.c
> > > +++ b/drivers/gpu/drm/radeon/radeon_atombios.c
> > > @@ -2111,7 +2111,7 @@ static int 
> > > radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
> > > 
> > > ucOverdriveThermalController];
> > > info.addr = 
> > > power_info->info.ucOverdriveControllerAddress >> 1;
> > > strlcpy(info.type, name, sizeof(info.type));
> > > -   i2c_new_device(>pm.i2c_bus->adapter, );
> > > +   i2c_new_client_device(>pm.i2c_bus->adapter, 
> > > );
> > > }
> > > }
> > > num_modes = power_info->info.ucNumOfPowerModeEntries;
> > > @@ -2351,7 +2351,7 @@ static void 
> > > radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
> > > const char *name = 
> > > pp_lib_thermal_controller_names[controller->ucType];
> > > info.addr = controller->ucI2cAddress >> 1;
> > > strlcpy(info.type, name, 
> > > sizeof(info.type));
> > > -   
> > > i2c_new_device(>pm.i2c_bus->adapter, );
> > > +   
> > > i2c_new_client_device(>pm.i2c_bus->adapter, );
> > > }
> > > } else {
> > > DRM_INFO("Unknown thermal controller type %d at 
> > > 0x%02x %s fan control\n",
> > > diff --git a/drivers/gpu/drm/radeon/radeon_combios.c 
> > > b/drivers/gpu/drm/radeon/radeon_combios.c
> > > index c3e49c973812..d3c04df7e75d 100644
> > > --- a/drivers/gpu/drm/radeon/radeon_combios.c
> > > +++ b/drivers/gpu/drm/radeon/radeon_combios.c
> > > @@ -2704,7 +2704,7 @@ void radeon_combios_get_power_modes(struct 
> > > radeon_device *rdev)
> > > const char *name = 
> > > thermal_controller_names[thermal_controller];
> > > info.addr = i2c_addr >> 1;
> > > strlcpy(info.type, name, 
> > > sizeof(info.type));
> > > -   
> > > i2c_new_device(>pm.i2c_bus->adapter, );
> > > +   
> > > i2c_new_client_device(>pm.i2c_bus->adapter, );
> > > }
> > > }
> > > } else {
> > > @@ -2721,7 +2721,7 @@ void radeon_combios_get_power_modes(struct 
> > > radeon_device *rdev)
> > > const char *name = "f75375";
> > > info.addr = 0x28;
> > > strlcpy(info.type, name, 
> > > sizeof(info.type));
> > > -   
> > > i2c_new_device(>pm.i2c_bus->adapter, );
> > > +   
> > > i2c_new_client_device(>pm.i2c_bus->adapter, );
> > > DRM_INFO("Possible %s thermal controller 
> > > at 0x%02x\n",
> > >  name, info.addr);
> > > }
> > > --
> > > 2.20.1
> > >
> > > ___
> > > dri-devel mailing list
> > > dri-de...@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> > ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [PATCH 6/6] drm/radeon: convert to use i2c_new_client_device()

[Sam Ravnborg]

On Fri, Mar 27, 2020 at 10:25:16AM -0400, Alex Deucher wrote:
> On Thu, Mar 26, 2020 at 5:35 PM Wolfram Sang
>  wrote:
> >
> > Move away from the deprecated API.
> >
> > Signed-off-by: Wolfram Sang 
> 
> patches 1,6, are:
> Acked-by: Alex Deucher 
Should we commit all to drm-misc-next?

Sam


> 
> > ---
> >  drivers/gpu/drm/radeon/radeon_atombios.c | 4 ++--
> >  drivers/gpu/drm/radeon/radeon_combios.c  | 4 ++--
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
> > b/drivers/gpu/drm/radeon/radeon_atombios.c
> > index 848ef68d9086..5d2591725189 100644
> > --- a/drivers/gpu/drm/radeon/radeon_atombios.c
> > +++ b/drivers/gpu/drm/radeon/radeon_atombios.c
> > @@ -2111,7 +2111,7 @@ static int 
> > radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
> > 
> > ucOverdriveThermalController];
> > info.addr = 
> > power_info->info.ucOverdriveControllerAddress >> 1;
> > strlcpy(info.type, name, sizeof(info.type));
> > -   i2c_new_device(>pm.i2c_bus->adapter, );
> > +   i2c_new_client_device(>pm.i2c_bus->adapter, 
> > );
> > }
> > }
> > num_modes = power_info->info.ucNumOfPowerModeEntries;
> > @@ -2351,7 +2351,7 @@ static void 
> > radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
> > const char *name = 
> > pp_lib_thermal_controller_names[controller->ucType];
> > info.addr = controller->ucI2cAddress >> 1;
> > strlcpy(info.type, name, sizeof(info.type));
> > -   i2c_new_device(>pm.i2c_bus->adapter, 
> > );
> > +   
> > i2c_new_client_device(>pm.i2c_bus->adapter, );
> > }
> > } else {
> > DRM_INFO("Unknown thermal controller type %d at 
> > 0x%02x %s fan control\n",
> > diff --git a/drivers/gpu/drm/radeon/radeon_combios.c 
> > b/drivers/gpu/drm/radeon/radeon_combios.c
> > index c3e49c973812..d3c04df7e75d 100644
> > --- a/drivers/gpu/drm/radeon/radeon_combios.c
> > +++ b/drivers/gpu/drm/radeon/radeon_combios.c
> > @@ -2704,7 +2704,7 @@ void radeon_combios_get_power_modes(struct 
> > radeon_device *rdev)
> > const char *name = 
> > thermal_controller_names[thermal_controller];
> > info.addr = i2c_addr >> 1;
> > strlcpy(info.type, name, sizeof(info.type));
> > -   i2c_new_device(>pm.i2c_bus->adapter, 
> > );
> > +   
> > i2c_new_client_device(>pm.i2c_bus->adapter, );
> > }
> > }
> > } else {
> > @@ -2721,7 +2721,7 @@ void radeon_combios_get_power_modes(struct 
> > radeon_device *rdev)
> > const char *name = "f75375";
> > info.addr = 0x28;
> > strlcpy(info.type, name, sizeof(info.type));
> > -   i2c_new_device(>pm.i2c_bus->adapter, 
> > );
> > +   
> > i2c_new_client_device(>pm.i2c_bus->adapter, );
> > DRM_INFO("Possible %s thermal controller at 
> > 0x%02x\n",
> >  name, info.addr);
> > }
> > --
> > 2.20.1
> >
> > ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
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Re: [PATCH 6/6] drm/radeon: convert to use i2c_new_client_device()

[Alex Deucher]

On Thu, Mar 26, 2020 at 5:35 PM Wolfram Sang
 wrote:
>
> Move away from the deprecated API.
>
> Signed-off-by: Wolfram Sang 

patches 1,6, are:
Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/radeon/radeon_atombios.c | 4 ++--
>  drivers/gpu/drm/radeon/radeon_combios.c  | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
> b/drivers/gpu/drm/radeon/radeon_atombios.c
> index 848ef68d9086..5d2591725189 100644
> --- a/drivers/gpu/drm/radeon/radeon_atombios.c
> +++ b/drivers/gpu/drm/radeon/radeon_atombios.c
> @@ -2111,7 +2111,7 @@ static int radeon_atombios_parse_power_table_1_3(struct 
> radeon_device *rdev)
> 
> ucOverdriveThermalController];
> info.addr = 
> power_info->info.ucOverdriveControllerAddress >> 1;
> strlcpy(info.type, name, sizeof(info.type));
> -   i2c_new_device(>pm.i2c_bus->adapter, );
> +   i2c_new_client_device(>pm.i2c_bus->adapter, 
> );
> }
> }
> num_modes = power_info->info.ucNumOfPowerModeEntries;
> @@ -2351,7 +2351,7 @@ static void 
> radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
> const char *name = 
> pp_lib_thermal_controller_names[controller->ucType];
> info.addr = controller->ucI2cAddress >> 1;
> strlcpy(info.type, name, sizeof(info.type));
> -   i2c_new_device(>pm.i2c_bus->adapter, 
> );
> +   
> i2c_new_client_device(>pm.i2c_bus->adapter, );
> }
> } else {
> DRM_INFO("Unknown thermal controller type %d at 
> 0x%02x %s fan control\n",
> diff --git a/drivers/gpu/drm/radeon/radeon_combios.c 
> b/drivers/gpu/drm/radeon/radeon_combios.c
> index c3e49c973812..d3c04df7e75d 100644
> --- a/drivers/gpu/drm/radeon/radeon_combios.c
> +++ b/drivers/gpu/drm/radeon/radeon_combios.c
> @@ -2704,7 +2704,7 @@ void radeon_combios_get_power_modes(struct 
> radeon_device *rdev)
> const char *name = 
> thermal_controller_names[thermal_controller];
> info.addr = i2c_addr >> 1;
> strlcpy(info.type, name, sizeof(info.type));
> -   i2c_new_device(>pm.i2c_bus->adapter, 
> );
> +   
> i2c_new_client_device(>pm.i2c_bus->adapter, );
> }
> }
> } else {
> @@ -2721,7 +2721,7 @@ void radeon_combios_get_power_modes(struct 
> radeon_device *rdev)
> const char *name = "f75375";
> info.addr = 0x28;
> strlcpy(info.type, name, sizeof(info.type));
> -   i2c_new_device(>pm.i2c_bus->adapter, 
> );
> +   
> i2c_new_client_device(>pm.i2c_bus->adapter, );
> DRM_INFO("Possible %s thermal controller at 
> 0x%02x\n",
>  name, info.addr);
> }
> --
> 2.20.1
>
> ___
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> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [PATCH 2/2] drm/amd/powerplay: move the ASIC specific nbio operation out of smu_v11_0.c

[Deucher, Alexander]

[AMD Public Use]

Series is:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Evan Quan 

Sent: Friday, March 27, 2020 3:57 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Quan, Evan 
Subject: [PATCH 2/2] drm/amd/powerplay: move the ASIC specific nbio operation 
out of smu_v11_0.c

This is ASIC specific and should be placed in _ppt.c of each ASIC.

Change-Id: If2b29ccf0dfc0dc90e1636a806b13ce2efed58c6
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 15 ++-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c   | 18 --
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c| 10 +-
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c   | 14 +-
 4 files changed, 44 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index c6d3bef15320..5db8c56066ee 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -35,6 +35,7 @@
 #include "arcturus_ppt.h"
 #include "smu_v11_0_pptable.h"
 #include "arcturus_ppsmc.h"
+#include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
 #include "amdgpu_xgmi.h"
 #include 
@@ -2210,6 +2211,18 @@ static void arcturus_i2c_eeprom_control_fini(struct 
i2c_adapter *control)
 i2c_del_adapter(control);
 }

+static bool arcturus_is_baco_supported(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+   uint32_t val;
+
+   if (!smu_v11_0_baco_is_support(smu))
+   return false;
+
+   val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+   return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+}
+
 static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
 {
 PPTable_t *pptable = smu->smu_table.driver_pptable;
@@ -2321,7 +2334,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
 .register_irq_handler = smu_v11_0_register_irq_handler,
 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
 .get_max_sustainable_clocks_by_dc = 
smu_v11_0_get_max_sustainable_clocks_by_dc,
-   .baco_is_support= smu_v11_0_baco_is_support,
+   .baco_is_support= arcturus_is_baco_supported,
 .baco_get_state = smu_v11_0_baco_get_state,
 .baco_set_state = smu_v11_0_baco_set_state,
 .baco_enter = smu_v11_0_baco_enter,
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 1112e4c5f4d7..c94270f7c198 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -28,13 +28,15 @@
 #include "smu_internal.h"
 #include "atomfirmware.h"
 #include "amdgpu_atomfirmware.h"
+#include "soc15_common.h"
 #include "smu_v11_0.h"
 #include "smu11_driver_if_navi10.h"
 #include "atom.h"
 #include "navi10_ppt.h"
 #include "smu_v11_0_pptable.h"
 #include "smu_v11_0_ppsmc.h"
-#include "nbio/nbio_7_4_sh_mask.h"
+#include "nbio/nbio_2_3_offset.h"
+#include "nbio/nbio_2_3_sh_mask.h"

 #include "asic_reg/mp/mp_11_0_sh_mask.h"

@@ -1942,6 +1944,18 @@ static int navi10_setup_od_limits(struct smu_context 
*smu) {
 return 0;
 }

+static bool navi10_is_baco_supported(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+   uint32_t val;
+
+   if (!smu_v11_0_baco_is_support(smu))
+   return false;
+
+   val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+   return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+}
+
 static int navi10_set_default_od_settings(struct smu_context *smu, bool 
initialize) {
 OverDriveTable_t *od_table, *boot_od_table;
 int ret = 0;
@@ -2318,7 +2332,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
 .register_irq_handler = smu_v11_0_register_irq_handler,
 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
 .get_max_sustainable_clocks_by_dc = 
smu_v11_0_get_max_sustainable_clocks_by_dc,
-   .baco_is_support= smu_v11_0_baco_is_support,
+   .baco_is_support= navi10_is_baco_supported,
 .baco_get_state = smu_v11_0_baco_get_state,
 .baco_set_state = smu_v11_0_baco_set_state,
 .baco_enter = smu_v11_0_baco_enter,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 31b93cff19d5..655ba4fb05dc 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -42,8 +42,6 @@
 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
 #include "asic_reg/mp/mp_11_0_offset.h"
 #include "asic_reg/mp/mp_11_0_sh_mask.h"
-#include "asic_reg/nbio/nbio_7_4_offset.h"
-#include "asic_reg/nbio/nbio_7_4_sh_mask.h"
 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"

@@ -1662,9 +1660,7 @@ static int smu_v11_0_baco_set_armd3_sequence(struct 
smu_context *smu, enum smu_v

 bool 

RE: [RFC PATCH 0/2] add direct IB pool

[Liu, Monk]

Bye the way: if you want to avoid IB test pending by GPU recover, you can move 
IB test out of TDR routine, so IB test will execute after GPU scheduler resumed 
with TDR completed .

_
Monk Liu|GPU Virtualization Team |AMD
[sig-cloud-gpu]

From: Pan, Xinhui 
Sent: Thursday, March 26, 2020 2:02 PM
To: amd-gfx@lists.freedesktop.org; Liu, Monk 
Cc: Deucher, Alexander ; Kuehling, Felix 
; Koenig, Christian 
Subject: Re: [RFC PATCH 0/2] add direct IB pool


[AMD Official Use Only - Internal Distribution Only]

yes, IB test and  vram restore will alloc IBs.
I hit this issue for quite a long time ago. We test benchmarks on ARM server 
which is running android.
Hunders of processes hit too many issues. Panic and memory corruption 
everywhere.
Now i have a littke time to fix this deadlock.
if you want to repro it, set gpu timeout to 50ms，then run vulkan,ocl, 
amdgputest, etc together.
I believe you will see more weird issues.

From: Liu, Monk mailto:monk@amd.com>>
Sent: Thursday, March 26, 2020 1:31:04 PM
To: Pan, Xinhui mailto:xinhui@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; Kuehling, Felix 
mailto:felix.kuehl...@amd.com>>; Pan, Xinhui 
mailto:xinhui@amd.com>>; Koenig, Christian 
mailto:christian.koe...@amd.com>>
Subject: RE: [RFC PATCH 0/2] add direct IB pool

That sounds a roughly doable plan to me , although we didn't hit this issue in 
our virtualization stress test but like a possible issue.

>>> So the ring test above got stuck if no ib to alloc.
Why there is IB alloc happened in ring test ? I remember there is no IB 
allocated for ring test, are you referring to IB test ?



_
Monk Liu|GPU Virtualization Team |AMD


-Original Message-
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of xinhui pan
Sent: Thursday, March 26, 2020 10:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; Kuehling, Felix 
mailto:felix.kuehl...@amd.com>>; Pan, Xinhui 
mailto:xinhui@amd.com>>; Koenig, Christian 
mailto:christian.koe...@amd.com>>
Subject: [RFC PATCH 0/2] add direct IB pool

druing gpu recovery, we alloc ibs for ring tests to test if recovery succeed or 
not.

As gpu recovery parked the gpu scheduler thread, any pending jobs hold the ib 
resource has no chance to free. So the ring test above got stuck if no ib to 
alloc.

If we schedule IBs directly in job_submit_direct, we can alloc ibs in the new 
ib pool. It should have less contention.

If the IB could be freed in time, IOW, not depending on any scheduler, nor any 
other blocking code. It is better to alloc ibs in direct pool.

xinhui pan (2):
  drm/amdgpu: add direct ib pool
  drm/amdgpu: use new job alloc variation if possible

 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 12 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   |  4 ++--
 13 files changed, 35 insertions(+), 18 deletions(-)

--
2.17.1

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RE: [RFC PATCH 0/2] add direct IB pool

[Liu, Monk]

Oh, 50ms … umm I can advice our IQE team to introduce this stress test option

Thanks

_
Monk Liu|GPU Virtualization Team |AMD
[sig-cloud-gpu]

From: Pan, Xinhui 
Sent: Thursday, March 26, 2020 2:02 PM
To: amd-gfx@lists.freedesktop.org; Liu, Monk 
Cc: Deucher, Alexander ; Kuehling, Felix 
; Koenig, Christian 
Subject: Re: [RFC PATCH 0/2] add direct IB pool


[AMD Official Use Only - Internal Distribution Only]

yes, IB test and  vram restore will alloc IBs.
I hit this issue for quite a long time ago. We test benchmarks on ARM server 
which is running android.
Hunders of processes hit too many issues. Panic and memory corruption 
everywhere.
Now i have a littke time to fix this deadlock.
if you want to repro it, set gpu timeout to 50ms，then run vulkan,ocl, 
amdgputest, etc together.
I believe you will see more weird issues.

From: Liu, Monk mailto:monk@amd.com>>
Sent: Thursday, March 26, 2020 1:31:04 PM
To: Pan, Xinhui mailto:xinhui@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; Kuehling, Felix 
mailto:felix.kuehl...@amd.com>>; Pan, Xinhui 
mailto:xinhui@amd.com>>; Koenig, Christian 
mailto:christian.koe...@amd.com>>
Subject: RE: [RFC PATCH 0/2] add direct IB pool

That sounds a roughly doable plan to me , although we didn't hit this issue in 
our virtualization stress test but like a possible issue.

>>> So the ring test above got stuck if no ib to alloc.
Why there is IB alloc happened in ring test ? I remember there is no IB 
allocated for ring test, are you referring to IB test ?



_
Monk Liu|GPU Virtualization Team |AMD


-Original Message-
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of xinhui pan
Sent: Thursday, March 26, 2020 10:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; Kuehling, Felix 
mailto:felix.kuehl...@amd.com>>; Pan, Xinhui 
mailto:xinhui@amd.com>>; Koenig, Christian 
mailto:christian.koe...@amd.com>>
Subject: [RFC PATCH 0/2] add direct IB pool

druing gpu recovery, we alloc ibs for ring tests to test if recovery succeed or 
not.

As gpu recovery parked the gpu scheduler thread, any pending jobs hold the ib 
resource has no chance to free. So the ring test above got stuck if no ib to 
alloc.

If we schedule IBs directly in job_submit_direct, we can alloc ibs in the new 
ib pool. It should have less contention.

If the IB could be freed in time, IOW, not depending on any scheduler, nor any 
other blocking code. It is better to alloc ibs in direct pool.

xinhui pan (2):
  drm/amdgpu: add direct ib pool
  drm/amdgpu: use new job alloc variation if possible

 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 12 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  8 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   |  4 ++--
 13 files changed, 35 insertions(+), 18 deletions(-)

--
2.17.1

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RE: [PATCH] drm/amdgpu: fix non-pointer dereference for non-RAS supported

[Clements, John]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: John Clements 

-Original Message-
From: Quan, Evan  
Sent: Friday, March 27, 2020 3:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Clements, John ; Quan, Evan 
Subject: [PATCH] drm/amdgpu: fix non-pointer dereference for non-RAS supported

Backtrace on gpu recover test on Navi10.

[ 1324.516681] RIP: 0010:amdgpu_ras_set_error_query_ready+0x15/0x20 [amdgpu] [ 
1324.523778] Code: 4c 89 f7 e8 cd a2 a0 d8 e9 99 fe ff ff 45 31 ff e9 91 fe ff 
ff 0f 1f 44 00 00 55 48 85 ff 48 89 e5 74 0e 48 8b 87 d8 2b 01 00 <40> 88 b0 38 
01 00 00 5d c3 66 90 0f 1f 44 00 00 55 31 c0 48 85 ff [ 1324.543452] RSP: 
0018:aa1040e4bd28 EFLAGS: 00010286 [ 1324.549025] RAX:  
RBX: 911198b2 RCX:  [ 1324.556217] RDX: 
000c0a01 RSI:  RDI: 911198b2 [ 1324.563514] 
RBP: aa1040e4bd28 R08: 1000 R09: 91119d0028c0 [ 
1324.570804] R10: 9a606b40 R11:  R12:  
[ 1324.578413] R13: aa1040e4bd70 R14: 911198b2 R15: 
 [ 1324.586464] FS:  7f4441cbf540() 
GS:91119ed8() knlGS: [ 1324.595434] CS:  0010 DS: 
 ES:  CR0: 80050033 [ 1324.601345] CR2: 0138 CR3: 
0003fcdf8004 CR4: 003606e0 [ 13
 24.608694] DR0:  DR1:  DR2:  [ 
1324.616303] DR3:  DR6: fffe0ff0 DR7: 0400 
[ 1324.623678] Call Trace:
[ 1324.626270]  amdgpu_device_gpu_recover+0x6e7/0xc50 [amdgpu] [ 1324.632018]  
? seq_printf+0x4e/0x70 [ 1324.636652]  amdgpu_debugfs_gpu_recover+0x50/0x80 
[amdgpu] [ 1324.643371]  seq_read+0xda/0x420 [ 1324.647601]  
full_proxy_read+0x5c/0x90 [ 1324.652426]  __vfs_read+0x1b/0x40 [ 1324.656734]  
vfs_read+0x8e/0x130 [ 1324.660981]  ksys_read+0xa7/0xe0 [ 1324.665201]  
__x64_sys_read+0x1a/0x20 [ 1324.669907]  do_syscall_64+0x57/0x1c0 [ 
1324.674517]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[ 1324.680654] RIP: 0033:0x7f44417cf081

Change-Id: I053089a8e44749db23ec882d14f876ded9c1332d
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 9e9e0f7747b7..8a78db648442 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -82,13 +82,13 @@ static bool amdgpu_ras_check_bad_page(struct amdgpu_device 
*adev,
 
 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)  
{
-   if (adev)
+   if (adev && amdgpu_ras_get_context(adev))
amdgpu_ras_get_context(adev)->error_query_ready = ready;  }
 
 bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)  {
-   if (adev)
+   if (adev && amdgpu_ras_get_context(adev))
return amdgpu_ras_get_context(adev)->error_query_ready;
 
return false;
--
2.26.0
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Re: [PATCH v2] drm/amdgpu: implement more ib pools

[Christian König]

Am 27.03.20 um 10:44 schrieb Pan, Xinhui:



2020年3月27日 16:24，Koenig, Christian  写道：

Am 27.03.20 um 04:08 schrieb xinhui pan:

We have three ib pools, they are normal, VM, direct pools.

Any jobs which schedule IBs without dependence on gpu scheduler should
use DIRECT pool.

Any jobs schedule direct VM update IBs should use VM pool.

Any other jobs use NORMAL pool.

Signed-off-by: xinhui pan 

Two more coding style suggestions below, with those fixed feel free to add a 
Reviewed-by: Christian König .

But in general your function parameter indentation is sometimes off. Not much 
of an issue, but what editor and settings are you using?

I use vim with
set tabstop=4
set shiftwidth=4


Oh, that is completely wrong. tabstop should be 8 not 4.

Please consider using https://github.com/vivien/vim-linux-coding-style, 
it should give you correct coding style while typing.


Another good practice is to use the checkpatch.pl script regularly. A 
couple of people has that as git commit hook and so run it automatically 
on each commit operation.


Christian.



But this now I use sed to replace some code.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 41 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  5 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  4 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c|  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  8 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  6 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  9 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c |  6 ++-
  drivers/gpu/drm/amd/amdgpu/cik_sdma.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  |  3 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   |  6 ++-
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  6 ++-
  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  |  2 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c  |  3 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c  |  3 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  |  3 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c  |  3 +-
  drivers/gpu/drm/amd/amdgpu/si_dma.c |  3 +-
  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c   |  6 ++-
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   |  6 ++-
  25 files changed, 103 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7dd74253e7b6..649bf5b8ea4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -390,6 +390,13 @@ struct amdgpu_sa_bo {
  int amdgpu_fence_slab_init(void);
  void amdgpu_fence_slab_fini(void);
  +enum amdgpu_ib_pool_type {
+   AMDGPU_IB_POOL_NORMAL = 0,
+   AMDGPU_IB_POOL_VM,
+   AMDGPU_IB_POOL_DIRECT,
+
+   AMDGPU_IB_POOL_MAX
+};
  /*
   * IRQS.
   */
@@ -441,7 +448,8 @@ struct amdgpu_fpriv {
  int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- unsigned size, struct amdgpu_ib *ib);
+ unsigned size, struct amdgpu_ib *ib,
+ enum amdgpu_ib_pool_type pool);
  void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
struct dma_fence *f);
  int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
@@ -848,7 +856,7 @@ struct amdgpu_device {
unsignednum_rings;
struct amdgpu_ring  *rings[AMDGPU_MAX_RINGS];
boolib_pool_ready;
-   struct amdgpu_sa_managerring_tmp_bo;
+   struct amdgpu_sa_managerring_tmp_bo[AMDGPU_IB_POOL_MAX];
/* interrupts */
struct amdgpu_irq   irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 59ec5e2be211..0f26668ae6f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -921,7 +921,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
ring = to_amdgpu_ring(entity->rq->sched);
r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
-  chunk_ib->ib_bytes : 0, ib);
+  chunk_ib->ib_bytes : 0, ib, 
AMDGPU_IB_POOL_NORMAL);
if (r) {
DRM_ERROR("Failed to get ib !\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index bece01f1cf09..0bfcd30df051 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -61,12 +61,13 @@
   * Returns 0 on success, error on failure.
 

Re: [PATCH v2] drm/amdgpu: implement more ib pools

[Pan, Xinhui]

> 2020年3月27日 16:24，Koenig, Christian  写道：
> 
> Am 27.03.20 um 04:08 schrieb xinhui pan:
>> We have three ib pools, they are normal, VM, direct pools.
>> 
>> Any jobs which schedule IBs without dependence on gpu scheduler should
>> use DIRECT pool.
>> 
>> Any jobs schedule direct VM update IBs should use VM pool.
>> 
>> Any other jobs use NORMAL pool.
>> 
>> Signed-off-by: xinhui pan 
> 
> Two more coding style suggestions below, with those fixed feel free to add a 
> Reviewed-by: Christian König .
> 
> But in general your function parameter indentation is sometimes off. Not much 
> of an issue, but what editor and settings are you using?

I use vim with
set tabstop=4
set shiftwidth=4

But this now I use sed to replace some code.

> 
>> ---
>>  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 41 +++--
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  5 ++-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  4 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c|  3 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  8 ++--
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  3 +-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  6 ++-
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  9 +++--
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c |  6 ++-
>>  drivers/gpu/drm/amd/amdgpu/cik_sdma.c   |  3 +-
>>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  |  3 +-
>>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  3 +-
>>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  3 +-
>>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   |  6 ++-
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  6 ++-
>>  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  |  2 +-
>>  drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c  |  3 +-
>>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c  |  3 +-
>>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  |  3 +-
>>  drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c  |  3 +-
>>  drivers/gpu/drm/amd/amdgpu/si_dma.c |  3 +-
>>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c   |  6 ++-
>>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   |  6 ++-
>>  25 files changed, 103 insertions(+), 49 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 7dd74253e7b6..649bf5b8ea4e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -390,6 +390,13 @@ struct amdgpu_sa_bo {
>>  int amdgpu_fence_slab_init(void);
>>  void amdgpu_fence_slab_fini(void);
>>  +enum amdgpu_ib_pool_type {
>> +AMDGPU_IB_POOL_NORMAL = 0,
>> +AMDGPU_IB_POOL_VM,
>> +AMDGPU_IB_POOL_DIRECT,
>> +
>> +AMDGPU_IB_POOL_MAX
>> +};
>>  /*
>>   * IRQS.
>>   */
>> @@ -441,7 +448,8 @@ struct amdgpu_fpriv {
>>  int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
>>int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>> -  unsigned size, struct amdgpu_ib *ib);
>> +  unsigned size, struct amdgpu_ib *ib,
>> +  enum amdgpu_ib_pool_type pool);
>>  void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
>>  struct dma_fence *f);
>>  int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>> @@ -848,7 +856,7 @@ struct amdgpu_device {
>>  unsignednum_rings;
>>  struct amdgpu_ring  *rings[AMDGPU_MAX_RINGS];
>>  boolib_pool_ready;
>> -struct amdgpu_sa_managerring_tmp_bo;
>> +struct amdgpu_sa_managerring_tmp_bo[AMDGPU_IB_POOL_MAX];
>>  /* interrupts */
>>  struct amdgpu_irq   irq;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> index 59ec5e2be211..0f26668ae6f7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> @@ -921,7 +921,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
>>  ring = to_amdgpu_ring(entity->rq->sched);
>>  r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
>> -   chunk_ib->ib_bytes : 0, ib);
>> +   chunk_ib->ib_bytes : 0, ib, 
>> AMDGPU_IB_POOL_NORMAL);
>>  if (r) {
>>  DRM_ERROR("Failed to get ib !\n");
>>  return r;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> index bece01f1cf09..0bfcd30df051 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> @@ -61,12 +61,13 @@
>>   * Returns 0 on success, error on failure.
>>   */
>>  int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>> -  unsigned size, struct amdgpu_ib *ib)
>> +  unsigned size, struct amdgpu_ib *ib,
>> +  enum 

Re: [PATCH v2] drm/amdgpu: implement more ib pools

[Christian König]

Am 27.03.20 um 04:08 schrieb xinhui pan:

We have three ib pools, they are normal, VM, direct pools.

Any jobs which schedule IBs without dependence on gpu scheduler should
use DIRECT pool.

Any jobs schedule direct VM update IBs should use VM pool.

Any other jobs use NORMAL pool.

Signed-off-by: xinhui pan 


Two more coding style suggestions below, with those fixed feel free to 
add a Reviewed-by: Christian König .


But in general your function parameter indentation is sometimes off. Not 
much of an issue, but what editor and settings are you using?



---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 41 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c |  5 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  4 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c|  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  8 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |  6 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  9 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c |  6 ++-
  drivers/gpu/drm/amd/amdgpu/cik_sdma.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  |  3 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   |  6 ++-
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  6 ++-
  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  |  2 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c  |  3 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c  |  3 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  |  3 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c  |  3 +-
  drivers/gpu/drm/amd/amdgpu/si_dma.c |  3 +-
  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c   |  6 ++-
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   |  6 ++-
  25 files changed, 103 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7dd74253e7b6..649bf5b8ea4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -390,6 +390,13 @@ struct amdgpu_sa_bo {
  int amdgpu_fence_slab_init(void);
  void amdgpu_fence_slab_fini(void);
  
+enum amdgpu_ib_pool_type {

+   AMDGPU_IB_POOL_NORMAL = 0,
+   AMDGPU_IB_POOL_VM,
+   AMDGPU_IB_POOL_DIRECT,
+
+   AMDGPU_IB_POOL_MAX
+};
  /*
   * IRQS.
   */
@@ -441,7 +448,8 @@ struct amdgpu_fpriv {
  int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
  
  int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

- unsigned size, struct amdgpu_ib *ib);
+ unsigned size, struct amdgpu_ib *ib,
+ enum amdgpu_ib_pool_type pool);
  void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
struct dma_fence *f);
  int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
@@ -848,7 +856,7 @@ struct amdgpu_device {
unsignednum_rings;
struct amdgpu_ring  *rings[AMDGPU_MAX_RINGS];
boolib_pool_ready;
-   struct amdgpu_sa_managerring_tmp_bo;
+   struct amdgpu_sa_managerring_tmp_bo[AMDGPU_IB_POOL_MAX];
  
  	/* interrupts */

struct amdgpu_irq   irq;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 59ec5e2be211..0f26668ae6f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -921,7 +921,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
  
  		ring = to_amdgpu_ring(entity->rq->sched);

r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
-  chunk_ib->ib_bytes : 0, ib);
+  chunk_ib->ib_bytes : 0, ib, 
AMDGPU_IB_POOL_NORMAL);
if (r) {
DRM_ERROR("Failed to get ib !\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index bece01f1cf09..0bfcd30df051 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -61,12 +61,13 @@
   * Returns 0 on success, error on failure.
   */
  int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- unsigned size, struct amdgpu_ib *ib)
+ unsigned size, struct amdgpu_ib *ib,
+ enum amdgpu_ib_pool_type pool_type)


I would put the ib last in the parameter list since it is the resulting 
object.



  {
int r;
  
  	if (size) {

-   r = amdgpu_sa_bo_new(>ring_tmp_bo,
+   r = amdgpu_sa_bo_new(>ring_tmp_bo[pool_type],
  >sa_bo, size, 256);
if 

[PATCH 1/6] drm/amdgpu: convert to use i2c_new_client_device()

[Wolfram Sang]

Move away from the deprecated API.

Signed-off-by: Wolfram Sang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index ba1bb95a3cf9..0e8018c9aa8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -856,7 +856,7 @@ void amdgpu_add_thermal_controller(struct amdgpu_device 
*adev)
const char *name = 
pp_lib_thermal_controller_names[controller->ucType];
info.addr = controller->ucI2cAddress >> 1;
strlcpy(info.type, name, sizeof(info.type));
-   i2c_new_device(>pm.i2c_bus->adapter, 
);
+   
i2c_new_client_device(>pm.i2c_bus->adapter, );
}
} else {
DRM_INFO("Unknown thermal controller type %d at 0x%02x 
%s fan control\n",
-- 
2.20.1

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[PATCH 6/6] drm/radeon: convert to use i2c_new_client_device()

[Wolfram Sang]

Move away from the deprecated API.

Signed-off-by: Wolfram Sang 
---
 drivers/gpu/drm/radeon/radeon_atombios.c | 4 ++--
 drivers/gpu/drm/radeon/radeon_combios.c  | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c 
b/drivers/gpu/drm/radeon/radeon_atombios.c
index 848ef68d9086..5d2591725189 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2111,7 +2111,7 @@ static int radeon_atombios_parse_power_table_1_3(struct 
radeon_device *rdev)

ucOverdriveThermalController];
info.addr = 
power_info->info.ucOverdriveControllerAddress >> 1;
strlcpy(info.type, name, sizeof(info.type));
-   i2c_new_device(>pm.i2c_bus->adapter, );
+   i2c_new_client_device(>pm.i2c_bus->adapter, 
);
}
}
num_modes = power_info->info.ucNumOfPowerModeEntries;
@@ -2351,7 +2351,7 @@ static void 
radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
const char *name = 
pp_lib_thermal_controller_names[controller->ucType];
info.addr = controller->ucI2cAddress >> 1;
strlcpy(info.type, name, sizeof(info.type));
-   i2c_new_device(>pm.i2c_bus->adapter, 
);
+   
i2c_new_client_device(>pm.i2c_bus->adapter, );
}
} else {
DRM_INFO("Unknown thermal controller type %d at 0x%02x 
%s fan control\n",
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c 
b/drivers/gpu/drm/radeon/radeon_combios.c
index c3e49c973812..d3c04df7e75d 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -2704,7 +2704,7 @@ void radeon_combios_get_power_modes(struct radeon_device 
*rdev)
const char *name = 
thermal_controller_names[thermal_controller];
info.addr = i2c_addr >> 1;
strlcpy(info.type, name, sizeof(info.type));
-   i2c_new_device(>pm.i2c_bus->adapter, 
);
+   
i2c_new_client_device(>pm.i2c_bus->adapter, );
}
}
} else {
@@ -2721,7 +2721,7 @@ void radeon_combios_get_power_modes(struct radeon_device 
*rdev)
const char *name = "f75375";
info.addr = 0x28;
strlcpy(info.type, name, sizeof(info.type));
-   i2c_new_device(>pm.i2c_bus->adapter, 
);
+   
i2c_new_client_device(>pm.i2c_bus->adapter, );
DRM_INFO("Possible %s thermal controller at 
0x%02x\n",
 name, info.addr);
}
-- 
2.20.1

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[PATCH 0/6] gpu: convert to use new I2C API

[Wolfram Sang]

We are deprecating calls which return NULL in favor of new variants which
return an ERR_PTR. Only build tested.


Wolfram Sang (6):
  drm/amdgpu: convert to use i2c_new_client_device()
  drm/gma500: convert to use i2c_new_client_device()
  drm/i2c/sil164: convert to use i2c_new_client_device()
  drm/i2c/tda998x: convert to use i2c_new_client_device()
  drm/nouveau/therm: convert to use i2c_new_client_device()
  drm/radeon: convert to use i2c_new_client_device()

 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 2 +-
 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c | 8 
 drivers/gpu/drm/i2c/sil164_drv.c   | 7 +--
 drivers/gpu/drm/i2c/tda998x_drv.c  | 6 +++---
 drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c | 4 ++--
 drivers/gpu/drm/radeon/radeon_atombios.c   | 4 ++--
 drivers/gpu/drm/radeon/radeon_combios.c| 4 ++--
 7 files changed, 19 insertions(+), 16 deletions(-)

-- 
2.20.1

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[PATCH 2/2] drm/amd/powerplay: move the ASIC specific nbio operation out of smu_v11_0.c

[Evan Quan]

This is ASIC specific and should be placed in _ppt.c of each ASIC.

Change-Id: If2b29ccf0dfc0dc90e1636a806b13ce2efed58c6
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 15 ++-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c   | 18 --
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c| 10 +-
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c   | 14 +-
 4 files changed, 44 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index c6d3bef15320..5db8c56066ee 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -35,6 +35,7 @@
 #include "arcturus_ppt.h"
 #include "smu_v11_0_pptable.h"
 #include "arcturus_ppsmc.h"
+#include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
 #include "amdgpu_xgmi.h"
 #include 
@@ -2210,6 +2211,18 @@ static void arcturus_i2c_eeprom_control_fini(struct 
i2c_adapter *control)
i2c_del_adapter(control);
 }
 
+static bool arcturus_is_baco_supported(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+   uint32_t val;
+
+   if (!smu_v11_0_baco_is_support(smu))
+   return false;
+
+   val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+   return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+}
+
 static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
 {
PPTable_t *pptable = smu->smu_table.driver_pptable;
@@ -2321,7 +2334,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.register_irq_handler = smu_v11_0_register_irq_handler,
.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
.get_max_sustainable_clocks_by_dc = 
smu_v11_0_get_max_sustainable_clocks_by_dc,
-   .baco_is_support= smu_v11_0_baco_is_support,
+   .baco_is_support= arcturus_is_baco_supported,
.baco_get_state = smu_v11_0_baco_get_state,
.baco_set_state = smu_v11_0_baco_set_state,
.baco_enter = smu_v11_0_baco_enter,
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 1112e4c5f4d7..c94270f7c198 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -28,13 +28,15 @@
 #include "smu_internal.h"
 #include "atomfirmware.h"
 #include "amdgpu_atomfirmware.h"
+#include "soc15_common.h"
 #include "smu_v11_0.h"
 #include "smu11_driver_if_navi10.h"
 #include "atom.h"
 #include "navi10_ppt.h"
 #include "smu_v11_0_pptable.h"
 #include "smu_v11_0_ppsmc.h"
-#include "nbio/nbio_7_4_sh_mask.h"
+#include "nbio/nbio_2_3_offset.h"
+#include "nbio/nbio_2_3_sh_mask.h"
 
 #include "asic_reg/mp/mp_11_0_sh_mask.h"
 
@@ -1942,6 +1944,18 @@ static int navi10_setup_od_limits(struct smu_context 
*smu) {
return 0;
 }
 
+static bool navi10_is_baco_supported(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+   uint32_t val;
+
+   if (!smu_v11_0_baco_is_support(smu))
+   return false;
+
+   val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+   return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
+}
+
 static int navi10_set_default_od_settings(struct smu_context *smu, bool 
initialize) {
OverDriveTable_t *od_table, *boot_od_table;
int ret = 0;
@@ -2318,7 +2332,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.register_irq_handler = smu_v11_0_register_irq_handler,
.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
.get_max_sustainable_clocks_by_dc = 
smu_v11_0_get_max_sustainable_clocks_by_dc,
-   .baco_is_support= smu_v11_0_baco_is_support,
+   .baco_is_support= navi10_is_baco_supported,
.baco_get_state = smu_v11_0_baco_get_state,
.baco_set_state = smu_v11_0_baco_set_state,
.baco_enter = smu_v11_0_baco_enter,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 31b93cff19d5..655ba4fb05dc 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -42,8 +42,6 @@
 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
 #include "asic_reg/mp/mp_11_0_offset.h"
 #include "asic_reg/mp/mp_11_0_sh_mask.h"
-#include "asic_reg/nbio/nbio_7_4_offset.h"
-#include "asic_reg/nbio/nbio_7_4_sh_mask.h"
 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
 
@@ -1662,9 +1660,7 @@ static int smu_v11_0_baco_set_armd3_sequence(struct 
smu_context *smu, enum smu_v
 
 bool smu_v11_0_baco_is_support(struct smu_context *smu)
 {
-   struct amdgpu_device *adev = smu->adev;
struct smu_baco_context *smu_baco = >smu_baco;
-   uint32_t val;
bool baco_support;
 
mutex_lock(_baco->mutex);
@@ -1679,11 +1675,7 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu)
   

[PATCH 1/2] drm/amd/powerplay: drop redundant BIF doorbell interrupt operations

[Evan Quan]

This is already done in soc15.c. And this is really ASIC specific
and should not be placed here.

Change-Id: I7c9ee3cce07463849a29c7bcbcb493f817626274
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 14 --
 1 file changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 160ed40bbc86..31b93cff19d5 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1700,11 +1700,9 @@ enum smu_baco_state smu_v11_0_baco_get_state(struct 
smu_context *smu)
 
 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state 
state)
 {
-
struct smu_baco_context *smu_baco = >smu_baco;
struct amdgpu_device *adev = smu->adev;
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
-   uint32_t bif_doorbell_intr_cntl;
uint32_t data;
int ret = 0;
 
@@ -1713,14 +1711,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, 
enum smu_baco_state state)
 
mutex_lock(_baco->mutex);
 
-   bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
-
if (state == SMU_BACO_STATE_ENTER) {
-   bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
-   BIF_DOORBELL_INT_CNTL,
-   DOORBELL_INTERRUPT_DISABLE, 1);
-   WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, 
bif_doorbell_intr_cntl);
-
if (!ras || !ras->supported) {
data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
data |= 0x8000;
@@ -1741,11 +1732,6 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, 
enum smu_baco_state state)
goto out;
}
 
-   bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
-   BIF_DOORBELL_INT_CNTL,
-   DOORBELL_INTERRUPT_DISABLE, 0);
-   WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, 
bif_doorbell_intr_cntl);
-
/* clear vbios scratch 6 and 7 for coming asic reinit */
WREG32(adev->bios_scratch_reg_offset + 6, 0);
WREG32(adev->bios_scratch_reg_offset + 7, 0);
-- 
2.26.0

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[PATCH] drm/amdgpu: fix non-pointer dereference for non-RAS supported

[Evan Quan]

Backtrace on gpu recover test on Navi10.

[ 1324.516681] RIP: 0010:amdgpu_ras_set_error_query_ready+0x15/0x20 [amdgpu]
[ 1324.523778] Code: 4c 89 f7 e8 cd a2 a0 d8 e9 99 fe ff ff 45 31 ff e9 91 fe 
ff ff 0f 1f 44 00 00 55 48 85 ff 48 89 e5 74 0e 48 8b 87 d8 2b 01 00 <40> 88 b0 
38 01 00 00 5d c3 66 90 0f 1f 44 00 00 55 31 c0 48 85 ff
[ 1324.543452] RSP: 0018:aa1040e4bd28 EFLAGS: 00010286
[ 1324.549025] RAX:  RBX: 911198b2 RCX: 
[ 1324.556217] RDX: 000c0a01 RSI:  RDI: 911198b2
[ 1324.563514] RBP: aa1040e4bd28 R08: 1000 R09: 91119d0028c0
[ 1324.570804] R10: 9a606b40 R11:  R12: 
[ 1324.578413] R13: aa1040e4bd70 R14: 911198b2 R15: 
[ 1324.586464] FS:  7f4441cbf540() GS:91119ed8() 
knlGS:
[ 1324.595434] CS:  0010 DS:  ES:  CR0: 80050033
[ 1324.601345] CR2: 0138 CR3: 0003fcdf8004 CR4: 003606e0
[ 1324.608694] DR0:  DR1:  DR2: 
[ 1324.616303] DR3:  DR6: fffe0ff0 DR7: 0400
[ 1324.623678] Call Trace:
[ 1324.626270]  amdgpu_device_gpu_recover+0x6e7/0xc50 [amdgpu]
[ 1324.632018]  ? seq_printf+0x4e/0x70
[ 1324.636652]  amdgpu_debugfs_gpu_recover+0x50/0x80 [amdgpu]
[ 1324.643371]  seq_read+0xda/0x420
[ 1324.647601]  full_proxy_read+0x5c/0x90
[ 1324.652426]  __vfs_read+0x1b/0x40
[ 1324.656734]  vfs_read+0x8e/0x130
[ 1324.660981]  ksys_read+0xa7/0xe0
[ 1324.665201]  __x64_sys_read+0x1a/0x20
[ 1324.669907]  do_syscall_64+0x57/0x1c0
[ 1324.674517]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[ 1324.680654] RIP: 0033:0x7f44417cf081

Change-Id: I053089a8e44749db23ec882d14f876ded9c1332d
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 9e9e0f7747b7..8a78db648442 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -82,13 +82,13 @@ static bool amdgpu_ras_check_bad_page(struct amdgpu_device 
*adev,
 
 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 {
-   if (adev)
+   if (adev && amdgpu_ras_get_context(adev))
amdgpu_ras_get_context(adev)->error_query_ready = ready;
 }
 
 bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 {
-   if (adev)
+   if (adev && amdgpu_ras_get_context(adev))
return amdgpu_ras_get_context(adev)->error_query_ready;
 
return false;
-- 
2.26.0

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