[PATCH 4/4] drm/amdgpu: add mode1 reset module parameter
For sienna cichlid, defaut path is baco reset, only
when parameter mode1_reset is set, mode1 reset will
be chosen.
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 8
drivers/gpu/drm/amd/amdgpu/nv.c| 9 ++---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
4 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 0682a270c17b..01b14237dc94 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -196,6 +196,7 @@ static const bool debug_evictions; /* = false */
#endif
extern int amdgpu_tmz;
+extern int amdgpu_mode1_reset;
#ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 94c83a9d4987..d30d31aead7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -154,6 +154,7 @@ int amdgpu_mes = 0;
int amdgpu_noretry = 1;
int amdgpu_force_asic_type = -1;
int amdgpu_tmz = 0;
+int amdgpu_mode1_reset = 0;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -793,6 +794,13 @@ module_param_named(abmlevel, amdgpu_dm_abm_level, uint,
0444);
MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 =
on)");
module_param_named(tmz, amdgpu_tmz, int, 0444);
+/**
+ * DOC: mode1_reset (int)
+ * Enable SMU mode1 reset (0 = disabled (default), 1 = enabled)
+ */
+MODULE_PARM_DESC(mode1_reset, "Enable SMU mode1 reset (0 = disabled (default),
1 = enabled)");
+module_param_named(mode1_reset, amdgpu_mode1_reset, int, 0444);
+
static const struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index abccb155b28e..11a662a2f8d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -316,10 +316,13 @@ nv_asic_reset_method(struct amdgpu_device *adev)
{
struct smu_context *smu = >smu;
- if (smu_baco_is_support(smu))
- return AMD_RESET_METHOD_BACO;
- else if (smu_mode1_reset_is_support(smu))
+ /**
+* If mode1 reset is support, choose mode1 reset
+*/
+ if (smu_mode1_reset_is_support(smu))
return AMD_RESET_METHOD_MODE1;
+ else if (smu_baco_is_support(smu))
+ return AMD_RESET_METHOD_BACO;
else
return AMD_RESET_METHOD_PSP_MODE1;
}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index cae5aa792ac4..ee74f0cf6231 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2741,7 +2741,7 @@ bool smu_mode1_reset_is_support(struct smu_context *smu)
{
bool ret = false;
- if (!smu->pm_enabled)
+ if (!smu->pm_enabled || !amdgpu_mode1_reset)
return false;
mutex_lock(>mutex);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/4] drm/amd/powerplay: add SMU mode1 reset
>From PM FW 58.26.0 for sienna cichlid, SMU mode1 reset
is support, driver sends PPSMC_MSG_Mode1Reset message
to PM FW could trigger this reset.
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 37 +++
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 4 ++
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 29 ++-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 11 ++
6 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index fe4948aa662f..cae5aa792ac4 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2737,6 +2737,43 @@ int smu_baco_exit(struct smu_context *smu)
return ret;
}
+bool smu_mode1_reset_is_support(struct smu_context *smu)
+{
+ bool ret = false;
+
+ if (!smu->pm_enabled)
+ return false;
+
+ mutex_lock(>mutex);
+
+ if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
+ ret = smu->ppt_funcs->mode1_reset_is_support(smu);
+
+ mutex_unlock(>mutex);
+
+ return ret;
+}
+
+int smu_mode1_reset(struct smu_context *smu)
+{
+ int ret = 0;
+
+ if (!smu->pm_enabled)
+ return -EOPNOTSUPP;
+
+ mutex_lock(>mutex);
+
+ if (smu->ppt_funcs->mode1_reset)
+ ret = smu->ppt_funcs->mode1_reset(smu);
+
+ mutex_unlock(>mutex);
+
+ if (ret)
+ dev_err(smu->adev->dev, "Mode1 reset failed!\n");
+
+ return ret;
+}
+
int smu_mode2_reset(struct smu_context *smu)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 7b349e038972..ba59620950d7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -561,6 +561,8 @@ struct pptable_funcs {
int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state
state);
int (*baco_enter)(struct smu_context *smu);
int (*baco_exit)(struct smu_context *smu);
+ bool (*mode1_reset_is_support)(struct smu_context *smu);
+ int (*mode1_reset)(struct smu_context *smu);
int (*mode2_reset)(struct smu_context *smu);
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type
clk_type, uint32_t *min, uint32_t *max);
int (*set_soft_freq_limited_range)(struct smu_context *smu, enum
smu_clk_type clk_type, uint32_t min, uint32_t max);
@@ -672,6 +674,8 @@ int smu_baco_get_state(struct smu_context *smu, enum
smu_baco_state *state);
int smu_baco_enter(struct smu_context *smu);
int smu_baco_exit(struct smu_context *smu);
+bool smu_mode1_reset_is_support(struct smu_context *smu);
+int smu_mode1_reset(struct smu_context *smu);
int smu_mode2_reset(struct smu_context *smu);
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
index dff2295705be..7b585e205a5a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -173,6 +173,7 @@
__SMU_DUMMY_MAP(GmiPwrDnControl), \
__SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE), \
__SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \
+ __SMU_DUMMY_MAP(Mode1Reset), \
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index d07bf4fe6e4a..38599112ae59 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -252,6 +252,8 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum
smu_baco_state state)
int smu_v11_0_baco_enter(struct smu_context *smu);
int smu_v11_0_baco_exit(struct smu_context *smu);
+int smu_v11_0_mode1_reset(struct smu_context *smu);
+
int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type
clk_type,
uint32_t *min, uint32_t *max);
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dc5ca9121db5..612788bbc6c3 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -39,8 +39,8 @@
#include "nbio/nbio_2_3_sh_mask.h"
#include "thm/thm_11_0_2_offset.h"
#include "thm/thm_11_0_2_sh_mask.h"
-
-#include "asic_reg/mp/mp_11_0_sh_mask.h"
+#include "mp/mp_11_0_offset.h"
+#include "mp/mp_11_0_sh_mask.h"
/*
* DO NOT use these for err/warn/info/debug messages.
@@ -116,6 +116,7 @@ static struct smu_11_0_cmn2aisc_mapping
[PATCH 3/4] drm/amdgpu: enable mode1 reset
For sienna cichlid, add mode1 reset path for sGPU.
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 24 --
drivers/gpu/drm/amd/amdgpu/nv.c | 32 +--
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 2 +-
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 2 +-
4 files changed, 39 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 565dc59a9e89..85d2aee546b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2119,6 +2119,7 @@ static bool amdgpu_device_check_vram_lost(struct
amdgpu_device *adev)
*/
switch (amdgpu_asic_reset_method(adev)) {
case AMD_RESET_METHOD_BACO:
+ case AMD_RESET_METHOD_MODE1:
case AMD_RESET_METHOD_PSP_MODE1:
return true;
default:
@@ -4220,7 +4221,8 @@ static int amdgpu_device_suspend_display_audio(struct
amdgpu_device *adev)
*/
reset_method = amdgpu_asic_reset_method(adev);
if ((reset_method != AMD_RESET_METHOD_BACO) &&
-(reset_method != AMD_RESET_METHOD_PSP_MODE1))
+ (reset_method != AMD_RESET_METHOD_PSP_MODE1) &&
+ (reset_method != AMD_RESET_METHOD_MODE1))
return -EINVAL;
p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
@@ -4275,16 +4277,18 @@ int amdgpu_device_gpu_recover(struct amdgpu_device
*adev,
struct amdgpu_device *tmp_adev = NULL;
int i, r = 0;
bool in_ras_intr = amdgpu_ras_intr_triggered();
- bool use_baco =
- (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ?
- true : false;
+ bool is_full_reset = false;
bool audio_suspended = false;
+ if ((amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ||
+ (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_MODE1))
+ is_full_reset = true;
+
/*
* Flush RAM to disk so that after reboot
* the user can read log and see why the system rebooted.
*/
- if (in_ras_intr && !use_baco && amdgpu_ras_get_context(adev)->reboot) {
+ if (in_ras_intr && !is_full_reset &&
amdgpu_ras_get_context(adev)->reboot) {
DRM_WARN("Emergency reboot.");
@@ -4293,7 +4297,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
}
dev_info(adev->dev, "GPU %s begin!\n",
- (in_ras_intr && !use_baco) ? "jobs stop":"reset");
+ (in_ras_intr && !is_full_reset) ? "jobs stop":"reset");
/*
* Here we trylock to avoid chain of resets executing from
@@ -4365,7 +4369,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
amdgpu_fbdev_set_suspend(tmp_adev, 1);
/* disable ras on ALL IPs */
- if (!(in_ras_intr && !use_baco) &&
+ if (!(in_ras_intr && !is_full_reset) &&
amdgpu_device_ip_need_full_reset(tmp_adev))
amdgpu_ras_suspend(tmp_adev);
@@ -4377,12 +4381,12 @@ int amdgpu_device_gpu_recover(struct amdgpu_device
*adev,
drm_sched_stop(>sched, job ? >base : NULL);
- if (in_ras_intr && !use_baco)
+ if (in_ras_intr && !is_full_reset)
amdgpu_job_stop_all_jobs_on_sched(>sched);
}
}
- if (in_ras_intr && !use_baco)
+ if (in_ras_intr && !is_full_reset)
goto skip_sched_resume;
/*
@@ -4459,7 +4463,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
skip_sched_resume:
list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
/*unlock kfd: SRIOV would do it separately */
- if (!(in_ras_intr && !use_baco) && !amdgpu_sriov_vf(tmp_adev))
+ if (!(in_ras_intr && !is_full_reset) &&
!amdgpu_sriov_vf(tmp_adev))
amdgpu_amdkfd_post_reset(tmp_adev);
if (audio_suspended)
amdgpu_device_resume_display_audio(tmp_adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 1d27dd3676ad..abccb155b28e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -258,23 +258,32 @@ static int nv_read_register(struct amdgpu_device *adev,
u32 se_num,
return -EINVAL;
}
-static int nv_asic_mode1_reset(struct amdgpu_device *adev)
+static int nv_asic_mode1_reset(struct amdgpu_device *adev,
+ enum amd_reset_method reset_method)
{
u32 i;
int ret = 0;
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
- dev_info(adev->dev, "GPU psp mode1 reset\n");
+ dev_info(adev->dev, "GPU %s reset\n",
+
[PATCH 2/4] drm/amdgpu: add psp mode1 reset mode
AMD_RESET_METHOD_MODE1 will be used by SMU
mode1 reset for sienna cichlid, so add
AMD_RESET_METHOD_PSP_MODE1 for psp mode1 reset.
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/nv.c| 6 +++---
drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++---
4 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4de93cef79b9..0682a270c17b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -580,7 +580,8 @@ enum amd_reset_method {
AMD_RESET_METHOD_MODE0,
AMD_RESET_METHOD_MODE1,
AMD_RESET_METHOD_MODE2,
- AMD_RESET_METHOD_BACO
+ AMD_RESET_METHOD_BACO,
+ AMD_RESET_METHOD_PSP_MODE1,
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fec6cf3f0c8a..565dc59a9e89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2119,7 +2119,7 @@ static bool amdgpu_device_check_vram_lost(struct
amdgpu_device *adev)
*/
switch (amdgpu_asic_reset_method(adev)) {
case AMD_RESET_METHOD_BACO:
- case AMD_RESET_METHOD_MODE1:
+ case AMD_RESET_METHOD_PSP_MODE1:
return true;
default:
return false;
@@ -4174,7 +4174,7 @@ static bool amdgpu_device_lock_adev(struct amdgpu_device
*adev, bool trylock)
atomic_inc(>gpu_reset_counter);
adev->in_gpu_reset = true;
switch (amdgpu_asic_reset_method(adev)) {
- case AMD_RESET_METHOD_MODE1:
+ case AMD_RESET_METHOD_PSP_MODE1:
adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
break;
case AMD_RESET_METHOD_MODE2:
@@ -4220,7 +4220,7 @@ static int amdgpu_device_suspend_display_audio(struct
amdgpu_device *adev)
*/
reset_method = amdgpu_asic_reset_method(adev);
if ((reset_method != AMD_RESET_METHOD_BACO) &&
-(reset_method != AMD_RESET_METHOD_MODE1))
+(reset_method != AMD_RESET_METHOD_PSP_MODE1))
return -EINVAL;
p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 356849136d1d..1d27dd3676ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -265,7 +265,7 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
- dev_info(adev->dev, "GPU mode1 reset\n");
+ dev_info(adev->dev, "GPU psp mode1 reset\n");
/* disable BM */
pci_clear_master(adev->pdev);
@@ -274,7 +274,7 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
ret = psp_gpu_reset(adev);
if (ret)
- dev_err(adev->dev, "GPU mode1 reset failed\n");
+ dev_err(adev->dev, "GPU psp mode1 reset failed\n");
pci_restore_state(adev->pdev);
@@ -310,7 +310,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu))
return AMD_RESET_METHOD_BACO;
else
- return AMD_RESET_METHOD_MODE1;
+ return AMD_RESET_METHOD_PSP_MODE1;
}
static int nv_asic_reset(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 8c739b285915..86ce2f165038 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -479,7 +479,7 @@ static int soc15_asic_mode1_reset(struct amdgpu_device
*adev)
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
- dev_info(adev->dev, "GPU mode1 reset\n");
+ dev_info(adev->dev, "GPU psp mode1 reset\n");
/* disable BM */
pci_clear_master(adev->pdev);
@@ -488,7 +488,7 @@ static int soc15_asic_mode1_reset(struct amdgpu_device
*adev)
ret = psp_gpu_reset(adev);
if (ret)
- dev_err(adev->dev, "GPU mode1 reset failed\n");
+ dev_err(adev->dev, "GPU psp mode1 reset failed\n");
pci_restore_state(adev->pdev);
@@ -559,7 +559,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
if (baco_reset)
return AMD_RESET_METHOD_BACO;
else
- return AMD_RESET_METHOD_MODE1;
+ return AMD_RESET_METHOD_PSP_MODE1;
}
static int soc15_asic_reset(struct amdgpu_device *adev)
--
2.17.1
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amdgpu/gfx10: fix race condition for kiq
During preemption test for gfx10, it uses kiq to trigger
gfx preemption, which would result in race condition
with flushing TLB for kiq.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a6170a346b39..ddf6d8128753 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7836,12 +7836,17 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring
*ring)
struct amdgpu_device *adev = ring->adev;
struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *kiq_ring = >ring;
+ unsigned long flags;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
- if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
+ spin_lock_irqsave(>ring_lock, flags);
+
+ if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
+ spin_unlock_irqrestore(>ring_lock, flags);
return -ENOMEM;
+ }
/* assert preemption condition */
amdgpu_ring_set_preempt_cond_exec(ring, false);
@@ -7852,6 +7857,8 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring
*ring)
++ring->trail_seq);
amdgpu_ring_commit(kiq_ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
+
/* poll the trailing fence */
for (i = 0; i < adev->usec_timeout; i++) {
if (ring->trail_seq ==
--
2.26.2
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[PATCH 2/2] drm/amdgpu: fix preemption unit test
Remove signaled jobs from job list and ensure the
job was indeed preempted.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index aeada7c9fbea..bd5061fbe031 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1343,27 +1343,37 @@ static void amdgpu_ib_preempt_job_recovery(struct
drm_gpu_scheduler *sched)
static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
{
struct amdgpu_job *job;
- struct drm_sched_job *s_job;
+ struct drm_sched_job *s_job, *tmp;
uint32_t preempt_seq;
struct dma_fence *fence, **ptr;
struct amdgpu_fence_driver *drv = >fence_drv;
struct drm_gpu_scheduler *sched = >sched;
+ bool preempted = true;
if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
return;
preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
- if (preempt_seq <= atomic_read(>last_seq))
- return;
+ if (preempt_seq <= atomic_read(>last_seq)) {
+ preempted = false;
+ goto no_preempt;
+ }
preempt_seq &= drv->num_fences_mask;
ptr = >fences[preempt_seq];
fence = rcu_dereference_protected(*ptr, 1);
+no_preempt:
spin_lock(>job_list_lock);
- list_for_each_entry(s_job, >ring_mirror_list, node) {
+ list_for_each_entry_safe(s_job, tmp, >ring_mirror_list, node) {
+ if (dma_fence_is_signaled(_job->s_fence->finished)) {
+ /* remove job from ring_mirror_list */
+ list_del_init(_job->node);
+ sched->ops->free_job(s_job);
+ continue;
+ }
job = to_amdgpu_job(s_job);
- if (job->fence == fence)
+ if (preempted && job->fence == fence)
/* mark the job as preempted */
job->preemption_status |= AMDGPU_IB_PREEMPTED;
}
--
2.26.2
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RE: [PATCH 11/14] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range
[AMD Official Use Only - Internal Distribution Only]
Thanks. Other ASICs from SMU V11 should need this also.
A new patch was created to apply this for all SMU V11 ASICs.
Please see the updated patch series.
BR,
Evan
-Original Message-
From: Alex Deucher
Sent: Friday, July 10, 2020 4:45 AM
To: Quan, Evan
Cc: amd-gfx list ; Deucher, Alexander
Subject: Re: [PATCH 11/14] drm/amd/powerplay: drop Sienna Cichlid specific
set_soft_freq_limited_range
On Fri, Jul 3, 2020 at 4:34 AM Evan Quan wrote:
>
> Use the common smu_v11_0_set_soft_freq_limited_range.
>
> Change-Id: I9f8772880b324ce9e741291751bb1b8ff4c36ea3
> Signed-off-by: Evan Quan
> ---
> .../drm/amd/powerplay/sienna_cichlid_ppt.c| 20 ++-
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 1 -
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 20 +++
> 3 files changed, 18 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> index 27f77bde184f..141944df97b0 100644
> --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> @@ -1046,22 +1046,6 @@ static int sienna_cichlid_print_clk_levels(struct
> smu_context *smu,
> return size;
> }
>
> -int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
> - enum smu_clk_type clk_type,
> - uint32_t min, uint32_t max)
> -{
> - struct amdgpu_device *adev = smu->adev;
> - int ret;
> -
> - if (clk_type == SMU_GFXCLK)
> - amdgpu_gfx_off_ctrl(adev, false);
> - ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max);
> - if (clk_type == SMU_GFXCLK)
> - amdgpu_gfx_off_ctrl(adev, true);
> -
> - return ret;
> -}
> -
> static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
>enum smu_clk_type clk_type,
> uint32_t mask) { @@ -1097,7 +1081,7 @@ static int
> sienna_cichlid_force_clk_levels(struct smu_context *smu,
> if (ret)
> goto forec_level_out;
>
> - ret = sienna_cichlid_set_soft_freq_limited_range(smu,
> clk_type, min_freq, max_freq);
> + ret = smu_v11_0_set_soft_freq_limited_range(smu,
> + clk_type, min_freq, max_freq);
> if (ret)
> goto forec_level_out;
> break;
> @@ -2566,7 +2550,7 @@ static const struct pptable_funcs
> sienna_cichlid_ppt_funcs = {
> .baco_enter = smu_v11_0_baco_enter,
> .baco_exit = smu_v11_0_baco_exit,
> .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
> - .set_soft_freq_limited_range =
> sienna_cichlid_set_soft_freq_limited_range,
> + .set_soft_freq_limited_range =
> + smu_v11_0_set_soft_freq_limited_range,
> .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
> .set_thermal_range = sienna_cichlid_set_thermal_range, };
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> index 8fbfa0562007..1b357e349d1e 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> @@ -93,7 +93,6 @@
> #define smu_asic_set_performance_level(smu, level)
> smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)
> #define smu_dump_pptable(smu)
> smu_ppt_funcs(dump_pptable, 0, smu)
> #define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq)
> smu_ppt_funcs(get_dpm_clk_limited, -EINVAL, smu, clk_type, dpm_level, freq)
> -#define smu_set_soft_freq_limited_range(smu, clk_type, min, max)
> smu_ppt_funcs(set_soft_freq_limited_range, -EINVAL, smu, clk_type, min, max)
> #define smu_override_pcie_parameters(smu)
> smu_ppt_funcs(override_pcie_parameters, 0, smu)
> #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap)
> smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)
> #define smu_set_thermal_range(smu, range)
> smu_ppt_funcs(set_thermal_range, 0, smu, range)
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index c2564df304f7..1ed5ac946c05 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1745,9 +1745,12 @@ int smu_v11_0_get_dpm_ultimate_freq(struct smu_context
> *smu, enum smu_clk_type c
> return ret;
> }
>
> -int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum
> smu_clk_type clk_type,
> - uint32_t min, uint32_t max)
> +int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
> +
RE: [PATCH 02/14] drm/amd/powerplay: update Arcturus default dpm table setting
[AMD Official Use Only - Internal Distribution Only]
Just sent out the updated patch series with this one splitted into two as
commented.
BR,
Evan
-Original Message-
From: Alex Deucher
Sent: Friday, July 10, 2020 4:39 AM
To: Quan, Evan
Cc: amd-gfx list ; Deucher, Alexander
Subject: Re: [PATCH 02/14] drm/amd/powerplay: update Arcturus default dpm table
setting
On Fri, Jul 3, 2020 at 4:33 AM Evan Quan wrote:
>
> Preparing for coming code sharing around performance level setting.
>
> Change-Id: Ie32b6af39f22d05c08096959bab0e02e53856170
> Signed-off-by: Evan Quan
You might want to split this into two patches, one to split out the
smu_v11_0_set_single_dpm_table into the common smu11 code, and then the rest as
separate patch. That will make it the arcturus patch cleaner and more like the
patches for other asics.
Alex.
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 297 +++---
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 +
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 38 +++
> 3 files changed, 161 insertions(+), 178 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index 5b793e354704..a3747ab4af32 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -291,7 +291,6 @@ static int arcturus_get_pwr_src_index(struct smu_context
> *smc, uint32_t index)
> return mapping.map_to;
> }
>
> -
> static int arcturus_get_workload_type(struct smu_context *smu, enum
> PP_SMC_POWER_PROFILE profile) {
> struct smu_11_0_cmn2aisc_mapping mapping; @@ -338,23 +337,11
> @@ static int arcturus_allocate_dpm_context(struct smu_context *smu)
> {
> struct smu_dpm_context *smu_dpm = >smu_dpm;
>
> - if (smu_dpm->dpm_context)
> - return -EINVAL;
> -
> - smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
> + smu_dpm->dpm_context = kzalloc(sizeof(struct
> + smu_11_0_dpm_context),
>GFP_KERNEL);
> if (!smu_dpm->dpm_context)
> return -ENOMEM;
> -
> - if (smu_dpm->golden_dpm_context)
> - return -EINVAL;
> -
> - smu_dpm->golden_dpm_context = kzalloc(sizeof(struct
> arcturus_dpm_table),
> - GFP_KERNEL);
> - if (!smu_dpm->golden_dpm_context)
> - return -ENOMEM;
> -
> - smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
> + smu_dpm->dpm_context_size = sizeof(struct
> + smu_11_0_dpm_context);
>
> smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct
> smu_power_state),
>GFP_KERNEL); @@ -382,119
> +369,84 @@ arcturus_get_allowed_feature_mask(struct smu_context *smu,
> return 0;
> }
>
> -static int
> -arcturus_set_single_dpm_table(struct smu_context *smu,
> - struct arcturus_single_dpm_table
> *single_dpm_table,
> - PPCLK_e clk_id)
> -{
> - int ret = 0;
> - uint32_t i, num_of_levels = 0, clk;
> -
> - ret = smu_send_smc_msg_with_param(smu,
> - SMU_MSG_GetDpmFreqByIndex,
> - (clk_id << 16 | 0xFF),
> - _of_levels);
> - if (ret) {
> - dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n",
> __func__);
> - return ret;
> - }
> -
> - single_dpm_table->count = num_of_levels;
> - for (i = 0; i < num_of_levels; i++) {
> - ret = smu_send_smc_msg_with_param(smu,
> - SMU_MSG_GetDpmFreqByIndex,
> - (clk_id << 16 | i),
> - );
> - if (ret) {
> - dev_err(smu->adev->dev, "[%s] failed to get dpm freq
> by index!\n", __func__);
> - return ret;
> - }
> - single_dpm_table->dpm_levels[i].value = clk;
> - single_dpm_table->dpm_levels[i].enabled = true;
> - }
> - return 0;
> -}
> -
> -static void arcturus_init_single_dpm_state(struct arcturus_dpm_state
> *dpm_state) -{
> - dpm_state->soft_min_level = 0x0;
> - dpm_state->soft_max_level = 0x;
> -dpm_state->hard_min_level = 0x0;
> -dpm_state->hard_max_level = 0x;
> -}
> -
> static int arcturus_set_default_dpm_table(struct smu_context *smu) {
> - int ret;
> -
> - struct smu_dpm_context *smu_dpm = >smu_dpm;
> - struct arcturus_dpm_table *dpm_table = NULL;
> - struct arcturus_single_dpm_table *single_dpm_table;
> -
> - dpm_table = smu_dpm->dpm_context;
> + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> + PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
> + struct smu_11_0_dpm_table *dpm_table = NULL;
> +
[PATCH 16/16] drm/amd/powerplay: drop unused APIs and parameters
Leftover of previous performance level setting cleanups.
Change-Id: Idddc4adce365b34eacbc13f75cc0629859c6d412
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 ++--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++--
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 12 +---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/smu_internal.h | 5 -
5 files changed, 10 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index d2401379bd33..20f39aa04fb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1105,7 +1105,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(>smu, SMU_SCLK, mask, true);
+ ret = smu_force_clk_levels(>smu, SMU_SCLK, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
@@ -1173,7 +1173,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(>smu, SMU_MCLK, mask, true);
+ ret = smu_force_clk_levels(>smu, SMU_MCLK, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -1241,7 +1241,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device
*dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(>smu, SMU_SOCCLK, mask, true);
+ ret = smu_force_clk_levels(>smu, SMU_SOCCLK, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
else
@@ -1311,7 +1311,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(>smu, SMU_FCLK, mask, true);
+ ret = smu_force_clk_levels(>smu, SMU_FCLK, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
else
@@ -1381,7 +1381,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device
*dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(>smu, SMU_DCEFCLK, mask, true);
+ ret = smu_force_clk_levels(>smu, SMU_DCEFCLK, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
else
@@ -1451,7 +1451,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(>smu, SMU_PCIE, mask, true);
+ ret = smu_force_clk_levels(>smu, SMU_PCIE, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
else
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 4080b3c792ac..38b3b47d12b7 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1764,8 +1764,7 @@ int smu_set_display_count(struct smu_context *smu,
uint32_t count)
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
-uint32_t mask,
-bool lock_needed)
+uint32_t mask)
{
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int ret = 0;
@@ -1778,14 +1777,12 @@ int smu_force_clk_levels(struct smu_context *smu,
return -EINVAL;
}
- if (lock_needed)
- mutex_lock(>mutex);
+ mutex_lock(>mutex);
if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
- if (lock_needed)
- mutex_unlock(>mutex);
+ mutex_unlock(>mutex);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 91c8b69da026..470b0377a860 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -476,13 +476,6 @@ struct pptable_funcs {
int (*display_config_changed)(struct smu_context *smu);
int (*apply_clocks_adjust_rules)(struct smu_context *smu);
int (*notify_smc_display_config)(struct smu_context *smu);
- int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
- int (*unforce_dpm_levels)(struct smu_context *smu);
-
[PATCH 11/16] drm/amd/powerplay: drop unnecessary Sienna Cichlid specific APIs
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Change-Id: I04c810859794b07ce8905a8df797ed6b5ae116a8
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 178 +-
1 file changed, 1 insertion(+), 177 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 8fae7dd982c7..27f77bde184f 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1181,59 +1181,6 @@ static int sienna_cichlid_display_config_changed(struct
smu_context *smu)
return ret;
}
-static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool
highest)
-{
- int ret = 0, i = 0;
- uint32_t min_freq, max_freq, force_freq;
- enum smu_clk_type clk_type;
-
- enum smu_clk_type clks[] = {
- SMU_GFXCLK,
- SMU_MCLK,
- SMU_SOCCLK,
- };
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- clk_type = clks[i];
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, _freq,
_freq);
- if (ret)
- return ret;
-
- force_freq = highest ? max_freq : min_freq;
- ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type,
force_freq, force_freq);
- if (ret)
- return ret;
- }
-
- return ret;
-}
-
-static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
-{
- int ret = 0, i = 0;
- uint32_t min_freq, max_freq;
- enum smu_clk_type clk_type;
-
- enum smu_clk_type clks[] = {
- SMU_GFXCLK,
- SMU_MCLK,
- SMU_SOCCLK,
- };
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- clk_type = clks[i];
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, _freq,
_freq);
- if (ret)
- return ret;
-
- ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type,
min_freq, max_freq);
- if (ret)
- return ret;
- }
-
- return ret;
-}
-
static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t
*value)
{
if (!value)
@@ -1486,50 +1433,6 @@ static int sienna_cichlid_set_power_profile_mode(struct
smu_context *smu, long *
return ret;
}
-static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
-enum amd_dpm_forced_level level,
-uint32_t *sclk_mask,
-uint32_t *mclk_mask,
-uint32_t *soc_mask)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret = 0;
- uint32_t level_count = 0;
-
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
- if (sclk_mask)
- *sclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
- if (mclk_mask)
- *mclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
- if(sclk_mask) {
- amdgpu_gfx_off_ctrl(adev, false);
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_SCLK,
_count);
- amdgpu_gfx_off_ctrl(adev, true);
- if (ret)
- return ret;
- *sclk_mask = level_count - 1;
- }
-
- if(mclk_mask) {
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_MCLK,
_count);
- if (ret)
- return ret;
- *mclk_mask = level_count - 1;
- }
-
- if(soc_mask) {
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK,
_count);
- if (ret)
- return ret;
- *soc_mask = level_count - 1;
- }
- }
-
- return ret;
-}
-
static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
{
struct smu_clocks min_clocks = {0};
@@ -1761,82 +1664,6 @@ static int sienna_cichlid_get_uclk_dpm_states(struct
smu_context *smu, uint32_t
return 0;
}
-static int sienna_cichlid_set_performance_level(struct smu_context *smu,
- enum amd_dpm_forced_level level);
-
-static int sienna_cichlid_set_standard_performance_level(struct smu_context
*smu)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret = 0;
- uint32_t sclk_freq = 0, uclk_freq = 0;
-
- switch (adev->asic_type) {
- /* TODO: need to set specify clk value by asic type, not support
[PATCH 01/16] drm/amd/powerplay: add more members for dpm table
These members can help to cache the clock frequencies for all
dpm levels. Then simplifying the code for dpm level switching
is possible.
Change-Id: Ic80359adb8c0e018f306782f24e3f8906436f5e2
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 3d746b75396e..289c571d6e4e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -48,6 +48,7 @@
#define SMU11_TOOL_SIZE0x19000
+#define MAX_DPM_LEVELS 16
#define MAX_PCIE_CONF 2
#define CLK_MAP(clk, index) \
@@ -91,9 +92,17 @@ struct smu_11_0_max_sustainable_clocks {
uint32_t soc_clock;
};
+struct smu_11_0_dpm_clk_level {
+ boolenabled;
+ uint32_tvalue;
+};
+
struct smu_11_0_dpm_table {
- uint32_tmin;/* MHz */
- uint32_tmax;/* MHz */
+ uint32_tmin;/* MHz */
+ uint32_tmax;/* MHz */
+ uint32_tcount;
+ boolis_fine_grained;
+ struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
};
struct smu_11_0_pcie_table {
@@ -107,7 +116,9 @@ struct smu_11_0_dpm_tables {
struct smu_11_0_dpm_tableuclk_table;
struct smu_11_0_dpm_tableeclk_table;
struct smu_11_0_dpm_tablevclk_table;
+ struct smu_11_0_dpm_tablevclk1_table;
struct smu_11_0_dpm_tabledclk_table;
+ struct smu_11_0_dpm_tabledclk1_table;
struct smu_11_0_dpm_tabledcef_table;
struct smu_11_0_dpm_tablepixel_table;
struct smu_11_0_dpm_tabledisplay_table;
--
2.27.0
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 10/16] drm/amd/powerplay: drop unnecessary Navi1x specific APIs
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Change-Id: I2c8831b9d00618c6578ee42b34e26892c5dba515
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 248 +
1 file changed, 1 insertion(+), 247 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index d3e11d81c0ad..6d638a67bc4d 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1376,59 +1376,6 @@ static int navi10_display_config_changed(struct
smu_context *smu)
return ret;
}
-static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
-{
- int ret = 0, i = 0;
- uint32_t min_freq, max_freq, force_freq;
- enum smu_clk_type clk_type;
-
- enum smu_clk_type clks[] = {
- SMU_GFXCLK,
- SMU_MCLK,
- SMU_SOCCLK,
- };
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- clk_type = clks[i];
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, _freq,
_freq);
- if (ret)
- return ret;
-
- force_freq = highest ? max_freq : min_freq;
- ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type,
force_freq, force_freq);
- if (ret)
- return ret;
- }
-
- return ret;
-}
-
-static int navi10_unforce_dpm_levels(struct smu_context *smu)
-{
- int ret = 0, i = 0;
- uint32_t min_freq, max_freq;
- enum smu_clk_type clk_type;
-
- enum smu_clk_type clks[] = {
- SMU_GFXCLK,
- SMU_MCLK,
- SMU_SOCCLK,
- };
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- clk_type = clks[i];
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, _freq,
_freq);
- if (ret)
- return ret;
-
- ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type,
min_freq, max_freq);
- if (ret)
- return ret;
- }
-
- return ret;
-}
-
static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
{
if (!value)
@@ -1681,47 +1628,6 @@ static int navi10_set_power_profile_mode(struct
smu_context *smu, long *input, u
return ret;
}
-static int navi10_get_profiling_clk_mask(struct smu_context *smu,
-enum amd_dpm_forced_level level,
-uint32_t *sclk_mask,
-uint32_t *mclk_mask,
-uint32_t *soc_mask)
-{
- int ret = 0;
- uint32_t level_count = 0;
-
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
- if (sclk_mask)
- *sclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
- if (mclk_mask)
- *mclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
- if(sclk_mask) {
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_SCLK,
_count);
- if (ret)
- return ret;
- *sclk_mask = level_count - 1;
- }
-
- if(mclk_mask) {
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_MCLK,
_count);
- if (ret)
- return ret;
- *mclk_mask = level_count - 1;
- }
-
- if(soc_mask) {
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK,
_count);
- if (ret)
- return ret;
- *soc_mask = level_count - 1;
- }
- }
-
- return ret;
-}
-
static int navi10_notify_smc_display_config(struct smu_context *smu)
{
struct smu_clocks min_clocks = {0};
@@ -1954,155 +1860,6 @@ static int navi10_get_uclk_dpm_states(struct
smu_context *smu, uint32_t *clocks_
return 0;
}
-static int navi10_set_performance_level(struct smu_context *smu,
- enum amd_dpm_forced_level level);
-
-static int navi10_set_standard_performance_level(struct smu_context *smu)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret = 0;
- uint32_t sclk_freq = 0, uclk_freq = 0;
-
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- sclk_freq = NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
- uclk_freq = NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
- break;
- case CHIP_NAVI14:
- sclk_freq = NAVI14_UMD_PSTATE_PROFILING_GFXCLK;
- uclk_freq = NAVI14_UMD_PSTATE_PROFILING_MEMCLK;
-
[PATCH 06/16] drm/amd/powerplay: add new UMD pstate data structure
This is used to cache the clock frequencies for all UMD pstates.
So that we do not need to calculate from scratch on every UMD
pstate switch.
Change-Id: I3f2ef5ee2e6e433518f726988bbe5970848b99c8
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 66912884f093..91c8b69da026 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -352,6 +352,20 @@ struct smu_baco_context
bool platform_support;
};
+struct pstates_clk_freq {
+ uint32_tmin;
+ uint32_tstandard;
+ uint32_tpeak;
+};
+
+struct smu_umd_pstate_table {
+ struct pstates_clk_freq gfxclk_pstate;
+ struct pstates_clk_freq socclk_pstate;
+ struct pstates_clk_freq uclk_pstate;
+ struct pstates_clk_freq vclk_pstate;
+ struct pstates_clk_freq dclk_pstate;
+};
+
#define WORKLOAD_POLICY_MAX 7
struct smu_context
{
@@ -376,6 +390,7 @@ struct smu_context
struct dentry *debugfs_sclk;
#endif
+ struct smu_umd_pstate_table pstate_table;
uint32_t pstate_sclk;
uint32_t pstate_mclk;
--
2.27.0
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/16] drm/amd/powerplay: drop unnecessary Arcturus specific APIs
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Change-Id: Icd96ce42218d78d670dd0c1f88663fd42108b311
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 170 ---
1 file changed, 170 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 33d472ffb2be..afd07c497205 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1218,173 +1218,6 @@ static int arcturus_get_fan_speed_percent(struct
smu_context *smu,
return ret;
}
-static uint32_t arcturus_find_lowest_dpm_level(struct smu_11_0_dpm_table
*table)
-{
- uint32_t i;
-
- for (i = 0; i < table->count; i++) {
- if (table->dpm_levels[i].enabled)
- break;
- }
- if (i >= table->count) {
- i = 0;
- table->dpm_levels[i].enabled = true;
- }
-
- return i;
-}
-
-static uint32_t arcturus_find_highest_dpm_level(struct smu_context *smu,
- struct smu_11_0_dpm_table
*table)
-{
- int i = 0;
-
- if (table->count <= 0) {
- dev_err(smu->adev->dev, "[%s] DPM Table has no entry!",
__func__);
- return 0;
- }
- if (table->count > MAX_DPM_NUMBER) {
- dev_err(smu->adev->dev, "[%s] DPM Table has too many entries!",
__func__);
- return MAX_DPM_NUMBER - 1;
- }
-
- for (i = table->count - 1; i >= 0; i--) {
- if (table->dpm_levels[i].enabled)
- break;
- }
- if (i < 0) {
- i = 0;
- table->dpm_levels[i].enabled = true;
- }
-
- return i;
-}
-
-static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool
highest)
-{
- struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
- struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
- uint32_t soft_level;
- int ret = 0;
-
- /* gfxclk */
- if (highest)
- soft_level = arcturus_find_highest_dpm_level(smu,
&(dpm_context->dpm_tables.gfx_table));
- else
- soft_level =
arcturus_find_lowest_dpm_level(&(dpm_context->dpm_tables.gfx_table));
-
- ret = arcturus_upload_dpm_level(smu,
- false,
- FEATURE_DPM_GFXCLK_MASK,
- soft_level);
- if (ret) {
- dev_err(smu->adev->dev, "Failed to upload boot level to %s!\n",
- highest ? "highest" : "lowest");
- return ret;
- }
-
- ret = arcturus_upload_dpm_level(smu,
- true,
- FEATURE_DPM_GFXCLK_MASK,
- soft_level);
- if (ret) {
- dev_err(smu->adev->dev, "Failed to upload dpm max level to
%s!\n!",
- highest ? "highest" : "lowest");
- return ret;
- }
-
- if (hive)
- /*
-* Force XGMI Pstate to highest or lowest
-* TODO: revise this when xgmi dpm is functional
-*/
- ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
-
- return ret;
-}
-
-static int arcturus_unforce_dpm_levels(struct smu_context *smu)
-{
- struct smu_11_0_dpm_context *dpm_context =
- (struct smu_11_0_dpm_context *)smu->smu_dpm.dpm_context;
- struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
- uint32_t soft_min_level, soft_max_level;
- int ret = 0;
-
- /* gfxclk */
- soft_min_level =
arcturus_find_lowest_dpm_level(&(dpm_context->dpm_tables.gfx_table));
- soft_max_level = arcturus_find_highest_dpm_level(smu,
&(dpm_context->dpm_tables.gfx_table));
-
- ret = arcturus_upload_dpm_level(smu,
- false,
- FEATURE_DPM_GFXCLK_MASK,
- soft_min_level);
- if (ret) {
- dev_err(smu->adev->dev, "Failed to upload DPM Bootup Levels!");
- return ret;
- }
-
- ret = arcturus_upload_dpm_level(smu,
- true,
- FEATURE_DPM_GFXCLK_MASK,
- soft_max_level);
- if (ret) {
- dev_err(smu->adev->dev, "Failed to upload DPM Max Levels!");
- return ret;
- }
-
- if (hive)
- /*
-* Reset XGMI Pstate back to default
-* TODO: revise this when xgmi dpm is functional
-*/
- ret
[PATCH 07/16] drm/amd/powerplay: update UMD pstate clock settings
Preparing for coming code sharing around performance level
setting.
Change-Id: I51b1536b62995f0fecd51b91f238793f57485aa9
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 6 +-
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 47 ++---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 99 ---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 35 ---
4 files changed, 141 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6839faaab611..4080b3c792ac 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2168,6 +2168,8 @@ int smu_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor,
void *data, uint32_t *size)
{
+ struct smu_umd_pstate_table *pstate_table =
+ >pstate_table;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2180,11 +2182,11 @@ int smu_read_sensor(struct smu_context *smu,
switch (sensor) {
case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
- *((uint32_t *)data) = smu->pstate_sclk;
+ *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard *
100;
*size = 4;
break;
case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
- *((uint32_t *)data) = smu->pstate_mclk;
+ *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
*size = 4;
break;
case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index a3747ab4af32..33d472ffb2be 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -548,27 +548,44 @@ static int arcturus_run_btc(struct smu_context *smu)
static int arcturus_populate_umd_state_clk(struct smu_context *smu)
{
- struct smu_dpm_context *smu_dpm = >smu_dpm;
- struct arcturus_dpm_table *dpm_table = NULL;
- struct arcturus_single_dpm_table *gfx_table = NULL;
- struct arcturus_single_dpm_table *mem_table = NULL;
+ struct smu_11_0_dpm_context *dpm_context =
+ smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_table *gfx_table =
+ _context->dpm_tables.gfx_table;
+ struct smu_11_0_dpm_table *mem_table =
+ _context->dpm_tables.uclk_table;
+ struct smu_11_0_dpm_table *soc_table =
+ _context->dpm_tables.soc_table;
+ struct smu_umd_pstate_table *pstate_table =
+ >pstate_table;
+
+ pstate_table->gfxclk_pstate.min = gfx_table->min;
+ pstate_table->gfxclk_pstate.peak = gfx_table->max;
- dpm_table = smu_dpm->dpm_context;
- gfx_table = &(dpm_table->gfx_table);
- mem_table = &(dpm_table->mem_table);
+ pstate_table->uclk_pstate.min = mem_table->min;
+ pstate_table->uclk_pstate.peak = mem_table->max;
- smu->pstate_sclk = gfx_table->dpm_levels[0].value;
- smu->pstate_mclk = mem_table->dpm_levels[0].value;
+ pstate_table->socclk_pstate.min = soc_table->min;
+ pstate_table->socclk_pstate.peak = soc_table->max;
if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
- mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
- smu->pstate_sclk =
gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
- smu->pstate_mclk =
mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
+ mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
+ soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
+ pstate_table->gfxclk_pstate.standard =
+
gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
+ pstate_table->uclk_pstate.standard =
+
mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
+ pstate_table->socclk_pstate.standard =
+
soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
+ } else {
+ pstate_table->gfxclk_pstate.standard =
+ pstate_table->gfxclk_pstate.min;
+ pstate_table->uclk_pstate.standard =
+ pstate_table->uclk_pstate.min;
+ pstate_table->socclk_pstate.standard =
+ pstate_table->socclk_pstate.min;
}
- smu->pstate_sclk = smu->pstate_sclk * 100;
- smu->pstate_mclk = smu->pstate_mclk * 100;
-
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index a022e93a487c..d3e11d81c0ad 100644
---
[PATCH 02/16] drm/amd/powerplay: implement a common set dpm table API for smu V11
Maximum the code sharing around smu V11.
Change-Id: Ice0a874f3f70457f1012ca566f9f784ff3e9cd94
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 38 +++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 289c571d6e4e..14d6eef8cf17 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -285,6 +285,10 @@ int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *value);
+int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct smu_11_0_dpm_table *single_dpm_table);
+
int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min_value,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 03be59492af1..7206b9f76042 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1951,6 +1951,44 @@ int smu_v11_0_get_dpm_level_count(struct smu_context
*smu,
value);
}
+int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct smu_11_0_dpm_table *single_dpm_table)
+{
+ int ret = 0;
+ uint32_t clk;
+ int i;
+
+ ret = smu_v11_0_get_dpm_level_count(smu,
+ clk_type,
+ _dpm_table->count);
+ if (ret) {
+ dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n",
__func__);
+ return ret;
+ }
+
+ for (i = 0; i < single_dpm_table->count; i++) {
+ ret = smu_v11_0_get_dpm_freq_by_index(smu,
+ clk_type,
+ i,
+ );
+ if (ret) {
+ dev_err(smu->adev->dev, "[%s] failed to get dpm freq by
index!\n", __func__);
+ return ret;
+ }
+
+ single_dpm_table->dpm_levels[i].value = clk;
+ single_dpm_table->dpm_levels[i].enabled = true;
+
+ if (i == 0)
+ single_dpm_table->min = clk;
+ else if (i == single_dpm_table->count - 1)
+ single_dpm_table->max = clk;
+ }
+
+ return 0;
+}
+
int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min_value,
--
2.27.0
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[PATCH 05/16] drm/amd/powerplay: update Sienna Cichlid default dpm table setup
Cache all clocks levels for every dpm table. They are needed
by other APIs.
Change-Id: Idaa853356720e48ab3279f420ba1ae18bb7de4fd
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 234 --
1 file changed, 211 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index f2bbe56798d7..d750d06378e9 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -597,41 +597,229 @@ static int sienna_cichlid_allocate_dpm_context(struct
smu_context *smu)
static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
{
- struct smu_dpm_context *smu_dpm = >smu_dpm;
- struct smu_table_context *table_context = >smu_table;
- struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
- PPTable_t *driver_ppt = NULL;
+ struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
+ PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
+ struct smu_11_0_dpm_table *dpm_table;
+ int ret = 0;
int i;
-driver_ppt = table_context->driver_pptable;
+ /* socclk dpm table setup */
+ dpm_table = _context->dpm_tables.soc_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_SOCCLK,
+dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value =
smu->smu_table.boot_values.socclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
+
+ /* gfxclk dpm table setup */
+ dpm_table = _context->dpm_tables.gfx_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_GFXCLK,
+dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value =
smu->smu_table.boot_values.gfxclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
+
+ /* uclk dpm table setup */
+ dpm_table = _context->dpm_tables.uclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_UCLK,
+dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value =
smu->smu_table.boot_values.uclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
-dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
-dpm_context->dpm_tables.soc_table.max =
driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
+ /* fclk dpm table setup */
+ dpm_table = _context->dpm_tables.fclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_FCLK,
+dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value =
smu->smu_table.boot_values.fclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
-dpm_context->dpm_tables.gfx_table.min =
[PATCH 12/16] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range
Use the common smu_v11_0_set_soft_freq_limited_range.
Change-Id: I9f8772880b324ce9e741291751bb1b8ff4c36ea3
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 20 ++-
drivers/gpu/drm/amd/powerplay/smu_internal.h | 1 -
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 20 +++
3 files changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 27f77bde184f..141944df97b0 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1046,22 +1046,6 @@ static int sienna_cichlid_print_clk_levels(struct
smu_context *smu,
return size;
}
-int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
- enum smu_clk_type clk_type,
- uint32_t min, uint32_t max)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret;
-
- if (clk_type == SMU_GFXCLK)
- amdgpu_gfx_off_ctrl(adev, false);
- ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max);
- if (clk_type == SMU_GFXCLK)
- amdgpu_gfx_off_ctrl(adev, true);
-
- return ret;
-}
-
static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, uint32_t mask)
{
@@ -1097,7 +1081,7 @@ static int sienna_cichlid_force_clk_levels(struct
smu_context *smu,
if (ret)
goto forec_level_out;
- ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type,
min_freq, max_freq);
+ ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type,
min_freq, max_freq);
if (ret)
goto forec_level_out;
break;
@@ -2566,7 +2550,7 @@ static const struct pptable_funcs
sienna_cichlid_ppt_funcs = {
.baco_enter = smu_v11_0_baco_enter,
.baco_exit = smu_v11_0_baco_exit,
.get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
- .set_soft_freq_limited_range =
sienna_cichlid_set_soft_freq_limited_range,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
.set_thermal_range = sienna_cichlid_set_thermal_range,
};
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 1c808ffe3ab1..91d3965bbe80 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -93,7 +93,6 @@
#define smu_asic_set_performance_level(smu, level)
smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)
#define smu_dump_pptable(smu)
smu_ppt_funcs(dump_pptable, 0, smu)
#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq)
smu_ppt_funcs(get_dpm_clk_limited, -EINVAL, smu, clk_type, dpm_level, freq)
-#define smu_set_soft_freq_limited_range(smu, clk_type, min, max)
smu_ppt_funcs(set_soft_freq_limited_range, -EINVAL, smu, clk_type, min, max)
#define smu_override_pcie_parameters(smu)
smu_ppt_funcs(override_pcie_parameters, 0, smu)
#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap)
smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)
#define smu_set_thermal_range(smu, range)
smu_ppt_funcs(set_thermal_range, 0, smu, range)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index f96ff062eb64..c2779d0b51f6 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1745,9 +1745,12 @@ int smu_v11_0_get_dpm_ultimate_freq(struct smu_context
*smu, enum smu_clk_type c
return ret;
}
-int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum
smu_clk_type clk_type,
- uint32_t min, uint32_t max)
+int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t min,
+ uint32_t max)
{
+ struct amdgpu_device *adev = smu->adev;
int ret = 0, clk_id = 0;
uint32_t param;
@@ -1755,12 +1758,16 @@ int smu_v11_0_set_soft_freq_limited_range(struct
smu_context *smu, enum smu_clk_
if (clk_id < 0)
return clk_id;
+ if (clk_type == SMU_GFXCLK &&
+ adev->asic_type == CHIP_SIENNA_CICHLID)
+ amdgpu_gfx_off_ctrl(adev, false);
+
if (max > 0) {
param = (uint32_t)((clk_id << 16) | (max & 0x));
ret =
[PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
Before and after setting gfx clock soft max/min frequency.
Change-Id: I6f828da8de096ebc0ae27eaa89f988def2d547ec
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c2779d0b51f6..33e0718f2635 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1758,8 +1758,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct
smu_context *smu,
if (clk_id < 0)
return clk_id;
- if (clk_type == SMU_GFXCLK &&
- adev->asic_type == CHIP_SIENNA_CICHLID)
+ if (clk_type == SMU_GFXCLK)
amdgpu_gfx_off_ctrl(adev, false);
if (max > 0) {
@@ -1779,8 +1778,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct
smu_context *smu,
}
out:
- if (clk_type == SMU_GFXCLK &&
- adev->asic_type == CHIP_SIENNA_CICHLID)
+ if (clk_type == SMU_GFXCLK)
amdgpu_gfx_off_ctrl(adev, true);
return ret;
--
2.27.0
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[PATCH 14/16] drm/amd/powerplay: drop unnecessary wrappers
By calling the target APIs directly.
Change-Id: I0f24f603d2fcb94d2078a35c405a1406093ba5e3
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index d4aa01a05c54..49a8d636ef4d 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -743,26 +743,26 @@ static int renoir_set_performance_level(struct
smu_context *smu,
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
- ret = smu_force_dpm_limit_value(smu, true);
+ ret = renoir_force_dpm_limit_value(smu, true);
break;
case AMD_DPM_FORCED_LEVEL_LOW:
- ret = smu_force_dpm_limit_value(smu, false);
+ ret = renoir_force_dpm_limit_value(smu, false);
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- ret = smu_unforce_dpm_levels(smu);
+ ret = renoir_unforce_dpm_levels(smu);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
- ret = smu_get_profiling_clk_mask(smu, level,
-_mask,
-_mask,
-_mask);
+ ret = renoir_get_profiling_clk_mask(smu, level,
+ _mask,
+ _mask,
+ _mask);
if (ret)
return ret;
- smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
- smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
- smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
+ renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
+ renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
+ renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
ret = renoir_set_peak_clock_by_device(smu);
@@ -942,8 +942,6 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.get_current_power_state = renoir_get_current_power_state,
.dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
.dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
- .force_dpm_limit_value = renoir_force_dpm_limit_value,
- .unforce_dpm_levels = renoir_unforce_dpm_levels,
.get_workload_type = renoir_get_workload_type,
.get_profiling_clk_mask = renoir_get_profiling_clk_mask,
.force_clk_levels = renoir_force_clk_levels,
--
2.27.0
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[PATCH 15/16] drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper
By moving the implemention to renoir_ppt.c considering
it's really ASIC specific.
Change-Id: I6f7a594235dffdf75b56d1de5b9dc6d49833d7e8
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 3 -
drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 172 ++
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 100 --
3 files changed, 138 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 0c1e1455c68f..fd83a723f32c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -73,9 +73,6 @@ int smu_v12_0_set_default_dpm_tables(struct smu_context *smu);
int smu_v12_0_get_enabled_mask(struct smu_context *smu,
uint32_t *feature_mask, uint32_t num);
-int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type
clk_type,
-uint32_t *min, uint32_t *max);
-
int smu_v12_0_mode2_reset(struct smu_context *smu);
int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum
smu_clk_type clk_type,
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 49a8d636ef4d..5b76d67d03d7 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -241,6 +241,137 @@ static int renoir_get_dpm_clk_limited(struct smu_context
*smu, enum smu_clk_type
return 0;
}
+static int renoir_get_profiling_clk_mask(struct smu_context *smu,
+enum amd_dpm_forced_level level,
+uint32_t *sclk_mask,
+uint32_t *mclk_mask,
+uint32_t *soc_mask)
+{
+
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
+ if (sclk_mask)
+ *sclk_mask = 0;
+ } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
+ if (mclk_mask)
+ *mclk_mask = 0;
+ } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ if(sclk_mask)
+ /* The sclk as gfxclk and has three level about
max/min/current */
+ *sclk_mask = 3 - 1;
+
+ if(mclk_mask)
+ *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
+
+ if(soc_mask)
+ *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
+ }
+
+ return 0;
+}
+
+static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *min,
+ uint32_t *max)
+{
+ int ret = 0;
+ uint32_t mclk_mask, soc_mask;
+ uint32_t clock_limit;
+
+ if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
+ switch (clk_type) {
+ case SMU_MCLK:
+ case SMU_UCLK:
+ clock_limit = smu->smu_table.boot_values.uclk;
+ break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clock_limit = smu->smu_table.boot_values.gfxclk;
+ break;
+ case SMU_SOCCLK:
+ clock_limit = smu->smu_table.boot_values.socclk;
+ break;
+ default:
+ clock_limit = 0;
+ break;
+ }
+
+ /* clock in Mhz unit */
+ if (min)
+ *min = clock_limit / 100;
+ if (max)
+ *max = clock_limit / 100;
+
+ return 0;
+ }
+
+ if (max) {
+ ret = renoir_get_profiling_clk_mask(smu,
+
AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
+ NULL,
+ _mask,
+ _mask);
+ if (ret)
+ goto failed;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ ret = smu_send_smc_msg(smu,
SMU_MSG_GetMaxGfxclkFrequency, max);
+ if (ret) {
+ dev_err(smu->adev->dev, "Attempt to get max GX
frequency from SMC Failed !\n");
+ goto failed;
+ }
+ break;
+ case SMU_UCLK:
+ case SMU_FCLK:
+ case SMU_MCLK:
+ ret = renoir_get_dpm_clk_limited(smu, clk_type,
mclk_mask, max);
+ if (ret)
+
[PATCH 08/16] drm/amd/powerplay: update the common API for performance level setting
So that it can be more widely shared around SMU v11 ASICs.
Change-Id: Ie110edf2ec519699448d3ff3215188ba243d2415
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 91 +++
1 file changed, 77 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 7206b9f76042..f96ff062eb64 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1855,38 +1855,101 @@ int smu_v11_0_override_pcie_parameters(struct
smu_context *smu)
int smu_v11_0_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
+ struct smu_11_0_dpm_context *dpm_context =
+ smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_table *gfx_table =
+ _context->dpm_tables.gfx_table;
+ struct smu_11_0_dpm_table *mem_table =
+ _context->dpm_tables.uclk_table;
+ struct smu_11_0_dpm_table *soc_table =
+ _context->dpm_tables.soc_table;
+ struct smu_umd_pstate_table *pstate_table =
+ >pstate_table;
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t sclk_min = 0, sclk_max = 0;
+ uint32_t mclk_min = 0, mclk_max = 0;
+ uint32_t socclk_min = 0, socclk_max = 0;
int ret = 0;
- uint32_t sclk_mask, mclk_mask, soc_mask;
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
- ret = smu_force_dpm_limit_value(smu, true);
+ sclk_min = sclk_max = gfx_table->max;
+ mclk_min = mclk_max = mem_table->max;
+ socclk_min = socclk_max = soc_table->max;
break;
case AMD_DPM_FORCED_LEVEL_LOW:
- ret = smu_force_dpm_limit_value(smu, false);
+ sclk_min = sclk_max = gfx_table->min;
+ mclk_min = mclk_max = mem_table->min;
+ socclk_min = socclk_max = soc_table->min;
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
+ sclk_min = gfx_table->min;
+ sclk_max = gfx_table->max;
+ mclk_min = mem_table->min;
+ mclk_max = mem_table->max;
+ socclk_min = soc_table->min;
+ socclk_max = soc_table->max;
+ break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- ret = smu_unforce_dpm_levels(smu);
+ sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
+ mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
+ socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+ sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
+ break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+ mclk_min = mclk_max = pstate_table->uclk_pstate.min;
+ break;
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- ret = smu_get_profiling_clk_mask(smu, level,
-_mask,
-_mask,
-_mask);
- if (ret)
- return ret;
- smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
- smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
- smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
+ sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
+ mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
+ socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+ return 0;
default:
- break;
+ dev_err(adev->dev, "Invalid performance level %d\n", level);
+ return -EINVAL;
+ }
+
+ /*
+* Separate MCLK and SOCCLK soft min/max settings are not allowed
+* on Arcturus.
+*/
+ if (adev->asic_type == CHIP_ARCTURUS) {
+ mclk_min = mclk_max = 0;
+ socclk_min = socclk_max = 0;
}
+
+ if (sclk_min && sclk_max) {
+ ret = smu_v11_0_set_soft_freq_limited_range(smu,
+ SMU_GFXCLK,
+ sclk_min,
+ sclk_max);
+ if (ret)
+ return ret;
+ }
+
+ if (mclk_min && mclk_max) {
+ ret = smu_v11_0_set_soft_freq_limited_range(smu,
+
[PATCH 03/16] drm/amd/powerplay: update Arcturus default dpm table setting
Preparing for coming code sharing around performance level
setting.
Change-Id: Iaa77af7a272121503f09ad5fbfbe9dff2d2597b1
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 297 ---
1 file changed, 119 insertions(+), 178 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 5b793e354704..a3747ab4af32 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -291,7 +291,6 @@ static int arcturus_get_pwr_src_index(struct smu_context
*smc, uint32_t index)
return mapping.map_to;
}
-
static int arcturus_get_workload_type(struct smu_context *smu, enum
PP_SMC_POWER_PROFILE profile)
{
struct smu_11_0_cmn2aisc_mapping mapping;
@@ -338,23 +337,11 @@ static int arcturus_allocate_dpm_context(struct
smu_context *smu)
{
struct smu_dpm_context *smu_dpm = >smu_dpm;
- if (smu_dpm->dpm_context)
- return -EINVAL;
-
- smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
+ smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
GFP_KERNEL);
if (!smu_dpm->dpm_context)
return -ENOMEM;
-
- if (smu_dpm->golden_dpm_context)
- return -EINVAL;
-
- smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
- GFP_KERNEL);
- if (!smu_dpm->golden_dpm_context)
- return -ENOMEM;
-
- smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
+ smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct
smu_power_state),
GFP_KERNEL);
@@ -382,119 +369,84 @@ arcturus_get_allowed_feature_mask(struct smu_context
*smu,
return 0;
}
-static int
-arcturus_set_single_dpm_table(struct smu_context *smu,
- struct arcturus_single_dpm_table *single_dpm_table,
- PPCLK_e clk_id)
-{
- int ret = 0;
- uint32_t i, num_of_levels = 0, clk;
-
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_GetDpmFreqByIndex,
- (clk_id << 16 | 0xFF),
- _of_levels);
- if (ret) {
- dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n",
__func__);
- return ret;
- }
-
- single_dpm_table->count = num_of_levels;
- for (i = 0; i < num_of_levels; i++) {
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_GetDpmFreqByIndex,
- (clk_id << 16 | i),
- );
- if (ret) {
- dev_err(smu->adev->dev, "[%s] failed to get dpm freq by
index!\n", __func__);
- return ret;
- }
- single_dpm_table->dpm_levels[i].value = clk;
- single_dpm_table->dpm_levels[i].enabled = true;
- }
- return 0;
-}
-
-static void arcturus_init_single_dpm_state(struct arcturus_dpm_state
*dpm_state)
-{
- dpm_state->soft_min_level = 0x0;
- dpm_state->soft_max_level = 0x;
-dpm_state->hard_min_level = 0x0;
-dpm_state->hard_max_level = 0x;
-}
-
static int arcturus_set_default_dpm_table(struct smu_context *smu)
{
- int ret;
-
- struct smu_dpm_context *smu_dpm = >smu_dpm;
- struct arcturus_dpm_table *dpm_table = NULL;
- struct arcturus_single_dpm_table *single_dpm_table;
-
- dpm_table = smu_dpm->dpm_context;
+ struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
+ PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
+ struct smu_11_0_dpm_table *dpm_table = NULL;
+ int ret = 0;
- /* socclk */
- single_dpm_table = &(dpm_table->soc_table);
+ /* socclk dpm table setup */
+ dpm_table = _context->dpm_tables.soc_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
- ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
- PPCLK_SOCCLK);
- if (ret) {
- dev_err(smu->adev->dev, "[%s] failed to get socclk dpm
levels!\n", __func__);
+ ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_SOCCLK,
+dpm_table);
+ if (ret)
return ret;
- }
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
} else {
- single_dpm_table->count = 1;
-
[PATCH 04/16] drm/amd/powerplay: update Navi10 default dpm table setup
Cache all clocks levels for every dpm table. They are needed
by other APIs.
Change-Id: I8114cf31e6ec8c9af4578d51749eb213befdcc71
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 182 ++---
1 file changed, 158 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index d96e8334b5e2..a022e93a487c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -689,41 +689,175 @@ static int navi10_allocate_dpm_context(struct
smu_context *smu)
static int navi10_set_default_dpm_table(struct smu_context *smu)
{
- struct smu_dpm_context *smu_dpm = >smu_dpm;
- struct smu_table_context *table_context = >smu_table;
- struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
- PPTable_t *driver_ppt = NULL;
+ struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
+ PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
+ struct smu_11_0_dpm_table *dpm_table;
+ int ret = 0;
int i;
- driver_ppt = table_context->driver_pptable;
-
- dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
- dpm_context->dpm_tables.soc_table.max =
driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
+ /* socclk dpm table setup */
+ dpm_table = _context->dpm_tables.soc_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_SOCCLK,
+dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value =
smu->smu_table.boot_values.socclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
- dpm_context->dpm_tables.gfx_table.max =
driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
+ /* gfxclk dpm table setup */
+ dpm_table = _context->dpm_tables.gfx_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_GFXCLK,
+dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value =
smu->smu_table.boot_values.gfxclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
- dpm_context->dpm_tables.uclk_table.max =
driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
+ /* uclk dpm table setup */
+ dpm_table = _context->dpm_tables.uclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_UCLK,
+dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value =
smu->smu_table.boot_values.uclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
- dpm_context->dpm_tables.vclk_table.max =
driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
+ /* vclk dpm table setup */
+ dpm_table = _context->dpm_tables.vclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_VCLK,
+dpm_table);
+ if (ret)
+ return ret;
+
RE: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
Best Regards
Kenneth
-Original Message-
From: Gao, Likun
Sent: Friday, July 10, 2020 11:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth
; Gao, Likun
Subject: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
From: Likun Gao
Update sienna_cichlid driver if header and related files.
Signed-off-by: Likun Gao
Change-Id: If303e7fca32ebf922ee5d918855bbaca8dc61d38
---
.../inc/smu11_driver_if_sienna_cichlid.h| 17 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
.../gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 -
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index 302c2bcf9404..b2232e24d82f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if // any structure is
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x32
+#define SMU11_DRIVER_IF_VERSION 0x33
-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
#define NUM_GFXCLK_DPM_LEVELS 16
#define NUM_SMNCLK_DPM_LEVELS 2
@@ -128,7 +128,7 @@
#define FEATURE_2_STEP_PSTATE_BIT 46
#define FEATURE_SMNCLK_DPM_BIT 47
#define FEATURE_SPARE_48_BIT48
-#define FEATURE_SPARE_49_BIT49
+#define FEATURE_GFX_EDC_BIT 49
#define FEATURE_SPARE_50_BIT50
#define FEATURE_SPARE_51_BIT51
#define FEATURE_SPARE_52_BIT52
@@ -564,6 +564,12 @@ typedef enum {
TDC_THROTTLER_COUNT
} TDC_THROTTLER_e;
+typedef enum {
+ CUSTOMER_VARIANT_ROW,
+ CUSTOMER_VARIANT_FALCON,
+ CUSTOMER_VARIANT_COUNT,
+} CUSTOMER_VARIANT_e;
+
// Used for 2-step UCLK DPM change workaround typedef struct {
uint16_t Fmin;
@@ -786,7 +792,10 @@ typedef struct {
QuadraticInt_tReservedEquation3;
// SECTION: Sku Reserved
- uint32_t SkuReserved[15];
+ uint8_t CustomerVariant;
+ uint8_t Spare[3];
+ uint32_t SkuReserved[14];
+
// MAJOR SECTION: BOARD PARAMETERS
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index d07bf4fe6e4a..b2f65438ad8d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36 #define
SMU11_DRIVER_IF_VERSION_NV12 0x33 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x32
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
/* MP Apertures */
#define MP0_Public 0x0380
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dc5ca9121db5..3efa41444ddf 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -2317,7 +2317,6 @@ static void sienna_cichlid_dump_pptable(struct
smu_context *smu)
dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n",
pptable->SkuReserved[11]);
dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n",
pptable->SkuReserved[12]);
dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n",
pptable->SkuReserved[13]);
- dev_info(smu->adev->dev, "SkuReserved[14] = 0x%x\n",
pptable->SkuReserved[14]);
dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n",
pptable->GamingClk[0]);
dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n",
pptable->GamingClk[1]);
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
From: Likun Gao
Update sienna_cichlid driver if header and related files.
Signed-off-by: Likun Gao
Change-Id: If303e7fca32ebf922ee5d918855bbaca8dc61d38
---
.../inc/smu11_driver_if_sienna_cichlid.h| 17 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
.../gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 -
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index 302c2bcf9404..b2232e24d82f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x32
+#define SMU11_DRIVER_IF_VERSION 0x33
-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
#define NUM_GFXCLK_DPM_LEVELS 16
#define NUM_SMNCLK_DPM_LEVELS 2
@@ -128,7 +128,7 @@
#define FEATURE_2_STEP_PSTATE_BIT 46
#define FEATURE_SMNCLK_DPM_BIT 47
#define FEATURE_SPARE_48_BIT48
-#define FEATURE_SPARE_49_BIT49
+#define FEATURE_GFX_EDC_BIT 49
#define FEATURE_SPARE_50_BIT50
#define FEATURE_SPARE_51_BIT51
#define FEATURE_SPARE_52_BIT52
@@ -564,6 +564,12 @@ typedef enum {
TDC_THROTTLER_COUNT
} TDC_THROTTLER_e;
+typedef enum {
+ CUSTOMER_VARIANT_ROW,
+ CUSTOMER_VARIANT_FALCON,
+ CUSTOMER_VARIANT_COUNT,
+} CUSTOMER_VARIANT_e;
+
// Used for 2-step UCLK DPM change workaround
typedef struct {
uint16_t Fmin;
@@ -786,7 +792,10 @@ typedef struct {
QuadraticInt_tReservedEquation3;
// SECTION: Sku Reserved
- uint32_t SkuReserved[15];
+ uint8_t CustomerVariant;
+ uint8_t Spare[3];
+ uint32_t SkuReserved[14];
+
// MAJOR SECTION: BOARD PARAMETERS
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index d07bf4fe6e4a..b2f65438ad8d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x32
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
/* MP Apertures */
#define MP0_Public 0x0380
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dc5ca9121db5..3efa41444ddf 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -2317,7 +2317,6 @@ static void sienna_cichlid_dump_pptable(struct
smu_context *smu)
dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n",
pptable->SkuReserved[11]);
dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n",
pptable->SkuReserved[12]);
dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n",
pptable->SkuReserved[13]);
- dev_info(smu->adev->dev, "SkuReserved[14] = 0x%x\n",
pptable->SkuReserved[14]);
dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n",
pptable->GamingClk[0]);
dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n",
pptable->GamingClk[1]);
--
2.25.1
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RE: [PATCH] drm/amd/smu: correct a mistake
[AMD Official Use Only - Internal Distribution Only] There is already a patch for this. https://lists.freedesktop.org/archives/amd-gfx/2020-July/051134.html -Original Message- From: chen gong Sent: Thursday, July 9, 2020 6:41 PM To: amd-gfx@lists.freedesktop.org Cc: Quan, Evan ; Gong, Curry Subject: [PATCH] drm/amd/smu: correct a mistake Corresponding to smu_workload_get_type(smu, type) is "get_workload_type" Signed-off-by: chen gong --- drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h index afd786b..31e1fcb 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h @@ -77,7 +77,7 @@ #define smu_feature_get_index(smu, fea)smu_ppt_funcs(get_smu_feature_index, -EINVAL, smu, fea) #define smu_table_get_index(smu, tab)smu_ppt_funcs(get_smu_table_index, -EINVAL, smu, tab) #define smu_power_get_index(smu, src)smu_ppt_funcs(get_smu_power_index, -EINVAL, smu, src) -#define smu_workload_get_type(smu, type)smu_ppt_funcs(get_smu_power_index, -EINVAL, smu, type) +#define smu_workload_get_type(smu, type)smu_ppt_funcs(get_workload_type, -EINVAL, smu, type) #define smu_run_btc(smu)smu_ppt_funcs(run_btc, 0, smu) #define smu_get_allowed_feature_mask(smu, feature_mask, num)smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num) #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis)smu_ppt_funcs(store_cc6_data, 0, smu, st, cc6_dis, pst_dis, pst_sw_dis) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: minor cleanup of phase1 suspend code
On Thu, Jul 9, 2020 at 3:15 PM Nirmoy Das wrote:
>
> Cleanup of phase1 suspend code to reduce unnecessary indentation.
>
> Signed-off-by: Nirmoy Das
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 --
> 1 file changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 2913e41f63a5..81ca92127c00 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2456,18 +2456,21 @@ static int amdgpu_device_ip_suspend_phase1(struct
> amdgpu_device *adev)
> for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
> if (!adev->ip_blocks[i].status.valid)
> continue;
> +
> /* displays are handled separately */
> - if (adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_DCE) {
> - /* XXX handle errors */
> - r = adev->ip_blocks[i].version->funcs->suspend(adev);
> - /* XXX handle errors */
> - if (r) {
> - DRM_ERROR("suspend of IP block <%s> failed
> %d\n",
> -
> adev->ip_blocks[i].version->funcs->name, r);
> - return r;
> - }
> - adev->ip_blocks[i].status.hw = false;
> + if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
> + continue;
> +
> + /* XXX handle errors */
> + r = adev->ip_blocks[i].version->funcs->suspend(adev);
> + /* XXX handle errors */
> + if (r) {
> + DRM_ERROR("suspend of IP block <%s> failed %d\n",
> + adev->ip_blocks[i].version->funcs->name, r);
> + return r;
> }
> +
> + adev->ip_blocks[i].status.hw = false;
> }
>
> return 0;
> --
> 2.27.0
>
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Re: [PATCH 6/6] drm/amd/powerplay: drop unused code around thermal range setting
On Fri, Jul 3, 2020 at 4:59 AM Evan Quan wrote:
>
> Leftover of previous cleanups.
>
> Change-Id: I36a018349647125513e47edda66db2005bd8b0c5
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 32 ---
> .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 2 --
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 32 ---
> .../drm/amd/powerplay/sienna_cichlid_ppt.c| 32 ---
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 --
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++
> 6 files changed, 3 insertions(+), 113 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index 209ccf38c020..56dc20a617fd 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -2314,37 +2314,6 @@ static void
> arcturus_log_thermal_throttling_event(struct smu_context *smu)
> log_buf);
> }
>
> -static int arcturus_set_thermal_range(struct smu_context *smu,
> - struct smu_temperature_range range)
> -{
> - struct amdgpu_device *adev = smu->adev;
> - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
> - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
> - uint32_t val;
> - struct smu_table_context *table_context = >smu_table;
> - struct smu_11_0_powerplay_table *powerplay_table =
> table_context->power_play_table;
> -
> - low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
> - range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
> - high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP,
> powerplay_table->software_shutdown_temp);
> -
> - if (low > high)
> - return -EINVAL;
> -
> - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
> - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
> - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
> - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
> - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
> - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high
> & 0xff));
> - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low &
> 0xff));
> - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
> -
> - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
> -
> - return 0;
> -}
> -
> static const struct pptable_funcs arcturus_ppt_funcs = {
> /* translate smu index into arcturus specific index */
> .get_smu_msg_index = arcturus_get_smu_msg_index,
> @@ -2427,7 +2396,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .set_df_cstate = arcturus_set_df_cstate,
> .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
> .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
> - .set_thermal_range = arcturus_set_thermal_range,
> };
>
> void arcturus_set_ppt_funcs(struct smu_context *smu)
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index dede24959652..52e5603dcc97 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -480,7 +480,6 @@ struct pptable_funcs {
> int (*set_cpu_power_state)(struct smu_context *smu);
> bool (*is_dpm_running)(struct smu_context *smu);
> int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
> - int (*set_thermal_fan_table)(struct smu_context *smu);
> int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t
> *speed);
> int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
> int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
> @@ -570,7 +569,6 @@ struct pptable_funcs {
> int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);
> int (*set_power_source)(struct smu_context *smu, enum
> smu_power_src_type power_src);
> void (*log_thermal_throttling_event)(struct smu_context *smu);
> - int (*set_thermal_range)(struct smu_context *smu, struct
> smu_temperature_range range);
> };
>
> typedef enum {
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index a04a0ba632a9..41bd6d157271 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -2340,37 +2340,6 @@ static int
> navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
> return navi10_dummy_pstate_control(smu, true);
> }
>
> -static int navi10_set_thermal_range(struct smu_context *smu,
> - struct smu_temperature_range range)
> -{
> -
Re: [PATCH 2/2] drm/amd/powerplay: correct the supported pcie GenSpeed and LaneCount
On Fri, Jul 3, 2020 at 4:55 AM Evan Quan wrote:
>
> The LCLK dpm table setup should be performed in .update_pcie_parameters().
> Otherwise, the updated GenSpeed and LaneCount information will be lost.
>
> Change-Id: I028c26ca0e54098cb93d9e9266719f1762ba2d7e
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
Thanks,
Alex
> ---
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 17 +++--
> .../gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 17 +++--
> 2 files changed, 14 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 3db5e663aa6f..97d14539c95e 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -693,7 +693,6 @@ static int navi10_set_default_dpm_table(struct
> smu_context *smu)
> PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
> struct smu_11_0_dpm_table *dpm_table;
> int ret = 0;
> - int i;
>
> /* socclk dpm table setup */
> dpm_table = _context->dpm_tables.soc_table;
> @@ -857,12 +856,6 @@ static int navi10_set_default_dpm_table(struct
> smu_context *smu)
> dpm_table->max = dpm_table->dpm_levels[0].value;
> }
>
> - /* lclk dpm table setup */
> - for (i = 0; i < MAX_PCIE_CONF; i++) {
> - dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
> driver_ppt->PcieGenSpeed[i];
> - dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
> driver_ppt->PcieLaneCount[i];
> - }
> -
> return 0;
> }
>
> @@ -1936,12 +1929,16 @@ static int navi10_update_pcie_parameters(struct
> smu_context *smu,
> uint32_t pcie_gen_cap,
> uint32_t pcie_width_cap)
> {
> + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> PPTable_t *pptable = smu->smu_table.driver_pptable;
> - int ret, i;
> uint32_t smu_pcie_arg;
> + int ret, i;
>
> - struct smu_dpm_context *smu_dpm = >smu_dpm;
> - struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
> + /* lclk dpm table setup */
> + for (i = 0; i < MAX_PCIE_CONF; i++) {
> + dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
> pptable->PcieGenSpeed[i];
> + dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
> pptable->PcieLaneCount[i];
> + }
>
> for (i = 0; i < NUM_LINK_LEVELS; i++) {
> smu_pcie_arg = (i << 16) |
> diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> index 7a108676f90a..46be02e4b93c 100644
> --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> @@ -601,7 +601,6 @@ static int sienna_cichlid_set_default_dpm_table(struct
> smu_context *smu)
> PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
> struct smu_11_0_dpm_table *dpm_table;
> int ret = 0;
> - int i;
>
> /* socclk dpm table setup */
> dpm_table = _context->dpm_tables.soc_table;
> @@ -819,12 +818,6 @@ static int sienna_cichlid_set_default_dpm_table(struct
> smu_context *smu)
> dpm_table->max = dpm_table->dpm_levels[0].value;
> }
>
> - /* lclk dpm table setup */
> - for (i = 0; i < MAX_PCIE_CONF; i++) {
> - dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
> driver_ppt->PcieGenSpeed[i];
> - dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
> driver_ppt->PcieLaneCount[i];
> - }
> -
> return 0;
> }
>
> @@ -1722,12 +1715,16 @@ static int
> sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
> uint32_t pcie_gen_cap,
> uint32_t pcie_width_cap)
> {
> + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> PPTable_t *pptable = smu->smu_table.driver_pptable;
> - int ret, i;
> uint32_t smu_pcie_arg;
> + int ret, i;
>
> - struct smu_dpm_context *smu_dpm = >smu_dpm;
> - struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
> + /* lclk dpm table setup */
> + for (i = 0; i < MAX_PCIE_CONF; i++) {
> + dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
> pptable->PcieGenSpeed[i];
> + dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
> pptable->PcieLaneCount[i];
> + }
>
> for (i = 0; i < NUM_LINK_LEVELS; i++) {
> smu_pcie_arg = (i << 16) |
> --
> 2.27.0
>
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Re: [PATCH 14/14] drm/amd/powerplay: drop unused APIs and parameters
On Fri, Jul 3, 2020 at 4:34 AM Evan Quan wrote:
>
> Leftover of previous performance level setting cleanups.
>
> Change-Id: Idddc4adce365b34eacbc13f75cc0629859c6d412
> Signed-off-by: Evan Quan
patches 5-10, 12-14:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 ++--
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++--
> drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 12 +---
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 --
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 5 -
> 5 files changed, 10 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 26c8e39a78bd..c418613699ed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1105,7 +1105,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device
> *dev,
> }
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(>smu, SMU_SCLK, mask, true);
> + ret = smu_force_clk_levels(>smu, SMU_SCLK, mask);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
>
> @@ -1173,7 +1173,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device
> *dev,
> }
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(>smu, SMU_MCLK, mask, true);
> + ret = smu_force_clk_levels(>smu, SMU_MCLK, mask);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
>
> @@ -1241,7 +1241,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device
> *dev,
> }
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(>smu, SMU_SOCCLK, mask,
> true);
> + ret = smu_force_clk_levels(>smu, SMU_SOCCLK, mask);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
> else
> @@ -1311,7 +1311,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device
> *dev,
> }
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(>smu, SMU_FCLK, mask, true);
> + ret = smu_force_clk_levels(>smu, SMU_FCLK, mask);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
> else
> @@ -1381,7 +1381,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device
> *dev,
> }
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(>smu, SMU_DCEFCLK, mask,
> true);
> + ret = smu_force_clk_levels(>smu, SMU_DCEFCLK, mask);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
> else
> @@ -1451,7 +1451,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device
> *dev,
> }
>
> if (is_support_sw_smu(adev))
> - ret = smu_force_clk_levels(>smu, SMU_PCIE, mask, true);
> + ret = smu_force_clk_levels(>smu, SMU_PCIE, mask);
> else if (adev->powerplay.pp_funcs->force_clock_level)
> ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
> else
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 4080b3c792ac..38b3b47d12b7 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1764,8 +1764,7 @@ int smu_set_display_count(struct smu_context *smu,
> uint32_t count)
>
> int smu_force_clk_levels(struct smu_context *smu,
> enum smu_clk_type clk_type,
> -uint32_t mask,
> -bool lock_needed)
> +uint32_t mask)
> {
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> int ret = 0;
> @@ -1778,14 +1777,12 @@ int smu_force_clk_levels(struct smu_context *smu,
> return -EINVAL;
> }
>
> - if (lock_needed)
> - mutex_lock(>mutex);
> + mutex_lock(>mutex);
>
> if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
> ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
>
> - if (lock_needed)
> - mutex_unlock(>mutex);
> + mutex_unlock(>mutex);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 91c8b69da026..470b0377a860 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -476,13 +476,6 @@ struct pptable_funcs {
> int (*display_config_changed)(struct
Re: [PATCH 11/14] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range
On Fri, Jul 3, 2020 at 4:34 AM Evan Quan wrote:
>
> Use the common smu_v11_0_set_soft_freq_limited_range.
>
> Change-Id: I9f8772880b324ce9e741291751bb1b8ff4c36ea3
> Signed-off-by: Evan Quan
> ---
> .../drm/amd/powerplay/sienna_cichlid_ppt.c| 20 ++-
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 1 -
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 20 +++
> 3 files changed, 18 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> index 27f77bde184f..141944df97b0 100644
> --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> @@ -1046,22 +1046,6 @@ static int sienna_cichlid_print_clk_levels(struct
> smu_context *smu,
> return size;
> }
>
> -int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
> - enum smu_clk_type clk_type,
> - uint32_t min, uint32_t max)
> -{
> - struct amdgpu_device *adev = smu->adev;
> - int ret;
> -
> - if (clk_type == SMU_GFXCLK)
> - amdgpu_gfx_off_ctrl(adev, false);
> - ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max);
> - if (clk_type == SMU_GFXCLK)
> - amdgpu_gfx_off_ctrl(adev, true);
> -
> - return ret;
> -}
> -
> static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
>enum smu_clk_type clk_type, uint32_t mask)
> {
> @@ -1097,7 +1081,7 @@ static int sienna_cichlid_force_clk_levels(struct
> smu_context *smu,
> if (ret)
> goto forec_level_out;
>
> - ret = sienna_cichlid_set_soft_freq_limited_range(smu,
> clk_type, min_freq, max_freq);
> + ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type,
> min_freq, max_freq);
> if (ret)
> goto forec_level_out;
> break;
> @@ -2566,7 +2550,7 @@ static const struct pptable_funcs
> sienna_cichlid_ppt_funcs = {
> .baco_enter = smu_v11_0_baco_enter,
> .baco_exit = smu_v11_0_baco_exit,
> .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
> - .set_soft_freq_limited_range =
> sienna_cichlid_set_soft_freq_limited_range,
> + .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
> .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
> .set_thermal_range = sienna_cichlid_set_thermal_range,
> };
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> index 8fbfa0562007..1b357e349d1e 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> @@ -93,7 +93,6 @@
> #define smu_asic_set_performance_level(smu, level)
> smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)
> #define smu_dump_pptable(smu)
> smu_ppt_funcs(dump_pptable, 0, smu)
> #define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq)
> smu_ppt_funcs(get_dpm_clk_limited, -EINVAL, smu, clk_type, dpm_level, freq)
> -#define smu_set_soft_freq_limited_range(smu, clk_type, min, max)
> smu_ppt_funcs(set_soft_freq_limited_range, -EINVAL, smu, clk_type, min, max)
> #define smu_override_pcie_parameters(smu)
> smu_ppt_funcs(override_pcie_parameters, 0, smu)
> #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap)
> smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)
> #define smu_set_thermal_range(smu, range)
> smu_ppt_funcs(set_thermal_range, 0, smu, range)
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index c2564df304f7..1ed5ac946c05 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1745,9 +1745,12 @@ int smu_v11_0_get_dpm_ultimate_freq(struct smu_context
> *smu, enum smu_clk_type c
> return ret;
> }
>
> -int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum
> smu_clk_type clk_type,
> - uint32_t min, uint32_t max)
> +int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
> + enum smu_clk_type clk_type,
> + uint32_t min,
> + uint32_t max)
> {
> + struct amdgpu_device *adev = smu->adev;
> int ret = 0, clk_id = 0;
> uint32_t param;
>
> @@ -1755,12 +1758,16 @@ int smu_v11_0_set_soft_freq_limited_range(struct
> smu_context *smu, enum smu_clk_
> if (clk_id < 0)
> return clk_id;
>
> + if
Re: [PATCH 04/14] drm/amd/powerplay: update Sienna Cichlid default dpm table setup
On Fri, Jul 3, 2020 at 4:33 AM Evan Quan wrote:
>
> Cache all clocks levels for every dpm table. They are needed
> by other APIs.
>
> Change-Id: Idaa853356720e48ab3279f420ba1ae18bb7de4fd
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> .../drm/amd/powerplay/sienna_cichlid_ppt.c| 234 --
> 1 file changed, 211 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> index f2bbe56798d7..d750d06378e9 100644
> --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> @@ -597,41 +597,229 @@ static int sienna_cichlid_allocate_dpm_context(struct
> smu_context *smu)
>
> static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
> {
> - struct smu_dpm_context *smu_dpm = >smu_dpm;
> - struct smu_table_context *table_context = >smu_table;
> - struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
> - PPTable_t *driver_ppt = NULL;
> + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> + PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
> + struct smu_11_0_dpm_table *dpm_table;
> + int ret = 0;
> int i;
>
> -driver_ppt = table_context->driver_pptable;
> + /* socclk dpm table setup */
> + dpm_table = _context->dpm_tables.soc_table;
> + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
> + ret = smu_v11_0_set_single_dpm_table(smu,
> +SMU_SOCCLK,
> +dpm_table);
> + if (ret)
> + return ret;
> + dpm_table->is_fine_grained =
> +
> !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
> + } else {
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value =
> smu->smu_table.boot_values.socclk / 100;
> + dpm_table->dpm_levels[0].enabled = true;
> + dpm_table->min = dpm_table->dpm_levels[0].value;
> + dpm_table->max = dpm_table->dpm_levels[0].value;
> + }
> +
> + /* gfxclk dpm table setup */
> + dpm_table = _context->dpm_tables.gfx_table;
> + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
> + ret = smu_v11_0_set_single_dpm_table(smu,
> +SMU_GFXCLK,
> +dpm_table);
> + if (ret)
> + return ret;
> + dpm_table->is_fine_grained =
> +
> !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
> + } else {
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value =
> smu->smu_table.boot_values.gfxclk / 100;
> + dpm_table->dpm_levels[0].enabled = true;
> + dpm_table->min = dpm_table->dpm_levels[0].value;
> + dpm_table->max = dpm_table->dpm_levels[0].value;
> + }
> +
> + /* uclk dpm table setup */
> + dpm_table = _context->dpm_tables.uclk_table;
> + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
> + ret = smu_v11_0_set_single_dpm_table(smu,
> +SMU_UCLK,
> +dpm_table);
> + if (ret)
> + return ret;
> + dpm_table->is_fine_grained =
> + !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
> + } else {
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value =
> smu->smu_table.boot_values.uclk / 100;
> + dpm_table->dpm_levels[0].enabled = true;
> + dpm_table->min = dpm_table->dpm_levels[0].value;
> + dpm_table->max = dpm_table->dpm_levels[0].value;
> + }
>
> -dpm_context->dpm_tables.soc_table.min =
> driver_ppt->FreqTableSocclk[0];
> -dpm_context->dpm_tables.soc_table.max =
> driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
> + /* fclk dpm table setup */
> + dpm_table = _context->dpm_tables.fclk_table;
> + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
> + ret = smu_v11_0_set_single_dpm_table(smu,
> +SMU_FCLK,
> +dpm_table);
> + if (ret)
> + return ret;
> + dpm_table->is_fine_grained =
> + !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
> + } else {
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value =
>
Re: [PATCH 03/14] drm/amd/powerplay: update Navi10 default dpm table setup
On Fri, Jul 3, 2020 at 4:33 AM Evan Quan wrote:
>
> Cache all clocks levels for every dpm table. They are needed
> by other APIs.
>
> Change-Id: I8114cf31e6ec8c9af4578d51749eb213befdcc71
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 182 ++---
> 1 file changed, 158 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index d96e8334b5e2..a022e93a487c 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -689,41 +689,175 @@ static int navi10_allocate_dpm_context(struct
> smu_context *smu)
>
> static int navi10_set_default_dpm_table(struct smu_context *smu)
> {
> - struct smu_dpm_context *smu_dpm = >smu_dpm;
> - struct smu_table_context *table_context = >smu_table;
> - struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
> - PPTable_t *driver_ppt = NULL;
> + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> + PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
> + struct smu_11_0_dpm_table *dpm_table;
> + int ret = 0;
> int i;
>
> - driver_ppt = table_context->driver_pptable;
> -
> - dpm_context->dpm_tables.soc_table.min =
> driver_ppt->FreqTableSocclk[0];
> - dpm_context->dpm_tables.soc_table.max =
> driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
> + /* socclk dpm table setup */
> + dpm_table = _context->dpm_tables.soc_table;
> + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
> + ret = smu_v11_0_set_single_dpm_table(smu,
> +SMU_SOCCLK,
> +dpm_table);
> + if (ret)
> + return ret;
> + dpm_table->is_fine_grained =
> +
> !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
> + } else {
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value =
> smu->smu_table.boot_values.socclk / 100;
> + dpm_table->dpm_levels[0].enabled = true;
> + dpm_table->min = dpm_table->dpm_levels[0].value;
> + dpm_table->max = dpm_table->dpm_levels[0].value;
> + }
>
> - dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
> - dpm_context->dpm_tables.gfx_table.max =
> driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
> + /* gfxclk dpm table setup */
> + dpm_table = _context->dpm_tables.gfx_table;
> + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
> + ret = smu_v11_0_set_single_dpm_table(smu,
> +SMU_GFXCLK,
> +dpm_table);
> + if (ret)
> + return ret;
> + dpm_table->is_fine_grained =
> +
> !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
> + } else {
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value =
> smu->smu_table.boot_values.gfxclk / 100;
> + dpm_table->dpm_levels[0].enabled = true;
> + dpm_table->min = dpm_table->dpm_levels[0].value;
> + dpm_table->max = dpm_table->dpm_levels[0].value;
> + }
>
> - dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
> - dpm_context->dpm_tables.uclk_table.max =
> driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
> + /* uclk dpm table setup */
> + dpm_table = _context->dpm_tables.uclk_table;
> + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
> + ret = smu_v11_0_set_single_dpm_table(smu,
> +SMU_UCLK,
> +dpm_table);
> + if (ret)
> + return ret;
> + dpm_table->is_fine_grained =
> + !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
> + } else {
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value =
> smu->smu_table.boot_values.uclk / 100;
> + dpm_table->dpm_levels[0].enabled = true;
> + dpm_table->min = dpm_table->dpm_levels[0].value;
> + dpm_table->max = dpm_table->dpm_levels[0].value;
> + }
>
> - dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
> - dpm_context->dpm_tables.vclk_table.max =
> driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
> + /* vclk dpm table setup */
> + dpm_table = _context->dpm_tables.vclk_table;
> + if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
> +
Re: [PATCH 01/14] drm/amd/powerplay: add more members for dpm table
On Fri, Jul 3, 2020 at 4:33 AM Evan Quan wrote:
>
> These members can help to cache the clock frequencies for all
> dpm levels. Then simplifying the code for dpm level switching
> is possible.
>
> Change-Id: Ic80359adb8c0e018f306782f24e3f8906436f5e2
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> index 3d746b75396e..289c571d6e4e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> @@ -48,6 +48,7 @@
>
> #define SMU11_TOOL_SIZE0x19000
>
> +#define MAX_DPM_LEVELS 16
> #define MAX_PCIE_CONF 2
>
> #define CLK_MAP(clk, index) \
> @@ -91,9 +92,17 @@ struct smu_11_0_max_sustainable_clocks {
> uint32_t soc_clock;
> };
>
> +struct smu_11_0_dpm_clk_level {
> + boolenabled;
> + uint32_tvalue;
> +};
> +
> struct smu_11_0_dpm_table {
> - uint32_tmin;/* MHz */
> - uint32_tmax;/* MHz */
> + uint32_tmin;/* MHz */
> + uint32_tmax;/* MHz */
> + uint32_tcount;
> + boolis_fine_grained;
> + struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
> };
>
> struct smu_11_0_pcie_table {
> @@ -107,7 +116,9 @@ struct smu_11_0_dpm_tables {
> struct smu_11_0_dpm_tableuclk_table;
> struct smu_11_0_dpm_tableeclk_table;
> struct smu_11_0_dpm_tablevclk_table;
> + struct smu_11_0_dpm_tablevclk1_table;
> struct smu_11_0_dpm_tabledclk_table;
> + struct smu_11_0_dpm_tabledclk1_table;
> struct smu_11_0_dpm_tabledcef_table;
> struct smu_11_0_dpm_tablepixel_table;
> struct smu_11_0_dpm_tabledisplay_table;
> --
> 2.27.0
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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amd-gfx@lists.freedesktop.org
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Re: [PATCH 02/14] drm/amd/powerplay: update Arcturus default dpm table setting
On Fri, Jul 3, 2020 at 4:33 AM Evan Quan wrote:
>
> Preparing for coming code sharing around performance level
> setting.
>
> Change-Id: Ie32b6af39f22d05c08096959bab0e02e53856170
> Signed-off-by: Evan Quan
You might want to split this into two patches, one to split out the
smu_v11_0_set_single_dpm_table into the common smu11 code, and then
the rest as separate patch. That will make it the arcturus patch
cleaner and more like the patches for other asics.
Alex.
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 297 +++---
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 +
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 38 +++
> 3 files changed, 161 insertions(+), 178 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index 5b793e354704..a3747ab4af32 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -291,7 +291,6 @@ static int arcturus_get_pwr_src_index(struct smu_context
> *smc, uint32_t index)
> return mapping.map_to;
> }
>
> -
> static int arcturus_get_workload_type(struct smu_context *smu, enum
> PP_SMC_POWER_PROFILE profile)
> {
> struct smu_11_0_cmn2aisc_mapping mapping;
> @@ -338,23 +337,11 @@ static int arcturus_allocate_dpm_context(struct
> smu_context *smu)
> {
> struct smu_dpm_context *smu_dpm = >smu_dpm;
>
> - if (smu_dpm->dpm_context)
> - return -EINVAL;
> -
> - smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
> + smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
>GFP_KERNEL);
> if (!smu_dpm->dpm_context)
> return -ENOMEM;
> -
> - if (smu_dpm->golden_dpm_context)
> - return -EINVAL;
> -
> - smu_dpm->golden_dpm_context = kzalloc(sizeof(struct
> arcturus_dpm_table),
> - GFP_KERNEL);
> - if (!smu_dpm->golden_dpm_context)
> - return -ENOMEM;
> -
> - smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
> + smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
>
> smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct
> smu_power_state),
>GFP_KERNEL);
> @@ -382,119 +369,84 @@ arcturus_get_allowed_feature_mask(struct smu_context
> *smu,
> return 0;
> }
>
> -static int
> -arcturus_set_single_dpm_table(struct smu_context *smu,
> - struct arcturus_single_dpm_table
> *single_dpm_table,
> - PPCLK_e clk_id)
> -{
> - int ret = 0;
> - uint32_t i, num_of_levels = 0, clk;
> -
> - ret = smu_send_smc_msg_with_param(smu,
> - SMU_MSG_GetDpmFreqByIndex,
> - (clk_id << 16 | 0xFF),
> - _of_levels);
> - if (ret) {
> - dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n",
> __func__);
> - return ret;
> - }
> -
> - single_dpm_table->count = num_of_levels;
> - for (i = 0; i < num_of_levels; i++) {
> - ret = smu_send_smc_msg_with_param(smu,
> - SMU_MSG_GetDpmFreqByIndex,
> - (clk_id << 16 | i),
> - );
> - if (ret) {
> - dev_err(smu->adev->dev, "[%s] failed to get dpm freq
> by index!\n", __func__);
> - return ret;
> - }
> - single_dpm_table->dpm_levels[i].value = clk;
> - single_dpm_table->dpm_levels[i].enabled = true;
> - }
> - return 0;
> -}
> -
> -static void arcturus_init_single_dpm_state(struct arcturus_dpm_state
> *dpm_state)
> -{
> - dpm_state->soft_min_level = 0x0;
> - dpm_state->soft_max_level = 0x;
> -dpm_state->hard_min_level = 0x0;
> -dpm_state->hard_max_level = 0x;
> -}
> -
> static int arcturus_set_default_dpm_table(struct smu_context *smu)
> {
> - int ret;
> -
> - struct smu_dpm_context *smu_dpm = >smu_dpm;
> - struct arcturus_dpm_table *dpm_table = NULL;
> - struct arcturus_single_dpm_table *single_dpm_table;
> -
> - dpm_table = smu_dpm->dpm_context;
> + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> + PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
> + struct smu_11_0_dpm_table *dpm_table = NULL;
> + int ret = 0;
>
> - /* socclk */
> - single_dpm_table = &(dpm_table->soc_table);
> + /* socclk dpm table setup */
> + dpm_table = _context->dpm_tables.soc_table;
> if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
> - ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
> -
Re: [PATCH] drm/amd/powerplay: correct the .get_workload_type() pointer
On Fri, Jul 3, 2020 at 4:54 AM Evan Quan wrote: > > This seemed a typo. > > Change-Id: I1e4da590829395617e90d0d43562f934a1ae0234 > Signed-off-by: Evan Quan Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h > b/drivers/gpu/drm/amd/powerplay/smu_internal.h > index 8c5cf3860e38..afb3ef874fc5 100644 > --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h > +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h > @@ -73,7 +73,7 @@ > #define smu_feature_get_index(smu, fea) > smu_ppt_funcs(get_smu_feature_index, -EINVAL, smu, fea) > #define smu_table_get_index(smu, tab) > smu_ppt_funcs(get_smu_table_index, -EINVAL, smu, tab) > #define smu_power_get_index(smu, src) > smu_ppt_funcs(get_smu_power_index, -EINVAL, smu, src) > -#define smu_workload_get_type(smu, type) > smu_ppt_funcs(get_smu_power_index, -EINVAL, smu, type) > +#define smu_workload_get_type(smu, type) > smu_ppt_funcs(get_workload_type, -EINVAL, smu, type) > #define smu_run_btc(smu) > smu_ppt_funcs(run_btc, 0, smu) > #define smu_get_allowed_feature_mask(smu, feature_mask, num) > smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num) > #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) > smu_ppt_funcs(store_cc6_data, 0, smu, st, cc6_dis, pst_dis, pst_sw_dis) > -- > 2.27.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 4/4] drm/amd/powerplay: put dpm frequency setting common code in smu_v11_0.c
On Thu, Jul 2, 2020 at 5:47 AM Evan Quan wrote:
>
> As designed the common code shared among all smu v11 ASCIs go to
> smu_v11_0.c. This helps to maintain clear code layers.
>
> Change-Id: I1f848eba0b6b56f8b5ef6f0888ee6955ba1d2070
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 65 --
> .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 6 --
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 14
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 38 +
> .../drm/amd/powerplay/sienna_cichlid_ppt.c| 18 ++--
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 84 +++
> 6 files changed, 129 insertions(+), 96 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 95685bb9582a..6839faaab611 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -284,71 +284,6 @@ int smu_get_dpm_freq_range(struct smu_context *smu,
> return ret;
> }
>
> -int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type
> clk_type,
> - uint16_t level, uint32_t *value)
> -{
> - int ret = 0, clk_id = 0;
> - uint32_t param;
> -
> - if (!value)
> - return -EINVAL;
> -
> - if (!smu_clk_dpm_is_enabled(smu, clk_type))
> - return 0;
> -
> - clk_id = smu_clk_get_index(smu, clk_type);
> - if (clk_id < 0)
> - return clk_id;
> -
> - param = (uint32_t)(((clk_id & 0x) << 16) | (level & 0x));
> -
> - ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmFreqByIndex,
> - param, value);
> - if (ret)
> - return ret;
> -
> - /* BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
> -* now, we un-support it */
> - *value = *value & 0x7fff;
> -
> - return ret;
> -}
> -
> -int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type
> clk_type,
> - uint32_t *value)
> -{
> - return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
> -}
> -
> -int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type
> clk_type,
> - uint32_t *min_value, uint32_t *max_value)
> -{
> - int ret = 0;
> - uint32_t level_count = 0;
> -
> - if (!min_value && !max_value)
> - return -EINVAL;
> -
> - if (min_value) {
> - /* by default, level 0 clock value as min value */
> - ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, min_value);
> - if (ret)
> - return ret;
> - }
> -
> - if (max_value) {
> - ret = smu_get_dpm_level_count(smu, clk_type, _count);
> - if (ret)
> - return ret;
> -
> - ret = smu_get_dpm_freq_by_index(smu, clk_type, level_count -
> 1, max_value);
> - if (ret)
> - return ret;
> - }
> -
> - return ret;
> -}
> -
> bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type
> clk_type)
> {
> enum smu_feature_mask feature_id = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index ae16cc4c2b2d..66912884f093 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -715,16 +715,10 @@ int smu_switch_power_profile(struct smu_context *smu,
> enum PP_SMC_POWER_PROFILE type,
> bool en);
> int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version,
> uint32_t *smu_version);
> -int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type
> clk_type,
> - uint16_t level, uint32_t *value);
> -int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type
> clk_type,
> - uint32_t *value);
> int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type
> clk_type,
>uint32_t *min, uint32_t *max);
> int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type
> clk_type,
> uint32_t min, uint32_t max);
> -int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type
> clk_type,
> - uint32_t *min_value, uint32_t *max_value);
> enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
> int smu_force_performance_level(struct smu_context *smu, enum
> amd_dpm_forced_level level);
> int smu_set_display_count(struct smu_context *smu, uint32_t count);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> index
Re: [PATCH 4/4] drm/amd/powerplay: drop unused code and wrapper around clock retrieving
On Thu, Jul 2, 2020 at 5:45 AM Evan Quan wrote:
>
> Clean code by dropping unnecessary ones.
>
> Change-Id: Idf89ef6fa787b61cd8baf8ded7e3f323bdcef189
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 8 +++-
> .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 --
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 +---
> drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 8
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 8 +++-
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 4 +-
> .../drm/amd/powerplay/sienna_cichlid_ppt.c| 8 +++-
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 1 -
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 47 +--
> drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 41
> 10 files changed, 22 insertions(+), 114 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index 2e04ac1d8ff9..5b793e354704 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -1212,8 +1212,13 @@ static int arcturus_read_sensor(struct smu_context
> *smu,
> *(uint32_t *)data *= 100;
> *size = 4;
> break;
> + case AMDGPU_PP_SENSOR_VDDGFX:
> + ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
> + *size = 4;
> + break;
> default:
> - ret = smu_v11_0_read_sensor(smu, sensor, data, size);
> + ret = -EOPNOTSUPP;
> + break;
> }
> mutex_unlock(>sensor_lock);
>
> @@ -2566,7 +2571,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .set_default_dpm_table = arcturus_set_default_dpm_table,
> .populate_umd_state_clk = arcturus_populate_umd_state_clk,
> .get_thermal_temperature_range =
> arcturus_get_thermal_temperature_range,
> - .get_current_clk_freq_by_table =
> arcturus_get_current_clk_freq_by_table,
> .print_clk_levels = arcturus_print_clk_levels,
> .force_clk_levels = arcturus_force_clk_levels,
> .read_sensor = arcturus_read_sensor,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index f3bc1f16b0a4..43b4a31b0ffd 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -476,9 +476,6 @@ struct pptable_funcs {
> int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
> int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
> struct
> dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
> - int (*get_current_clk_freq_by_table)(struct smu_context *smu,
> -enum smu_clk_type clk_type,
> -uint32_t *value);
> int (*get_thermal_temperature_range)(struct smu_context *smu, struct
> smu_temperature_range *range);
> int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t
> *clocks_in_khz, uint32_t *num_states);
> int (*set_default_od_settings)(struct smu_context *smu);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> index d07bf4fe6e4a..f2f0b738fb4c 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> @@ -197,19 +197,13 @@ int smu_v11_0_get_current_power_limit(struct
> smu_context *smu,
>
> int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
>
> -int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
> - enum smu_clk_type clk_id,
> - uint32_t *value);
> -
> int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
>
> int smu_v11_0_enable_thermal_alert(struct smu_context *smu);
>
> int smu_v11_0_disable_thermal_alert(struct smu_context *smu);
>
> -int smu_v11_0_read_sensor(struct smu_context *smu,
> -enum amd_pp_sensors sensor,
> -void *data, uint32_t *size);
> +int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
>
> int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t
> clk);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> index d29f75223987..0c1e1455c68f 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> @@ -60,10 +60,6 @@ int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool
> gate);
>
> int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
>
> -int smu_v12_0_read_sensor(struct smu_context *smu,
> -
[PATCH] drm/amdgpu: minor cleanup of phase1 suspend code
Cleanup of phase1 suspend code to reduce unnecessary indentation.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 --
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2913e41f63a5..81ca92127c00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2456,18 +2456,21 @@ static int amdgpu_device_ip_suspend_phase1(struct
amdgpu_device *adev)
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.valid)
continue;
+
/* displays are handled separately */
- if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
- /* XXX handle errors */
- r = adev->ip_blocks[i].version->funcs->suspend(adev);
- /* XXX handle errors */
- if (r) {
- DRM_ERROR("suspend of IP block <%s> failed
%d\n",
-
adev->ip_blocks[i].version->funcs->name, r);
- return r;
- }
- adev->ip_blocks[i].status.hw = false;
+ if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
+ continue;
+
+ /* XXX handle errors */
+ r = adev->ip_blocks[i].version->funcs->suspend(adev);
+ /* XXX handle errors */
+ if (r) {
+ DRM_ERROR("suspend of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+ return r;
}
+
+ adev->ip_blocks[i].status.hw = false;
}
return 0;
--
2.27.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[pull] amdgpu and radeon drm-fixes-5.8
Hi Dave, Daniel, Fixes for 5.8. The following changes since commit dcb7fd82c75ee2d6e6f9d8cc71c52519ed52e258: Linux 5.8-rc4 (2020-07-05 16:20:22 -0700) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux tags/amd-drm-fixes-5.8-2020-07-09 for you to fetch changes up to f4892c327a8e5df7ce16cab40897daf90baf6bec: drm/amdgpu: don't do soft recovery if gpu_recovery=0 (2020-07-09 14:42:49 -0400) amd-drm-fixes-5.8-2020-07-09: amdgpu: - Fix a suspend/resume issue with PSP - Backlight fix for Renoir - Fix for gpu recovery debugging radeon: - Fix a double free in error path Aaron Ma (1): drm/amd/display: add dmcub check on RENOIR Huang Rui (2): drm/amdgpu: asd function needs to be unloaded in suspend phase drm/amdgpu: add TMR destory function for psp Marek Olšák (1): drm/amdgpu: don't do soft recovery if gpu_recovery=0 Tom Rix (1): drm/radeon: fix double free drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 63 +-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/radeon/ci_dpm.c | 7 ++- 4 files changed, 65 insertions(+), 10 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 2/2] drm/amdgpu: stop allocating dummy GTT nodes v2
[AMD Public Use]
-Original Message-
From: Christian König
Sent: Thursday, July 9, 2020 8:40 PM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Chauhan, Madhav
Subject: [PATCH 2/2] drm/amdgpu: stop allocating dummy GTT nodes v2
Now that TTM is fixed up we can finally stop that nonsense.
v2: Update the documentation as well.
LGTM, Reviewed-by: Madhav Chauhan
Regards,
Madhav
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 106 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 +++-
2 files changed, 43 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 2c20d23d62d1..0c44352ad5eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -150,60 +150,7 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager
*man)
*/
bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem) {
- struct amdgpu_gtt_node *node = mem->mm_node;
-
- return (node->node.start != AMDGPU_BO_INVALID_OFFSET);
-}
-
-/**
- * amdgpu_gtt_mgr_alloc - allocate new ranges
- *
- * @man: TTM memory type manager
- * @tbo: TTM BO we need this range for
- * @place: placement flags and restrictions
- * @mem: the resulting mem object
- *
- * Allocate the address space for a node.
- */
-static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
- struct ttm_buffer_object *tbo,
- const struct ttm_place *place,
- struct ttm_mem_reg *mem)
-{
- struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
- struct amdgpu_gtt_mgr *mgr = man->priv;
- struct amdgpu_gtt_node *node = mem->mm_node;
- enum drm_mm_insert_mode mode;
- unsigned long fpfn, lpfn;
- int r;
-
- if (amdgpu_gtt_mgr_has_gart_addr(mem))
- return 0;
-
- if (place)
- fpfn = place->fpfn;
- else
- fpfn = 0;
-
- if (place && place->lpfn)
- lpfn = place->lpfn;
- else
- lpfn = adev->gart.num_cpu_pages;
-
- mode = DRM_MM_INSERT_BEST;
- if (place && place->flags & TTM_PL_FLAG_TOPDOWN)
- mode = DRM_MM_INSERT_HIGH;
-
- spin_lock(>lock);
- r = drm_mm_insert_node_in_range(>mm, >node, mem->num_pages,
- mem->page_alignment, 0, fpfn, lpfn,
- mode);
- spin_unlock(>lock);
-
- if (!r)
- mem->start = node->node.start;
-
- return r;
+ return mem->mm_node != NULL;
}
/**
@@ -214,7 +161,7 @@ static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager
*man,
* @place: placement flags and restrictions
* @mem: the resulting mem object
*
- * Dummy, allocate the node but no space for it yet.
+ * GTT accounting and GART node allocation if necessary.
*/
static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man,
struct ttm_buffer_object *tbo, @@ -234,29 +181,37
@@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man,
atomic64_sub(mem->num_pages, >available);
spin_unlock(>lock);
+ if (!place->lpfn) {
+ mem->mm_node = NULL;
+ mem->start = AMDGPU_BO_INVALID_OFFSET;
+ return 0;
+ }
+
node = kzalloc(sizeof(*node), GFP_KERNEL);
if (!node) {
r = -ENOMEM;
goto err_out;
}
- node->node.start = AMDGPU_BO_INVALID_OFFSET;
- node->node.size = mem->num_pages;
node->tbo = tbo;
- mem->mm_node = node;
- if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) {
- r = amdgpu_gtt_mgr_alloc(man, tbo, place, mem);
- if (unlikely(r)) {
- kfree(node);
- mem->mm_node = NULL;
- goto err_out;
- }
- } else {
- mem->start = node->node.start;
- }
+ spin_lock(>lock);
+ r = drm_mm_insert_node_in_range(>mm, >node, mem->num_pages,
+ mem->page_alignment, 0, place->fpfn,
+ place->lpfn, DRM_MM_INSERT_BEST);
+ spin_unlock(>lock);
+
+ if (unlikely(r))
+ goto err_free;
+
+ mem->mm_node = node;
+ mem->start = node->node.start;
return 0;
+
+err_free:
+ kfree(node);
+
err_out:
atomic64_add(mem->num_pages, >available);
@@ -279,17 +234,14 @@ static void amdgpu_gtt_mgr_del(struct
ttm_mem_type_manager *man,
struct amdgpu_gtt_mgr *mgr = man->priv;
struct amdgpu_gtt_node *node = mem->mm_node;
- if (!node)
- return;
-
- spin_lock(>lock);
- if (node->node.start !=
RE: [PATCH 1/2] drm/ttm: further cleanup ttm_mem_reg handling
[AMD Public Use]
-Original Message-
From: Christian König
Sent: Thursday, July 9, 2020 8:40 PM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Chauhan, Madhav
Subject: [PATCH 1/2] drm/ttm: further cleanup ttm_mem_reg handling
Stop touching the backend private pointer alltogether and make sure we never
put the same mem twice by.
Signed-off-by: Christian König
Thanks for clarification earlier, Looks fine to me.
Reviewed-by: Madhav Chauhan
---
drivers/gpu/drm/ttm/ttm_bo.c| 46 +++--
include/drm/ttm/ttm_bo_driver.h | 2 --
2 files changed, 26 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index
0c13fe96c7e3..7be36b9996ed 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -312,7 +312,6 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object
*bo,
if (bdev->driver->move_notify)
bdev->driver->move_notify(bo, evict, mem);
bo->mem = *mem;
- mem->mm_node = NULL;
goto moved;
}
}
@@ -616,7 +615,6 @@ static void ttm_bo_release(struct kref *kref)
ttm_bo_cleanup_memtype_use(bo);
dma_resv_unlock(bo->base.resv);
- BUG_ON(bo->mem.mm_node != NULL);
atomic_dec(_bo_glob.bo_count);
dma_fence_put(bo->moving);
if (!ttm_bo_uses_embedded_gem_object(bo))
@@ -843,12 +841,29 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
return ret;
}
+static int ttm_bo_mem_get(struct ttm_buffer_object *bo,
+ const struct ttm_place *place,
+ struct ttm_mem_reg *mem)
+{
+ struct ttm_mem_type_manager *man = >bdev->man[mem->mem_type];
+
+ mem->mm_node = NULL;
+ if (!man->func || !man->func->get_node)
+ return 0;
+
+ return man->func->get_node(man, bo, place, mem); }
+
void ttm_bo_mem_put(struct ttm_buffer_object *bo, struct ttm_mem_reg *mem) {
struct ttm_mem_type_manager *man = >bdev->man[mem->mem_type];
- if (mem->mm_node)
- (*man->func->put_node)(man, mem);
+ if (!man->func || !man->func->put_node)
+ return;
+
+ man->func->put_node(man, mem);
+ mem->mm_node = NULL;
+ mem->mem_type = TTM_PL_SYSTEM;
}
EXPORT_SYMBOL(ttm_bo_mem_put);
@@ -902,7 +917,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object
*bo,
ticket = dma_resv_locking_ctx(bo->base.resv);
do {
- ret = (*man->func->get_node)(man, bo, place, mem);
+ ret = ttm_bo_mem_get(bo, place, mem);
if (likely(!ret))
break;
if (unlikely(ret != -ENOSPC))
@@ -1032,7 +1047,6 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
if (unlikely(ret))
return ret;
- mem->mm_node = NULL;
for (i = 0; i < placement->num_placement; ++i) {
const struct ttm_place *place = >placement[i];
struct ttm_mem_type_manager *man;
@@ -1044,20 +1058,16 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
goto error;
type_found = true;
- mem->mm_node = NULL;
- if (mem->mem_type == TTM_PL_SYSTEM)
- return 0;
-
- man = >man[mem->mem_type];
- ret = (*man->func->get_node)(man, bo, place, mem);
+ ret = ttm_bo_mem_get(bo, place, mem);
if (ret == -ENOSPC)
continue;
if (unlikely(ret))
goto error;
+ man = >man[mem->mem_type];
ret = ttm_bo_add_move_fence(bo, man, mem, ctx->no_wait_gpu);
if (unlikely(ret)) {
- (*man->func->put_node)(man, mem);
+ ttm_bo_mem_put(bo, mem);
if (ret == -EBUSY)
continue;
@@ -1076,12 +1086,8 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
goto error;
type_found = true;
- mem->mm_node = NULL;
- if (mem->mem_type == TTM_PL_SYSTEM)
- return 0;
-
ret = ttm_bo_mem_force_space(bo, place, mem, ctx);
- if (ret == 0 && mem->mm_node)
+ if (likely(!ret))
return 0;
if (ret && ret != -EBUSY)
@@ -1129,7 +1135,7 @@ static int ttm_bo_move_buffer(struct ttm_buffer_object
*bo,
goto out_unlock;
ret = ttm_bo_handle_move_mem(bo, , false, ctx);
out_unlock:
- if (ret && mem.mm_node)
+ if (ret)
ttm_bo_mem_put(bo, );
return ret;
}
@@ -1144,7 +1150,7 @@ static bool ttm_bo_places_compat(const struct ttm_place
*places,
[PATCH 2/2] drm/amdgpu: stop allocating dummy GTT nodes v2
Now that TTM is fixed up we can finally stop that nonsense.
v2: Update the documentation as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 106 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 +++-
2 files changed, 43 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 2c20d23d62d1..0c44352ad5eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -150,60 +150,7 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager
*man)
*/
bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem)
{
- struct amdgpu_gtt_node *node = mem->mm_node;
-
- return (node->node.start != AMDGPU_BO_INVALID_OFFSET);
-}
-
-/**
- * amdgpu_gtt_mgr_alloc - allocate new ranges
- *
- * @man: TTM memory type manager
- * @tbo: TTM BO we need this range for
- * @place: placement flags and restrictions
- * @mem: the resulting mem object
- *
- * Allocate the address space for a node.
- */
-static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
- struct ttm_buffer_object *tbo,
- const struct ttm_place *place,
- struct ttm_mem_reg *mem)
-{
- struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
- struct amdgpu_gtt_mgr *mgr = man->priv;
- struct amdgpu_gtt_node *node = mem->mm_node;
- enum drm_mm_insert_mode mode;
- unsigned long fpfn, lpfn;
- int r;
-
- if (amdgpu_gtt_mgr_has_gart_addr(mem))
- return 0;
-
- if (place)
- fpfn = place->fpfn;
- else
- fpfn = 0;
-
- if (place && place->lpfn)
- lpfn = place->lpfn;
- else
- lpfn = adev->gart.num_cpu_pages;
-
- mode = DRM_MM_INSERT_BEST;
- if (place && place->flags & TTM_PL_FLAG_TOPDOWN)
- mode = DRM_MM_INSERT_HIGH;
-
- spin_lock(>lock);
- r = drm_mm_insert_node_in_range(>mm, >node, mem->num_pages,
- mem->page_alignment, 0, fpfn, lpfn,
- mode);
- spin_unlock(>lock);
-
- if (!r)
- mem->start = node->node.start;
-
- return r;
+ return mem->mm_node != NULL;
}
/**
@@ -214,7 +161,7 @@ static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager
*man,
* @place: placement flags and restrictions
* @mem: the resulting mem object
*
- * Dummy, allocate the node but no space for it yet.
+ * GTT accounting and GART node allocation if necessary.
*/
static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man,
struct ttm_buffer_object *tbo,
@@ -234,29 +181,37 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager
*man,
atomic64_sub(mem->num_pages, >available);
spin_unlock(>lock);
+ if (!place->lpfn) {
+ mem->mm_node = NULL;
+ mem->start = AMDGPU_BO_INVALID_OFFSET;
+ return 0;
+ }
+
node = kzalloc(sizeof(*node), GFP_KERNEL);
if (!node) {
r = -ENOMEM;
goto err_out;
}
- node->node.start = AMDGPU_BO_INVALID_OFFSET;
- node->node.size = mem->num_pages;
node->tbo = tbo;
- mem->mm_node = node;
- if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) {
- r = amdgpu_gtt_mgr_alloc(man, tbo, place, mem);
- if (unlikely(r)) {
- kfree(node);
- mem->mm_node = NULL;
- goto err_out;
- }
- } else {
- mem->start = node->node.start;
- }
+ spin_lock(>lock);
+ r = drm_mm_insert_node_in_range(>mm, >node, mem->num_pages,
+ mem->page_alignment, 0, place->fpfn,
+ place->lpfn, DRM_MM_INSERT_BEST);
+ spin_unlock(>lock);
+
+ if (unlikely(r))
+ goto err_free;
+
+ mem->mm_node = node;
+ mem->start = node->node.start;
return 0;
+
+err_free:
+ kfree(node);
+
err_out:
atomic64_add(mem->num_pages, >available);
@@ -279,17 +234,14 @@ static void amdgpu_gtt_mgr_del(struct
ttm_mem_type_manager *man,
struct amdgpu_gtt_mgr *mgr = man->priv;
struct amdgpu_gtt_node *node = mem->mm_node;
- if (!node)
- return;
-
- spin_lock(>lock);
- if (node->node.start != AMDGPU_BO_INVALID_OFFSET)
+ if (node) {
+ spin_lock(>lock);
drm_mm_remove_node(>node);
- spin_unlock(>lock);
- atomic64_add(mem->num_pages, >available);
+ spin_unlock(>lock);
+ kfree(node);
+ }
- kfree(node);
- mem->mm_node = NULL;
+
[PATCH 1/2] drm/ttm: further cleanup ttm_mem_reg handling
Stop touching the backend private pointer alltogether and
make sure we never put the same mem twice by.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c| 46 +++--
include/drm/ttm/ttm_bo_driver.h | 2 --
2 files changed, 26 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 0c13fe96c7e3..7be36b9996ed 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -312,7 +312,6 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object
*bo,
if (bdev->driver->move_notify)
bdev->driver->move_notify(bo, evict, mem);
bo->mem = *mem;
- mem->mm_node = NULL;
goto moved;
}
}
@@ -616,7 +615,6 @@ static void ttm_bo_release(struct kref *kref)
ttm_bo_cleanup_memtype_use(bo);
dma_resv_unlock(bo->base.resv);
- BUG_ON(bo->mem.mm_node != NULL);
atomic_dec(_bo_glob.bo_count);
dma_fence_put(bo->moving);
if (!ttm_bo_uses_embedded_gem_object(bo))
@@ -843,12 +841,29 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
return ret;
}
+static int ttm_bo_mem_get(struct ttm_buffer_object *bo,
+ const struct ttm_place *place,
+ struct ttm_mem_reg *mem)
+{
+ struct ttm_mem_type_manager *man = >bdev->man[mem->mem_type];
+
+ mem->mm_node = NULL;
+ if (!man->func || !man->func->get_node)
+ return 0;
+
+ return man->func->get_node(man, bo, place, mem);
+}
+
void ttm_bo_mem_put(struct ttm_buffer_object *bo, struct ttm_mem_reg *mem)
{
struct ttm_mem_type_manager *man = >bdev->man[mem->mem_type];
- if (mem->mm_node)
- (*man->func->put_node)(man, mem);
+ if (!man->func || !man->func->put_node)
+ return;
+
+ man->func->put_node(man, mem);
+ mem->mm_node = NULL;
+ mem->mem_type = TTM_PL_SYSTEM;
}
EXPORT_SYMBOL(ttm_bo_mem_put);
@@ -902,7 +917,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object
*bo,
ticket = dma_resv_locking_ctx(bo->base.resv);
do {
- ret = (*man->func->get_node)(man, bo, place, mem);
+ ret = ttm_bo_mem_get(bo, place, mem);
if (likely(!ret))
break;
if (unlikely(ret != -ENOSPC))
@@ -1032,7 +1047,6 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
if (unlikely(ret))
return ret;
- mem->mm_node = NULL;
for (i = 0; i < placement->num_placement; ++i) {
const struct ttm_place *place = >placement[i];
struct ttm_mem_type_manager *man;
@@ -1044,20 +1058,16 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
goto error;
type_found = true;
- mem->mm_node = NULL;
- if (mem->mem_type == TTM_PL_SYSTEM)
- return 0;
-
- man = >man[mem->mem_type];
- ret = (*man->func->get_node)(man, bo, place, mem);
+ ret = ttm_bo_mem_get(bo, place, mem);
if (ret == -ENOSPC)
continue;
if (unlikely(ret))
goto error;
+ man = >man[mem->mem_type];
ret = ttm_bo_add_move_fence(bo, man, mem, ctx->no_wait_gpu);
if (unlikely(ret)) {
- (*man->func->put_node)(man, mem);
+ ttm_bo_mem_put(bo, mem);
if (ret == -EBUSY)
continue;
@@ -1076,12 +1086,8 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
goto error;
type_found = true;
- mem->mm_node = NULL;
- if (mem->mem_type == TTM_PL_SYSTEM)
- return 0;
-
ret = ttm_bo_mem_force_space(bo, place, mem, ctx);
- if (ret == 0 && mem->mm_node)
+ if (likely(!ret))
return 0;
if (ret && ret != -EBUSY)
@@ -1129,7 +1135,7 @@ static int ttm_bo_move_buffer(struct ttm_buffer_object
*bo,
goto out_unlock;
ret = ttm_bo_handle_move_mem(bo, , false, ctx);
out_unlock:
- if (ret && mem.mm_node)
+ if (ret)
ttm_bo_mem_put(bo, );
return ret;
}
@@ -1144,7 +1150,7 @@ static bool ttm_bo_places_compat(const struct ttm_place
*places,
for (i = 0; i < num_placement; i++) {
const struct ttm_place *heap = [i];
- if (mem->mm_node && (mem->start < heap->fpfn ||
+ if ((mem->start < heap->fpfn ||
(heap->lpfn != 0 && (mem->start + mem->num_pages) >
heap->lpfn)))
continue;
diff --git
Re: [Intel-gfx] [PATCH 03/25] dma-buf.rst: Document why idenfinite fences are a bad idea
Am 09.07.20 um 14:31 schrieb Daniel Vetter: On Thu, Jul 9, 2020 at 2:11 PM Daniel Stone wrote: On Thu, 9 Jul 2020 at 09:05, Daniel Vetter wrote: On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote: On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote: Comes up every few years, gets somewhat tedious to discuss, let's write this down once and for all. Thanks for writing this up! I wonder if any of the notes from my reply to the previous-version thread would be helpful to more explicitly encode the carrot of dma-fence's positive guarantees, rather than just the stick of 'don't do this'. ;) Either way, this is: I think the carrot should go into the intro section for dma-fence, this section here is very much just the "don't do this" part. The previous patches have an attempt at encoding this a bit, maybe see whether there's a place for your reply (or parts of it) to fit? Sounds good to me. Acked-by: Daniel Stone What I'm not sure about is whether the text should be more explicit in flat out mandating the amdkfd eviction fences for long running compute workloads or workloads where userspace fencing is allowed. ... or whether we just say that you can never use dma-fence in conjunction with userptr. Uh userptr is entirely different thing. That one is ok. It's userpsace fences or gpu futexes or future fences or whatever we want to call them. Or is there some other confusion here?. I mean generating a dma_fence from a batch which will try to page in userptr. Given that userptr could be backed by absolutely anything at all, it doesn't seem smart to allow fences to rely on a pointer to an mmap'ed NFS file. So it seems like batches should be mutually exclusive between arbitrary SVM userptr and generating a dma-fence? Locking is Tricky (tm) but essentially what at least amdgpu does is pull in the backing storage before we publish any dma-fence. And then some serious locking magic to make sure that doesn't race with a core mm invalidation event. So for your case here the cs ioctl just blocks until the nfs pages are pulled in. Yeah, we had some iterations until all was settled. Basic idea is the following: 1. Have a sequence counter increased whenever a change to the page tables happens. 2. During CS grab the current value of this counter. 3. Get all the pages you need in an array. 4. Prepare CS, grab the low level lock the MM notifier waits for and double check the counter. 5. If the counter is still the same all is well and the DMA-fence pushed to the hardware. 6. If the counter has changed repeat. Can result in a nice live lock when you constantly page things in/out, but that is expected behavior. Christian. Once we've committed for the dma-fence it's only the other way round, i.e. core mm will stall on the dma-fence if it wants to throw out these pages again. More or less at least. That way we never have a dma-fence depending upon any core mm operations. The only pain here is that this severely limits what you can do in the critical path towards signalling a dma-fence, because the tldr is "no interacting with core mm at all allowed". Speaking of entirely different things ... the virtio-gpu bit really doesn't belong in this patch. Oops, dunno where I lost that as a sparate patch. Will split out again :-( -Daniel Cheers, Daniel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea
Comes up every few years, gets somewhat tedious to discuss, let's
write this down once and for all.
What I'm not sure about is whether the text should be more explicit in
flat out mandating the amdkfd eviction fences for long running compute
workloads or workloads where userspace fencing is allowed.
v2: Now with dot graph!
v3: Typo (Dave Airlie)
Acked-by: Christian König
Acked-by: Daniel Stone
Cc: Jesse Natalie
Cc: Steve Pronovost
Cc: Jason Ekstrand
Cc: Felix Kuehling
Cc: Mika Kuoppala
Cc: Thomas Hellstrom
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-r...@vger.kernel.org
Cc: amd-gfx@lists.freedesktop.org
Cc: intel-...@lists.freedesktop.org
Cc: Chris Wilson
Cc: Maarten Lankhorst
Cc: Christian König
Signed-off-by: Daniel Vetter
---
Documentation/driver-api/dma-buf.rst | 70
1 file changed, 70 insertions(+)
diff --git a/Documentation/driver-api/dma-buf.rst
b/Documentation/driver-api/dma-buf.rst
index f8f6decde359..100bfd227265 100644
--- a/Documentation/driver-api/dma-buf.rst
+++ b/Documentation/driver-api/dma-buf.rst
@@ -178,3 +178,73 @@ DMA Fence uABI/Sync File
.. kernel-doc:: include/linux/sync_file.h
:internal:
+Indefinite DMA Fences
+
+
+At various times _fence with an indefinite time until dma_fence_wait()
+finishes have been proposed. Examples include:
+
+* Future fences, used in HWC1 to signal when a buffer isn't used by the display
+ any longer, and created with the screen update that makes the buffer visible.
+ The time this fence completes is entirely under userspace's control.
+
+* Proxy fences, proposed to handle _syncobj for which the fence has not yet
+ been set. Used to asynchronously delay command submission.
+
+* Userspace fences or gpu futexes, fine-grained locking within a command buffer
+ that userspace uses for synchronization across engines or with the CPU, which
+ are then imported as a DMA fence for integration into existing winsys
+ protocols.
+
+* Long-running compute command buffers, while still using traditional end of
+ batch DMA fences for memory management instead of context preemption DMA
+ fences which get reattached when the compute job is rescheduled.
+
+Common to all these schemes is that userspace controls the dependencies of
these
+fences and controls when they fire. Mixing indefinite fences with normal
+in-kernel DMA fences does not work, even when a fallback timeout is included to
+protect against malicious userspace:
+
+* Only the kernel knows about all DMA fence dependencies, userspace is not
aware
+ of dependencies injected due to memory management or scheduler decisions.
+
+* Only userspace knows about all dependencies in indefinite fences and when
+ exactly they will complete, the kernel has no visibility.
+
+Furthermore the kernel has to be able to hold up userspace command submission
+for memory management needs, which means we must support indefinite fences
being
+dependent upon DMA fences. If the kernel also support indefinite fences in the
+kernel like a DMA fence, like any of the above proposal would, there is the
+potential for deadlocks.
+
+.. kernel-render:: DOT
+ :alt: Indefinite Fencing Dependency Cycle
+ :caption: Indefinite Fencing Dependency Cycle
+
+ digraph "Fencing Cycle" {
+ node [shape=box bgcolor=grey style=filled]
+ kernel [label="Kernel DMA Fences"]
+ userspace [label="userspace controlled fences"]
+ kernel -> userspace [label="memory management"]
+ userspace -> kernel [label="Future fence, fence proxy, ..."]
+
+ { rank=same; kernel userspace }
+ }
+
+This means that the kernel might accidentally create deadlocks
+through memory management dependencies which userspace is unaware of, which
+randomly hangs workloads until the timeout kicks in. Workloads, which from
+userspace's perspective, do not contain a deadlock. In such a mixed fencing
+architecture there is no single entity with knowledge of all dependencies.
+Thefore preventing such deadlocks from within the kernel is not possible.
+
+The only solution to avoid dependencies loops is by not allowing indefinite
+fences in the kernel. This means:
+
+* No future fences, proxy fences or userspace fences imported as DMA fences,
+ with or without a timeout.
+
+* No DMA fences that signal end of batchbuffer for command submission where
+ userspace is allowed to use userspace fencing or long running compute
+ workloads. This also means no implicit fencing for shared buffers in these
+ cases.
--
2.27.0
___
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Re: [Intel-gfx] [PATCH 03/25] dma-buf.rst: Document why idenfinite fences are a bad idea
On Thu, Jul 9, 2020 at 2:11 PM Daniel Stone wrote: > > On Thu, 9 Jul 2020 at 09:05, Daniel Vetter wrote: > > On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote: > > > On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote: > > > > Comes up every few years, gets somewhat tedious to discuss, let's > > > > write this down once and for all. > > > > > > Thanks for writing this up! I wonder if any of the notes from my reply > > > to the previous-version thread would be helpful to more explicitly > > > encode the carrot of dma-fence's positive guarantees, rather than just > > > the stick of 'don't do this'. ;) Either way, this is: > > > > I think the carrot should go into the intro section for dma-fence, this > > section here is very much just the "don't do this" part. The previous > > patches have an attempt at encoding this a bit, maybe see whether there's > > a place for your reply (or parts of it) to fit? > > Sounds good to me. > > > > Acked-by: Daniel Stone > > > > > > > What I'm not sure about is whether the text should be more explicit in > > > > flat out mandating the amdkfd eviction fences for long running compute > > > > workloads or workloads where userspace fencing is allowed. > > > > > > ... or whether we just say that you can never use dma-fence in > > > conjunction with userptr. > > > > Uh userptr is entirely different thing. That one is ok. It's userpsace > > fences or gpu futexes or future fences or whatever we want to call them. > > Or is there some other confusion here?. > > I mean generating a dma_fence from a batch which will try to page in > userptr. Given that userptr could be backed by absolutely anything at > all, it doesn't seem smart to allow fences to rely on a pointer to an > mmap'ed NFS file. So it seems like batches should be mutually > exclusive between arbitrary SVM userptr and generating a dma-fence? Locking is Tricky (tm) but essentially what at least amdgpu does is pull in the backing storage before we publish any dma-fence. And then some serious locking magic to make sure that doesn't race with a core mm invalidation event. So for your case here the cs ioctl just blocks until the nfs pages are pulled in. Once we've committed for the dma-fence it's only the other way round, i.e. core mm will stall on the dma-fence if it wants to throw out these pages again. More or less at least. That way we never have a dma-fence depending upon any core mm operations. The only pain here is that this severely limits what you can do in the critical path towards signalling a dma-fence, because the tldr is "no interacting with core mm at all allowed". > Speaking of entirely different things ... the virtio-gpu bit really > doesn't belong in this patch. Oops, dunno where I lost that as a sparate patch. Will split out again :-( -Daniel > > Cheers, > Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [Intel-gfx] [PATCH 03/25] dma-buf.rst: Document why idenfinite fences are a bad idea
On Thu, 9 Jul 2020 at 09:05, Daniel Vetter wrote: > On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote: > > On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote: > > > Comes up every few years, gets somewhat tedious to discuss, let's > > > write this down once and for all. > > > > Thanks for writing this up! I wonder if any of the notes from my reply > > to the previous-version thread would be helpful to more explicitly > > encode the carrot of dma-fence's positive guarantees, rather than just > > the stick of 'don't do this'. ;) Either way, this is: > > I think the carrot should go into the intro section for dma-fence, this > section here is very much just the "don't do this" part. The previous > patches have an attempt at encoding this a bit, maybe see whether there's > a place for your reply (or parts of it) to fit? Sounds good to me. > > Acked-by: Daniel Stone > > > > > What I'm not sure about is whether the text should be more explicit in > > > flat out mandating the amdkfd eviction fences for long running compute > > > workloads or workloads where userspace fencing is allowed. > > > > ... or whether we just say that you can never use dma-fence in > > conjunction with userptr. > > Uh userptr is entirely different thing. That one is ok. It's userpsace > fences or gpu futexes or future fences or whatever we want to call them. > Or is there some other confusion here?. I mean generating a dma_fence from a batch which will try to page in userptr. Given that userptr could be backed by absolutely anything at all, it doesn't seem smart to allow fences to rely on a pointer to an mmap'ed NFS file. So it seems like batches should be mutually exclusive between arbitrary SVM userptr and generating a dma-fence? Speaking of entirely different things ... the virtio-gpu bit really doesn't belong in this patch. Cheers, Daniel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 03/25] dma-buf.rst: Document why idenfinite fences are a bad idea
Am 07.07.20 um 22:12 schrieb Daniel Vetter:
Comes up every few years, gets somewhat tedious to discuss, let's
write this down once and for all.
What I'm not sure about is whether the text should be more explicit in
flat out mandating the amdkfd eviction fences for long running compute
workloads or workloads where userspace fencing is allowed.
v2: Now with dot graph!
Cc: Jesse Natalie
Cc: Steve Pronovost
Cc: Jason Ekstrand
Cc: Felix Kuehling
Cc: Mika Kuoppala
Cc: Thomas Hellstrom
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-r...@vger.kernel.org
Cc: amd-gfx@lists.freedesktop.org
Cc: intel-...@lists.freedesktop.org
Cc: Chris Wilson
Cc: Maarten Lankhorst
Cc: Christian König
Signed-off-by: Daniel Vetter
Acked-by: Christian König
---
Documentation/driver-api/dma-buf.rst | 70
drivers/gpu/drm/virtio/virtgpu_display.c | 20 ---
2 files changed, 70 insertions(+), 20 deletions(-)
diff --git a/Documentation/driver-api/dma-buf.rst
b/Documentation/driver-api/dma-buf.rst
index f8f6decde359..037ba0078bb4 100644
--- a/Documentation/driver-api/dma-buf.rst
+++ b/Documentation/driver-api/dma-buf.rst
@@ -178,3 +178,73 @@ DMA Fence uABI/Sync File
.. kernel-doc:: include/linux/sync_file.h
:internal:
+Idefinite DMA Fences
+
+
+At various times _fence with an indefinite time until dma_fence_wait()
+finishes have been proposed. Examples include:
+
+* Future fences, used in HWC1 to signal when a buffer isn't used by the display
+ any longer, and created with the screen update that makes the buffer visible.
+ The time this fence completes is entirely under userspace's control.
+
+* Proxy fences, proposed to handle _syncobj for which the fence has not yet
+ been set. Used to asynchronously delay command submission.
+
+* Userspace fences or gpu futexes, fine-grained locking within a command buffer
+ that userspace uses for synchronization across engines or with the CPU, which
+ are then imported as a DMA fence for integration into existing winsys
+ protocols.
+
+* Long-running compute command buffers, while still using traditional end of
+ batch DMA fences for memory management instead of context preemption DMA
+ fences which get reattached when the compute job is rescheduled.
+
+Common to all these schemes is that userspace controls the dependencies of
these
+fences and controls when they fire. Mixing indefinite fences with normal
+in-kernel DMA fences does not work, even when a fallback timeout is included to
+protect against malicious userspace:
+
+* Only the kernel knows about all DMA fence dependencies, userspace is not
aware
+ of dependencies injected due to memory management or scheduler decisions.
+
+* Only userspace knows about all dependencies in indefinite fences and when
+ exactly they will complete, the kernel has no visibility.
+
+Furthermore the kernel has to be able to hold up userspace command submission
+for memory management needs, which means we must support indefinite fences
being
+dependent upon DMA fences. If the kernel also support indefinite fences in the
+kernel like a DMA fence, like any of the above proposal would, there is the
+potential for deadlocks.
+
+.. kernel-render:: DOT
+ :alt: Indefinite Fencing Dependency Cycle
+ :caption: Indefinite Fencing Dependency Cycle
+
+ digraph "Fencing Cycle" {
+ node [shape=box bgcolor=grey style=filled]
+ kernel [label="Kernel DMA Fences"]
+ userspace [label="userspace controlled fences"]
+ kernel -> userspace [label="memory management"]
+ userspace -> kernel [label="Future fence, fence proxy, ..."]
+
+ { rank=same; kernel userspace }
+ }
+
+This means that the kernel might accidentally create deadlocks
+through memory management dependencies which userspace is unaware of, which
+randomly hangs workloads until the timeout kicks in. Workloads, which from
+userspace's perspective, do not contain a deadlock. In such a mixed fencing
+architecture there is no single entity with knowledge of all dependencies.
+Thefore preventing such deadlocks from within the kernel is not possible.
+
+The only solution to avoid dependencies loops is by not allowing indefinite
+fences in the kernel. This means:
+
+* No future fences, proxy fences or userspace fences imported as DMA fences,
+ with or without a timeout.
+
+* No DMA fences that signal end of batchbuffer for command submission where
+ userspace is allowed to use userspace fencing or long running compute
+ workloads. This also means no implicit fencing for shared buffers in these
+ cases.
diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c
b/drivers/gpu/drm/virtio/virtgpu_display.c
index f3ce49c5a34c..af55b334be2f 100644
--- a/drivers/gpu/drm/virtio/virtgpu_display.c
+++ b/drivers/gpu/drm/virtio/virtgpu_display.c
@@ -314,25 +314,6 @@ virtio_gpu_user_framebuffer_create(struct drm_device *dev,
return _gpu_fb->base;
}
-static void
[PATCH] drm/amd/smu: correct a mistake
Corresponding to smu_workload_get_type(smu, type) is "get_workload_type" Signed-off-by: chen gong --- drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h index afd786b..31e1fcb 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h @@ -77,7 +77,7 @@ #define smu_feature_get_index(smu, fea) smu_ppt_funcs(get_smu_feature_index, -EINVAL, smu, fea) #define smu_table_get_index(smu, tab) smu_ppt_funcs(get_smu_table_index, -EINVAL, smu, tab) #define smu_power_get_index(smu, src) smu_ppt_funcs(get_smu_power_index, -EINVAL, smu, src) -#define smu_workload_get_type(smu, type) smu_ppt_funcs(get_smu_power_index, -EINVAL, smu, type) +#define smu_workload_get_type(smu, type) smu_ppt_funcs(get_workload_type, -EINVAL, smu, type) #define smu_run_btc(smu) smu_ppt_funcs(run_btc, 0, smu) #define smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num) #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) smu_ppt_funcs(store_cc6_data, 0, smu, st, cc6_dis, pst_dis, pst_sw_dis) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 02/25] dma-fence: prime lockdep annotations
Hi Jason, Below the paragraph I've added after our discussions around dma-fences outside of drivers/gpu. Good enough for an ack on this, or want something changed? Thanks, Daniel > + * Note that only GPU drivers have a reasonable excuse for both requiring > + * _interval_notifier and callbacks at the same time as having > to > + * track asynchronous compute work using _fence. No driver outside of > + * drivers/gpu should ever call dma_fence_wait() in such contexts. On Tue, Jul 07, 2020 at 10:12:06PM +0200, Daniel Vetter wrote: > Two in one go: > - it is allowed to call dma_fence_wait() while holding a > dma_resv_lock(). This is fundamental to how eviction works with ttm, > so required. > > - it is allowed to call dma_fence_wait() from memory reclaim contexts, > specifically from shrinker callbacks (which i915 does), and from mmu > notifier callbacks (which amdgpu does, and which i915 sometimes also > does, and probably always should, but that's kinda a debate). Also > for stuff like HMM we really need to be able to do this, or things > get real dicey. > > Consequence is that any critical path necessary to get to a > dma_fence_signal for a fence must never a) call dma_resv_lock nor b) > allocate memory with GFP_KERNEL. Also by implication of > dma_resv_lock(), no userspace faulting allowed. That's some supremely > obnoxious limitations, which is why we need to sprinkle the right > annotations to all relevant paths. > > The one big locking context we're leaving out here is mmu notifiers, > added in > > commit 23b68395c7c78a764e8963fc15a7cfd318bf187f > Author: Daniel Vetter > Date: Mon Aug 26 22:14:21 2019 +0200 > > mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end > > that one covers a lot of other callsites, and it's also allowed to > wait on dma-fences from mmu notifiers. But there's no ready-made > functions exposed to prime this, so I've left it out for now. > > v2: Also track against mmu notifier context. > > v3: kerneldoc to spec the cross-driver contract. Note that currently > i915 throws in a hard-coded 10s timeout on foreign fences (not sure > why that was done, but it's there), which is why that rule is worded > with SHOULD instead of MUST. > > Also some of the mmu_notifier/shrinker rules might surprise SoC > drivers, I haven't fully audited them all. Which is infeasible anyway, > we'll need to run them with lockdep and dma-fence annotations and see > what goes boom. > > v4: A spelling fix from Mika > > v5: #ifdef for CONFIG_MMU_NOTIFIER. Reported by 0day. Unfortunately > this means lockdep enforcement is slightly inconsistent, it won't spot > GFP_NOIO and GFP_NOFS allocations in the wrong spot if > CONFIG_MMU_NOTIFIER is disabled in the kernel config. Oh well. > > v5: Note that only drivers/gpu has a reasonable (or at least > historical) excuse to use dma_fence_wait() from shrinker and mmu > notifier callbacks. Everyone else should either have a better memory > manager model, or better hardware. This reflects discussions with > Jason Gunthorpe. > > Cc: Jason Gunthorpe > Cc: Felix Kuehling > Cc: kernel test robot > Reviewed-by: Thomas Hellström (v4) > Cc: Mika Kuoppala > Cc: Thomas Hellstrom > Cc: linux-me...@vger.kernel.org > Cc: linaro-mm-...@lists.linaro.org > Cc: linux-r...@vger.kernel.org > Cc: amd-gfx@lists.freedesktop.org > Cc: intel-...@lists.freedesktop.org > Cc: Chris Wilson > Cc: Maarten Lankhorst > Cc: Christian König > Signed-off-by: Daniel Vetter > --- > Documentation/driver-api/dma-buf.rst | 6 > drivers/dma-buf/dma-fence.c | 46 > drivers/dma-buf/dma-resv.c | 8 + > include/linux/dma-fence.h| 1 + > 4 files changed, 61 insertions(+) > > diff --git a/Documentation/driver-api/dma-buf.rst > b/Documentation/driver-api/dma-buf.rst > index 05d856131140..f8f6decde359 100644 > --- a/Documentation/driver-api/dma-buf.rst > +++ b/Documentation/driver-api/dma-buf.rst > @@ -133,6 +133,12 @@ DMA Fences > .. kernel-doc:: drivers/dma-buf/dma-fence.c > :doc: DMA fences overview > > +DMA Fence Cross-Driver Contract > +~~~ > + > +.. kernel-doc:: drivers/dma-buf/dma-fence.c > + :doc: fence cross-driver contract > + > DMA Fence Signalling Annotations > > > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > index 0005bc002529..af1d8ea926b3 100644 > --- a/drivers/dma-buf/dma-fence.c > +++ b/drivers/dma-buf/dma-fence.c > @@ -64,6 +64,52 @@ static atomic64_t dma_fence_context_counter = > ATOMIC64_INIT(1); > * _buf.resv pointer. > */ > > +/** > + * DOC: fence cross-driver contract > + * > + * Since _fence provide a cross driver contract, all drivers must follow > the > + * same rules: > + * > + * * Fences must complete in a reasonable time. Fences which represent > kernels > + * and shaders submitted by userspace, which could run forever, must be > backed > +
Re: [Intel-gfx] [PATCH 03/25] dma-buf.rst: Document why idenfinite fences are a bad idea
On Thu, Jul 09, 2020 at 08:36:43AM +0100, Daniel Stone wrote: > Hi, > > On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote: > > Comes up every few years, gets somewhat tedious to discuss, let's > > write this down once and for all. > > Thanks for writing this up! I wonder if any of the notes from my reply > to the previous-version thread would be helpful to more explicitly > encode the carrot of dma-fence's positive guarantees, rather than just > the stick of 'don't do this'. ;) Either way, this is: I think the carrot should go into the intro section for dma-fence, this section here is very much just the "don't do this" part. The previous patches have an attempt at encoding this a bit, maybe see whether there's a place for your reply (or parts of it) to fit? > Acked-by: Daniel Stone > > > What I'm not sure about is whether the text should be more explicit in > > flat out mandating the amdkfd eviction fences for long running compute > > workloads or workloads where userspace fencing is allowed. > > ... or whether we just say that you can never use dma-fence in > conjunction with userptr. Uh userptr is entirely different thing. That one is ok. It's userpsace fences or gpu futexes or future fences or whatever we want to call them. Or is there some other confusion here?. -Daniel > > Cheers, > Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations
On Thu, Jul 09, 2020 at 08:29:21AM +0100, Daniel Stone wrote: > Hi, > Jumping in after a couple of weeks where I've paged most everything > out of my brain ... > > On Fri, 19 Jun 2020 at 10:43, Daniel Vetter wrote: > > On Fri, Jun 19, 2020 at 10:13:35AM +0100, Chris Wilson wrote: > > > > The proposed patches might very well encode the wrong contract, that's > > > > all up for discussion. But fundamentally questioning that we need one > > > > is missing what upstream is all about. > > > > > > Then I have not clearly communicated, as my opinion is not that > > > validation is worthless, but that the implementation is enshrining a > > > global property on a low level primitive that prevents it from being > > > used elsewhere. And I want to replace completion [chains] with fences, and > > > bio with fences, and closures with fences, and what other equivalencies > > > there are in the kernel. The fence is as central a locking construct as > > > struct completion and deserves to be a foundational primitive provided > > > by kernel/ used throughout all drivers for discrete problem domains. > > > > > > This is narrowing dma_fence whereby adding > > > struct lockdep_map *dma_fence::wait_map > > > and annotating linkage, allows you to continue to specify that all > > > dma_fence used for a particular purpose must follow common rules, > > > without restricting the primitive for uses outside of this scope. > > > > Somewhere else in this thread I had discussions with Jason Gunthorpe about > > this topic. It might maybe change somewhat depending upon exact rules, but > > his take is very much "I don't want dma_fence in rdma". Or pretty close to > > that at least. > > > > Similar discussions with habanalabs, they're using dma_fence internally > > without any of the uapi. Discussion there has also now concluded that it's > > best if they remove them, and simply switch over to a wait_queue or > > completion like every other driver does. > > > > The next round of the patches already have a paragraph to at least > > somewhat limit how non-gpu drivers use dma_fence. And I guess actual > > consensus might be pointing even more strongly at dma_fence being solely > > something for gpus and closely related subsystem (maybe media) for syncing > > dma-buf access. > > > > So dma_fence as general replacement for completion chains I think just > > wont happen. > > > > What might make sense is if e.g. the lockdep annotations could be reused, > > at least in design, for wait_queue or completion or anything else > > really. I do think that has a fair chance compared to the automagic > > cross-release annotations approach, which relied way too heavily on > > guessing where barriers are. My experience from just a bit of playing > > around with these patches here and discussing them with other driver > > maintainers is that accurately deciding where critical sections start and > > end is a job for humans only. And if you get it wrong, you will have a > > false positive. > > > > And you're indeed correct that if we'd do annotations for completions and > > wait queues, then that would need to have a class per semantically > > equivalent user, like we have lockdep classes for mutexes, not just one > > overall. > > > > But dma_fence otoh is something very specific, which comes with very > > specific rules attached - it's not a generic wait_queue at all. Originally > > it did start out as one even, but it is a very specialized wait_queue. > > > > So there's imo two cases: > > > > - Your completion is entirely orthogonal of dma_fences, and can never ever > > block a dma_fence. Don't use dma_fence for this, and no problem. It's > > just another wait_queue somewhere. > > > > - Your completion can eventually, maybe through lots of convolutions and > > depdencies, block a dma_fence. In that case full dma_fence rules apply, > > and the only thing you can do with a custom annotation is make the rules > > even stricter. E.g. if a sub-timeline in the scheduler isn't allowed to > > take certain scheduler locks. But the userspace visible/published fence > > do take them, maybe as part of command submission or retirement. > > Entirely hypotethical, no idea any driver actually needs this. > > I don't claim to understand the implementation of i915's scheduler and > GEM handling, and it seems like there's some public context missing > here. But to me, the above is a good statement of what I (and a lot of > other userspace) have been relying on - that dma-fence is a very > tightly scoped thing which is very predictable but in extremis. > > It would be great to have something like this enshrined in dma-fence > documentation, visible to both kernel and external users. The > properties we've so far been assuming for the graphics pipeline - > covering production & execution of vertex/fragment workloads on the > GPU, framebuffer display, and to the extent this is necessary > involving compute - are something like this: > > A single
Re: [Intel-gfx] [PATCH 01/25] dma-fence: basic lockdep annotations
On Thu, Jul 09, 2020 at 08:32:41AM +0100, Daniel Stone wrote: > Hi, > > On Wed, 8 Jul 2020 at 16:13, Daniel Vetter wrote: > > On Wed, Jul 8, 2020 at 4:57 PM Christian König > > wrote: > > > Could we merge this controlled by a separate config option? > > > > > > This way we could have the checks upstream without having to fix all the > > > stuff before we do this? > > > > Since it's fully opt-in annotations nothing blows up if we don't merge > > any annotations. So we could start merging the first 3 patches. After > > that the fun starts ... > > > > My rough idea was that first I'd try to tackle display, thus far > > there's 2 actual issues in drivers: > > - amdgpu has some dma_resv_lock in commit_tail, plus a kmalloc. I > > think those should be fairly easy to fix (I'd try a stab at them even) > > - vmwgfx has a full on locking inversion with dma_resv_lock in > > commit_tail, and that one is functional. Not just reading something > > which we can safely assume to be invariant anyway (like the tmz flag > > for amdgpu, or whatever it was). > > > > I've done a pile more annotations patches for other atomic drivers > > now, so hopefully that flushes out any remaining offenders here. Since > > some of the annotations are in helper code worst case we might need a > > dev->mode_config.broken_atomic_commit flag to disable them. At least > > for now I have 0 plans to merge any of these while there's known > > unsolved issues. Maybe if some drivers take forever to get fixed we > > can then apply some duct-tape for the atomic helper annotation patch. > > Instead of a flag we can also copypasta the atomic_commit_tail hook, > > leaving the annotations out and adding a huge warning about that. > > How about an opt-in drm_driver DRIVER_DEADLOCK_HAPPY flag? At first > this could just disable the annotations and nothing else, but as we > see the annotations gaining real-world testing and maturity, we could > eventually make it taint the kernel. You can do that pretty much per-driver, since the annotations are pretty much per-driver. No annotations in your code, no lockdep splat. Only if there's some dma_fence_begin/end_signalling() calls is there even the chance of a problem. E.g. this round has the i915 patch dropped and *trar* intel-gfx-ci is happy (or well at least a lot happier, there's some noise in there that's probably not from my stuff). So I guess if amd wants this, we could do an DRM_AMDGPU_MOAR_LOCKDEP Kconfig or similar. I haven't tested, but I think as long as we don't merge any of the amdgpu specific patches, there's no splat in amdgpu. So with that I think that's plenty enough opt-in for each driver. The only problem is a bit shared helper code like atomic helpers and drm scheduler. There we might need some opt-out (I don't think merging makes sense when most of the users are still broken). -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [Intel-gfx] [PATCH 03/25] dma-buf.rst: Document why idenfinite fences are a bad idea
Hi, On Tue, 7 Jul 2020 at 21:13, Daniel Vetter wrote: > Comes up every few years, gets somewhat tedious to discuss, let's > write this down once and for all. Thanks for writing this up! I wonder if any of the notes from my reply to the previous-version thread would be helpful to more explicitly encode the carrot of dma-fence's positive guarantees, rather than just the stick of 'don't do this'. ;) Either way, this is: Acked-by: Daniel Stone > What I'm not sure about is whether the text should be more explicit in > flat out mandating the amdkfd eviction fences for long running compute > workloads or workloads where userspace fencing is allowed. ... or whether we just say that you can never use dma-fence in conjunction with userptr. Cheers, Daniel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [Intel-gfx] [PATCH 01/25] dma-fence: basic lockdep annotations
Hi, On Wed, 8 Jul 2020 at 16:13, Daniel Vetter wrote: > On Wed, Jul 8, 2020 at 4:57 PM Christian König > wrote: > > Could we merge this controlled by a separate config option? > > > > This way we could have the checks upstream without having to fix all the > > stuff before we do this? > > Since it's fully opt-in annotations nothing blows up if we don't merge > any annotations. So we could start merging the first 3 patches. After > that the fun starts ... > > My rough idea was that first I'd try to tackle display, thus far > there's 2 actual issues in drivers: > - amdgpu has some dma_resv_lock in commit_tail, plus a kmalloc. I > think those should be fairly easy to fix (I'd try a stab at them even) > - vmwgfx has a full on locking inversion with dma_resv_lock in > commit_tail, and that one is functional. Not just reading something > which we can safely assume to be invariant anyway (like the tmz flag > for amdgpu, or whatever it was). > > I've done a pile more annotations patches for other atomic drivers > now, so hopefully that flushes out any remaining offenders here. Since > some of the annotations are in helper code worst case we might need a > dev->mode_config.broken_atomic_commit flag to disable them. At least > for now I have 0 plans to merge any of these while there's known > unsolved issues. Maybe if some drivers take forever to get fixed we > can then apply some duct-tape for the atomic helper annotation patch. > Instead of a flag we can also copypasta the atomic_commit_tail hook, > leaving the annotations out and adding a huge warning about that. How about an opt-in drm_driver DRIVER_DEADLOCK_HAPPY flag? At first this could just disable the annotations and nothing else, but as we see the annotations gaining real-world testing and maturity, we could eventually make it taint the kernel. Cheers, Daniel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
drm: BUG: unable to handle page fault for address: 17ec6000
Dear Linux folks, Building Linux v5.8-rc4-25-gbfe91da29bfad with Clang/LLD 1:11~++20200701093119+ffee8040534-1~exp1 from Debian experimental for 32-bit (`ARCH=i386`), starting Weston (Wayland) or X.Org Server results in non-working screen, and Linux shows the trace below [1]. [ 502.044997] BUG: unable to handle page fault for address: 17ec6000 [ 502.045650] #PF: supervisor write access in kernel mode [ 502.046301] #PF: error_code(0x0002) - not-present page [ 502.046956] *pde = [ 502.047612] Oops: 0002 [#1] SMP [ 502.048269] CPU: 0 PID: 2125 Comm: Xorg.wrap Not tainted 5.8.0-rc4-00105-g4da71f1ee6263 #141 [ 502.048967] Hardware name: System manufacturer System Product Name/F2A85-M PRO, BIOS 6601 11/25/2014 [ 502.049686] EIP: __srcu_read_lock+0x11/0x20 [ 502.050413] Code: 83 e0 03 50 56 68 72 c6 99 dd 68 46 c6 99 dd e8 3a c8 fe ff 83 c4 10 eb ce 0f 1f 44 00 00 55 89 e5 8b 48 68 8b 40 7c 83 e1 01 <64> ff 04 88 f0 83 44 24 fc 00 89 c8 5d c3 90 0f 1f 44 00 00 55 89 [ 502.052027] EAX: EBX: f36671b8 ECX: EDX: 0286 [ 502.052856] ESI: f3f94eb8 EDI: f3e51c00 EBP: f303dd9c ESP: f303dd9c [ 502.053695] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00010246 [ 502.054543] CR0: 80050033 CR2: 17ec6000 CR3: 2eea2000 CR4: 000406d0 [ 502.055402] Call Trace: [ 502.056275] drm_minor_acquire+0x6f/0x140 [drm] [ 502.057162] drm_stub_open+0x2e/0x110 [drm] [ 502.058049] chrdev_open+0xdd/0x1e0 [ 502.058937] do_dentry_open+0x21d/0x330 [ 502.059828] vfs_open+0x23/0x30 [ 502.060718] path_openat+0x947/0xd60 [ 502.061610] ? unlink_anon_vmas+0x53/0x120 [ 502.062504] do_filp_open+0x6d/0x100 [ 502.063404] ? __alloc_fd+0x73/0x140 [ 502.064305] do_sys_openat2+0x1b3/0x2a0 [ 502.065217] __ia32_sys_openat+0x90/0xb0 [ 502.066128] ? prepare_exit_to_usermode+0xa/0x20 [ 502.067046] do_fast_syscall_32+0x68/0xd0 [ 502.067970] do_SYSENTER_32+0x12/0x20 [ 502.068902] entry_SYSENTER_32+0x9f/0xf2 [ 502.069839] EIP: 0xb7ef14f9 [ 502.070764] Code: Bad RIP value. [ 502.071689] EAX: ffda EBX: ff9c ECX: bfa6a2ac EDX: 8002 [ 502.072654] ESI: EDI: b7ed1000 EBP: bfa6b2c8 ESP: bfa6a1c0 [ 502.073630] DS: 007b ES: 007b FS: GS: 0033 SS: 007b EFLAGS: 0246 [ 502.074615] Modules linked in: af_packet k10temp r8169 realtek i2c_piix4 snd_hda_codec_realtek snd_hda_codec_generic ohci_pci ohci_hcd ehci_pci snd_hda_codec_hdmi ehci_hcd radeon i2c_algo_bit snd_hda_intel ttm snd_intel_dspcfg snd_hda_codec drm_kms_helper snd_hda_core snd_pcm cfbimgblt cfbcopyarea cfbfillrect snd_timer sysimgblt syscopyarea sysfillrect snd fb_sys_fops xhci_pci xhci_hcd soundcore acpi_cpufreq drm drm_panel_orientation_quirks agpgart ipv6 nf_defrag_ipv6 [ 502.077895] CR2: 17ec6000 [ 502.079050] ---[ end trace ced4517b63a6db26 ]--- [ 502.080214] EIP: __srcu_read_lock+0x11/0x20 [ 502.081392] Code: 83 e0 03 50 56 68 72 c6 99 dd 68 46 c6 99 dd e8 3a c8 fe ff 83 c4 10 eb ce 0f 1f 44 00 00 55 89 e5 8b 48 68 8b 40 7c 83 e1 01 <64> ff 04 88 f0 83 44 24 fc 00 89 c8 5d c3 90 0f 1f 44 00 00 55 89 [ 502.083891] EAX: EBX: f36671b8 ECX: EDX: 0286 [ 502.085148] ESI: f3f94eb8 EDI: f3e51c00 EBP: f303dd9c ESP: f303dd9c [ 502.086406] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00010246 [ 502.087675] CR0: 80050033 CR2: 17ec6000 CR3: 2eea2000 CR4: 000406d0 $ dmesg | ./scripts/decodecode [ 55.784870] Code: 83 e0 03 50 56 68 ca c6 99 cf 68 9e c6 99 cf e8 3a c8 fe ff 83 c4 10 eb ce 0f 1f 44 00 00 55 89 e5 8b 48 68 8b 40 7c 83 e1 01 <64> ff 04 88 f0 83 44 24 fc 00 89 c8 5d c3 90 0f 1f 44 00 00 55 89 All code 0: 83 e0 03and$0x3,%eax 3: 50 push %eax 4: 56 push %esi 5: 68 ca c6 99 cf push $0xcf99c6ca a: 68 9e c6 99 cf push $0xcf99c69e f: e8 3a c8 fe ff call 0xfffec84e 14: 83 c4 10add$0x10,%esp 17: eb ce jmp0xffe7 19: 0f 1f 44 00 00 nopl 0x0(%eax,%eax,1) 1e: 55 push %ebp 1f: 89 e5 mov%esp,%ebp 21: 8b 48 68mov0x68(%eax),%ecx 24: 8b 40 7cmov0x7c(%eax),%eax 27: 83 e1 01and$0x1,%ecx 2a:* 64 ff 04 88 incl %fs:(%eax,%ecx,4)<-- trapping instruction 2e: f0 83 44 24 fc 00 lock addl $0x0,-0x4(%esp) 34: 89 c8 mov%ecx,%eax 36: 5d pop%ebp 37: c3 ret 38: 90 nop 39: 0f 1f 44 00 00 nopl 0x0(%eax,%eax,1) 3e: 55 push %ebp 3f: 89 .byte 0x89 Code starting with the faulting instruction === 0: 64 ff 04 88 incl %fs:(%eax,%ecx,4) 4: f0 83 44 24 fc 00 lock addl
Re: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations
Hi, Jumping in after a couple of weeks where I've paged most everything out of my brain ... On Fri, 19 Jun 2020 at 10:43, Daniel Vetter wrote: > On Fri, Jun 19, 2020 at 10:13:35AM +0100, Chris Wilson wrote: > > > The proposed patches might very well encode the wrong contract, that's > > > all up for discussion. But fundamentally questioning that we need one > > > is missing what upstream is all about. > > > > Then I have not clearly communicated, as my opinion is not that > > validation is worthless, but that the implementation is enshrining a > > global property on a low level primitive that prevents it from being > > used elsewhere. And I want to replace completion [chains] with fences, and > > bio with fences, and closures with fences, and what other equivalencies > > there are in the kernel. The fence is as central a locking construct as > > struct completion and deserves to be a foundational primitive provided > > by kernel/ used throughout all drivers for discrete problem domains. > > > > This is narrowing dma_fence whereby adding > > struct lockdep_map *dma_fence::wait_map > > and annotating linkage, allows you to continue to specify that all > > dma_fence used for a particular purpose must follow common rules, > > without restricting the primitive for uses outside of this scope. > > Somewhere else in this thread I had discussions with Jason Gunthorpe about > this topic. It might maybe change somewhat depending upon exact rules, but > his take is very much "I don't want dma_fence in rdma". Or pretty close to > that at least. > > Similar discussions with habanalabs, they're using dma_fence internally > without any of the uapi. Discussion there has also now concluded that it's > best if they remove them, and simply switch over to a wait_queue or > completion like every other driver does. > > The next round of the patches already have a paragraph to at least > somewhat limit how non-gpu drivers use dma_fence. And I guess actual > consensus might be pointing even more strongly at dma_fence being solely > something for gpus and closely related subsystem (maybe media) for syncing > dma-buf access. > > So dma_fence as general replacement for completion chains I think just > wont happen. > > What might make sense is if e.g. the lockdep annotations could be reused, > at least in design, for wait_queue or completion or anything else > really. I do think that has a fair chance compared to the automagic > cross-release annotations approach, which relied way too heavily on > guessing where barriers are. My experience from just a bit of playing > around with these patches here and discussing them with other driver > maintainers is that accurately deciding where critical sections start and > end is a job for humans only. And if you get it wrong, you will have a > false positive. > > And you're indeed correct that if we'd do annotations for completions and > wait queues, then that would need to have a class per semantically > equivalent user, like we have lockdep classes for mutexes, not just one > overall. > > But dma_fence otoh is something very specific, which comes with very > specific rules attached - it's not a generic wait_queue at all. Originally > it did start out as one even, but it is a very specialized wait_queue. > > So there's imo two cases: > > - Your completion is entirely orthogonal of dma_fences, and can never ever > block a dma_fence. Don't use dma_fence for this, and no problem. It's > just another wait_queue somewhere. > > - Your completion can eventually, maybe through lots of convolutions and > depdencies, block a dma_fence. In that case full dma_fence rules apply, > and the only thing you can do with a custom annotation is make the rules > even stricter. E.g. if a sub-timeline in the scheduler isn't allowed to > take certain scheduler locks. But the userspace visible/published fence > do take them, maybe as part of command submission or retirement. > Entirely hypotethical, no idea any driver actually needs this. I don't claim to understand the implementation of i915's scheduler and GEM handling, and it seems like there's some public context missing here. But to me, the above is a good statement of what I (and a lot of other userspace) have been relying on - that dma-fence is a very tightly scoped thing which is very predictable but in extremis. It would be great to have something like this enshrined in dma-fence documentation, visible to both kernel and external users. The properties we've so far been assuming for the graphics pipeline - covering production & execution of vertex/fragment workloads on the GPU, framebuffer display, and to the extent this is necessary involving compute - are something like this: A single dma-fence with no dependencies represents (the tail of) a unit of work, which has been all but committed to the hardware. Once committed to the hardware, this work will complete (successfully or in error) in bounded time. The unit of work referred to
Re: [Proposal] DRM: AMD: Convert logging to drm_* functions.
Am 08.07.20 um 18:11 schrieb Suraj Upadhyay: Hii AMD Maintainers, I plan to convert logging of information, error and warnings inside the AMD driver(s) to drm_* functions and macros for loggin, as described by the TODO list in the DRM documentation[1]. I need your approval for the change before sending any patches, to make sure that this is a good idea and that the patches will be merged. The patches will essentially convert all the dev_info(), dev_warn(), dev_err() and dev_err_once() to drm_info(), drm_warn(), drm_err() and drm_err_once() respectively. Well to be honest I would rather like see the conversion done in the other direction. I think the drm_* functions are just an unnecessary extra layer on top of the core kernel functions and should probably be removed sooner or later because of midlayering. Regards, Christian. Thank You, Suraj Upadhyay. [1] https://dri.freedesktop.org/docs/drm/gpu/todo.html#convert-logging-to-drm-functions-with-drm-device-paramater ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid
From: Likun Gao
Update sienna_cichlid driver if header and related files.
Signed-off-by: Likun Gao
Change-Id: If303e7fca32ebf922ee5d918855bbaca8dc61d38
---
.../inc/smu11_driver_if_sienna_cichlid.h| 17 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
.../gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 -
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index 302c2bcf9404..b2232e24d82f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x32
+#define SMU11_DRIVER_IF_VERSION 0x33
-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
#define NUM_GFXCLK_DPM_LEVELS 16
#define NUM_SMNCLK_DPM_LEVELS 2
@@ -128,7 +128,7 @@
#define FEATURE_2_STEP_PSTATE_BIT 46
#define FEATURE_SMNCLK_DPM_BIT 47
#define FEATURE_SPARE_48_BIT48
-#define FEATURE_SPARE_49_BIT49
+#define FEATURE_GFX_EDC_BIT 49
#define FEATURE_SPARE_50_BIT50
#define FEATURE_SPARE_51_BIT51
#define FEATURE_SPARE_52_BIT52
@@ -564,6 +564,12 @@ typedef enum {
TDC_THROTTLER_COUNT
} TDC_THROTTLER_e;
+typedef enum {
+ CUSTOMER_VARIANT_ROW,
+ CUSTOMER_VARIANT_FALCON,
+ CUSTOMER_VARIANT_COUNT,
+} CUSTOMER_VARIANT_e;
+
// Used for 2-step UCLK DPM change workaround
typedef struct {
uint16_t Fmin;
@@ -786,7 +792,10 @@ typedef struct {
QuadraticInt_tReservedEquation3;
// SECTION: Sku Reserved
- uint32_t SkuReserved[15];
+ uint8_t CustomerVariant;
+ uint8_t Spare[3];
+ uint32_t SkuReserved[14];
+
// MAJOR SECTION: BOARD PARAMETERS
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index d07bf4fe6e4a..b2f65438ad8d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x32
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
/* MP Apertures */
#define MP0_Public 0x0380
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dc5ca9121db5..3efa41444ddf 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -2317,7 +2317,6 @@ static void sienna_cichlid_dump_pptable(struct
smu_context *smu)
dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n",
pptable->SkuReserved[11]);
dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n",
pptable->SkuReserved[12]);
dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n",
pptable->SkuReserved[13]);
- dev_info(smu->adev->dev, "SkuReserved[14] = 0x%x\n",
pptable->SkuReserved[14]);
dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n",
pptable->GamingClk[0]);
dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n",
pptable->GamingClk[1]);
--
2.25.1
___
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Re: [PATCH] Revert "drm/amd/display: add mechanism to skip DCN init"
On Thu, Jul 09, 2020 at 01:32:53PM +0800, Zhu, Changfeng wrote:
> From: changzhu
>
> From: Changfeng
>
> To avoid s3 faild at the first cycle on renoir platform, it
> needs to revert this patch:
> drm/amd/display: add mechanism to skip DCN init
>
> Change-Id: Idca8933d728531fb68ea2ff00c6c8d77d2a3cdca
> Signed-off-by: changfeng
Ackedy-by: Huang Rui
> ---
> drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +-
> drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 28 +
> drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 2 -
> .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +-
> drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 5 +--
> .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 15 ---
> .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 4 --
> .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 10 +
> .../gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 6 +++
> .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 40 ++-
> 10 files changed, 72 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 67402d75e67e..db5feb89d4af 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -2681,7 +2681,6 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source
> src)
> dal_irq_service_ack(dc->res_pool->irqs, src);
> }
>
> -
> void dc_set_power_state(
> struct dc *dc,
> enum dc_acpi_cm_power_state power_state)
> @@ -2693,6 +2692,9 @@ void dc_set_power_state(
> case DC_ACPI_CM_POWER_STATE_D0:
> dc_resource_state_construct(dc, dc->current_state);
>
> + if (dc->ctx->dmub_srv)
> + dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
> +
> dc->hwss.init_hw(dc);
>
> if (dc->hwss.init_sys_ctx != NULL &&
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
> b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
> index 96532f7ba480..eea2429ac67d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
> +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
> @@ -106,17 +106,29 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv
> *dc_dmub_srv)
> DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
> }
>
> -bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
> +void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
> {
> - struct dmub_srv *dmub;
> - union dmub_fw_boot_status status;
> + struct dmub_srv *dmub = dc_dmub_srv->dmub;
> + struct dc_context *dc_ctx = dc_dmub_srv->ctx;
> + enum dmub_status status;
>
> - if (!dc_dmub_srv || !dc_dmub_srv->dmub)
> - return false;
> + for (;;) {
> + /* Wait up to a second for PHY init. */
> + status = dmub_srv_wait_for_phy_init(dmub, 100);
> + if (status == DMUB_STATUS_OK)
> + /* Initialization OK */
> + break;
>
> - dmub = dc_dmub_srv->dmub;
> + DC_ERROR("DMCUB PHY init failed: status=%d\n", status);
> + ASSERT(0);
>
> - status = dmub->hw_funcs.get_fw_status(dmub);
> + if (status != DMUB_STATUS_TIMEOUT)
> + /*
> + * Server likely initialized or we don't have
> + * DMCUB HW support - this won't end.
> + */
> + break;
>
> - return status.bits.optimized_init_done;
> + /* Continue spinning so we don't hang the ASIC. */
> + }
> }
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
> b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
> index 8bd20d0d7689..a3a09ccb6d26 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
> @@ -56,6 +56,4 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);
>
> void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv);
>
> -bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv);
> -
> #endif /* _DMUB_DC_SRV_H_ */
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index cb45f05a0319..abb160b5c395 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -1288,9 +1288,7 @@ void dcn10_init_hw(struct dc *dc)
> if (!dcb->funcs->is_accelerated_mode(dcb))
> hws->funcs.disable_vga(dc->hwseq);
>
> - if (!dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv))
> - hws->funcs.bios_golden_init(dc);
> -
> + hws->funcs.bios_golden_init(dc);
> if (dc->ctx->dc_bios->fw_info_valid) {
> res_pool->ref_clocks.xtalin_clock_inKhz =
>
> dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
> diff --git
