答复: [PATCH] drm/amd/powerplay: fix typos for clk map
Reviewed-by: Likun Gao
Regards,
Likun
-邮件原件-
发件人: Jiansong Chen [mailto:jiansong.c...@amd.com]
发送时间: 2020年7月21日 12:36
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhou1, Tao ; Feng, Kenneth ; Gao,
Likun ; Chen, Jiansong (Simon)
主题: [PATCH] drm/amd/powerplay: fix typos for clk map
It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0.
Signed-off-by: Jiansong Chen
Change-Id: Ib2239b35840d3774a0e1aa3114d2f965e6d88e7c
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index cae8e776fafe..87eedd7c28ec 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -128,8 +128,8 @@ static struct cmn2asic_mapping
sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(DCLK, PPCLK_DCLK_0),
- CLK_MAP(DCLK1, PPCLK_DCLK_0),
- CLK_MAP(VCLK, PPCLK_VCLK_1),
+ CLK_MAP(DCLK1, PPCLK_DCLK_1),
+ CLK_MAP(VCLK, PPCLK_VCLK_0),
CLK_MAP(VCLK1, PPCLK_VCLK_1),
CLK_MAP(DCEFCLK,PPCLK_DCEFCLK),
CLK_MAP(DISPCLK,PPCLK_DISPCLK),
--
2.17.1
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RE: [PATCH] drm/amd/powerplay: fix typos for clk map
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Tao Zhou
-Original Message-
From: Jiansong Chen
Sent: Tuesday, July 21, 2020 12:36 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Feng, Kenneth ; Gao,
Likun ; Chen, Jiansong (Simon)
Subject: [PATCH] drm/amd/powerplay: fix typos for clk map
It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0.
Signed-off-by: Jiansong Chen
Change-Id: Ib2239b35840d3774a0e1aa3114d2f965e6d88e7c
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index cae8e776fafe..87eedd7c28ec 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -128,8 +128,8 @@ static struct cmn2asic_mapping
sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(UCLK,PPCLK_UCLK),
CLK_MAP(MCLK,PPCLK_UCLK),
CLK_MAP(DCLK,PPCLK_DCLK_0),
-CLK_MAP(DCLK1,PPCLK_DCLK_0),
-CLK_MAP(VCLK,PPCLK_VCLK_1),
+CLK_MAP(DCLK1,PPCLK_DCLK_1),
+CLK_MAP(VCLK,PPCLK_VCLK_0),
CLK_MAP(VCLK1,PPCLK_VCLK_1),
CLK_MAP(DCEFCLK,PPCLK_DCEFCLK),
CLK_MAP(DISPCLK,PPCLK_DISPCLK),
--
2.17.1
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[PATCH] drm/amd/powerplay: add msg map for mode1 reset
From: Likun Gao
Mapping Mode1Reset message for sienna_cichlid.
Signed-off-by: Likun Gao
Change-Id: I9b8d39b10c7723af4589577fdbfa4acd5af6e85d
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index cae8e776fafe..bf3d6bbba930 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -118,6 +118,7 @@ static struct cmn2asic_msg_mapping
sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg,
1),
MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME,
1),
MSG_MAP(ArmD3, PPSMC_MSG_ArmD3,
1),
+ MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset,
1),
};
static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
--
2.25.1
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[PATCH] drm/amd/powerplay: fix typos for clk map
It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0.
Signed-off-by: Jiansong Chen
Change-Id: Ib2239b35840d3774a0e1aa3114d2f965e6d88e7c
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index cae8e776fafe..87eedd7c28ec 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -128,8 +128,8 @@ static struct cmn2asic_mapping
sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(DCLK, PPCLK_DCLK_0),
- CLK_MAP(DCLK1, PPCLK_DCLK_0),
- CLK_MAP(VCLK, PPCLK_VCLK_1),
+ CLK_MAP(DCLK1, PPCLK_DCLK_1),
+ CLK_MAP(VCLK, PPCLK_VCLK_0),
CLK_MAP(VCLK1, PPCLK_VCLK_1),
CLK_MAP(DCEFCLK,PPCLK_DCEFCLK),
CLK_MAP(DISPCLK,PPCLK_DISPCLK),
--
2.17.1
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[PATCH AUTOSEL 5.4 22/34] drm/amdgpu: fix preemption unit test
From: Jack Xiao
[ Upstream commit d845a2051b6b673fab4229b920ea04c7c4352b51 ]
Remove signaled jobs from job list and ensure the
job was indeed preempted.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 1e25ca34d876c..700e26b69abca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -990,27 +990,37 @@ static void amdgpu_ib_preempt_job_recovery(struct
drm_gpu_scheduler *sched)
static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
{
struct amdgpu_job *job;
- struct drm_sched_job *s_job;
+ struct drm_sched_job *s_job, *tmp;
uint32_t preempt_seq;
struct dma_fence *fence, **ptr;
struct amdgpu_fence_driver *drv = >fence_drv;
struct drm_gpu_scheduler *sched = >sched;
+ bool preempted = true;
if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
return;
preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
- if (preempt_seq <= atomic_read(>last_seq))
- return;
+ if (preempt_seq <= atomic_read(>last_seq)) {
+ preempted = false;
+ goto no_preempt;
+ }
preempt_seq &= drv->num_fences_mask;
ptr = >fences[preempt_seq];
fence = rcu_dereference_protected(*ptr, 1);
+no_preempt:
spin_lock(>job_list_lock);
- list_for_each_entry(s_job, >ring_mirror_list, node) {
+ list_for_each_entry_safe(s_job, tmp, >ring_mirror_list, node) {
+ if (dma_fence_is_signaled(_job->s_fence->finished)) {
+ /* remove job from ring_mirror_list */
+ list_del_init(_job->node);
+ sched->ops->free_job(s_job);
+ continue;
+ }
job = to_amdgpu_job(s_job);
- if (job->fence == fence)
+ if (preempted && job->fence == fence)
/* mark the job as preempted */
job->preemption_status |= AMDGPU_IB_PREEMPTED;
}
--
2.25.1
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[PATCH AUTOSEL 5.4 21/34] drm/amdgpu/gfx10: fix race condition for kiq
From: Jack Xiao
[ Upstream commit 7d65a577bb58d4f27a3398a4c0cb0b00ab7d0511 ]
During preemption test for gfx10, it uses kiq to trigger
gfx preemption, which would result in race condition
with flushing TLB for kiq.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Acked-by: Christian König
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 6f118292e40fb..64d96eb0a2337 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4683,12 +4683,17 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring
*ring)
struct amdgpu_device *adev = ring->adev;
struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *kiq_ring = >ring;
+ unsigned long flags;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
- if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
+ spin_lock_irqsave(>ring_lock, flags);
+
+ if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
+ spin_unlock_irqrestore(>ring_lock, flags);
return -ENOMEM;
+ }
/* assert preemption condition */
amdgpu_ring_set_preempt_cond_exec(ring, false);
@@ -4699,6 +4704,8 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring
*ring)
++ring->trail_seq);
amdgpu_ring_commit(kiq_ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
+
/* poll the trailing fence */
for (i = 0; i < adev->usec_timeout; i++) {
if (ring->trail_seq ==
--
2.25.1
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[PATCH AUTOSEL 5.7 27/40] drm/amdgpu: fix preemption unit test
From: Jack Xiao
[ Upstream commit d845a2051b6b673fab4229b920ea04c7c4352b51 ]
Remove signaled jobs from job list and ensure the
job was indeed preempted.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index c0f9a651dc067..92b18c4760e55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1156,27 +1156,37 @@ static void amdgpu_ib_preempt_job_recovery(struct
drm_gpu_scheduler *sched)
static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
{
struct amdgpu_job *job;
- struct drm_sched_job *s_job;
+ struct drm_sched_job *s_job, *tmp;
uint32_t preempt_seq;
struct dma_fence *fence, **ptr;
struct amdgpu_fence_driver *drv = >fence_drv;
struct drm_gpu_scheduler *sched = >sched;
+ bool preempted = true;
if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
return;
preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
- if (preempt_seq <= atomic_read(>last_seq))
- return;
+ if (preempt_seq <= atomic_read(>last_seq)) {
+ preempted = false;
+ goto no_preempt;
+ }
preempt_seq &= drv->num_fences_mask;
ptr = >fences[preempt_seq];
fence = rcu_dereference_protected(*ptr, 1);
+no_preempt:
spin_lock(>job_list_lock);
- list_for_each_entry(s_job, >ring_mirror_list, node) {
+ list_for_each_entry_safe(s_job, tmp, >ring_mirror_list, node) {
+ if (dma_fence_is_signaled(_job->s_fence->finished)) {
+ /* remove job from ring_mirror_list */
+ list_del_init(_job->node);
+ sched->ops->free_job(s_job);
+ continue;
+ }
job = to_amdgpu_job(s_job);
- if (job->fence == fence)
+ if (preempted && job->fence == fence)
/* mark the job as preempted */
job->preemption_status |= AMDGPU_IB_PREEMPTED;
}
--
2.25.1
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[PATCH AUTOSEL 5.7 26/40] drm/amdgpu/gfx10: fix race condition for kiq
From: Jack Xiao
[ Upstream commit 7d65a577bb58d4f27a3398a4c0cb0b00ab7d0511 ]
During preemption test for gfx10, it uses kiq to trigger
gfx preemption, which would result in race condition
with flushing TLB for kiq.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Acked-by: Christian König
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0e0daf0021b60..ff94f756978d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4746,12 +4746,17 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring
*ring)
struct amdgpu_device *adev = ring->adev;
struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *kiq_ring = >ring;
+ unsigned long flags;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
- if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
+ spin_lock_irqsave(>ring_lock, flags);
+
+ if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
+ spin_unlock_irqrestore(>ring_lock, flags);
return -ENOMEM;
+ }
/* assert preemption condition */
amdgpu_ring_set_preempt_cond_exec(ring, false);
@@ -4762,6 +4767,8 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring
*ring)
++ring->trail_seq);
amdgpu_ring_commit(kiq_ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
+
/* poll the trailing fence */
for (i = 0; i < adev->usec_timeout; i++) {
if (ring->trail_seq ==
--
2.25.1
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Re: [Mesa-dev] [XDC 2020] Virtual conference + Call for Proposals extended 2 weeks more
On 7/3/20 4:41 PM, Samuel Iglesias Gonsálvez wrote: > Hi, > > In the last meeting, X.Org Foundation board has decided that XDC 2020 > will be a virtual conference, given the uncertain COVID-19 situation in > Europe by September, including the possibility of a second wave, > outbreaks and travel restrictions, either in Poland or in other > countries. > > XDC 2020 organization team agrees on this decision and it volunteered > to organize our first virtual XDC! > > We would like to announce as well that the new CFP deadline is Sunday > July 19th 2020. Don't forget to submit your talk, demo and workshop > proposals! > As approved in last board's meeting [0], CfP is extended until two weeks before the conference, or until we fill all the slots (whichever happens first). Please submit your talk proposals early! Last two years we had lots of talks about new and fresh development and we prioritized those over other kind of talks, as they had more potential for discussions and hallway track. However, this year that doesn't make too much sense, so we encourage our community to submit any talk related to open-source graphics stack, including those that focus on project status updates. Sam [0] https://www.x.org/wiki/BoardOfDirectors/MeetingSummaries/2020/07-16/ > Thanks, > > Sam > > > ___ > mesa-dev mailing list > mesa-...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > signature.asc Description: OpenPGP digital signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea
Hi, On 7/9/20 2:33 PM, Daniel Vetter wrote: Comes up every few years, gets somewhat tedious to discuss, let's write this down once and for all. What I'm not sure about is whether the text should be more explicit in flat out mandating the amdkfd eviction fences for long running compute workloads or workloads where userspace fencing is allowed. Although (in my humble opinion) it might be possible to completely untangle kernel-introduced fences for resource management and dma-fences used for completion- and dependency tracking and lift a lot of restrictions for the dma-fences, including prohibiting infinite ones, I think this makes sense describing the current state. Reviewed-by: Thomas Hellstrom ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re:
Hi Christian, On Mon, Jul 20, 2020 at 11:00 AM Christian König wrote: > > Hi Mauro, > > I'm not deep into the whole DC design, so just some general high level > comments on the cover letter: > > 1. Please add a subject line to the cover letter, my spam filter thinks > that this is suspicious otherwise. My mistake in the editing of covert letter with git send-email, I may have forgot to keep the Subject at the top > > 2. Then you should probably note how well (badly?) is that tested. Since > you noted proof of concept it might not even work. The Changelog is to be read as: [RFC] was the initial Proof of concept was the RFC and [PATCH v2] was just a rebase onto amd-staging-drm-next this series [PATCH v3] has all the known changes required for DCE6 specificity and based on a long offline thread with Alexander Deutcher and past dri-devel chats with Harry Wentland. It was tested for my possibilities of testing with HD7750 and HD7950, with checks in dmesg output for not getting "missing registers/masks" kernel WARNING and with kernel build on Ubuntu 20.04 and with android-x86 The proposal I made to Alex is that AMD testing systems will be used for further regression testing, as part of review and validation for eligibility to amd-staging-drm-next > > 3. How feature complete (HDMI audio?, Freesync?) is it? All the changes in DC impacting DCE8 (dc/dce80 path) were ported to DCE6 (dc/dce60 path) in the last two years from initial submission > > Apart from that it looks like a rather impressive piece of work :) > > Cheers, > Christian. Thanks, please consider that most of the latest DCE6 specific parts were possible due to recent Alex support in getting the correct DCE6 headers, his suggestions and continuous feedback. I would suggest that Alex comments on the proposed next steps to follow. Mauro > > Am 16.07.20 um 23:22 schrieb Mauro Rossi: > > The series adds SI support to AMD DC > > > > Changelog: > > > > [RFC] > > Preliminar Proof Of Concept, with DCE8 headers still used in > > dce60_resources.c > > > > [PATCH v2] > > Rebase on amd-staging-drm-next dated 17-Oct-2018 > > > > [PATCH v3] > > Add support for DCE6 specific headers, > > ad hoc DCE6 macros, funtions and fixes, > > rebase on current amd-staging-drm-next > > > > > > Commits [01/27]..[08/27] SI support added in various DC components > > > > [PATCH v3 01/27] drm/amdgpu: add some required DCE6 registers (v6) > > [PATCH v3 02/27] drm/amd/display: add asics info for SI parts > > [PATCH v3 03/27] drm/amd/display: dc/dce: add initial DCE6 support (v9b) > > [PATCH v3 04/27] drm/amd/display: dc/core: add SI/DCE6 support (v2) > > [PATCH v3 05/27] drm/amd/display: dc/bios: add support for DCE6 > > [PATCH v3 06/27] drm/amd/display: dc/gpio: add support for DCE6 (v2) > > [PATCH v3 07/27] drm/amd/display: dc/irq: add support for DCE6 (v4) > > [PATCH v3 08/27] drm/amd/display: amdgpu_dm: add SI support (v4) > > > > Commits [09/27]..[24/27] DCE6 specific code adaptions > > > > [PATCH v3 09/27] drm/amd/display: dc/clk_mgr: add support for SI parts (v2) > > [PATCH v3 10/27] drm/amd/display: dc/dce60: set max_cursor_size to 64 > > [PATCH v3 11/27] drm/amd/display: dce_audio: add DCE6 specific > > macros,functions > > [PATCH v3 12/27] drm/amd/display: dce_dmcu: add DCE6 specific macros > > [PATCH v3 13/27] drm/amd/display: dce_hwseq: add DCE6 specific > > macros,functions > > [PATCH v3 14/27] drm/amd/display: dce_ipp: add DCE6 specific > > macros,functions > > [PATCH v3 15/27] drm/amd/display: dce_link_encoder: add DCE6 specific > > macros,functions > > [PATCH v3 16/27] drm/amd/display: dce_mem_input: add DCE6 specific > > macros,functions > > [PATCH v3 17/27] drm/amd/display: dce_opp: add DCE6 specific > > macros,functions > > [PATCH v3 18/27] drm/amd/display: dce_transform: add DCE6 specific > > macros,functions > > [PATCH v3 19/27] drm/amdgpu: add some required DCE6 registers (v7) > > [PATCH v3 20/27] drm/amd/display: dce_transform: DCE6 Scaling Horizontal > > Filter Init > > [PATCH v3 21/27] drm/amd/display: dce60_hw_sequencer: add DCE6 > > macros,functions > > [PATCH v3 22/27] drm/amd/display: dce60_hw_sequencer: add DCE6 specific > > .cursor_lock > > [PATCH v3 23/27] drm/amd/display: dce60_timing_generator: add DCE6 specific > > functions > > [PATCH v3 24/27] drm/amd/display: dc/dce60: use DCE6 headers (v6) > > > > > > Commits [25/27]..[27/27] SI support final enablements > > > > [PATCH v3 25/27] drm/amd/display: create plane rotation property for > > Bonarie and later > > [PATCH v3 26/27] drm/amdgpu: enable DC support for SI parts (v2) > > [PATCH v3 27/27] drm/amd/display: enable SI support in the Kconfig (v2) > > > > > > Signed-off-by: Mauro Rossi > > > > ___ > > amd-gfx mailing list > > amd-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org
Re: Failed to find memory space for buffer eviction
Am 16.07.20 um 19:05 schrieb Felix Kuehling:
Am 2020-07-16 um 2:58 a.m. schrieb Christian König:
Am 15.07.20 um 17:14 schrieb Felix Kuehling:
Am 2020-07-15 um 5:28 a.m. schrieb Christian König:
[SNIP]
What could be problematic and result is an overrun is that TTM was
buggy and called put_node twice for the same memory.
So I've seen that the code needs fixing as well, but I'm not 100%
sure
how you ran into your problem.
This is in the KFD eviction test, which deliberately overcommits
VRAM in
order to trigger lots of evictions. It will use some GTT space
while BOs
are evicted. But shouldn't it move them further out of GTT and into
SYSTEM to free up GTT space?
Yes, exactly that should happen.
But for some reason it couldn't find a candidate to evict and the
14371 pages left are just a bit to small for the buffer.
That would be a nested eviction. A VRAM to GTT eviction requires a GTT
to SYSTEM eviction to make space in GTT. Is that even possible?
Yes, this is the core of the TTM design problem which I talked about
in my FOSDEM presentation in February.
Question do we still have this crude workaround that KFD is not taking
all reservations of the current process when allocating new BOs?
Not sure if you're referring to the workarounds we had to remove
eviction fences from reservations temporarily. Those are all gone. We're
making full use of the sync-object fence owner logic to avoid triggering
eviction fences unintentionally.
I was talking about this check here in amdgpu_ttm_bo_eviction_valuable():
/* If bo is a KFD BO, check if the bo belongs to the current
process.
* If true, then return false as any KFD process needs all its
BOs to
* be resident to run successfully
*/
flist = dma_resv_get_list(bo->base.resv);
if (flist) {
for (i = 0; i < flist->shared_count; ++i) {
f = rcu_dereference_protected(flist->shared[i],
dma_resv_held(bo->base.resv));
if (amdkfd_fence_check_mm(f, current->mm))
return false;
}
}
What can happen is that the allocating process owns to much of GTT as
well and as an end result we can't evict anything from GTT to allow for
VRAM eviction to happen.
I don't know why we would need to take all reservations when we allocate
a new BO. I'm probably misunderstanding you.
Taking all reservations when you change the set of BOs allocated in a
working context is mandatory for correct operation.
I've already noted multiple times that working around like we currently
do is just a hack and what you see here is one of the symptoms of this.
Regards,
Christian.
Regards,
Felix
That could maybe cause this as well.
Regards,
Christian.
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Re:
Hi Mauro, I'm not deep into the whole DC design, so just some general high level comments on the cover letter: 1. Please add a subject line to the cover letter, my spam filter thinks that this is suspicious otherwise. 2. Then you should probably note how well (badly?) is that tested. Since you noted proof of concept it might not even work. 3. How feature complete (HDMI audio?, Freesync?) is it? Apart from that it looks like a rather impressive piece of work :) Cheers, Christian. Am 16.07.20 um 23:22 schrieb Mauro Rossi: The series adds SI support to AMD DC Changelog: [RFC] Preliminar Proof Of Concept, with DCE8 headers still used in dce60_resources.c [PATCH v2] Rebase on amd-staging-drm-next dated 17-Oct-2018 [PATCH v3] Add support for DCE6 specific headers, ad hoc DCE6 macros, funtions and fixes, rebase on current amd-staging-drm-next Commits [01/27]..[08/27] SI support added in various DC components [PATCH v3 01/27] drm/amdgpu: add some required DCE6 registers (v6) [PATCH v3 02/27] drm/amd/display: add asics info for SI parts [PATCH v3 03/27] drm/amd/display: dc/dce: add initial DCE6 support (v9b) [PATCH v3 04/27] drm/amd/display: dc/core: add SI/DCE6 support (v2) [PATCH v3 05/27] drm/amd/display: dc/bios: add support for DCE6 [PATCH v3 06/27] drm/amd/display: dc/gpio: add support for DCE6 (v2) [PATCH v3 07/27] drm/amd/display: dc/irq: add support for DCE6 (v4) [PATCH v3 08/27] drm/amd/display: amdgpu_dm: add SI support (v4) Commits [09/27]..[24/27] DCE6 specific code adaptions [PATCH v3 09/27] drm/amd/display: dc/clk_mgr: add support for SI parts (v2) [PATCH v3 10/27] drm/amd/display: dc/dce60: set max_cursor_size to 64 [PATCH v3 11/27] drm/amd/display: dce_audio: add DCE6 specific macros,functions [PATCH v3 12/27] drm/amd/display: dce_dmcu: add DCE6 specific macros [PATCH v3 13/27] drm/amd/display: dce_hwseq: add DCE6 specific macros,functions [PATCH v3 14/27] drm/amd/display: dce_ipp: add DCE6 specific macros,functions [PATCH v3 15/27] drm/amd/display: dce_link_encoder: add DCE6 specific macros,functions [PATCH v3 16/27] drm/amd/display: dce_mem_input: add DCE6 specific macros,functions [PATCH v3 17/27] drm/amd/display: dce_opp: add DCE6 specific macros,functions [PATCH v3 18/27] drm/amd/display: dce_transform: add DCE6 specific macros,functions [PATCH v3 19/27] drm/amdgpu: add some required DCE6 registers (v7) [PATCH v3 20/27] drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init [PATCH v3 21/27] drm/amd/display: dce60_hw_sequencer: add DCE6 macros,functions [PATCH v3 22/27] drm/amd/display: dce60_hw_sequencer: add DCE6 specific .cursor_lock [PATCH v3 23/27] drm/amd/display: dce60_timing_generator: add DCE6 specific functions [PATCH v3 24/27] drm/amd/display: dc/dce60: use DCE6 headers (v6) Commits [25/27]..[27/27] SI support final enablements [PATCH v3 25/27] drm/amd/display: create plane rotation property for Bonarie and later [PATCH v3 26/27] drm/amdgpu: enable DC support for SI parts (v2) [PATCH v3 27/27] drm/amd/display: enable SI support in the Kconfig (v2) Signed-off-by: Mauro Rossi ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Amdgpu kernel oops and freezing graphics
Jack first, thanks for the answer > RX 5500m only has win10 support. I have seen that (well - too late, I admit). But I would be perfectly happy with the processor graphics of the 4800U. I bought the laptop because of the 17 inch display in first place. If there would be a way just to switch the 5500m off that would be perfectly enogh. I'm not a gamer... But AFAIK there is no way to do this without the kernel oopsing. I thought it would be possible to make the machine usable at least... Greetings Harvey -- I am root. If you see me laughing, you'd better have a backup! ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Amdgpu kernel oops and freezing graphics
Hello, this is my first post to this list so please be patient with me ;) The facts: it is now one week that I own a new laptop, a MSI Bravo 17 A4DDR/MS-17FK with Ryzen 7 4800U and hybrid graphics on a Radeon RX 5500M. I installed my beloved Archlinux but I can't start any graphics withpout kernel oops on it beside the normal console, even calling 'lspci' on the console is provoking errors. I am using linux kernel 5.7.9 and linux-firmware 20200619.e96c121 (FWIW: I even tried with a self-cmpiled kernel 5.8-rc5 and linux-firmware directly from the git repository - no changes) The following is only part of the information I can provide but I didn't want to make this mail bigger than it already is. the lspci -k output is: 00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir Root Complex Subsystem: Advanced Micro Devices, Inc. [AMD] Renoir Root Complex 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Renoir IOMMU Subsystem: Advanced Micro Devices, Inc. [AMD] Renoir IOMMU 00:01.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe Dummy Host Bridge 00:01.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe GPP Bridge Kernel driver in use: pcieport 00:02.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe Dummy Host Bridge 00:02.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe GPP Bridge Kernel driver in use: pcieport 00:02.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe GPP Bridge Kernel driver in use: pcieport 00:08.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe Dummy Host Bridge 00:08.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir Internal PCIe GPP Bridge to Bus Kernel driver in use: pcieport 00:08.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir Internal PCIe GPP Bridge to Bus Kernel driver in use: pcieport 00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller (rev 51) Subsystem: Micro-Star International Co., Ltd. [MSI] Device 12ac Kernel driver in use: piix4_smbus Kernel modules: i2c_piix4, sp5100_tco 00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge (rev 51) Subsystem: Micro-Star International Co., Ltd. [MSI] Device 12ac 00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir Device 24: Function 0 00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir Device 24: Function 1 00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir Device 24: Function 2 00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir Device 24: Function 3 Kernel driver in use: k10temp Kernel modules: k10temp 00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir Device 24: Function 4 00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir Device 24: Function 5 00:18.6 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir Device 24: Function 6 00:18.7 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir Device 24: Function 7 01:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Upstream Port of PCI Express Switch (rev c1) Kernel driver in use: pcieport 02:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Downstream Port of PCI Express Switch Kernel driver in use: pcieport 03:00.0 Display controller: Advanced Micro Devices, Inc. [AMD/ATI] Navi 14 [Radeon RX 5500/5500M / Pro 5500M] (rev c1) Subsystem: Micro-Star International Co., Ltd. [MSI] Device 12ac Kernel driver in use: amdgpu Kernel modules: amdgpu 03:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 HDMI Audio Subsystem: Micro-Star International Co., Ltd. [MSI] Device 12ac Kernel driver in use: snd_hda_intel Kernel modules: snd_hda_intel 04:00.0 Network controller: Intel Corporation Wi-Fi 6 AX200 (rev 1a) Subsystem: Intel Corporation Device 0084 Kernel driver in use: iwlwifi Kernel modules: iwlwifi 05:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15) Subsystem: Micro-Star International Co., Ltd. [MSI] Device 12ac Kernel driver in use: r8169 Kernel modules: r8169 06:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Renoir (rev c6) Subsystem: Micro-Star International Co., Ltd. [MSI] Device 12ac Kernel driver in use: amdgpu Kernel modules: amdgpu 06:00.2 Encryption controller: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 10h-1fh) Platform Security Processor Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 10h-1fh) Platform Security Processor Kernel driver in use: ccp Kernel modules: ccp 06:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Renoir USB 3.1 Subsystem: Micro-Star International Co., Ltd. [MSI] Device 12ac Kernel driver in use: xhci_hcd
RE: [PATCH] drm/amdgpu: add printing after executing page reservation to eeprom
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Tao Zhou
-Original Message-
From: Chen, Guchun
Sent: Monday, July 20, 2020 11:16 AM
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; Li,
Dennis ; Yang, Stanley ; Zhou1, Tao
; Clements, John
Cc: Chen, Guchun
Subject: [PATCH] drm/amdgpu: add printing after executing page reservation to
eeprom
This will tell users if the faulty page has been written to external eeprom
device in dmesg log.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 6f06e1214622..4a82a587de28 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1622,7 +1622,7 @@ static int amdgpu_ras_save_bad_pages(struct amdgpu_device
*adev)
data = con->eh_data;
save_count = data->count - control->num_recs;
/* only new entries are saved */
-if (save_count > 0)
+if (save_count > 0) {
if (amdgpu_ras_eeprom_process_recods(control,
>bps[control->num_recs],
true,
@@ -1631,6 +1631,9 @@ static int amdgpu_ras_save_bad_pages(struct amdgpu_device
*adev)
return -EIO;
}
+dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
+}
+
return 0;
}
--
2.17.1
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