RE: [PATCH 1/1] drm/amdgpu: rework ip block reinit for sriov
[AMD Official Use Only - Internal Distribution Only]
Hi Nirmoy,
Still think the original logical is more clear.
Best wishes
Emily Deng
>-Original Message-
>From: Das, Nirmoy
>Sent: Thursday, August 27, 2020 11:19 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deucher, Alexander ; Liu, Monk
>; Gu, JiaWei (Will) ; Deng, Emily
>; Das, Nirmoy
>Subject: [PATCH 1/1] drm/amdgpu: rework ip block reinit for sriov
>
>This patch removes some unwanted code duplication and simplifies sriov's ip
>block reinit logic.
>
>Signed-off-by: Nirmoy Das
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 117 +++--
> 1 file changed, 60 insertions(+), 57 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>index 696a61cc3ac6..0db6db03bcd3 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>@@ -2587,77 +2587,80 @@ int amdgpu_device_ip_suspend(struct
>amdgpu_device *adev)
> return r;
> }
>
>-static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
>+/** amdgpu_device_is_early_ip_block_sriov - check for early ip_blocks
>+ *
>+ * @ip_block: ip block that need to be check
>+ *
>+ * Returns a tri-state value for a given ip block.
>+ * If an ip block requires early reinit sriov then return 1 or 0 otherwise.
>+ * Return -1 on invalid ip block.
>+ *
>+ */
>+
>+static int
>+amdgpu_device_is_early_ip_block_sriov(const enum amd_ip_block_type
>+ip_block)
> {
>-int i, r;
>+switch (ip_block) {
>+/* early ip blocks */
>+case AMD_IP_BLOCK_TYPE_GMC:
>+case AMD_IP_BLOCK_TYPE_COMMON:
>+case AMD_IP_BLOCK_TYPE_PSP:
>+case AMD_IP_BLOCK_TYPE_IH:
>+return 1;
>+/* late ip blocks */
>+case AMD_IP_BLOCK_TYPE_SMC:
>+case AMD_IP_BLOCK_TYPE_DCE:
>+case AMD_IP_BLOCK_TYPE_GFX:
>+case AMD_IP_BLOCK_TYPE_SDMA:
>+case AMD_IP_BLOCK_TYPE_UVD:
>+case AMD_IP_BLOCK_TYPE_VCE:
>+case AMD_IP_BLOCK_TYPE_VCN:
>+return 0;
>+/* invalid ip block */
>+default:
>+return -1;
>+}
>+}
>
>-static enum amd_ip_block_type ip_order[] = {
>-AMD_IP_BLOCK_TYPE_GMC,
>-AMD_IP_BLOCK_TYPE_COMMON,
>-AMD_IP_BLOCK_TYPE_PSP,
>-AMD_IP_BLOCK_TYPE_IH,
>-};
>+static int amdgpu_device_ip_reinit_sriov(struct amdgpu_device *adev,
>+ const int is_early)
>+{
>+int i;
>
> for (i = 0; i < adev->num_ip_blocks; i++) {
>-int j;
>+int r = 0;
>+bool init_ip;
> struct amdgpu_ip_block *block;
>+enum amd_ip_block_type ip_block;
>
> block = >ip_blocks[i];
> block->status.hw = false;
>+ip_block = block->version->type;
>+init_ip = (is_early ==
>+ amdgpu_device_is_early_ip_block_sriov(ip_block));
>
>-for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
>-
>-if (block->version->type != ip_order[j] ||
>-!block->status.valid)
>-continue;
>+if (!init_ip ||
>+(!is_early && block->status.hw) ||
>+!block->status.valid)
>+continue;
>
>-r = block->version->funcs->hw_init(adev);
>-DRM_INFO("RE-INIT-early: %s %s\n", block->version-
>>funcs->name, r?"failed":"succeeded");
>-if (r)
>-return r;
>-block->status.hw = true;
>+if (init_ip && (ip_block == AMD_IP_BLOCK_TYPE_SMC)) {
>+r = block->version->funcs->resume(adev);
>+goto show_log;
> }
>-}
>-
>-return 0;
>-}
>
>-static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) -{
>-int i, r;
>-
>-static enum amd_ip_block_type ip_order[] = {
>-AMD_IP_BLOCK_TYPE_SMC,
>-AMD_IP_BLOCK_TYPE_DCE,
>-AMD_IP_BLOCK_TYPE_GFX,
>-AMD_IP_BLOCK_TYPE_SDMA,
>-AMD_IP_BLOCK_TYPE_UVD,
>-AMD_IP_BLOCK_TYPE_VCE,
>-AMD_IP_BLOCK_TYPE_VCN
>-};
>-
>-for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
>-int j;
>-struct amdgpu_ip_block *block;
>+if (init_ip)
>+r = block->version->funcs->hw_init(adev);
>
>-for (j = 0; j < adev->num_ip_blocks; j++) {
>-block = >ip_blocks[j];
>+show_log:
>+DRM_INFO("RE-INIT-%s: %s %s\n", is_early ? "early":"late",
>+ block->version->funcs->name, r ?
>"failed":"succeeded");
>
>-if (block->version->type != ip_order[i] ||
>-!block->status.valid ||
>-block->status.hw)
>-continue;
>+if (r)
>+return r;
>
>-if (block->version->type ==
>AMD_IP_BLOCK_TYPE_SMC)
>-r = block->version->funcs->resume(adev);
>-else
>-r = block->version->funcs->hw_init(adev);
>+block->status.hw = true;
>
>-DRM_INFO("RE-INIT-late: %s %s\n", block->version-
>>funcs->name, r?"failed":"succeeded");
>-if (r)
>-return r;
>-block->status.hw = true;
>-}
> }
>
> return 0;
>@@ -3901,7 +3904,7 @@ static int amdgpu_device_reset_sriov(struct
>amdgpu_device *adev,
> amdgpu_amdkfd_pre_reset(adev);
>
> /* Resume IP prior to SMC */
>-r = amdgpu_device_ip_reinit_early_sriov(adev);
>+r = amdgpu_device_ip_reinit_sriov(adev, 1);
> if (r)
> goto error;
>
>@@ -3914,7 +3917,7 @@ static int amdgpu_device_reset_sriov(struct
>amdgpu_device *adev,
> return r;
>
> /* now we are okay to resume SMC/CP/SDMA */
>-r = amdgpu_device_ip_reinit_late_sriov(adev);
>+r = amdgpu_device_ip_reinit_sriov(adev, 0);
> if (r)
> goto error;
>
>--
>2.28.0
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Re: [PATCH 5/7] drm/amdgpu: Fix consecutive DPC recoveries failure.
Ping
Andrey
From: amd-gfx on behalf of Andrey
Grodzovsky
Sent: 27 August 2020 10:54
To: Alex Deucher
Cc: Deucher, Alexander ; Das, Nirmoy
; amd-gfx list
Subject: Re: [PATCH 5/7] drm/amdgpu: Fix consecutive DPC recoveries failure.
On 8/26/20 11:20 AM, Alex Deucher wrote:
> On Wed, Aug 26, 2020 at 10:46 AM Andrey Grodzovsky
> wrote:
>> DPC recovery after prev. DPC recovery or after prev. MODE1 reset fails
>> unles you save the cashe the saved PCI confspace to load it after
>> each new reset.
>> Also use same cached state for other use case of restoring PCI confspace
>> such as GPU mode1 or VGA switheroo.
>>
> We don't want to keep the saved state around in the pci core
> otherwise, the pci core will assume we are managing the saved state
> for suspend and resume. I think we want logic like this:
>
> At driver load time:
> pci_save_state(pdev);
> adev->pci_state = pci_store_saved_state(pdev);
> pci_restore_state(adev->pdev);
>
> then in the case of dpc, do:
> pci_load_saved_state(pdev, adev->pci_state);
>
> For all the other cases, just leave the code as is.
Actually, as we already discussed - caching the PCI confspace only once on boot
and not doing it again after each subsequent
controlled or spontaneous reset runs the risk of loading back outdated confspace
settings. I am not sure if and when but, is it indeed
possible we make changes to PCI confspace registers during runtime and so the
cached state from boot might be outdated
to load back ?
Andrey
>
> Alex
>
>
>> Signed-off-by: Andrey Grodzovsky
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 6 +++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 60
>> +++---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 4 +-
>> drivers/gpu/drm/amd/amdgpu/nv.c| 4 +-
>> drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +-
>> 5 files changed, 66 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 3489622..42ee208 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -992,7 +992,9 @@ struct amdgpu_device {
>> atomic_tthrottling_logging_enabled;
>> struct ratelimit_state throttling_logging_rs;
>> uint32_tras_features;
>> +
> Unrelated whitespace changes.
>
>> boolin_dpc;
>> + struct pci_saved_state *pci_state;
>> };
>>
>> static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
>> @@ -1272,6 +1274,10 @@ pci_ers_result_t amdgpu_pci_mmio_enabled(struct
>> pci_dev *pdev);
>> pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
>> void amdgpu_pci_resume(struct pci_dev *pdev);
>>
>> +bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
>> +bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
>> +
>> +
>>
>> #include "amdgpu_object.h"
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index d9e3994..2c088df 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -1283,7 +1283,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev
>> *pdev,
>> dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
>>
>> pci_set_power_state(dev->pdev, PCI_D0);
>> - pci_restore_state(dev->pdev);
>> + amdgpu_device_load_pci_state(dev->pdev);
>> r = pci_enable_device(dev->pdev);
>> if (r)
>> DRM_WARN("pci_enable_device failed (%d)\n", r);
>> @@ -1296,7 +1296,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev
>> *pdev,
>> drm_kms_helper_poll_disable(dev);
>> dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
>> amdgpu_device_suspend(dev, true);
>> - pci_save_state(dev->pdev);
>> + amdgpu_device_cache_pci_state(dev->pdev);
>> /* Shut down the device */
>> pci_disable_device(dev->pdev);
>> pci_set_power_state(dev->pdev, PCI_D3cold);
>> @@ -3401,8 +3401,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>> if (r)
>> dev_err(adev->dev, "amdgpu_pmu_init failed\n");
>>
>> - if (pci_save_state(pdev))
>> - DRM_ERROR("Failed to save PCI state!!\n");
>> + /* Have stored pci confspace at hand for restore in sudden PCI error
>> */
>> + if (!amdgpu_device_cache_pci_state(adev->pdev))
>> + DRM_WARN("Failed to cache PCI state!");
>>
>> return 0;
>>
>> @@ -3430,6 +3431,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
>> flush_delayed_work(>delayed_init_work);
>> adev->shutdown = true;
>>
>> +
[PATCH][next] drm/amdgpu/swsmu: fix potential uint32_t multiplication overflow
From: Colin Ian King
The calculation of tmp64 is performed using a 32 bit multiply and then
is stored in the uint64_t variable tmp64. This indicates that a 64 bit
result may be expected, so cast crystal_clock_freq to a uint64_t
to ensure a 64 bit multiplication is being performed to avoid any
potential 32 bit overflow.
Addresses-Coverity: ("Unintentional integer overflow)"
Fixes: 13819ef6453c ("drm/amdgpu/swsmu: add smu11 helpers to get manual fan
speeds")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index d2a15e6f48be..0a5161d09722 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1218,7 +1218,7 @@ int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
crystal_clock_freq = amdgpu_asic_get_xclk(adev);
- tmp64 = 60 * crystal_clock_freq * 1;
+ tmp64 = (uint64_t)crystal_clock_freq * 60 * 1;
do_div(tmp64, (tach_period * 8));
*speed = (uint32_t)tmp64;
--
2.27.0
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Re: [PATCH 1/1] drm/amdgpu: fix compiler warnings
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Alex Deucher
From: Das, Nirmoy
Sent: Thursday, August 27, 2020 11:58 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Das, Nirmoy
Subject: [PATCH 1/1] drm/amdgpu: fix compiler warnings
Fixes below compiler warnings:
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:381:1: warning: ‘static’ is not at
beginning of declaration [-Wold-style-declaration]
381 | void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev,
uint32_t reg, uint32_t v, uint32_t acc_flags)
| ^~~~
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:381:1: warning: ‘inline’ is not at
beginning of declaration [-Wold-style-declaration]
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c: In function ‘amdgpu_device_fini’:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3381:6: warning: variable ‘r’ set
but not used [-Wunused-but-set-variable]
3381 | int r;
| ^
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 696a61cc3ac6..6518e444bead 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -378,7 +378,9 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t
offset, uint8_t value)
BUG();
}
-void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t
reg, uint32_t v, uint32_t acc_flags)
+static inline void amdgpu_mm_wreg_mmio(struct amdgpu_device *adev,
+ uint32_t reg, uint32_t v,
+ uint32_t acc_flags)
{
trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
@@ -3378,8 +3380,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
*/
void amdgpu_device_fini(struct amdgpu_device *adev)
{
- int r;
-
dev_info(adev->dev, "amdgpu: finishing device.\n");
flush_delayed_work(>delayed_init_work);
adev->shutdown = true;
@@ -3402,7 +3402,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
if (adev->pm_sysfs_en)
amdgpu_pm_sysfs_fini(adev);
amdgpu_fbdev_fini(adev);
- r = amdgpu_device_ip_fini(adev);
+ amdgpu_device_ip_fini(adev);
release_firmware(adev->firmware.gpu_info_fw);
adev->firmware.gpu_info_fw = NULL;
adev->accel_working = false;
--
2.28.0
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Re: 0001-Fix-a-array-bound-overflow-bug-in-function-umr_clock
isn't a better fix to simply delete the line? The print seems redundant to me. Tom On Thu, Aug 27, 2020 at 9:27 AM 张二东 wrote: > > > > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/1] drm/amdgpu: fix compiler warnings
Fixes below compiler warnings:
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:381:1: warning: ‘static’ is not at
beginning of declaration [-Wold-style-declaration]
381 | void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev,
uint32_t reg, uint32_t v, uint32_t acc_flags)
| ^~~~
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:381:1: warning: ‘inline’ is not at
beginning of declaration [-Wold-style-declaration]
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c: In function ‘amdgpu_device_fini’:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3381:6: warning: variable ‘r’ set
but not used [-Wunused-but-set-variable]
3381 | int r;
| ^
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 696a61cc3ac6..6518e444bead 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -378,7 +378,9 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t
offset, uint8_t value)
BUG();
}
-void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t
reg, uint32_t v, uint32_t acc_flags)
+static inline void amdgpu_mm_wreg_mmio(struct amdgpu_device *adev,
+ uint32_t reg, uint32_t v,
+ uint32_t acc_flags)
{
trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
@@ -3378,8 +3380,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
*/
void amdgpu_device_fini(struct amdgpu_device *adev)
{
- int r;
-
dev_info(adev->dev, "amdgpu: finishing device.\n");
flush_delayed_work(>delayed_init_work);
adev->shutdown = true;
@@ -3402,7 +3402,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
if (adev->pm_sysfs_en)
amdgpu_pm_sysfs_fini(adev);
amdgpu_fbdev_fini(adev);
- r = amdgpu_device_ip_fini(adev);
+ amdgpu_device_ip_fini(adev);
release_firmware(adev->firmware.gpu_info_fw);
adev->firmware.gpu_info_fw = NULL;
adev->accel_working = false;
--
2.28.0
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[PATCH 1/1] drm/amdgpu: rework ip block reinit for sriov
This patch removes some unwanted code duplication and
simplifies sriov's ip block reinit logic.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 117 +++--
1 file changed, 60 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 696a61cc3ac6..0db6db03bcd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2587,77 +2587,80 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
return r;
}
-static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
+/** amdgpu_device_is_early_ip_block_sriov - check for early ip_blocks
+ *
+ * @ip_block: ip block that need to be check
+ *
+ * Returns a tri-state value for a given ip block.
+ * If an ip block requires early reinit sriov then return 1 or 0 otherwise.
+ * Return -1 on invalid ip block.
+ *
+ */
+
+static int
+amdgpu_device_is_early_ip_block_sriov(const enum amd_ip_block_type ip_block)
{
- int i, r;
+ switch (ip_block) {
+ /* early ip blocks */
+ case AMD_IP_BLOCK_TYPE_GMC:
+ case AMD_IP_BLOCK_TYPE_COMMON:
+ case AMD_IP_BLOCK_TYPE_PSP:
+ case AMD_IP_BLOCK_TYPE_IH:
+ return 1;
+ /* late ip blocks */
+ case AMD_IP_BLOCK_TYPE_SMC:
+ case AMD_IP_BLOCK_TYPE_DCE:
+ case AMD_IP_BLOCK_TYPE_GFX:
+ case AMD_IP_BLOCK_TYPE_SDMA:
+ case AMD_IP_BLOCK_TYPE_UVD:
+ case AMD_IP_BLOCK_TYPE_VCE:
+ case AMD_IP_BLOCK_TYPE_VCN:
+ return 0;
+ /* invalid ip block */
+ default:
+ return -1;
+ }
+}
- static enum amd_ip_block_type ip_order[] = {
- AMD_IP_BLOCK_TYPE_GMC,
- AMD_IP_BLOCK_TYPE_COMMON,
- AMD_IP_BLOCK_TYPE_PSP,
- AMD_IP_BLOCK_TYPE_IH,
- };
+static int amdgpu_device_ip_reinit_sriov(struct amdgpu_device *adev,
+const int is_early)
+{
+ int i;
for (i = 0; i < adev->num_ip_blocks; i++) {
- int j;
+ int r = 0;
+ bool init_ip;
struct amdgpu_ip_block *block;
+ enum amd_ip_block_type ip_block;
block = >ip_blocks[i];
block->status.hw = false;
+ ip_block = block->version->type;
+ init_ip = (is_early ==
+ amdgpu_device_is_early_ip_block_sriov(ip_block));
- for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
-
- if (block->version->type != ip_order[j] ||
- !block->status.valid)
- continue;
+ if (!init_ip ||
+ (!is_early && block->status.hw) ||
+ !block->status.valid)
+ continue;
- r = block->version->funcs->hw_init(adev);
- DRM_INFO("RE-INIT-early: %s %s\n",
block->version->funcs->name, r?"failed":"succeeded");
- if (r)
- return r;
- block->status.hw = true;
+ if (init_ip && (ip_block == AMD_IP_BLOCK_TYPE_SMC)) {
+ r = block->version->funcs->resume(adev);
+ goto show_log;
}
- }
-
- return 0;
-}
-static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
-{
- int i, r;
-
- static enum amd_ip_block_type ip_order[] = {
- AMD_IP_BLOCK_TYPE_SMC,
- AMD_IP_BLOCK_TYPE_DCE,
- AMD_IP_BLOCK_TYPE_GFX,
- AMD_IP_BLOCK_TYPE_SDMA,
- AMD_IP_BLOCK_TYPE_UVD,
- AMD_IP_BLOCK_TYPE_VCE,
- AMD_IP_BLOCK_TYPE_VCN
- };
-
- for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
- int j;
- struct amdgpu_ip_block *block;
+ if (init_ip)
+ r = block->version->funcs->hw_init(adev);
- for (j = 0; j < adev->num_ip_blocks; j++) {
- block = >ip_blocks[j];
+show_log:
+ DRM_INFO("RE-INIT-%s: %s %s\n", is_early ? "early":"late",
+block->version->funcs->name, r ? "failed":"succeeded");
- if (block->version->type != ip_order[i] ||
- !block->status.valid ||
- block->status.hw)
- continue;
+ if (r)
+ return r;
- if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
- r = block->version->funcs->resume(adev);
- else
- r = block->version->funcs->hw_init(adev);
+ block->status.hw = true;
-
Re: [PATCH 5/7] drm/amdgpu: Fix consecutive DPC recoveries failure.
On 8/26/20 11:20 AM, Alex Deucher wrote:
On Wed, Aug 26, 2020 at 10:46 AM Andrey Grodzovsky
wrote:
DPC recovery after prev. DPC recovery or after prev. MODE1 reset fails
unles you save the cashe the saved PCI confspace to load it after
each new reset.
Also use same cached state for other use case of restoring PCI confspace
such as GPU mode1 or VGA switheroo.
We don't want to keep the saved state around in the pci core
otherwise, the pci core will assume we are managing the saved state
for suspend and resume. I think we want logic like this:
At driver load time:
pci_save_state(pdev);
adev->pci_state = pci_store_saved_state(pdev);
pci_restore_state(adev->pdev);
then in the case of dpc, do:
pci_load_saved_state(pdev, adev->pci_state);
For all the other cases, just leave the code as is.
Actually, as we already discussed - caching the PCI confspace only once on boot
and not doing it again after each subsequent
controlled or spontaneous reset runs the risk of loading back outdated confspace
settings. I am not sure if and when but, is it indeed
possible we make changes to PCI confspace registers during runtime and so the
cached state from boot might be outdated
to load back ?
Andrey
Alex
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 6 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 60 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 4 +-
drivers/gpu/drm/amd/amdgpu/nv.c| 4 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +-
5 files changed, 66 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3489622..42ee208 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -992,7 +992,9 @@ struct amdgpu_device {
atomic_tthrottling_logging_enabled;
struct ratelimit_state throttling_logging_rs;
uint32_tras_features;
+
Unrelated whitespace changes.
boolin_dpc;
+ struct pci_saved_state *pci_state;
};
static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
@@ -1272,6 +1274,10 @@ pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev
*pdev);
pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
void amdgpu_pci_resume(struct pci_dev *pdev);
+bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
+bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
+
+
#include "amdgpu_object.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d9e3994..2c088df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1283,7 +1283,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev
*pdev,
dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
pci_set_power_state(dev->pdev, PCI_D0);
- pci_restore_state(dev->pdev);
+ amdgpu_device_load_pci_state(dev->pdev);
r = pci_enable_device(dev->pdev);
if (r)
DRM_WARN("pci_enable_device failed (%d)\n", r);
@@ -1296,7 +1296,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev
*pdev,
drm_kms_helper_poll_disable(dev);
dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
amdgpu_device_suspend(dev, true);
- pci_save_state(dev->pdev);
+ amdgpu_device_cache_pci_state(dev->pdev);
/* Shut down the device */
pci_disable_device(dev->pdev);
pci_set_power_state(dev->pdev, PCI_D3cold);
@@ -3401,8 +3401,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
if (r)
dev_err(adev->dev, "amdgpu_pmu_init failed\n");
- if (pci_save_state(pdev))
- DRM_ERROR("Failed to save PCI state!!\n");
+ /* Have stored pci confspace at hand for restore in sudden PCI error */
+ if (!amdgpu_device_cache_pci_state(adev->pdev))
+ DRM_WARN("Failed to cache PCI state!");
return 0;
@@ -3430,6 +3431,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
flush_delayed_work(>delayed_init_work);
adev->shutdown = true;
+ kfree(adev->pci_state);
+
/* make sure IB test finished before entering exclusive mode
* to avoid preemption on IB test
* */
@@ -4855,7 +4858,7 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev
*pdev)
/* wait for asic to come out of reset */
msleep(500);
- pci_restore_state(pdev);
+ amdgpu_device_load_pci_state(pdev);
/* confirm ASIC came out of reset */
for (i = 0; i < adev->usec_timeout; i++) {
@@ -4934,8 +4937,10 @@ pci_ers_result_t
Re: [PATCH] drm/amd/display: Fix memory leak in amdgpu_dm_mode_config_init()
> When amdgpu_display_modeset_create_props() fails, state and
> state->context should be freed to prevent memleak. It's the
> same when amdgpu_dm_audio_init() fails.
* Can another imperative wording become helpful for the change description?
* Would you like to consider the tag “Fixes” for the commit message?
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c?id=08572451b4b1783fdff787b0188c4d50fdf96b81
…
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2834,12 +2834,18 @@ static int amdgpu_dm_mode_config_init(struct
> amdgpu_device *adev)
> _atomic_state_funcs);
>
> r = amdgpu_display_modeset_create_props(adev);
> - if (r)
> + if (r) {
> + dc_release_state(state->context);
> + kfree(state);
> return r;
> + }
>
> r = amdgpu_dm_audio_init(adev);
> - if (r)
> + if (r) {
> + dc_release_state(state->context);
> + kfree(state);
> return r;
> + }
>
> return 0;
> }
I imagine that the exception handling code can be improved another bit
for this function implementation.
How do you think about to avoid such duplicate source code?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst?id=15bc20c6af4ceee97a1f90b43c0e386643c071b4#n475
Regards,
Markus
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Re: [PATCH] drm/radeon: Prefer lower feedback dividers
Applied. Thanks!
Alex
On Thu, Aug 27, 2020 at 7:18 AM Christian König
wrote:
>
> Am 25.08.20 um 19:33 schrieb Kai-Heng Feng:
> > Commit 2e26ccb119bd ("drm/radeon: prefer lower reference dividers")
> > fixed screen flicker for HP Compaq nx9420 but breaks other laptops like
> > Asus X50SL.
> >
> > Turns out we also need to favor lower feedback dividers.
>
> Mhm, let's hope that this works out for all others as well :)
>
> >
> > Users confirmed this change fixes the regression and doesn't regress the
> > original fix.
> >
> > Fixes: 2e26ccb119bd ("drm/radeon: prefer lower reference dividers")
> > BugLink: https://bugs.launchpad.net/bugs/1791312
> > BugLink: https://bugs.launchpad.net/bugs/1861554
> > Signed-off-by: Kai-Heng Feng
>
> Reviewed-by: Christian König
>
> > ---
> > drivers/gpu/drm/radeon/radeon_display.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_display.c
> > b/drivers/gpu/drm/radeon/radeon_display.c
> > index e0ae911ef427..7b69d6dfe44a 100644
> > --- a/drivers/gpu/drm/radeon/radeon_display.c
> > +++ b/drivers/gpu/drm/radeon/radeon_display.c
> > @@ -933,7 +933,7 @@ static void avivo_get_fb_ref_div(unsigned nom, unsigned
> > den, unsigned post_div,
> >
> > /* get matching reference and feedback divider */
> > *ref_div = min(max(den/post_div, 1u), ref_div_max);
> > - *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
> > + *fb_div = max(nom * *ref_div * post_div / den, 1u);
> >
> > /* limit fb divider to its maximum */
> > if (*fb_div > fb_div_max) {
>
> ___
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> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [PATCH 1/7] drm/amdgpu: Implement DPC recovery
Indeed, I noticed it later and did it in patch 6 (merging 1 and 6 was very messy
due to following changes so I just kept it as a separate patch).
Andrey
On 8/26/20 9:23 PM, Li, Dennis wrote:
[AMD Official Use Only - Internal Distribution Only]
Hi, Andrey,
I found that the sequences of amdgpu_pci_slot_reset is mostly similar to
amdgpu_do_asic_reset. Could help us refactor them to reuse more codes?
Best Regards
Dennis Li
-Original Message-
From: amd-gfx On Behalf Of Andrey
Grodzovsky
Sent: Wednesday, August 26, 2020 10:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Grodzovsky, Andrey
; Das, Nirmoy
Subject: [PATCH 1/7] drm/amdgpu: Implement DPC recovery
Add DPC handlers with basic recovery functionality.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 9 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 181 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 9 +-
3 files changed, 196 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 49ea9fa..3399242 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -49,6 +49,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -1263,6 +1265,13 @@ static inline int amdgpu_dm_display_resume(struct
amdgpu_device *adev) { return void amdgpu_register_gpu_instance(struct
amdgpu_device *adev); void amdgpu_unregister_gpu_instance(struct amdgpu_device
*adev);
+pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
+ pci_channel_state_t state);
+pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
+pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); void
+amdgpu_pci_resume(struct pci_dev *pdev);
+
+
#include "amdgpu_object.h"
/* used by df_v3_6.c and amdgpu_pmu.c */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5a948ed..84f8d14 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -350,7 +350,9 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev,
uint32_t reg,
*
* Returns the 8 bit value from the offset specified.
*/
-uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
+uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
+
if (offset < adev->rmmio_size)
return (readb(adev->rmmio + offset));
BUG();
@@ -371,7 +373,9 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev,
uint32_t offset) {
*
* Writes the value specified to the offset specified.
*/
-void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t
value) {
+void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset,
+uint8_t value) {
+
if (offset < adev->rmmio_size)
writeb(value, adev->rmmio + offset);
else
@@ -380,6 +384,7 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t
offset, uint8_t value)
void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t acc_flags) {
+
trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
if ((reg * 4) < adev->rmmio_size)
@@ -407,6 +412,7 @@ void static inline amdgpu_mm_wreg_mmio(struct amdgpu_device
*adev, uint32_t reg, void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v,
uint32_t acc_flags)
{
+
if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
return amdgpu_kiq_wreg(adev, reg, v);
@@ -461,6 +467,7 @@ u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
*/
void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) {
+
if ((reg * 4) < adev->rio_mem_size)
iowrite32(v, adev->rio_mem + (reg * 4));
else {
@@ -480,6 +487,7 @@ void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg,
u32 v)
*/
u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) {
+
if (index < adev->doorbell.num_doorbells) {
return readl(adev->doorbell.ptr + index);
} else {
@@ -500,6 +508,7 @@ u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32
index)
*/
void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) {
+
if (index < adev->doorbell.num_doorbells) {
writel(v, adev->doorbell.ptr + index);
} else {
@@ -518,6 +527,7 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32
index, u32 v)
*/
u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) {
+
if (index < adev->doorbell.num_doorbells) {
return atomic64_read((atomic64_t *)(adev->doorbell.ptr +
index));
} else {
@@ -538,6 +548,7 @@ u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32
index)
*/
0001-Fix-a-array-bound-overflow-bug-in-function-umr_clock
0001-Fix-a-array-bound-overflow-bug-in-function-umr_clock.patch Description: Binary data ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/radeon: Prefer lower feedback dividers
Am 25.08.20 um 19:33 schrieb Kai-Heng Feng:
Commit 2e26ccb119bd ("drm/radeon: prefer lower reference dividers")
fixed screen flicker for HP Compaq nx9420 but breaks other laptops like
Asus X50SL.
Turns out we also need to favor lower feedback dividers.
Mhm, let's hope that this works out for all others as well :)
Users confirmed this change fixes the regression and doesn't regress the
original fix.
Fixes: 2e26ccb119bd ("drm/radeon: prefer lower reference dividers")
BugLink: https://bugs.launchpad.net/bugs/1791312
BugLink: https://bugs.launchpad.net/bugs/1861554
Signed-off-by: Kai-Heng Feng
Reviewed-by: Christian König
---
drivers/gpu/drm/radeon/radeon_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/radeon_display.c
b/drivers/gpu/drm/radeon/radeon_display.c
index e0ae911ef427..7b69d6dfe44a 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -933,7 +933,7 @@ static void avivo_get_fb_ref_div(unsigned nom, unsigned
den, unsigned post_div,
/* get matching reference and feedback divider */
*ref_div = min(max(den/post_div, 1u), ref_div_max);
- *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
+ *fb_div = max(nom * *ref_div * post_div / den, 1u);
/* limit fb divider to its maximum */
if (*fb_div > fb_div_max) {
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RE: [PATCH] SWDEV-220451 - Query guest's information by VF2PF message - part 2
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Monk Liu
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Bokun Zhang
Sent: Saturday, May 2, 2020 1:48 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Bokun
Subject: [PATCH] SWDEV-220451 - Query guest's information by VF2PF message -
part 2
- Guest side change
- Refactor and implement VF2PF information
- Share checksum function between guest and host
- Refactor code in amdgpu_virt.c since some of them are useless
Change-Id: I881989d8fb6b6af88209badf4c4070c281f65b6a
Signed-off-by: Bokun Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 249 -
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 232 ---
3 files changed, 354 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a928fa9077c6..37f1d2669d51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3305,8 +3305,10 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
/* make sure IB test finished before entering exclusive mode
* to avoid preemption on IB test
* */
-if (amdgpu_sriov_vf(adev))
+if (amdgpu_sriov_vf(adev)) {
amdgpu_virt_request_full_gpu(adev, false);
+amdgpu_virt_fini_data_exchange(adev);
+}
/* disable all interrupts */
amdgpu_irq_disable_all(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 8c10084f44ef..b83212b76277 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -27,6 +27,12 @@
#include "amdgpu.h"
+#define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \
+do { \
+vf2pf_info->ucode_info[ucode].id = ucode; \
+vf2pf_info->ucode_info[ucode].version = ver; \
+} while (0)
+
bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) {
/* By now all MMIO pages except mailbox are blocked */ @@ -228,77 +234,212 @@
void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
adev->virt.mm_table.gpu_addr = 0;
}
-
-int amdgpu_virt_fw_reserve_get_checksum(void *obj,
-unsigned long obj_size,
-unsigned int key,
-unsigned int chksum)
+/*
+ * encode: obj.checksum = amd_sriov_msg_checksum(obj, size, key, 0)
+ * decode:0 = amd_sriov_msg_checksum(obj, size, key, obj.checksum)
+ */
+unsigned int amd_sriov_msg_checksum(void *obj,
+unsigned long obj_size,
+unsigned int key,
+unsigned int checksum)
{
-unsigned int ret = key;
+unsigned int ret = 0;
unsigned long i = 0;
unsigned char *pos;
-pos = (char *)obj;
-/* calculate checksum */
+/* calculate checksum of obj*/
+pos = (unsigned char *)obj;
for (i = 0; i < obj_size; ++i)
ret += *(pos + i);
-/* minus the chksum itself */
-pos = (char *)
-for (i = 0; i < sizeof(chksum); ++i)
+
+pos = (unsigned char *)
+for (i = 0; i < sizeof(checksum); ++i)
ret -= *(pos + i);
+
+ret ^= key;
+
+ret -= checksum;
+
return ret;
}
-void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
+static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) {
+struct amd_sriov_msg_pf2vf_info_header *pf2vf_info =
adev->virt.fw_reserve.p_pf2vf;
+uint32_t checksum;
+
+if (adev->virt.fw_reserve.p_pf2vf == NULL)
+return -EINVAL;
+
+if (pf2vf_info->size > 1024) {
+DRM_ERROR("invalid pf2vf message size\n");
+return -EINVAL;
+}
+
+switch (pf2vf_info->version) {
+case 1:
+checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum;
+checksum = amd_sriov_msg_checksum(
+adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
+adev->virt.fw_reserve.checksum_key, checksum);
+if (checksum != 0) {
+DRM_ERROR("invalid pf2vf message\n");
+return -EINVAL;
+}
+
+adev->virt.vf2pf_update_interval_ms = 0;
+adev->virt.gim_feature =
+((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags;
+break;
+case 2:
+checksum = pf2vf_info->checksum;
+checksum = amd_sriov_msg_checksum(
+adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
+0, checksum);
+if (checksum != 0) {
+DRM_ERROR("invalid pf2vf message\n");
+return -EINVAL;
+}
+
+adev->virt.vf2pf_update_interval_ms =
+((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms;
+adev->virt.gim_feature =
+((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all;
+break;
+default:
+DRM_ERROR("invalid pf2vf version\n");
+return -EINVAL;
+}
+
+if (adev->virt.vf2pf_update_interval_ms < 200 ||
adev->virt.vf2pf_update_interval_ms > 1)
+adev->virt.vf2pf_update_interval_ms = 2000;
+
+return 0;
+}
+
+static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device
+*adev) {
+struct amd_sriov_msg_vf2pf_info *vf2pf_info;
+vf2pf_info = (struct amd_sriov_msg_vf2pf_info *)
+adev->virt.fw_reserve.p_vf2pf;
+
+if (adev->virt.fw_reserve.p_vf2pf == NULL)
+return;
+
+POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE,
adev->vce.fw_version);
RE: [PATCH] SWDEV-220451 - Query guest's information by VF2PF message - Guest side - part 1
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Monk Liu
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Bokun Zhang
Sent: Wednesday, August 5, 2020 11:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Bokun
Subject: [PATCH] SWDEV-220451 - Query guest's information by VF2PF message -
Guest side - part 1
- Add guest side change to support VF2PF message
- Fix coding style
Change-Id: I82e5518cb10ec0b19fecaba7e05b02f4b7f2b409
Signed-off-by: Bokun Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h| 29 +-
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 276
2 files changed, 285 insertions(+), 20 deletions(-) create mode 100644
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index b0b2bdc750df..ad2b2628ab67 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -24,6 +24,8 @@
#ifndef AMDGPU_VIRT_H
#define AMDGPU_VIRT_H
+#include "amdgv_sriovmsg.h"
+
#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
#define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this
GPU */
#define AMDGPU_SRIOV_CAPS_IS_VF(1 << 2) /* this GPU is a virtual
function */
@@ -69,7 +71,10 @@ struct amdgpu_virt_fw_reserve {
struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
unsigned int checksum_key;
};
+
/*
+ * Legacy GIM header
+ *
* Defination between PF and VF
* Structures forcibly aligned to 4 to keep the same style as PF.
*/
@@ -89,15 +94,7 @@ enum AMDGIM_FEATURE_FLAG {
AMDGIM_FEATURE_HW_PERF_SIMULATION = (1 << 3), };
-struct amd_sriov_msg_pf2vf_info_header {
-/* the total structure size in byte. */
-uint32_t size;
-/* version of this structure, written by the GIM */
-uint32_t version;
-/* reserved */
-uint32_t reserved[2];
-} __aligned(4);
-struct amdgim_pf2vf_info_v1 {
+struct amdgim_pf2vf_info_v1 {
/* header contains size and version */
struct amd_sriov_msg_pf2vf_info_header header;
/* max_width * max_height */
@@ -116,6 +113,7 @@ struct amdgim_pf2vf_info_v1 {
unsigned int checksum;
} __aligned(4);
+/* TODO: below struct is duplicated to amd_sriov_msg_pf2vf_info */
struct amdgim_pf2vf_info_v2 {
/* header contains size and version */
struct amd_sriov_msg_pf2vf_info_header header; @@ -146,16 +144,6 @@ struct
amdgim_pf2vf_info_v2 {
uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 +
sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 3)]; }
__aligned(4);
-
-struct amd_sriov_msg_vf2pf_info_header {
-/* the total structure size in byte. */
-uint32_t size;
-/*version of this structure, written by the guest */
-uint32_t version;
-/* reserved */
-uint32_t reserved[2];
-} __aligned(4);
-
struct amdgim_vf2pf_info_v1 {
/* header contains size and version */
struct amd_sriov_msg_vf2pf_info_header header; @@ -217,8 +205,9 @@ struct
amdgim_vf2pf_info_v2 {
uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 +
sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; }
__aligned(4);
+/* TODO: below macro and typedef will cause compile error, need to
+remove */
#define AMDGPU_FW_VRAM_VF2PF_VER 2
-typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
+typedef struct amd_sriov_msg_vf2pf_info amdgim_vf2pf_info;
#define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
do { \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
new file mode 100644
index ..5355827ed0ae
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright 2018-2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+"Software"),
+ * to deal in the Software without restriction, including without
+limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
+sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom
+the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
+DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
+OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef AMDGV_SRIOV_MSG__H_
+#define
RE: [PATCH] SWDEV-220451 - Query guest's information by VF2PF message - Guest side - part 1
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Emily.Deng
>-Original Message-
>From: amd-gfx On Behalf Of Bokun
>Zhang
>Sent: Wednesday, August 5, 2020 11:32 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Zhang, Bokun
>Subject: [PATCH] SWDEV-220451 - Query guest's information by VF2PF
>message - Guest side - part 1
>
>- Add guest side change to support VF2PF message
>- Fix coding style
>
>Change-Id: I82e5518cb10ec0b19fecaba7e05b02f4b7f2b409
>Signed-off-by: Bokun Zhang
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h| 29 +-
> drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 276
>
> 2 files changed, 285 insertions(+), 20 deletions(-) create mode 100644
>drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
>index b0b2bdc750df..ad2b2628ab67 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
>@@ -24,6 +24,8 @@
> #ifndef AMDGPU_VIRT_H
> #define AMDGPU_VIRT_H
>
>+#include "amdgv_sriovmsg.h"
>+
> #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready
>*/
> #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on
>this GPU */
> #define AMDGPU_SRIOV_CAPS_IS_VF(1 << 2) /* this GPU is a virtual
>function */
>@@ -69,7 +71,10 @@ struct amdgpu_virt_fw_reserve {
> struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
> unsigned int checksum_key;
> };
>+
> /*
>+ * Legacy GIM header
>+ *
> * Defination between PF and VF
> * Structures forcibly aligned to 4 to keep the same style as PF.
> */
>@@ -89,15 +94,7 @@ enum AMDGIM_FEATURE_FLAG {
> AMDGIM_FEATURE_HW_PERF_SIMULATION = (1 << 3), };
>
>-struct amd_sriov_msg_pf2vf_info_header {
>-/* the total structure size in byte. */
>-uint32_t size;
>-/* version of this structure, written by the GIM */
>-uint32_t version;
>-/* reserved */
>-uint32_t reserved[2];
>-} __aligned(4);
>-struct amdgim_pf2vf_info_v1 {
>+struct amdgim_pf2vf_info_v1 {
> /* header contains size and version */
> struct amd_sriov_msg_pf2vf_info_header header;
> /* max_width * max_height */
>@@ -116,6 +113,7 @@ struct amdgim_pf2vf_info_v1 {
> unsigned int checksum;
> } __aligned(4);
>
>+/* TODO: below struct is duplicated to amd_sriov_msg_pf2vf_info */
> struct amdgim_pf2vf_info_v2 {
> /* header contains size and version */
> struct amd_sriov_msg_pf2vf_info_header header; @@ -146,16 +144,6
>@@ struct amdgim_pf2vf_info_v2 {
> uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0,
>0, (9 + sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 3)];
> }
>__aligned(4);
>
>-
>-struct amd_sriov_msg_vf2pf_info_header {
>-/* the total structure size in byte. */
>-uint32_t size;
>-/*version of this structure, written by the guest */
>-uint32_t version;
>-/* reserved */
>-uint32_t reserved[2];
>-} __aligned(4);
>-
> struct amdgim_vf2pf_info_v1 {
> /* header contains size and version */
> struct amd_sriov_msg_vf2pf_info_header header; @@ -217,8 +205,9
>@@ struct amdgim_vf2pf_info_v2 {
> uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256,
>64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)),
>0)]; } __aligned(4);
>
>+/* TODO: below macro and typedef will cause compile error, need to
>+remove */
> #define AMDGPU_FW_VRAM_VF2PF_VER 2
>-typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
>+typedef struct amd_sriov_msg_vf2pf_info amdgim_vf2pf_info;
>
> #define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
> do { \
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
>b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
>new file mode 100644
>index ..5355827ed0ae
>--- /dev/null
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
>@@ -0,0 +1,276 @@
>+/*
>+ * Copyright 2018-2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person
>+obtaining a
>+ * copy of this software and associated documentation files (the
>+"Software"),
>+ * to deal in the Software without restriction, including without
>+limitation
>+ * the rights to use, copy, modify, merge, publish, distribute,
>+sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom
>+the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be
>+included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>+EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>+MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
>EVENT
>+SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>+DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>+OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
>THE USE
>+OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+
Re: [PATCH] drm/amdgpu: simplify hw status clear/set logic
On 8/27/20 4:32 AM, Jiawei wrote:
Optimize code to iterate less loops in
amdgpu_device_ip_reinit_early_sriov()
Signed-off-by: Jiawei
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8f37f9f99105..696a61cc3ac6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2598,17 +2598,16 @@ static int amdgpu_device_ip_reinit_early_sriov(struct
amdgpu_device *adev)
AMD_IP_BLOCK_TYPE_IH,
};
- for (i = 0; i < adev->num_ip_blocks; i++)
- adev->ip_blocks[i].status.hw = false;
-
- for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
+ for (i = 0; i < adev->num_ip_blocks; i++) {
int j;
struct amdgpu_ip_block *block;
- for (j = 0; j < adev->num_ip_blocks; j++) {
- block = >ip_blocks[j];
+ block = >ip_blocks[i];
+ block->status.hw = false;
- if (block->version->type != ip_order[i] ||
+ for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
We could probably replace this "for" loop with a big if-statement
if ( block->version->type== AMD_IP_BLOCK_TYPE_GMC ||
block->version->type== AMD_IP_BLOCK_TYPE_COMMON ... )
But anyway it looks good to me as it is. Acked-by: Nirmoy Das
+
+ if (block->version->type != ip_order[j] ||
!block->status.valid)
continue;
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/pm: enable MP0 DPM for sienna_cichlid
[AMD Public Use] Reviewed-by: Tao Zhou > -Original Message- > From: Jiansong Chen > Sent: Thursday, August 27, 2020 2:47 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhou1, Tao ; Feng, Kenneth > ; Chen, Jiansong (Simon) > Subject: [PATCH] drm/amd/pm: enable MP0 DPM for sienna_cichlid > > Enable MP0 clock DPM for sienna_cichlid. > > Signed-off-by: Jiansong Chen > Change-Id: Iee6a05a634c200f9bbb895b963365bb001a451bc > --- > drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > index b48ac591db8b..b67931fd64b4 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > @@ -68,7 +68,8 @@ > FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ > FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ > FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ > - FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) > + FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)| \ > + FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) > > #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 > > @@ -230,6 +231,7 @@ sienna_cichlid_get_allowed_feature_mask(struct > smu_context *smu, > > *(uint64_t *)feature_mask |= > FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) > | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) > + | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) > | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) > | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) > | FEATURE_MASK(FEATURE_DS_FCLK_BIT) > -- > 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: simplify hw status clear/set logic
Reviewed-by: Emily.Deng
>-Original Message-
>From: amd-gfx On Behalf Of Gu,
>JiaWei (Will)
>Sent: Thursday, August 27, 2020 2:50 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Gu, JiaWei (Will)
>Subject: RE: [PATCH] drm/amdgpu: simplify hw status clear/set logic
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Ping...
>
>-Original Message-
>From: Jiawei
>Sent: Thursday, August 27, 2020 10:32 AM
>To: amd-gfx@lists.freedesktop.org
>Cc: Gu, JiaWei (Will)
>Subject: [PATCH] drm/amdgpu: simplify hw status clear/set logic
>
>Optimize code to iterate less loops in
>amdgpu_device_ip_reinit_early_sriov()
>
>Signed-off-by: Jiawei
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 ++---
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>index 8f37f9f99105..696a61cc3ac6 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>@@ -2598,17 +2598,16 @@ static int
>amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
> AMD_IP_BLOCK_TYPE_IH,
> };
>
>- for (i = 0; i < adev->num_ip_blocks; i++)
>- adev->ip_blocks[i].status.hw = false;
>-
>- for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
>+ for (i = 0; i < adev->num_ip_blocks; i++) {
> int j;
> struct amdgpu_ip_block *block;
>
>- for (j = 0; j < adev->num_ip_blocks; j++) {
>- block = >ip_blocks[j];
>+ block = >ip_blocks[i];
>+ block->status.hw = false;
>
>- if (block->version->type != ip_order[i] ||
>+ for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
>+
>+ if (block->version->type != ip_order[j] ||
> !block->status.valid)
> continue;
>
>--
>2.17.1
>___
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>amd-gfx@lists.freedesktop.org
>https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.free
>desktop.org%2Fmailman%2Flistinfo%2Famd-
>gfxdata=02%7C01%7CEmily.Deng%40amd.com%7Cd49aeebc6337454ad
>be508d84a558474%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
>37341078483894286sdata=ORgvulljLZNfexMcXZCXi4JEmz3J357Oxa%2B
>GxYW3%2FSo%3Dreserved=0
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RE: [PATCH] drm/amdgpu: simplify hw status clear/set logic
[AMD Official Use Only - Internal Distribution Only]
Ping...
-Original Message-
From: Jiawei
Sent: Thursday, August 27, 2020 10:32 AM
To: amd-gfx@lists.freedesktop.org
Cc: Gu, JiaWei (Will)
Subject: [PATCH] drm/amdgpu: simplify hw status clear/set logic
Optimize code to iterate less loops in
amdgpu_device_ip_reinit_early_sriov()
Signed-off-by: Jiawei
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8f37f9f99105..696a61cc3ac6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2598,17 +2598,16 @@ static int amdgpu_device_ip_reinit_early_sriov(struct
amdgpu_device *adev)
AMD_IP_BLOCK_TYPE_IH,
};
- for (i = 0; i < adev->num_ip_blocks; i++)
- adev->ip_blocks[i].status.hw = false;
-
- for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
+ for (i = 0; i < adev->num_ip_blocks; i++) {
int j;
struct amdgpu_ip_block *block;
- for (j = 0; j < adev->num_ip_blocks; j++) {
- block = >ip_blocks[j];
+ block = >ip_blocks[i];
+ block->status.hw = false;
- if (block->version->type != ip_order[i] ||
+ for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
+
+ if (block->version->type != ip_order[j] ||
!block->status.valid)
continue;
--
2.17.1
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[PATCH] drm/amd/pm: enable MP0 DPM for sienna_cichlid
Enable MP0 clock DPM for sienna_cichlid. Signed-off-by: Jiansong Chen Change-Id: Iee6a05a634c200f9bbb895b963365bb001a451bc --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index b48ac591db8b..b67931fd64b4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -68,7 +68,8 @@ FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) + FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)| \ + FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 @@ -230,6 +231,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) + | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_DS_FCLK_BIT) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/4] drm/amd/pm: drop unnecessary feature->mutex lock protections(V2)
Series is Acked-by: Nirmoy Das On 8/25/20 9:49 AM, Evan Quan wrote: As these operations are performed in hardware setup and there is actually no race conditions during this period considering: 1. the hardware setup is serial and cannnot be in parallel 2. all other operations can be performed only after hardware setup complete. V2: rich the commit log description Change-Id: I096d7ab0855ff59b0ecb56fd9d6d9946b3605fc8 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 -- 2 files changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 09dc5303762b..b7cad8ef6153 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -361,20 +361,16 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) int ret = 0; uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; - mutex_lock(>mutex); bitmap_zero(feature->allowed, SMU_FEATURE_MAX); - mutex_unlock(>mutex); ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, SMU_FEATURE_MAX/32); if (ret) return ret; - mutex_lock(>mutex); bitmap_or(feature->allowed, feature->allowed, (unsigned long *)allowed_feature_mask, feature->feature_num); - mutex_unlock(>mutex); return ret; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index 548db1edd352..28a19ffd22a1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -721,7 +721,6 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - mutex_lock(>mutex); if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) goto failed; @@ -738,7 +737,6 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu) goto failed; failed: - mutex_unlock(>mutex); return ret; } ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
