RE: [PATCH 2/4] drm/amdgpu: add VCN 3.0 AV1 registers
[AMD Public Use] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Wednesday, September 16, 2020 02:24 To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH 2/4] drm/amdgpu: add VCN 3.0 AV1 registers This adds the AV1 registers. Signed-off-by: Alex Deucher --- .../include/asic_reg/vcn/vcn_3_0_0_sh_mask.h | 34 +++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h index c0efd90808f2..58cf7adb9d54 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h @@ -2393,6 +2393,7 @@ #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC__SHIFT 0x7 #define VCN_FEATURES__HAS_SCLR_DEC__SHIFT 0x8 #define VCN_FEATURES__HAS_VP9_DEC__SHIFT 0x9 +#define VCN_FEATURES__HAS_AV1_DEC__SHIFT 0xa #define VCN_FEATURES__HAS_EFC_ENC__SHIFT 0xb #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC__SHIFT 0xc #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC__SHIFT 0xd @@ -2407,6 +2408,7 @@ #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC_MASK 0x0080L #define VCN_FEATURES__HAS_SCLR_DEC_MASK 0x0100L #define VCN_FEATURES__HAS_VP9_DEC_MASK 0x0200L +#define VCN_FEATURES__HAS_AV1_DEC_MASK 0x0400L #define VCN_FEATURES__HAS_EFC_ENC_MASK 0x0800L #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC_MASK 0x1000L #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC_MASK 0x2000L @@ -2809,8 +2811,10 @@ #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 #define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 #define UVD_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define UVD_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b #define UVD_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c #define UVD_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define UVD_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e #define UVD_SUVD_CGC_GATE__SMPA__SHIFT 0x1f #define UVD_SUVD_CGC_GATE__SRE_MASK 0x0001L #define UVD_SUVD_CGC_GATE__SIT_MASK 0x0002L @@ -2839,8 +2843,10 @@ #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x0100L #define UVD_SUVD_CGC_GATE__EFC_MASK 0x0200L #define UVD_SUVD_CGC_GATE__SAOE_MASK 0x0400L +#define UVD_SUVD_CGC_GATE__SRE_AV1_MASK 0x0800L #define UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 0x1000L #define UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 0x2000L +#define UVD_SUVD_CGC_GATE__SCM_AV1_MASK 0x4000L #define UVD_SUVD_CGC_GATE__SMPA_MASK 0x8000L //UVD_SUVD_CGC_STATUS #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 @@ -2873,6 +2879,8 @@ #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b
RE: [PATCH 3/4] drm/amdgpu: use the AV1 defines for VCN 3.0
[AMD Public Use] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Wednesday, September 16, 2020 02:24 To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH 3/4] drm/amdgpu: use the AV1 defines for VCN 3.0 Switch from magic numbers to defines for AV1 clockgating. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 589d6cd8adec..e074f7ed388c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -746,18 +746,18 @@ static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) | UVD_SUVD_CGC_GATE__IME_HEVC_MASK | UVD_SUVD_CGC_GATE__EFC_MASK | UVD_SUVD_CGC_GATE__SAOE_MASK - | 0x0800 + | UVD_SUVD_CGC_GATE__SRE_AV1_MASK | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK - | 0x4000 + | UVD_SUVD_CGC_GATE__SCM_AV1_MASK | UVD_SUVD_CGC_GATE__SMPA_MASK); WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK | UVD_SUVD_CGC_GATE2__MPBE1_MASK - | 0x0004 - | 0x0008 + | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK + | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK | UVD_SUVD_CGC_GATE2__MPC1_MASK); WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); @@ -776,8 +776,8 @@ static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK - | 0x8000 - | 0x0001 + | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK + | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); @@ -892,8 +892,8 @@ static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK - | 0x8000 - | 0x0001 + | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK + | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Chawking.zhang%40amd.com%7Cf1b6a751d3c949dacef608d859a49351%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637357910672209491sdata=YZ0iB9Ol3M1ErK1LzQqmXvO3USy7G7NvoHxff0liN%2BE%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 4/4] drm/amdgpu: add device ID for sienna_cichlid (v2)
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, September 16, 2020 02:24
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Gao, Likun
Subject: [PATCH 4/4] drm/amdgpu: add device ID for sienna_cichlid (v2)
From: Likun Gao
Add device ID for sienna_cichlid.
v2: squash in additional device ids.
Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6e4c860e8ae0..0bf22134f17a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1076,6 +1076,14 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
+ /* Sienna_Cichlid */
+ {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+ {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+ {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+ {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+ {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+ {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+
{0, 0, 0}
};
--
2.25.4
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Re: [PATCH 1/4] drm/amdgpu: add the GC 10.3 VRS registers
Reviewed-by:Hawking Zhang Sent from my iPhone > On Sep 16, 2020, at 02:24, Alex Deucher wrote: > > Add the VRS registers. > > Signed-off-by: Alex Deucher > --- > .../include/asic_reg/gc/gc_10_3_0_default.h | 2 + > .../include/asic_reg/gc/gc_10_3_0_offset.h| 4 ++ > .../include/asic_reg/gc/gc_10_3_0_sh_mask.h | 50 +++ > 3 files changed, 56 insertions(+) > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > index 1116779252e6..e245e912535e 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > @@ -2727,6 +2727,7 @@ > #define mmDB_STENCIL_WRITE_BASE_DEFAULT >0x > #define mmDB_RESERVED_REG_1_DEFAULT >0x > #define mmDB_RESERVED_REG_3_DEFAULT >0x > +#define mmDB_VRS_OVERRIDE_CNTL_DEFAULT > 0x > #define mmDB_Z_READ_BASE_HI_DEFAULT >0x > #define mmDB_STENCIL_READ_BASE_HI_DEFAULT >0x > #define mmDB_Z_WRITE_BASE_HI_DEFAULT >0x > @@ -3062,6 +3063,7 @@ > #define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT >0x > #define mmPA_STEREO_CNTL_DEFAULT >0x > #define mmPA_STATE_STEREO_X_DEFAULT >0x > +#define mmPA_CL_VRS_CNTL_DEFAULT > 0x > #define mmPA_SU_POINT_SIZE_DEFAULT >0x > #define mmPA_SU_POINT_MINMAX_DEFAULT >0x > #define mmPA_SU_LINE_CNTL_DEFAULT >0x > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > index cbaad7d83194..66a4151fa676 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > @@ -5379,6 +5379,8 @@ > #define mmDB_RESERVED_REG_1_BASE_IDX > 1 > #define mmDB_RESERVED_REG_3 > 0x0017 > #define mmDB_RESERVED_REG_3_BASE_IDX > 1 > +#define mmDB_VRS_OVERRIDE_CNTL > 0x0019 > +#define mmDB_VRS_OVERRIDE_CNTL_BASE_IDX > 1 > #define mmDB_Z_READ_BASE_HI > 0x001a > #define mmDB_Z_READ_BASE_HI_BASE_IDX > 1 > #define mmDB_STENCIL_READ_BASE_HI > 0x001b > @@ -6049,6 +6051,8 @@ > #define mmPA_STEREO_CNTL_BASE_IDX > 1 > #define mmPA_STATE_STEREO_X > 0x0211 > #define mmPA_STATE_STEREO_X_BASE_IDX > 1 > +#define mmPA_CL_VRS_CNTL > 0x0212 > +#define mmPA_CL_VRS_CNTL_BASE_IDX > 1 > #define mmPA_SU_POINT_SIZE > 0x0280 > #define mmPA_SU_POINT_SIZE_BASE_IDX > 1 > #define mmPA_SU_POINT_MINMAX > 0x0281 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > index c2d035ef3e94..aed799d9a0e8 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > @@ -9777,6 +9777,7 @@ > #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT > 0x3 > #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT > 0x4 > #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT > 0x8 > +#define
[pull] amdgpu, amdkfd, radeon drm-fixes-5.9
Hi Dave, Daniel, Fixes for 5.9. The following changes since commit 7f7a47952c0f981f9c9a6409c8cf8d025d55af64: Merge tag 'drm-misc-fixes-2020-09-09' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes (2020-09-11 09:49:23 +1000) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux tags/amd-drm-fixes-5.9-2020-09-17 for you to fetch changes up to 875d369d8f75275d30e59421602d9366426abff7: drm/amd/display: Don't log hdcp module warnings in dmesg (2020-09-17 00:13:34 -0400) amd-drm-fixes-5.9-2020-09-17: amdgpu: - Sienna Cichlid fixes - Navy Flounder fixes - DC fixes amdkfd: - Fix a GPU reset crash - Fix a memory leak radeon: - Revert a PLL fix that broke other boards Andrey Grodzovsky (1): drm/amdgpu: Include sienna_cichlid in USBC PD FW support. Bhawanpreet Lakha (2): drm/amd/display: Don't use DRM_ERROR() for DTM add topology drm/amd/display: Don't log hdcp module warnings in dmesg Christian König (1): drm/radeon: revert "Prefer lower feedback dividers" Dennis Li (2): drm/kfd: fix a system crash issue during GPU recovery drm/amdkfd: fix a memory leak issue Jiansong Chen (2): drm/amd/pm: support runtime pptable update for sienna_cichlid etc. drm/amdgpu: declare ta firmware for navy_flounder Jun Lei (1): drm/amd/display: update nv1x stutter latencies Michel Dänzer (1): drm/amdgpu/dc: Require primary plane to be enabled whenever the CRTC is drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 2 +- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +++--- .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +-- .../gpu/drm/amd/display/modules/hdcp/hdcp_log.h| 2 +- .../gpu/drm/amd/display/modules/hdcp/hdcp_psp.c| 2 +- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 12 ++-- drivers/gpu/drm/radeon/radeon_display.c| 2 +- 9 files changed, 29 insertions(+), 33 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: remove experimental flag from navi12
Ping?
On Tue, Sep 15, 2020 at 2:22 PM Alex Deucher wrote:
>
> Navi12 has worked fine for a while now.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index d87d37c25329..6e4c860e8ae0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1073,8 +1073,8 @@ static const struct pci_device_id pciidlist[] = {
> {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_RENOIR|AMD_IS_APU},
>
> /* Navi12 */
> - {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
> - {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
> + {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
> + {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
>
> {0, 0, 0}
> };
> --
> 2.25.4
>
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Re: [PATCH 1/4] drm/amdgpu: add the GC 10.3 VRS registers
Ping on this series? Alex On Tue, Sep 15, 2020 at 2:24 PM Alex Deucher wrote: > > Add the VRS registers. > > Signed-off-by: Alex Deucher > --- > .../include/asic_reg/gc/gc_10_3_0_default.h | 2 + > .../include/asic_reg/gc/gc_10_3_0_offset.h| 4 ++ > .../include/asic_reg/gc/gc_10_3_0_sh_mask.h | 50 +++ > 3 files changed, 56 insertions(+) > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > index 1116779252e6..e245e912535e 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h > @@ -2727,6 +2727,7 @@ > #define mmDB_STENCIL_WRITE_BASE_DEFAULT > 0x > #define mmDB_RESERVED_REG_1_DEFAULT > 0x > #define mmDB_RESERVED_REG_3_DEFAULT > 0x > +#define mmDB_VRS_OVERRIDE_CNTL_DEFAULT > 0x > #define mmDB_Z_READ_BASE_HI_DEFAULT > 0x > #define mmDB_STENCIL_READ_BASE_HI_DEFAULT > 0x > #define mmDB_Z_WRITE_BASE_HI_DEFAULT > 0x > @@ -3062,6 +3063,7 @@ > #define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT > 0x > #define mmPA_STEREO_CNTL_DEFAULT > 0x > #define mmPA_STATE_STEREO_X_DEFAULT > 0x > +#define mmPA_CL_VRS_CNTL_DEFAULT > 0x > #define mmPA_SU_POINT_SIZE_DEFAULT > 0x > #define mmPA_SU_POINT_MINMAX_DEFAULT > 0x > #define mmPA_SU_LINE_CNTL_DEFAULT > 0x > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > index cbaad7d83194..66a4151fa676 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h > @@ -5379,6 +5379,8 @@ > #define mmDB_RESERVED_REG_1_BASE_IDX > 1 > #define mmDB_RESERVED_REG_3 > 0x0017 > #define mmDB_RESERVED_REG_3_BASE_IDX > 1 > +#define mmDB_VRS_OVERRIDE_CNTL > 0x0019 > +#define mmDB_VRS_OVERRIDE_CNTL_BASE_IDX > 1 > #define mmDB_Z_READ_BASE_HI > 0x001a > #define mmDB_Z_READ_BASE_HI_BASE_IDX > 1 > #define mmDB_STENCIL_READ_BASE_HI > 0x001b > @@ -6049,6 +6051,8 @@ > #define mmPA_STEREO_CNTL_BASE_IDX > 1 > #define mmPA_STATE_STEREO_X > 0x0211 > #define mmPA_STATE_STEREO_X_BASE_IDX > 1 > +#define mmPA_CL_VRS_CNTL > 0x0212 > +#define mmPA_CL_VRS_CNTL_BASE_IDX > 1 > #define mmPA_SU_POINT_SIZE > 0x0280 > #define mmPA_SU_POINT_SIZE_BASE_IDX > 1 > #define mmPA_SU_POINT_MINMAX > 0x0281 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > index c2d035ef3e94..aed799d9a0e8 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h > @@ -9777,6 +9777,7 @@ > #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT > 0x3 > #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT > 0x4 > #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT > 0x8 >
RE: [PATCH v1] powerplay:hwmgr - modify the return value
[AMD Official Use Only - Internal Distribution Only]
Thanks. Reviewed-by: Evan Quan
-Original Message-
From: Xiaoliang Pang
Sent: Thursday, September 17, 2020 11:46 AM
To: Quan, Evan ; Deucher, Alexander
; Koenig, Christian ;
airl...@linux.ie; dan...@ffwll.ch; Feng, Kenneth ;
zhengbi...@huawei.com; pe...@vangils.xyz; yt...@amd.com
Cc: Das, Nirmoy ; Huang, JinHuiEric
; amd-gfx@lists.freedesktop.org;
dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org;
tianjia.zh...@linux.alibaba.com; dawning.p...@gmail.com
Subject: [PATCH v1] powerplay:hwmgr - modify the return value
modify the return value is -EINVAL
Fixes: f83a9991648bb("drm/amd/powerplay: add Vega10 powerplay support (v5)")
Fixes: 2cac05dee6e30("drm/amd/powerplay: add the hw manager for vega12 (v4)")
Cc: Eric Huang
Cc: Evan Quan
Signed-off-by: Xiaoliang Pang
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index c378a000c934..7eada3098ffc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4659,7 +4659,7 @@ static int
vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
if ((data->water_marks_bitmap & WaterMarksExist) &&
!(data->water_marks_bitmap & WaterMarksLoaded)) {
result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
-PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
+PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
data->water_marks_bitmap |= WaterMarksLoaded;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index a678a67f1c0d..04da52cea824 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -2390,7 +2390,7 @@ static int
vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
!(data->water_marks_bitmap & WaterMarksLoaded)) {
result = smum_smc_table_manager(hwmgr,
(uint8_t *)wm_table, TABLE_WATERMARKS, false);
-PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
+PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
data->water_marks_bitmap |= WaterMarksLoaded;
}
--
2.17.1
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[PATCH 1/1] drm/amdgpu: Fix handling of KFD initialization failures
Remember KFD module initializaton status in a global variable. Skip KFD
device probing when the module was not initialized. Other amdgpu_amdkfd
calls are then protected by the adev->kfd.dev check.
Also print a clear error message when KFD disables itself. Amdgpu
continues its intialization even when KFD failed.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 11 ++-
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_module.c| 1 +
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index d58148f455dd..7f14461f7f40 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -36,6 +36,8 @@
*/
uint64_t amdgpu_amdkfd_total_mem_size;
+bool kfd_initialized;
+
int amdgpu_amdkfd_init(void)
{
struct sysinfo si;
@@ -51,19 +53,26 @@ int amdgpu_amdkfd_init(void)
#else
ret = -ENOENT;
#endif
+ kfd_initialized = !ret;
return ret;
}
void amdgpu_amdkfd_fini(void)
{
- kgd2kfd_exit();
+ if (kfd_initialized) {
+ kgd2kfd_exit();
+ kfd_initialized = false;
+ }
}
void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
{
bool vf = amdgpu_sriov_vf(adev);
+ if (!kfd_initialized)
+ return;
+
adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
adev->pdev, adev->asic_type, vf);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index b7b16adb0615..297484ca7d19 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -97,6 +97,7 @@ void kfd_chardev_exit(void)
device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
class_destroy(kfd_class);
unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
+ kfd_device = NULL;
}
struct device *kfd_chardev(void)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index f4b7f7e6c40e..e5aa51f44dd5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -70,6 +70,7 @@ static int kfd_init(void)
err_topology:
kfd_chardev_exit();
err_ioctl:
+ pr_err("KFD is disabled due to module intialization failure\n");
return err;
}
--
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[PATCH v1] powerplay:hwmgr - modify the return value
modify the return value is -EINVAL
Fixes: f83a9991648bb("drm/amd/powerplay: add Vega10 powerplay support (v5)")
Fixes: 2cac05dee6e30("drm/amd/powerplay: add the hw manager for vega12 (v4)")
Cc: Eric Huang
Cc: Evan Quan
Signed-off-by: Xiaoliang Pang
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index c378a000c934..7eada3098ffc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4659,7 +4659,7 @@ static int
vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
if ((data->water_marks_bitmap & WaterMarksExist) &&
!(data->water_marks_bitmap & WaterMarksLoaded)) {
result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table,
WMTABLE, false);
- PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return
EINVAL);
+ PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return
-EINVAL);
data->water_marks_bitmap |= WaterMarksLoaded;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index a678a67f1c0d..04da52cea824 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -2390,7 +2390,7 @@ static int
vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
!(data->water_marks_bitmap & WaterMarksLoaded)) {
result = smum_smc_table_manager(hwmgr,
(uint8_t *)wm_table,
TABLE_WATERMARKS, false);
- PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return
EINVAL);
+ PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return
-EINVAL);
data->water_marks_bitmap |= WaterMarksLoaded;
}
--
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Re: [PATCH v3 2/3] drm/amdkfd: Add process eviction counters to sysfs
Some nit-picks and one more possible simplification inline. I want to
make adding more stats later as painless as possible.
Looks good otherwise.
Am 2020-09-16 um 2:42 p.m. schrieb Philip Cox:
> Add per-process eviction counters to sysfs to keep track of
> how many eviction events have happened for each process.
>
> v2: rename the stats dir, and track all evictions per process, per device.
> v3: Simplify the stats kobject handling and cleanup.
>
> Signed-off-by: Philip Cox
> ---
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 9 ++
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 +-
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 97 +++
> 3 files changed, 114 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index cafbc3aa980a..5b9e0df2a90e 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -653,6 +653,7 @@ static int evict_process_queues_nocpsch(struct
> device_queue_manager *dqm,
> pr_info_ratelimited("Evicting PASID 0x%x queues\n",
> pdd->process->pasid);
>
> + pdd->last_evict_timestamp = get_jiffies_64();
> /* Mark all queues as evicted. Deactivate all active queues on
>* the qpd.
>*/
> @@ -714,6 +715,7 @@ static int evict_process_queues_cpsch(struct
> device_queue_manager *dqm,
> q->properties.is_active = false;
> decrement_queue_count(dqm, q->properties.type);
> }
> + pdd->last_evict_timestamp = get_jiffies_64();
> retval = execute_queues_cpsch(dqm,
> qpd->is_debug ?
> KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
> @@ -732,6 +734,7 @@ static int restore_process_queues_nocpsch(struct
> device_queue_manager *dqm,
> struct mqd_manager *mqd_mgr;
> struct kfd_process_device *pdd;
> uint64_t pd_base;
> + uint64_t eviction_duration;
> int retval, ret = 0;
>
> pdd = qpd_to_pdd(qpd);
> @@ -799,6 +802,8 @@ static int restore_process_queues_nocpsch(struct
> device_queue_manager *dqm,
> ret = retval;
> }
> qpd->evicted = 0;
> + eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
> + atomic64_add(eviction_duration, >evict_duration_counter);
> out:
> if (mm)
> mmput(mm);
> @@ -812,6 +817,7 @@ static int restore_process_queues_cpsch(struct
> device_queue_manager *dqm,
> struct queue *q;
> struct kfd_process_device *pdd;
> uint64_t pd_base;
> + uint64_t eviction_duration;
> int retval = 0;
>
> pdd = qpd_to_pdd(qpd);
> @@ -845,6 +851,9 @@ static int restore_process_queues_cpsch(struct
> device_queue_manager *dqm,
> retval = execute_queues_cpsch(dqm,
> KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
> qpd->evicted = 0;
> + eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
> + atomic64_add(eviction_duration, >evict_duration_counter);
> +
> out:
> dqm_unlock(dqm);
> return retval;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> index 023629f28495..a500fe611b43 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> @@ -631,7 +631,7 @@ enum kfd_pdd_bound {
> PDD_BOUND_SUSPENDED,
> };
>
> -#define MAX_SYSFS_FILENAME_LEN 11
> +#define MAX_SYSFS_FILENAME_LEN 15
>
> /*
> * SDMA counter runs at 100MHz frequency.
> @@ -692,6 +692,13 @@ struct kfd_process_device {
> uint64_t sdma_past_activity_counter;
> struct attribute attr_sdma;
> char sdma_filename[MAX_SYSFS_FILENAME_LEN];
> +
> + /* Eviction activity tracking */
> + unsigned long last_evict_timestamp;
get_jiffies_64 returns u64. You should use an equivalent type (uint64_t)
here for consistency.
> + atomic64_t evict_duration_counter;
> + struct attribute attr_evict;
> +
> + struct kobject *kobj_stats;
> };
>
> #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> index 1e15aa7d8ae8..b4ba394ad599 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -344,6 +344,26 @@ static ssize_t kfd_procfs_queue_show(struct kobject
> *kobj,
>
> return 0;
> }
> +static ssize_t kfd_procfs_stats_show(struct kobject *kobj,
> + struct attribute *attr, char *buffer)
> +{
> + if (strcmp(attr->name, "evicted_ms") == 0) {
> + struct kfd_process_device *pdd = container_of(attr,
> + struct kfd_process_device,
> + attr_evict);
> + uint64_t
Re: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.
On Wed, Sep 16, 2020 at 6:16 PM Zhuo, Qingqing wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo wrote:
> >
> > From: jinlong zhang
> >
> > [why]
> > while read edid return defer, then it enter to msleep, but it actually
> > took more time during msleep, this will cause remaining edid read
> > fail.
> >
> > [how]
> > Replacing msleep with udelay, it will not take any extra time, edid return
> > pass finally.
>
> How long of a delay are we talking about here? Some platforms don't support
> long udelays and someone will send a patch to change this to msleep.
>
> Alex
>
> -
>
> Hi Alex,
>
> It's between 0-5ms for generic cases, though there exist some dongle
> workaround cases where we will do 70ms. Would this be a concern?
I think ARM has a limit of 2ms for udelay.
Alex
>
> Thank you,
> Lillian
>
>
> >
> > Signed-off-by: jinlong zhang
> > Reviewed-by: Wenjing Liu
> > Acked-by: Qingqing Zhuo
> > ---
> > drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > index 743042d5905a..cdcad82765e0 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service
> > *ddc,
> > if ((*payload->reply ==
> > AUX_TRANSACTION_REPLY_AUX_DEFER) ||
> > (*payload->reply ==
> > AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
> > if (payload->defer_delay >
> > 0)
> > -
> > msleep(payload->defer_delay);
> > +
> > + udelay(payload->defer_delay * 1000);
> > }
> > }
> > break;
> > --
> > 2.17.1
> >
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Re: [PATCH] Revert "drm/radeon: handle PCIe root ports with addressing limitations"
On Wed, Sep 16, 2020 at 3:04 AM Christoph Hellwig wrote: > > On Tue, Sep 15, 2020 at 02:46:07PM -0400, Alex Deucher wrote: > > This change breaks tons of systems. > > Did you do at least some basic root causing on why? Do GPUs get > fed address they can't deal with? Any examples? > > Bug 1 doesn't seem to contain any analysis and was reported against > a very old kernel that had all kind of fixes since. > > Bug 2 seems to imply a drm kthread is accessing some structure it > shouldn't, which would imply a mismatch between pools used by radeon > now and those actually provided by the core. Something that should > be pretty to trivial to fix for someone understanding the whole ttm > pool maze. > > Bug 3: same as 1, but an even older kernel. > > Bug 4: looks like 1 and 3, and actually verified to work properly > in 5.9-rc. Did you try to get the other reporters test this as well? It would appear that the change in 5.9 to disable AGP on radeon fixed the issue. I'm following up on the other tickets to see if I can get confirmation. On another thread[1], the user was able to avoid the issue by disabling HIMEM. Looks like some issue with HIMEM and/or AGP. Alex [1] https://lkml.org/lkml/2019/12/14/263 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.
[AMD Official Use Only - Internal Distribution Only]
On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo wrote:
>
> From: jinlong zhang
>
> [why]
> while read edid return defer, then it enter to msleep, but it actually
> took more time during msleep, this will cause remaining edid read
> fail.
>
> [how]
> Replacing msleep with udelay, it will not take any extra time, edid return
> pass finally.
How long of a delay are we talking about here? Some platforms don't support
long udelays and someone will send a patch to change this to msleep.
Alex
-
Hi Alex,
It's between 0-5ms for generic cases, though there exist some dongle workaround
cases where we will do 70ms. Would this be a concern?
Thank you,
Lillian
>
> Signed-off-by: jinlong zhang
> Reviewed-by: Wenjing Liu
> Acked-by: Qingqing Zhuo
> ---
> drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> index 743042d5905a..cdcad82765e0 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service
> *ddc,
> if ((*payload->reply ==
> AUX_TRANSACTION_REPLY_AUX_DEFER) ||
> (*payload->reply ==
> AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
> if (payload->defer_delay > 0)
> -
> msleep(payload->defer_delay);
> +
> + udelay(payload->defer_delay * 1000);
> }
> }
> break;
> --
> 2.17.1
>
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Re: [PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.
On Wed, Sep 16, 2020 at 3:42 PM Qingqing Zhuo wrote:
>
> From: jinlong zhang
>
> [why]
> while read edid return defer, then it enter to msleep,
> but it actually took more time during msleep,
> this will cause remaining edid read fail.
>
> [how]
> Replacing msleep with udelay, it will not take any extra time, edid return
> pass finally.
How long of a delay are we talking about here? Some platforms don't
support long udelays and someone will send a patch to change this to
msleep.
Alex
>
> Signed-off-by: jinlong zhang
> Reviewed-by: Wenjing Liu
> Acked-by: Qingqing Zhuo
> ---
> drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> index 743042d5905a..cdcad82765e0 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> @@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service
> *ddc,
> if ((*payload->reply ==
> AUX_TRANSACTION_REPLY_AUX_DEFER) ||
> (*payload->reply ==
> AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
> if (payload->defer_delay > 0)
> -
> msleep(payload->defer_delay);
> +
> udelay(payload->defer_delay * 1000);
> }
> }
> break;
> --
> 2.17.1
>
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Re: [PATCH 3/3] SWDEV-247673 - stop data_exchange work thread before reset
On Wed, Sep 16, 2020 at 11:05 AM Bokun Zhang wrote:
>
> From: Tiecheng Zhou
>
> In FLR routine, init_data_exchange is called at reset_sriov
> while fini_data_exchange is not. This will duplicating work
> thread.
>
> So call fini_data_exchange before reset for SRIOV
>
> Change-Id: I974c6a3c5de86736eebefc386c03fe0e18e1fae3
> Signed-off-by: Tiecheng Zhou
> Signed-off-by: Bokun Zhang
Please drop the SWDEV reference from the subject and prefix the patch
with drm/amdgpu:
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 483ec0136332..e71cf3b34e15 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -4080,6 +4080,11 @@ static int amdgpu_device_pre_asic_reset(struct
> amdgpu_device *adev,
>
> amdgpu_debugfs_wait_dump(adev);
>
> + if (amdgpu_sriov_vf(adev)) {
> + /* stop the data exchange thread */
> + amdgpu_virt_fini_data_exchange(adev);
> + }
> +
> /* block all schedulers and reset given job's ring */
> for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
> struct amdgpu_ring *ring = adev->rings[i];
> --
> 2.20.1
>
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Re: [PATCH 2/3] SWDEV-220451 - Query guest's information by VF2PF message - Guest side - part 2
On Wed, Sep 16, 2020 at 11:05 AM Bokun Zhang wrote:
>
> - Add VF2PF message support
> - Remove incorrect Macro to avoid compile error
> - Remove duplicated struct and use amdgv_sriovmsg.h
>
> Change-Id: I8175d304871f4b5aab75fd071a6bdf8008137dbe
> Signed-off-by: Bokun Zhang
Please drop the SWDEV reference from the subject and prefix the patch
with drm/amdgpu: Also please provide a better patch subject and
description. It looks like this patch is doing multiple things and
it's hard to understand them all.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 244 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 75 +--
> 3 files changed, 198 insertions(+), 125 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 5d702f6e77de..483ec0136332 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3443,8 +3443,10 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
> /* make sure IB test finished before entering exclusive mode
> * to avoid preemption on IB test
> * */
> - if (amdgpu_sriov_vf(adev))
> + if (amdgpu_sriov_vf(adev)) {
> amdgpu_virt_request_full_gpu(adev, false);
> + amdgpu_virt_fini_data_exchange(adev);
> + }
>
> /* disable all interrupts */
> amdgpu_irq_disable_all(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index f76961d17246..1f1171812e35 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -31,6 +31,12 @@
> #include "soc15.h"
> #include "nv.h"
>
> +#define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \
> + do { \
> + vf2pf_info->ucode_info[ucode].id = ucode; \
> + vf2pf_info->ucode_info[ucode].version = ver; \
> + } while (0)
> +
> bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
> {
> /* By now all MMIO pages except mailbox are blocked */
> @@ -239,10 +245,10 @@ void amdgpu_virt_free_mm_table(struct amdgpu_device
> *adev)
> }
>
>
> -int amdgpu_virt_fw_reserve_get_checksum(void *obj,
> - unsigned long obj_size,
> - unsigned int key,
> - unsigned int chksum)
> +unsigned int amd_sriov_msg_checksum(void *obj,
> + unsigned long obj_size,
> + unsigned int key,
> + unsigned int checksum)
> {
> unsigned int ret = key;
> unsigned long i = 0;
> @@ -252,9 +258,9 @@ int amdgpu_virt_fw_reserve_get_checksum(void *obj,
> /* calculate checksum */
> for (i = 0; i < obj_size; ++i)
> ret += *(pos + i);
> - /* minus the chksum itself */
> - pos = (char *)
> - for (i = 0; i < sizeof(chksum); ++i)
> + /* minus the checksum itself */
> + pos = (char *)
> + for (i = 0; i < sizeof(checksum); ++i)
> ret -= *(pos + i);
> return ret;
> }
> @@ -415,33 +421,187 @@ static void amdgpu_virt_add_bad_page(struct
> amdgpu_device *adev,
> }
> }
>
> -void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
> +static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
> {
> - uint32_t pf2vf_size = 0;
> - uint32_t checksum = 0;
> + struct amd_sriov_msg_pf2vf_info_header *pf2vf_info =
> adev->virt.fw_reserve.p_pf2vf;
> + uint32_t checksum;
> uint32_t checkval;
> - char *str;
> +
> + if (adev->virt.fw_reserve.p_pf2vf == NULL)
> + return -EINVAL;
> +
> + if (pf2vf_info->size > 1024) {
> + DRM_ERROR("invalid pf2vf message size\n");
> + return -EINVAL;
> + }
> +
> + switch (pf2vf_info->version) {
> + case 1:
> + checksum = ((struct amdgim_pf2vf_info_v1
> *)pf2vf_info)->checksum;
> + checkval = amd_sriov_msg_checksum(
> + adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
> + adev->virt.fw_reserve.checksum_key, checksum);
> + if (checksum != checkval) {
> + DRM_ERROR("invalid pf2vf message\n");
> + return -EINVAL;
> + }
> +
> + adev->virt.gim_feature =
> + ((struct amdgim_pf2vf_info_v1
> *)pf2vf_info)->feature_flags;
> + break;
> + case 2:
> + /* TODO: missing key, need to add it later */
> + checksum = ((struct amd_sriov_msg_pf2vf_info
> *)pf2vf_info)->checksum;
> + checkval = amd_sriov_msg_checksum(
> + adev->virt.fw_reserve.p_pf2vf,
Re: [PATCH 1/3] SWDEV-220451 - Query guest's information by VF2PF message - Guest side - part 1
On Wed, Sep 16, 2020 at 11:05 AM Bokun Zhang wrote:
>
> - Add guest side change to support VF2PF message
> - Fix coding style
>
> Change-Id: I82e5518cb10ec0b19fecaba7e05b02f4b7f2b409
> Signed-off-by: Bokun Zhang
Please drop the SWDEV reference from the subject and prefix the patch
with drm/amdgpu: Also please provide a better patch subject and
description. It looks like you are just updating the vf2pf interface.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h| 29 +-
> drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 276
> 2 files changed, 285 insertions(+), 20 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index b2046c3a404d..082fb0736645 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -24,6 +24,8 @@
> #ifndef AMDGPU_VIRT_H
> #define AMDGPU_VIRT_H
>
> +#include "amdgv_sriovmsg.h"
> +
> #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
> #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this
> GPU */
> #define AMDGPU_SRIOV_CAPS_IS_VF(1 << 2) /* this GPU is a virtual
> function */
> @@ -79,7 +81,10 @@ struct amdgpu_virt_fw_reserve {
> struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
> unsigned int checksum_key;
> };
> +
> /*
> + * Legacy GIM header
> + *
> * Defination between PF and VF
> * Structures forcibly aligned to 4 to keep the same style as PF.
> */
> @@ -101,15 +106,7 @@ enum AMDGIM_FEATURE_FLAG {
> AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
> };
>
> -struct amd_sriov_msg_pf2vf_info_header {
> - /* the total structure size in byte. */
> - uint32_t size;
> - /* version of this structure, written by the GIM */
> - uint32_t version;
> - /* reserved */
> - uint32_t reserved[2];
> -} __aligned(4);
> -struct amdgim_pf2vf_info_v1 {
> +struct amdgim_pf2vf_info_v1 {
> /* header contains size and version */
> struct amd_sriov_msg_pf2vf_info_header header;
> /* max_width * max_height */
> @@ -128,6 +125,7 @@ struct amdgim_pf2vf_info_v1 {
> unsigned int checksum;
> } __aligned(4);
>
> +/* TODO: below struct is duplicated to amd_sriov_msg_pf2vf_info */
> struct amdgim_pf2vf_info_v2 {
> /* header contains size and version */
> struct amd_sriov_msg_pf2vf_info_header header;
> @@ -166,16 +164,6 @@ struct amdgim_pf2vf_info_v2 {
> uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (18 +
> sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 0)];
> } __aligned(4);
>
> -
> -struct amd_sriov_msg_vf2pf_info_header {
> - /* the total structure size in byte. */
> - uint32_t size;
> - /*version of this structure, written by the guest */
> - uint32_t version;
> - /* reserved */
> - uint32_t reserved[2];
> -} __aligned(4);
> -
> struct amdgim_vf2pf_info_v1 {
> /* header contains size and version */
> struct amd_sriov_msg_vf2pf_info_header header;
> @@ -237,8 +225,9 @@ struct amdgim_vf2pf_info_v2 {
> uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12
> + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
> } __aligned(4);
>
> +/* TODO: below macro and typedef will cause compile error, need to remove */
> #define AMDGPU_FW_VRAM_VF2PF_VER 2
> -typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
> +typedef struct amd_sriov_msg_vf2pf_info amdgim_vf2pf_info;
>
> #define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
> do { \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
> b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
> new file mode 100644
> index ..5355827ed0ae
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
> @@ -0,0 +1,276 @@
> +/*
> + * Copyright 2018-2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER
Re: [PATCH] drm/amd/display: Remove set but used 'temp'
On Tue, Sep 15, 2020 at 11:34 PM Ye Bin wrote:
>
> Addresses the following gcc warning with "make W=1":
>
> In file included from
> drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../dmub_srv.h:67:0,
> from drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn21.c:26:
> drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h: In function
> ‘dmub_rb_flush_pending’:
> drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h:795:12:
> warning: variable ‘temp’ set but not used
> [-Wunused-but-set-variable]
> uint64_t temp;
> ^
> In file included from
> drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../dmub_srv.h:67:0,
> from
> drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn30.c:26:
> drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h: In function
> ‘dmub_rb_flush_pending’:
> drivers/gpu/drm/amd/amdgpu/../display/dmub/src/../inc/dmub_cmd.h:795:12:
> warning: variable ‘temp’ set but not used
> [-Wunused-but-set-variable]
>uint64_t temp;
>
> Reported-by: Hulk Robot
> Signed-off-by: Ye Bin
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> index d7e7f2eda92f..e32828ffc3e0 100644
> --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> @@ -791,12 +791,10 @@ static inline void dmub_rb_flush_pending(const struct
> dmub_rb *rb)
>
> while (rptr != wptr) {
> uint64_t volatile *data = (uint64_t volatile
> *)rb->base_address + rptr / sizeof(uint64_t);
> - //uint64_t volatile *p = (uint64_t volatile *)data;
> - uint64_t temp;
> int i;
>
> for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
> - temp = *data++;
> + *data++;
>
> rptr += DMUB_RB_CMD_SIZE;
> if (rptr >= rb->capacity)
> --
> 2.16.2.dirty
>
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Re: [PATCH] drm/amdgpu: No sysfs, not an error condition
On Wed, Sep 16, 2020 at 1:09 PM Luben Tuikov wrote:
>
> Not being able to create amdgpu sysfs attributes
> is not a fatal error warranting not to continue
> to try to bring up the display. Thus, if we get
> an error trying to create amdgpu sysfs attrs,
> report it and continue on to try to bring up
> a display.
>
> Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 5d702f6e77de..62174f5e8311 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3400,10 +3400,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> flush_delayed_work(>delayed_init_work);
>
> r = sysfs_create_files(>dev->kobj, amdgpu_dev_attributes);
> - if (r) {
> + if (r)
> dev_err(adev->dev, "Could not create amdgpu device attr\n");
> - return r;
> - }
>
> if (IS_ENABLED(CONFIG_PERF_EVENTS))
> r = amdgpu_pmu_init(adev);
> --
> 2.28.0.394.ge197136389
>
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Re: [PATCH] drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700
On Wed, Sep 16, 2020 at 12:21 PM Tom St Denis wrote: > > This register was requested for umr debugging support. > > Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher > --- > .../amd/include/asic_reg/uvd/uvd_7_0_offset.h | 3 +++ > .../include/asic_reg/uvd/uvd_7_0_sh_mask.h| 20 +++ > 2 files changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h > b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h > index 07aceffb108a..524ba4421c17 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h > @@ -151,6 +151,8 @@ > #define mmUVD_LMI_CTRL2_BASE_IDX > 1 > #define mmUVD_MASTINT_EN > 0x0540 > #define mmUVD_MASTINT_EN_BASE_IDX > 1 > +#define mmUVD_FW_STATUS > 0x0557 > +#define mmUVD_FW_STATUS_BASE_IDX > 1 > #define mmJPEG_CGC_CTRL > 0x0565 > #define mmJPEG_CGC_CTRL_BASE_IDX > 1 > #define mmUVD_LMI_CTRL > 0x0566 > @@ -219,4 +221,5 @@ > #define mmUVD_CONTEXT_ID2_BASE_IDX > 1 > > > + > #endif > diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h > b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h > index b427f73bd536..919be1842bd5 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h > @@ -807,5 +807,25 @@ > #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT > 0x0 > #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK > 0xL > > +//UVD_FW_STATUS > +#define UVD_FW_STATUS__BUSY__SHIFT > 0x0 > +#define UVD_FW_STATUS__ACTIVE__SHIFT > 0x1 > +#define UVD_FW_STATUS__SEND_EFUSE_REQ__SHIFT > 0x2 > +#define UVD_FW_STATUS__DONE__SHIFT > 0x8 > +#define UVD_FW_STATUS__PASS__SHIFT > 0x10 > +#define UVD_FW_STATUS__FAIL__SHIFT > 0x11 > +#define UVD_FW_STATUS__INVALID_LEN__SHIFT > 0x12 > +#define UVD_FW_STATUS__INVALID_0_PADDING__SHIFT > 0x13 > +#define UVD_FW_STATUS__INVALID_NONCE__SHIFT > 0x14 > +#define UVD_FW_STATUS__BUSY_MASK > 0x0001L > +#define UVD_FW_STATUS__ACTIVE_MASK > 0x0002L > +#define UVD_FW_STATUS__SEND_EFUSE_REQ_MASK > 0x0004L > +#define UVD_FW_STATUS__DONE_MASK > 0x0100L > +#define UVD_FW_STATUS__PASS_MASK > 0x0001L > +#define UVD_FW_STATUS__FAIL_MASK > 0x0002L > +#define UVD_FW_STATUS__INVALID_LEN_MASK > 0x0004L > +#define UVD_FW_STATUS__INVALID_0_PADDING_MASK > 0x0008L > +#define UVD_FW_STATUS__INVALID_NONCE_MASK > 0x0010L > + > > #endif > -- > 2.26.2 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/15] drm/amd/display: [FW Promotion] Release 0.0.34
From: Anthony Koo
[Header Changes]
- Add new SCRATCH0 status bits for detecting restore state
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index f20d6df6def1..137613a60419 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0xd0772ca1b
+#define DMUB_FW_VERSION_GIT_HASH 0xf547f0b9d
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 33
+#define DMUB_FW_VERSION_REVISION 34
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
@@ -170,7 +170,7 @@ union dmub_fw_boot_status {
uint32_t dal_fw : 1;
uint32_t mailbox_rdy : 1;
uint32_t optimized_init_done : 1;
- uint32_t reserved : 29;
+ uint32_t restore_required : 1;
} bits;
uint32_t all;
};
@@ -179,6 +179,7 @@ enum dmub_fw_boot_status_bit {
DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0),
DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1),
DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2),
+ DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3),
};
/* Register bit definition for SCRATCH15 */
@@ -301,6 +302,10 @@ enum dmub_cmd_type {
DMUB_CMD__VBIOS = 128,
};
+enum dmub_out_cmd_type {
+ DMUB_OUT_CMD__NULL = 0,
+};
+
#pragma pack(push, 1)
struct dmub_cmd_header {
--
2.17.1
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[PATCH 06/15] drm/amd/display: eDP intermittent black screen during PnP
From: Peikang Zhang
[Why]
We dont's turn off backlight before power off eDP (VDD),
which is a violation of eDP specs.
[How]
Power off eDP backlight before power off eDP
Signed-off-by: Peikang Zhang
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 ++
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 1 +
6 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 81c026319ccd..dba338c88256 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -229,6 +229,8 @@ void dp_disable_link_phy(struct dc_link *link, enum
signal_type signal)
dp_receiver_power_ctrl(link, false);
if (signal == SIGNAL_TYPE_EDP) {
+ if (link->dc->hwss.edp_backlight_control)
+ link->dc->hwss.edp_backlight_control(link, false);
link->link_enc->funcs->disable_output(link->link_enc, signal);
link->dc->hwss.edp_power_control(link, false);
} else {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 1002ce9979dc..27a1262a20f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2890,6 +2890,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.setup_stereo = NULL,
.set_avmute = dce110_set_avmute,
.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
+ .edp_backlight_control = dce110_edp_backlight_control,
.edp_power_control = dce110_edp_power_control,
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
.set_cursor_position = dce110_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index a1d1559bb5d7..b24c8ae8b1ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -66,6 +66,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.get_hw_state = dcn10_get_hw_state,
.clear_status_bits = dcn10_clear_status_bits,
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+ .edp_backlight_control = dce110_edp_backlight_control,
.edp_power_control = dce110_edp_power_control,
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
.set_cursor_position = dcn10_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index 966e1790b9bf..072193c5ffe6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -68,6 +68,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
.get_hw_state = dcn10_get_hw_state,
.clear_status_bits = dcn10_clear_status_bits,
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+ .edp_backlight_control = dce110_edp_backlight_control,
.edp_power_control = dce110_edp_power_control,
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
.set_cursor_position = dcn10_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 2ba880c3943c..2b7396c9fcb4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -69,6 +69,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
.get_hw_state = dcn10_get_hw_state,
.clear_status_bits = dcn10_clear_status_bits,
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+ .edp_backlight_control = dce110_edp_backlight_control,
.edp_power_control = dce110_edp_power_control,
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
.set_cursor_position = dcn10_set_cursor_position,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 19daa456e3bf..7c90c506 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -69,6 +69,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
.get_hw_state = dcn10_get_hw_state,
.clear_status_bits = dcn10_clear_status_bits,
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+ .edp_backlight_control
[PATCH 03/15] drm/amd/display: 3.2.103
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d9b22d6a985a..d65483483d05 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.102" +#define DC_VER "3.2.103" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/15] drm/amd/display: Replace msleep with udelay while read edid return defer.
From: jinlong zhang
[why]
while read edid return defer, then it enter to msleep,
but it actually took more time during msleep,
this will cause remaining edid read fail.
[how]
Replacing msleep with udelay, it will not take any extra time, edid return pass
finally.
Signed-off-by: jinlong zhang
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 743042d5905a..cdcad82765e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -653,7 +653,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
if ((*payload->reply ==
AUX_TRANSACTION_REPLY_AUX_DEFER) ||
(*payload->reply ==
AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
if (payload->defer_delay > 0)
-
msleep(payload->defer_delay);
+
udelay(payload->defer_delay * 1000);
}
}
break;
--
2.17.1
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[PATCH 02/15] drm/amd/display: [FW Promotion] Release 0.0.33
From: Anthony Koo Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index a0bd502dc7d7..f20d6df6def1 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -36,10 +36,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x82f998da6 +#define DMUB_FW_VERSION_GIT_HASH 0xd0772ca1b #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 32 +#define DMUB_FW_VERSION_REVISION 33 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/15] drm/amd/display: TMDS Fallback transition
From: Chris Park
[Why]
HDMI requires fallback to TMDS by redetection
in order to switch PHY settings.
This avoids black out when link training fail
during mode setting, link quality update,
disable driver sequence.
[How]
Allow driver to redetect HDMI displays
based on retraining or fallback mechanism.
Signed-off-by: Chris Park
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 13 +
drivers/gpu/drm/amd/display/dc/dc_link.h| 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 0b9a4fc642ae..98b4d5e2e336 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -158,7 +158,20 @@ static bool validate_dsc_caps_on_connector(struct
amdgpu_dm_connector *aconnecto
u8 dsc_caps[16] = { 0 };
aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
+#if defined(CONFIG_HP_HOOK_WORKAROUND)
+ /*
+* drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
+* because it only check the dsc/fec caps of the "port variable" and
not the dock
+*
+* This case will return NULL: DSC capabe MST dock connected to a non
fec/dsc capable display
+*
+* Workaround: explicitly check the use case above and use the mst
dock's aux as dsc_aux
+*
+*/
+ if (!aconnector->dsc_aux && !port->parent->port_parent)
+ aconnector->dsc_aux = >mst_port->dm_dp_aux.aux;
+#endif
if (!aconnector->dsc_aux)
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index e002ef706e1d..266b93a705d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -237,6 +237,8 @@ enum dc_detect_reason {
DETECT_REASON_BOOT,
DETECT_REASON_HPD,
DETECT_REASON_HPDRX,
+ DETECT_REASON_FALLBACK,
+ DETECT_REASON_RETRAIN
};
bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
--
2.17.1
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[PATCH 08/15] drm/amd/display: Increase timeout for DP Disable
From: Wesley Chalmers [WHY] When disabling DP video, the current REG_WAIT timeout of 50ms is too low for certain cases with very high VSYNC intervals. [HOW] Increase the timeout to 102ms, so that refresh rates as low as 10Hz can be handled properly. Signed-off-by: Wesley Chalmers Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo Cc: --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c index 9cf139be3f40..f70fcadf1ee5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c @@ -896,10 +896,10 @@ void enc1_stream_encoder_dp_blank( */ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); /* Larger delay to wait until VBLANK - use max retry of -* 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode + +* 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode + * a little more because we may not trust delay accuracy. */ - max_retries = DP_BLANK_MAX_RETRY * 250; + max_retries = DP_BLANK_MAX_RETRY * 501; /* disable DP stream */ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/15] drm/amd/display: Fix ODM policy implementation
From: Wesley Chalmers
[WHY]
Only the leftmost ODM pipe should be offset when scaling. A previous
code change was intended to implement this policy, but a section of code
was overlooked.
Signed-off-by: Wesley Chalmers
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Cc:
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 4cea9344d8aa..e430148e47cf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -785,14 +785,15 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
/*
* Only the leftmost ODM pipe should be offset by a nonzero distance
*/
- if (!pipe_ctx->prev_odm_pipe)
+ if (!pipe_ctx->prev_odm_pipe) {
data->recout.x = stream->dst.x;
- else
- data->recout.x = 0;
- if (stream->src.x < surf_clip.x)
- data->recout.x += (surf_clip.x - stream->src.x) *
stream->dst.width
+ if (stream->src.x < surf_clip.x)
+ data->recout.x += (surf_clip.x - stream->src.x) *
stream->dst.width
/ stream->src.width;
+ } else
+ data->recout.x = 0;
+
data->recout.width = surf_clip.width * stream->dst.width /
stream->src.width;
if (data->recout.width + data->recout.x > stream->dst.x +
stream->dst.width)
data->recout.width = stream->dst.x + stream->dst.width -
data->recout.x;
--
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[PATCH 01/15] drm/amd/display: Fix incorrect backlight register offset for DCN
From: David Galiffi [Why] Typo in backlight refactor introduced wrong register offset. [How] SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2). Signed-off-by: David Galiffi Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo Cc: --- drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h index 99c68ca9c7e0..967d04d75b98 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h @@ -54,7 +54,7 @@ SR(BL_PWM_CNTL2), \ SR(BL_PWM_PERIOD_CNTL), \ SR(BL_PWM_GRP1_REG_LOCK), \ - SR(BIOS_SCRATCH_2) + NBIO_SR(BIOS_SCRATCH_2) #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/15] drm/amd/display: Check for flip pending before locking pipes.
From: Taimur Hassan
[Why]
When running a game/benchmark with v-sync disabled, disabling a plane
(which is v-sync) can cause an underflow. This is due to flips that are
pending before pipe locking being applied after locks are released and
pipes have been re-arranged or disconnected. This can potentially apply
a flip on the incorrect pipe.
[How]
Check that any pending flips are cleared before locking any pipes to
ensure flips are applied on the correct pipes.
Signed-off-by: Taimur Hassan
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 ++-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 12 ++--
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h| 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h| 2 +-
4 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 83ce55edb3aa..1efc823c2a14 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2324,7 +2324,6 @@ static void commit_planes_for_stream(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
{
- bool mpcc_disconnected = false;
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
@@ -2355,14 +2354,8 @@ static void commit_planes_for_stream(struct dc *dc,
context_clock_trace(dc, context);
}
- if (update_type != UPDATE_TYPE_FAST &&
dc->hwss.interdependent_update_lock &&
- dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
- dc->hwss.interdependent_update_lock(dc, context, true);
- mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
- dc->hwss.interdependent_update_lock(dc, context, false);
- if (mpcc_disconnected)
- dc->hwss.wait_for_pending_cleared(dc, context);
- }
+ if (update_type != UPDATE_TYPE_FAST &&
dc->hwss.interdependent_update_lock && dc->hwss.wait_for_pending_cleared)
+ dc->hwss.disconnect_pipes(dc, context);
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d0f3bf953d02..79fe9571cf5d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2761,7 +2761,7 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
return NULL;
}
-bool dcn10_disconnect_pipes(
+void dcn10_disconnect_pipes(
struct dc *dc,
struct dc_state *context)
{
@@ -2772,6 +2772,10 @@ bool dcn10_disconnect_pipes(
bool mpcc_disconnected = false;
struct pipe_ctx *old_pipe;
struct pipe_ctx *new_pipe;
+
+ dc->hwss.wait_for_pending_cleared(dc, context);
+ dc->hwss.interdependent_update_lock(dc, context, true);
+
DC_LOGGER_INIT(dc->ctx->logger);
/* Set pipe update flags and lock pipes */
@@ -2874,7 +2878,11 @@ bool dcn10_disconnect_pipes(
}
}
}
- return mpcc_disconnected;
+
+ dc->hwss.interdependent_update_lock(dc, context, false);
+
+ if (mpcc_disconnected)
+ dc->hwss.wait_for_pending_cleared(dc, context);
}
void dcn10_wait_for_pending_cleared(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index e5691e499023..9a0f7a8a85cd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -194,7 +194,7 @@ void dcn10_get_surface_visual_confirm_color(
void dcn10_get_hdr_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
-bool dcn10_disconnect_pipes(
+void dcn10_disconnect_pipes(
struct dc *dc,
struct dc_state *context);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 64c1be818b0e..f48ee24d42f9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -67,7 +67,7 @@ struct hw_sequencer_funcs {
int num_planes, struct dc_state *context);
void (*program_front_end_for_ctx)(struct dc *dc,
struct dc_state *context);
- bool (*disconnect_pipes)(struct dc *dc,
+ void (*disconnect_pipes)(struct dc *dc,
struct dc_state *context);
void
[PATCH 11/15] drm/amd/display: Implement PSR wait for enable/disable
From: Wyatt Wood
[Why]
For DMUB implementation of PSR, the 'wait' parameter,
used to determine if driver should wait for PSR enable/disable,
is not implemented correctly.
[How]
Implement wait for PSR enable/disable.
Signed-off-by: Wyatt Wood
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 27 ++-
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 2 +-
3 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 1871ff6119ae..f13396254b5d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2566,7 +2566,7 @@ bool dc_link_set_psr_allow_active(struct dc_link *link,
bool allow_active, bool
link->psr_settings.psr_allow_active = allow_active;
if (psr != NULL && link->psr_settings.psr_feature_enabled)
- psr->funcs->psr_enable(psr, allow_active);
+ psr->funcs->psr_enable(psr, allow_active, wait);
else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
link->psr_settings.psr_feature_enabled)
dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
else
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 5167d6b8a48d..bf24f1029547 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -119,10 +119,11 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub,
struct dc_stream_state *
/**
* Enable/Disable PSR.
*/
-static void dmub_psr_enable(struct dmub_psr *dmub, bool enable)
+static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
{
union dmub_rb_cmd cmd;
struct dc_context *dc = dmub->ctx;
+ uint32_t retry_count, psr_state = 0;
cmd.psr_enable.header.type = DMUB_CMD__PSR;
@@ -136,6 +137,30 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool
enable)
dc_dmub_srv_cmd_queue(dc->dmub_srv, );
dc_dmub_srv_cmd_execute(dc->dmub_srv);
dc_dmub_srv_wait_idle(dc->dmub_srv);
+
+ /* Below loops 1000 x 500us = 500 ms.
+* Exit PSR may need to wait 1-2 frames to power up. Timeout after at
+* least a few frames. Should never hit the max retry assert below.
+*/
+ if (wait) {
+ for (retry_count = 0; retry_count <= 1000; retry_count++) {
+ dmub_psr_get_state(dmub, _state);
+
+ if (enable) {
+ if (psr_state != 0)
+ break;
+ } else {
+ if (psr_state == 0)
+ break;
+ }
+
+ udelay(500);
+ }
+
+ /* assert if max retry hit */
+ if (retry_count >= 1000)
+ ASSERT(0);
+ }
}
/**
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index f404fecd6410..dc121ed92d2e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -36,7 +36,7 @@ struct dmub_psr {
struct dmub_psr_funcs {
bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link,
struct psr_context *psr_context);
- void (*psr_enable)(struct dmub_psr *dmub, bool enable);
+ void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait);
void (*psr_get_state)(struct dmub_psr *dmub, uint32_t *psr_state);
void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level);
};
--
2.17.1
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[PATCH 10/15] drm/amd/display: allow DP RX to use more cr aux rd interval delay
From: Wenjing Liu
[why]
Regression is caused by previous change with attempt to correct the
extended cr aux rd interval delay due to mis interpretation of the DP specs.
I4b4f508e30e5218ffeb7e40cc19e6dc54357361e
The change turns out not working well with certain RXs.
So we decided to keep the cr aux rd interval logic as before.
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 47fb09f41bfb..232d77721ad9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -49,6 +49,23 @@ static struct dc_link_settings
get_common_supported_link_settings(
struct dc_link_settings link_setting_a,
struct dc_link_settings link_setting_b);
+static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
+ const struct dc_link_settings *link_settings)
+{
+ union training_aux_rd_interval training_rd_interval;
+ uint32_t wait_in_micro_secs = 100;
+
+ memset(_rd_interval, 0, sizeof(training_rd_interval));
+ core_link_read_dpcd(
+ link,
+ DP_TRAINING_AUX_RD_INTERVAL,
+ (uint8_t *)_rd_interval,
+ sizeof(training_rd_interval));
+ if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
+ wait_in_micro_secs =
training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
+ return wait_in_micro_secs;
+}
+
static uint32_t get_eq_training_aux_rd_interval(
struct dc_link *link,
const struct dc_link_settings *link_settings)
@@ -1251,7 +1268,7 @@ static void initialize_training_settings(
if (overrides->cr_pattern_time != NULL)
lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
else
- lt_settings->cr_pattern_time = 100;
+ lt_settings->cr_pattern_time =
get_cr_training_aux_rd_interval(link, link_setting);
if (overrides->eq_pattern_time != NULL)
lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
--
2.17.1
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[PATCH 05/15] drm/amd/display: Bug in dce_is_panel_backlight_on()
From: Peikang Zhang
[Why]
dce_is_panel_backlight_on() will return wrong value if
LVTMA_BLON_OVRD is 0
[How]
When LVTMA_BLON_OVRD is 0, read
LVTMA_PWRSEQ_TARGET_STATE instead
Signed-off-by: Peikang Zhang
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c | 10 +++---
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 4
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
index df7f826eebd8..74f7619d4154 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
@@ -159,11 +159,15 @@ static uint32_t dce_panel_cntl_hw_init(struct panel_cntl
*panel_cntl)
static bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl)
{
struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
- uint32_t value;
+ uint32_t blon, blon_ovrd, pwrseq_target_state;
- REG_GET(PWRSEQ_CNTL, LVTMA_BLON, );
+ REG_GET_2(PWRSEQ_CNTL, LVTMA_BLON, , LVTMA_BLON_OVRD, _ovrd);
+ REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, _target_state);
- return value;
+ if (blon_ovrd)
+ return blon;
+ else
+ return pwrseq_target_state;
}
static bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
index 967d04d75b98..6bd1196083a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
@@ -61,8 +61,10 @@
#define DCE_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
+ DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON_OVRD, mask_sh),\
DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
+ DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE,
mask_sh), \
DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R,
mask_sh), \
DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
DCE_PANEL_CNTL_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
@@ -76,8 +78,10 @@
#define DCE_PANEL_CNTL_REG_FIELD_LIST(type) \
type LVTMA_BLON;\
+ type LVTMA_BLON_OVRD;\
type LVTMA_DIGON;\
type LVTMA_DIGON_OVRD;\
+ type LVTMA_PWRSEQ_TARGET_STATE; \
type LVTMA_PWRSEQ_TARGET_STATE_R; \
type BL_PWM_REF_DIV; \
type BL_PWM_EN; \
--
2.17.1
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[PATCH 09/15] drm/amd/display: Enable DP YCbCr420 mode support for DCN10
From: Gary Li
[WHY]
In DCN10 when a panel with YCbCr420 capability is connected via
USB-C to HDMI active dongle, no YCbCr420 option is listed in
Radeon settings.
[HOW]
Enable DP YCbCr420 mode support for DCN10
Signed-off-by: Gary Li
Reviewed-by: Eric Yang
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 1abd81e17f09..a78712caf124 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -798,7 +798,7 @@ static const struct encoder_feature_support
link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 60,
.hdmi_ycbcr420_supported = true,
- .dp_ycbcr420_supported = false,
+ .dp_ycbcr420_supported = true,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
--
2.17.1
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[PATCH 00/15] DC Patches September 21, 2020
This DC patchset brings improvements in multiple areas. In summary, we have: * DC version 3.2.104. * DMUB Firmware release 0.0.34. * Improve on HDMI fallback mechanism. * Enable DP YCbCr420 mode support for DCN10 ASICs. * Bug fixes for backlight, ODM, eDP and others. -- Anthony Koo (2): drm/amd/display: [FW Promotion] Release 0.0.33 drm/amd/display: [FW Promotion] Release 0.0.34 Aric Cyr (2): drm/amd/display: 3.2.103 drm/amd/display: 3.2.104 Chris Park (1): drm/amd/display: TMDS Fallback transition David Galiffi (1): drm/amd/display: Fix incorrect backlight register offset for DCN Gary Li (1): drm/amd/display: Enable DP YCbCr420 mode support for DCN10 Peikang Zhang (2): drm/amd/display: Bug in dce_is_panel_backlight_on() drm/amd/display: eDP intermittent black screen during PnP Taimur Hassan (1): drm/amd/display: Check for flip pending before locking pipes. Wenjing Liu (1): drm/amd/display: allow DP RX to use more cr aux rd interval delay Wesley Chalmers (2): drm/amd/display: Fix ODM policy implementation drm/amd/display: Increase timeout for DP Disable Wyatt Wood (1): drm/amd/display: Implement PSR wait for enable/disable jinlong zhang (1): drm/amd/display: Replace msleep with udelay while read edid return defer. .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 13 + drivers/gpu/drm/amd/display/dc/core/dc.c | 11 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 19 - .../drm/amd/display/dc/core/dc_link_hwss.c| 2 ++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 11 drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_link.h | 2 ++ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +- .../drm/amd/display/dc/dce/dce_panel_cntl.c | 10 --- .../drm/amd/display/dc/dce/dce_panel_cntl.h | 6 - drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 27 ++- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 2 +- .../display/dc/dce110/dce110_hw_sequencer.c | 1 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 +++-- .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 1 + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- .../display/dc/dcn10/dcn10_stream_encoder.c | 4 +-- .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 + .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 1 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +--- 24 files changed, 113 insertions(+), 34 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 15/15] drm/amd/display: 3.2.104
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d65483483d05..061ca15660ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.103" +#define DC_VER "3.2.104" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Add missing "Copy GSL groups when committing a new context"
On 2020-09-16 1:08 p.m., Bhawanpreet Lakha wrote:
[Why]
"Copy GSL groups when committing a new context" patch was accidentally
removed during a refactor
Patch: 21ffcc94d5b ("drm/amd/display: Copy GSL groups when committing a new
context")
[How]
Re add it
Fixes: b6e881c9474 ("drm/amd/display: update navi to use new surface programming
behaviour")
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 5720b6e5d321..01530e686f43 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1642,6 +1642,17 @@ void dcn20_program_front_end_for_ctx(
struct dce_hwseq *hws = dc->hwseq;
DC_LOGGER_INIT(dc->ctx->logger);
+ /* Carry over GSL groups in case the context is changing. */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
+ struct pipe_ctx *old_pipe_ctx =
+ >current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->stream == old_pipe_ctx->stream)
+ pipe_ctx->stream_res.gsl_group =
+ old_pipe_ctx->stream_res.gsl_group;
+ }
+
if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[i];
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[PATCH v3 2/3] drm/amdkfd: Add process eviction counters to sysfs
Add per-process eviction counters to sysfs to keep track of
how many eviction events have happened for each process.
v2: rename the stats dir, and track all evictions per process, per device.
v3: Simplify the stats kobject handling and cleanup.
Signed-off-by: Philip Cox
---
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 9 ++
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 97 +++
3 files changed, 114 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index cafbc3aa980a..5b9e0df2a90e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -653,6 +653,7 @@ static int evict_process_queues_nocpsch(struct
device_queue_manager *dqm,
pr_info_ratelimited("Evicting PASID 0x%x queues\n",
pdd->process->pasid);
+ pdd->last_evict_timestamp = get_jiffies_64();
/* Mark all queues as evicted. Deactivate all active queues on
* the qpd.
*/
@@ -714,6 +715,7 @@ static int evict_process_queues_cpsch(struct
device_queue_manager *dqm,
q->properties.is_active = false;
decrement_queue_count(dqm, q->properties.type);
}
+ pdd->last_evict_timestamp = get_jiffies_64();
retval = execute_queues_cpsch(dqm,
qpd->is_debug ?
KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
@@ -732,6 +734,7 @@ static int restore_process_queues_nocpsch(struct
device_queue_manager *dqm,
struct mqd_manager *mqd_mgr;
struct kfd_process_device *pdd;
uint64_t pd_base;
+ uint64_t eviction_duration;
int retval, ret = 0;
pdd = qpd_to_pdd(qpd);
@@ -799,6 +802,8 @@ static int restore_process_queues_nocpsch(struct
device_queue_manager *dqm,
ret = retval;
}
qpd->evicted = 0;
+ eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
+ atomic64_add(eviction_duration, >evict_duration_counter);
out:
if (mm)
mmput(mm);
@@ -812,6 +817,7 @@ static int restore_process_queues_cpsch(struct
device_queue_manager *dqm,
struct queue *q;
struct kfd_process_device *pdd;
uint64_t pd_base;
+ uint64_t eviction_duration;
int retval = 0;
pdd = qpd_to_pdd(qpd);
@@ -845,6 +851,9 @@ static int restore_process_queues_cpsch(struct
device_queue_manager *dqm,
retval = execute_queues_cpsch(dqm,
KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
qpd->evicted = 0;
+ eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
+ atomic64_add(eviction_duration, >evict_duration_counter);
+
out:
dqm_unlock(dqm);
return retval;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 023629f28495..a500fe611b43 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -631,7 +631,7 @@ enum kfd_pdd_bound {
PDD_BOUND_SUSPENDED,
};
-#define MAX_SYSFS_FILENAME_LEN 11
+#define MAX_SYSFS_FILENAME_LEN 15
/*
* SDMA counter runs at 100MHz frequency.
@@ -692,6 +692,13 @@ struct kfd_process_device {
uint64_t sdma_past_activity_counter;
struct attribute attr_sdma;
char sdma_filename[MAX_SYSFS_FILENAME_LEN];
+
+ /* Eviction activity tracking */
+ unsigned long last_evict_timestamp;
+ atomic64_t evict_duration_counter;
+ struct attribute attr_evict;
+
+ struct kobject *kobj_stats;
};
#define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 1e15aa7d8ae8..b4ba394ad599 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -344,6 +344,26 @@ static ssize_t kfd_procfs_queue_show(struct kobject *kobj,
return 0;
}
+static ssize_t kfd_procfs_stats_show(struct kobject *kobj,
+struct attribute *attr, char *buffer)
+{
+ if (strcmp(attr->name, "evicted_ms") == 0) {
+ struct kfd_process_device *pdd = container_of(attr,
+ struct kfd_process_device,
+ attr_evict);
+ uint64_t evict_jiffies;
+
+ evict_jiffies = atomic64_read(>evict_duration_counter);
+
+ return snprintf(buffer,
+ PAGE_SIZE,
+ "%llu\n",
+ jiffies64_to_msecs(evict_jiffies));
+ } else
+ pr_err("Invalid attribute");
+
+ return 0;
+}
static struct attribute attr_queue_size = {
.name =
Re: [PATCH v2 21/21] drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver
Am 15.09.20 um 16:59 schrieb Thomas Zimmermann:
> Several GEM and PRIME callbacks have been deprecated in favor of
> per-instance GEM object functions. Remove the callbacks as they are
> now unused. The only exception is .gem_prime_mmap, which is still
> in use by several drivers.
>
> What is also gone is gem_vm_ops in struct drm_driver. All drivers now
> use struct drm_gem_object_funcs.vm_ops instead.
>
> While at it, the patch also improves error handling around calls
> to .free and .get_sg_table callbacks.
>
> v2:
> * update related TODO item (Sam)
>
> Signed-off-by: Thomas Zimmermann
> ---
> Documentation/gpu/todo.rst | 7 +--
> drivers/gpu/drm/drm_gem.c| 35 +++-
> drivers/gpu/drm/drm_gem_cma_helper.c | 6 +-
> drivers/gpu/drm/drm_prime.c | 17 +++---
> include/drm/drm_drv.h| 85 ++--
> 5 files changed, 25 insertions(+), 125 deletions(-)
>
> diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
> index b0ea17da8ff6..0fc6bc222392 100644
> --- a/Documentation/gpu/todo.rst
> +++ b/Documentation/gpu/todo.rst
> @@ -289,11 +289,8 @@ struct drm_gem_object_funcs
> ---
>
> GEM objects can now have a function table instead of having the callbacks on
> the
> -DRM driver struct. This is now the preferred way and drivers can be moved
> over.
> -
> -We also need a 2nd version of the CMA define that doesn't require the
> -vmapping to be present (different hook for prime importing). Plus this needs
> to
> -be rolled out to all drivers using their own implementations, too.
> +DRM driver struct. This is now the preferred way. Callbacks in drivers have
> been
> +converted, except for struct drm_driver.gem_prime_mmap.
>
> Level: Intermediate
>
> diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
> index 19d73868490e..96945bed8291 100644
> --- a/drivers/gpu/drm/drm_gem.c
> +++ b/drivers/gpu/drm/drm_gem.c
> @@ -247,12 +247,9 @@ drm_gem_object_release_handle(int id, void *ptr, void
> *data)
> {
> struct drm_file *file_priv = data;
> struct drm_gem_object *obj = ptr;
> - struct drm_device *dev = obj->dev;
>
> if (obj->funcs && obj->funcs->close)
> obj->funcs->close(obj, file_priv);
> - else if (dev->driver->gem_close_object)
> - dev->driver->gem_close_object(obj, file_priv);
>
> drm_gem_remove_prime_handles(obj, file_priv);
> drm_vma_node_revoke(>vma_node, file_priv);
> @@ -407,10 +404,6 @@ drm_gem_handle_create_tail(struct drm_file *file_priv,
> ret = obj->funcs->open(obj, file_priv);
> if (ret)
> goto err_revoke;
> - } else if (dev->driver->gem_open_object) {
> - ret = dev->driver->gem_open_object(obj, file_priv);
> - if (ret)
> - goto err_revoke;
> }
>
> *handlep = handle;
> @@ -982,12 +975,11 @@ drm_gem_object_free(struct kref *kref)
> {
> struct drm_gem_object *obj =
> container_of(kref, struct drm_gem_object, refcount);
> - struct drm_device *dev = obj->dev;
>
> - if (obj->funcs)
> - obj->funcs->free(obj);
> - else if (dev->driver->gem_free_object_unlocked)
> - dev->driver->gem_free_object_unlocked(obj);
> + if (drm_WARN_ON_ONCE(obj->dev, !obj->funcs || !obj->funcs->free))
> + return;
> +
> + obj->funcs->free(obj);
> }
> EXPORT_SYMBOL(drm_gem_object_free);
>
> @@ -1049,9 +1041,9 @@ EXPORT_SYMBOL(drm_gem_vm_close);
> * @obj_size: the object size to be mapped, in bytes
> * @vma: VMA for the area to be mapped
> *
> - * Set up the VMA to prepare mapping of the GEM object using the gem_vm_ops
> - * provided by the driver. Depending on their requirements, drivers can
> either
> - * provide a fault handler in their gem_vm_ops (in which case any accesses to
> + * Set up the VMA to prepare mapping of the GEM object using the GEM object's
> + * vm_ops. Depending on their requirements, GEM objects can either
> + * provide a fault handler in their vm_ops (in which case any accesses to
> * the object will be trapped, to perform migration, GTT binding, surface
> * register allocation, or performance monitoring), or mmap the buffer memory
> * synchronously after calling drm_gem_mmap_obj.
> @@ -1065,12 +1057,11 @@ EXPORT_SYMBOL(drm_gem_vm_close);
> * callers must verify access restrictions before calling this helper.
> *
> * Return 0 or success or -EINVAL if the object size is smaller than the VMA
> - * size, or if no gem_vm_ops are provided.
> + * size, or if no vm_ops are provided.
> */
> int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
>struct vm_area_struct *vma)
> {
> - struct drm_device *dev = obj->dev;
> int ret;
>
> /* Check for valid size. */
> @@ -1095,8 +1086,6 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj,
>
Re: [PATCH] drm/amdgpu: No sysfs, not an error condition
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Slava Abramov
From: amd-gfx on behalf of Luben Tuikov
Sent: Wednesday, September 16, 2020 1:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Tuikov, Luben
Subject: [PATCH] drm/amdgpu: No sysfs, not an error condition
Not being able to create amdgpu sysfs attributes
is not a fatal error warranting not to continue
to try to bring up the display. Thus, if we get
an error trying to create amdgpu sysfs attrs,
report it and continue on to try to bring up
a display.
Signed-off-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5d702f6e77de..62174f5e8311 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3400,10 +3400,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
flush_delayed_work(>delayed_init_work);
r = sysfs_create_files(>dev->kobj, amdgpu_dev_attributes);
- if (r) {
+ if (r)
dev_err(adev->dev, "Could not create amdgpu device attr\n");
- return r;
- }
if (IS_ENABLED(CONFIG_PERF_EVENTS))
r = amdgpu_pmu_init(adev);
--
2.28.0.394.ge197136389
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[PATCH] drm/amd/display: Add missing "Copy GSL groups when committing a new context"
[Why]
"Copy GSL groups when committing a new context" patch was accidentally
removed during a refactor
Patch: 21ffcc94d5b ("drm/amd/display: Copy GSL groups when committing a new
context")
[How]
Re add it
Fixes: b6e881c9474 ("drm/amd/display: update navi to use new surface
programming behaviour")
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 5720b6e5d321..01530e686f43 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1642,6 +1642,17 @@ void dcn20_program_front_end_for_ctx(
struct dce_hwseq *hws = dc->hwseq;
DC_LOGGER_INIT(dc->ctx->logger);
+ /* Carry over GSL groups in case the context is changing. */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
+ struct pipe_ctx *old_pipe_ctx =
+ >current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->stream == old_pipe_ctx->stream)
+ pipe_ctx->stream_res.gsl_group =
+ old_pipe_ctx->stream_res.gsl_group;
+ }
+
if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[i];
--
2.25.1
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[PATCH] drm/amdgpu: No sysfs, not an error condition
Not being able to create amdgpu sysfs attributes
is not a fatal error warranting not to continue
to try to bring up the display. Thus, if we get
an error trying to create amdgpu sysfs attrs,
report it and continue on to try to bring up
a display.
Signed-off-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5d702f6e77de..62174f5e8311 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3400,10 +3400,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
flush_delayed_work(>delayed_init_work);
r = sysfs_create_files(>dev->kobj, amdgpu_dev_attributes);
- if (r) {
+ if (r)
dev_err(adev->dev, "Could not create amdgpu device attr\n");
- return r;
- }
if (IS_ENABLED(CONFIG_PERF_EVENTS))
r = amdgpu_pmu_init(adev);
--
2.28.0.394.ge197136389
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[PATCH] drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700
This register was requested for umr debugging support. Signed-off-by: Tom St Denis --- .../amd/include/asic_reg/uvd/uvd_7_0_offset.h | 3 +++ .../include/asic_reg/uvd/uvd_7_0_sh_mask.h| 20 +++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h index 07aceffb108a..524ba4421c17 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h @@ -151,6 +151,8 @@ #define mmUVD_LMI_CTRL2_BASE_IDX 1 #define mmUVD_MASTINT_EN 0x0540 #define mmUVD_MASTINT_EN_BASE_IDX 1 +#define mmUVD_FW_STATUS 0x0557 +#define mmUVD_FW_STATUS_BASE_IDX 1 #define mmJPEG_CGC_CTRL 0x0565 #define mmJPEG_CGC_CTRL_BASE_IDX 1 #define mmUVD_LMI_CTRL 0x0566 @@ -219,4 +221,5 @@ #define mmUVD_CONTEXT_ID2_BASE_IDX 1 + #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h index b427f73bd536..919be1842bd5 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h @@ -807,5 +807,25 @@ #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xL +//UVD_FW_STATUS +#define UVD_FW_STATUS__BUSY__SHIFT 0x0 +#define UVD_FW_STATUS__ACTIVE__SHIFT 0x1 +#define UVD_FW_STATUS__SEND_EFUSE_REQ__SHIFT 0x2 +#define UVD_FW_STATUS__DONE__SHIFT 0x8 +#define UVD_FW_STATUS__PASS__SHIFT 0x10 +#define UVD_FW_STATUS__FAIL__SHIFT 0x11 +#define UVD_FW_STATUS__INVALID_LEN__SHIFT 0x12 +#define UVD_FW_STATUS__INVALID_0_PADDING__SHIFT 0x13 +#define UVD_FW_STATUS__INVALID_NONCE__SHIFT 0x14 +#define UVD_FW_STATUS__BUSY_MASK 0x0001L +#define UVD_FW_STATUS__ACTIVE_MASK 0x0002L +#define UVD_FW_STATUS__SEND_EFUSE_REQ_MASK 0x0004L +#define UVD_FW_STATUS__DONE_MASK 0x0100L +#define UVD_FW_STATUS__PASS_MASK 0x0001L +#define UVD_FW_STATUS__FAIL_MASK 0x0002L +#define UVD_FW_STATUS__INVALID_LEN_MASK 0x0004L +#define UVD_FW_STATUS__INVALID_0_PADDING_MASK 0x0008L +#define UVD_FW_STATUS__INVALID_NONCE_MASK 0x0010L + #endif -- 2.26.2 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH -next 0/8] drm/amd/amdgpu: fix comparison pointer to bool warning
On Wed, Sep 16, 2020 at 04:02:18PM +0200, Christian König wrote: > Am 16.09.20 um 15:36 schrieb Alex Deucher: > > On Wed, Sep 16, 2020 at 3:51 AM Daniel Vetter wrote: > > > On Wed, Sep 16, 2020 at 09:38:34AM +0200, Christian König wrote: > > > > Am 15.09.20 um 21:35 schrieb Ville Syrjälä: > > > > > On Tue, Sep 15, 2020 at 03:16:32PM -0400, Alex Deucher wrote: > > > > > > I question the value of these warnings. Why even have a boolean > > > > > > type > > > > > > if you are going to get warnings when you use them... > > > > > > That said, applied to avoid getting these patches again and again > > > > > > every time someone sees this. > > > > > if (this_is_sparta) > > > > > if (this_is_sparta == true) > > > > > if (this_is_sparta != false) > > > > > > > > > > I think the first one reads the best, and avoids having to > > > > > decide between truth and falsehood :) > > > > +1 > > > +1, especially because we also have the inversion when using negative > > > errno codes for failures and 0 as success, which results in > > > > > > if (errno == 0) /* success case */ > > > > > > but > > > if (bool == 0) /* failure case */ > > > > > > now creative people do sometimes > > > > > > if (!errno) /* success case */ > > > > > > which I think is horribly confusing. So imo for more easier telling apart > > > of these too I think consistently using the short form for booleans, and > > > consistently using the more explicit long form for errno checks is a Very > > > Good Pattern :-) > > I don't disagree with your logic, but we regularly get patches to > > convert errno checks to drop the direct comparison because that is the > > "preferred kernel style". Arguably, we should be explicit in all > > cases as that avoids all confusion. With that in mind, my original > > point stands. Why have a type when comparisons against valid settings > > for that type produce errors? Oh, I didn't know that this happens for errno too. I withdraw my +1 and concur this is a bikeshed. I guess still applying to shut up the patch stream is the most reasonable thing :-/ -Daniel > Well it isn't an error, but raising a nice warning is most likely a good > idea. > > Christian. > > > > > Alex > > > > > Cheers, Daniel > > > > > > > Christian. > > > > > > > > > > Alex > > > > > > > > > > > > On Wed, Sep 9, 2020 at 9:21 AM Christian König > > > > > > wrote: > > > > > > > Acked-by: Christian König for the > > > > > > > series. > > > > > > > > > > > > > > Am 09.09.20 um 15:07 schrieb Zheng Bin: > > > > > > > > Zheng Bin (8): > > > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > > > gfx_v9_0.c > > > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > > > gfx_v10_0.c > > > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > > > sdma_v5_0.c > > > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > > > sdma_v5_2.c > > > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > > > si.c > > > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > > > uvd_v6_0.c > > > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > > >amdgpu_atpx_handler.c > > > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > > > sdma_v4_0.c > > > > > > > > > > > > > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 4 ++-- > > > > > > > > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- > > > > > > > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 2 +- > > > > > > > > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- > > > > > > > > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- > > > > > > > > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +- > > > > > > > > drivers/gpu/drm/amd/amdgpu/si.c | 2 +- > > > > > > > > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 4 ++-- > > > > > > > > 8 files changed, 11 insertions(+), 11 deletions(-) > > > > > > > > > > > > > > > > -- > > > > > > > > 2.26.0.106.g9fadedd > > > > > > > > > > > > > > > ___ > > > > > > > amd-gfx mailing list > > > > > > > amd-gfx@lists.freedesktop.org > > > > > > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cchristian.koenig%40amd.com%7Cdc7a8d7517d341e3a80c08d85a458ba8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637358602051676053sdata=MS0vcBcU7unXjEFlbd8kLbJkJ4sKcvIdLjc8yhX4UUI%3Dreserved=0 > > > > > > ___ > > > > > > dri-devel mailing list > > > > > > dri-de...@lists.freedesktop.org > > > > > >
Re: [PATCH v2 0/4] Enlarge tracepoints in the display component
On 2020-09-16 5:12 a.m., Daniel Vetter wrote: On Fri, Sep 11, 2020 at 10:59:23AM -0400, Rodrigo Siqueira wrote: Debug issues related to display can be a challenge due to the complexity around this topic and different source of information might help in this process. We already have support for tracepoints inside the display component, i.e., we have the basic functionalities available and we just need to expand it in order to make it more valuable for debugging. For this reason, this patchset reworks part of the current tracepoint options and add different sets of tracing inside amdgpu_dm, display core, and DCN10. The first patch of this series just rework part of the current tracepoints and the last set of patches introduces new tracepoints. This first patchset version is functional. Please, let me know what I can improve in the current version but also let me know what kind of tracepoint I can add for the next version. Finally, I want to highlight that this work is based on a set of patches originally made by Nicholas Kazlauskas. Change in V2: - I added another patch for capturing the clock state for different display architecture. Hm I'm not super sure tracepoints for state dumping are the right thing here. We kinda have the atomic state dumping code with all the various callbacks, and you can extend that pretty easily. Gives you full state dump in debugfs, plus a few function to dump into dmesg. Maybe what we need is a function to dump this also into printk tracepoint (otoh with Sean Paul's tracepoint work we'd get that through the dmesg stuff already), and then you could do it there? Upside is that for customers they'd get a much more consistent way to debug display issues across different drivers. For low-level hw debug what we do is give the hw guys an mmio trace, and they replay it on the fancy boxes :-) So for that I think this here is again too high level, but maybe what you have is a bit different. -Daniel We have raw register traces, but what I find most useful is to be able to see are the incoming DRM IOCTLs, objects and properties per commit. Many of the bugs we see in display code is in the conversion from DRM -> DM -> DC state. The current HW state is kind of useless in most cases, but the sequence helps track down intermittent problems and understand state transitions. Tracepoints provide everything I really need to be able to track down these problems without falling back to a full debugger. The existing DRM prints (even at high logging levels) aren't enough to understand what's going on in most cases in our driver so funneling those into tracepoints to improve perf doesn't really help that much. I think this kind of idea was rejected for DRM core last year with Sean's patch series but if we can't get them into core then I'd like to get them into our driver at least. These are a cleaned up version of Sean's work + my work that I end up applying locally whenever I debug something. Regards, Nicholas Kazlauskas Rodrigo Siqueira (4): drm/amd/display: Rework registers tracepoint drm/amd/display: Add tracepoint for amdgpu_dm drm/amd/display: Add pipe_state tracepoint drm/amd/display: Add tracepoint for capturing clocks state .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 + .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 712 +- .../dc/clk_mgr/dce112/dce112_clk_mgr.c| 5 + .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c| 4 + .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 4 + .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 4 + .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 4 + drivers/gpu/drm/amd/display/dc/core/dc.c | 11 + .../gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 5 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 17 +- 10 files changed, 747 insertions(+), 36 deletions(-) -- 2.28.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/3] SWDEV-220451 - Query guest's information by VF2PF message - Guest side - part 2
- Add VF2PF message support
- Remove incorrect Macro to avoid compile error
- Remove duplicated struct and use amdgv_sriovmsg.h
Change-Id: I8175d304871f4b5aab75fd071a6bdf8008137dbe
Signed-off-by: Bokun Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 244 -
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 75 +--
3 files changed, 198 insertions(+), 125 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5d702f6e77de..483ec0136332 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3443,8 +3443,10 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
/* make sure IB test finished before entering exclusive mode
* to avoid preemption on IB test
* */
- if (amdgpu_sriov_vf(adev))
+ if (amdgpu_sriov_vf(adev)) {
amdgpu_virt_request_full_gpu(adev, false);
+ amdgpu_virt_fini_data_exchange(adev);
+ }
/* disable all interrupts */
amdgpu_irq_disable_all(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index f76961d17246..1f1171812e35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -31,6 +31,12 @@
#include "soc15.h"
#include "nv.h"
+#define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \
+ do { \
+ vf2pf_info->ucode_info[ucode].id = ucode; \
+ vf2pf_info->ucode_info[ucode].version = ver; \
+ } while (0)
+
bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
{
/* By now all MMIO pages except mailbox are blocked */
@@ -239,10 +245,10 @@ void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
}
-int amdgpu_virt_fw_reserve_get_checksum(void *obj,
- unsigned long obj_size,
- unsigned int key,
- unsigned int chksum)
+unsigned int amd_sriov_msg_checksum(void *obj,
+ unsigned long obj_size,
+ unsigned int key,
+ unsigned int checksum)
{
unsigned int ret = key;
unsigned long i = 0;
@@ -252,9 +258,9 @@ int amdgpu_virt_fw_reserve_get_checksum(void *obj,
/* calculate checksum */
for (i = 0; i < obj_size; ++i)
ret += *(pos + i);
- /* minus the chksum itself */
- pos = (char *)
- for (i = 0; i < sizeof(chksum); ++i)
+ /* minus the checksum itself */
+ pos = (char *)
+ for (i = 0; i < sizeof(checksum); ++i)
ret -= *(pos + i);
return ret;
}
@@ -415,33 +421,187 @@ static void amdgpu_virt_add_bad_page(struct
amdgpu_device *adev,
}
}
-void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
+static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
{
- uint32_t pf2vf_size = 0;
- uint32_t checksum = 0;
+ struct amd_sriov_msg_pf2vf_info_header *pf2vf_info =
adev->virt.fw_reserve.p_pf2vf;
+ uint32_t checksum;
uint32_t checkval;
- char *str;
+
+ if (adev->virt.fw_reserve.p_pf2vf == NULL)
+ return -EINVAL;
+
+ if (pf2vf_info->size > 1024) {
+ DRM_ERROR("invalid pf2vf message size\n");
+ return -EINVAL;
+ }
+
+ switch (pf2vf_info->version) {
+ case 1:
+ checksum = ((struct amdgim_pf2vf_info_v1
*)pf2vf_info)->checksum;
+ checkval = amd_sriov_msg_checksum(
+ adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
+ adev->virt.fw_reserve.checksum_key, checksum);
+ if (checksum != checkval) {
+ DRM_ERROR("invalid pf2vf message\n");
+ return -EINVAL;
+ }
+
+ adev->virt.gim_feature =
+ ((struct amdgim_pf2vf_info_v1
*)pf2vf_info)->feature_flags;
+ break;
+ case 2:
+ /* TODO: missing key, need to add it later */
+ checksum = ((struct amd_sriov_msg_pf2vf_info
*)pf2vf_info)->checksum;
+ checkval = amd_sriov_msg_checksum(
+ adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
+ 0, checksum);
+ if (checksum != checkval) {
+ DRM_ERROR("invalid pf2vf message\n");
+ return -EINVAL;
+ }
+
+ adev->virt.vf2pf_update_interval_ms =
+ ((struct amd_sriov_msg_pf2vf_info
*)pf2vf_info)->vf2pf_update_interval_ms;
+ adev->virt.gim_feature =
+ ((struct amd_sriov_msg_pf2vf_info
*)pf2vf_info)->feature_flags.all;
+
+ break;
+
[PATCH 3/3] SWDEV-247673 - stop data_exchange work thread before reset
From: Tiecheng Zhou
In FLR routine, init_data_exchange is called at reset_sriov
while fini_data_exchange is not. This will duplicating work
thread.
So call fini_data_exchange before reset for SRIOV
Change-Id: I974c6a3c5de86736eebefc386c03fe0e18e1fae3
Signed-off-by: Tiecheng Zhou
Signed-off-by: Bokun Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 483ec0136332..e71cf3b34e15 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4080,6 +4080,11 @@ static int amdgpu_device_pre_asic_reset(struct
amdgpu_device *adev,
amdgpu_debugfs_wait_dump(adev);
+ if (amdgpu_sriov_vf(adev)) {
+ /* stop the data exchange thread */
+ amdgpu_virt_fini_data_exchange(adev);
+ }
+
/* block all schedulers and reset given job's ring */
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = adev->rings[i];
--
2.20.1
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[PATCH 1/3] SWDEV-220451 - Query guest's information by VF2PF message - Guest side - part 1
- Add guest side change to support VF2PF message
- Fix coding style
Change-Id: I82e5518cb10ec0b19fecaba7e05b02f4b7f2b409
Signed-off-by: Bokun Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h| 29 +-
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 276
2 files changed, 285 insertions(+), 20 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index b2046c3a404d..082fb0736645 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -24,6 +24,8 @@
#ifndef AMDGPU_VIRT_H
#define AMDGPU_VIRT_H
+#include "amdgv_sriovmsg.h"
+
#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
#define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this
GPU */
#define AMDGPU_SRIOV_CAPS_IS_VF(1 << 2) /* this GPU is a virtual
function */
@@ -79,7 +81,10 @@ struct amdgpu_virt_fw_reserve {
struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
unsigned int checksum_key;
};
+
/*
+ * Legacy GIM header
+ *
* Defination between PF and VF
* Structures forcibly aligned to 4 to keep the same style as PF.
*/
@@ -101,15 +106,7 @@ enum AMDGIM_FEATURE_FLAG {
AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
};
-struct amd_sriov_msg_pf2vf_info_header {
- /* the total structure size in byte. */
- uint32_t size;
- /* version of this structure, written by the GIM */
- uint32_t version;
- /* reserved */
- uint32_t reserved[2];
-} __aligned(4);
-struct amdgim_pf2vf_info_v1 {
+struct amdgim_pf2vf_info_v1 {
/* header contains size and version */
struct amd_sriov_msg_pf2vf_info_header header;
/* max_width * max_height */
@@ -128,6 +125,7 @@ struct amdgim_pf2vf_info_v1 {
unsigned int checksum;
} __aligned(4);
+/* TODO: below struct is duplicated to amd_sriov_msg_pf2vf_info */
struct amdgim_pf2vf_info_v2 {
/* header contains size and version */
struct amd_sriov_msg_pf2vf_info_header header;
@@ -166,16 +164,6 @@ struct amdgim_pf2vf_info_v2 {
uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (18 +
sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 0)];
} __aligned(4);
-
-struct amd_sriov_msg_vf2pf_info_header {
- /* the total structure size in byte. */
- uint32_t size;
- /*version of this structure, written by the guest */
- uint32_t version;
- /* reserved */
- uint32_t reserved[2];
-} __aligned(4);
-
struct amdgim_vf2pf_info_v1 {
/* header contains size and version */
struct amd_sriov_msg_vf2pf_info_header header;
@@ -237,8 +225,9 @@ struct amdgim_vf2pf_info_v2 {
uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 +
sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
} __aligned(4);
+/* TODO: below macro and typedef will cause compile error, need to remove */
#define AMDGPU_FW_VRAM_VF2PF_VER 2
-typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
+typedef struct amd_sriov_msg_vf2pf_info amdgim_vf2pf_info;
#define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
do { \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
new file mode 100644
index ..5355827ed0ae
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright 2018-2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef AMDGV_SRIOV_MSG__H_
+#define AMDGV_SRIOV_MSG__H_
+
+/* unit in kilobytes */
+#define AMD_SRIOV_MSG_VBIOS_OFFSET 0
+#define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64
+#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KBAMD_SRIOV_MSG_VBIOS_SIZE_KB
+#define
Re: [PATCH] drm/amdgpu: unmap register bar on device init failure
Reviewed-by: Andrey Grodzovsky
Andrey
On 9/16/20 10:33 AM, Alex Deucher wrote:
We never unmapped the regiser BAR on failure.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d633e5448476..61ba5eba678a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3209,13 +3209,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_device_get_job_timeout_settings(adev);
if (r) {
dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
- return r;
+ goto failed_unmap;
}
/* early init functions */
r = amdgpu_device_ip_early_init(adev);
if (r)
- return r;
+ goto failed_unmap;
/* doorbell bar mapping and doorbell index init*/
amdgpu_device_doorbell_init(adev);
@@ -3421,6 +3421,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
if (boco)
vga_switcheroo_fini_domain_pm_ops(adev->dev);
+failed_unmap:
+ iounmap(adev->rmmio);
+ adev->rmmio = NULL;
+
return r;
}
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Re: [PATCH v2] Revert "drm/radeon: handle PCIe root ports with addressing limitations"
On Wed, Sep 16, 2020 at 09:20:17AM -0400, Alex Deucher wrote: > This causes screen corruption when using the GPU which makes the > system unusable. You have not addressed any of my questions, especially if the commit that fixed one of the reports (the only one with a recent kernel) fixed most of the others as well. Nor that fact that the crash one really looks like the symptom of an underlying issue that absolutely needs to be fixed first. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: unmap register bar on device init failure
We never unmapped the regiser BAR on failure.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d633e5448476..61ba5eba678a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3209,13 +3209,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
r = amdgpu_device_get_job_timeout_settings(adev);
if (r) {
dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
- return r;
+ goto failed_unmap;
}
/* early init functions */
r = amdgpu_device_ip_early_init(adev);
if (r)
- return r;
+ goto failed_unmap;
/* doorbell bar mapping and doorbell index init*/
amdgpu_device_doorbell_init(adev);
@@ -3421,6 +3421,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
if (boco)
vga_switcheroo_fini_domain_pm_ops(adev->dev);
+failed_unmap:
+ iounmap(adev->rmmio);
+ adev->rmmio = NULL;
+
return r;
}
--
2.25.4
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Re: [PATCH -next 0/8] drm/amd/amdgpu: fix comparison pointer to bool warning
Am 16.09.20 um 15:36 schrieb Alex Deucher: On Wed, Sep 16, 2020 at 3:51 AM Daniel Vetter wrote: On Wed, Sep 16, 2020 at 09:38:34AM +0200, Christian König wrote: Am 15.09.20 um 21:35 schrieb Ville Syrjälä: On Tue, Sep 15, 2020 at 03:16:32PM -0400, Alex Deucher wrote: I question the value of these warnings. Why even have a boolean type if you are going to get warnings when you use them... That said, applied to avoid getting these patches again and again every time someone sees this. if (this_is_sparta) if (this_is_sparta == true) if (this_is_sparta != false) I think the first one reads the best, and avoids having to decide between truth and falsehood :) +1 +1, especially because we also have the inversion when using negative errno codes for failures and 0 as success, which results in if (errno == 0) /* success case */ but if (bool == 0) /* failure case */ now creative people do sometimes if (!errno) /* success case */ which I think is horribly confusing. So imo for more easier telling apart of these too I think consistently using the short form for booleans, and consistently using the more explicit long form for errno checks is a Very Good Pattern :-) I don't disagree with your logic, but we regularly get patches to convert errno checks to drop the direct comparison because that is the "preferred kernel style". Arguably, we should be explicit in all cases as that avoids all confusion. With that in mind, my original point stands. Why have a type when comparisons against valid settings for that type produce errors? Well it isn't an error, but raising a nice warning is most likely a good idea. Christian. Alex Cheers, Daniel Christian. Alex On Wed, Sep 9, 2020 at 9:21 AM Christian König wrote: Acked-by: Christian König for the series. Am 09.09.20 um 15:07 schrieb Zheng Bin: Zheng Bin (8): drm/amd/amdgpu: fix comparison pointer to bool warning in gfx_v9_0.c drm/amd/amdgpu: fix comparison pointer to bool warning in gfx_v10_0.c drm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v5_0.c drm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v5_2.c drm/amd/amdgpu: fix comparison pointer to bool warning in si.c drm/amd/amdgpu: fix comparison pointer to bool warning in uvd_v6_0.c drm/amd/amdgpu: fix comparison pointer to bool warning in amdgpu_atpx_handler.c drm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v4_0.c drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +- drivers/gpu/drm/amd/amdgpu/si.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 4 ++-- 8 files changed, 11 insertions(+), 11 deletions(-) -- 2.26.0.106.g9fadedd ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cchristian.koenig%40amd.com%7Cdc7a8d7517d341e3a80c08d85a458ba8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637358602051676053sdata=MS0vcBcU7unXjEFlbd8kLbJkJ4sKcvIdLjc8yhX4UUI%3Dreserved=0 ___ dri-devel mailing list dri-de...@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-develdata=02%7C01%7Cchristian.koenig%40amd.com%7Cdc7a8d7517d341e3a80c08d85a458ba8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637358602051686051sdata=MgfR%2BwCVY9gWfhQ9i5kWcKiiYkV1C8O2dEKlZYSqscE%3Dreserved=0 ___ dri-devel mailing list dri-de...@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-develdata=02%7C01%7Cchristian.koenig%40amd.com%7Cdc7a8d7517d341e3a80c08d85a458ba8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637358602051686051sdata=MgfR%2BwCVY9gWfhQ9i5kWcKiiYkV1C8O2dEKlZYSqscE%3Dreserved=0 -- Daniel Vetter Software Engineer, Intel Corporation https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fblog.ffwll.ch%2Fdata=02%7C01%7Cchristian.koenig%40amd.com%7Cdc7a8d7517d341e3a80c08d85a458ba8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637358602051686051sdata=GvLs5OXw2Ny%2BieJxm8hjawNb0rGA966539iAwlWwPMY%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH -next 0/8] drm/amd/amdgpu: fix comparison pointer to bool warning
On Wed, Sep 16, 2020 at 3:51 AM Daniel Vetter wrote: > > On Wed, Sep 16, 2020 at 09:38:34AM +0200, Christian König wrote: > > Am 15.09.20 um 21:35 schrieb Ville Syrjälä: > > > On Tue, Sep 15, 2020 at 03:16:32PM -0400, Alex Deucher wrote: > > > > I question the value of these warnings. Why even have a boolean type > > > > if you are going to get warnings when you use them... > > > > That said, applied to avoid getting these patches again and again > > > > every time someone sees this. > > > if (this_is_sparta) > > > if (this_is_sparta == true) > > > if (this_is_sparta != false) > > > > > > I think the first one reads the best, and avoids having to > > > decide between truth and falsehood :) > > > > +1 > > +1, especially because we also have the inversion when using negative > errno codes for failures and 0 as success, which results in > > if (errno == 0) /* success case */ > > but > if (bool == 0) /* failure case */ > > now creative people do sometimes > > if (!errno) /* success case */ > > which I think is horribly confusing. So imo for more easier telling apart > of these too I think consistently using the short form for booleans, and > consistently using the more explicit long form for errno checks is a Very > Good Pattern :-) I don't disagree with your logic, but we regularly get patches to convert errno checks to drop the direct comparison because that is the "preferred kernel style". Arguably, we should be explicit in all cases as that avoids all confusion. With that in mind, my original point stands. Why have a type when comparisons against valid settings for that type produce errors? Alex > > Cheers, Daniel > > > > > Christian. > > > > > > > > > Alex > > > > > > > > On Wed, Sep 9, 2020 at 9:21 AM Christian König > > > > wrote: > > > > > Acked-by: Christian König for the series. > > > > > > > > > > Am 09.09.20 um 15:07 schrieb Zheng Bin: > > > > > > Zheng Bin (8): > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > gfx_v9_0.c > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > gfx_v10_0.c > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > sdma_v5_0.c > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > sdma_v5_2.c > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in si.c > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > uvd_v6_0.c > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > amdgpu_atpx_handler.c > > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > > sdma_v4_0.c > > > > > > > > > > > >drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 4 ++-- > > > > > >drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- > > > > > >drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 2 +- > > > > > >drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- > > > > > >drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- > > > > > >drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +- > > > > > >drivers/gpu/drm/amd/amdgpu/si.c | 2 +- > > > > > >drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 4 ++-- > > > > > >8 files changed, 11 insertions(+), 11 deletions(-) > > > > > > > > > > > > -- > > > > > > 2.26.0.106.g9fadedd > > > > > > > > > > > ___ > > > > > amd-gfx mailing list > > > > > amd-gfx@lists.freedesktop.org > > > > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > > > ___ > > > > dri-devel mailing list > > > > dri-de...@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > > > ___ > > dri-devel mailing list > > dri-de...@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] Revert "drm/radeon: handle PCIe root ports with addressing limitations"
This causes screen corruption when using the GPU which makes the
system unusable.
It was noticed by several people closer to when the change went in as
well. We looked into it a bit at the time but couldn't determine the
problem. It only seems to affect really old chips (like 15-20 years
old) which makes it hard to reproduce if you don't have an old system.
There were a couple of threads at the time, but nothing was resolved.
I was able to find one of them:
https://lkml.org/lkml/2019/12/14/263
This reverts commit 33b3ad3788ab ("drm/radeon: handle PCIe root ports with
addressing limitations").
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206973
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206697
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=207763
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1140
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1287
Fixes: 33b3ad3788ab ("drm/radeon: handle PCIe root ports with addressing
limitations")
Signed-off-by: Alex Deucher
Cc: sta...@vger.kernel.org
Cc: Christoph Hellwig
Cc: christian.koe...@amd.com
---
v2: provide a better commit message. The issue seems to be related to himem.
Any ideas?
drivers/gpu/drm/radeon/radeon.h| 1 +
drivers/gpu/drm/radeon/radeon_device.c | 13 -
drivers/gpu/drm/radeon/radeon_ttm.c| 2 +-
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index cc4f58d16589..019f756b3f80 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2391,6 +2391,7 @@ struct radeon_device {
struct radeon_wbwb;
struct radeon_dummy_pagedummy_page;
boolshutdown;
+ boolneed_dma32;
boolneed_swiotlb;
boolaccel_working;
boolfastfb_working; /* IGP feature*/
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index 266e3cbbd09b..f74c74ad8b5d 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1363,25 +1363,28 @@ int radeon_device_init(struct radeon_device *rdev,
else
rdev->mc.mc_mask = 0xULL; /* 32 bit MC */
- /* set DMA mask.
+ /* set DMA mask + need_dma32 flags.
* PCIE - can handle 40-bits.
* IGP - can handle 40-bits
* AGP - generally dma32 is safest
* PCI - dma32 for legacy pci gart, 40 bits on newer asics
*/
- dma_bits = 40;
+ rdev->need_dma32 = false;
if (rdev->flags & RADEON_IS_AGP)
- dma_bits = 32;
+ rdev->need_dma32 = true;
if ((rdev->flags & RADEON_IS_PCI) &&
(rdev->family <= CHIP_RS740))
- dma_bits = 32;
+ rdev->need_dma32 = true;
#ifdef CONFIG_PPC64
if (rdev->family == CHIP_CEDAR)
- dma_bits = 32;
+ rdev->need_dma32 = true;
#endif
+ dma_bits = rdev->need_dma32 ? 32 : 40;
r = dma_set_mask_and_coherent(>pdev->dev, DMA_BIT_MASK(dma_bits));
if (r) {
+ rdev->need_dma32 = true;
+ dma_bits = 32;
pr_warn("radeon: No suitable DMA available\n");
return r;
}
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
index 74ad50c7491c..7e5c2fb8eab0 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -738,7 +738,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
_bo_driver,
rdev->ddev->anon_inode->i_mapping,
rdev->ddev->vma_offset_manager,
- dma_addressing_limited(>pdev->dev));
+ rdev->need_dma32);
if (r) {
DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
return r;
--
2.25.4
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Re: [PATCH] Revert "drm/radeon: handle PCIe root ports with addressing limitations"
On Wed, Sep 16, 2020 at 2:32 AM Greg KH wrote:
>
> On Tue, Sep 15, 2020 at 02:46:07PM -0400, Alex Deucher wrote:
> > This change breaks tons of systems.
>
> Very vague :(
Screen corruption making the system unusable.
>
> This commit has also been merged for over a year, why the sudden
> problem now?
>
It was noticed by several people closer to when the change went in as
well. If you notice, most of the bugs date back quite a while. We
looked into it a bit at the time but couldn't determine the problem.
It only seems to affect really old chips (like 15-20 years old) which
makes it hard to reproduce if you don't have an old system. There
were a couple of threads at the time, but nothing was resolved. I was
able to find one of them:
https://lkml.org/lkml/2019/12/14/263
There were several new bugs filed which brought the issue back to my
attention recently.
> > This reverts commit 33b3ad3788aba846fc8b9a065fe2685a0b64f713.
>
> You mean "33b3ad3788ab ("drm/radeon: handle PCIe root ports with
> addressing limitations")"?
>
> That's the proper way to reference commits in changelogs please. It's
> even documented that way...
When you revert a patch with git, that is what it does. Maybe we
should fix git to change the formatting.
>
> >
> > Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206973
> > Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206697
> > Bug: https://bugzilla.kernel.org/show_bug.cgi?id=207763
> > Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1140
> > Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1287
> > Signed-off-by: Alex Deucher
> > Cc: sta...@vger.kernel.org
> > Cc: Christoph Hellwig
> > Cc: christian.koe...@amd.com
>
> Fixes: 33b3ad3788ab ("drm/radeon: handle PCIe root ports with addressing
> limitations")
>
Sure, I can add that, but it doesn't really fix it, it reverts it.
But point taken, it does fix the commit by removing it.
Alex
> as well?
>
> thanks,
>
> greg k-h
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Re: [PATCH v2 21/21] drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver
On Tue, Sep 15, 2020 at 04:59:58PM +0200, Thomas Zimmermann wrote:
> Several GEM and PRIME callbacks have been deprecated in favor of
> per-instance GEM object functions. Remove the callbacks as they are
> now unused. The only exception is .gem_prime_mmap, which is still
> in use by several drivers.
>
> What is also gone is gem_vm_ops in struct drm_driver. All drivers now
> use struct drm_gem_object_funcs.vm_ops instead.
>
> While at it, the patch also improves error handling around calls
> to .free and .get_sg_table callbacks.
>
> v2:
> * update related TODO item (Sam)
>
> Signed-off-by: Thomas Zimmermann
Nice work!
Acked-by: Daniel Vetter
> ---
> Documentation/gpu/todo.rst | 7 +--
> drivers/gpu/drm/drm_gem.c| 35 +++-
> drivers/gpu/drm/drm_gem_cma_helper.c | 6 +-
> drivers/gpu/drm/drm_prime.c | 17 +++---
> include/drm/drm_drv.h| 85 ++--
> 5 files changed, 25 insertions(+), 125 deletions(-)
>
> diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
> index b0ea17da8ff6..0fc6bc222392 100644
> --- a/Documentation/gpu/todo.rst
> +++ b/Documentation/gpu/todo.rst
> @@ -289,11 +289,8 @@ struct drm_gem_object_funcs
> ---
>
> GEM objects can now have a function table instead of having the callbacks on
> the
> -DRM driver struct. This is now the preferred way and drivers can be moved
> over.
> -
> -We also need a 2nd version of the CMA define that doesn't require the
> -vmapping to be present (different hook for prime importing). Plus this needs
> to
> -be rolled out to all drivers using their own implementations, too.
> +DRM driver struct. This is now the preferred way. Callbacks in drivers have
> been
> +converted, except for struct drm_driver.gem_prime_mmap.
>
> Level: Intermediate
>
> diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
> index 19d73868490e..96945bed8291 100644
> --- a/drivers/gpu/drm/drm_gem.c
> +++ b/drivers/gpu/drm/drm_gem.c
> @@ -247,12 +247,9 @@ drm_gem_object_release_handle(int id, void *ptr, void
> *data)
> {
> struct drm_file *file_priv = data;
> struct drm_gem_object *obj = ptr;
> - struct drm_device *dev = obj->dev;
>
> if (obj->funcs && obj->funcs->close)
> obj->funcs->close(obj, file_priv);
> - else if (dev->driver->gem_close_object)
> - dev->driver->gem_close_object(obj, file_priv);
>
> drm_gem_remove_prime_handles(obj, file_priv);
> drm_vma_node_revoke(>vma_node, file_priv);
> @@ -407,10 +404,6 @@ drm_gem_handle_create_tail(struct drm_file *file_priv,
> ret = obj->funcs->open(obj, file_priv);
> if (ret)
> goto err_revoke;
> - } else if (dev->driver->gem_open_object) {
> - ret = dev->driver->gem_open_object(obj, file_priv);
> - if (ret)
> - goto err_revoke;
> }
>
> *handlep = handle;
> @@ -982,12 +975,11 @@ drm_gem_object_free(struct kref *kref)
> {
> struct drm_gem_object *obj =
> container_of(kref, struct drm_gem_object, refcount);
> - struct drm_device *dev = obj->dev;
>
> - if (obj->funcs)
> - obj->funcs->free(obj);
> - else if (dev->driver->gem_free_object_unlocked)
> - dev->driver->gem_free_object_unlocked(obj);
> + if (drm_WARN_ON_ONCE(obj->dev, !obj->funcs || !obj->funcs->free))
> + return;
> +
> + obj->funcs->free(obj);
> }
> EXPORT_SYMBOL(drm_gem_object_free);
>
> @@ -1049,9 +1041,9 @@ EXPORT_SYMBOL(drm_gem_vm_close);
> * @obj_size: the object size to be mapped, in bytes
> * @vma: VMA for the area to be mapped
> *
> - * Set up the VMA to prepare mapping of the GEM object using the gem_vm_ops
> - * provided by the driver. Depending on their requirements, drivers can
> either
> - * provide a fault handler in their gem_vm_ops (in which case any accesses to
> + * Set up the VMA to prepare mapping of the GEM object using the GEM object's
> + * vm_ops. Depending on their requirements, GEM objects can either
> + * provide a fault handler in their vm_ops (in which case any accesses to
> * the object will be trapped, to perform migration, GTT binding, surface
> * register allocation, or performance monitoring), or mmap the buffer memory
> * synchronously after calling drm_gem_mmap_obj.
> @@ -1065,12 +1057,11 @@ EXPORT_SYMBOL(drm_gem_vm_close);
> * callers must verify access restrictions before calling this helper.
> *
> * Return 0 or success or -EINVAL if the object size is smaller than the VMA
> - * size, or if no gem_vm_ops are provided.
> + * size, or if no vm_ops are provided.
> */
> int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
>struct vm_area_struct *vma)
> {
> - struct drm_device *dev = obj->dev;
> int ret;
>
> /* Check for valid size. */
> @@ -1095,8 +1086,6 @@
Re: [PATCH v2 17/21] drm/virtgpu: Set PRIME export function in struct drm_gem_object_funcs
On Tue, Sep 15, 2020 at 04:59:54PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces virtgpu's per-driver PRIME export
> function with a per-object function.
>
> Signed-off-by: Thomas Zimmermann
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/virtio/virtgpu_drv.c| 1 -
> drivers/gpu/drm/virtio/virtgpu_object.c | 1 +
> 2 files changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.c
> b/drivers/gpu/drm/virtio/virtgpu_drv.c
> index b039f493bda9..1f8d6ed11d21 100644
> --- a/drivers/gpu/drm/virtio/virtgpu_drv.c
> +++ b/drivers/gpu/drm/virtio/virtgpu_drv.c
> @@ -203,7 +203,6 @@ static struct drm_driver driver = {
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> .gem_prime_mmap = drm_gem_prime_mmap,
> - .gem_prime_export = virtgpu_gem_prime_export,
> .gem_prime_import = virtgpu_gem_prime_import,
> .gem_prime_import_sg_table = virtgpu_gem_prime_import_sg_table,
>
> diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c
> b/drivers/gpu/drm/virtio/virtgpu_object.c
> index 842f8b61aa89..4f7d7ea8194c 100644
> --- a/drivers/gpu/drm/virtio/virtgpu_object.c
> +++ b/drivers/gpu/drm/virtio/virtgpu_object.c
> @@ -108,6 +108,7 @@ static const struct drm_gem_object_funcs
> virtio_gpu_shmem_funcs = {
> .close = virtio_gpu_gem_object_close,
>
> .print_info = drm_gem_shmem_print_info,
> + .export = virtgpu_gem_prime_export,
> .pin = drm_gem_shmem_pin,
> .unpin = drm_gem_shmem_unpin,
> .get_sg_table = drm_gem_shmem_get_sg_table,
> --
> 2.28.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH v2 13/21] drm/rockchip: Convert to drm_gem_object_funcs
On Tue, Sep 15, 2020 at 04:59:50PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in rockchip. The only exception is gem_prime_mmap,
> which is non-trivial to convert.
>
> Signed-off-by: Thomas Zimmermann
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 5 -
> drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 10 ++
> 2 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> index 0f3eb392fe39..b7654f5e4225 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> @@ -212,15 +212,10 @@ static const struct file_operations
> rockchip_drm_driver_fops = {
> static struct drm_driver rockchip_drm_driver = {
> .driver_features= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> .lastclose = drm_fb_helper_lastclose,
> - .gem_vm_ops = _gem_cma_vm_ops,
> - .gem_free_object_unlocked = rockchip_gem_free_object,
> .dumb_create= rockchip_gem_dumb_create,
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> - .gem_prime_get_sg_table = rockchip_gem_prime_get_sg_table,
> .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table,
> - .gem_prime_vmap = rockchip_gem_prime_vmap,
> - .gem_prime_vunmap = rockchip_gem_prime_vunmap,
> .gem_prime_mmap = rockchip_gem_mmap_buf,
> .fops = _drm_driver_fops,
> .name = DRIVER_NAME,
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
> index 0055d86576f7..bddc7d99efe3 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
> @@ -296,6 +296,14 @@ static void rockchip_gem_release_object(struct
> rockchip_gem_object *rk_obj)
> kfree(rk_obj);
> }
>
> +static const struct drm_gem_object_funcs rockchip_gem_object_funcs = {
> + .free = rockchip_gem_free_object,
> + .get_sg_table = rockchip_gem_prime_get_sg_table,
> + .vmap = rockchip_gem_prime_vmap,
> + .vunmap = rockchip_gem_prime_vunmap,
> + .vm_ops = _gem_cma_vm_ops,
> +};
> +
> static struct rockchip_gem_object *
> rockchip_gem_alloc_object(struct drm_device *drm, unsigned int size)
> {
> @@ -310,6 +318,8 @@ static struct rockchip_gem_object *
>
> obj = _obj->base;
>
> + obj->funcs = _gem_object_funcs;
> +
> drm_gem_object_init(drm, obj, size);
>
> return rk_obj;
> --
> 2.28.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH v2 09/21] drm/nouveau: Introduce GEM object functions
On Tue, Sep 15, 2020 at 04:59:46PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in nouveau.
>
> Signed-off-by: Thomas Zimmermann
Hm ttm and gem mmap world still quite disjoint ... Anyway that's an
entirely different thing.
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/nouveau/nouveau_drm.c | 9 -
> drivers/gpu/drm/nouveau/nouveau_gem.c | 13 +
> drivers/gpu/drm/nouveau/nouveau_gem.h | 2 ++
> drivers/gpu/drm/nouveau/nouveau_prime.c | 2 ++
> 4 files changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
> b/drivers/gpu/drm/nouveau/nouveau_drm.c
> index 42fc5c813a9b..72640bca1617 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_drm.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
> @@ -1207,16 +1207,7 @@ driver_stub = {
>
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> - .gem_prime_pin = nouveau_gem_prime_pin,
> - .gem_prime_unpin = nouveau_gem_prime_unpin,
> - .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
> .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
> - .gem_prime_vmap = nouveau_gem_prime_vmap,
> - .gem_prime_vunmap = nouveau_gem_prime_vunmap,
> -
> - .gem_free_object_unlocked = nouveau_gem_object_del,
> - .gem_open_object = nouveau_gem_object_open,
> - .gem_close_object = nouveau_gem_object_close,
>
> .dumb_create = nouveau_display_dumb_create,
> .dumb_map_offset = nouveau_display_dumb_map_offset,
> diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c
> b/drivers/gpu/drm/nouveau/nouveau_gem.c
> index 89adadf4706b..28e0cbb00876 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_gem.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
> @@ -169,6 +169,17 @@ nouveau_gem_object_close(struct drm_gem_object *gem,
> struct drm_file *file_priv)
> ttm_bo_unreserve(>bo);
> }
>
> +const struct drm_gem_object_funcs nouveau_gem_object_funcs = {
> + .free = nouveau_gem_object_del,
> + .open = nouveau_gem_object_open,
> + .close = nouveau_gem_object_close,
> + .pin = nouveau_gem_prime_pin,
> + .unpin = nouveau_gem_prime_unpin,
> + .get_sg_table = nouveau_gem_prime_get_sg_table,
> + .vmap = nouveau_gem_prime_vmap,
> + .vunmap = nouveau_gem_prime_vunmap,
> +};
> +
> int
> nouveau_gem_new(struct nouveau_cli *cli, u64 size, int align, uint32_t
> domain,
> uint32_t tile_mode, uint32_t tile_flags,
> @@ -186,6 +197,8 @@ nouveau_gem_new(struct nouveau_cli *cli, u64 size, int
> align, uint32_t domain,
> if (IS_ERR(nvbo))
> return PTR_ERR(nvbo);
>
> + nvbo->bo.base.funcs = _gem_object_funcs;
> +
> /* Initialize the embedded gem-object. We return a single gem-reference
>* to the caller, instead of a normal nouveau_bo ttm reference. */
> ret = drm_gem_object_init(drm->dev, >bo.base, size);
> diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.h
> b/drivers/gpu/drm/nouveau/nouveau_gem.h
> index 978e07591990..b35c180322e2 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_gem.h
> +++ b/drivers/gpu/drm/nouveau/nouveau_gem.h
> @@ -5,6 +5,8 @@
> #include "nouveau_drv.h"
> #include "nouveau_bo.h"
>
> +extern const struct drm_gem_object_funcs nouveau_gem_object_funcs;
> +
> static inline struct nouveau_bo *
> nouveau_gem_object(struct drm_gem_object *gem)
> {
> diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c
> b/drivers/gpu/drm/nouveau/nouveau_prime.c
> index b2ecb91f8ddc..a8264aebf3d4 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_prime.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
> @@ -77,6 +77,8 @@ struct drm_gem_object
> *nouveau_gem_prime_import_sg_table(struct drm_device *dev,
>
> nvbo->valid_domains = NOUVEAU_GEM_DOMAIN_GART;
>
> + nvbo->bo.base.funcs = _gem_object_funcs;
> +
> /* Initialize the embedded gem-object. We return a single gem-reference
>* to the caller, instead of a normal nouveau_bo ttm reference. */
> ret = drm_gem_object_init(dev, >bo.base, size);
> --
> 2.28.0
>
--
Daniel Vetter
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Re: [PATCH v2 08/21] drm/msm: Introduce GEM object funcs
On Tue, Sep 15, 2020 at 04:59:45PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in msm. The only exception is gem_prime_mmap,
> which is non-trivial to convert.
>
> Signed-off-by: Thomas Zimmermann
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/msm/msm_drv.c | 13 -
> drivers/gpu/drm/msm/msm_drv.h | 1 -
> drivers/gpu/drm/msm/msm_gem.c | 19 ++-
> 3 files changed, 18 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index 79333842f70a..5952767ea478 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -978,12 +978,6 @@ static const struct drm_ioctl_desc msm_ioctls[] = {
> DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query,
> DRM_RENDER_ALLOW),
> };
>
> -static const struct vm_operations_struct vm_ops = {
> - .fault = msm_gem_fault,
> - .open = drm_gem_vm_open,
> - .close = drm_gem_vm_close,
> -};
> -
> static const struct file_operations fops = {
> .owner = THIS_MODULE,
> .open = drm_open,
> @@ -1009,18 +1003,11 @@ static struct drm_driver msm_driver = {
> .irq_preinstall = msm_irq_preinstall,
> .irq_postinstall= msm_irq_postinstall,
> .irq_uninstall = msm_irq_uninstall,
> - .gem_free_object_unlocked = msm_gem_free_object,
> - .gem_vm_ops = _ops,
> .dumb_create= msm_gem_dumb_create,
> .dumb_map_offset= msm_gem_dumb_map_offset,
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> - .gem_prime_pin = msm_gem_prime_pin,
> - .gem_prime_unpin= msm_gem_prime_unpin,
> - .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
> .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
> - .gem_prime_vmap = msm_gem_prime_vmap,
> - .gem_prime_vunmap = msm_gem_prime_vunmap,
> .gem_prime_mmap = msm_gem_prime_mmap,
> #ifdef CONFIG_DEBUG_FS
> .debugfs_init = msm_debugfs_init,
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index af259b0573ea..7bcea10be81f 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -269,7 +269,6 @@ void msm_gem_shrinker_cleanup(struct drm_device *dev);
> int msm_gem_mmap_obj(struct drm_gem_object *obj,
> struct vm_area_struct *vma);
> int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
> -vm_fault_t msm_gem_fault(struct vm_fault *vmf);
> uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
> int msm_gem_get_iova(struct drm_gem_object *obj,
> struct msm_gem_address_space *aspace, uint64_t *iova);
> diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
> index b4553caaa196..de915ff6f4b4 100644
> --- a/drivers/gpu/drm/msm/msm_gem.c
> +++ b/drivers/gpu/drm/msm/msm_gem.c
> @@ -247,7 +247,7 @@ int msm_gem_mmap(struct file *filp, struct vm_area_struct
> *vma)
> return msm_gem_mmap_obj(vma->vm_private_data, vma);
> }
>
> -vm_fault_t msm_gem_fault(struct vm_fault *vmf)
> +static vm_fault_t msm_gem_fault(struct vm_fault *vmf)
> {
> struct vm_area_struct *vma = vmf->vma;
> struct drm_gem_object *obj = vma->vm_private_data;
> @@ -994,6 +994,22 @@ int msm_gem_new_handle(struct drm_device *dev, struct
> drm_file *file,
> return ret;
> }
>
> +static const struct vm_operations_struct vm_ops = {
> + .fault = msm_gem_fault,
> + .open = drm_gem_vm_open,
> + .close = drm_gem_vm_close,
> +};
> +
> +static const struct drm_gem_object_funcs msm_gem_object_funcs = {
> + .free = msm_gem_free_object,
> + .pin = msm_gem_prime_pin,
> + .unpin = msm_gem_prime_unpin,
> + .get_sg_table = msm_gem_prime_get_sg_table,
> + .vmap = msm_gem_prime_vmap,
> + .vunmap = msm_gem_prime_vunmap,
> + .vm_ops = _ops,
> +};
> +
> static int msm_gem_new_impl(struct drm_device *dev,
> uint32_t size, uint32_t flags,
> struct drm_gem_object **obj)
> @@ -1024,6 +1040,7 @@ static int msm_gem_new_impl(struct drm_device *dev,
> INIT_LIST_HEAD(_obj->vmas);
>
> *obj = _obj->base;
> + (*obj)->funcs = _gem_object_funcs;
>
> return 0;
> }
> --
> 2.28.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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RE: [PATCH] drm/amdgpu: declare ta firmware for navy_flounder
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Tianci Yin
-Original Message-
From: Jiansong Chen
Sent: Wednesday, September 16, 2020 7:34 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Yin, Tianci (Rico) ;
Chen, Jiansong (Simon)
Subject: [PATCH] drm/amdgpu: declare ta firmware for navy_flounder
The information provided via MODULE_FIRMWARE appears in the module information.
External tools(eg. dracut) may use the list of fw files to include them as
appropriate in an initramfs, thus missing declaration will lead to request
firmware failure in boot time.
Signed-off-by: Jiansong Chen
Change-Id: I0eb0231d0e4672ee00ebdbe0bd8e75245a8c1698
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index e16874f30d5d..6c5d9612abcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -58,7 +58,7 @@ MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
-MODULE_FIRMWARE("amdgpu/navy_flounder_asd.bin");
+MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
/* address block */
#define smnMP1_FIRMWARE_FLAGS0x3010024
--
2.25.1
___
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Re: [PATCH v2 07/21] drm/mediatek: Introduce GEM object functions
On Tue, Sep 15, 2020 at 04:59:44PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in mediatek. The only exception is gem_prime_mmap,
> which is non-trivial to convert.
>
> Signed-off-by: Thomas Zimmermann
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 -
> drivers/gpu/drm/mediatek/mtk_drm_gem.c | 11 +++
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 040a8f393fe2..2f8d0043fca7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -301,18 +301,13 @@ struct drm_gem_object *mtk_drm_gem_prime_import(struct
> drm_device *dev,
> static struct drm_driver mtk_drm_driver = {
> .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
>
> - .gem_free_object_unlocked = mtk_drm_gem_free_object,
> - .gem_vm_ops = _gem_cma_vm_ops,
> .dumb_create = mtk_drm_gem_dumb_create,
>
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> .gem_prime_import = mtk_drm_gem_prime_import,
> - .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table,
> .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
> .gem_prime_mmap = mtk_drm_gem_mmap_buf,
> - .gem_prime_vmap = mtk_drm_gem_prime_vmap,
> - .gem_prime_vunmap = mtk_drm_gem_prime_vunmap,
> .fops = _drm_fops,
>
> .name = DRIVER_NAME,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c
> b/drivers/gpu/drm/mediatek/mtk_drm_gem.c
> index 6190cc3b7b0d..591b90410e4a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c
> @@ -8,11 +8,20 @@
> #include
> #include
> #include
> +#include
> #include
>
> #include "mtk_drm_drv.h"
> #include "mtk_drm_gem.h"
>
> +static const struct drm_gem_object_funcs mtk_drm_gem_object_funcs = {
> + .free = mtk_drm_gem_free_object,
> + .get_sg_table = mtk_gem_prime_get_sg_table,
> + .vmap = mtk_drm_gem_prime_vmap,
> + .vunmap = mtk_drm_gem_prime_vunmap,
> + .vm_ops = _gem_cma_vm_ops,
> +};
> +
> static struct mtk_drm_gem_obj *mtk_drm_gem_init(struct drm_device *dev,
> unsigned long size)
> {
> @@ -25,6 +34,8 @@ static struct mtk_drm_gem_obj *mtk_drm_gem_init(struct
> drm_device *dev,
> if (!mtk_gem_obj)
> return ERR_PTR(-ENOMEM);
>
> + mtk_gem_obj->base.funcs = _drm_gem_object_funcs;
> +
> ret = drm_gem_object_init(dev, _gem_obj->base, size);
> if (ret < 0) {
> DRM_ERROR("failed to initialize gem object\n");
> --
> 2.28.0
Reviewed-by: Daniel Vetter
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH] drm/amdgpu: declare ta firmware for navy_flounder
The information provided via MODULE_FIRMWARE appears in
the module information. External tools(eg. dracut) may use the
list of fw files to include them as appropriate in an initramfs,
thus missing declaration will lead to request firmware failure
in boot time.
Signed-off-by: Jiansong Chen
Change-Id: I0eb0231d0e4672ee00ebdbe0bd8e75245a8c1698
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index e16874f30d5d..6c5d9612abcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -58,7 +58,7 @@ MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
-MODULE_FIRMWARE("amdgpu/navy_flounder_asd.bin");
+MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
/* address block */
#define smnMP1_FIRMWARE_FLAGS 0x3010024
--
2.25.1
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Re: [PATCH v2 05/21] drm/gma500: Introduce GEM object functions
On Tue, Sep 15, 2020 at 04:59:42PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in gma500.
>
> Signed-off-by: Thomas Zimmermann
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/gma500/framebuffer.c | 2 ++
> drivers/gpu/drm/gma500/gem.c | 18 --
> drivers/gpu/drm/gma500/gem.h | 3 +++
> drivers/gpu/drm/gma500/psb_drv.c | 9 -
> drivers/gpu/drm/gma500/psb_drv.h | 2 --
> 5 files changed, 21 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/framebuffer.c
> b/drivers/gpu/drm/gma500/framebuffer.c
> index 54d9876b5305..5ede24fb44ae 100644
> --- a/drivers/gpu/drm/gma500/framebuffer.c
> +++ b/drivers/gpu/drm/gma500/framebuffer.c
> @@ -24,6 +24,7 @@
> #include
>
> #include "framebuffer.h"
> +#include "gem.h"
> #include "gtt.h"
> #include "psb_drv.h"
> #include "psb_intel_drv.h"
> @@ -285,6 +286,7 @@ static struct gtt_range *psbfb_alloc(struct drm_device
> *dev, int aligned_size)
> /* Begin by trying to use stolen memory backing */
> backing = psb_gtt_alloc_range(dev, aligned_size, "fb", 1, PAGE_SIZE);
> if (backing) {
> + backing->gem.funcs = _gem_object_funcs;
> drm_gem_private_object_init(dev, >gem, aligned_size);
> return backing;
> }
> diff --git a/drivers/gpu/drm/gma500/gem.c b/drivers/gpu/drm/gma500/gem.c
> index f9c4b1d76f56..8f07de83b6fb 100644
> --- a/drivers/gpu/drm/gma500/gem.c
> +++ b/drivers/gpu/drm/gma500/gem.c
> @@ -18,7 +18,9 @@
>
> #include "psb_drv.h"
>
> -void psb_gem_free_object(struct drm_gem_object *obj)
> +static vm_fault_t psb_gem_fault(struct vm_fault *vmf);
> +
> +static void psb_gem_free_object(struct drm_gem_object *obj)
> {
> struct gtt_range *gtt = container_of(obj, struct gtt_range, gem);
>
> @@ -36,6 +38,17 @@ int psb_gem_get_aperture(struct drm_device *dev, void
> *data,
> return -EINVAL;
> }
>
> +static const struct vm_operations_struct psb_gem_vm_ops = {
> + .fault = psb_gem_fault,
> + .open = drm_gem_vm_open,
> + .close = drm_gem_vm_close,
> +};
> +
> +const struct drm_gem_object_funcs psb_gem_object_funcs = {
> + .free = psb_gem_free_object,
> + .vm_ops = _gem_vm_ops,
> +};
> +
> /**
> * psb_gem_create - create a mappable object
> * @file: the DRM file of the client
> @@ -63,6 +76,7 @@ int psb_gem_create(struct drm_file *file, struct drm_device
> *dev, u64 size,
> dev_err(dev->dev, "no memory for %lld byte GEM object\n", size);
> return -ENOSPC;
> }
> + r->gem.funcs = _gem_object_funcs;
> /* Initialize the extra goodies GEM needs to do all the hard work */
> if (drm_gem_object_init(dev, >gem, size) != 0) {
> psb_gtt_free_range(dev, r);
> @@ -123,7 +137,7 @@ int psb_gem_dumb_create(struct drm_file *file, struct
> drm_device *dev,
> * vma->vm_private_data points to the GEM object that is backing this
> * mapping.
> */
> -vm_fault_t psb_gem_fault(struct vm_fault *vmf)
> +static vm_fault_t psb_gem_fault(struct vm_fault *vmf)
> {
> struct vm_area_struct *vma = vmf->vma;
> struct drm_gem_object *obj;
> diff --git a/drivers/gpu/drm/gma500/gem.h b/drivers/gpu/drm/gma500/gem.h
> index 4a74dc623b6b..3741a711b9fd 100644
> --- a/drivers/gpu/drm/gma500/gem.h
> +++ b/drivers/gpu/drm/gma500/gem.h
> @@ -8,6 +8,9 @@
> #ifndef _GEM_H
> #define _GEM_H
>
> +extern const struct drm_gem_object_funcs psb_gem_object_funcs;
> +
> extern int psb_gem_create(struct drm_file *file, struct drm_device *dev,
> u64 size, u32 *handlep, int stolen, u32 align);
> +
> #endif
> diff --git a/drivers/gpu/drm/gma500/psb_drv.c
> b/drivers/gpu/drm/gma500/psb_drv.c
> index 34b4aae9a15e..b13376a6fb91 100644
> --- a/drivers/gpu/drm/gma500/psb_drv.c
> +++ b/drivers/gpu/drm/gma500/psb_drv.c
> @@ -480,12 +480,6 @@ static const struct dev_pm_ops psb_pm_ops = {
> .runtime_idle = psb_runtime_idle,
> };
>
> -static const struct vm_operations_struct psb_gem_vm_ops = {
> - .fault = psb_gem_fault,
> - .open = drm_gem_vm_open,
> - .close = drm_gem_vm_close,
> -};
> -
> static const struct file_operations psb_gem_fops = {
> .owner = THIS_MODULE,
> .open = drm_open,
> @@ -507,9 +501,6 @@ static struct drm_driver driver = {
> .irq_uninstall = psb_irq_uninstall,
> .irq_handler = psb_irq_handler,
>
> - .gem_free_object_unlocked = psb_gem_free_object,
> - .gem_vm_ops = _gem_vm_ops,
> -
> .dumb_create = psb_gem_dumb_create,
> .ioctls = psb_ioctls,
> .fops = _gem_fops,
> diff --git a/drivers/gpu/drm/gma500/psb_drv.h
> b/drivers/gpu/drm/gma500/psb_drv.h
> index 956926341316..c71a5a4e912c 100644
> --- a/drivers/gpu/drm/gma500/psb_drv.h
> +++ b/drivers/gpu/drm/gma500/psb_drv.h
>
Re: [PATCH v2 04/21] drm/exynos: Introduce GEM object functions
On Wed, Sep 16, 2020 at 12:36:28PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 16.09.20 um 12:03 schrieb Daniel Vetter:
> > On Tue, Sep 15, 2020 at 04:59:41PM +0200, Thomas Zimmermann wrote:
> >> GEM object functions deprecate several similar callback interfaces in
> >> struct drm_driver. This patch replaces the per-driver callbacks with
> >> per-instance callbacks in exynos. The only exception is gem_prime_mmap,
> >> which is non-trivial to convert.
> >>
> >> Signed-off-by: Thomas Zimmermann
> >> ---
> >> drivers/gpu/drm/exynos/exynos_drm_drv.c | 10 --
> >> drivers/gpu/drm/exynos/exynos_drm_gem.c | 15 +++
> >> 2 files changed, 15 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c
> >> b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> >> index dbd80f1e4c78..fe46680ca208 100644
> >> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
> >> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> >> @@ -75,11 +75,6 @@ static void exynos_drm_postclose(struct drm_device
> >> *dev, struct drm_file *file)
> >>file->driver_priv = NULL;
> >> }
> >>
> >> -static const struct vm_operations_struct exynos_drm_gem_vm_ops = {
> >> - .open = drm_gem_vm_open,
> >> - .close = drm_gem_vm_close,
> >> -};
> >> -
> >> static const struct drm_ioctl_desc exynos_ioctls[] = {
> >>DRM_IOCTL_DEF_DRV(EXYNOS_GEM_CREATE, exynos_drm_gem_create_ioctl,
> >>DRM_RENDER_ALLOW),
> >> @@ -124,16 +119,11 @@ static struct drm_driver exynos_drm_driver = {
> >>.open = exynos_drm_open,
> >>.lastclose = drm_fb_helper_lastclose,
> >>.postclose = exynos_drm_postclose,
> >> - .gem_free_object_unlocked = exynos_drm_gem_free_object,
> >> - .gem_vm_ops = _drm_gem_vm_ops,
> >>.dumb_create= exynos_drm_gem_dumb_create,
> >>.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> >>.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> >>.gem_prime_import = exynos_drm_gem_prime_import,
> >> - .gem_prime_get_sg_table = exynos_drm_gem_prime_get_sg_table,
> >>.gem_prime_import_sg_table = exynos_drm_gem_prime_import_sg_table,
> >> - .gem_prime_vmap = exynos_drm_gem_prime_vmap,
> >> - .gem_prime_vunmap = exynos_drm_gem_prime_vunmap,
> >>.gem_prime_mmap = exynos_drm_gem_prime_mmap,
> >>.ioctls = exynos_ioctls,
> >>.num_ioctls = ARRAY_SIZE(exynos_ioctls),
> >> diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c
> >> b/drivers/gpu/drm/exynos/exynos_drm_gem.c
> >> index efa476858db5..69a5cf28b4ae 100644
> >> --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
> >> +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
> >> @@ -129,6 +129,19 @@ void exynos_drm_gem_destroy(struct exynos_drm_gem
> >> *exynos_gem)
> >>kfree(exynos_gem);
> >> }
> >>
> >> +static const struct vm_operations_struct exynos_drm_gem_vm_ops = {
> >> + .open = drm_gem_vm_open,
> >> + .close = drm_gem_vm_close,
> >> +};
> >
> > Hm moving the drm_gem_cma_vm_ops into drm_gem.h or so and maybe calling
> > them drm_gem_simple_ops or so would remove a pile of these. But perhaps a
> > quick follow up series.
>
> Good idea. Several interfaces use the term 'default' in their name, so
> something like drm_gem_default_vm_ops seems appropriate.
Default sounds like a fine naming choice too.
> BTW is there a reason why we have file operations like
> DEFINE_DRM_GEM_CMA_FOPS() in each module? It seems like this could also
> be provided by the rsp memory-manager library.
It's for the module reference counting of the underlying file. So
file_operations need this.
-Daniel
>
> Best regards
> Thomas
>
> >
> > Reviewed-by: Daniel Vetter
> >
> >> +
> >> +static const struct drm_gem_object_funcs exynos_drm_gem_object_funcs = {
> >> + .free = exynos_drm_gem_free_object,
> >> + .get_sg_table = exynos_drm_gem_prime_get_sg_table,
> >> + .vmap = exynos_drm_gem_prime_vmap,
> >> + .vunmap = exynos_drm_gem_prime_vunmap,
> >> + .vm_ops = _drm_gem_vm_ops,
> >> +};
> >> +
> >> static struct exynos_drm_gem *exynos_drm_gem_init(struct drm_device *dev,
> >> unsigned long size)
> >> {
> >> @@ -143,6 +156,8 @@ static struct exynos_drm_gem
> >> *exynos_drm_gem_init(struct drm_device *dev,
> >>exynos_gem->size = size;
> >>obj = _gem->base;
> >>
> >> + obj->funcs = _drm_gem_object_funcs;
> >> +
> >>ret = drm_gem_object_init(dev, obj, size);
> >>if (ret < 0) {
> >>DRM_DEV_ERROR(dev->dev, "failed to initialize gem object\n");
> >> --
> >> 2.28.0
> >>
> >
>
> --
> Thomas Zimmermann
> Graphics Driver Developer
> SUSE Software Solutions Germany GmbH
> Maxfeldstr. 5, 90409 Nürnberg, Germany
> (HRB 36809, AG Nürnberg)
> Geschäftsführer: Felix Imendörffer
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
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Re: [PATCH v2 03/21] drm/etnaviv: Introduce GEM object functions
On Tue, Sep 15, 2020 at 04:59:40PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in etnaviv. The only exception is gem_prime_mmap,
> which is non-trivial to convert.
>
> Signed-off-by: Thomas Zimmermann
> ---
> drivers/gpu/drm/etnaviv/etnaviv_drv.c | 13 -
> drivers/gpu/drm/etnaviv/etnaviv_drv.h | 1 -
> drivers/gpu/drm/etnaviv/etnaviv_gem.c | 19 ++-
> 3 files changed, 18 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
> b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
> index a9a3afaef9a1..aa270b79e585 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
> @@ -468,12 +468,6 @@ static const struct drm_ioctl_desc etnaviv_ioctls[] = {
> ETNA_IOCTL(PM_QUERY_SIG, pm_query_sig, DRM_RENDER_ALLOW),
> };
>
> -static const struct vm_operations_struct vm_ops = {
> - .fault = etnaviv_gem_fault,
> - .open = drm_gem_vm_open,
> - .close = drm_gem_vm_close,
> -};
> -
> static const struct file_operations fops = {
> .owner = THIS_MODULE,
> .open = drm_open,
> @@ -490,16 +484,9 @@ static struct drm_driver etnaviv_drm_driver = {
> .driver_features= DRIVER_GEM | DRIVER_RENDER,
> .open = etnaviv_open,
> .postclose = etnaviv_postclose,
> - .gem_free_object_unlocked = etnaviv_gem_free_object,
> - .gem_vm_ops = _ops,
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> - .gem_prime_pin = etnaviv_gem_prime_pin,
> - .gem_prime_unpin= etnaviv_gem_prime_unpin,
> - .gem_prime_get_sg_table = etnaviv_gem_prime_get_sg_table,
> .gem_prime_import_sg_table = etnaviv_gem_prime_import_sg_table,
> - .gem_prime_vmap = etnaviv_gem_prime_vmap,
> - .gem_prime_vunmap = etnaviv_gem_prime_vunmap,
> .gem_prime_mmap = etnaviv_gem_prime_mmap,
> #ifdef CONFIG_DEBUG_FS
> .debugfs_init = etnaviv_debugfs_init,
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
> b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
> index 4d8dc9236e5f..914f0867ff71 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
> @@ -49,7 +49,6 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void
> *data,
> struct drm_file *file);
>
> int etnaviv_gem_mmap(struct file *filp, struct vm_area_struct *vma);
> -vm_fault_t etnaviv_gem_fault(struct vm_fault *vmf);
> int etnaviv_gem_mmap_offset(struct drm_gem_object *obj, u64 *offset);
> struct sg_table *etnaviv_gem_prime_get_sg_table(struct drm_gem_object *obj);
> void *etnaviv_gem_prime_vmap(struct drm_gem_object *obj);
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
> b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
> index ea19f1d27275..312e9d58d5a7 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
> @@ -171,7 +171,7 @@ int etnaviv_gem_mmap(struct file *filp, struct
> vm_area_struct *vma)
> return obj->ops->mmap(obj, vma);
> }
>
> -vm_fault_t etnaviv_gem_fault(struct vm_fault *vmf)
> +static vm_fault_t etnaviv_gem_fault(struct vm_fault *vmf)
> {
> struct vm_area_struct *vma = vmf->vma;
> struct drm_gem_object *obj = vma->vm_private_data;
> @@ -561,6 +561,22 @@ void etnaviv_gem_obj_add(struct drm_device *dev, struct
> drm_gem_object *obj)
> mutex_unlock(>gem_lock);
> }
>
> +static const struct vm_operations_struct vm_ops = {
> + .fault = etnaviv_gem_fault,
> + .open = drm_gem_vm_open,
> + .close = drm_gem_vm_close,
> +};
> +
> +static const struct drm_gem_object_funcs etnaviv_gem_object_funcs = {
> + .free = etnaviv_gem_free_object,
> + .pin = etnaviv_gem_prime_pin,
> + .unpin = etnaviv_gem_prime_unpin,
> + .get_sg_table = etnaviv_gem_prime_get_sg_table,
> + .vmap = etnaviv_gem_prime_vmap,
> + .vunmap = etnaviv_gem_prime_vunmap,
> + .vm_ops = _ops,
> +};
Reviewed-by: Daniel Vetter
> +
> static int etnaviv_gem_new_impl(struct drm_device *dev, u32 size, u32 flags,
> const struct etnaviv_gem_ops *ops, struct drm_gem_object **obj)
> {
> @@ -595,6 +611,7 @@ static int etnaviv_gem_new_impl(struct drm_device *dev,
> u32 size, u32 flags,
> INIT_LIST_HEAD(_obj->vram_list);
>
> *obj = _obj->base;
> + (*obj)->funcs = _gem_object_funcs;
>
> return 0;
> }
> --
> 2.28.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH v2 04/21] drm/exynos: Introduce GEM object functions
Hi
Am 16.09.20 um 12:03 schrieb Daniel Vetter:
> On Tue, Sep 15, 2020 at 04:59:41PM +0200, Thomas Zimmermann wrote:
>> GEM object functions deprecate several similar callback interfaces in
>> struct drm_driver. This patch replaces the per-driver callbacks with
>> per-instance callbacks in exynos. The only exception is gem_prime_mmap,
>> which is non-trivial to convert.
>>
>> Signed-off-by: Thomas Zimmermann
>> ---
>> drivers/gpu/drm/exynos/exynos_drm_drv.c | 10 --
>> drivers/gpu/drm/exynos/exynos_drm_gem.c | 15 +++
>> 2 files changed, 15 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c
>> b/drivers/gpu/drm/exynos/exynos_drm_drv.c
>> index dbd80f1e4c78..fe46680ca208 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
>> @@ -75,11 +75,6 @@ static void exynos_drm_postclose(struct drm_device *dev,
>> struct drm_file *file)
>> file->driver_priv = NULL;
>> }
>>
>> -static const struct vm_operations_struct exynos_drm_gem_vm_ops = {
>> -.open = drm_gem_vm_open,
>> -.close = drm_gem_vm_close,
>> -};
>> -
>> static const struct drm_ioctl_desc exynos_ioctls[] = {
>> DRM_IOCTL_DEF_DRV(EXYNOS_GEM_CREATE, exynos_drm_gem_create_ioctl,
>> DRM_RENDER_ALLOW),
>> @@ -124,16 +119,11 @@ static struct drm_driver exynos_drm_driver = {
>> .open = exynos_drm_open,
>> .lastclose = drm_fb_helper_lastclose,
>> .postclose = exynos_drm_postclose,
>> -.gem_free_object_unlocked = exynos_drm_gem_free_object,
>> -.gem_vm_ops = _drm_gem_vm_ops,
>> .dumb_create= exynos_drm_gem_dumb_create,
>> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
>> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>> .gem_prime_import = exynos_drm_gem_prime_import,
>> -.gem_prime_get_sg_table = exynos_drm_gem_prime_get_sg_table,
>> .gem_prime_import_sg_table = exynos_drm_gem_prime_import_sg_table,
>> -.gem_prime_vmap = exynos_drm_gem_prime_vmap,
>> -.gem_prime_vunmap = exynos_drm_gem_prime_vunmap,
>> .gem_prime_mmap = exynos_drm_gem_prime_mmap,
>> .ioctls = exynos_ioctls,
>> .num_ioctls = ARRAY_SIZE(exynos_ioctls),
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c
>> b/drivers/gpu/drm/exynos/exynos_drm_gem.c
>> index efa476858db5..69a5cf28b4ae 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
>> @@ -129,6 +129,19 @@ void exynos_drm_gem_destroy(struct exynos_drm_gem
>> *exynos_gem)
>> kfree(exynos_gem);
>> }
>>
>> +static const struct vm_operations_struct exynos_drm_gem_vm_ops = {
>> +.open = drm_gem_vm_open,
>> +.close = drm_gem_vm_close,
>> +};
>
> Hm moving the drm_gem_cma_vm_ops into drm_gem.h or so and maybe calling
> them drm_gem_simple_ops or so would remove a pile of these. But perhaps a
> quick follow up series.
Good idea. Several interfaces use the term 'default' in their name, so
something like drm_gem_default_vm_ops seems appropriate.
BTW is there a reason why we have file operations like
DEFINE_DRM_GEM_CMA_FOPS() in each module? It seems like this could also
be provided by the rsp memory-manager library.
Best regards
Thomas
>
> Reviewed-by: Daniel Vetter
>
>> +
>> +static const struct drm_gem_object_funcs exynos_drm_gem_object_funcs = {
>> +.free = exynos_drm_gem_free_object,
>> +.get_sg_table = exynos_drm_gem_prime_get_sg_table,
>> +.vmap = exynos_drm_gem_prime_vmap,
>> +.vunmap = exynos_drm_gem_prime_vunmap,
>> +.vm_ops = _drm_gem_vm_ops,
>> +};
>> +
>> static struct exynos_drm_gem *exynos_drm_gem_init(struct drm_device *dev,
>>unsigned long size)
>> {
>> @@ -143,6 +156,8 @@ static struct exynos_drm_gem *exynos_drm_gem_init(struct
>> drm_device *dev,
>> exynos_gem->size = size;
>> obj = _gem->base;
>>
>> +obj->funcs = _drm_gem_object_funcs;
>> +
>> ret = drm_gem_object_init(dev, obj, size);
>> if (ret < 0) {
>> DRM_DEV_ERROR(dev->dev, "failed to initialize gem object\n");
>> --
>> 2.28.0
>>
>
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer
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Re: [PATCH v2 04/21] drm/exynos: Introduce GEM object functions
On Tue, Sep 15, 2020 at 04:59:41PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in exynos. The only exception is gem_prime_mmap,
> which is non-trivial to convert.
>
> Signed-off-by: Thomas Zimmermann
> ---
> drivers/gpu/drm/exynos/exynos_drm_drv.c | 10 --
> drivers/gpu/drm/exynos/exynos_drm_gem.c | 15 +++
> 2 files changed, 15 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c
> b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> index dbd80f1e4c78..fe46680ca208 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> @@ -75,11 +75,6 @@ static void exynos_drm_postclose(struct drm_device *dev,
> struct drm_file *file)
> file->driver_priv = NULL;
> }
>
> -static const struct vm_operations_struct exynos_drm_gem_vm_ops = {
> - .open = drm_gem_vm_open,
> - .close = drm_gem_vm_close,
> -};
> -
> static const struct drm_ioctl_desc exynos_ioctls[] = {
> DRM_IOCTL_DEF_DRV(EXYNOS_GEM_CREATE, exynos_drm_gem_create_ioctl,
> DRM_RENDER_ALLOW),
> @@ -124,16 +119,11 @@ static struct drm_driver exynos_drm_driver = {
> .open = exynos_drm_open,
> .lastclose = drm_fb_helper_lastclose,
> .postclose = exynos_drm_postclose,
> - .gem_free_object_unlocked = exynos_drm_gem_free_object,
> - .gem_vm_ops = _drm_gem_vm_ops,
> .dumb_create= exynos_drm_gem_dumb_create,
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> .gem_prime_import = exynos_drm_gem_prime_import,
> - .gem_prime_get_sg_table = exynos_drm_gem_prime_get_sg_table,
> .gem_prime_import_sg_table = exynos_drm_gem_prime_import_sg_table,
> - .gem_prime_vmap = exynos_drm_gem_prime_vmap,
> - .gem_prime_vunmap = exynos_drm_gem_prime_vunmap,
> .gem_prime_mmap = exynos_drm_gem_prime_mmap,
> .ioctls = exynos_ioctls,
> .num_ioctls = ARRAY_SIZE(exynos_ioctls),
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c
> b/drivers/gpu/drm/exynos/exynos_drm_gem.c
> index efa476858db5..69a5cf28b4ae 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
> @@ -129,6 +129,19 @@ void exynos_drm_gem_destroy(struct exynos_drm_gem
> *exynos_gem)
> kfree(exynos_gem);
> }
>
> +static const struct vm_operations_struct exynos_drm_gem_vm_ops = {
> + .open = drm_gem_vm_open,
> + .close = drm_gem_vm_close,
> +};
Hm moving the drm_gem_cma_vm_ops into drm_gem.h or so and maybe calling
them drm_gem_simple_ops or so would remove a pile of these. But perhaps a
quick follow up series.
Reviewed-by: Daniel Vetter
> +
> +static const struct drm_gem_object_funcs exynos_drm_gem_object_funcs = {
> + .free = exynos_drm_gem_free_object,
> + .get_sg_table = exynos_drm_gem_prime_get_sg_table,
> + .vmap = exynos_drm_gem_prime_vmap,
> + .vunmap = exynos_drm_gem_prime_vunmap,
> + .vm_ops = _drm_gem_vm_ops,
> +};
> +
> static struct exynos_drm_gem *exynos_drm_gem_init(struct drm_device *dev,
> unsigned long size)
> {
> @@ -143,6 +156,8 @@ static struct exynos_drm_gem *exynos_drm_gem_init(struct
> drm_device *dev,
> exynos_gem->size = size;
> obj = _gem->base;
>
> + obj->funcs = _drm_gem_object_funcs;
> +
> ret = drm_gem_object_init(dev, obj, size);
> if (ret < 0) {
> DRM_DEV_ERROR(dev->dev, "failed to initialize gem object\n");
> --
> 2.28.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] Revert "drm/radeon: handle PCIe root ports with addressing limitations"
On Wed, Sep 16, 2020 at 08:33:00AM +0200, Greg KH wrote:
> On Tue, Sep 15, 2020 at 02:46:07PM -0400, Alex Deucher wrote:
> > This change breaks tons of systems.
>
> Very vague :(
>
> This commit has also been merged for over a year, why the sudden
> problem now?
Unrelated rant, but one year is generally what it takes for most users to
upgrade to new kernels, through their distro updates. Especially for older
hw like the radeon drivers (since 5 years or so amd gpus switched over to
amdgpu.ko).
So surprise that bugs only show up after 1+ year shouldn't be a surprise
:-) My personal rule is that I put a 1 year spacer between a risky change
and any cleanup that enables. Too many regrets in the past.
Cheers, Daniel
>
> > This reverts commit 33b3ad3788aba846fc8b9a065fe2685a0b64f713.
>
> You mean "33b3ad3788ab ("drm/radeon: handle PCIe root ports with
> addressing limitations")"?
>
> That's the proper way to reference commits in changelogs please. It's
> even documented that way...
>
> >
> > Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206973
> > Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206697
> > Bug: https://bugzilla.kernel.org/show_bug.cgi?id=207763
> > Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1140
> > Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1287
> > Signed-off-by: Alex Deucher
> > Cc: sta...@vger.kernel.org
> > Cc: Christoph Hellwig
> > Cc: christian.koe...@amd.com
>
> Fixes: 33b3ad3788ab ("drm/radeon: handle PCIe root ports with addressing
> limitations")
>
> as well?
>
> thanks,
>
> greg k-h
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Re: [PATCH v2 0/4] Enlarge tracepoints in the display component
On Fri, Sep 11, 2020 at 10:59:23AM -0400, Rodrigo Siqueira wrote: > Debug issues related to display can be a challenge due to the complexity > around this topic and different source of information might help in this > process. We already have support for tracepoints inside the display > component, i.e., we have the basic functionalities available and we just > need to expand it in order to make it more valuable for debugging. For > this reason, this patchset reworks part of the current tracepoint > options and add different sets of tracing inside amdgpu_dm, display > core, and DCN10. The first patch of this series just rework part of the > current tracepoints and the last set of patches introduces new > tracepoints. > > This first patchset version is functional. Please, let me know what I > can improve in the current version but also let me know what kind of > tracepoint I can add for the next version. > > Finally, I want to highlight that this work is based on a set of patches > originally made by Nicholas Kazlauskas. > > Change in V2: > - I added another patch for capturing the clock state for different display > architecture. Hm I'm not super sure tracepoints for state dumping are the right thing here. We kinda have the atomic state dumping code with all the various callbacks, and you can extend that pretty easily. Gives you full state dump in debugfs, plus a few function to dump into dmesg. Maybe what we need is a function to dump this also into printk tracepoint (otoh with Sean Paul's tracepoint work we'd get that through the dmesg stuff already), and then you could do it there? Upside is that for customers they'd get a much more consistent way to debug display issues across different drivers. For low-level hw debug what we do is give the hw guys an mmio trace, and they replay it on the fancy boxes :-) So for that I think this here is again too high level, but maybe what you have is a bit different. -Daniel > > Rodrigo Siqueira (4): > drm/amd/display: Rework registers tracepoint > drm/amd/display: Add tracepoint for amdgpu_dm > drm/amd/display: Add pipe_state tracepoint > drm/amd/display: Add tracepoint for capturing clocks state > > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 + > .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 712 +- > .../dc/clk_mgr/dce112/dce112_clk_mgr.c| 5 + > .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c| 4 + > .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 4 + > .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 4 + > .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 4 + > drivers/gpu/drm/amd/display/dc/core/dc.c | 11 + > .../gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 5 + > .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 17 +- > 10 files changed, 747 insertions(+), 36 deletions(-) > > -- > 2.28.0 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH -next 0/8] drm/amd/amdgpu: fix comparison pointer to bool warning
On Wed, Sep 16, 2020 at 09:38:34AM +0200, Christian König wrote: > Am 15.09.20 um 21:35 schrieb Ville Syrjälä: > > On Tue, Sep 15, 2020 at 03:16:32PM -0400, Alex Deucher wrote: > > > I question the value of these warnings. Why even have a boolean type > > > if you are going to get warnings when you use them... > > > That said, applied to avoid getting these patches again and again > > > every time someone sees this. > > if (this_is_sparta) > > if (this_is_sparta == true) > > if (this_is_sparta != false) > > > > I think the first one reads the best, and avoids having to > > decide between truth and falsehood :) > > +1 +1, especially because we also have the inversion when using negative errno codes for failures and 0 as success, which results in if (errno == 0) /* success case */ but if (bool == 0) /* failure case */ now creative people do sometimes if (!errno) /* success case */ which I think is horribly confusing. So imo for more easier telling apart of these too I think consistently using the short form for booleans, and consistently using the more explicit long form for errno checks is a Very Good Pattern :-) Cheers, Daniel > > Christian. > > > > > > Alex > > > > > > On Wed, Sep 9, 2020 at 9:21 AM Christian König > > > wrote: > > > > Acked-by: Christian König for the series. > > > > > > > > Am 09.09.20 um 15:07 schrieb Zheng Bin: > > > > > Zheng Bin (8): > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > gfx_v9_0.c > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > gfx_v10_0.c > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > sdma_v5_0.c > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > sdma_v5_2.c > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in si.c > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > uvd_v6_0.c > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > amdgpu_atpx_handler.c > > > > > drm/amd/amdgpu: fix comparison pointer to bool warning in > > > > > sdma_v4_0.c > > > > > > > > > >drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 4 ++-- > > > > >drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- > > > > >drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 2 +- > > > > >drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- > > > > >drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- > > > > >drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +- > > > > >drivers/gpu/drm/amd/amdgpu/si.c | 2 +- > > > > >drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 4 ++-- > > > > >8 files changed, 11 insertions(+), 11 deletions(-) > > > > > > > > > > -- > > > > > 2.26.0.106.g9fadedd > > > > > > > > > ___ > > > > amd-gfx mailing list > > > > amd-gfx@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > > ___ > > > dri-devel mailing list > > > dri-de...@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: prevent double kfree ttm->sg
Am 15.09.20 um 23:52 schrieb Philip Yang: Set ttm->sg to NULL after kfree, to avoid memory corruption backtrace: [ 420.932812] kernel BUG at /build/linux-do9eLF/linux-4.15.0/mm/slub.c:295! [ 420.934182] invalid opcode: [#1] SMP NOPTI [ 420.935445] Modules linked in: xt_conntrack ipt_MASQUERADE [ 420.951332] Hardware name: Dell Inc. PowerEdge R7525/0PYVT1, BIOS 1.5.4 07/09/2020 [ 420.952887] RIP: 0010:__slab_free+0x180/0x2d0 [ 420.954419] RSP: 0018:be426291fa60 EFLAGS: 00010246 [ 420.955963] RAX: 9e29263e9c30 RBX: 9e29263e9c30 RCX: 0001814b [ 420.957512] RDX: 9e29263e9c30 RSI: f3d33e98fa40 RDI: 9e297e407a80 [ 420.959055] RBP: be426291fb00 R08: 0001 R09: c0d39ade [ 420.960587] R10: be426291fb20 R11: 9e49ffdd4000 R12: 9e297e407a80 [ 420.962105] R13: f3d33e98fa40 R14: 9e29263e9c30 R15: 9e2954464fd8 [ 420.963611] FS: 7fa2ea097780() GS:9e297e84() knlGS: [ 420.965144] CS: 0010 DS: ES: CR0: 80050033 [ 420.93] CR2: 7f16bfffefb8 CR3: 001ff0c62000 CR4: 00340ee0 [ 420.968193] Call Trace: [ 420.969703] ? __page_cache_release+0x3c/0x220 [ 420.971294] ? amdgpu_ttm_tt_unpopulate+0x5e/0x80 [amdgpu] [ 420.972789] kfree+0x168/0x180 [ 420.974353] ? amdgpu_ttm_tt_set_user_pages+0x64/0xc0 [amdgpu] [ 420.975850] ? kfree+0x168/0x180 [ 420.977403] amdgpu_ttm_tt_unpopulate+0x5e/0x80 [amdgpu] [ 420.97] ttm_tt_unpopulate.part.10+0x53/0x60 [amdttm] [ 420.980357] ttm_tt_destroy.part.11+0x4f/0x60 [amdttm] [ 420.981814] ttm_tt_destroy+0x13/0x20 [amdttm] [ 420.983273] ttm_bo_cleanup_memtype_use+0x36/0x80 [amdttm] [ 420.984725] ttm_bo_release+0x1c9/0x360 [amdttm] [ 420.986167] amdttm_bo_put+0x24/0x30 [amdttm] [ 420.987663] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 420.989165] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x9ca/0xb10 [amdgpu] [ 420.990666] kfd_ioctl_alloc_memory_of_gpu+0xef/0x2c0 [amdgpu] Signed-off-by: Philip Yang Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 8b704451a18c..4b3ab9a25e91 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1076,6 +1076,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) release_sg: kfree(ttm->sg); + ttm->sg = NULL; return r; } ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH -next 0/8] drm/amd/amdgpu: fix comparison pointer to bool warning
Am 15.09.20 um 21:35 schrieb Ville Syrjälä: On Tue, Sep 15, 2020 at 03:16:32PM -0400, Alex Deucher wrote: I question the value of these warnings. Why even have a boolean type if you are going to get warnings when you use them... That said, applied to avoid getting these patches again and again every time someone sees this. if (this_is_sparta) if (this_is_sparta == true) if (this_is_sparta != false) I think the first one reads the best, and avoids having to decide between truth and falsehood :) +1 Christian. Alex On Wed, Sep 9, 2020 at 9:21 AM Christian König wrote: Acked-by: Christian König for the series. Am 09.09.20 um 15:07 schrieb Zheng Bin: Zheng Bin (8): drm/amd/amdgpu: fix comparison pointer to bool warning in gfx_v9_0.c drm/amd/amdgpu: fix comparison pointer to bool warning in gfx_v10_0.c drm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v5_0.c drm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v5_2.c drm/amd/amdgpu: fix comparison pointer to bool warning in si.c drm/amd/amdgpu: fix comparison pointer to bool warning in uvd_v6_0.c drm/amd/amdgpu: fix comparison pointer to bool warning in amdgpu_atpx_handler.c drm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v4_0.c drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +- drivers/gpu/drm/amd/amdgpu/si.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 4 ++-- 8 files changed, 11 insertions(+), 11 deletions(-) -- 2.26.0.106.g9fadedd ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ dri-devel mailing list dri-de...@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] Revert "drm/radeon: handle PCIe root ports with addressing limitations"
On Tue, Sep 15, 2020 at 02:46:07PM -0400, Alex Deucher wrote: > This change breaks tons of systems. Did you do at least some basic root causing on why? Do GPUs get fed address they can't deal with? Any examples? Bug 1 doesn't seem to contain any analysis and was reported against a very old kernel that had all kind of fixes since. Bug 2 seems to imply a drm kthread is accessing some structure it shouldn't, which would imply a mismatch between pools used by radeon now and those actually provided by the core. Something that should be pretty to trivial to fix for someone understanding the whole ttm pool maze. Bug 3: same as 1, but an even older kernel. Bug 4: looks like 1 and 3, and actually verified to work properly in 5.9-rc. Did you try to get the other reporters test this as well? All over not a very useful changelog. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] Revert "drm/radeon: handle PCIe root ports with addressing limitations"
On Tue, Sep 15, 2020 at 02:46:07PM -0400, Alex Deucher wrote:
> This change breaks tons of systems.
Very vague :(
This commit has also been merged for over a year, why the sudden
problem now?
> This reverts commit 33b3ad3788aba846fc8b9a065fe2685a0b64f713.
You mean "33b3ad3788ab ("drm/radeon: handle PCIe root ports with
addressing limitations")"?
That's the proper way to reference commits in changelogs please. It's
even documented that way...
>
> Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206973
> Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206697
> Bug: https://bugzilla.kernel.org/show_bug.cgi?id=207763
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1140
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1287
> Signed-off-by: Alex Deucher
> Cc: sta...@vger.kernel.org
> Cc: Christoph Hellwig
> Cc: christian.koe...@amd.com
Fixes: 33b3ad3788ab ("drm/radeon: handle PCIe root ports with addressing
limitations")
as well?
thanks,
greg k-h
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