[PATCH] drm/amdgpu: enable VCN PG and CG for vangogh
[AMD Official Use Only - Internal Distribution Only] Enable VCN 3.0 PG and CG for Vangogh by setting up flags. Signed-off-by: Boyuan Zhang --- drivers/gpu/drm/amd/amdgpu/nv.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 4b1a4acb60d9..ce787489aaeb 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -938,8 +938,13 @@ static int nv_common_early_init(void *handle) adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | - AMD_CG_SUPPORT_GFX_3D_CGLS; - adev->pg_flags = AMD_PG_SUPPORT_GFX_PG; + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_JPEG_MGCG; + adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | + AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_VCN_DPG | + AMD_PG_SUPPORT_JPEG; adev->external_rev_id = adev->rev_id + 0x01; break; -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amd/display: Avoid MST manager resource leak.
On 2020-10-15 11:02 p.m., Alex Deucher wrote: On Wed, Oct 14, 2020 at 1:25 PM Andrey Grodzovsky wrote: On connector destruction call drm_dp_mst_topology_mgr_destroy to release resources allocated in drm_dp_mst_topology_mgr_init. Do it only if MST manager was initialized before otherwsie a crash is seen on driver unload/device unplug. Not really an mst expert, but this seems to match what i915 and nouveau do. Series is: Acked-by: Alex Deucher Signed-off-by: Andrey Grodzovsky Looks reasonable to me. Untested, however. Reviewed-by: Nicholas Kazlauskas Regards, Nicholas Kazlauskas --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a72447d..64799c4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5170,6 +5170,13 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) struct amdgpu_device *adev = drm_to_adev(connector->dev); struct amdgpu_display_manager *dm = >dm; + /* +* Call only if mst_mgr was initialized before since it's not done +* for all connector types. +*/ + if (aconnector->mst_mgr.dev) + drm_dp_mst_topology_mgr_destroy(>mst_mgr); + #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/4] drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry
On Fri, Oct 16, 2020 at 5:21 AM Prike Liang wrote:
>
> The new amdgpu_gfx_state_change_set() funtion can support set GFX power
> change status to D0/D3.
>
> Signed-off-by: Prike Liang
> Acked-by: Huang Rui
> Reviewed-by: Alex Deucher
I presume we'll need something similar for renoir? That can be a
follow up patch.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 20
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 7 +++
> drivers/gpu/drm/amd/include/kgd_pp_interface.h| 1 +
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 20
> drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 9 +
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
> drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 3 ++-
> 7 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index d612033..e1d6c8a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -789,3 +789,23 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev,
> uint32_t reg, uint32_t v)
> failed_kiq_write:
> pr_err("failed to write reg:%x\n", reg);
> }
> +
> +/* amdgpu_gfx_state_change_set - Handle gfx power state change set
> + * @adev: amdgpu_device pointer
> + * @state: gfx power state(1 -eGpuChangeState_D0Entry and 2
> -eGpuChangeState_D3Entry)
> + *
> + */
> +
> +void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum
> gfx_change_state state)
> +{
> +
> + mutex_lock(>pm.mutex);
> +
> + if (adev->powerplay.pp_funcs &&
> + adev->powerplay.pp_funcs->gfx_state_change_set)
> + ((adev)->powerplay.pp_funcs->gfx_state_change_set(
> + (adev)->powerplay.pp_handle, state));
> +
> + mutex_unlock(>pm.mutex);
> +
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index d43c116..73942b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -47,6 +47,12 @@ enum gfx_pipe_priority {
> AMDGPU_GFX_PIPE_PRIO_MAX
> };
>
> +/* Argument for PPSMC_MSG_GpuChangeState */
> +enum gfx_change_state {
> + GpuChangeState_D0Entry = 1,
> + GpuChangeState_D3Entry,
> +};
> +
> #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
> #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
>
> @@ -387,4 +393,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device
> *adev,
> struct amdgpu_iv_entry *entry);
> uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
> void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
> +void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum
> gfx_change_state state);
> #endif
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index a7f92d0..e7b69dd 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -284,6 +284,7 @@ struct amd_pm_funcs {
> int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input,
> uint32_t size);
> int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
> int (*smu_i2c_bus_access)(void *handle, bool acquire);
> + int (*gfx_state_change_set)(void *handle, uint32_t state);
> /* export to DC */
> u32 (*get_sclk)(void *handle, bool low);
> u32 (*get_mclk)(void *handle, bool low);
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 7e6dcdf..4f319be 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1321,6 +1321,25 @@ static int pp_set_powergating_by_smu(void *handle,
> return ret;
> }
>
> +static int pp_gfx_state_change_set(void *handle, uint32_t state)
> +{
> + struct pp_hwmgr *hwmgr = handle;
> +
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
> +
> + if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
> + pr_info_ratelimited("%s was not implemented.\n", __func__);
> + return -EINVAL;
> + }
> +
> + mutex_lock(>smu_lock);
> + hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
> + mutex_unlock(>smu_lock);
> +
> + return 0;
> +}
> +
> static int pp_notify_smu_enable_pwe(void *handle)
> {
> struct pp_hwmgr *hwmgr = handle;
> @@ -1625,6 +1644,7 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
> .switch_power_profile = pp_dpm_switch_power_profile,
> .set_clockgating_by_smu = pp_set_clockgating_by_smu,
> .set_powergating_by_smu = pp_set_powergating_by_smu,
> + .gfx_state_change_set = pp_gfx_state_change_set,
>
[PATCH] drm/amdgpu/gmc10: remove dummy read workaround for newer chips
Sienna Cichlid and newer have a hw fix so no longer require the workaround. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index f7a8417b2946..40af17610207 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -107,7 +107,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, * be updated to avoid reading an incorrect value due to * the new fast GRBM interface. */ - if (entry->vmid_src == AMDGPU_GFXHUB_0) + if ((entry->vmid_src == AMDGPU_GFXHUB_0) && + (adev->asic_type < CHIP_SIENNA_CICHLID)) RREG32(hub->vm_l2_pro_fault_status); status = RREG32(hub->vm_l2_pro_fault_status); @@ -232,7 +233,8 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, * Issue a dummy read to wait for the ACK register to be cleared * to avoid a false ACK due to the new fast GRBM interface. */ - if (vmhub == AMDGPU_GFXHUB_0) + if ((vmhub == AMDGPU_GFXHUB_0) && + (adev->asic_type < CHIP_SIENNA_CICHLID)) RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng); /* Wait for ACK with a delay.*/ -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/4] drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN
Avoids confusion in configurations. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 - drivers/gpu/drm/amd/display/Kconfig | 27 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 60 +++ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 - drivers/gpu/drm/amd/display/dc/Makefile | 10 .../drm/amd/display/dc/bios/bios_parser2.c| 18 -- .../display/dc/bios/command_table_helper2.c | 12 .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 - .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 4 -- .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 14 + drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 34 ++- .../gpu/drm/amd/display/dc/core/dc_stream.c | 12 ++-- drivers/gpu/drm/amd/display/dc/dc.h | 22 +++ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 18 -- drivers/gpu/drm/amd/display/dc/dc_stream.h| 6 -- drivers/gpu/drm/amd/display/dc/dc_types.h | 10 +--- drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 6 -- .../drm/amd/display/dc/dce/dce_clock_source.c | 8 +-- .../drm/amd/display/dc/dce/dce_clock_source.h | 12 ++-- .../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 31 -- .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 2 - .../amd/display/dc/dcn10/dcn10_link_encoder.h | 9 --- .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 5 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 31 -- .../display/dc/dcn10/dcn10_stream_encoder.h | 8 --- .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 8 --- .../drm/amd/display/dc/dcn20/dcn20_hubbub.c | 4 -- .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 6 -- .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 18 -- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 13 +--- .../amd/display/dc/dcn20/dcn20_link_encoder.h | 2 - .../drm/amd/display/dc/dcn20/dcn20_resource.c | 23 +-- .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 7 --- .../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h | 2 - drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 - drivers/gpu/drm/amd/display/dc/dm_pp_smu.h| 6 +- drivers/gpu/drm/amd/display/dc/dml/Makefile | 5 -- .../dc/dml/dcn30/display_mode_vba_30.c| 4 +- .../dc/dml/dcn30/display_rq_dlg_calc_30.c | 2 +- .../drm/amd/display/dc/dml/display_mode_lib.c | 10 +--- .../drm/amd/display/dc/dml/display_mode_lib.h | 4 -- .../amd/display/dc/dml/display_mode_structs.h | 2 - .../drm/amd/display/dc/dml/display_mode_vba.c | 2 - .../drm/amd/display/dc/dml/display_mode_vba.h | 2 - drivers/gpu/drm/amd/display/dc/gpio/Makefile | 5 +- .../display/dc/gpio/dcn30/hw_factory_dcn30.c | 2 +- .../display/dc/gpio/dcn30/hw_factory_dcn30.h | 2 +- .../dc/gpio/dcn30/hw_translate_dcn30.c| 2 +- .../dc/gpio/dcn30/hw_translate_dcn30.h| 2 +- .../gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 --- .../drm/amd/display/dc/gpio/hw_translate.c| 9 --- .../gpu/drm/amd/display/dc/inc/core_types.h | 8 +-- .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 26 +--- .../amd/display/dc/inc/hw/clk_mgr_internal.h | 7 +-- .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 6 -- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 - drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 6 +- drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 -- .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 2 - .../gpu/drm/amd/display/dc/inc/hw/mcif_wb.h | 4 -- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 19 +- .../amd/display/dc/inc/hw/stream_encoder.h| 2 - .../amd/display/dc/inc/hw/timing_generator.h | 6 -- .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 -- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 - drivers/gpu/drm/amd/display/dc/irq/Makefile | 4 -- .../display/dc/irq/dcn30/irq_service_dcn30.c | 2 +- .../display/dc/irq/dcn30/irq_service_dcn30.h | 2 +- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 6 -- drivers/gpu/drm/amd/display/dmub/src/Makefile | 4 -- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 18 -- .../gpu/drm/amd/display/include/dal_asic_id.h | 6 -- .../gpu/drm/amd/display/include/dal_types.h | 6 -- .../display/include/grph_object_ctrl_defs.h | 4 -- .../amd/display/modules/power/power_helpers.c | 11 +--- 77 files changed, 81 insertions(+), 614 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index fb9e61f861e9..13955d6ec113 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3002,8 +3002,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) case CHIP_NAVI14: case CHIP_NAVI12: case CHIP_RENOIR: -#endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case
[PATCH 2/4] drm/amdgpu/display: remove dal_cmd_tbl_helper_dcn2_get_table2
It's unused and identical to dal_cmd_tbl_helper_dce112_get_table2.
Signed-off-by: Alex Deucher
---
.../dce112/command_table_helper2_dce112.c | 40 ---
.../dce112/command_table_helper2_dce112.h | 3 --
2 files changed, 43 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
index bf0affef893f..755b6e33140a 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
@@ -388,43 +388,3 @@ const struct command_table_helper
*dal_cmd_tbl_helper_dce112_get_table2(void)
{
return _table_helper_funcs;
}
-
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-/* function table */
-static const struct command_table_helper command_table_helper_funcs_dcn2x = {
- .controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom2,
- .encoder_action_to_atom = encoder_action_to_atom,
- .engine_bp_to_atom = engine_bp_to_atom,
- .clock_source_id_to_atom = clock_source_id_to_atom,
- .clock_source_id_to_atom_phy_clk_src_id =
- clock_source_id_to_atom_phy_clk_src_id,
- .signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
- .hpd_sel_to_atom = hpd_sel_to_atom,
- .dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
- .phy_id_to_atom = phy_id_to_atom,
- .disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
- .clock_source_id_to_ref_clk_src = NULL,
- .transmitter_bp_to_atom = NULL,
- .encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom2,
- .encoder_mode_bp_to_atom =
- dal_cmd_table_helper_encoder_mode_bp_to_atom2,
- .dc_clock_type_to_atom = dc_clock_type_to_atom,
- .transmitter_color_depth_to_atom = transmitter_color_depth_to_atom,
-
-};
-
-/*
- * dal_cmd_tbl_helper_dce110_get_table
- *
- * @brief
- * Initialize command table helper functions
- *
- * @param
- * const struct command_table_helper **h - [out] struct of functions
- *
- */
-const struct command_table_helper *dal_cmd_tbl_helper_dcn2_get_table2(void)
-{
- return _table_helper_funcs_dcn2x;
-}
-#endif
diff --git
a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
index 2d9e9f3c579d..abf28a06f5bc 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
@@ -30,8 +30,5 @@ struct command_table_helper;
/* Initialize command table helper functions */
const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table2(void);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-const struct command_table_helper *dal_cmd_tbl_helper_dcn2_get_table2(void);
-#endif
#endif /* __DAL_COMMAND_TABLE_HELPER_DCE110_H__ */
--
2.25.4
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[PATCH 3/4] drm/amdgpu: drop CONFIG_DRM_AMD_DC_DCN3_01 from atomfirmware.h
Not needed.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/atomfirmware.h | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 4eb578b1baef..6139d10f4289 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1309,9 +1309,6 @@ struct atom_integrated_system_info_v1_12
uint32_t reserved[63];
};
-
-#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
-
struct edp_info_table
{
uint16_t edp_backlight_pwm_hz;
@@ -1367,7 +1364,6 @@ struct atom_integrated_system_info_v2_1
uint32_t reserved7[32];
};
-#endif
// system_config
enum atom_system_vbiosmisc_def{
--
2.25.4
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[PATCH 1/4] drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINE
No need for a separate config option at this point.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/Kconfig | 8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 --
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 --
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 --
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 --
5 files changed, 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index 93cdcd1ee9ff..cf87133f88e6 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -17,14 +17,6 @@ config DRM_AMD_DC_DCN
help
Raven, Navi and Renoir family support for display engine
-config DRM_AMD_DC_GREEN_SARDINE
- bool "Green Sardine support"
- default y
- depends on DRM_AMD_DC_DCN
-help
-Choose this option if you want to have
-Green Sardine support for display engine
-
config DRM_AMD_DC_DCN3_0
bool "DCN 3.0 family"
depends on DRM_AMD_DC && X86
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8a90063ac08a..2aa810d3554b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -100,10 +100,8 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
#endif
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
#define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
-#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
@@ -985,10 +983,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
case CHIP_RAVEN:
case CHIP_RENOIR:
init_data.flags.gpu_vm_support = true;
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
init_data.flags.disable_dmcu = true;
-#endif
break;
default:
break;
@@ -1289,10 +1285,8 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
case CHIP_RENOIR:
dmub_asic = DMUB_ASIC_DCN21;
fw_name_dmub = FIRMWARE_RENOIR_DMUB;
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
-#endif
break;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
case CHIP_SIENNA_CICHLID:
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index b361dc6c3489..19d97ed6beb8 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -170,12 +170,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx,
struct pp_smu_funcs *p
break;
}
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
break;
}
-#endif
if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
break;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index ab105f26b511..419c0df08602 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -126,10 +126,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id
asic_id)
dc_version = DCN_VERSION_1_01;
if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_2_1;
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_2_1;
-#endif
break;
#endif
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index b4c3838322af..2bf60ac2974f 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -209,12 +209,10 @@ enum {
#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev)((eChipRev >=
NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN))
#endif
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
#define GREEN_SARDINE_A0 0xA1
#ifndef ASICREV_IS_GREEN_SARDINE
#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >=
Re: [PATCH] drm/amdgpu: move amdgpu_num_kcq handling to a helper
Am 2020-10-16 um 10:20 a.m. schrieb Alex Deucher:
> Add a helper so we can set per asic default values. Also,
> the module parameter is currently clamped to 8, but clamp it
> per asic just in case some asics have different limits in the
> future. Enable the option on gfx6,7 as well for consistency.
>
> Signed-off-by: Alex Deucher
Reviewed-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 11 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
> 8 files changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index abddcd9dab3d..fb9e61f861e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1374,13 +1374,6 @@ static int amdgpu_device_check_arguments(struct
> amdgpu_device *adev)
>
> amdgpu_gmc_tmz_set(adev);
>
> - if (amdgpu_num_kcq == -1) {
> - amdgpu_num_kcq = 8;
> - } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
> - amdgpu_num_kcq = 8;
> - dev_warn(adev->dev, "set kernel compute queue number to 8 due
> to invalid parameter provided by user\n");
> - }
> -
> amdgpu_gmc_noretry_set(adev);
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 8c9bacfdbc30..e584f48f3b54 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -804,3 +804,14 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev,
> uint32_t reg, uint32_t v)
> failed_kiq_write:
> dev_err(adev->dev, "failed to write reg:%x\n", reg);
> }
> +
> +int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
> +{
> + if (amdgpu_num_kcq == -1) {
> + return 8;
> + } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
> + dev_warn(adev->dev, "set kernel compute queue number to 8 due
> to invalid parameter provided by user\n");
> + return 8;
> + }
> + return amdgpu_num_kcq;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 190753930b11..786eb4aa7314 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -393,4 +393,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device
> *adev,
> struct amdgpu_iv_entry *entry);
> uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
> void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
> +int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 669c352c27af..b4df472194af 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7406,7 +7406,8 @@ static int gfx_v10_0_early_init(void *handle)
> break;
> }
>
> - adev->gfx.num_compute_rings = amdgpu_num_kcq;
> + adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
> + AMDGPU_MAX_COMPUTE_RINGS);
>
> gfx_v10_0_set_kiq_pm4_funcs(adev);
> gfx_v10_0_set_ring_funcs(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 79c52c7a02e3..671c46ebeced 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -3064,7 +3064,8 @@ static int gfx_v6_0_early_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
> - adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
> + adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
> + GFX6_NUM_COMPUTE_RINGS);
> adev->gfx.funcs = _v6_0_gfx_funcs;
> adev->gfx.rlc.funcs = _v6_0_rlc_funcs;
> gfx_v6_0_set_ring_funcs(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 04eaf3a8fddb..cb07bc21dcbe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -4238,7 +4238,8 @@ static int gfx_v7_0_early_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
> - adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
> + adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
Re: [PATCH 1/1] drm/amdgpu: fix compute queue priority if num_kcq is less than 4
Am 2020-10-16 um 11:34 a.m. schrieb Nirmoy Das:
> Compute queues are configurable with module param, num_kcq.
> amdgpu_gfx_is_high_priority_compute_queue was setting 1st 4 queues to
> high priority queue leaving a null drm scheduler in
> adev->gpu_sched[hw_ip]["normal_prio"].sched if num_kcq < 5
>
> Fixes: 33abcb1f5a1719b1c (drm/amdgpu: set compute queue priority at mqd_init)
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 8c9bacfdbc30..56d384656c45 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -193,10 +193,10 @@ static bool amdgpu_gfx_is_multipipe_capable(struct
> amdgpu_device *adev)
> }
>
> bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> -int queue)
> +int pipe)
> {
> - /* Policy: make queue 0 of each pipe as high priority compute queue */
> - return (queue == 0);
> + /* Policy: even pipe num = normal priority, odd pipe num = high
> priority */
> + return ((pipe % 2) != 0);
I think this will break on systems where multipipe_policy is false. If
all KCQs are on the same pipe, you'll end up without any high-priority
queues.
Regards,
Felix
>
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 190753930b11..b167ebb6385d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -374,7 +374,7 @@ void amdgpu_queue_mask_bit_to_mec_queue(struct
> amdgpu_device *adev, int bit,
> bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
>int pipe, int queue);
> bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> -int queue);
> +int pipe);
> int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
> int pipe, int queue);
> void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index e42542e564f7..e39737680017 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4465,7 +4465,7 @@ static int gfx_v10_0_compute_ring_init(struct
> amdgpu_device *adev, int ring_id,
> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> + ring->pipe;
> - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
> + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe) ?
> AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> r = amdgpu_ring_init(adev, ring, 1024,
> @@ -6498,7 +6498,7 @@ static void gfx_v10_0_compute_mqd_set_priority(struct
> amdgpu_ring *ring, struct
> struct amdgpu_device *adev = ring->adev;
>
> if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> - if (amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring->queue)) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring->pipe)) {
> mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> mqd->cp_hqd_queue_priority =
> AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index d5843e8a6e17..ada54a96c676 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1915,7 +1915,7 @@ static int gfx_v8_0_compute_ring_init(struct
> amdgpu_device *adev, int ring_id,
> + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> + ring->pipe;
>
> - hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
> + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe) ?
> AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> r = amdgpu_ring_init(adev, ring, 1024,
> @@ -4433,7 +4433,7 @@ static void gfx_v8_0_mqd_set_priority(struct
> amdgpu_ring *ring, struct vi_mqd *m
> struct amdgpu_device *adev = ring->adev;
>
> if (ring->funcs->type ==
[PATCH 1/1] drm/amdgpu: fix compute queue priority if num_kcq is less than 4
Compute queues are configurable with module param, num_kcq.
amdgpu_gfx_is_high_priority_compute_queue was setting 1st 4 queues to
high priority queue leaving a null drm scheduler in
adev->gpu_sched[hw_ip]["normal_prio"].sched if num_kcq < 5
Fixes: 33abcb1f5a1719b1c (drm/amdgpu: set compute queue priority at mqd_init)
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 8c9bacfdbc30..56d384656c45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -193,10 +193,10 @@ static bool amdgpu_gfx_is_multipipe_capable(struct
amdgpu_device *adev)
}
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
- int queue)
+ int pipe)
{
- /* Policy: make queue 0 of each pipe as high priority compute queue */
- return (queue == 0);
+ /* Policy: even pipe num = normal priority, odd pipe num = high
priority */
+ return ((pipe % 2) != 0);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 190753930b11..b167ebb6385d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -374,7 +374,7 @@ void amdgpu_queue_mask_bit_to_mec_queue(struct
amdgpu_device *adev, int bit,
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
int pipe, int queue);
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
- int queue);
+ int pipe);
int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
int pipe, int queue);
void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index e42542e564f7..e39737680017 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4465,7 +4465,7 @@ static int gfx_v10_0_compute_ring_init(struct
amdgpu_device *adev, int ring_id,
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
+ ring->pipe;
- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe) ?
AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
/* type-2 packets are deprecated on MEC, use type-3 instead */
r = amdgpu_ring_init(adev, ring, 1024,
@@ -6498,7 +6498,7 @@ static void gfx_v10_0_compute_mqd_set_priority(struct
amdgpu_ring *ring, struct
struct amdgpu_device *adev = ring->adev;
if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
- if (amdgpu_gfx_is_high_priority_compute_queue(adev,
ring->queue)) {
+ if (amdgpu_gfx_is_high_priority_compute_queue(adev,
ring->pipe)) {
mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
mqd->cp_hqd_queue_priority =
AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index d5843e8a6e17..ada54a96c676 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1915,7 +1915,7 @@ static int gfx_v8_0_compute_ring_init(struct
amdgpu_device *adev, int ring_id,
+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
+ ring->pipe;
- hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
+ hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe) ?
AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
/* type-2 packets are deprecated on MEC, use type-3 instead */
r = amdgpu_ring_init(adev, ring, 1024,
@@ -4433,7 +4433,7 @@ static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring
*ring, struct vi_mqd *m
struct amdgpu_device *adev = ring->adev;
if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
- if (amdgpu_gfx_is_high_priority_compute_queue(adev,
ring->queue)) {
+ if (amdgpu_gfx_is_high_priority_compute_queue(adev,
ring->pipe)) {
mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
mqd->cp_hqd_queue_priority =
Re: [PATCH] drm/amd/psp: Fix sysfs: cannot create duplicate filename
[AMD Public Use] Reviewed-by: Alex Deucher Want to add a Fixes: tag? From: amd-gfx on behalf of Andrey Grodzovsky Sent: Friday, October 16, 2020 10:52 AM To: amd-gfx@lists.freedesktop.org Cc: Grodzovsky, Andrey ; Zhang, Jack (Jian) Subject: [PATCH] drm/amd/psp: Fix sysfs: cannot create duplicate filename psp sysfs not cleaned up on driver unload for sienna_cichlid Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 803b3ab..675b14a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -210,7 +210,8 @@ static int psp_sw_fini(void *handle) adev->psp.ta_fw = NULL; } - if (adev->asic_type == CHIP_NAVI10) + if (adev->asic_type == CHIP_NAVI10 || + adev->asic_type == CHIP_SIENNA_CICHLID) psp_sysfs_fini(adev); return 0; -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Calexander.deucher%40amd.com%7C4b9827047c1f4f1a535908d871e3193a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637384567500193749%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=klYQ7ZzcmrPbXDeEARNHMTjJMUyZWPSn7N3KTQZ2%2FMc%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: move amdgpu_num_kcq handling to a helper
Acked-by: Nirmoy Das
On 10/16/20 4:20 PM, Alex Deucher wrote:
Add a helper so we can set per asic default values. Also,
the module parameter is currently clamped to 8, but clamp it
per asic just in case some asics have different limits in the
future. Enable the option on gfx6,7 as well for consistency.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 11 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
8 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abddcd9dab3d..fb9e61f861e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1374,13 +1374,6 @@ static int amdgpu_device_check_arguments(struct
amdgpu_device *adev)
amdgpu_gmc_tmz_set(adev);
- if (amdgpu_num_kcq == -1) {
- amdgpu_num_kcq = 8;
- } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
- amdgpu_num_kcq = 8;
- dev_warn(adev->dev, "set kernel compute queue number to 8 due to
invalid parameter provided by user\n");
- }
-
amdgpu_gmc_noretry_set(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 8c9bacfdbc30..e584f48f3b54 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -804,3 +804,14 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v)
failed_kiq_write:
dev_err(adev->dev, "failed to write reg:%x\n", reg);
}
+
+int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
+{
+ if (amdgpu_num_kcq == -1) {
+ return 8;
+ } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
+ dev_warn(adev->dev, "set kernel compute queue number to 8 due to
invalid parameter provided by user\n");
+ return 8;
+ }
+ return amdgpu_num_kcq;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 190753930b11..786eb4aa7314 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -393,4 +393,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry);
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
+int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 669c352c27af..b4df472194af 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7406,7 +7406,8 @@ static int gfx_v10_0_early_init(void *handle)
break;
}
- adev->gfx.num_compute_rings = amdgpu_num_kcq;
+ adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+ AMDGPU_MAX_COMPUTE_RINGS);
gfx_v10_0_set_kiq_pm4_funcs(adev);
gfx_v10_0_set_ring_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 79c52c7a02e3..671c46ebeced 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3064,7 +3064,8 @@ static int gfx_v6_0_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
- adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
+ adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+ GFX6_NUM_COMPUTE_RINGS);
adev->gfx.funcs = _v6_0_gfx_funcs;
adev->gfx.rlc.funcs = _v6_0_rlc_funcs;
gfx_v6_0_set_ring_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 04eaf3a8fddb..cb07bc21dcbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4238,7 +4238,8 @@ static int gfx_v7_0_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
- adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
+ adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+ AMDGPU_MAX_COMPUTE_RINGS);
adev->gfx.funcs = _v7_0_gfx_funcs;
adev->gfx.rlc.funcs = _v7_0_rlc_funcs;
[PATCH] drm/amd/psp: Fix sysfs: cannot create duplicate filename
psp sysfs not cleaned up on driver unload for sienna_cichlid Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 803b3ab..675b14a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -210,7 +210,8 @@ static int psp_sw_fini(void *handle) adev->psp.ta_fw = NULL; } - if (adev->asic_type == CHIP_NAVI10) + if (adev->asic_type == CHIP_NAVI10 || + adev->asic_type == CHIP_SIENNA_CICHLID) psp_sysfs_fini(adev); return 0; -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven
On 10/16/20 3:56 PM, Alex Deucher wrote:
On Wed, Oct 14, 2020 at 9:53 AM Nirmoy Das wrote:
Because of firmware bug, Raven asics can't handle jobs
scheduled to multiple compute queues. So enable only one
compute queue till we have a firmware fix.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 8c9bacfdbc30..ca2ac985b300 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -195,6 +195,10 @@ static bool amdgpu_gfx_is_multipipe_capable(struct
amdgpu_device *adev)
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
int queue)
{
+ /* We only enable one compute queue for Raven */
+ if (adev->asic_type == CHIP_RAVEN)
+ return false;
+
/* Policy: make queue 0 of each pipe as high priority compute queue */
return (queue == 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 0d8e203b10ef..f3fc9ad8bc20 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4633,7 +4633,16 @@ static int gfx_v9_0_early_init(void *handle)
adev->gfx.num_gfx_rings = 0;
else
adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
- adev->gfx.num_compute_rings = amdgpu_num_kcq;
+
+ /* raven firmware currently can not load balance jobs
+* among multiple compute queues. Enable only one
+* compute queue till we have a firmware fix.
+*/
+ if (adev->asic_type == CHIP_RAVEN)
+ adev->gfx.num_compute_rings = 1;
+ else
+ adev->gfx.num_compute_rings = amdgpu_num_kcq;
+
I would suggest something like this instead so we can override easily
for testing:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abddcd9dab3d..a2954b41e59d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1376,6 +1376,12 @@ static int amdgpu_device_check_arguments(struct
amdgpu_device *adev)
if (amdgpu_num_kcq == -1) {
amdgpu_num_kcq = 8;
+ /* raven firmware currently can not load balance jobs
+* among multiple compute queues. Enable only one
+* compute queue till we have a firmware fix.
+*/
+ if (adev->asic_type == CHIP_RAVEN)
+ amdgpu_num_kcq = 1;
} else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
amdgpu_num_kcq = 8;
dev_warn(adev->dev, "set kernel compute queue number
to 8 due to invalid parameter provided by user\n");
Thanks, this looks much better,
I will update.
Nirmoy
Alex
gfx_v9_0_set_kiq_pm4_funcs(adev);
gfx_v9_0_set_ring_funcs(adev);
gfx_v9_0_set_irq_funcs(adev);
--
2.28.0
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[PATCH] drm/amdgpu: move amdgpu_num_kcq handling to a helper
Add a helper so we can set per asic default values. Also,
the module parameter is currently clamped to 8, but clamp it
per asic just in case some asics have different limits in the
future. Enable the option on gfx6,7 as well for consistency.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 11 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
8 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abddcd9dab3d..fb9e61f861e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1374,13 +1374,6 @@ static int amdgpu_device_check_arguments(struct
amdgpu_device *adev)
amdgpu_gmc_tmz_set(adev);
- if (amdgpu_num_kcq == -1) {
- amdgpu_num_kcq = 8;
- } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
- amdgpu_num_kcq = 8;
- dev_warn(adev->dev, "set kernel compute queue number to 8 due
to invalid parameter provided by user\n");
- }
-
amdgpu_gmc_noretry_set(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 8c9bacfdbc30..e584f48f3b54 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -804,3 +804,14 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v)
failed_kiq_write:
dev_err(adev->dev, "failed to write reg:%x\n", reg);
}
+
+int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
+{
+ if (amdgpu_num_kcq == -1) {
+ return 8;
+ } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
+ dev_warn(adev->dev, "set kernel compute queue number to 8 due
to invalid parameter provided by user\n");
+ return 8;
+ }
+ return amdgpu_num_kcq;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 190753930b11..786eb4aa7314 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -393,4 +393,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry);
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
+int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 669c352c27af..b4df472194af 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7406,7 +7406,8 @@ static int gfx_v10_0_early_init(void *handle)
break;
}
- adev->gfx.num_compute_rings = amdgpu_num_kcq;
+ adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+ AMDGPU_MAX_COMPUTE_RINGS);
gfx_v10_0_set_kiq_pm4_funcs(adev);
gfx_v10_0_set_ring_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 79c52c7a02e3..671c46ebeced 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3064,7 +3064,8 @@ static int gfx_v6_0_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
- adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
+ adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+ GFX6_NUM_COMPUTE_RINGS);
adev->gfx.funcs = _v6_0_gfx_funcs;
adev->gfx.rlc.funcs = _v6_0_rlc_funcs;
gfx_v6_0_set_ring_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 04eaf3a8fddb..cb07bc21dcbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4238,7 +4238,8 @@ static int gfx_v7_0_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
- adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
+ adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+ AMDGPU_MAX_COMPUTE_RINGS);
adev->gfx.funcs = _v7_0_gfx_funcs;
adev->gfx.rlc.funcs = _v7_0_rlc_funcs;
gfx_v7_0_set_ring_funcs(adev);
diff --git
Re: [PATCH 2/2] drm/amdgpu: enable only one compute queue for raven
On Wed, Oct 14, 2020 at 9:53 AM Nirmoy Das wrote:
>
> Because of firmware bug, Raven asics can't handle jobs
> scheduled to multiple compute queues. So enable only one
> compute queue till we have a firmware fix.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 ++-
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 8c9bacfdbc30..ca2ac985b300 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -195,6 +195,10 @@ static bool amdgpu_gfx_is_multipipe_capable(struct
> amdgpu_device *adev)
> bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
>int queue)
> {
> + /* We only enable one compute queue for Raven */
> + if (adev->asic_type == CHIP_RAVEN)
> + return false;
> +
> /* Policy: make queue 0 of each pipe as high priority compute queue */
> return (queue == 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 0d8e203b10ef..f3fc9ad8bc20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4633,7 +4633,16 @@ static int gfx_v9_0_early_init(void *handle)
> adev->gfx.num_gfx_rings = 0;
> else
> adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
> - adev->gfx.num_compute_rings = amdgpu_num_kcq;
> +
> + /* raven firmware currently can not load balance jobs
> +* among multiple compute queues. Enable only one
> +* compute queue till we have a firmware fix.
> +*/
> + if (adev->asic_type == CHIP_RAVEN)
> + adev->gfx.num_compute_rings = 1;
> + else
> + adev->gfx.num_compute_rings = amdgpu_num_kcq;
> +
I would suggest something like this instead so we can override easily
for testing:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abddcd9dab3d..a2954b41e59d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1376,6 +1376,12 @@ static int amdgpu_device_check_arguments(struct
amdgpu_device *adev)
if (amdgpu_num_kcq == -1) {
amdgpu_num_kcq = 8;
+ /* raven firmware currently can not load balance jobs
+* among multiple compute queues. Enable only one
+* compute queue till we have a firmware fix.
+*/
+ if (adev->asic_type == CHIP_RAVEN)
+ amdgpu_num_kcq = 1;
} else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
amdgpu_num_kcq = 8;
dev_warn(adev->dev, "set kernel compute queue number
to 8 due to invalid parameter provided by user\n");
Alex
> gfx_v9_0_set_kiq_pm4_funcs(adev);
> gfx_v9_0_set_ring_funcs(adev);
> gfx_v9_0_set_irq_funcs(adev);
> --
> 2.28.0
>
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RE: [PATCH] drm/amd/pm: drop navy_flounder hardcode of using soft pptable
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Jiansong Chen
Sent: Friday, October 16, 2020 20:51
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Zhang, Hawking ;
Chen, Jiansong (Simon)
Subject: [PATCH] drm/amd/pm: drop navy_flounder hardcode of using soft pptable
Drop navy_flounder hardcode of using soft pptable, so that it can use pptable
from vbios when available.
Signed-off-by: Jiansong Chen
Change-Id: I33436b023d03ae77a1b92da5a8062e8466e80110
---
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index c2a6eb93d93c..fff1d2522463 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -337,7 +337,6 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
if ((version_major == 2 &&
smu->smu_table.boot_values.pp_table_id > 0) ||
- adev->asic_type == CHIP_NAVY_FLOUNDER ||
adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
dev_info(adev->dev, "use driver provided pptable %d\n",
smu->smu_table.boot_values.pp_table_id);
switch (version_minor) {
--
2.25.1
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[PATCH] drm/amd/pm: drop navy_flounder hardcode of using soft pptable
Drop navy_flounder hardcode of using soft pptable, so that it
can use pptable from vbios when available.
Signed-off-by: Jiansong Chen
Change-Id: I33436b023d03ae77a1b92da5a8062e8466e80110
---
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index c2a6eb93d93c..fff1d2522463 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -337,7 +337,6 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
if ((version_major == 2 &&
smu->smu_table.boot_values.pp_table_id > 0) ||
- adev->asic_type == CHIP_NAVY_FLOUNDER ||
adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
dev_info(adev->dev, "use driver provided pptable %d\n",
smu->smu_table.boot_values.pp_table_id);
switch (version_minor) {
--
2.25.1
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Re: [PATCH v4 10/10] drm/fb_helper: Support framebuffers in I/O memory
On Fri, Oct 16, 2020 at 02:19:42PM +0200, Thomas Zimmermann wrote: > Hi > > On Fri, 16 Oct 2020 14:03:47 +0200 Sam Ravnborg wrote: > > > Hi Thomas. > > > > On Thu, Oct 15, 2020 at 02:38:06PM +0200, Thomas Zimmermann wrote: > > > At least sparc64 requires I/O-specific access to framebuffers. This > > > patch updates the fbdev console accordingly. > > > > > > For drivers with direct access to the framebuffer memory, the callback > > > functions in struct fb_ops test for the type of memory and call the rsp > > > fb_sys_ of fb_cfb_ functions. > > > > > > For drivers that employ a shadow buffer, fbdev's blit function retrieves > > > the framebuffer address as struct dma_buf_map, and uses dma_buf_map > > > interfaces to access the buffer. > > > > > > The bochs driver on sparc64 uses a workaround to flag the framebuffer as > > > I/O memory and avoid a HW exception. With the introduction of struct > > > dma_buf_map, this is not required any longer. The patch removes the rsp > > > code from both, bochs and fbdev. > > > > > > v4: > > > * move dma_buf_map changes into separate patch (Daniel) > > > * TODO list: comment on fbdev updates (Daniel) > > > > > > Signed-off-by: Thomas Zimmermann > > > > The original workaround fixed it so we could run qemu with the > > -nographic option. > > > > So I went ahead and tried to run quemu version: > > v5.0.0-1970-g0b100c8e72-dirty. > > And with the BOCHS driver built-in. > > > > With the following command line: > > qemu-system-sparc64 -m 512 -kernel vmlinux -append console=ttyS0 -nographic > > > > Behaviour was the same before and after applying this patch. > > (panic due to VFS: Unable to mount root fs on unknown-block(0,0)) > > So I consider it fixed for real now and not just a workaround. > > > > I also tested with: > > qemu-system-sparc64 -m 512 -kernel vmlinux -append console=ttyS0 -serial > > stdio > > > > and it worked in both cases too. > > FTR, you booted a kernel and got graphics output. The error is simply that > there was no disk to mount? The short version "Yes". The longer version: With "qemu-system-sparc64 -m 512 -kernel vmlinux -append console=ttyS0 -serial stdio" I got graphical output - one penguin. With "qemu-system-sparc64 -m 512 -kernel vmlinux -append console=ttyS0 -nographic" I got no graphical output, as implied by the -nographic option. But the boot continued - where it would panic before when we accessed IO memory as system memory. In both cases I got an error because I had not specified any rootfs, so qemu failed to mount any rootfs. So expected. Sam > > Best regards > Thomas > > > > > All the comments above so future-me have an easier time finding how to > > reproduce. > > > > Tested-by: Sam Ravnborg > > > > Sam > > > > > --- > > > Documentation/gpu/todo.rst| 19 ++- > > > drivers/gpu/drm/bochs/bochs_kms.c | 1 - > > > drivers/gpu/drm/drm_fb_helper.c | 217 -- > > > include/drm/drm_mode_config.h | 12 -- > > > 4 files changed, 220 insertions(+), 29 deletions(-) > > > > > > diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst > > > index 7e6fc3c04add..638b7f704339 100644 > > > --- a/Documentation/gpu/todo.rst > > > +++ b/Documentation/gpu/todo.rst > > > @@ -197,13 +197,28 @@ Convert drivers to use drm_fbdev_generic_setup() > > > > > > > > > Most drivers can use drm_fbdev_generic_setup(). Driver have to implement > > > -atomic modesetting and GEM vmap support. Current generic fbdev emulation > > > -expects the framebuffer in system memory (or system-like memory). > > > +atomic modesetting and GEM vmap support. Historically, generic fbdev > > > emulation +expected the framebuffer in system memory or system-like > > > memory. By employing +struct dma_buf_map, drivers with frambuffers in I/O > > > memory can be supported +as well. > > > > > > Contact: Maintainer of the driver you plan to convert > > > > > > Level: Intermediate > > > > > > +Reimplement functions in drm_fbdev_fb_ops without fbdev > > > +--- > > > + > > > +A number of callback functions in drm_fbdev_fb_ops could benefit from > > > +being rewritten without dependencies on the fbdev module. Some of the > > > +helpers could further benefit from using struct dma_buf_map instead of > > > +raw pointers. > > > + > > > +Contact: Thomas Zimmermann , Daniel Vetter > > > + > > > +Level: Advanced > > > + > > > + > > > drm_framebuffer_funcs and drm_mode_config_funcs.fb_create cleanup > > > - > > > > > > diff --git a/drivers/gpu/drm/bochs/bochs_kms.c > > > b/drivers/gpu/drm/bochs/bochs_kms.c index 13d0d04c4457..853081d186d5 > > > 100644 --- a/drivers/gpu/drm/bochs/bochs_kms.c > > > +++ b/drivers/gpu/drm/bochs/bochs_kms.c > > > @@ -151,7 +151,6 @@ int bochs_kms_init(struct bochs_device *bochs) > > >
Re: [PATCH] drm/amdgpu: don't map BO in reserved region
Am 16.10.20 um 14:33 schrieb Madhav Chauhan:
2MB area is reserved at top inside VM.
Suggested-by: Christian König
Signed-off-by: Madhav Chauhan
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 5047989fe941..5b50860eece4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -596,6 +596,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct ww_acquire_ctx ticket;
struct list_head list, duplicates;
uint64_t va_flags;
+ uint64_t vm_size;
int r = 0;
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
@@ -616,6 +617,15 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
args->va_address &= AMDGPU_GMC_HOLE_MASK;
+ vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
+ vm_size -= AMDGPU_VA_RESERVED_SIZE;
+ if (args->va_address + args->map_size > vm_size) {
+ dev_dbg(>pdev->dev,
+ "va_address 0x%llx is in top reserved area 0x%llx\n",
+ args->va_address + args->map_size, vm_size);
+ return -EINVAL;
+ }
+
if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
dev_dbg(>pdev->dev, "invalid flags combination 0x%08X\n",
args->flags);
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[PATCH] drm/amdgpu: don't map BO in reserved region
2MB area is reserved at top inside VM.
Suggested-by: Christian König
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 5047989fe941..5b50860eece4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -596,6 +596,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct ww_acquire_ctx ticket;
struct list_head list, duplicates;
uint64_t va_flags;
+ uint64_t vm_size;
int r = 0;
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
@@ -616,6 +617,15 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
args->va_address &= AMDGPU_GMC_HOLE_MASK;
+ vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
+ vm_size -= AMDGPU_VA_RESERVED_SIZE;
+ if (args->va_address + args->map_size > vm_size) {
+ dev_dbg(>pdev->dev,
+ "va_address 0x%llx is in top reserved area 0x%llx\n",
+ args->va_address + args->map_size, vm_size);
+ return -EINVAL;
+ }
+
if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
dev_dbg(>pdev->dev, "invalid flags combination 0x%08X\n",
args->flags);
--
2.17.1
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Re: [PATCH v4 10/10] drm/fb_helper: Support framebuffers in I/O memory
Hi On Fri, 16 Oct 2020 14:03:47 +0200 Sam Ravnborg wrote: > Hi Thomas. > > On Thu, Oct 15, 2020 at 02:38:06PM +0200, Thomas Zimmermann wrote: > > At least sparc64 requires I/O-specific access to framebuffers. This > > patch updates the fbdev console accordingly. > > > > For drivers with direct access to the framebuffer memory, the callback > > functions in struct fb_ops test for the type of memory and call the rsp > > fb_sys_ of fb_cfb_ functions. > > > > For drivers that employ a shadow buffer, fbdev's blit function retrieves > > the framebuffer address as struct dma_buf_map, and uses dma_buf_map > > interfaces to access the buffer. > > > > The bochs driver on sparc64 uses a workaround to flag the framebuffer as > > I/O memory and avoid a HW exception. With the introduction of struct > > dma_buf_map, this is not required any longer. The patch removes the rsp > > code from both, bochs and fbdev. > > > > v4: > > * move dma_buf_map changes into separate patch (Daniel) > > * TODO list: comment on fbdev updates (Daniel) > > > > Signed-off-by: Thomas Zimmermann > > The original workaround fixed it so we could run qemu with the > -nographic option. > > So I went ahead and tried to run quemu version: > v5.0.0-1970-g0b100c8e72-dirty. > And with the BOCHS driver built-in. > > With the following command line: > qemu-system-sparc64 -m 512 -kernel vmlinux -append console=ttyS0 -nographic > > Behaviour was the same before and after applying this patch. > (panic due to VFS: Unable to mount root fs on unknown-block(0,0)) > So I consider it fixed for real now and not just a workaround. > > I also tested with: > qemu-system-sparc64 -m 512 -kernel vmlinux -append console=ttyS0 -serial > stdio > > and it worked in both cases too. FTR, you booted a kernel and got graphics output. The error is simply that there was no disk to mount? Best regards Thomas > > All the comments above so future-me have an easier time finding how to > reproduce. > > Tested-by: Sam Ravnborg > > Sam > > > --- > > Documentation/gpu/todo.rst| 19 ++- > > drivers/gpu/drm/bochs/bochs_kms.c | 1 - > > drivers/gpu/drm/drm_fb_helper.c | 217 -- > > include/drm/drm_mode_config.h | 12 -- > > 4 files changed, 220 insertions(+), 29 deletions(-) > > > > diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst > > index 7e6fc3c04add..638b7f704339 100644 > > --- a/Documentation/gpu/todo.rst > > +++ b/Documentation/gpu/todo.rst > > @@ -197,13 +197,28 @@ Convert drivers to use drm_fbdev_generic_setup() > > > > > > Most drivers can use drm_fbdev_generic_setup(). Driver have to implement > > -atomic modesetting and GEM vmap support. Current generic fbdev emulation > > -expects the framebuffer in system memory (or system-like memory). > > +atomic modesetting and GEM vmap support. Historically, generic fbdev > > emulation +expected the framebuffer in system memory or system-like > > memory. By employing +struct dma_buf_map, drivers with frambuffers in I/O > > memory can be supported +as well. > > > > Contact: Maintainer of the driver you plan to convert > > > > Level: Intermediate > > > > +Reimplement functions in drm_fbdev_fb_ops without fbdev > > +--- > > + > > +A number of callback functions in drm_fbdev_fb_ops could benefit from > > +being rewritten without dependencies on the fbdev module. Some of the > > +helpers could further benefit from using struct dma_buf_map instead of > > +raw pointers. > > + > > +Contact: Thomas Zimmermann , Daniel Vetter > > + > > +Level: Advanced > > + > > + > > drm_framebuffer_funcs and drm_mode_config_funcs.fb_create cleanup > > - > > > > diff --git a/drivers/gpu/drm/bochs/bochs_kms.c > > b/drivers/gpu/drm/bochs/bochs_kms.c index 13d0d04c4457..853081d186d5 > > 100644 --- a/drivers/gpu/drm/bochs/bochs_kms.c > > +++ b/drivers/gpu/drm/bochs/bochs_kms.c > > @@ -151,7 +151,6 @@ int bochs_kms_init(struct bochs_device *bochs) > > bochs->dev->mode_config.preferred_depth = 24; > > bochs->dev->mode_config.prefer_shadow = 0; > > bochs->dev->mode_config.prefer_shadow_fbdev = 1; > > - bochs->dev->mode_config.fbdev_use_iomem = true; > > bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = > > true; > > bochs->dev->mode_config.funcs = _mode_funcs; > > diff --git a/drivers/gpu/drm/drm_fb_helper.c > > b/drivers/gpu/drm/drm_fb_helper.c index 6212cd7cde1d..462b0c130ebb 100644 > > --- a/drivers/gpu/drm/drm_fb_helper.c > > +++ b/drivers/gpu/drm/drm_fb_helper.c > > @@ -372,24 +372,22 @@ static void drm_fb_helper_resume_worker(struct > > work_struct *work) } > > > > static void drm_fb_helper_dirty_blit_real(struct drm_fb_helper > > *fb_helper, > > - struct drm_clip_rect *clip) > > +
Re: [PATCH v4 10/10] drm/fb_helper: Support framebuffers in I/O memory
Hi Thomas.
On Thu, Oct 15, 2020 at 02:38:06PM +0200, Thomas Zimmermann wrote:
> At least sparc64 requires I/O-specific access to framebuffers. This
> patch updates the fbdev console accordingly.
>
> For drivers with direct access to the framebuffer memory, the callback
> functions in struct fb_ops test for the type of memory and call the rsp
> fb_sys_ of fb_cfb_ functions.
>
> For drivers that employ a shadow buffer, fbdev's blit function retrieves
> the framebuffer address as struct dma_buf_map, and uses dma_buf_map
> interfaces to access the buffer.
>
> The bochs driver on sparc64 uses a workaround to flag the framebuffer as
> I/O memory and avoid a HW exception. With the introduction of struct
> dma_buf_map, this is not required any longer. The patch removes the rsp
> code from both, bochs and fbdev.
>
> v4:
> * move dma_buf_map changes into separate patch (Daniel)
> * TODO list: comment on fbdev updates (Daniel)
>
> Signed-off-by: Thomas Zimmermann
The original workaround fixed it so we could run qemu with the
-nographic option.
So I went ahead and tried to run quemu version:
v5.0.0-1970-g0b100c8e72-dirty.
And with the BOCHS driver built-in.
With the following command line:
qemu-system-sparc64 -m 512 -kernel vmlinux -append console=ttyS0 -nographic
Behaviour was the same before and after applying this patch.
(panic due to VFS: Unable to mount root fs on unknown-block(0,0))
So I consider it fixed for real now and not just a workaround.
I also tested with:
qemu-system-sparc64 -m 512 -kernel vmlinux -append console=ttyS0 -serial stdio
and it worked in both cases too.
All the comments above so future-me have an easier time finding how to
reproduce.
Tested-by: Sam Ravnborg
Sam
> ---
> Documentation/gpu/todo.rst| 19 ++-
> drivers/gpu/drm/bochs/bochs_kms.c | 1 -
> drivers/gpu/drm/drm_fb_helper.c | 217 --
> include/drm/drm_mode_config.h | 12 --
> 4 files changed, 220 insertions(+), 29 deletions(-)
>
> diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
> index 7e6fc3c04add..638b7f704339 100644
> --- a/Documentation/gpu/todo.rst
> +++ b/Documentation/gpu/todo.rst
> @@ -197,13 +197,28 @@ Convert drivers to use drm_fbdev_generic_setup()
>
>
> Most drivers can use drm_fbdev_generic_setup(). Driver have to implement
> -atomic modesetting and GEM vmap support. Current generic fbdev emulation
> -expects the framebuffer in system memory (or system-like memory).
> +atomic modesetting and GEM vmap support. Historically, generic fbdev
> emulation
> +expected the framebuffer in system memory or system-like memory. By employing
> +struct dma_buf_map, drivers with frambuffers in I/O memory can be supported
> +as well.
>
> Contact: Maintainer of the driver you plan to convert
>
> Level: Intermediate
>
> +Reimplement functions in drm_fbdev_fb_ops without fbdev
> +---
> +
> +A number of callback functions in drm_fbdev_fb_ops could benefit from
> +being rewritten without dependencies on the fbdev module. Some of the
> +helpers could further benefit from using struct dma_buf_map instead of
> +raw pointers.
> +
> +Contact: Thomas Zimmermann , Daniel Vetter
> +
> +Level: Advanced
> +
> +
> drm_framebuffer_funcs and drm_mode_config_funcs.fb_create cleanup
> -
>
> diff --git a/drivers/gpu/drm/bochs/bochs_kms.c
> b/drivers/gpu/drm/bochs/bochs_kms.c
> index 13d0d04c4457..853081d186d5 100644
> --- a/drivers/gpu/drm/bochs/bochs_kms.c
> +++ b/drivers/gpu/drm/bochs/bochs_kms.c
> @@ -151,7 +151,6 @@ int bochs_kms_init(struct bochs_device *bochs)
> bochs->dev->mode_config.preferred_depth = 24;
> bochs->dev->mode_config.prefer_shadow = 0;
> bochs->dev->mode_config.prefer_shadow_fbdev = 1;
> - bochs->dev->mode_config.fbdev_use_iomem = true;
> bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = true;
>
> bochs->dev->mode_config.funcs = _mode_funcs;
> diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
> index 6212cd7cde1d..462b0c130ebb 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -372,24 +372,22 @@ static void drm_fb_helper_resume_worker(struct
> work_struct *work)
> }
>
> static void drm_fb_helper_dirty_blit_real(struct drm_fb_helper *fb_helper,
> - struct drm_clip_rect *clip)
> + struct drm_clip_rect *clip,
> + struct dma_buf_map *dst)
> {
> struct drm_framebuffer *fb = fb_helper->fb;
> unsigned int cpp = fb->format->cpp[0];
> size_t offset = clip->y1 * fb->pitches[0] + clip->x1 * cpp;
> void *src = fb_helper->fbdev->screen_buffer + offset;
> - void *dst = fb_helper->buffer->map.vaddr + offset;
Re: [PATCH v4 10/10] drm/fb_helper: Support framebuffers in I/O memory
Hi
On Fri, 16 Oct 2020 12:58:54 +0200 Sam Ravnborg wrote:
> Hi Thomas.
>
> On Thu, Oct 15, 2020 at 02:38:06PM +0200, Thomas Zimmermann wrote:
> > At least sparc64 requires I/O-specific access to framebuffers. This
> > patch updates the fbdev console accordingly.
> >
> > For drivers with direct access to the framebuffer memory, the callback
> > functions in struct fb_ops test for the type of memory and call the rsp
> > fb_sys_ of fb_cfb_ functions.
> >
> > For drivers that employ a shadow buffer, fbdev's blit function retrieves
> > the framebuffer address as struct dma_buf_map, and uses dma_buf_map
> > interfaces to access the buffer.
> >
> > The bochs driver on sparc64 uses a workaround to flag the framebuffer as
> > I/O memory and avoid a HW exception. With the introduction of struct
> > dma_buf_map, this is not required any longer. The patch removes the rsp
> > code from both, bochs and fbdev.
> >
> > v4:
> > * move dma_buf_map changes into separate patch (Daniel)
> > * TODO list: comment on fbdev updates (Daniel)
>
> I have been offline for a while so have not followed all the threads on
> this. So may comments below may well be addressed but I failed to see
> it.
>
> If the point about fb_sync is already addressed/considered then:
> Reviewed-by: Sam Ravnborg
It has not been brought up yet. See below.
>
>
> > Signed-off-by: Thomas Zimmermann
> > ---
> > Documentation/gpu/todo.rst| 19 ++-
> > drivers/gpu/drm/bochs/bochs_kms.c | 1 -
> > drivers/gpu/drm/drm_fb_helper.c | 217 --
> > include/drm/drm_mode_config.h | 12 --
> > 4 files changed, 220 insertions(+), 29 deletions(-)
> >
> > diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
> > index 7e6fc3c04add..638b7f704339 100644
> > --- a/Documentation/gpu/todo.rst
> > +++ b/Documentation/gpu/todo.rst
> > @@ -197,13 +197,28 @@ Convert drivers to use drm_fbdev_generic_setup()
> >
> >
> > Most drivers can use drm_fbdev_generic_setup(). Driver have to implement
> > -atomic modesetting and GEM vmap support. Current generic fbdev emulation
> > -expects the framebuffer in system memory (or system-like memory).
> > +atomic modesetting and GEM vmap support. Historically, generic fbdev
> > emulation +expected the framebuffer in system memory or system-like
> > memory. By employing +struct dma_buf_map, drivers with frambuffers in I/O
> > memory can be supported +as well.
> >
> > Contact: Maintainer of the driver you plan to convert
> >
> > Level: Intermediate
> >
> > +Reimplement functions in drm_fbdev_fb_ops without fbdev
> > +---
> > +
> > +A number of callback functions in drm_fbdev_fb_ops could benefit from
> > +being rewritten without dependencies on the fbdev module. Some of the
> > +helpers could further benefit from using struct dma_buf_map instead of
> > +raw pointers.
> > +
> > +Contact: Thomas Zimmermann , Daniel Vetter
> > +
> > +Level: Advanced
> > +
> > +
> > drm_framebuffer_funcs and drm_mode_config_funcs.fb_create cleanup
> > -
> >
> > diff --git a/drivers/gpu/drm/bochs/bochs_kms.c
> > b/drivers/gpu/drm/bochs/bochs_kms.c index 13d0d04c4457..853081d186d5
> > 100644 --- a/drivers/gpu/drm/bochs/bochs_kms.c
> > +++ b/drivers/gpu/drm/bochs/bochs_kms.c
> > @@ -151,7 +151,6 @@ int bochs_kms_init(struct bochs_device *bochs)
> > bochs->dev->mode_config.preferred_depth = 24;
> > bochs->dev->mode_config.prefer_shadow = 0;
> > bochs->dev->mode_config.prefer_shadow_fbdev = 1;
> > - bochs->dev->mode_config.fbdev_use_iomem = true;
> > bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order =
> > true;
> > bochs->dev->mode_config.funcs = _mode_funcs;
> Good to see this workaround gone again!
>
> > diff --git a/drivers/gpu/drm/drm_fb_helper.c
> > b/drivers/gpu/drm/drm_fb_helper.c index 6212cd7cde1d..462b0c130ebb 100644
> > --- a/drivers/gpu/drm/drm_fb_helper.c
> > +++ b/drivers/gpu/drm/drm_fb_helper.c
> > @@ -372,24 +372,22 @@ static void drm_fb_helper_resume_worker(struct
> > work_struct *work) }
> >
> > static void drm_fb_helper_dirty_blit_real(struct drm_fb_helper
> > *fb_helper,
> > - struct drm_clip_rect *clip)
> > + struct drm_clip_rect *clip,
> > + struct dma_buf_map *dst)
> > {
> > struct drm_framebuffer *fb = fb_helper->fb;
> > unsigned int cpp = fb->format->cpp[0];
> > size_t offset = clip->y1 * fb->pitches[0] + clip->x1 * cpp;
> > void *src = fb_helper->fbdev->screen_buffer + offset;
> > - void *dst = fb_helper->buffer->map.vaddr + offset;
> > size_t len = (clip->x2 - clip->x1) * cpp;
> > unsigned int y;
> >
> > - for (y = clip->y1; y < clip->y2; y++) {
> > - if (!fb_helper->dev->mode_config.fbdev_use_iomem)
> > -
Re: [PATCH v4 09/10] dma-buf-map: Add memcpy and pointer-increment interfaces
Hi Thomas.
On Thu, Oct 15, 2020 at 02:38:05PM +0200, Thomas Zimmermann wrote:
> To do framebuffer updates, one needs memcpy from system memory and a
> pointer-increment function. Add both interfaces with documentation.
>
> Signed-off-by: Thomas Zimmermann
> ---
> include/linux/dma-buf-map.h | 72 +++--
> 1 file changed, 62 insertions(+), 10 deletions(-)
>
> diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
> index 2e8bbecb5091..6ca0f304dda2 100644
> --- a/include/linux/dma-buf-map.h
> +++ b/include/linux/dma-buf-map.h
> @@ -32,6 +32,14 @@
> * accessing the buffer. Use the returned instance and the helper functions
> * to access the buffer's memory in the correct way.
> *
> + * The type :c:type:`struct dma_buf_map ` and its helpers are
> + * actually independent from the dma-buf infrastructure. When sharing buffers
> + * among devices, drivers have to know the location of the memory to access
> + * the buffers in a safe way. :c:type:`struct dma_buf_map `
> + * solves this problem for dma-buf and its users. If other drivers or
> + * sub-systems require similar functionality, the type could be generalized
> + * and moved to a more prominent header file.
> + *
> * Open-coding access to :c:type:`struct dma_buf_map ` is
> * considered bad style. Rather then accessing its fields directly, use one
> * of the provided helper functions, or implement your own. For example,
> @@ -51,6 +59,14 @@
> *
> * dma_buf_map_set_vaddr_iomem( 0xdeadbeaf);
> *
> + * Instances of struct dma_buf_map do not have to be cleaned up, but
> + * can be cleared to NULL with dma_buf_map_clear(). Cleared mappings
> + * always refer to system memory.
> + *
> + * .. code-block:: c
> + *
> + * dma_buf_map_clear();
> + *
> * Test if a mapping is valid with either dma_buf_map_is_set() or
> * dma_buf_map_is_null().
> *
> @@ -73,17 +89,19 @@
> * if (dma_buf_map_is_equal(_map, _map))
> * // always false
> *
> - * Instances of struct dma_buf_map do not have to be cleaned up, but
> - * can be cleared to NULL with dma_buf_map_clear(). Cleared mappings
> - * always refer to system memory.
> + * A set up instance of struct dma_buf_map can be used to access or
> manipulate
> + * the buffer memory. Depending on the location of the memory, the provided
> + * helpers will pick the correct operations. Data can be copied into the
> memory
> + * with dma_buf_map_memcpy_to(). The address can be manipulated with
> + * dma_buf_map_incr().
> *
> - * The type :c:type:`struct dma_buf_map ` and its helpers are
> - * actually independent from the dma-buf infrastructure. When sharing buffers
> - * among devices, drivers have to know the location of the memory to access
> - * the buffers in a safe way. :c:type:`struct dma_buf_map `
> - * solves this problem for dma-buf and its users. If other drivers or
> - * sub-systems require similar functionality, the type could be generalized
> - * and moved to a more prominent header file.
> + * .. code-block:: c
> + *
> + * const void *src = ...; // source buffer
> + * size_t len = ...; // length of src
> + *
> + * dma_buf_map_memcpy_to(, src, len);
> + * dma_buf_map_incr(, len); // go to first byte after the memcpy
> */
>
> /**
> @@ -210,4 +228,38 @@ static inline void dma_buf_map_clear(struct dma_buf_map
> *map)
> }
> }
>
> +/**
> + * dma_buf_map_memcpy_to - Memcpy into dma-buf mapping
> + * @dst: The dma-buf mapping structure
> + * @src: The source buffer
> + * @len: The number of byte in src
> + *
> + * Copies data into a dma-buf mapping. The source buffer is in system
> + * memory. Depending on the buffer's location, the helper picks the correct
> + * method of accessing the memory.
> + */
> +static inline void dma_buf_map_memcpy_to(struct dma_buf_map *dst, const void
> *src, size_t len)
> +{
> + if (dst->is_iomem)
> + memcpy_toio(dst->vaddr_iomem, src, len);
> + else
> + memcpy(dst->vaddr, src, len);
sparc64 needs "#include " to build as is does not get
this via io.h
Sam
> +}
> +
> +/**
> + * dma_buf_map_incr - Increments the address stored in a dma-buf mapping
> + * @map: The dma-buf mapping structure
> + * @incr:The number of bytes to increment
> + *
> + * Increments the address stored in a dma-buf mapping. Depending on the
> + * buffer's location, the correct value will be updated.
> + */
> +static inline void dma_buf_map_incr(struct dma_buf_map *map, size_t incr)
> +{
> + if (map->is_iomem)
> + map->vaddr_iomem += incr;
> + else
> + map->vaddr += incr;
> +}
> +
> #endif /* __DMA_BUF_MAP_H__ */
> --
> 2.28.0
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Re: [PATCH] drm/amdgpu: add a list in VM for BOs in the done state
Am 16.10.20 um 12:55 schrieb Mihir Patel:
From: Mihir Bhogilal Patel
Add a new list in VM for done state i.e. BOs which are
invalidated and updated in PTEs.
Signed-off-by: Mihir Bhogilal Patel
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 19 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 122814c3ff5f..c08b76f4042a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -300,7 +300,7 @@ static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base
*vm_bo)
static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
{
spin_lock(_bo->vm->invalidated_lock);
- list_del_init(_bo->vm_status);
+ list_move(_bo->vm_status, _bo->vm->done);
spin_unlock(_bo->vm->invalidated_lock);
}
@@ -2823,7 +2823,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
INIT_LIST_HEAD(>invalidated);
spin_lock_init(>invalidated_lock);
INIT_LIST_HEAD(>freed);
-
+ INIT_LIST_HEAD(>done);
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(>immediate, DRM_SCHED_PRIORITY_NORMAL,
@@ -3410,11 +3410,13 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm,
struct seq_file *m)
u64 total_relocated = 0;
u64 total_moved = 0;
u64 total_invalidated = 0;
+ u64 total_done = 0;
unsigned int total_idle_objs = 0;
unsigned int total_evicted_objs = 0;
unsigned int total_relocated_objs = 0;
unsigned int total_moved_objs = 0;
unsigned int total_invalidated_objs = 0;
+ unsigned int total_done_objs = 0;
unsigned int id = 0;
seq_puts(m, "\tIdle BOs:\n");
@@ -3460,8 +3462,17 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm,
struct seq_file *m)
continue;
total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo,
m);
}
- spin_unlock(>invalidated_lock);
total_invalidated_objs = id;
+ id = 0;
+
+ seq_puts(m, "\tDone BOs:\n");
+ list_for_each_entry_safe(bo_va, tmp, >done, base.vm_status) {
+ if (!bo_va->base.bo)
+ continue;
+ total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
+ }
+ spin_unlock(>invalidated_lock);
+ total_done_objs = id;
seq_printf(m, "\tTotal idle size:%12lld\tobjs:\t%d\n", total_idle,
total_idle_objs);
@@ -3473,5 +3484,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm,
struct seq_file *m)
total_moved_objs);
seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n",
total_invalidated,
total_invalidated_objs);
+ seq_printf(m, "\tTotal done size:%12lld\tobjs:\t%d\n",
total_done,
+ total_done_objs);
}
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 74cc14179c41..ffea3b89b9da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -274,6 +274,9 @@ struct amdgpu_vm {
/* BO mappings freed, but not yet updated in the PT */
struct list_headfreed;
+ /* BOs which are invalidated, has been updated in the PTs */
+ struct list_headdone;
+
/* contains the page directory */
struct amdgpu_vm_pt root;
struct dma_fence*last_update;
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Re: [PATCH v4 10/10] drm/fb_helper: Support framebuffers in I/O memory
Hi Thomas.
On Thu, Oct 15, 2020 at 02:38:06PM +0200, Thomas Zimmermann wrote:
> At least sparc64 requires I/O-specific access to framebuffers. This
> patch updates the fbdev console accordingly.
>
> For drivers with direct access to the framebuffer memory, the callback
> functions in struct fb_ops test for the type of memory and call the rsp
> fb_sys_ of fb_cfb_ functions.
>
> For drivers that employ a shadow buffer, fbdev's blit function retrieves
> the framebuffer address as struct dma_buf_map, and uses dma_buf_map
> interfaces to access the buffer.
>
> The bochs driver on sparc64 uses a workaround to flag the framebuffer as
> I/O memory and avoid a HW exception. With the introduction of struct
> dma_buf_map, this is not required any longer. The patch removes the rsp
> code from both, bochs and fbdev.
>
> v4:
> * move dma_buf_map changes into separate patch (Daniel)
> * TODO list: comment on fbdev updates (Daniel)
I have been offline for a while so have not followed all the threads on
this. So may comments below may well be addressed but I failed to see
it.
If the point about fb_sync is already addressed/considered then:
Reviewed-by: Sam Ravnborg
> Signed-off-by: Thomas Zimmermann
> ---
> Documentation/gpu/todo.rst| 19 ++-
> drivers/gpu/drm/bochs/bochs_kms.c | 1 -
> drivers/gpu/drm/drm_fb_helper.c | 217 --
> include/drm/drm_mode_config.h | 12 --
> 4 files changed, 220 insertions(+), 29 deletions(-)
>
> diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
> index 7e6fc3c04add..638b7f704339 100644
> --- a/Documentation/gpu/todo.rst
> +++ b/Documentation/gpu/todo.rst
> @@ -197,13 +197,28 @@ Convert drivers to use drm_fbdev_generic_setup()
>
>
> Most drivers can use drm_fbdev_generic_setup(). Driver have to implement
> -atomic modesetting and GEM vmap support. Current generic fbdev emulation
> -expects the framebuffer in system memory (or system-like memory).
> +atomic modesetting and GEM vmap support. Historically, generic fbdev
> emulation
> +expected the framebuffer in system memory or system-like memory. By employing
> +struct dma_buf_map, drivers with frambuffers in I/O memory can be supported
> +as well.
>
> Contact: Maintainer of the driver you plan to convert
>
> Level: Intermediate
>
> +Reimplement functions in drm_fbdev_fb_ops without fbdev
> +---
> +
> +A number of callback functions in drm_fbdev_fb_ops could benefit from
> +being rewritten without dependencies on the fbdev module. Some of the
> +helpers could further benefit from using struct dma_buf_map instead of
> +raw pointers.
> +
> +Contact: Thomas Zimmermann , Daniel Vetter
> +
> +Level: Advanced
> +
> +
> drm_framebuffer_funcs and drm_mode_config_funcs.fb_create cleanup
> -
>
> diff --git a/drivers/gpu/drm/bochs/bochs_kms.c
> b/drivers/gpu/drm/bochs/bochs_kms.c
> index 13d0d04c4457..853081d186d5 100644
> --- a/drivers/gpu/drm/bochs/bochs_kms.c
> +++ b/drivers/gpu/drm/bochs/bochs_kms.c
> @@ -151,7 +151,6 @@ int bochs_kms_init(struct bochs_device *bochs)
> bochs->dev->mode_config.preferred_depth = 24;
> bochs->dev->mode_config.prefer_shadow = 0;
> bochs->dev->mode_config.prefer_shadow_fbdev = 1;
> - bochs->dev->mode_config.fbdev_use_iomem = true;
> bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = true;
>
> bochs->dev->mode_config.funcs = _mode_funcs;
Good to see this workaround gone again!
> diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
> index 6212cd7cde1d..462b0c130ebb 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -372,24 +372,22 @@ static void drm_fb_helper_resume_worker(struct
> work_struct *work)
> }
>
> static void drm_fb_helper_dirty_blit_real(struct drm_fb_helper *fb_helper,
> - struct drm_clip_rect *clip)
> + struct drm_clip_rect *clip,
> + struct dma_buf_map *dst)
> {
> struct drm_framebuffer *fb = fb_helper->fb;
> unsigned int cpp = fb->format->cpp[0];
> size_t offset = clip->y1 * fb->pitches[0] + clip->x1 * cpp;
> void *src = fb_helper->fbdev->screen_buffer + offset;
> - void *dst = fb_helper->buffer->map.vaddr + offset;
> size_t len = (clip->x2 - clip->x1) * cpp;
> unsigned int y;
>
> - for (y = clip->y1; y < clip->y2; y++) {
> - if (!fb_helper->dev->mode_config.fbdev_use_iomem)
> - memcpy(dst, src, len);
> - else
> - memcpy_toio((void __iomem *)dst, src, len);
> + dma_buf_map_incr(dst, offset); /* go to first pixel within clip rect */
>
> + for (y = clip->y1; y < clip->y2; y++) {
> +
[PATCH] drm/amdgpu: add a list in VM for BOs in the done state
From: Mihir Bhogilal Patel
Add a new list in VM for done state i.e. BOs which are
invalidated and updated in PTEs.
Signed-off-by: Mihir Bhogilal Patel
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 19 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 122814c3ff5f..c08b76f4042a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -300,7 +300,7 @@ static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base
*vm_bo)
static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
{
spin_lock(_bo->vm->invalidated_lock);
- list_del_init(_bo->vm_status);
+ list_move(_bo->vm_status, _bo->vm->done);
spin_unlock(_bo->vm->invalidated_lock);
}
@@ -2823,7 +2823,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
INIT_LIST_HEAD(>invalidated);
spin_lock_init(>invalidated_lock);
INIT_LIST_HEAD(>freed);
-
+ INIT_LIST_HEAD(>done);
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(>immediate, DRM_SCHED_PRIORITY_NORMAL,
@@ -3410,11 +3410,13 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm,
struct seq_file *m)
u64 total_relocated = 0;
u64 total_moved = 0;
u64 total_invalidated = 0;
+ u64 total_done = 0;
unsigned int total_idle_objs = 0;
unsigned int total_evicted_objs = 0;
unsigned int total_relocated_objs = 0;
unsigned int total_moved_objs = 0;
unsigned int total_invalidated_objs = 0;
+ unsigned int total_done_objs = 0;
unsigned int id = 0;
seq_puts(m, "\tIdle BOs:\n");
@@ -3460,8 +3462,17 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm,
struct seq_file *m)
continue;
total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo,
m);
}
- spin_unlock(>invalidated_lock);
total_invalidated_objs = id;
+ id = 0;
+
+ seq_puts(m, "\tDone BOs:\n");
+ list_for_each_entry_safe(bo_va, tmp, >done, base.vm_status) {
+ if (!bo_va->base.bo)
+ continue;
+ total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
+ }
+ spin_unlock(>invalidated_lock);
+ total_done_objs = id;
seq_printf(m, "\tTotal idle size:%12lld\tobjs:\t%d\n",
total_idle,
total_idle_objs);
@@ -3473,5 +3484,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm,
struct seq_file *m)
total_moved_objs);
seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n",
total_invalidated,
total_invalidated_objs);
+ seq_printf(m, "\tTotal done size:%12lld\tobjs:\t%d\n",
total_done,
+ total_done_objs);
}
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 74cc14179c41..ffea3b89b9da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -274,6 +274,9 @@ struct amdgpu_vm {
/* BO mappings freed, but not yet updated in the PT */
struct list_headfreed;
+ /* BOs which are invalidated, has been updated in the PTs */
+ struct list_headdone;
+
/* contains the page directory */
struct amdgpu_vm_pt root;
struct dma_fence*last_update;
--
2.17.1
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Re: [PATCH v4 09/10] dma-buf-map: Add memcpy and pointer-increment interfaces
Hi Sam
On Fri, 16 Oct 2020 12:08:54 +0200 Sam Ravnborg wrote:
> Hi Thomas.
>
> On Thu, Oct 15, 2020 at 02:38:05PM +0200, Thomas Zimmermann wrote:
> > To do framebuffer updates, one needs memcpy from system memory and a
> > pointer-increment function. Add both interfaces with documentation.
> >
> > Signed-off-by: Thomas Zimmermann
>
> Looks good.
> Reviewed-by: Sam Ravnborg
Thanks. If you have the time, may I ask you to test this patchset on the
bochs/sparc64 system that failed with the original code?
Best regards
Thomas
>
> > ---
> > include/linux/dma-buf-map.h | 72 +++--
> > 1 file changed, 62 insertions(+), 10 deletions(-)
> >
> > diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
> > index 2e8bbecb5091..6ca0f304dda2 100644
> > --- a/include/linux/dma-buf-map.h
> > +++ b/include/linux/dma-buf-map.h
> > @@ -32,6 +32,14 @@
> > * accessing the buffer. Use the returned instance and the helper
> > functions
> > * to access the buffer's memory in the correct way.
> > *
> > + * The type :c:type:`struct dma_buf_map ` and its helpers
> > are
> > + * actually independent from the dma-buf infrastructure. When sharing
> > buffers
> > + * among devices, drivers have to know the location of the memory to
> > access
> > + * the buffers in a safe way. :c:type:`struct dma_buf_map `
> > + * solves this problem for dma-buf and its users. If other drivers or
> > + * sub-systems require similar functionality, the type could be
> > generalized
> > + * and moved to a more prominent header file.
> > + *
> > * Open-coding access to :c:type:`struct dma_buf_map ` is
> > * considered bad style. Rather then accessing its fields directly, use
> > one
> > * of the provided helper functions, or implement your own. For example,
> > @@ -51,6 +59,14 @@
> > *
> > * dma_buf_map_set_vaddr_iomem( 0xdeadbeaf);
> > *
> > + * Instances of struct dma_buf_map do not have to be cleaned up, but
> > + * can be cleared to NULL with dma_buf_map_clear(). Cleared mappings
> > + * always refer to system memory.
> > + *
> > + * .. code-block:: c
> > + *
> > + * dma_buf_map_clear();
> > + *
> > * Test if a mapping is valid with either dma_buf_map_is_set() or
> > * dma_buf_map_is_null().
> > *
> > @@ -73,17 +89,19 @@
> > * if (dma_buf_map_is_equal(_map, _map))
> > * // always false
> > *
> > - * Instances of struct dma_buf_map do not have to be cleaned up, but
> > - * can be cleared to NULL with dma_buf_map_clear(). Cleared mappings
> > - * always refer to system memory.
> > + * A set up instance of struct dma_buf_map can be used to access or
> > manipulate
> > + * the buffer memory. Depending on the location of the memory, the
> > provided
> > + * helpers will pick the correct operations. Data can be copied into the
> > memory
> > + * with dma_buf_map_memcpy_to(). The address can be manipulated with
> > + * dma_buf_map_incr().
> > *
> > - * The type :c:type:`struct dma_buf_map ` and its helpers
> > are
> > - * actually independent from the dma-buf infrastructure. When sharing
> > buffers
> > - * among devices, drivers have to know the location of the memory to
> > access
> > - * the buffers in a safe way. :c:type:`struct dma_buf_map `
> > - * solves this problem for dma-buf and its users. If other drivers or
> > - * sub-systems require similar functionality, the type could be
> > generalized
> > - * and moved to a more prominent header file.
> > + * .. code-block:: c
> > + *
> > + * const void *src = ...; // source buffer
> > + * size_t len = ...; // length of src
> > + *
> > + * dma_buf_map_memcpy_to(, src, len);
> > + * dma_buf_map_incr(, len); // go to first byte after the
> > memcpy */
> >
> > /**
> > @@ -210,4 +228,38 @@ static inline void dma_buf_map_clear(struct
> > dma_buf_map *map) }
> > }
> >
> > +/**
> > + * dma_buf_map_memcpy_to - Memcpy into dma-buf mapping
> > + * @dst: The dma-buf mapping structure
> > + * @src: The source buffer
> > + * @len: The number of byte in src
> > + *
> > + * Copies data into a dma-buf mapping. The source buffer is in system
> > + * memory. Depending on the buffer's location, the helper picks the
> > correct
> > + * method of accessing the memory.
> > + */
> > +static inline void dma_buf_map_memcpy_to(struct dma_buf_map *dst, const
> > void *src, size_t len) +{
> > + if (dst->is_iomem)
> > + memcpy_toio(dst->vaddr_iomem, src, len);
> > + else
> > + memcpy(dst->vaddr, src, len);
> > +}
> > +
> > +/**
> > + * dma_buf_map_incr - Increments the address stored in a dma-buf mapping
> > + * @map: The dma-buf mapping structure
> > + * @incr: The number of bytes to increment
> > + *
> > + * Increments the address stored in a dma-buf mapping. Depending on the
> > + * buffer's location, the correct value will be updated.
> > + */
> > +static inline void dma_buf_map_incr(struct dma_buf_map *map, size_t incr)
> > +{
> > + if (map->is_iomem)
> > + map->vaddr_iomem += incr;
>
Re: [PATCH v4 09/10] dma-buf-map: Add memcpy and pointer-increment interfaces
Hi Thomas.
On Thu, Oct 15, 2020 at 02:38:05PM +0200, Thomas Zimmermann wrote:
> To do framebuffer updates, one needs memcpy from system memory and a
> pointer-increment function. Add both interfaces with documentation.
>
> Signed-off-by: Thomas Zimmermann
Looks good.
Reviewed-by: Sam Ravnborg
> ---
> include/linux/dma-buf-map.h | 72 +++--
> 1 file changed, 62 insertions(+), 10 deletions(-)
>
> diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
> index 2e8bbecb5091..6ca0f304dda2 100644
> --- a/include/linux/dma-buf-map.h
> +++ b/include/linux/dma-buf-map.h
> @@ -32,6 +32,14 @@
> * accessing the buffer. Use the returned instance and the helper functions
> * to access the buffer's memory in the correct way.
> *
> + * The type :c:type:`struct dma_buf_map ` and its helpers are
> + * actually independent from the dma-buf infrastructure. When sharing buffers
> + * among devices, drivers have to know the location of the memory to access
> + * the buffers in a safe way. :c:type:`struct dma_buf_map `
> + * solves this problem for dma-buf and its users. If other drivers or
> + * sub-systems require similar functionality, the type could be generalized
> + * and moved to a more prominent header file.
> + *
> * Open-coding access to :c:type:`struct dma_buf_map ` is
> * considered bad style. Rather then accessing its fields directly, use one
> * of the provided helper functions, or implement your own. For example,
> @@ -51,6 +59,14 @@
> *
> * dma_buf_map_set_vaddr_iomem( 0xdeadbeaf);
> *
> + * Instances of struct dma_buf_map do not have to be cleaned up, but
> + * can be cleared to NULL with dma_buf_map_clear(). Cleared mappings
> + * always refer to system memory.
> + *
> + * .. code-block:: c
> + *
> + * dma_buf_map_clear();
> + *
> * Test if a mapping is valid with either dma_buf_map_is_set() or
> * dma_buf_map_is_null().
> *
> @@ -73,17 +89,19 @@
> * if (dma_buf_map_is_equal(_map, _map))
> * // always false
> *
> - * Instances of struct dma_buf_map do not have to be cleaned up, but
> - * can be cleared to NULL with dma_buf_map_clear(). Cleared mappings
> - * always refer to system memory.
> + * A set up instance of struct dma_buf_map can be used to access or
> manipulate
> + * the buffer memory. Depending on the location of the memory, the provided
> + * helpers will pick the correct operations. Data can be copied into the
> memory
> + * with dma_buf_map_memcpy_to(). The address can be manipulated with
> + * dma_buf_map_incr().
> *
> - * The type :c:type:`struct dma_buf_map ` and its helpers are
> - * actually independent from the dma-buf infrastructure. When sharing buffers
> - * among devices, drivers have to know the location of the memory to access
> - * the buffers in a safe way. :c:type:`struct dma_buf_map `
> - * solves this problem for dma-buf and its users. If other drivers or
> - * sub-systems require similar functionality, the type could be generalized
> - * and moved to a more prominent header file.
> + * .. code-block:: c
> + *
> + * const void *src = ...; // source buffer
> + * size_t len = ...; // length of src
> + *
> + * dma_buf_map_memcpy_to(, src, len);
> + * dma_buf_map_incr(, len); // go to first byte after the memcpy
> */
>
> /**
> @@ -210,4 +228,38 @@ static inline void dma_buf_map_clear(struct dma_buf_map
> *map)
> }
> }
>
> +/**
> + * dma_buf_map_memcpy_to - Memcpy into dma-buf mapping
> + * @dst: The dma-buf mapping structure
> + * @src: The source buffer
> + * @len: The number of byte in src
> + *
> + * Copies data into a dma-buf mapping. The source buffer is in system
> + * memory. Depending on the buffer's location, the helper picks the correct
> + * method of accessing the memory.
> + */
> +static inline void dma_buf_map_memcpy_to(struct dma_buf_map *dst, const void
> *src, size_t len)
> +{
> + if (dst->is_iomem)
> + memcpy_toio(dst->vaddr_iomem, src, len);
> + else
> + memcpy(dst->vaddr, src, len);
> +}
> +
> +/**
> + * dma_buf_map_incr - Increments the address stored in a dma-buf mapping
> + * @map: The dma-buf mapping structure
> + * @incr:The number of bytes to increment
> + *
> + * Increments the address stored in a dma-buf mapping. Depending on the
> + * buffer's location, the correct value will be updated.
> + */
> +static inline void dma_buf_map_incr(struct dma_buf_map *map, size_t incr)
> +{
> + if (map->is_iomem)
> + map->vaddr_iomem += incr;
> + else
> + map->vaddr += incr;
> +}
> +
> #endif /* __DMA_BUF_MAP_H__ */
> --
> 2.28.0
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RE: [PATCH] drm/amd/swsmu: correct wrong feature bit mapping
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
-Original Message-
From: Wang, Kevin(Yang)
Sent: Friday, October 16, 2020 5:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth
; Lazar, Lijo ; Wang, Kevin(Yang)
Subject: [PATCH] drm/amd/swsmu: correct wrong feature bit mapping
1.
when smc feature bit isn't mapped,
the feature state isn't showed on sysfs node of pp_features.
2.
add pp_features table title
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 27 --
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index c30d3338825f..92b2ea4c197b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -431,10 +431,9 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
char *buf)
{
uint32_t feature_mask[2] = { 0 };
- int32_t feature_index = 0;
+ int feature_index = 0;
uint32_t count = 0;
- uint32_t sort_feature[SMU_FEATURE_COUNT];
- uint64_t hw_feature_count = 0;
+ int8_t sort_feature[SMU_FEATURE_COUNT];
size_t size = 0;
int ret = 0, i;
@@ -447,23 +446,31 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context
*smu,
size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
feature_mask[1], feature_mask[0]);
+ memset(sort_feature, -1, sizeof(sort_feature));
+
for (i = 0; i < SMU_FEATURE_COUNT; i++) {
feature_index = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_FEATURE,
i);
if (feature_index < 0)
continue;
+
sort_feature[feature_index] = i;
- hw_feature_count++;
}
- for (i = 0; i < hw_feature_count; i++) {
+ size += sprintf(buf + size, "%-2s. %-20s %-3s : %-s\n",
+ "No", "Feature", "Bit", "State");
+
+ for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+ if (sort_feature[i] < 0)
+ continue;
+
size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
- count++,
- smu_get_feature_name(smu, sort_feature[i]),
- i,
- !!smu_cmn_feature_is_enabled(smu,
sort_feature[i]) ?
- "enabled" : "disabled");
+ count++,
+ smu_get_feature_name(smu, sort_feature[i]),
+ i,
+ !!smu_cmn_feature_is_enabled(smu,
sort_feature[i]) ?
+ "enabled" : "disabled");
}
return size;
--
2.17.1
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Re: [PATCH v4 05/10] drm/ttm: Add vmap/vunmap to TTM and TTM GEM helpers
Am 15.10.20 um 19:52 schrieb Thomas Zimmermann:
Hi
On Thu, 15 Oct 2020 18:49:09 +0200 Daniel Vetter wrote:
On Thu, Oct 15, 2020 at 04:08:13PM +0200, Christian König wrote:
Am 15.10.20 um 14:38 schrieb Thomas Zimmermann:
The new functions ttm_bo_{vmap,vunmap}() map and unmap a TTM BO in
kernel address space. The mapping's address is returned as struct
dma_buf_map. Each function is a simplified version of TTM's existing
kmap code. Both functions respect the memory's location ani/or
writecombine flags.
On top TTM's functions, GEM TTM helpers got drm_gem_ttm_{vmap,vunmap}(),
two helpers that convert a GEM object into the TTM BO and forward the
call to TTM's vmap/vunmap. These helpers can be dropped into the rsp
GEM object callbacks.
v4:
* drop ttm_kmap_obj_to_dma_buf() in favor of vmap helpers
(Daniel, Christian)
Bunch of minor comments below, but over all look very solid to me.
Yeah I think just duplicating the ttm bo map stuff for vmap is indeed the
cleanest. And then we can maybe push the combinatorial monster into
vmwgfx, which I think is the only user after this series. Or perhaps a
dedicated set of helpers to map an invidual page (again using the
dma_buf_map stuff).
From a quick look, I'd say it should be possible to have the same interface
for kmap/kunmap as for vmap/vunmap (i.e., parameters are bo and dma-buf-map).
All mapping state can be deduced from this. And struct ttm_bo_kmap_obj can be
killed off entirely.
Yes, that would be rather nice to have.
Thanks,
Christian.
Best regards
Thomas
I'll let Christian with the details, but at a high level this is
definitely
Acked-by: Daniel Vetter
Thanks a lot for doing all this.
-Daniel
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_gem_ttm_helper.c | 38 +++
drivers/gpu/drm/ttm/ttm_bo_util.c| 72
include/drm/drm_gem_ttm_helper.h | 6 +++
include/drm/ttm/ttm_bo_api.h | 28 +++
include/linux/dma-buf-map.h | 20
5 files changed, 164 insertions(+)
diff --git a/drivers/gpu/drm/drm_gem_ttm_helper.c
b/drivers/gpu/drm/drm_gem_ttm_helper.c index 0e4fb9ba43ad..db4c14d78a30
100644 --- a/drivers/gpu/drm/drm_gem_ttm_helper.c
+++ b/drivers/gpu/drm/drm_gem_ttm_helper.c
@@ -49,6 +49,44 @@ void drm_gem_ttm_print_info(struct drm_printer *p,
unsigned int indent, }
EXPORT_SYMBOL(drm_gem_ttm_print_info);
+/**
+ * drm_gem_ttm_vmap() - vmap _buffer_object
+ * @gem: GEM object.
+ * @map: [out] returns the dma-buf mapping.
+ *
+ * Maps a GEM object with ttm_bo_vmap(). This function can be used as
+ * _gem_object_funcs.vmap callback.
+ *
+ * Returns:
+ * 0 on success, or a negative errno code otherwise.
+ */
+int drm_gem_ttm_vmap(struct drm_gem_object *gem,
+struct dma_buf_map *map)
+{
+ struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem);
+
+ return ttm_bo_vmap(bo, map);
+
+}
+EXPORT_SYMBOL(drm_gem_ttm_vmap);
+
+/**
+ * drm_gem_ttm_vunmap() - vunmap _buffer_object
+ * @gem: GEM object.
+ * @map: dma-buf mapping.
+ *
+ * Unmaps a GEM object with ttm_bo_vunmap(). This function can be used
as
+ * _gem_object_funcs.vmap callback.
+ */
+void drm_gem_ttm_vunmap(struct drm_gem_object *gem,
+ struct dma_buf_map *map)
+{
+ struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem);
+
+ ttm_bo_vunmap(bo, map);
+}
+EXPORT_SYMBOL(drm_gem_ttm_vunmap);
+
/**
* drm_gem_ttm_mmap() - mmap _buffer_object
* @gem: GEM object.
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c index bdee4df1f3f2..80c42c774c7d
100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -526,6 +527,77 @@ void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map)
}
EXPORT_SYMBOL(ttm_bo_kunmap);
+int ttm_bo_vmap(struct ttm_buffer_object *bo, struct dma_buf_map *map)
+{
+ struct ttm_resource *mem = >mem;
+ int ret;
+
+ ret = ttm_mem_io_reserve(bo->bdev, mem);
+ if (ret)
+ return ret;
+
+ if (mem->bus.is_iomem) {
+ void __iomem *vaddr_iomem;
+ unsigned long size = bo->num_pages << PAGE_SHIFT;
Please use uint64_t here and make sure to cast bo->num_pages before
shifting.
We have an unit tests of allocating a 8GB BO and that should work on a
32bit machine as well :)
+
+ if (mem->bus.addr)
+ vaddr_iomem = (void *)(((u8 *)mem->bus.addr));
+ else if (mem->placement & TTM_PL_FLAG_WC)
I've just nuked the TTM_PL_FLAG_WC flag in drm-misc-next. There is a new
mem->bus.caching enum as replacement.
+ vaddr_iomem = ioremap_wc(mem->bus.offset,
size);
+ else
+ vaddr_iomem = ioremap(mem->bus.offset, size);
+
+ if (!vaddr_iomem)
+ return -ENOMEM;
[PATCH 3/4] drm/amdgpu: update amdgpu device suspend/resume sequence for s0i3 support
- Need skip the RLC/CP/GFX disable for let GFXOFF enter during suspend period.
- For s0i3 suspend only need suspend DCE and each IP interrupt.
- Before VBIOS POSTed check and atom HW INT need set the GPU power status change
to D0 in the resume period, otherwise the HW will be mess up and see the SDMA
hang.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a027a8f..b16a7f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2432,8 +2432,10 @@ static int amdgpu_device_ip_suspend_phase1(struct
amdgpu_device *adev)
{
int i, r;
- amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
- amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
+ if (!amdgpu_acpi_is_s0ix_supported()) {
+ amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
+ amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
+ }
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.valid)
@@ -3459,12 +3461,15 @@ int amdgpu_device_suspend(struct drm_device *dev, bool
fbcon)
amdgpu_fence_driver_suspend(adev);
- r = amdgpu_device_ip_suspend_phase2(adev);
-
+ if (!amdgpu_acpi_is_s0ix_supported())
+ r = amdgpu_device_ip_suspend_phase2(adev);
+ else
+ amdgpu_gfx_state_change_set(adev, GpuChangeState_D3Entry);
/* evict remaining vram memory
* This second call to evict vram is to evict the gart page table
* using the CPU.
*/
+
amdgpu_bo_evict_vram(adev);
return 0;
@@ -3492,6 +3497,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool
fbcon)
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
return 0;
+ if (amdgpu_acpi_is_s0ix_supported())
+ amdgpu_gfx_state_change_set(adev, GpuChangeState_D0Entry);
+
/* post card */
if (amdgpu_device_need_post(adev)) {
r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
--
2.7.4
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[PATCH 4/4] drm/amdgpu: fix reset support for s0i3 enablement
update amdgpu device suspend sequence for gpu reset during s0i3 enable.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b16a7f7..ed44971 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2432,7 +2432,7 @@ static int amdgpu_device_ip_suspend_phase1(struct
amdgpu_device *adev)
{
int i, r;
- if (!amdgpu_acpi_is_s0ix_supported()) {
+ if (!amdgpu_acpi_is_s0ix_supported() || adev->in_gpu_reset) {
amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
}
@@ -3461,7 +3461,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool
fbcon)
amdgpu_fence_driver_suspend(adev);
- if (!amdgpu_acpi_is_s0ix_supported())
+ if (!amdgpu_acpi_is_s0ix_supported() || adev->in_gpu_reset)
r = amdgpu_device_ip_suspend_phase2(adev);
else
amdgpu_gfx_state_change_set(adev, GpuChangeState_D3Entry);
--
2.7.4
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[PATCH 1/4] drm/amdgpu: add s0i3 capacity check for s0i3 routine
add amdgpu_acpi_is_s0ix_supported() to check the platform
whether support s0i3.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 14 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index cd91398..6bbeb04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1228,9 +1228,11 @@ int amdgpu_acpi_pcie_notify_device_ready(struct
amdgpu_device *adev);
void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
struct amdgpu_dm_backlight_caps *caps);
+bool amdgpu_acpi_is_s0ix_supported(void);
#else
static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
+static inline bool amdgpu_acpi_is_s0ix_supported(void) { return false; }
#endif
int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 956cbbd..88740e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#include
#include "amdgpu.h"
@@ -907,3 +908,16 @@ void amdgpu_acpi_fini(struct amdgpu_device *adev)
unregister_acpi_notifier(>acpi_nb);
kfree(adev->atif);
}
+
+/**
+ * amdgpu_acpi_is_s0ix_supported
+ *
+ * returns true if supported, false if not.
+ */
+bool amdgpu_acpi_is_s0ix_supported()
+{
+ if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)
+ return true;
+
+ return false;
+}
--
2.7.4
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[PATCH 2/4] drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry
The new amdgpu_gfx_state_change_set() funtion can support set GFX power
change status to D0/D3.
Signed-off-by: Prike Liang
Acked-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 7 +++
drivers/gpu/drm/amd/include/kgd_pp_interface.h| 1 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 20
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 9 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 3 ++-
7 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index d612033..e1d6c8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -789,3 +789,23 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v)
failed_kiq_write:
pr_err("failed to write reg:%x\n", reg);
}
+
+/* amdgpu_gfx_state_change_set - Handle gfx power state change set
+ * @adev: amdgpu_device pointer
+ * @state: gfx power state(1 -eGpuChangeState_D0Entry and 2
-eGpuChangeState_D3Entry)
+ *
+ */
+
+void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum
gfx_change_state state)
+{
+
+ mutex_lock(>pm.mutex);
+
+ if (adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->gfx_state_change_set)
+ ((adev)->powerplay.pp_funcs->gfx_state_change_set(
+ (adev)->powerplay.pp_handle, state));
+
+ mutex_unlock(>pm.mutex);
+
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index d43c116..73942b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -47,6 +47,12 @@ enum gfx_pipe_priority {
AMDGPU_GFX_PIPE_PRIO_MAX
};
+/* Argument for PPSMC_MSG_GpuChangeState */
+enum gfx_change_state {
+ GpuChangeState_D0Entry = 1,
+ GpuChangeState_D3Entry,
+};
+
#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
@@ -387,4 +393,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry);
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
+void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum
gfx_change_state state);
#endif
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index a7f92d0..e7b69dd 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -284,6 +284,7 @@ struct amd_pm_funcs {
int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input,
uint32_t size);
int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
int (*smu_i2c_bus_access)(void *handle, bool acquire);
+ int (*gfx_state_change_set)(void *handle, uint32_t state);
/* export to DC */
u32 (*get_sclk)(void *handle, bool low);
u32 (*get_mclk)(void *handle, bool low);
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 7e6dcdf..4f319be 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1321,6 +1321,25 @@ static int pp_set_powergating_by_smu(void *handle,
return ret;
}
+static int pp_gfx_state_change_set(void *handle, uint32_t state)
+{
+ struct pp_hwmgr *hwmgr = handle;
+
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
+
+ if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
+ pr_info_ratelimited("%s was not implemented.\n", __func__);
+ return -EINVAL;
+ }
+
+ mutex_lock(>smu_lock);
+ hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
+ mutex_unlock(>smu_lock);
+
+ return 0;
+}
+
static int pp_notify_smu_enable_pwe(void *handle)
{
struct pp_hwmgr *hwmgr = handle;
@@ -1625,6 +1644,7 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
.switch_power_profile = pp_dpm_switch_power_profile,
.set_clockgating_by_smu = pp_set_clockgating_by_smu,
.set_powergating_by_smu = pp_set_powergating_by_smu,
+ .gfx_state_change_set = pp_gfx_state_change_set,
.get_power_profile_mode = pp_get_power_profile_mode,
.set_power_profile_mode = pp_set_power_profile_mode,
.odn_edit_dpm_table = pp_odn_edit_dpm_table,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index c9cfe90..3f354da 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++
[PATCH] drm/amd/swsmu: correct wrong feature bit mapping
1.
when smc feature bit isn't mapped,
the feature state isn't showed on sysfs node of pp_features.
2.
add pp_features table title
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 27 --
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index c30d3338825f..92b2ea4c197b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -431,10 +431,9 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
char *buf)
{
uint32_t feature_mask[2] = { 0 };
- int32_t feature_index = 0;
+ int feature_index = 0;
uint32_t count = 0;
- uint32_t sort_feature[SMU_FEATURE_COUNT];
- uint64_t hw_feature_count = 0;
+ int8_t sort_feature[SMU_FEATURE_COUNT];
size_t size = 0;
int ret = 0, i;
@@ -447,23 +446,31 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context
*smu,
size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
feature_mask[1], feature_mask[0]);
+ memset(sort_feature, -1, sizeof(sort_feature));
+
for (i = 0; i < SMU_FEATURE_COUNT; i++) {
feature_index = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_FEATURE,
i);
if (feature_index < 0)
continue;
+
sort_feature[feature_index] = i;
- hw_feature_count++;
}
- for (i = 0; i < hw_feature_count; i++) {
+ size += sprintf(buf + size, "%-2s. %-20s %-3s : %-s\n",
+ "No", "Feature", "Bit", "State");
+
+ for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+ if (sort_feature[i] < 0)
+ continue;
+
size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
- count++,
- smu_get_feature_name(smu, sort_feature[i]),
- i,
- !!smu_cmn_feature_is_enabled(smu,
sort_feature[i]) ?
- "enabled" : "disabled");
+ count++,
+ smu_get_feature_name(smu, sort_feature[i]),
+ i,
+ !!smu_cmn_feature_is_enabled(smu,
sort_feature[i]) ?
+ "enabled" : "disabled");
}
return size;
--
2.17.1
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[PATCH] drm/amdgpu/sriov: reopen sienna_child smu ip block under sriov
open smu ip block meets with one-vf mode need Signed-off-by: Jane Jian --- drivers/gpu/drm/amd/amdgpu/nv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 4b1a4acb60d9..ef52d46b1458 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -572,7 +572,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) amdgpu_device_ip_block_add(adev, _v11_0_ip_block); if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && - is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) + is_support_sw_smu(adev)) amdgpu_device_ip_block_add(adev, _v11_0_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _virtual_ip_block); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
