Re: [PATCH 2/2] drm/amd/pm: fix compile warnings about variable used uninitialized
[AMD Official Use Only - Internal Distribution Only]
Series is:
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Tuesday, October 27, 2020 10:45 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
; kernel test robot
Subject: [PATCH 2/2] drm/amd/pm: fix compile warnings about variable used
uninitialized
Fix the compile warnings below:
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13:
>> warning: variable 'min' is used uninitialized whenever 'if' condition is
>> false [-Wsometimes-uninitialized]
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13:
>> warning: variable 'max' is used uninitialized whenever 'if' condition is
>> false [-Wsometimes-uninitialized]
Change-Id: Id2dece80162cd10f004abbf3b62cba0c84e988f2
Signed-off-by: Evan Quan
Reported-by: kernel test robot
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 49db61a89505..5937150e6b37 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1856,7 +1856,7 @@ static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct amdgpu_device *adev = hwmgr->adev;
- uint32_t asicrev1, evv_revision, max, min;
+ uint32_t asicrev1, evv_revision, max = 0, min = 0;
atomctrl_read_efuse(hwmgr, STRAP_EVV_REVISION_LSB,
STRAP_EVV_REVISION_MSB,
_revision);
@@ -1893,8 +1893,7 @@ static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)
max = 2500;
}
}
- } else if ((hwmgr->chip_id == CHIP_POLARIS11) ||
- (hwmgr->chip_id == CHIP_POLARIS12)) {
+ } else {
min = 1100;
max = 2100;
}
--
2.29.0
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[PATCH 1/2] drm/amd/pm: fix compile warning about missing prototype for function
Fix the warning below:
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.c:1234:29:
>> warning: no previous prototype for function 'asic_internal_ss_get_ss_table'
>> [-Wmissing-prototypes]
ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
^
drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.c:1234:1: note:
declare 'static' if the function is not intended to be used outside of this
translation unit
ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
^
static
1 warning generated.
Change-Id: Ib4f252d0103fc10f7a89b495d9e0bfe8439b6c65
Signed-off-by: Evan Quan
Reported-by: kernel test robot
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
index 401b3b516db0..c2fee6796bd9 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
@@ -1231,7 +1231,7 @@ uint32_t atomctrl_get_mpll_reference_clock(struct
pp_hwmgr *hwmgr)
/**
* Get the asic internal spread spectrum table
*/
-ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
+static ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
{
ATOM_ASIC_INTERNAL_SS_INFO *table = NULL;
u8 frev, crev;
--
2.29.0
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[PATCH 2/2] drm/amd/pm: fix compile warnings about variable used uninitialized
Fix the compile warnings below:
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13:
>> warning: variable 'min' is used uninitialized whenever 'if' condition is
>> false [-Wsometimes-uninitialized]
>> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13:
>> warning: variable 'max' is used uninitialized whenever 'if' condition is
>> false [-Wsometimes-uninitialized]
Change-Id: Id2dece80162cd10f004abbf3b62cba0c84e988f2
Signed-off-by: Evan Quan
Reported-by: kernel test robot
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 49db61a89505..5937150e6b37 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1856,7 +1856,7 @@ static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct amdgpu_device *adev = hwmgr->adev;
- uint32_t asicrev1, evv_revision, max, min;
+ uint32_t asicrev1, evv_revision, max = 0, min = 0;
atomctrl_read_efuse(hwmgr, STRAP_EVV_REVISION_LSB,
STRAP_EVV_REVISION_MSB,
_revision);
@@ -1893,8 +1893,7 @@ static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)
max = 2500;
}
}
- } else if ((hwmgr->chip_id == CHIP_POLARIS11) ||
- (hwmgr->chip_id == CHIP_POLARIS12)) {
+ } else {
min = 1100;
max = 2100;
}
--
2.29.0
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RE: [PATCH] drm/amdgpu/display: fix indentation in defer_delay_converter_wa()
[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Evan Quan -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Tuesday, October 27, 2020 1:51 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH] drm/amdgpu/display: fix indentation in defer_delay_converter_wa() Fixes this warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c: In function ‘defer_delay_converter_wa’: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c:285:2: warning: this ‘if’ clause does not guard... [-Wmisleading-indentation] 285 | if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 && | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c:291:3: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the ‘if’ 291 | if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 && | ^~ Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c index ef0f50db4907..54beda4d4e85 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c @@ -283,15 +283,15 @@ static uint32_t defer_delay_converter_wa( struct dc_link *link = ddc->link; if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 && -!memcmp(link->dpcd_caps.branch_dev_name, -DP_DVI_CONVERTER_ID_4, -sizeof(link->dpcd_caps.branch_dev_name))) +!memcmp(link->dpcd_caps.branch_dev_name, +DP_DVI_CONVERTER_ID_4, +sizeof(link->dpcd_caps.branch_dev_name))) return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ? defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY; -if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 && -!memcmp(link->dpcd_caps.branch_dev_name, -DP_DVI_CONVERTER_ID_5, -sizeof(link->dpcd_caps.branch_dev_name))) +if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 && +!memcmp(link->dpcd_caps.branch_dev_name, +DP_DVI_CONVERTER_ID_5, +sizeof(link->dpcd_caps.branch_dev_name))) return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY_1MS ? I2C_OVER_AUX_DEFER_WA_DELAY_1MS : defer_delay; -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Cevan.quan%40amd.com%7C4add589b1d8e4da5ca1508d879d7b126%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637393314640831230%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=IFfWUfCrpUalNb28hRkXU5M7zOMlrTuussAwIItuHKA%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
[AMD Official Use Only - Internal Distribution Only]
Hi Sandeep,
Did you run the tests on Hawaii?
And can you help to confirm which method is used for gpu reset? "BACO reset" or
" PCI CONFIG reset" (you can grep these keywords in dmesg)?
BR
Evan
-Original Message-
From: Sandeep
Sent: Tuesday, October 27, 2020 10:33 PM
To: Quan, Evan
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
Subject: Re: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
On Tue, 27 Oct 2020 at 17:04, Sandeep wrote:
>
>
>
> On Tue, 27 Oct, 2020, 17:01 Sandeep, wrote:
>>
>>
>> On Tue, 27 Oct, 2020, 08:10 Evan Quan, wrote:
>>>
>>> Which can be used for S4(hibernation) support.
>>>
>>> Change-Id: I6e4962c120a3baed14cea04ed1742ff11a273d34
>>> Signed-off-by: Evan Quan
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/cik.c | 4 +++-
>>> drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c | 7 ---
>>> 2 files changed, 7 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
>>> b/drivers/gpu/drm/amd/amdgpu/cik.c
>>> index 03ff8bd1fee8..5442df094102 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
>>> @@ -1336,11 +1336,13 @@ cik_asic_reset_method(struct amdgpu_device
>>> *adev)
>>>
>>> switch (adev->asic_type) {
>>> case CHIP_BONAIRE:
>>> - case CHIP_HAWAII:
>>> /* disable baco reset until it works */
>>> /* smu7_asic_get_baco_capability(adev, _reset); */
>>> baco_reset = false;
>>> break;
>>> + case CHIP_HAWAII:
>>> + baco_reset = cik_asic_supports_baco(adev);
>>> + break;
>>> default:
>>> baco_reset = false;
>>> break;
>>> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> index 3be40114e63d..45f608838f6e 100644
>>> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> @@ -142,12 +142,12 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK,
>>> BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK,
>>> BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
>>> { CMD_DELAY_MS, 0, 0, 0, 20, 0 },
>>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
>>> 0x, 0x20 },
>>> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
>>> + 0x, 0x200 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK,
>>> BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
>>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
>>> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5,
>>> + 0x1c00 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL,
>>> BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0,
>>> 0x01 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK,
>>> BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
>>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0,
>>> 5, 0x10 },
>>> + { CMD_WAITFOR, mmBACO_CNTL,
>>> + BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK,
>>> BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
>>> { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0,
>>> 0x, 0x00 } }; @@ -155,6 +155,7 @@ static const struct
>>> baco_cmd_entry exit_baco_tbl[] = static const struct baco_cmd_entry
>>> clean_baco_tbl[] = {
>>> { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
>>> + { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
>>> { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 } };
>>>
>>> --
>>> 2.29.0
>>
>>
>>
>> Not sure why I'm cc'd on this, I'm not a maintainer, nor does this patch
>> seem related to any patches I've contributed.
>>
>> - Sandeep
>
>
> Ok, I just saw the other email. I'll try testing the patch and see if it
> fixes the hibernation bug.
>
> - Sandeep
I tested and while suspend works correctly, hibernation is completely broken.
The system fails to resume from hibernation which is much worse than before.
- Sandeep
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[PATCH] drm/amd/amdgpu: Add rev_id workaround logic for SRIOV setup
- When we are under SRIOV setup, the rev_id cannot be read
properly. Therefore, we will return default value for it
Change-Id: I188d8e1b77f97c2eb29ef01aaf9ff9ea396a51c2
Signed-off-by: Bokun Zhang
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index e0048806afaa..04c152843601 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -53,8 +53,20 @@ static void nbio_v2_3_remap_hdp_registers(struct
amdgpu_device *adev)
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
{
- u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+ u32 tmp;
+
+ if (amdgpu_sriov_vf(adev)) {
+ /* workaround on rev_id for sriov
+ * guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0,
+ * as a consequence, the rev_id and external_rev_id are wrong.
+ *
+ * workaround it by hardcoding the rev_id to 0,
+ * (which is the default value)
+ */
+ return 0;
+ }
+ tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
--
2.25.1
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[PATCH 05/25] drm/amd/display: Keep GSL for full updates with planes that flip VSYNC
From: Alvin Lee
[Why]
When enabling PIP in Heaven, the PIP planes are VSYNC
flip and is also the top-most pipe. In this case GSL
will be disabled because we only check immediate flip
for the top pipe. However, the desktop planes are still
flip immediate so we should at least keep GSL on until
the full update.
[How]
Check each pipe in the tree to see if any planes
are flip immediate. Maintain the GSL lock if yes,
and take it down after when unlocking if any planes
are flipping VSYNC. Keeping GSL on with VSYNC +
flip immediate planes causes corruption.
Signed-off-by: Alvin Lee
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 71499c131947..3b26396cbc5c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1158,6 +1158,7 @@ void dcn20_pipe_control_lock(
struct pipe_ctx *pipe,
bool lock)
{
+ struct pipe_ctx *temp_pipe;
bool flip_immediate = false;
/* use TG master update lock to lock everything on the TG
@@ -1169,6 +1170,13 @@ void dcn20_pipe_control_lock(
if (pipe->plane_state != NULL)
flip_immediate = pipe->plane_state->flip_immediate;
+ temp_pipe = pipe->bottom_pipe;
+ while (!flip_immediate && temp_pipe) {
+ if (temp_pipe->plane_state != NULL)
+ flip_immediate = temp_pipe->plane_state->flip_immediate;
+ temp_pipe = temp_pipe->bottom_pipe;
+ }
+
if (flip_immediate && lock) {
const int TIMEOUT_FOR_FLIP_PENDING = 10;
int i;
@@ -1196,6 +1204,17 @@ void dcn20_pipe_control_lock(
(!flip_immediate && pipe->stream_res.gsl_group > 0))
dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
+ temp_pipe = pipe->bottom_pipe;
+ while (flip_immediate && temp_pipe) {
+ if (temp_pipe->plane_state != NULL)
+ flip_immediate = temp_pipe->plane_state->flip_immediate;
+ temp_pipe = temp_pipe->bottom_pipe;
+ }
+
+ if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
+ !flip_immediate)
+ dcn20_setup_gsl_group_as_lock(dc, pipe, false);
+
if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
--
2.17.1
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[PATCH 13/25] drm/amd/display: correct eDP T9 delay
From: Hugo Hu
[Why]
The current end of T9 delay is relay on polling
sink status by DPCD. But the polling for sink
status change after NoVideoStream_flag set to 0.
[How]
Add function edp_add_delay_for_T9 to add T9 delay.
Move the sink status polling after blank.
Signed-off-by: Hugo Hu
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/dc/core/dc_link_hwss.c | 13 -
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 16
drivers/gpu/drm/amd/display/dc/inc/link_hwss.h | 1 +
3 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 11a619befb42..124ce215fca5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -156,6 +156,13 @@ void dp_enable_link_phy(
dp_receiver_power_ctrl(link, true);
}
+void edp_add_delay_for_T9(struct dc_link *link)
+{
+ if (link->local_sink &&
+
link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
+
udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off *
1000);
+}
+
bool edp_receiver_ready_T9(struct dc_link *link)
{
unsigned int tries = 0;
@@ -165,7 +172,7 @@ bool edp_receiver_ready_T9(struct dc_link *link)
result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, ,
sizeof(edpRev));
- /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
+/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
if (result == DC_OK && edpRev >= DP_EDP_12) {
do {
sinkstatus = 1;
@@ -178,10 +185,6 @@ bool edp_receiver_ready_T9(struct dc_link *link)
} while (++tries < 50);
}
- if (link->local_sink &&
-
link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
-
udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off *
1000);
-
return result;
}
bool edp_receiver_ready_T7(struct dc_link *link)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 3ac6c7b65a45..9f56887029ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -992,8 +992,6 @@ void dce110_edp_backlight_control(
link_transmitter_control(ctx->dc_bios, );
-
-
if (enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_POST_T7_DELAY);
@@ -1004,7 +1002,7 @@ void dce110_edp_backlight_control(
/*edp 1.2*/
if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
- edp_receiver_ready_T9(link);
+ edp_add_delay_for_T9(link);
if (!enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_PRE_T11_DELAY);
@@ -1145,12 +1143,14 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
- /*
-* After output is idle pattern some sinks need time to
recognize the stream
-* has changed or they enter protection state and hang.
-*/
- if (!dc_is_embedded_signal(pipe_ctx->stream->signal))
+ if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
+ /*
+* After output is idle pattern some sinks need time to
recognize the stream
+* has changed or they enter protection state and hang.
+*/
msleep(60);
+ } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
+ edp_receiver_ready_T9(link);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index 9af7ee5bc8ee..33590a728fc5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -51,6 +51,7 @@ void dp_enable_link_phy(
const struct dc_link_settings *link_settings);
void dp_receiver_power_ctrl(struct dc_link *link, bool on);
+void edp_add_delay_for_T9(struct dc_link *link);
bool edp_receiver_ready_T9(struct dc_link *link);
bool edp_receiver_ready_T7(struct dc_link *link);
--
2.17.1
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[PATCH 25/25] drm/amd/display: fix recout calculation for left side clip
From: Dmytro Laktyushkin Recout calculation does not corrrectly handle plane clip rect that extends beyond the left most border of stream source rect. This change adds handling by truncating the invisible clip rect. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Hersen Wu Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index d49a8b3e5137..998d87b852a7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -825,6 +825,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) } else data->recout.x = 0; + if (stream->src.x > surf_clip.x) + surf_clip.width -= stream->src.x - surf_clip.x; data->recout.width = surf_clip.width * stream->dst.width / stream->src.width; if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width) data->recout.width = stream->dst.x + stream->dst.width - data->recout.x; @@ -833,6 +835,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) if (stream->src.y < surf_clip.y) data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height / stream->src.height; + else if (stream->src.y > surf_clip.y) + surf_clip.height -= stream->src.y - surf_clip.y; data->recout.height = surf_clip.height * stream->dst.height / stream->src.height; if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 23/25] drm/amd/display: [FW Promotion] Release 0.0.40
From: Anthony Koo
[Header Changes]
- Add command for retrieving PSR residency
- Add command for forcing PSR static
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 221bb2d65c1c..81433c22fb51 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x26ad601d9
+#define DMUB_FW_VERSION_GIT_HASH 0x9f0af34af
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 39
+#define DMUB_FW_VERSION_REVISION 40
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
@@ -274,6 +274,7 @@ enum dmub_gpint_command {
* ARGS: Stream mask, 1 bit per active stream index.
*/
DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
+ DMUB_GPINT__PSR_RESIDENCY = 9,
};
//==
@@ -583,6 +584,7 @@ enum dmub_cmd_psr_type {
DMUB_CMD__PSR_ENABLE= 2,
DMUB_CMD__PSR_DISABLE = 3,
DMUB_CMD__PSR_SET_LEVEL = 4,
+ DMUB_CMD__PSR_FORCE_STATIC = 5,
};
enum psr_version {
@@ -643,6 +645,10 @@ struct dmub_rb_cmd_psr_set_version {
struct dmub_cmd_psr_set_version_data psr_set_version_data;
};
+struct dmub_rb_cmd_psr_force_static {
+ struct dmub_cmd_header header;
+};
+
union dmub_hw_lock_flags {
struct {
uint8_t lock_pipe : 1;
@@ -800,6 +806,7 @@ union dmub_rb_cmd {
struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
struct dmub_rb_cmd_psr_enable psr_enable;
struct dmub_rb_cmd_psr_set_level psr_set_level;
+ struct dmub_rb_cmd_psr_force_static psr_force_static;
struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
struct dmub_rb_cmd_mall mall;
struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
--
2.17.1
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[PATCH 14/25] drm/amd/display: Update connector on DSC property change
From: Eryk Brol
[Why]
We want to trigger atomic check on connector when
DSC debugfs properties are changed. The previous
method was reverted because it accessed connector
properties unsafely and would also heavily
impact performance.
[How]
Add a flag for forcing DSC update in CRTC state
and add connector to the state if the flag is set.
Signed-off-by: Eryk Brol
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 124 ++
3 files changed, 130 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fdb1fa72061a..345eb2130869 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8773,6 +8773,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
enum dc_status status;
int ret, i;
bool lock_and_validation_needed = false;
+ struct dm_crtc_state *dm_old_crtc_state;
trace_amdgpu_dm_atomic_check_begin(state);
@@ -8815,9 +8816,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
}
#endif
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
+ dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+
if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
!new_crtc_state->color_mgmt_changed &&
- old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
+ old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled
&&
+ dm_old_crtc_state->dsc_force_changed == false)
continue;
if (!new_crtc_state->enable)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 6057eb6bc362..9bf141aa660c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -440,6 +440,7 @@ struct dm_crtc_state {
bool freesync_timing_changed;
bool freesync_vrr_info_changed;
+ bool dsc_force_changed;
bool vrr_supported;
struct mod_freesync_config freesync_config;
struct dc_info_packet vrr_infopacket;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 8cd646eef096..5c72ebd5998f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1253,6 +1253,10 @@ static ssize_t dp_dsc_clock_en_write(struct file *f,
const char __user *buf,
size_t size, loff_t *pos)
{
struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+ struct drm_connector *connector = >base;
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc = NULL;
+ struct dm_crtc_state *dm_crtc_state = NULL;
struct pipe_ctx *pipe_ctx;
int i;
char *wr_buf = NULL;
@@ -1295,6 +1299,25 @@ static ssize_t dp_dsc_clock_en_write(struct file *f,
const char __user *buf,
if (!pipe_ctx || !pipe_ctx->stream)
goto done;
+ // Get CRTC state
+ mutex_lock(>mode_config.mutex);
+ drm_modeset_lock(>mode_config.connection_mutex, NULL);
+
+ if (connector->state == NULL)
+ goto unlock;
+
+ crtc = connector->state->crtc;
+ if (crtc == NULL)
+ goto unlock;
+
+ drm_modeset_lock(>mutex, NULL);
+ if (crtc->state == NULL)
+ goto unlock;
+
+ dm_crtc_state = to_dm_crtc_state(crtc->state);
+ if (dm_crtc_state->stream == NULL)
+ goto unlock;
+
if (param[0] == 1)
aconnector->dsc_settings.dsc_force_enable =
DSC_CLK_FORCE_ENABLE;
else if (param[0] == 2)
@@ -1302,6 +1325,14 @@ static ssize_t dp_dsc_clock_en_write(struct file *f,
const char __user *buf,
else
aconnector->dsc_settings.dsc_force_enable =
DSC_CLK_FORCE_DEFAULT;
+ dm_crtc_state->dsc_force_changed = true;
+
+unlock:
+ if (crtc)
+ drm_modeset_unlock(>mutex);
+ drm_modeset_unlock(>mode_config.connection_mutex);
+ mutex_unlock(>mode_config.mutex);
+
done:
kfree(wr_buf);
return size;
@@ -1408,6 +1439,10 @@ static ssize_t dp_dsc_slice_width_write(struct file *f,
const char __user *buf,
{
struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
struct pipe_ctx *pipe_ctx;
+ struct drm_connector *connector = >base;
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc = NULL;
+ struct dm_crtc_state *dm_crtc_state
[PATCH 18/25] drm/amd/display: Calculate CRC on specific frame region
From: Wayne Lin
[why]
Currently, we only support calculating CRC on whole frame.
We want to extend the capability to calculate CRC on
specific frame area.
[how]
Calculate CRC on specific area once it's specified from the
input parameter.
Signed-off-by: Wayne Lin
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +--
drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 +
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index d0699e98db92..c29dc11619f7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -115,7 +115,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc
*crtc,
/* Enable CRTC CRC generation if necessary. */
if (dm_is_crc_source_crtc(source)) {
if (!dc_stream_configure_crc(stream_state->ctx->dc,
-stream_state, enable, enable)) {
+stream_state, NULL, enable,
enable)) {
ret = -EINVAL;
goto unlock;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 18154eea09f8..34e76fdc1334 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -346,7 +346,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
* calculate the crc.
*/
bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
-bool enable, bool continuous)
+struct crc_params *crc_window, bool enable, bool
continuous)
{
int i;
struct pipe_ctx *pipe;
@@ -362,7 +362,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct
dc_stream_state *stream,
if (i == MAX_PIPES)
return false;
- /* Always capture the full frame */
+ /* By default, capture the full frame */
param.windowa_x_start = 0;
param.windowa_y_start = 0;
param.windowa_x_end = pipe->stream->timing.h_addressable;
@@ -372,6 +372,17 @@ bool dc_stream_configure_crc(struct dc *dc, struct
dc_stream_state *stream,
param.windowb_x_end = pipe->stream->timing.h_addressable;
param.windowb_y_end = pipe->stream->timing.v_addressable;
+ if (crc_window) {
+ param.windowa_x_start = crc_window->windowa_x_start;
+ param.windowa_y_start = crc_window->windowa_y_start;
+ param.windowa_x_end = crc_window->windowa_x_end;
+ param.windowa_y_end = crc_window->windowa_y_end;
+ param.windowb_x_start = crc_window->windowb_x_start;
+ param.windowb_y_start = crc_window->windowb_y_start;
+ param.windowb_x_end = crc_window->windowb_x_end;
+ param.windowb_y_end = crc_window->windowb_y_end;
+ }
+
param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
param.odm_mode = pipe->next_odm_pipe ? 1:0;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 82a35d008094..e37720344819 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -457,6 +457,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
bool dc_stream_configure_crc(struct dc *dc,
struct dc_stream_state *stream,
+struct crc_params *crc_window,
bool enable,
bool continuous);
--
2.17.1
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[PATCH 09/25] drm/amd/display: 3.2.109
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index c74be6dafafc..273963e8e61a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.108" +#define DC_VER "3.2.109" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 02/25] drm/amd/display: Add MPC memory shutdown support for DCN3
From: Jacky Liao
[Why]
The MPC memory blocks in DCN3 should be powered down completely when
they are not in use. This will reduce power consumption.
[How]
This commits changes behaviour for dcn3 and does the following:
1. Write to MPC_RMU_LOW_PWR_MODE and MPCC_OGAM_MEM_LOW_PWR_MODE to
automatically shut down memory when not in use
2. mpc3_power_on_shaper_3dlut and mpc3_power_on_ogam_lut are called
to disable force power on when configuration finishes
3. Added a debug option to allow this behaviour to be turned off
Signed-off-by: Jacky Liao
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 56 ++-
.../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 9 +++
3 files changed, 63 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index b7f53908ebea..c74be6dafafc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -506,6 +506,7 @@ struct dc_debug_options {
bool disable_dsc;
bool enable_dram_clock_change_one_display_vactive;
bool force_ignore_link_settings;
+ bool enable_mpc_mem_powerdown: 1;
};
struct dc_debug_data {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 8fadd61a55ec..1671688557f4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -143,8 +143,16 @@ static void mpc3_power_on_ogam_lut(
{
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
- REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
- MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
+ if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {
+ // Force power on
+ REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_DIS,
power_on == true ? 1:0);
+ // Wait for confirmation when powering on
+ if (power_on)
+ REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id],
MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10);
+ } else {
+ REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
+ MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0 :
1);
+ }
}
static void mpc3_configure_ogam_lut(
@@ -360,6 +368,9 @@ void mpc3_set_output_gamma(
/*we need to program 2 fields here as apposed to 1*/
REG_UPDATE(MPCC_OGAM_CONTROL[mpcc_id],
MPCC_OGAM_SELECT, next_mode == LUT_RAM_A ? 0:1);
+
+ if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown)
+ mpc3_power_on_ogam_lut(mpc, mpcc_id, false);
}
void mpc3_set_denorm(
@@ -801,16 +812,28 @@ static void mpc3_power_on_shaper_3dlut(
uint32_t power_status_shaper = 2;
uint32_t power_status_3dlut = 2;
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+ int max_retries = 10;
if (rmu_idx == 0) {
REG_SET(MPC_RMU_MEM_PWR_CTRL, 0,
MPC_RMU0_MEM_PWR_DIS, power_on == true ? 1:0);
+ /* wait for memory to fully power up */
+ if (power_on && mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {
+ REG_WAIT(MPC_RMU_MEM_PWR_CTRL,
MPC_RMU0_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
+ REG_WAIT(MPC_RMU_MEM_PWR_CTRL,
MPC_RMU0_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
+ }
+
/*read status is not mandatory, it is just for debugging*/
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE,
_status_shaper);
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE,
_status_3dlut);
} else if (rmu_idx == 1) {
REG_SET(MPC_RMU_MEM_PWR_CTRL, 0,
MPC_RMU1_MEM_PWR_DIS, power_on == true ? 1:0);
+ if (power_on && mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {
+ REG_WAIT(MPC_RMU_MEM_PWR_CTRL,
MPC_RMU1_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
+ REG_WAIT(MPC_RMU_MEM_PWR_CTRL,
MPC_RMU1_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
+ }
+
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE,
_status_shaper);
REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE,
_status_3dlut);
}
@@ -838,6 +861,10 @@ bool mpc3_program_shaper(
REG_SET(SHAPER_CONTROL[rmu_idx], 0, MPC_RMU_SHAPER_LUT_MODE, 0);
return false;
}
+
+ if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown)
+ mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true);
+
current_mode = mpc3_get_shaper_current(mpc, rmu_idx);
if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
@@ -1196,6 +1223,9 @@ bool mpc3_program_3dlut(
mpc3_set_3dlut_mode(mpc, mode, is_12bits_color_channel,
[PATCH 15/25] drm/amd/display: Reset flip_immediate to topmost plane
From: Alvin Lee
[Why]
When checking if we want to disable GSL or not,
we should reset flip_immediate to be the flip type
of the topmost plane before looping through the
other planes.
[How]
Set flip_immediate to be the flip type of the topmost
plane before looping through the other planes.
Signed-off-by: Alvin Lee
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 3b26396cbc5c..a195dfb718dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1204,6 +1204,9 @@ void dcn20_pipe_control_lock(
(!flip_immediate && pipe->stream_res.gsl_group > 0))
dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
+ if (pipe->plane_state != NULL)
+ flip_immediate = pipe->plane_state->flip_immediate;
+
temp_pipe = pipe->bottom_pipe;
while (flip_immediate && temp_pipe) {
if (temp_pipe->plane_state != NULL)
--
2.17.1
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[PATCH 12/25] drm/amd/display: Add OPTC memory low power support
From: Jacky Liao
[Why]
The OPTC memory blocks should be powered down when they are not in use.
This will reduce power consumption.
[How]
1. Set ODM_MEM_UNASSIGNED_PWR_MODE to shutdown memory when unassigned
2. Set ODM_MEM_VBLANK_PWR_MODE to light sleep mode when in vblank
3. Added a debug option to allow this behaviour to be turned off
4. Restructured debug options to use a bitfield in a way that's more clear
Signed-off-by: Jacky Liao
Reviewed-by: Eric Yang
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h| 10 +-
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 12 ++--
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 ++
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 14 +++---
4 files changed, 32 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 273963e8e61a..87bc10279349 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -414,6 +414,14 @@ struct dc_bw_validation_profile {
} \
}
+union mem_low_power_enable_options {
+ struct {
+ bool mpc: 1;
+ bool optc: 1;
+ } bits;
+ uint32_t u32All;
+};
+
struct dc_debug_options {
enum visual_confirm visual_confirm;
bool sanity_checks;
@@ -506,7 +514,7 @@ struct dc_debug_options {
bool disable_dsc;
bool enable_dram_clock_change_one_display_vactive;
bool force_ignore_link_settings;
- bool enable_mpc_mem_powerdown: 1;
+ union mem_low_power_enable_options enable_mem_low_power;
};
struct dc_debug_data {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index b77e22bf6aec..a8103c762c08 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -607,6 +607,10 @@ struct dce_hwseq_registers {
uint32_t MC_VM_XGMI_LFB_CNTL;
uint32_t AZALIA_AUDIO_DTO;
uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
+ #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ uint32_t HPO_TOP_CLOCK_CONTROL;
+ uint32_t ODM_MEM_PWR_CTRL3;
+ #endif
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -845,7 +849,9 @@ struct dce_hwseq_registers {
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
- HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
+ HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+ HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
+ HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
@@ -1059,7 +1065,9 @@ struct dce_hwseq_registers {
type D2VGA_MODE_ENABLE; \
type D3VGA_MODE_ENABLE; \
type D4VGA_MODE_ENABLE; \
- type AZALIA_AUDIO_DTO_MODULE;
+ type AZALIA_AUDIO_DTO_MODULE; \
+ type ODM_MEM_UNASSIGNED_PWR_MODE; \
+ type ODM_MEM_VBLANK_PWR_MODE;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define HWSEQ_DCN3_REG_FIELD_LIST(type) \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 3699c9a2789c..53b892f16da4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -462,6 +462,12 @@ void dcn30_init_hw(struct dc *dc)
hws->funcs.disable_vga(dc->hwseq);
}
+ // Set default OPTC memory power states
+ if (dc->debug.enable_mem_low_power.bits.optc) {
+ // Shutdown when unassigned and light sleep in VBLANK
+ REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3,
ODM_MEM_VBLANK_PWR_MODE, 1);
+ }
+
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 1671688557f4..d7d053fc6e91 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -143,7 +143,7 @@ static void mpc3_power_on_ogam_lut(
{
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
- if (mpc->ctx->dc->debug.enable_mpc_mem_powerdown) {
+ if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
// Force power on
REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_DIS,
power_on == true ? 1:0);
// Wait for confirmation when powering on
@@ -369,7 +369,7 @@ void mpc3_set_output_gamma(
REG_UPDATE(MPCC_OGAM_CONTROL[mpcc_id],
MPCC_OGAM_SELECT, next_mode == LUT_RAM_A ?
[PATCH 21/25] drm/amd/display: set hdcp1 wa re-auth delay to 200ms
From: Jake Wang
[Why]
Fail and restart timing for HDCP1 retry occurs too quickly.
This would cause some MST monitors to show black screen.
[How]
Adjusted timing of fail and restart to 200ms.
Signed-off-by: Jake Wang
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
index f3711914364e..24ab95b093f7 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
@@ -231,7 +231,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct
mod_hdcp *hdcp,
fail_and_restart_in_ms(0, , output);
break;
} else if (conn->hdcp1_retry_count <
conn->link.adjust.hdcp1.min_auth_retries_wa) {
- fail_and_restart_in_ms(0, , output);
+ fail_and_restart_in_ms(200, , output);
break;
}
if (conn->is_repeater) {
--
2.17.1
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[PATCH 08/25] drm/amd/display: Blank HUBP during pixel data blank for DCN30
From: Joshua Aberback
[Why]
There are some timings for which we support p-state
switching in active, but not in blank. There was a
previous issue where a timing that had active-only
support would hang a p-state request when we were in
an extended blanking period. The workaround for that
issue was to block active-only p-state switching,
but that resulted in a lack of p-state support for
some common timings such as 1440p60. We want to fix
that issue properly by un-blocking p-state requests
while the display is blanked, so that we can re-enable
active-only p-state switching.
[How]
- new version of blank_pixel_data for DCN30
- call hubp->set_blank from dcn30_blank_pixel_data
- blank every hubp in the mpcc tree, and odm tree
- on blank enable, wait until the next frame before blanking HUBP
Signed-off-by: Joshua Aberback
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 83 +++
.../drm/amd/display/dc/dcn30/dcn30_hwseq.h| 2 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 +-
.../dc/dml/dcn30/display_mode_vba_30.c| 2 +-
4 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index f3ae208850b0..3699c9a2789c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -794,3 +794,86 @@ void dcn30_hardware_release(struct dc *dc)
dc->res_pool->hubbub->funcs->force_pstate_change_control(
dc->res_pool->hubbub, true, true);
}
+
+void dcn30_blank_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool
blank)
+{
+ struct tg_color black_color = {0};
+ struct stream_resource *stream_res = _ctx->stream_res;
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ enum dc_color_space color_space = stream->output_color_space;
+ enum controller_dp_test_pattern test_pattern =
CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
+ enum controller_dp_color_space test_pattern_color_space =
CONTROLLER_DP_COLOR_SPACE_UDEFINED;
+ struct pipe_ctx *odm_pipe;
+ struct pipe_ctx *mpcc_pipe;
+ int odm_cnt = 1;
+
+ int width = stream->timing.h_addressable + stream->timing.h_border_left
+ stream->timing.h_border_right;
+ int height = stream->timing.v_addressable +
stream->timing.v_border_bottom + stream->timing.v_border_top;
+
+ if (stream->link->test_pattern_enabled)
+ return;
+
+ /* get opp dpg blank color */
+ color_space_to_black_color(dc, color_space, _color);
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe =
odm_pipe->next_odm_pipe)
+ odm_cnt++;
+
+ width = width / odm_cnt;
+
+ if (blank) {
+ dc->hwss.set_abm_immediate_disable(pipe_ctx);
+
+ if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
+ test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
+ test_pattern_color_space =
CONTROLLER_DP_COLOR_SPACE_RGB;
+ }
+ } else {
+ test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
+ }
+
+ stream_res->opp->funcs->opp_set_disp_pattern_generator(
+ stream_res->opp,
+ test_pattern,
+ test_pattern_color_space,
+ stream->timing.display_color_depth,
+ _color,
+ width,
+ height,
+ 0);
+
+ /* wait for the next frame when enabling DPG */
+ if (blank && stream_res->tg->funcs->is_tg_enabled(stream_res->tg))
+
dc->hwseq->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
+
+ /* Blank HUBP to allow p-state during blank on all timings */
+ pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp,
blank);
+ for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe =
mpcc_pipe->bottom_pipe)
+
mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, blank);
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe =
odm_pipe->next_odm_pipe) {
+ odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
+ odm_pipe->stream_res.opp,
+ dc->debug.visual_confirm !=
VISUAL_CONFIRM_DISABLE && blank ?
+
CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
+ test_pattern_color_space,
+ stream->timing.display_color_depth,
+ _color,
+ width,
+ height,
+ 0);
+
+ if (blank &&
[PATCH 20/25] drm/amd/display: Revert HUBP blank behaviour for now
From: Joshua Aberback
[Why]
Commit "Blank HUBP during pixel data blank for DCN30 v2"
modifies HW behaviour during blank, which might have OS
dependencies. We need to assess the impact on amdgpu_dm
and only re-enable HUBP blanking when all necessary
changes are understood.
[How]
- revert functional changes
- leave architectural changes intact
Signed-off-by: Joshua Aberback
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 27 ++-
.../dc/dml/dcn30/display_mode_vba_30.c| 2 +-
2 files changed, 3 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 6b6e92e261ef..a57e83428a77 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -809,29 +809,6 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
const struct tg_color *solid_color,
int width, int height, int offset)
{
- struct stream_resource *stream_res = _ctx->stream_res;
- struct pipe_ctx *mpcc_pipe;
-
- if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) {
- /* turning on DPG */
-
stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp,
test_pattern, color_space,
- color_depth, solid_color, width, height, 0);
-
- /* wait for the next frame when enabling DPG */
- if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg))
-
dc->hwseq->funcs.wait_for_blank_complete(stream_res->opp);
-
- /* Blank HUBP to allow p-state during blank on all timings */
-
pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true);
- for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe =
mpcc_pipe->bottom_pipe)
-
mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
- } else {
- /* turning off DPG */
-
pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false);
- for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe =
mpcc_pipe->bottom_pipe)
-
mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false);
-
-
stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp,
test_pattern, color_space,
- color_depth, solid_color, width, height, 0);
- }
+
pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp,
test_pattern,
+ color_space, color_depth, solid_color, width, height,
0);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 50b7d011705d..9e0ae18e71fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -5558,7 +5558,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
}
}
- if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
+ if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0 && PrefetchMode ==
0) {
*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
} else if (((mode_lib->vba.SynchronizedVBlank == true ||
mode_lib->vba.TotalNumberOfActiveOTG == 1 ||
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode ==
0)) {
*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
--
2.17.1
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[PATCH 22/25] drm/amd/display: Add missing pflip irq
From: Bhawanpreet Lakha
If we have more than 4 displays we will run
into dummy irq calls or flip timout issues.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
index 49689f71f4f1..0effbb2bd74a 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
@@ -306,8 +306,8 @@ irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = {
pflip_int_entry(1),
pflip_int_entry(2),
pflip_int_entry(3),
- [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
- [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
+ pflip_int_entry(4),
+ pflip_int_entry(5),
[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
gpio_pad_int_entry(0),
gpio_pad_int_entry(1),
--
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[PATCH 19/25] drm/amd/display: WA to ensure MUX chip gets SUPPORTED_LINK_RATES of eDP
From: Dale Zhao
[Why]
Customer make a request to add this WA by driver.
Some MUX chips will power down with eDP 1.4 panel and
lose previous supported link rates(DPCD 0x010) in
customer's hybrid-GPU designs. As a result, during sleep
resuming and screen turns on from idle, link training
will be performed incorrectly and eDP will flicker or
black screen. These MUX chips need source to read DPCD
0x010 again during LKT so that it can restore supported
link rates of panel.
For driver side, supported link rate set is fetched when
link detection, no need to update but just read again
as WA.
[How]
Read DPCD 0x010 again during link training for eDP 1.4.
Signed-off-by: Dale Zhao
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9d1c5e1d06c0..54ac3de4e8e0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -183,6 +183,16 @@ static void dpcd_set_link_settings(
if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
lt_settings->link_settings.use_link_rate_set == true) {
rate = 0;
+ /* WA for some MUX chips that will power down with eDP and lose
supported
+* link rate set for eDP 1.4. Source reads DPCD 0x010 again to
ensure
+* MUX chip gets link rate set back before link training.
+*/
+ if (link->connector_signal == SIGNAL_TYPE_EDP) {
+ uint8_t supported_link_rates[16];
+
+ core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
+ supported_link_rates,
sizeof(supported_link_rates));
+ }
core_link_write_dpcd(link, DP_LINK_BW_SET, , 1);
core_link_write_dpcd(link, DP_LINK_RATE_SET,
_settings->link_settings.link_rate_set, 1);
--
2.17.1
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[PATCH 24/25] drm/amd/display: 3.2.110
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 87bc10279349..e6b92683dc5b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.109" +#define DC_VER "3.2.110" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/25] drm/amd/display: Update panel register
From: Chris Park
[Why]
Incorrect panel register settings are
applied for power sequence because the
register macro is not defined in resource.
[How]
Implement same register space to future
resource files.
Signed-off-by: Chris Park
Reviewed-by: Joshua Aberback
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index c4ffed95d35e..2345f12ceab3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -967,7 +967,7 @@ static const struct encoder_feature_support
link_enc_feature = {
[id] = {\
LE_DCN3_REG_LIST(id), \
UNIPHY_DCN2_REG_LIST(phyid), \
- DPCS_DCN2_REG_LIST(id), \
+ SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
}
static const struct dcn10_link_enc_registers link_enc_regs[] = {
--
2.17.1
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[PATCH 03/25] drm/amd/display: only check available pipe to disable vbios mode.
From: Yongqiang Sun
[Why & How]
1. only need to check first ODM pipe.
2. Only need to check eDP which is on.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1fa4a50e0a44..18154eea09f8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -861,12 +861,16 @@ static void disable_vbios_mode_if_required(
if (stream == NULL)
continue;
+ // only looking for first odm pipe
+ if (pipe->prev_odm_pipe)
+ continue;
+
if (stream->link->local_sink &&
stream->link->local_sink->sink_signal ==
SIGNAL_TYPE_EDP) {
link = stream->link;
}
- if (link != NULL) {
+ if (link != NULL &&
link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
unsigned int enc_inst, tg_inst = 0;
unsigned int pix_clk_100hz;
--
2.17.1
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[PATCH 17/25] drm/amd/display: Do not warn NULL dc_sink if forcing connector
From: Victor Lu
[why]
There is a DRM_ERROR when the dc_sink is NULL and
there should not be this warning when the connector
is forced.
[how]
Do not warn if dc_sink is NULL if the connector
is forced.
Signed-off-by: Victor Lu
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 345eb2130869..6b3ae523e62e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5485,7 +5485,8 @@ enum drm_mode_status
amdgpu_dm_connector_mode_valid(struct drm_connector *connec
dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
- if (dc_sink == NULL) {
+ if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
+ aconnector->base.force != DRM_FORCE_ON) {
DRM_ERROR("dc_sink is NULL!\n");
goto fail;
}
--
2.17.1
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[PATCH 04/25] drm/amd/display: Force prefetch mode to 0
From: Isabel Zhang
[Why]
On APU should be always using prefetch mode 0.
Currently, sometimes prefetch mode 1 is being
used causing system to hard hang due to
minTTUVBlank being too low.
[How]
Any ASIC running DCN21 will by default allow
self refresh and mclk switch. This sets both
min and max prefetch mode to 0 by default.
Signed-off-by: Isabel Zhang
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 70a18271bd2d..5ae3419682c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -301,7 +301,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.xfc_bus_transport_time_us = 4,
.xfc_xbuf_latency_tolerance_us = 4,
.use_urgent_burst_bw = 1,
- .num_states = 8
+ .num_states = 8,
+ .allow_dram_self_refresh_or_dram_clock_change_in_vblank
+ = dm_allow_self_refresh_and_mclk_switch
};
#ifndef MAX
--
2.17.1
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[PATCH 06/25] drm/amd/display: [FW Promotion] Release 0.0.39
From: Anthony Koo Signed-off-by: Anthony Koo Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index a4c3f078887d..221bb2d65c1c 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -36,10 +36,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x8aafc9acc +#define DMUB_FW_VERSION_GIT_HASH 0x26ad601d9 #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 38 +#define DMUB_FW_VERSION_REVISION 39 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/25] drm/amd/display: stop top_mgr when type change to non-MST during s3
From: Lewis Huang
[Why]
Driver keeps the invalid information cause report the
incorrect monitor which save in remote sink to OS
[How]
When connector type change from MST to non-MST,
stop the topology manager.
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 5652a072d9be..4dfa70c0301b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -854,6 +854,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
struct dpcd_caps prev_dpcd_caps;
bool same_dpcd = true;
enum dc_connection_type new_connection_type = dc_connection_none;
+ enum dc_connection_type pre_connection_type = dc_connection_none;
bool perform_dp_seamless_boot = false;
const uint32_t post_oui_delay = 30; // 30ms
@@ -889,6 +890,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
link_disconnect_sink(link);
if (new_connection_type != dc_connection_none) {
+ pre_connection_type = link->type;
link->type = new_connection_type;
link->link_state_valid = false;
@@ -962,6 +964,12 @@ static bool dc_link_detect_helper(struct dc_link *link,
return true;
}
+ // link switch from MST to non-MST stop topology manager
+ if (pre_connection_type == dc_connection_mst_branch &&
+ link->type != dc_connection_mst_branch) {
+ dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
+ }
+
if (link->type == dc_connection_mst_branch) {
LINK_INFO("link=%d, mst branch is now
Connected\n",
link->link_index);
--
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[PATCH 01/25] drm/amd/display: Fix compilation error
From: "Tao.Huang"
[Why]
The C standard does not specify whether an enum is signed or unsigned.
In the function prototype, one of the argument is defined as an enum
but its declaration was unit32_t. Fix this by changing the function
argument to enum in the declaration.
Signed-off-by: Tao.Huang
Signed-off-by: Florin Iucha
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h | 2 +-
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 6 +++---
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index 7f6bedbc1ff1..81bf2ecc2831 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -585,7 +585,7 @@ void dpp3_cm_set_gamut_remap(
const struct dpp_grph_csc_adjustment *adjust);
void dpp3_set_pre_degam(struct dpp *dpp_base,
- uint32_t degamma_lut_selection);
+ enum dc_transfer_func_predefined tr);
void dpp3_set_cursor_attributes(
struct dpp *dpp_base,
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
index 4da21966ddce..c6a1cd80aeae 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
@@ -51,7 +51,7 @@ static void get_qp_set(qp_set qps, enum colour_mode cm, enum
bits_per_comp bpc,
const struct qp_entry *table = 0L;
// alias enum
- enum { min = MM_MIN, max = MM_MAX };
+ enum { min = DAL_MM_MIN, max = DAL_MM_MAX };
switch (sel) {
TABLE_CASE(444, 8, max);
TABLE_CASE(444, 8, min);
@@ -233,8 +233,8 @@ static void _do_calc_rc_params(struct rc_params *rc, enum
colour_mode cm,
rc->flatness_max_qp = ((bpc == BPC_8) ? (12) : ((bpc == BPC_10) ?
(16) : (20))) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
rc->flatness_det_thresh = 2 << (bpc - 8);
- get_qp_set(rc->qp_min, cm, bpc, MM_MIN, bpp);
- get_qp_set(rc->qp_max, cm, bpc, MM_MAX, bpp);
+ get_qp_set(rc->qp_min, cm, bpc, DAL_MM_MIN, bpp);
+ get_qp_set(rc->qp_max, cm, bpc, DAL_MM_MAX, bpp);
if (cm == CM_444 && minor_version == 1) {
for (i = 0; i < QP_SET_SIZE; ++i) {
rc->qp_min[i] = rc->qp_min[i] > 0 ? rc->qp_min[i] - 1 :
0;
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
index 21723fa6561e..8123827840c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
@@ -66,8 +66,8 @@ enum bits_per_comp {
};
enum max_min {
- MM_MIN = 0,
- MM_MAX = 1
+ DAL_MM_MIN = 0,
+ DAL_MM_MAX = 1
};
struct qp_entry {
--
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[PATCH 10/25] drm/amd/display: fail instead of div by zero/bugcheck
From: Ashley Thomas
[why]
If pbn_per_slot is 0, fail instead of dividing by zero and
bugchecking.
[how]
Check for zero divisor before division operation.
Signed-off-by: Ashley Thomas
Reviewed-by: Wyatt Wood
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 2 ++
drivers/gpu/drm/amd/display/dc/core/dc_link.c| 4
drivers/gpu/drm/amd/display/dc/inc/core_status.h | 1 +
3 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 7977e2839065..21be2a684393 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -420,6 +420,8 @@ char *dc_status_to_str(enum dc_status status)
return "Fail clk below required CFG (hard_min in PPLIB)";
case DC_NOT_SUPPORTED:
return "The operation is not supported.";
+ case DC_UNSUPPORTED_VALUE:
+ return "The value specified is not supported.";
case DC_ERROR_UNEXPECTED:
return "Unexpected error";
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 4dfa70c0301b..eafefcf3696c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2951,6 +2951,10 @@ enum dc_status dc_link_allocate_mst_payload(struct
pipe_ctx *pipe_ctx)
/* slot X.Y for only current stream */
pbn_per_slot = get_pbn_per_slot(stream);
+ if (pbn_per_slot.value == 0) {
+ DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot
continue, returning DC_UNSUPPORTED_VALUE.\n");
+ return DC_UNSUPPORTED_VALUE;
+ }
pbn = get_pbn_from_timing(pipe_ctx);
avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 714593a15590..d34b0b0eea65 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -51,6 +51,7 @@ enum dc_status {
DC_FAIL_CLK_BELOW_CFG_REQUIRED = 23, /*THIS IS hard_min in PPLIB*/
DC_NOT_SUPPORTED = 24,
+ DC_UNSUPPORTED_VALUE = 25,
DC_ERROR_UNEXPECTED = -1
};
--
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[PATCH 16/25] drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2
From: Joshua Aberback
[Why]
Prior commit "Blank HUBP during pixel data blank for DCN30"
missed the call to set_disp_pattern_generator from
set_crtc_test_pattern, which re-exposed the issue for which
we initially blocked active-only p-state switching.
[How]
- remove dcn30_blank_pixel_data, set dcn30 back to dcn20 version
- new hwss funciton set_disp_pattern_generator
- dcn20 version just calls opp_set_disp_pattern_generator
- dcn30 version implements the HUBP blank
Signed-off-by: Joshua Aberback
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 62 ++--
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 20 +++-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.h| 9 ++
.../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 +
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 96 +--
.../drm/amd/display/dc/dcn30/dcn30_hwseq.h| 8 +-
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 3 +-
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 8 ++
9 files changed, 100 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2114c280895a..9d1c5e1d06c0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3848,7 +3848,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
controller_test_pattern, color_depth);
- else if (opp->funcs->opp_set_disp_pattern_generator) {
+ else if (link->dc->hwss.set_disp_pattern_generator) {
struct pipe_ctx *odm_pipe;
enum controller_dp_color_space controller_color_space;
int opp_cnt = 1;
@@ -3878,26 +3878,29 @@ static void set_crtc_test_pattern(struct dc_link *link,
dpg_width = width / opp_cnt;
offset = dpg_width;
- opp->funcs->opp_set_disp_pattern_generator(opp,
- controller_test_pattern,
- controller_color_space,
- color_depth,
- NULL,
- dpg_width,
- height,
- 0);
-
- for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe;
odm_pipe = odm_pipe->next_odm_pipe) {
- struct output_pixel_processor *odm_opp =
odm_pipe->stream_res.opp;
-
odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, );
-
odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
+ link->dc->hwss.set_disp_pattern_generator(link->dc,
+ pipe_ctx,
controller_test_pattern,
controller_color_space,
color_depth,
NULL,
dpg_width,
height,
- offset);
+ 0);
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe;
odm_pipe = odm_pipe->next_odm_pipe) {
+ struct output_pixel_processor *odm_opp =
odm_pipe->stream_res.opp;
+
+
odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, );
+
link->dc->hwss.set_disp_pattern_generator(link->dc,
+ odm_pipe,
+ controller_test_pattern,
+ controller_color_space,
+ color_depth,
+ NULL,
+ dpg_width,
+ height,
+ offset);
offset += offset;
}
}
@@ -3913,7 +3916,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
color_depth);
- else if (opp->funcs->opp_set_disp_pattern_generator) {
+ else if (link->dc->hwss.set_disp_pattern_generator) {
struct pipe_ctx
[PATCH 00/25] DC Patches Nov 2nd, 2020
This DC patchset brings improvements in multiple areas. In summary, we have: * DC 3.2.110 * Firmware release 0.0.40 * Enable CRC calculation on specific frame region * Bug fixes on GSL, recout calculation, missing pflip irq and more. --- Alvin Lee (2): drm/amd/display: Keep GSL for full updates with planes that flip VSYNC drm/amd/display: Reset flip_immediate to topmost plane Anthony Koo (2): drm/amd/display: [FW Promotion] Release 0.0.39 drm/amd/display: [FW Promotion] Release 0.0.40 Aric Cyr (2): drm/amd/display: 3.2.109 drm/amd/display: 3.2.110 Ashley Thomas (1): drm/amd/display: fail instead of div by zero/bugcheck Bhawanpreet Lakha (1): drm/amd/display: Add missing pflip irq Chris Park (1): drm/amd/display: Update panel register Dale Zhao (1): drm/amd/display: WA to ensure MUX chip gets SUPPORTED_LINK_RATES of eDP Dmytro Laktyushkin (1): drm/amd/display: fix recout calculation for left side clip Eryk Brol (1): drm/amd/display: Update connector on DSC property change Hugo Hu (1): drm/amd/display: correct eDP T9 delay Isabel Zhang (1): drm/amd/display: Force prefetch mode to 0 Jacky Liao (2): drm/amd/display: Add MPC memory shutdown support for DCN3 drm/amd/display: Add OPTC memory low power support Jake Wang (1): drm/amd/display: set hdcp1 wa re-auth delay to 200ms Joshua Aberback (3): drm/amd/display: Blank HUBP during pixel data blank for DCN30 drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2 drm/amd/display: Revert HUBP blank behaviour for now Lewis Huang (1): drm/amd/display: stop top_mgr when type change to non-MST during s3 Tao.Huang (1): drm/amd/display: Fix compilation error Victor Lu (1): drm/amd/display: Do not warn NULL dc_sink if forcing connector Wayne Lin (1): drm/amd/display: Calculate CRC on specific frame region Yongqiang Sun (1): drm/amd/display: only check available pipe to disable vbios mode. .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 124 ++ drivers/gpu/drm/amd/display/dc/core/dc.c | 21 ++- .../gpu/drm/amd/display/dc/core/dc_debug.c| 2 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 12 ++ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 72 +- .../drm/amd/display/dc/core/dc_link_hwss.c| 13 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 4 + drivers/gpu/drm/amd/display/dc/dc.h | 11 +- drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 + .../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 12 +- .../display/dc/dce110/dce110_hw_sequencer.c | 16 +-- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 42 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.h| 9 ++ .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 + .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +- .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h | 2 +- .../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 18 +++ .../drm/amd/display/dc/dcn30/dcn30_hwseq.h| 8 ++ .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 56 +++- .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 9 ++ .../amd/display/dc/dcn302/dcn302_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 6 +- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 4 +- .../gpu/drm/amd/display/dc/inc/core_status.h | 1 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 8 ++ .../gpu/drm/amd/display/dc/inc/link_hwss.h| 1 + .../display/dc/irq/dcn30/irq_service_dcn30.c | 4 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +- .../display/modules/hdcp/hdcp1_transition.c | 2 +- 34 files changed, 418 insertions(+), 72 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: remove unneeded semicolon
From: Tom Rix A semicolon is not needed after a switch statement. Signed-off-by: Tom Rix --- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 2 +- drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 7b4b2304bbff..5feb804af4be 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -858,7 +858,7 @@ static struct clock_source *find_matching_pll( return pool->clock_sources[DCE112_CLK_SRC_PLL5]; default: return NULL; - }; + } return 0; } diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c index fb6a19d020f9..ee5230ccf3c4 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c @@ -280,6 +280,6 @@ char *mod_hdcp_state_id_to_str(int32_t id) return "D2_A9_VALIDATE_STREAM_READY"; default: return "UNKNOWN_STATE_ID"; - }; + } } -- 2.18.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: remove unneeded semicolon
From: Tom Rix A semicolon is not needed after a switch statement. Signed-off-by: Tom Rix --- drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c index 1b213c4ddfcb..19c0a3655228 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c @@ -654,7 +654,7 @@ int amdgpu_pmu_init(struct amdgpu_device *adev) default: return 0; - }; + } return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 8bf6a7c056bc..a61cf8cfbfc3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -953,7 +953,7 @@ static char *amdgpu_ras_badpage_flags_str(unsigned int flags) case AMDGPU_RAS_RETIRE_PAGE_FAULT: default: return "F"; - }; + } } /** -- 2.18.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Subject: [RFC] clang tooling cleanups
This rfc will describe
An upcoming treewide cleanup.
How clang tooling was used to programatically do the clean up.
Solicit opinions on how to generally use clang tooling.
The clang warning -Wextra-semi-stmt produces about 10k warnings.
Reviewing these, a subset of semicolon after a switch looks safe to
fix all the time. An example problem
void foo(int a) {
switch(a) {
case 1:
...
}; <--- extra semicolon
}
Treewide, there are about 100 problems in 50 files for x86_64 allyesconfig.
These fixes will be the upcoming cleanup.
clang already supports fixing this problem. Add to your command line
clang -c -Wextra-semi-stmt -Xclang -fixit foo.c
foo.c:8:3: warning: empty expression statement has no effect;
remove unnecessary ';' to silence this warning [-Wextra-semi-stmt]
};
^
foo.c:8:3: note: FIX-IT applied suggested code changes
1 warning generated.
The big problem is using this treewide is it will fix all 10k problems.
10k changes to analyze and upstream is not practical.
Another problem is the generic fixer only removes the semicolon.
So empty lines with some tabs need to be manually cleaned.
What is needed is a more precise fixer.
Enter clang-tidy.
https://clang.llvm.org/extra/clang-tidy/
Already part of the static checker infrastructure, invoke on the clang
build with
make clang-tidy
It is only a matter of coding up a specific checker for the cleanup.
Upstream this is review is happening here
https://reviews.llvm.org/D90180
The development of a checker/fixer is
Start with a reproducer
void foo (int a) {
switch (a) {};
}
Generate the abstract syntax tree (AST)
clang -Xclang -ast-dump foo.c
`-FunctionDecl
|-ParmVarDecl
`-CompoundStmt
|-SwitchStmt
| |-ImplicitCastExpr
| | `-DeclRefExpr
| `-CompoundStmt
`-NullStmt
Write a matcher to get you most of the way
void SwitchSemiCheck::registerMatchers(MatchFinder *Finder) {
Finder->addMatcher(
compoundStmt(has(switchStmt().bind("switch"))).bind("comp"), this);
}
The 'bind' method is important, it allows a string to be associated
with a node in the AST. In this case these are
`-FunctionDecl
|-ParmVarDecl
`-CompoundStmt < comp
|-SwitchStmt < switch
| |-ImplicitCastExpr
| | `-DeclRefExpr
| `-CompoundStmt
`-NullStmt
When a match is made the 'check' method will be called.
void SwitchSemiCheck::check(const MatchFinder::MatchResult ) {
auto *C = Result.Nodes.getNodeAs("comp");
auto *S = Result.Nodes.getNodeAs("switch");
This is where the string in the bind calls are changed to nodes
`-FunctionDecl
|-ParmVarDecl
`-CompoundStmt < comp, C
|-SwitchStmt < switch, S
| |-ImplicitCastExpr
| | `-DeclRefExpr
| `-CompoundStmt
`-NullStmt <-- looking for N
And then more logic to find the NullStmt
auto Current = C->body_begin();
auto Next = Current;
Next++;
while (Next != C->body_end()) {
if (*Current == S) {
if (const auto *N = dyn_cast(*Next)) {
When it is found, a warning is printed and a FixItHint is proposed.
auto H = FixItHint::CreateReplacement(
SourceRange(S->getBody()->getEndLoc(), N->getSemiLoc()), "}");
diag(N->getSemiLoc(), "unneeded semicolon") << H;
This fixit replaces from the end of switch to the semicolon with a
'}'. Because the end of the switch is '}' this has the effect of
removing all the whitespace as well as the semicolon.
Because of the checker's placement in clang-tidy existing linuxkernel
checkers, all that was needed to fix the tree was to add a '-fix'to the
build's clang-tidy call.
I am looking for opinions on what we want to do specifically with
cleanups and generally about other source-to-source programmatic
changes to the code base.
For cleanups, I think we need a new toplevel target
clang-tidy-fix
And an explicit list of fixers that have a very high (100%?) fix rate.
Ideally a bot should make the changes, but a bot could also nag folks.
Is there interest in a bot making the changes? Does one already exist?
The general source-to-source is a bit blue sky. Ex/ could automagicly
refactor api, outline similar cut-n-pasted functions etc. Anything on
someone's wishlist you want to try out ?
Signed-off-by: Tom Rix
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Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c
[AMD Official Use Only - Internal Distribution Only]
Looks sane to me.
Acked-by: Slava Abramov
From: amd-gfx on behalf of Alex Deucher
Sent: Tuesday, October 27, 2020 11:20 AM
To: amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in
dcn30_hwseq.c
Ping?
On Mon, Oct 26, 2020 at 12:14 PM Alex Deucher wrote:
>
> This is required for MALL. Was accidently removed in PRS update.
>
> Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is
> enabled")
> Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")
> Signed-off-by: Alex Deucher
> ---
> .../gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index f3ae208850b0..cc2eca8c9a62 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc,
> bool enable)
> break;
> }
>
> + if (dc->current_state->stream_count == 1 // single
> display only
> + &&
> dc->current_state->stream_status[0].plane_count == 1 // single surface only
> + &&
> dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part
> == 0 // no VM
> + // Only 8 and 16 bit formats
> + &&
> dc->current_state->stream_status[0].plane_states[0]->format <=
> SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
> + &&
> dc->current_state->stream_status[0].plane_states[0]->format >=
> SURFACE_PIXEL_FORMAT_GRPH_ARGB) {
> + surface_size =
> dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch
> *
> +
> dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height
> *
> +
> (dc->current_state->stream_status[0].plane_states[0]->format >=
> SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
> +8 : 4);
> + } else {
> + // TODO: remove hard code size
> + surface_size = 128 * 1024 * 1024;
> + }
> +
> // TODO: remove hard code size
> if (surface_size < 128 * 1024 * 1024) {
> refresh_hz = div_u64((unsigned long long)
> dc->current_state->streams[0]->timing.pix_clk_100hz *
> --
> 2.25.4
>
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Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c
Ping?
On Mon, Oct 26, 2020 at 12:14 PM Alex Deucher wrote:
>
> This is required for MALL. Was accidently removed in PRS update.
>
> Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is
> enabled")
> Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")
> Signed-off-by: Alex Deucher
> ---
> .../gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index f3ae208850b0..cc2eca8c9a62 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc,
> bool enable)
> break;
> }
>
> + if (dc->current_state->stream_count == 1 // single
> display only
> + &&
> dc->current_state->stream_status[0].plane_count == 1 // single surface only
> + &&
> dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part
> == 0 // no VM
> + // Only 8 and 16 bit formats
> + &&
> dc->current_state->stream_status[0].plane_states[0]->format <=
> SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
> + &&
> dc->current_state->stream_status[0].plane_states[0]->format >=
> SURFACE_PIXEL_FORMAT_GRPH_ARGB) {
> + surface_size =
> dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch
> *
> +
> dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height
> *
> +
> (dc->current_state->stream_status[0].plane_states[0]->format >=
> SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
> +8 : 4);
> + } else {
> + // TODO: remove hard code size
> + surface_size = 128 * 1024 * 1024;
> + }
> +
> // TODO: remove hard code size
> if (surface_size < 128 * 1024 * 1024) {
> refresh_hz = div_u64((unsigned long long)
> dc->current_state->streams[0]->timing.pix_clk_100hz *
> --
> 2.25.4
>
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Re: [PATCH 1/4] drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINE
On Mon, Oct 26, 2020 at 7:06 PM Luben Tuikov wrote:
>
> Consolidating DCN seems like a good idea.
>
> Reviewed-by: Luben Tuikov
Is this for the whole series or just this patch?
Thanks!
Alex
>
> Regards,
> Luben
>
> On 2020-10-26 12:35 p.m., Alex Deucher wrote:
> > Ping again?
> >
> > On Thu, Oct 22, 2020 at 1:31 AM Alex Deucher wrote:
> >>
> >> Ping on this series?
> >>
> >> Alex
> >>
> >> On Fri, Oct 16, 2020 at 12:50 PM Alex Deucher
> >> wrote:
> >>>
> >>> No need for a separate config option at this point.
> >>>
> >>> Signed-off-by: Alex Deucher
> >>> ---
> >>> drivers/gpu/drm/amd/display/Kconfig | 8
> >>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 --
> >>> drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 --
> >>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 --
> >>> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 --
> >>> 5 files changed, 20 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/display/Kconfig
> >>> b/drivers/gpu/drm/amd/display/Kconfig
> >>> index 93cdcd1ee9ff..cf87133f88e6 100644
> >>> --- a/drivers/gpu/drm/amd/display/Kconfig
> >>> +++ b/drivers/gpu/drm/amd/display/Kconfig
> >>> @@ -17,14 +17,6 @@ config DRM_AMD_DC_DCN
> >>> help
> >>> Raven, Navi and Renoir family support for display engine
> >>>
> >>> -config DRM_AMD_DC_GREEN_SARDINE
> >>> - bool "Green Sardine support"
> >>> - default y
> >>> - depends on DRM_AMD_DC_DCN
> >>> -help
> >>> -Choose this option if you want to have
> >>> -Green Sardine support for display engine
> >>> -
> >>> config DRM_AMD_DC_DCN3_0
> >>> bool "DCN 3.0 family"
> >>> depends on DRM_AMD_DC && X86
> >>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >>> index 8a90063ac08a..2aa810d3554b 100644
> >>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >>> @@ -100,10 +100,8 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
> >>> #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
> >>> MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
> >>> #endif
> >>> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
> >>> #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
> >>> MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
> >>> -#endif
> >>> #if defined(CONFIG_DRM_AMD_DC_DCN3_01)
> >>> #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
> >>> MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
> >>> @@ -985,10 +983,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> >>> case CHIP_RAVEN:
> >>> case CHIP_RENOIR:
> >>> init_data.flags.gpu_vm_support = true;
> >>> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
> >>> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> >>> init_data.flags.disable_dmcu = true;
> >>> -#endif
> >>> break;
> >>> default:
> >>> break;
> >>> @@ -1289,10 +1285,8 @@ static int dm_dmub_sw_init(struct amdgpu_device
> >>> *adev)
> >>> case CHIP_RENOIR:
> >>> dmub_asic = DMUB_ASIC_DCN21;
> >>> fw_name_dmub = FIRMWARE_RENOIR_DMUB;
> >>> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
> >>> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> >>> fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
> >>> -#endif
> >>> break;
> >>> #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
> >>> case CHIP_SIENNA_CICHLID:
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> >>> b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> >>> index b361dc6c3489..19d97ed6beb8 100644
> >>> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> >>> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> >>> @@ -170,12 +170,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context
> >>> *ctx, struct pp_smu_funcs *p
> >>> break;
> >>> }
> >>>
> >>> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
> >>> if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
> >>> rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
> >>> break;
> >>> }
> >>> -#endif
> >>> if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
> >>> rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
> >>> break;
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >>> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >>> index ab105f26b511..419c0df08602 100644
> >>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >>> @@ -126,10 +126,8 @@ enum dce_version resource_parse_asic_id(struct
> >>>
Re: [PATCH] drm/amdgpu/display: fix indentation in defer_delay_converter_wa()
Ping? On Mon, Oct 26, 2020 at 1:50 PM Alex Deucher wrote: > > Fixes this warning: > drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c: In function > ‘defer_delay_converter_wa’: > drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c:285:2: warning: > this ‘if’ clause does not guard... [-Wmisleading-indentation] > 285 | if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 && > | ^~ > drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c:291:3: note: > ...this statement, but the latter is misleadingly indented as if it were > guarded by the ‘if’ > 291 | if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 && > | ^~ > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14 +++--- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c > b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c > index ef0f50db4907..54beda4d4e85 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c > @@ -283,15 +283,15 @@ static uint32_t defer_delay_converter_wa( > struct dc_link *link = ddc->link; > > if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 && > - !memcmp(link->dpcd_caps.branch_dev_name, > - DP_DVI_CONVERTER_ID_4, > - sizeof(link->dpcd_caps.branch_dev_name))) > + !memcmp(link->dpcd_caps.branch_dev_name, > + DP_DVI_CONVERTER_ID_4, > + sizeof(link->dpcd_caps.branch_dev_name))) > return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ? > defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY; > - if (link->dpcd_caps.branch_dev_id == > DP_BRANCH_DEVICE_ID_006037 && > - !memcmp(link->dpcd_caps.branch_dev_name, > - DP_DVI_CONVERTER_ID_5, > - sizeof(link->dpcd_caps.branch_dev_name))) > + if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 && > + !memcmp(link->dpcd_caps.branch_dev_name, > + DP_DVI_CONVERTER_ID_5, > + sizeof(link->dpcd_caps.branch_dev_name))) > return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY_1MS ? > I2C_OVER_AUX_DEFER_WA_DELAY_1MS : defer_delay; > > -- > 2.25.4 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/display: fix warnings when CONFIG_DRM_AMD_DC_DCN is not set
Properly protect the relevant code with CONFIG_DRM_AMD_DC_DCN.
Fixes: 0b08c54bb7a3 ("drm/amd/display: Fix the display corruption issue on
Navi10")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fdb1fa72061a..843080e4c39e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -893,6 +893,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
return 0;
}
+#if defined(CONFIG_DRM_AMD_DC_DCN)
static void mmhub_read_system_context(struct amdgpu_device *adev, struct
dc_phy_addr_space_config *pa_config)
{
uint64_t pt_base;
@@ -945,6 +946,7 @@ static void mmhub_read_system_context(struct amdgpu_device
*adev, struct dc_phy_
pa_config->is_hvm_enabled = 0;
}
+#endif
static int amdgpu_dm_init(struct amdgpu_device *adev)
{
@@ -952,7 +954,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
#ifdef CONFIG_DRM_AMD_DC_HDCP
struct dc_callback_init init_params;
#endif
- struct dc_phy_addr_space_config pa_config;
int r;
adev->dm.ddev = adev_to_drm(adev);
@@ -1060,6 +1061,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (adev->asic_type == CHIP_RENOIR) {
+ struct dc_phy_addr_space_config pa_config;
+
mmhub_read_system_context(adev, _config);
// Call the DC init_memory func
--
2.25.4
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Re: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
On Mon, Oct 26, 2020 at 10:43 PM Evan Quan wrote:
>
> Which can be used for S4(hibernation) support.
>
> Change-Id: I6e4962c120a3baed14cea04ed1742ff11a273d34
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/cik.c | 4 +++-
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c | 7 ---
> 2 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
> b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 03ff8bd1fee8..5442df094102 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -1336,11 +1336,13 @@ cik_asic_reset_method(struct amdgpu_device *adev)
>
> switch (adev->asic_type) {
> case CHIP_BONAIRE:
> - case CHIP_HAWAII:
> /* disable baco reset until it works */
> /* smu7_asic_get_baco_capability(adev, _reset); */
> baco_reset = false;
> break;
> + case CHIP_HAWAII:
> + baco_reset = cik_asic_supports_baco(adev);
> + break;
> default:
> baco_reset = false;
> break;
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
> index 3be40114e63d..45f608838f6e 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
> @@ -142,12 +142,12 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK,
>BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK,
>BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
> { CMD_DELAY_MS, 0, 0, 0, 20, 0 },
> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
> 0x, 0x20 },
> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
> 0x, 0x200 },
> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK,
> BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK,
> BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK,
> BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0,
> 5, 0x10 },
> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0,
> 5, 0x100 },
> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK,
> BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
> { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0x,
> 0x00 }
> };
> @@ -155,6 +155,7 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
> static const struct baco_cmd_entry clean_baco_tbl[] =
> {
> { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
> + { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
> { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
> };
The changes to this file look like a bug fix. Can you break that out
as a separate patch?
Alex
>
> --
> 2.29.0
>
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Re: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
On Tue, 27 Oct 2020 at 17:04, Sandeep wrote:
>
>
>
> On Tue, 27 Oct, 2020, 17:01 Sandeep, wrote:
>>
>>
>> On Tue, 27 Oct, 2020, 08:10 Evan Quan, wrote:
>>>
>>> Which can be used for S4(hibernation) support.
>>>
>>> Change-Id: I6e4962c120a3baed14cea04ed1742ff11a273d34
>>> Signed-off-by: Evan Quan
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/cik.c | 4 +++-
>>> drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c | 7 ---
>>> 2 files changed, 7 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
>>> b/drivers/gpu/drm/amd/amdgpu/cik.c
>>> index 03ff8bd1fee8..5442df094102 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
>>> @@ -1336,11 +1336,13 @@ cik_asic_reset_method(struct amdgpu_device *adev)
>>>
>>> switch (adev->asic_type) {
>>> case CHIP_BONAIRE:
>>> - case CHIP_HAWAII:
>>> /* disable baco reset until it works */
>>> /* smu7_asic_get_baco_capability(adev, _reset); */
>>> baco_reset = false;
>>> break;
>>> + case CHIP_HAWAII:
>>> + baco_reset = cik_asic_supports_baco(adev);
>>> + break;
>>> default:
>>> baco_reset = false;
>>> break;
>>> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> index 3be40114e63d..45f608838f6e 100644
>>> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> @@ -142,12 +142,12 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK,
>>> BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK,
>>> BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
>>> { CMD_DELAY_MS, 0, 0, 0, 20, 0 },
>>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
>>> 0x, 0x20 },
>>> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
>>> 0x, 0x200 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK,
>>> BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
>>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
>>> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL,
>>> BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0,
>>> 0x01 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK,
>>> BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
>>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0,
>>> 5, 0x10 },
>>> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0,
>>> 5, 0x100 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK,
>>> BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
>>> { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0,
>>> 0x, 0x00 }
>>> };
>>> @@ -155,6 +155,7 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
>>> static const struct baco_cmd_entry clean_baco_tbl[] =
>>> {
>>> { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
>>> + { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
>>> { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
>>> };
>>>
>>> --
>>> 2.29.0
>>
>>
>>
>> Not sure why I'm cc'd on this, I'm not a maintainer, nor does this patch
>> seem related to any patches I've contributed.
>>
>> - Sandeep
>
>
> Ok, I just saw the other email. I'll try testing the patch and see if it
> fixes the hibernation bug.
>
> - Sandeep
I tested and while suspend works correctly, hibernation is completely
broken. The system fails to resume from hibernation which is much
worse than before.
- Sandeep
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RE: [PATCH 0/3] Refine the codes about reseving bad pages.
[AMD Public Use] Series is Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: Dennis Li Sent: Tuesday, October 27, 2020 17:04 To: amd-gfx@lists.freedesktop.org; Deucher, Alexander ; Kuehling, Felix ; Zhang, Hawking ; Koenig, Christian Cc: Li, Dennis Subject: [PATCH 0/3] Refine the codes about reseving bad pages. Beside umc, others' UE interrupt callback could enter into amdgpu_ras_reset_gpu, so the first patch change to save bad pages in UMC error interrupt callback. When bad page error happens, the bad page mostly still be hold by some process, therefore driver will fail to reserve the bad page. The third patch will reserve the bad page when freeing it, make system has no chance to allocate it to other proccess. Dennis Li (3): drm/amdgpu: change to save bad pages in UMC error interrupt callback drm/amdgpu: remove redundant GPU reset drm/amdgpu: fix the issue of reserving bad pages failed drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 155 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 17 +- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 16 -- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 115 + 6 files changed, 164 insertions(+), 150 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/pm: Activate a more aggressive DPM policy while there's heavy load.
Is this really a patch for kernel.org? Seems like a hack for Stadia or
something. (And the patch description is not very good...)
This should really be made into a generic solution.
Regards
//Ernst
Den tis 27 okt. 2020 kl 07:38 skrev Li, Xin (Justin) :
> [AMD Official Use Only - Internal Distribution Only]
>
> Fix performace drop while streaming Doom
>
> Signed-off-by: Li, Xin (Justin)
> Signed-off-by: Zhao, Jiange
> ---
> drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> index eab9768029c1..5287ac4e8364 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> @@ -125,6 +125,20 @@ static int pp_hw_init(void *handle)
>
> ret = hwmgr_hw_init(hwmgr);
>
> + if (adev->pdev->device == 0x6860 && adev->pdev->revision == 0x07) {
> + long param[5];
> +
> + param[0] = 5; // busy_set_point
> + param[1] = 60; // FPS
> + param[2] = 0; // use_rlc_busy
> + param[3] = 3; // min_active_level
> + param[4] = PP_SMC_POWER_PROFILE_CUSTOM;
> +
> + mutex_lock(>smu_lock);
> + ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr,
> param, 4);
> + mutex_unlock(>smu_lock);
> + }
> +
> if (ret)
> pr_err("powerplay hw init failed\n");
>
> --
> 2.24.3 (Apple Git-128)
>
>
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Re: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
On Tue, 27 Oct, 2020, 17:01 Sandeep, wrote:
>
> On Tue, 27 Oct, 2020, 08:10 Evan Quan, wrote:
>
>> Which can be used for S4(hibernation) support.
>>
>> Change-Id: I6e4962c120a3baed14cea04ed1742ff11a273d34
>> Signed-off-by: Evan Quan
>> ---
>> drivers/gpu/drm/amd/amdgpu/cik.c | 4 +++-
>> drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c | 7 ---
>> 2 files changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
>> b/drivers/gpu/drm/amd/amdgpu/cik.c
>> index 03ff8bd1fee8..5442df094102 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
>> @@ -1336,11 +1336,13 @@ cik_asic_reset_method(struct amdgpu_device *adev)
>>
>> switch (adev->asic_type) {
>> case CHIP_BONAIRE:
>> - case CHIP_HAWAII:
>> /* disable baco reset until it works */
>> /* smu7_asic_get_baco_capability(adev, _reset); */
>> baco_reset = false;
>> break;
>> + case CHIP_HAWAII:
>> + baco_reset = cik_asic_supports_baco(adev);
>> + break;
>> default:
>> baco_reset = false;
>> break;
>> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>> index 3be40114e63d..45f608838f6e 100644
>> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>> @@ -142,12 +142,12 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
>> { CMD_READMODIFYWRITE, mmBACO_CNTL,
>> BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT,
>> 0, 0x00 },
>> { CMD_READMODIFYWRITE, mmBACO_CNTL,
>> BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT,
>> 0, 0x00 },
>> { CMD_DELAY_MS, 0, 0, 0, 20, 0 },
>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
>> 0x, 0x20 },
>> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
>> 0x, 0x200 },
>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK,
>> BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
>> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00
>> },
>> { CMD_READMODIFYWRITE, mmBACO_CNTL,
>> BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0,
>> 0x01 },
>> { CMD_READMODIFYWRITE, mmBACO_CNTL,
>> BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK,
>> 0, 5, 0x10 },
>> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK,
>> 0, 5, 0x100 },
>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK,
>> BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
>> { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0,
>> 0x, 0x00 }
>> };
>> @@ -155,6 +155,7 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
>> static const struct baco_cmd_entry clean_baco_tbl[] =
>> {
>> { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
>> + { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
>> { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
>> };
>>
>> --
>> 2.29.0
>>
>
>
> Not sure why I'm cc'd on this, I'm not a maintainer, nor does this patch
> seem related to any patches I've contributed.
>
> - Sandeep
>
Ok, I just saw the other email. I'll try testing the patch and see if it
fixes the hibernation bug.
- Sandeep
>
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Re: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
On Tue, 27 Oct, 2020, 08:10 Evan Quan, wrote:
> Which can be used for S4(hibernation) support.
>
> Change-Id: I6e4962c120a3baed14cea04ed1742ff11a273d34
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/cik.c | 4 +++-
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c | 7 ---
> 2 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
> b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 03ff8bd1fee8..5442df094102 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -1336,11 +1336,13 @@ cik_asic_reset_method(struct amdgpu_device *adev)
>
> switch (adev->asic_type) {
> case CHIP_BONAIRE:
> - case CHIP_HAWAII:
> /* disable baco reset until it works */
> /* smu7_asic_get_baco_capability(adev, _reset); */
> baco_reset = false;
> break;
> + case CHIP_HAWAII:
> + baco_reset = cik_asic_supports_baco(adev);
> + break;
> default:
> baco_reset = false;
> break;
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
> index 3be40114e63d..45f608838f6e 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
> @@ -142,12 +142,12 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
> { CMD_READMODIFYWRITE, mmBACO_CNTL,
> BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT,
> 0, 0x00 },
> { CMD_READMODIFYWRITE, mmBACO_CNTL,
> BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT,
> 0, 0x00 },
> { CMD_DELAY_MS, 0, 0, 0, 20, 0 },
> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
> 0x, 0x20 },
> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
> 0x, 0x200 },
> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK,
> BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00
> },
> { CMD_READMODIFYWRITE, mmBACO_CNTL,
> BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0,
> 0x01 },
> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK,
> BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK,
> 0, 5, 0x10 },
> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK,
> 0, 5, 0x100 },
> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK,
> BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
> { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0,
> 0x, 0x00 }
> };
> @@ -155,6 +155,7 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
> static const struct baco_cmd_entry clean_baco_tbl[] =
> {
> { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
> + { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
> { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
> };
>
> --
> 2.29.0
>
Not sure why I'm cc'd on this, I'm not a maintainer, nor does this patch
seem related to any patches I've contributed.
- Sandeep
>
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[PATCH v3 30/32] amdgpu: fix a few kernel-doc markup issues
A kernel-doc markup can't be mixed with a random comment, as it causes parsing problems. While here, change an invalid kernel-doc markup into a common comment. Signed-off-by: Mauro Carvalho Chehab --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 641c039150eb..5dbe93fe884c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -239,9 +239,11 @@ bool amdgpu_device_supports_baco(struct drm_device *dev) return amdgpu_asic_supports_baco(adev); } +/* + * VRAM access helper functions + */ + /** - * VRAM access helper functions. - * * amdgpu_device_vram_access - read/write a buffer in vram * * @adev: amdgpu_device pointer @@ -4497,7 +4499,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, bool need_emergency_restart = false; bool audio_suspended = false; - /** + /* * Special case: RAS triggered and full reset isn't supported */ need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); -- 2.26.2 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 28/32] drm: amdgpu_dm: fix a typo
dm_comressor_info -> dm_compressor_info
The kernel-doc markup is right, but the struct itself
and their references contain a typo.
Signed-off-by: Mauro Carvalho Chehab
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e2b23486ba4c..373b8481f76c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -583,7 +583,7 @@ static void amdgpu_dm_fbc_init(struct drm_connector
*connector)
{
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- struct dm_comressor_info *compressor = >dm.compressor;
+ struct dm_compressor_info *compressor = >dm.compressor;
struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
struct drm_display_mode *mode;
unsigned long max_size = 0;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 34f6369bf51f..a8a0e8cb1a11 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -86,7 +86,7 @@ struct irq_list_head {
* @bo_ptr: Pointer to the buffer object
* @gpu_addr: MMIO gpu addr
*/
-struct dm_comressor_info {
+struct dm_compressor_info {
void *cpu_addr;
struct amdgpu_bo *bo_ptr;
uint64_t gpu_addr;
@@ -148,7 +148,7 @@ struct amdgpu_dm_backlight_caps {
* @soc_bounding_box: SOC bounding box values provided by gpu_info FW
* @cached_state: Caches device atomic state for suspend/resume
* @cached_dc_state: Cached state of content streams
- * @compressor: Frame buffer compression buffer. See dm_comressor_info
+ * @compressor: Frame buffer compression buffer. See dm_compressor_info
* @force_timing_sync: set via debugfs. When set, indicates that all connected
*displays will be forced to synchronize.
*/
@@ -324,7 +324,7 @@ struct amdgpu_display_manager {
struct drm_atomic_state *cached_state;
struct dc_state *cached_dc_state;
- struct dm_comressor_info compressor;
+ struct dm_compressor_info compressor;
const struct firmware *fw_dmcu;
uint32_t dmcu_fw_version;
--
2.26.2
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[PATCH v3 22/32] drm: amdgpu: kernel-doc: update some adev parameters
Running "make htmldocs: produce lots of warnings on those files: ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'p_size' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:134: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'p_size' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:134: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' They're related to the repacement of some parameters by adev, and due to a few renamed parameters. While here, uniform the name of the parameter for it to be the same on all functions using a pointer to struct amdgpu_device. Update the kernel-doc documentation accordingly. Signed-off-by: Mauro Carvalho Chehab --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 28 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 7 +++-- 3 files changed, 20 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 37da3537ba2e..641c039150eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -705,7 +705,7 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, /** * amdgpu_invalid_rreg - dummy reg read function * - * @adev: amdgpu device pointer + * @adev: amdgpu_device pointer * @reg: offset of register * * Dummy register read function. Used for register blocks @@ -722,7 +722,7 @@ static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) /** * amdgpu_invalid_wreg - dummy reg write function * - * @adev: amdgpu device pointer + * @adev: amdgpu_device pointer * @reg: offset of register * @v: value to write to the register * @@ -739,7 +739,7 @@ static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32 /** * amdgpu_invalid_rreg64 - dummy 64 bit reg read function * - * @adev: amdgpu device pointer + * @adev: amdgpu_device pointer * @reg: offset of register * * Dummy register read function. Used for register blocks @@ -756,7 +756,7 @@ static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) /** *
Re: [PATCH 3/3] drm/amdgpu: fix the issue of reserving bad pages failed
Am 27.10.20 um 10:05 schrieb Dennis Li:
In amdgpu_ras_reset_gpu, because bad pages may not be freed,
it has high probability to reserve bad pages failed.
Change to reserve bad pages when freeing VRAM.
v2:
1. avoid allocating the drm_mm node outside of amdgpu_vram_mgr.c
2. move bad page reserving into amdgpu_ras_add_bad_pages, if vram mgr
reserve bad page failed, it will put it into pending list, otherwise
put it into processed list;
3. remove amdgpu_ras_release_bad_pages, because retired page's info has
been moved into amdgpu_vram_mgr
v3:
1. formate code style;
2. rename amdgpu_vram_reserve_scope as amdgpu_vram_reservation;
3. rename scope_pending as reservations_pending;
4. rename scope_processed as reserved_pages;
5. change to iterate over all the pending ones and try to insert them
with drm_mm_reserve_node();
v4:
1. rename amdgpu_vram_mgr_reserve_scope as
amdgpu_vram_mgr_reserve_range;
2. remove unused include "amdgpu_ras.h";
3. rename amdgpu_vram_mgr_check_and_reserve as
amdgpu_vram_mgr_do_reserve;
4. refine amdgpu_vram_mgr_reserve_range to call
amdgpu_vram_mgr_do_reserve.
Signed-off-by: Dennis Li
Signed-off-by: Wenhui Sheng
I don't know the RAS code vell enough to judge, but at least the
vram_mgr part is Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 150 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 8 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 115 ++
4 files changed, 158 insertions(+), 119 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 0f57a0003df6..84bb55ab6ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -80,6 +80,8 @@ enum amdgpu_ras_retire_page_reservation {
atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
+static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
+ uint64_t addr);
static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
uint64_t addr);
@@ -1573,10 +1575,12 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
.size = AMDGPU_GPU_PAGE_SIZE,
.flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
};
-
- if (data->last_reserved <= i)
+ ret = amdgpu_vram_mgr_query_page_status(
+ >mman.bdev.man[TTM_PL_VRAM],
+ data->bps[i].retired_page);
+ if (ret == -EBUSY)
(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
- else if (data->bps_bo[i] == NULL)
+ else if (ret == -ENOENT)
(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
}
@@ -1628,12 +1632,9 @@ static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
unsigned int new_space = old_space + pages;
unsigned int align_space = ALIGN(new_space, 512);
void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
- struct amdgpu_bo **bps_bo =
- kmalloc(align_space * sizeof(*data->bps_bo),
GFP_KERNEL);
- if (!bps || !bps_bo) {
+ if (!bps) {
kfree(bps);
- kfree(bps_bo);
return -ENOMEM;
}
@@ -1642,14 +1643,8 @@ static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
data->count * sizeof(*data->bps));
kfree(data->bps);
}
- if (data->bps_bo) {
- memcpy(bps_bo, data->bps_bo,
- data->count * sizeof(*data->bps_bo));
- kfree(data->bps_bo);
- }
data->bps = bps;
- data->bps_bo = bps_bo;
data->space_left += align_space - old_space;
return 0;
}
@@ -1661,6 +1656,7 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data *data;
int ret = 0;
+ uint32_t i;
if (!con || !con->eh_data || !bps || pages <= 0)
return 0;
@@ -1670,16 +1666,26 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
if (!data)
goto out;
- if (data->space_left <= pages)
- if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) {
+ for (i = 0; i < pages; i++) {
+ if (amdgpu_ras_check_bad_page_unlock(con,
+ bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
+ continue;
+
+ if (!data->space_left &&
+ amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
ret = -ENOMEM;
goto out;
}
- memcpy(>bps[data->count], bps,
[PATCH 10/10] drm/amd/pm: enable the rest functions of swSMU for vangogh.
This patch is to enable the rest functions of swSMU for vangogh. Signed-off-by: Xiaojian Du Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 1a8a9cf993ce..39990790ed67 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -,9 +,6 @@ static int smu_hw_init(void *handle) smu_set_gfx_cgpg(>smu, true); } - if (adev->asic_type == CHIP_VANGOGH) - return 0; - if (!smu->pm_enabled) return 0; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/10] drm/amd/pm: remove some redundant smu message mapping for vangogh
This patch is to remove some redundant smu message mapping for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 1e8558da84af..4a6d1381df16 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -302,13 +302,9 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(CCLK_DPM), \
__SMU_DUMMY_MAP(FAN_CONTROLLER), \
__SMU_DUMMY_MAP(VCN_DPM), \
- __SMU_DUMMY_MAP(FCLK_DPM), \
- __SMU_DUMMY_MAP(SOCCLK_DPM), \
- __SMU_DUMMY_MAP(MP0CLK_DPM), \
__SMU_DUMMY_MAP(LCLK_DPM), \
__SMU_DUMMY_MAP(SHUBCLK_DPM),\
__SMU_DUMMY_MAP(DCFCLK_DPM), \
- __SMU_DUMMY_MAP(GFX_DPM), \
__SMU_DUMMY_MAP(DS_DCFCLK), \
__SMU_DUMMY_MAP(S0I2), \
__SMU_DUMMY_MAP(SMU_LOW_POWER), \
--
2.17.1
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[PATCH 08/10] drm/amd/pm: add one new function to get 32 bit feature mask for vangogh
This patch is to add one new function to get 32 bit feature mask for
vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 55 +++---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 4 ++
2 files changed, 54 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 92b2ea4c197b..dc28f22aeb38 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -346,6 +346,43 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
return ret;
}
+int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
+ uint32_t *feature_mask,
+ uint32_t num)
+{
+ uint32_t feature_mask_en_low = 0;
+ uint32_t feature_mask_en_high = 0;
+ struct smu_feature *feature = >smu_feature;
+ int ret = 0;
+
+ if (!feature_mask || num < 2)
+ return -EINVAL;
+
+ if (bitmap_empty(feature->enabled, feature->feature_num)) {
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GetEnabledSmuFeatures, 0,
+
_mask_en_low);
+
+ if (ret)
+ return ret;
+
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GetEnabledSmuFeatures, 1,
+
_mask_en_high);
+
+ if (ret)
+ return ret;
+
+ feature_mask[0] = feature_mask_en_low;
+ feature_mask[1] = feature_mask_en_high;
+
+ } else {
+ bitmap_copy((unsigned long *)feature_mask, feature->enabled,
+feature->feature_num);
+ }
+
+ return ret;
+
+}
+
int smu_cmn_feature_update_enable_state(struct smu_context *smu,
uint64_t feature_mask,
bool enabled)
@@ -437,11 +474,19 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context
*smu,
size_t size = 0;
int ret = 0, i;
- ret = smu_cmn_get_enabled_mask(smu,
- feature_mask,
- 2);
- if (ret)
- return 0;
+ if (!smu->is_apu) {
+ ret = smu_cmn_get_enabled_mask(smu,
+ feature_mask,
+ 2);
+ if (ret)
+ return 0;
+ } else {
+ ret = smu_cmn_get_enabled_32_bits_mask(smu,
+ feature_mask,
+ 2);
+ if (ret)
+ return 0;
+ }
size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
feature_mask[1], feature_mask[0]);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index ab577be23c15..01e825d83d8d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -52,6 +52,10 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
uint32_t *feature_mask,
uint32_t num);
+int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
+ uint32_t *feature_mask,
+ uint32_t num);
+
int smu_cmn_feature_update_enable_state(struct smu_context *smu,
uint64_t feature_mask,
bool enabled);
--
2.17.1
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[PATCH 06/10] drm/amd/pm: set the initial value of pm info to zero
This patch is to set the initial value of pm info to zero.
The "value64" is ported to the hwmon and debugfs node, it is a uint64 type.
When it is used for NV10/VEGA10/VEGA20, its word size is appropriate,
because NV10/VEGA10/VEGA20 has a 64bit smu feature mask, which is separated to
high 32bit and low 32bit.
But some asic has only 32bit smu feature mask,and this 32bit mask will fill the
low 32bit of "value64".
So if this "value64" is not initialized to zero, the high 32bit will be
filled by a meaningless value, when the whole "value64" is ported to the
"SMC Feature Mask" in the "amdgpu_pm_info" on some specific asic, it
will be a wrong value.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 89632ee88ae2..080af05724ed 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -3464,7 +3464,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device
*adev)
{
uint32_t value;
- uint64_t value64;
+ uint64_t value64 = 0;
uint32_t query = 0;
int size;
--
2.17.1
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[PATCH 05/10] drm/amd/pm: update the smu v11.5 driver interface header for vangogh
This patch is to update the smu v11.5 driver interface header for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
.../drm/amd/pm/inc/smu11_driver_if_vangogh.h | 70 +--
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h| 2 +-
2 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
index 20f8c6f460b8..8f438c80132e 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
@@ -100,13 +100,13 @@ typedef struct {
DpmActivityMonitorCoeffExt_t
DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
} CustomDpmSettings_t;
-#define NUM_DCFCLK_DPM_LEVELS 6
-#define NUM_DISPCLK_DPM_LEVELS 6
-#define NUM_DPPCLK_DPM_LEVELS 6
-#define NUM_SOCCLK_DPM_LEVELS 8
-#define NUM_ISPICLK_DPM_LEVELS 6
-#define NUM_ISPXCLK_DPM_LEVELS 6
-#define NUM_VCN_DPM_LEVELS 8
+#define NUM_DCFCLK_DPM_LEVELS 7
+#define NUM_DISPCLK_DPM_LEVELS 7
+#define NUM_DPPCLK_DPM_LEVELS 7
+#define NUM_SOCCLK_DPM_LEVELS 7
+#define NUM_ISPICLK_DPM_LEVELS 7
+#define NUM_ISPXCLK_DPM_LEVELS 7
+#define NUM_VCN_DPM_LEVELS 5
#define NUM_FCLK_DPM_LEVELS 4
#define NUM_SOC_VOLTAGE_LEVELS 8
@@ -160,30 +160,30 @@ typedef struct {
#define THROTTLER_STATUS_BIT_TDC_CVIP 10
typedef struct {
- uint16_t AverageGfxclkFrequency; //[MHz]
- uint16_t AverageSocclkFrequency; //[MHz]
- uint16_t AverageVclkFrequency; //[MHz]
- uint16_t AverageDclkFrequency; //[MHz]
- uint16_t AverageMemclkFrequency; //[MHz]
+ uint16_t GfxclkFrequency; //[MHz]
+ uint16_t SocclkFrequency; //[MHz]
+ uint16_t VclkFrequency;//[MHz]
+ uint16_t DclkFrequency;//[MHz]
+ uint16_t MemclkFrequency; //[MHz]
uint16_t spare;
- uint16_t AverageGfxActivity; //[centi]
- uint16_t AverageUvdActivity; //[centi]
+ uint16_t GfxActivity; //[centi]
+ uint16_t UvdActivity; //[centi]
- uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
- uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
- uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
- uint16_t CurrentSocketPower; //[mW]
+ uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC,
VDDCR_GFX
+ uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC,
VDDCR_GFX
+ uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC,
VDDCR_GFX
+ uint16_t CurrentSocketPower; //[mW]
- //3rd party tools in Windows need this info in the case of APUs
- uint16_t CoreFrequency[8]; //[MHz]
- uint16_t CorePower[8]; //[mW]
- uint16_t CoreTemperature[8]; //[centi-Celsius]
- uint16_t L3Frequency[2]; //[MHz]
- uint16_t L3Temperature[2]; //[centi-Celsius]
+ //3rd party tools in Windows need info in the case of APUs
+ uint16_t CoreFrequency[8]; //[MHz]
+ uint16_t CorePower[8]; //[mW]
+ uint16_t CoreTemperature[8]; //[centi-Celsius]
+ uint16_t L3Frequency[2]; //[MHz]
+ uint16_t L3Temperature[2]; //[centi-Celsius]
- uint16_t GfxTemperature; //[centi-Celsius]
- uint16_t SocTemperature; //[centi-Celsius]
+ uint16_t GfxTemperature; //[centi-Celsius]
+ uint16_t SocTemperature; //[centi-Celsius]
uint16_t EdgeTemperature;
uint16_t ThrottlerStatus;
} SmuMetrics_t;
@@ -197,15 +197,15 @@ typedef struct {
#define WORKLOAD_PPLIB_CUSTOM_BIT 5
#define WORKLOAD_PPLIB_COUNT 6
-#define TABLE_BIOS_IF 0// Called by BIOS
-#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
-#define TABLE_CUSTOM_DPM 2 // Called by Driver
-#define TABLE_SPARE1 3
-#define TABLE_DPMCLOCKS 4// Called by Driver
-#define TABLE_MOMENTARY_PM 5 // Called by Tools
-#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
-#define TABLE_SMU_METRICS 7 // Called by Driver
-#define TABLE_COUNT 8
+#define TABLE_BIOS_IF0 // Called by BIOS
+#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
+#define TABLE_CUSTOM_DPM 2 // Called by Driver
+#define TABLE_SPARE1 3
+#define TABLE_DPMCLOCKS 4 // Called by Driver
+#define TABLE_SPARE2 5 // Called by Tools
+#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS7 // Called by Driver
+#define TABLE_COUNT 8
//ISP tile definitions
typedef enum {
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index b5f0cc7829f0..2efa0dd3719f 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -32,7 +32,7 @@
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
-#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x01
+#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
[PATCH 03/10] drm/amd/pm: add new smc message mapping for vangogh
This patch is to add new smc message mapping for vangogh. Signed-off-by: Xiaojian Du Reviewed-by: Huang Rui Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/smu_types.h | 24 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h index c8eee2a427d0..1e8558da84af 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h @@ -184,6 +184,30 @@ __SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \ __SMU_DUMMY_MAP(PowerUpCvip),\ __SMU_DUMMY_MAP(PowerDownCvip), \ + __SMU_DUMMY_MAP(EnableGfxOff), \ + __SMU_DUMMY_MAP(SetSoftMinGfxclk), \ + __SMU_DUMMY_MAP(SetSoftMinFclk), \ + __SMU_DUMMY_MAP(GetThermalLimit),\ + __SMU_DUMMY_MAP(GetCurrentTemperature), \ + __SMU_DUMMY_MAP(GetCurrentPower),\ + __SMU_DUMMY_MAP(GetCurrentVoltage), \ + __SMU_DUMMY_MAP(GetCurrentCurrent), \ + __SMU_DUMMY_MAP(GetAverageCpuActivity), \ + __SMU_DUMMY_MAP(GetAverageGfxActivity), \ + __SMU_DUMMY_MAP(GetAveragePower),\ + __SMU_DUMMY_MAP(GetAverageTemperature), \ + __SMU_DUMMY_MAP(SetAveragePowerTimeConstant),\ + __SMU_DUMMY_MAP(SetAverageActivityTimeConstant), \ + __SMU_DUMMY_MAP(SetAverageTemperatureTimeConstant), \ + __SMU_DUMMY_MAP(SetMitigationEndHysteresis), \ + __SMU_DUMMY_MAP(GetCurrentFreq), \ + __SMU_DUMMY_MAP(SetReducedPptLimit), \ + __SMU_DUMMY_MAP(SetReducedThermalLimit), \ + __SMU_DUMMY_MAP(DramLogSetDramAddr), \ + __SMU_DUMMY_MAP(StartDramLogging), \ + __SMU_DUMMY_MAP(StopDramLogging),\ + __SMU_DUMMY_MAP(SetSoftMinCclk), \ + __SMU_DUMMY_MAP(SetSoftMaxCclk), \ __SMU_DUMMY_MAP(SetGpoFeaturePMask), \ #undef __SMU_DUMMY_MAP -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh
This patch is to update the smu v11.5 smc header for vangogh. Signed-off-by: Xiaojian Du Reviewed-by: Huang Rui Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 114 +++ 1 file changed, 68 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h index 55c1b151a68d..1ada0eb64663 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h @@ -32,55 +32,77 @@ #define PPSMC_Result_CmdRejectedBusy 0xFC // Message Definitions: -#define PPSMC_MSG_TestMessage 0x1 -#define PPSMC_MSG_GetSmuVersion 0x2 -#define PPSMC_MSG_GetDriverIfVersion 0x3 -#define PPSMC_MSG_EnableGfxOff 0x4 -#define PPSMC_MSG_DisableGfxOff 0x5 -#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default -#define PPSMC_MSG_PowerUpIspByTile 0x7 -#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default -#define PPSMC_MSG_PowerUpVcn 0x9 -#define PPSMC_MSG_spare 0xA -#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display -#define PPSMC_MSG_SetMinVideoGfxclkFreq0xC //Sets SoftMin for GFXCLK. Arg is in MHz -#define PPSMC_MSG_ActiveProcessNotify 0xD -#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE -#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF -#define PPSMC_MSG_SetDriverDramAddrHigh 0x10 -#define PPSMC_MSG_SetDriverDramAddrLow 0x11 -#define PPSMC_MSG_TransferTableSmu2Dram 0x12 -#define PPSMC_MSG_TransferTableDram2Smu 0x13 -#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR -#define PPSMC_MSG_GetEnabledSmuFeatures 0x15 -#define PPSMC_MSG_spare1 0x16 -#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17 -#define PPSMC_MSG_SetMinVideoFclkFreq 0x18 -#define PPSMC_MSG_SetSoftMinVcn 0x19 -#define PPSMC_MSG_EnablePostCode 0x1A -#define PPSMC_MSG_GetGfxclkFrequency 0x1B -#define PPSMC_MSG_GetFclkFrequency 0x1C -#define PPSMC_MSG_AllowGfxOff 0x1D -#define PPSMC_MSG_DisallowGfxOff 0x1E -#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F -#define PPSMC_MSG_SetHardMinGfxClk 0x20 -#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21 -#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22 -#define PPSMC_MSG_SetSoftMaxVcn 0x23 -#define PPSMC_MSG_GpuChangeState 0x24 //FIXME AHOLLA - check how to do for VGM -#define PPSMC_MSG_SetPowerLimitPercentage 0x25 -#define PPSMC_MSG_PowerDownJpeg 0x26 -#define PPSMC_MSG_PowerUpJpeg 0x27 -#define PPSMC_MSG_SetHardMinFclkByFreq 0x28 -#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29 -#define PPSMC_MSG_PowerUpCvip 0x2A -#define PPSMC_MSG_PowerDownCvip 0x2B -#define PPSMC_Message_Count 0x2C +#define PPSMC_MSG_TestMessage 0x1 +#define PPSMC_MSG_GetSmuVersion0x2 +#define PPSMC_MSG_GetDriverIfVersion 0x3 +#define PPSMC_MSG_EnableGfxOff 0x4 +#define PPSMC_MSG_DisableGfxOff0x5 +#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default +#define PPSMC_MSG_PowerUpIspByTile 0x7 +#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default +#define PPSMC_MSG_PowerUpVcn 0x9 +#define PPSMC_MSG_spare0xA +#define PPSMC_MSG_SetHardMinVcn0xB // For wireless display +#define PPSMC_MSG_SetSoftMinGfxclk 0xC //Sets SoftMin for GFXCLK. Arg is in MHz +#define PPSMC_MSG_ActiveProcessNotify 0xD +#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE +#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF +#define PPSMC_MSG_SetDriverDramAddrHigh0x10 +#define PPSMC_MSG_SetDriverDramAddrLow 0x11 +#define PPSMC_MSG_TransferTableSmu2Dram0x12 +#define PPSMC_MSG_TransferTableDram2Smu0x13 +#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR +#define PPSMC_MSG_GetEnabledSmuFeatures0x15 +#define PPSMC_MSG_spare1 0x16 +#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17 +#define PPSMC_MSG_SetSoftMinFclk 0x18 //Used to be PPSMC_MSG_SetMinVideoFclkFreq +#define PPSMC_MSG_SetSoftMinVcn0x19 +#define PPSMC_MSG_EnablePostCode 0x1A +#define PPSMC_MSG_GetGfxclkFrequency 0x1B +#define PPSMC_MSG_GetFclkFrequency 0x1C +#define PPSMC_MSG_AllowGfxOff 0x1D +#define PPSMC_MSG_DisallowGfxOff 0x1E +#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F +#define PPSMC_MSG_SetHardMinGfxClk 0x20 +#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21 +#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22 +#define PPSMC_MSG_SetSoftMaxVcn0x23 +#define PPSMC_MSG_spare2 0x24
[PATCH 02/10] drm/amd/pm: update the smu v11.5 firmware header for vangogh
This patch is to update the smu v11.5 firmware header for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
index abf13abd3919..99a406984135 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
@@ -89,7 +89,7 @@
#define FEATURE_SOC_VOLTAGE_MON_BIT 55
#define FEATURE_ATHUB_PG_BIT 56
#define FEATURE_ECO_DEEPCSTATE_BIT57
-#define FEATURE_CC6 58
+#define FEATURE_CC6_BIT 58
#define NUM_FEATURES 59
typedef struct {
--
2.17.1
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[PATCH 04/10] drm/amd/pm: add UMD Pstate Msg Parameters for vangogh temporarily
This patch is to add UMD Pstate Msg Parameters for vangogh temporarily, the values refer to renoir. Signed-off-by: Xiaojian Du Reviewed-by: Huang Rui Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h index d8696e2274c4..8756766296cd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h @@ -27,4 +27,9 @@ extern void vangogh_set_ppt_funcs(struct smu_context *smu); +/* UMD PState Vangogh Msg Parameters in MHz */ +#define VANGOGH_UMD_PSTATE_GFXCLK 700 +#define VANGOGH_UMD_PSTATE_SOCCLK 678 +#define VANGOGH_UMD_PSTATE_FCLK 800 + #endif -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/10] drm/amd/pm: add some swSMU functions for vangogh.
This patch is to add some swSMU functions for vangogh, to support the
sensor info on "hwmon" and pm info.
Signed-off-by: Xiaojian Du
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 411 ++
1 file changed, 338 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 145712a24b80..83a1b0a04eb1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -52,53 +52,72 @@
FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)| \
FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
- FEATURE_MASK(FEATURE_GFX_DPM_BIT)| \
- FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \
- FEATURE_MASK(FEATURE_A55_DPM_BIT)| \
- FEATURE_MASK(FEATURE_CVIP_DSP_DPM_BIT))
+ FEATURE_MASK(FEATURE_GFX_DPM_BIT))
static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
- MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,
1),
- MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion,
1),
- MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion,
1),
- MSG_MAP(AllowGfxOff,PPSMC_MSG_EnableGfxOff,
1),
- MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff,
1),
- MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile,
1),
- MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile,
1),
- MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn,
1),
- MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn,
1),
- MSG_MAP(Spare, PPSMC_MSG_spare,
1),
- MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
1),
- MSG_MAP(SetMinVideoGfxclkFreq,
PPSMC_MSG_SetMinVideoGfxclkFreq,1),
- MSG_MAP(ActiveProcessNotify,PPSMC_MSG_ActiveProcessNotify,
1),
- MSG_MAP(SetHardMinIspiclkByFreq,
PPSMC_MSG_SetHardMinIspiclkByFreq, 1),
- MSG_MAP(SetHardMinIspxclkByFreq,
PPSMC_MSG_SetHardMinIspxclkByFreq, 1),
- MSG_MAP(SetDriverDramAddrHigh,
PPSMC_MSG_SetDriverDramAddrHigh,1),
- MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,
1),
- MSG_MAP(TransferTableSmu2Dram,
PPSMC_MSG_TransferTableSmu2Dram,1),
- MSG_MAP(TransferTableDram2Smu,
PPSMC_MSG_TransferTableDram2Smu,1),
- MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset,
1),
- MSG_MAP(GetEnabledSmuFeatures,
PPSMC_MSG_GetEnabledSmuFeatures,1),
- MSG_MAP(Spare1, PPSMC_MSG_spare1,
1),
- MSG_MAP(SetHardMinSocclkByFreq,
PPSMC_MSG_SetHardMinSocclkByFreq, 1),
- MSG_MAP(SetMinVideoFclkFreq,PPSMC_MSG_SetMinVideoFclkFreq,
1),
- MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn,
1),
- MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode,
1),
- MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency,
1),
- MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency,
1),
- MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk,
1),
- MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk,
1),
- MSG_MAP(SetSoftMaxSocclkByFreq,
PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
- MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq,
1),
- MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn,
1),
- MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState,
1),
- MSG_MAP(SetPowerLimitPercentage,
PPSMC_MSG_SetPowerLimitPercentage, 1),
- MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg,
1),
- MSG_MAP(PowerUpJpeg,PPSMC_MSG_PowerUpJpeg,
1),
- MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq,
1),
- MSG_MAP(SetSoftMinSocclkByFreq,
PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
- MSG_MAP(PowerUpCvip,PPSMC_MSG_PowerUpCvip,
1),
- MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip,
1),
+ MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,
0),
+ MSG_MAP(GetSmuVersion,
[PATCH 2/3] drm/amdgpu: remove redundant GPU reset
Because bad pages saving has been moved to UMC error interrupt callback,
which will trigger a new GPU reset after saving.
Signed-off-by: Dennis Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h| 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 16
2 files changed, 1 insertion(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 0926c0770d7a..7c39d706e6d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -33,7 +33,6 @@
#define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0)
#define AMDGPU_RAS_FLAG_INIT_NEED_RESET(0x1 << 1)
-#define AMDGPU_RAS_FLAG_SKIP_BAD_PAGE_RESV (0x1 << 2)
enum amdgpu_ras_block {
AMDGPU_RAS_BLOCK__UMC = 0,
@@ -513,14 +512,7 @@ static inline int amdgpu_ras_reset_gpu(struct
amdgpu_device *adev)
{
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
- /*
-* Save bad page to eeprom before gpu reset, i2c may be unstable
-* in gpu reset.
-*
-* Also, exclude the case when ras recovery issuer is
-* eeprom page write itself.
-*/
- if (!(ras->flags & AMDGPU_RAS_FLAG_SKIP_BAD_PAGE_RESV) && in_task())
+ if (in_task())
amdgpu_ras_reserve_bad_pages(adev);
if (atomic_cmpxchg(>in_recovery, 0, 1) == 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 695bcfc5c983..c3710c591b55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -479,7 +479,6 @@ int amdgpu_ras_eeprom_process_recods(struct
amdgpu_ras_eeprom_control *control,
int i, ret = 0;
struct i2c_msg *msgs, *msg;
unsigned char *buffs, *buff;
- bool sched_ras_recovery = false;
struct eeprom_table_record *record;
struct amdgpu_device *adev = to_amdgpu_device(control);
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
@@ -517,7 +516,6 @@ int amdgpu_ras_eeprom_process_recods(struct
amdgpu_ras_eeprom_control *control,
"Saved bad pages(%d) reaches threshold value(%d).\n",
control->num_recs + num, ras->bad_page_cnt_threshold);
control->tbl_hdr.header = EEPROM_TABLE_HDR_BAD;
- sched_ras_recovery = true;
}
/* In case of overflow just start from beginning to not lose newest
records */
@@ -603,20 +601,6 @@ int amdgpu_ras_eeprom_process_recods(struct
amdgpu_ras_eeprom_control *control,
__update_tbl_checksum(control, records, num, old_hdr_byte_sum);
__update_table_header(control, buffs);
-
- if (sched_ras_recovery) {
- /*
-* Before scheduling ras recovery, assert the related
-* flag first, which shall bypass common bad page
-* reservation execution in amdgpu_ras_reset_gpu.
-*/
- amdgpu_ras_get_context(adev)->flags |=
- AMDGPU_RAS_FLAG_SKIP_BAD_PAGE_RESV;
-
- dev_warn(adev->dev, "Conduct ras recovery due to bad "
- "page threshold reached.\n");
- amdgpu_ras_reset_gpu(adev);
- }
} else if (!__validate_tbl_checksum(control, records, num)) {
DRM_WARN("EEPROM Table checksum mismatch!");
/* TODO Uncomment when EEPROM read/write is relliable */
--
2.17.1
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[PATCH 3/3] drm/amdgpu: fix the issue of reserving bad pages failed
In amdgpu_ras_reset_gpu, because bad pages may not be freed,
it has high probability to reserve bad pages failed.
Change to reserve bad pages when freeing VRAM.
v2:
1. avoid allocating the drm_mm node outside of amdgpu_vram_mgr.c
2. move bad page reserving into amdgpu_ras_add_bad_pages, if vram mgr
reserve bad page failed, it will put it into pending list, otherwise
put it into processed list;
3. remove amdgpu_ras_release_bad_pages, because retired page's info has
been moved into amdgpu_vram_mgr
v3:
1. formate code style;
2. rename amdgpu_vram_reserve_scope as amdgpu_vram_reservation;
3. rename scope_pending as reservations_pending;
4. rename scope_processed as reserved_pages;
5. change to iterate over all the pending ones and try to insert them
with drm_mm_reserve_node();
v4:
1. rename amdgpu_vram_mgr_reserve_scope as
amdgpu_vram_mgr_reserve_range;
2. remove unused include "amdgpu_ras.h";
3. rename amdgpu_vram_mgr_check_and_reserve as
amdgpu_vram_mgr_do_reserve;
4. refine amdgpu_vram_mgr_reserve_range to call
amdgpu_vram_mgr_do_reserve.
Signed-off-by: Dennis Li
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 150 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 8 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 115 ++
4 files changed, 158 insertions(+), 119 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 0f57a0003df6..84bb55ab6ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -80,6 +80,8 @@ enum amdgpu_ras_retire_page_reservation {
atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
+static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
+ uint64_t addr);
static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
uint64_t addr);
@@ -1573,10 +1575,12 @@ static int amdgpu_ras_badpages_read(struct
amdgpu_device *adev,
.size = AMDGPU_GPU_PAGE_SIZE,
.flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
};
-
- if (data->last_reserved <= i)
+ ret = amdgpu_vram_mgr_query_page_status(
+ >mman.bdev.man[TTM_PL_VRAM],
+ data->bps[i].retired_page);
+ if (ret == -EBUSY)
(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
- else if (data->bps_bo[i] == NULL)
+ else if (ret == -ENOENT)
(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
}
@@ -1628,12 +1632,9 @@ static int amdgpu_ras_realloc_eh_data_space(struct
amdgpu_device *adev,
unsigned int new_space = old_space + pages;
unsigned int align_space = ALIGN(new_space, 512);
void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
- struct amdgpu_bo **bps_bo =
- kmalloc(align_space * sizeof(*data->bps_bo),
GFP_KERNEL);
- if (!bps || !bps_bo) {
+ if (!bps) {
kfree(bps);
- kfree(bps_bo);
return -ENOMEM;
}
@@ -1642,14 +1643,8 @@ static int amdgpu_ras_realloc_eh_data_space(struct
amdgpu_device *adev,
data->count * sizeof(*data->bps));
kfree(data->bps);
}
- if (data->bps_bo) {
- memcpy(bps_bo, data->bps_bo,
- data->count * sizeof(*data->bps_bo));
- kfree(data->bps_bo);
- }
data->bps = bps;
- data->bps_bo = bps_bo;
data->space_left += align_space - old_space;
return 0;
}
@@ -1661,6 +1656,7 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data *data;
int ret = 0;
+ uint32_t i;
if (!con || !con->eh_data || !bps || pages <= 0)
return 0;
@@ -1670,16 +1666,26 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
if (!data)
goto out;
- if (data->space_left <= pages)
- if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) {
+ for (i = 0; i < pages; i++) {
+ if (amdgpu_ras_check_bad_page_unlock(con,
+ bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
+ continue;
+
+ if (!data->space_left &&
+ amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
ret = -ENOMEM;
goto out;
}
- memcpy(>bps[data->count], bps, pages * sizeof(*data->bps));
- data->count += pages;
- data->space_left -= pages;
+ amdgpu_vram_mgr_reserve_range(
+
[PATCH 1/3] drm/amdgpu: change to save bad pages in UMC error interrupt callback
Instead of saving bad pages in amdgpu_ras_reset_gpu, it will reduce
the unnecessary calling of amdgpu_ras_save_bad_pages.
Signed-off-by: Dennis Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 7 ---
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 7f79d25fbccc..0f57a0003df6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1690,7 +1690,7 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
* write error record array to eeprom, the function should be
* protected by recovery_lock
*/
-static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
+int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data *data;
@@ -1863,9 +1863,6 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device
*adev)
data->last_reserved = i + 1;
bo = NULL;
}
-
- /* continue to save bad pages to eeprom even reesrve_vram fails */
- ret = amdgpu_ras_save_bad_pages(adev);
out:
mutex_unlock(>recovery_lock);
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 6b8d7bb83bb3..0926c0770d7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -506,6 +506,7 @@ bool amdgpu_ras_check_err_threshold(struct amdgpu_device
*adev);
int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
struct eeprom_table_record *bps, int pages);
+int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev);
int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev);
static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 262baf0f61ea..a2975c8092a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -126,10 +126,11 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device
*adev,
err_data->ue_count);
if ((amdgpu_bad_page_threshold != 0) &&
- err_data->err_addr_cnt &&
+ err_data->err_addr_cnt) {
amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
- err_data->err_addr_cnt))
- dev_warn(adev->dev, "Failed to add ras bad page!\n");
+ err_data->err_addr_cnt);
+ amdgpu_ras_save_bad_pages(adev);
+ }
amdgpu_ras_reset_gpu(adev);
}
--
2.17.1
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[PATCH 0/3] Refine the codes about reseving bad pages.
Beside umc, others' UE interrupt callback could enter into amdgpu_ras_reset_gpu, so the first patch change to save bad pages in UMC error interrupt callback. When bad page error happens, the bad page mostly still be hold by some process, therefore driver will fail to reserve the bad page. The third patch will reserve the bad page when freeing it, make system has no chance to allocate it to other proccess. Dennis Li (3): drm/amdgpu: change to save bad pages in UMC error interrupt callback drm/amdgpu: remove redundant GPU reset drm/amdgpu: fix the issue of reserving bad pages failed drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 155 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 17 +- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 16 -- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 115 + 6 files changed, 164 insertions(+), 150 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/pm: Activate a more aggressive DPM policy while there's heavy load.
[AMD Official Use Only - Internal Distribution Only]
Fix performace drop while streaming Doom
Signed-off-by: Li, Xin (Justin) mailto:xin2...@amd.com>>
Signed-off-by: Zhao, Jiange mailto:jiange.z...@amd.com>>
---
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index eab9768029c1..5287ac4e8364 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -125,6 +125,20 @@ static int pp_hw_init(void *handle)
ret = hwmgr_hw_init(hwmgr);
+ if (adev->pdev->device == 0x6860 && adev->pdev->revision == 0x07) {
+ long param[5];
+
+ param[0] = 5; // busy_set_point
+ param[1] = 60; // FPS
+ param[2] = 0; // use_rlc_busy
+ param[3] = 3; // min_active_level
+ param[4] = PP_SMC_POWER_PROFILE_CUSTOM;
+
+ mutex_lock(>smu_lock);
+ ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, param,
4);
+ mutex_unlock(>smu_lock);
+ }
+
if (ret)
pr_err("powerplay hw init failed\n");
--
2.24.3 (Apple Git-128)
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[PATCH] drm/amd/amdgpu: Add checksun check for pf2vf message
[AMD Official Use Only - Internal Distribution Only]
Add checksum checking for pf2vf message
Signed-off-by: Li, Xin (Justin) mailto:xin2...@amd.com>>
Signed-off-by: Zhou, Tiecheng
mailto:tiecheng.z...@amd.com>>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 836d784456e5..bfc74533b5ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -450,12 +450,11 @@ static int amdgpu_virt_read_pf2vf_data(struct
amdgpu_device *adev)
((struct amdgim_pf2vf_info_v1
*)pf2vf_info)->feature_flags;
break;
case 2:
- /* TODO: missing key, need to add it later */
checksum = ((struct amd_sriov_msg_pf2vf_info
*)pf2vf_info)->checksum;
checkval = amd_sriov_msg_checksum(
adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
- 0, checksum);
- if (checksum != checkval) {
+ adev->virt.fw_reserve.checksum_key, checksum);
+ if (checksum != 0 && checksum != checkval) {
DRM_ERROR("invalid pf2vf message\n");
return -EINVAL;
}
--
2.24.3 (Apple Git-128)
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