Re: [PATCH] drm/amd/amdgpu: Add checksun check for pf2vf message
[AMD Official Use Only - Internal Distribution Only]
Any updates on this patch?
Best Regards,
Li, Xin (Justin)
From: Li, Xin (Justin)
Date: Tuesday, October 27, 2020 at 14:36
To: amd-gfx@lists.freedesktop.org , Li, Xin
(Justin) , Zhou, Tiecheng
Subject: [PATCH] drm/amd/amdgpu: Add checksun check for pf2vf message
[AMD Official Use Only - Internal Distribution Only]
Add checksum checking for pf2vf message
Signed-off-by: Li, Xin (Justin) mailto:xin2...@amd.com>>
Signed-off-by: Zhou, Tiecheng
mailto:tiecheng.z...@amd.com>>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 836d784456e5..bfc74533b5ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -450,12 +450,11 @@ static int amdgpu_virt_read_pf2vf_data(struct
amdgpu_device *adev)
((struct amdgim_pf2vf_info_v1
*)pf2vf_info)->feature_flags;
break;
case 2:
- /* TODO: missing key, need to add it later */
checksum = ((struct amd_sriov_msg_pf2vf_info
*)pf2vf_info)->checksum;
checkval = amd_sriov_msg_checksum(
adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
- 0, checksum);
- if (checksum != checkval) {
+ adev->virt.fw_reserve.checksum_key, checksum);
+ if (checksum != 0 && checksum != checkval) {
DRM_ERROR("invalid pf2vf message\n");
return -EINVAL;
}
--
2.24.3 (Apple Git-128)
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[PATCH] drm/amd/display: Tune min clk values for MPO for RV
[Why]
Incorrect values were resulting in flash lines
when MPO was enabled and system was left idle.
[How]
Increase min clk values only when MPO is enabled
and display is active to not affect S3 power.
Signed-off-by: Pratik Vishwakarma
---
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c| 35 +--
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index e133edc587d3..c388a003956b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -187,6 +187,22 @@ static void ramp_up_dispclk_with_dpp(
clk_mgr->base.clks.max_supported_dppclk_khz =
new_clocks->max_supported_dppclk_khz;
}
+static bool is_mpo_enabled(struct dc_state *context)
+{
+ int i;
+
+ for (i = 0; i < context->stream_count; i++) {
+ if (context->stream_status[i].plane_count > 1) {
+ /*
+* No need to check for all streams as MPO
+* can be enabled on single stream only for RV.
+*/
+ return true;
+ }
+ }
+ return false;
+}
+
static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
@@ -284,9 +300,22 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
if (pp_smu->set_hard_min_fclk_by_freq &&
pp_smu->set_hard_min_dcfclk_by_freq &&
pp_smu->set_min_deep_sleep_dcfclk) {
- pp_smu->set_hard_min_fclk_by_freq(_smu->pp_smu,
new_clocks->fclk_khz / 1000);
- pp_smu->set_hard_min_dcfclk_by_freq(_smu->pp_smu,
new_clocks->dcfclk_khz / 1000);
- pp_smu->set_min_deep_sleep_dcfclk(_smu->pp_smu,
(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+ // Only increase clocks when display is active and MPO
is enabled
+ if (display_count && is_mpo_enabled(context)) {
+
pp_smu->set_hard_min_fclk_by_freq(_smu->pp_smu,
+ ((new_clocks->fclk_khz / 1000)
* 101) / 100);
+
pp_smu->set_hard_min_dcfclk_by_freq(_smu->pp_smu,
+ ((new_clocks->dcfclk_khz /
1000) * 101) / 100);
+
pp_smu->set_min_deep_sleep_dcfclk(_smu->pp_smu,
+
(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+ } else {
+
pp_smu->set_hard_min_fclk_by_freq(_smu->pp_smu,
+ new_clocks->fclk_khz / 1000);
+
pp_smu->set_hard_min_dcfclk_by_freq(_smu->pp_smu,
+ new_clocks->dcfclk_khz / 1000);
+
pp_smu->set_min_deep_sleep_dcfclk(_smu->pp_smu,
+
(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+ }
}
}
}
--
2.17.1
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[PATCH v4 06/11] drm/amd/display: Convert tiling_flags to modifiers.
This way the modifier path gets exercised all the time, improving
testing. Furthermore, for modifiers this is required as getfb2
will always return the modifier if the driver sets allow_fb_modifiers.
This only triggers once allow_fb_modifiers is set.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 123
1 file changed, 123 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 1a2664c3fc26..89c3ead36501 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -38,6 +38,7 @@
#include
#include
#include
+#include
#include
static void amdgpu_display_flip_callback(struct dma_fence *f,
@@ -541,6 +542,121 @@ uint32_t amdgpu_display_supported_domains(struct
amdgpu_device *adev,
return domain;
}
+static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
+{
+ struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
+ uint64_t modifier = 0;
+
+ if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags,
SWIZZLE_MODE)) {
+ modifier = DRM_FORMAT_MOD_LINEAR;
+ } else {
+ int swizzle = AMDGPU_TILING_GET(afb->tiling_flags,
SWIZZLE_MODE);
+ bool has_xor = swizzle >= 16;
+ int block_size_bits;
+ int version;
+ int pipe_xor_bits = 0;
+ int bank_xor_bits = 0;
+ int packers = 0;
+ uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags,
DCC_OFFSET_256B);
+
+ switch (swizzle >> 2) {
+ case 0: /* 256B */
+ block_size_bits = 8;
+ break;
+ case 1: /* 4KiB */
+ case 5: /* 4KiB _X */
+ block_size_bits = 12;
+ break;
+ case 2: /* 64KiB */
+ case 4: /* 64 KiB _T */
+ case 6: /* 64 KiB _X */
+ block_size_bits = 16;
+ break;
+ default:
+ /* RESERVED or VAR */
+ return -EINVAL;
+ }
+
+ if (adev->asic_type >= CHIP_SIENNA_CICHLID)
+ version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
+ else if (adev->family == AMDGPU_FAMILY_NV)
+ version = AMD_FMT_MOD_TILE_VER_GFX10;
+ else
+ version = AMD_FMT_MOD_TILE_VER_GFX9;
+
+ switch (swizzle & 3) {
+ case 0: /* Z microtiling */
+ return -EINVAL;
+ case 1: /* S microtiling */
+ if (!has_xor)
+ version = AMD_FMT_MOD_TILE_VER_GFX9;
+ break;
+ case 2:
+ if (!has_xor && afb->base.format->cpp[0] != 4)
+ version = AMD_FMT_MOD_TILE_VER_GFX9;
+ break;
+ case 3:
+ break;
+ }
+
+ if (has_xor) {
+ switch (version) {
+ case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
+ pipe_xor_bits = min(block_size_bits - 8,
+
ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes));
+ packers = min(block_size_bits - 8 -
pipe_xor_bits,
+
ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
+ break;
+ case AMD_FMT_MOD_TILE_VER_GFX10:
+ pipe_xor_bits = min(block_size_bits - 8,
+
ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes));
+ break;
+ case AMD_FMT_MOD_TILE_VER_GFX9:
+ pipe_xor_bits = min(block_size_bits - 8,
+
ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes) +
+
ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
+ bank_xor_bits = min(block_size_bits - 8 -
pipe_xor_bits,
+
ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
+ break;
+ }
+ }
+
+ modifier = AMD_FMT_MOD |
+ AMD_FMT_MOD_SET(TILE,
AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
+ AMD_FMT_MOD_SET(TILE_VERSION, version) |
+ AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+
[PATCH v4 01/11] drm/amd/display: Do not silently accept DCC for multiplane formats.
Silently accepting it could result in corruption. Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Alex Deucher Reviewed-by: Nicholas Kazlauskas --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2713caac4f2a..73987fdb6a09 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3908,7 +3908,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, return 0; if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) - return 0; + return -EINVAL; if (!dc->cap_funcs.get_dcc_compression_cap) return -EINVAL; -- 2.28.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 02/11] drm/amd: Init modifier field of helper fb.
Otherwise the field ends up being used uninitialized when enabling modifiers, failing validation with high likelyhood. v4: Use memset Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Alex Deucher (for v1) --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index e2c2eb45a793..0bf7d36c6686 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -207,6 +207,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, int ret; unsigned long tmp; + memset(_cmd, 0, sizeof(mode_cmd)); mode_cmd.width = sizes->surface_width; mode_cmd.height = sizes->surface_height; -- 2.28.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 07/11] drm/amd/display: Refactor surface tiling setup.
Prepare for inserting modifiers based configuration, while sharing
a bunch of DCC validation & initializing the device-based configuration.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 222 ++
1 file changed, 119 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5a0efaefbd7f..479c886816d9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3839,46 +3839,86 @@ static int fill_dc_scaling_info(const struct
drm_plane_state *state,
return 0;
}
-static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
+static void
+fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
+uint64_t tiling_flags)
{
- uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
+ /* Fill GFX8 params */
+ if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) ==
DC_ARRAY_2D_TILED_THIN1) {
+ unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
+
+ bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
+ bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
+ mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
+ tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
+ num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
+
+ /* XXX fix me for VI */
+ tiling_info->gfx8.num_banks = num_banks;
+ tiling_info->gfx8.array_mode =
+ DC_ARRAY_2D_TILED_THIN1;
+ tiling_info->gfx8.tile_split = tile_split;
+ tiling_info->gfx8.bank_width = bankw;
+ tiling_info->gfx8.bank_height = bankh;
+ tiling_info->gfx8.tile_aspect = mtaspect;
+ tiling_info->gfx8.tile_mode =
+ DC_ADDR_SURF_MICRO_TILING_DISPLAY;
+ } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
+ == DC_ARRAY_1D_TILED_THIN1) {
+ tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
+ }
- return offset ? (address + offset * 256) : 0;
+ tiling_info->gfx8.pipe_config =
+ AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
+}
+
+static void
+fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
+ union dc_tiling_info *tiling_info)
+{
+ tiling_info->gfx9.num_pipes =
+ adev->gfx.config.gb_addr_config_fields.num_pipes;
+ tiling_info->gfx9.num_banks =
+ adev->gfx.config.gb_addr_config_fields.num_banks;
+ tiling_info->gfx9.pipe_interleave =
+ adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
+ tiling_info->gfx9.num_shader_engines =
+ adev->gfx.config.gb_addr_config_fields.num_se;
+ tiling_info->gfx9.max_compressed_frags =
+ adev->gfx.config.gb_addr_config_fields.max_compress_frags;
+ tiling_info->gfx9.num_rb_per_se =
+ adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
+ tiling_info->gfx9.shaderEnable = 1;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+ if (adev->asic_type == CHIP_SIENNA_CICHLID ||
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
+ adev->asic_type == CHIP_VANGOGH)
+ tiling_info->gfx9.num_pkrs =
adev->gfx.config.gb_addr_config_fields.num_pkrs;
+#endif
}
static int
-fill_plane_dcc_attributes(struct amdgpu_device *adev,
- const struct amdgpu_framebuffer *afb,
- const enum surface_pixel_format format,
- const enum dc_rotation_angle rotation,
- const struct plane_size *plane_size,
- const union dc_tiling_info *tiling_info,
- const uint64_t info,
- struct dc_plane_dcc_param *dcc,
- struct dc_plane_address *address,
- bool force_disable_dcc)
+validate_dcc(struct amdgpu_device *adev,
+const enum surface_pixel_format format,
+const enum dc_rotation_angle rotation,
+const union dc_tiling_info *tiling_info,
+const struct dc_plane_dcc_param *dcc,
+const struct dc_plane_address *address,
+const struct plane_size *plane_size)
{
struct dc *dc = adev->dm.dc;
struct dc_dcc_surface_param input;
struct dc_surface_dcc_cap output;
- uint64_t plane_address = afb->address + afb->base.offsets[0];
- uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
- uint32_t i64b =
[PATCH v4 08/11] drm/amd/display: Set DC options from modifiers.
This sets the DC tiling options from the modifier, if modifiers
are used for the FB. This patch by itself does not expose the
support yet though.
There is not much validation yet to limit the scope of this
patch, but the current validation is at the same level as
the BO metadata path.
v2: Add modifier check to should_reset_plane.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 102 --
1 file changed, 95 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 479c886816d9..034397c1f2b1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3995,6 +3995,83 @@ fill_gfx9_plane_attributes_from_flags(struct
amdgpu_device *adev,
return 0;
}
+static bool
+modifier_has_dcc(uint64_t modifier)
+{
+ return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
+}
+
+static unsigned
+modifier_gfx9_swizzle_mode(uint64_t modifier)
+{
+ if (modifier == DRM_FORMAT_MOD_LINEAR)
+ return 0;
+
+ return AMD_FMT_MOD_GET(TILE, modifier);
+}
+
+static void
+fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
+ union dc_tiling_info *tiling_info,
+ uint64_t modifier)
+{
+ unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS,
modifier);
+ unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS,
modifier);
+ unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
+ unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
+
+ fill_gfx9_tiling_info_from_device(adev, tiling_info);
+
+ if (!IS_AMD_FMT_MOD(modifier))
+ return;
+
+ tiling_info->gfx9.num_pipes = 1u << pipes_log2;
+ tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits -
pipes_log2);
+
+ if (adev->family >= AMDGPU_FAMILY_NV) {
+ tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
+ } else {
+ tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
+
+ /* for DCC we know it isn't rb aligned, so rb_per_se doesn't
matter. */
+ }
+}
+
+static int
+fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
+ const struct amdgpu_framebuffer *afb,
+ const enum surface_pixel_format
format,
+ const enum dc_rotation_angle rotation,
+ const struct plane_size *plane_size,
+ union dc_tiling_info *tiling_info,
+ struct dc_plane_dcc_param *dcc,
+ struct dc_plane_address *address,
+ const bool force_disable_dcc)
+{
+ const uint64_t modifier = afb->base.modifier;
+ int ret;
+
+ fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
+ tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
+
+ if (modifier_has_dcc(modifier) && !force_disable_dcc) {
+ uint64_t dcc_address = afb->address + afb->base.offsets[1];
+
+ dcc->enable = 1;
+ dcc->meta_pitch = afb->base.pitches[1];
+ dcc->independent_64b_blks =
AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
+
+ address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
+ address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
+ }
+
+ ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address,
plane_size);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int
fill_plane_buffer_attributes(struct amdgpu_device *adev,
const struct amdgpu_framebuffer *afb,
@@ -4063,12 +4140,22 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
}
if (adev->family >= AMDGPU_FAMILY_AI) {
- ret = fill_gfx9_plane_attributes_from_flags(adev, afb, format,
rotation,
- plane_size,
tiling_info, dcc,
- address,
tiling_flags,
- force_disable_dcc);
- if (ret)
- return ret;
+ if (afb->base.flags & DRM_MODE_FB_MODIFIERS) {
+ ret = fill_gfx9_plane_attributes_from_modifiers(adev,
afb, format,
+
rotation, plane_size,
+
tiling_info, dcc,
+
[PATCH v4 03/11] drm/amd/display: Honor the offset for plane 0.
With modifiers I'd like to support non-dedicated buffers for
images.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
Cc: sta...@vger.kernel.org # 5.1.0
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 73987fdb6a09..833887b9b0ad 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3894,6 +3894,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
struct dc *dc = adev->dm.dc;
struct dc_dcc_surface_param input;
struct dc_surface_dcc_cap output;
+ uint64_t plane_address = afb->address + afb->base.offsets[0];
uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
uint64_t dcc_address;
@@ -3937,7 +3938,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
dcc->independent_64b_blks = i64b;
- dcc_address = get_dcc_address(afb->address, info);
+ dcc_address = get_dcc_address(plane_address, info);
address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
@@ -3968,6 +3969,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
address->tmz_surface = tmz_surface;
if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
+ uint64_t addr = afb->address + fb->offsets[0];
+
plane_size->surface_size.x = 0;
plane_size->surface_size.y = 0;
plane_size->surface_size.width = fb->width;
@@ -3976,9 +3979,10 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
fb->pitches[0] / fb->format->cpp[0];
address->type = PLN_ADDR_TYPE_GRAPHICS;
- address->grph.addr.low_part = lower_32_bits(afb->address);
- address->grph.addr.high_part = upper_32_bits(afb->address);
+ address->grph.addr.low_part = lower_32_bits(addr);
+ address->grph.addr.high_part = upper_32_bits(addr);
} else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
+ uint64_t luma_addr = afb->address + fb->offsets[0];
uint64_t chroma_addr = afb->address + fb->offsets[1];
plane_size->surface_size.x = 0;
@@ -3999,9 +4003,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
address->video_progressive.luma_addr.low_part =
- lower_32_bits(afb->address);
+ lower_32_bits(luma_addr);
address->video_progressive.luma_addr.high_part =
- upper_32_bits(afb->address);
+ upper_32_bits(luma_addr);
address->video_progressive.chroma_addr.low_part =
lower_32_bits(chroma_addr);
address->video_progressive.chroma_addr.high_part =
--
2.28.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 00/11] amd/display: Add GFX9+ modifier support.
This adds modifier support to the amdgpu kernel drivers for GFX9 and
later GPUs. It has been tested on
- VEGA10, RAVEN, NAVI14
- weston, sway, X with xf86-video-amdgpu (i.e. legacy path still works)
and includes some basic testing of the layout code.
The main goal is to keep it somewhat simple and regression free, so
on the display side this series only exposes what the current GPU
can render to. While we could expose more I think that is more
suitable for follow-up work as the benefit would be minimal and
there are some more design discussion there to discuss that are
orthogonal from the initial implementation.
Similarly this series only exposes 32-bpp displayable DCC in the cases
that radeonsi would use it and any extra capabilities here should be
future work.
I believe these are by far the most complicated modifiers we've seen
up till now, mostly related to
- GPU identification for cases where it matters wrt tiling.
- Every generation having tiling layout changes
- Compression settings.
I believe the complexity is necessary as every layout should be different
and all layouts should be the best in some situation (though not all
combinations of GPU parameters will actually have an existing GPU).
That said, on the render side the number of modifiers actually listed for
a given GPU is ~10, and in the current implementation that is the same
for the display side. (we could expose more actually differing layouts
on the display side for cross-GPU compatibility, but I consider that
out of scope for this initial work).
This series can be found on
https://github.com/BNieuwenhuizen/linux/tree/modifiers
An userspace implementation in radeonsi can be found on
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176
which has been reviewed and is ready for submission once these kernel
patches land.
v2:
Per suggestion from Daniel Vetter I added logic to get the tiling_flags at
addfb2 time and convert them into modifiers for GFX9+. Furthermore, the DCC
constant econding modifers only get exposed on RAVEN2 and newer.
v3:
Fixed some typos, rebased and CCing more people to actually get a review.
v4:
Changed an initialization from {0} to memset, fixed a missing switch case
in the modifier enumeration and added review tags.
Bas Nieuwenhuizen (11):
drm/amd/display: Do not silently accept DCC for multiplane formats.
drm/amd: Init modifier field of helper fb.
drm/amd/display: Honor the offset for plane 0.
drm/fourcc: Add AMD DRM modifiers.
drm/amd/display: Store tiling_flags in the framebuffer.
drm/amd/display: Convert tiling_flags to modifiers.
drm/amd/display: Refactor surface tiling setup.
drm/amd/display: Set DC options from modifiers.
drm/amd/display: Add formats for DCC with 2/3 planes.
drm/amd/display: Expose modifiers.
drm/amd/display: Clean up GFX9 tiling_flags path.
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 169 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 754 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 -
include/uapi/drm/drm_fourcc.h | 115 +++
6 files changed, 880 insertions(+), 165 deletions(-)
--
2.28.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 10/11] drm/amd/display: Expose modifiers.
This expose modifier support on GFX9+.
Only modifiers that can be rendered on the current GPU are
added. This is to reduce the number of modifiers exposed.
The HW could expose more, but the best mechanism to decide
what to expose without an explosion in modifiers is still
to be decided, and in the meantime this should not regress
things from pre-modifiers and does not risk regressions as
we make up our mind in the future.
v2:
- Added comment that D on Raven is only valid for 64bpp
and will be filtered based on format later.
- Removed D tiling modes that weren't useful for 64bpp
on GFX10+.
v4: Add AMDGPU_FAMILY_VGH case.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 339 +-
1 file changed, 338 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6b33e030fe20..2202c0060b5c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4133,6 +4133,336 @@ fill_gfx9_tiling_info_from_modifier(const struct
amdgpu_device *adev,
}
}
+enum dm_micro_swizzle {
+ MICRO_SWIZZLE_Z = 0,
+ MICRO_SWIZZLE_S = 1,
+ MICRO_SWIZZLE_D = 2,
+ MICRO_SWIZZLE_R = 3
+};
+
+static bool dm_plane_format_mod_supported(struct drm_plane *plane,
+ uint32_t format,
+ uint64_t modifier)
+{
+ struct amdgpu_device *adev = drm_to_adev(plane->dev);
+ const struct drm_format_info *info = drm_format_info(format);
+
+ enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier)
& 3;
+
+ if (!info)
+ return false;
+
+ /*
+* We always have to allow this modifier, because core DRM still
+* checks LINEAR support if userspace does not provide modifers.
+*/
+ if (modifier == DRM_FORMAT_MOD_LINEAR)
+ return true;
+
+ /*
+* The arbitrary tiling support for multiplane formats has not been
hooked
+* up.
+*/
+ if (info->num_planes > 1)
+ return false;
+
+ /*
+* For D swizzle the canonical modifier depends on the bpp, so check
+* it here.
+*/
+ if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) ==
AMD_FMT_MOD_TILE_VER_GFX9 &&
+ adev->family >= AMDGPU_FAMILY_NV) {
+ if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4)
+ return false;
+ }
+
+ if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D &&
+ info->cpp[0] < 8)
+ return false;
+
+ if (modifier_has_dcc(modifier)) {
+ /* Per radeonsi comments 16/64 bpp are more complicated. */
+ if (info->cpp[0] != 4)
+ return false;
+ }
+
+ return true;
+}
+
+static void
+add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod)
+{
+ if (!*mods)
+ return;
+
+ if (*cap - *size < 1) {
+ uint64_t new_cap = *cap * 2;
+ uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t),
GFP_KERNEL);
+
+ if (!new_mods) {
+ kfree(*mods);
+ *mods = NULL;
+ return;
+ }
+
+ memcpy(new_mods, *mods, sizeof(uint64_t) * *size);
+ kfree(*mods);
+ *mods = new_mods;
+ *cap = new_cap;
+ }
+
+ (*mods)[*size] = mod;
+ *size += 1;
+}
+
+static void
+add_gfx9_modifiers(const struct amdgpu_device *adev,
+ uint64_t **mods, uint64_t *size, uint64_t *capacity)
+{
+ int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
+ int pipe_xor_bits = min(8, pipes +
+
ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
+ int bank_xor_bits = min(8 - pipe_xor_bits,
+
ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
+ int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
+ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
+
+
+ if (adev->family == AMDGPU_FAMILY_RV) {
+ /* Raven2 and later */
+ bool has_constant_encode = adev->asic_type > CHIP_RAVEN ||
adev->external_rev_id >= 0x81;
+
+ /*
+* No _D DCC swizzles yet because we only allow 32bpp, which
+* doesn't support _D on DCN
+*/
+
+ if (has_constant_encode) {
+ add_modifier(mods, size, capacity, AMD_FMT_MOD |
+ AMD_FMT_MOD_SET(TILE,
AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
+ AMD_FMT_MOD_SET(TILE_VERSION,
[PATCH v4 09/11] drm/amd/display: Add formats for DCC with 2/3 planes.
For DCC we will use 2/3 planes to avoid X rendering to the frontbuffer
with DCC compressed images. To make this work with the core KMS
validation we need to add extra formats with the extra planes.
However, due to flexibility we set bpp = 0 for the extra planes and
do the validation ourselves.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 96 +++
1 file changed, 96 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 034397c1f2b1..6b33e030fe20 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -185,6 +185,9 @@ static bool amdgpu_dm_link_setup_psr(struct dc_stream_state
*stream);
static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
+static const struct drm_format_info *
+amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
+
/*
* dm_vblank_get_counter
*
@@ -2160,6 +2163,7 @@ const struct amdgpu_ip_block_version dm_ip_block =
static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_display_user_framebuffer_create,
+ .get_format_info = amd_get_format_info,
.output_poll_changed = drm_fb_helper_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
.atomic_commit = amdgpu_dm_atomic_commit,
@@ -4010,6 +4014,98 @@ modifier_gfx9_swizzle_mode(uint64_t modifier)
return AMD_FMT_MOD_GET(TILE, modifier);
}
+static const struct drm_format_info dcc_formats[] = {
+ { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub =
1, .vsub = 1, },
+{ .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub =
1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub =
1, .vsub = 1,
+ .has_alpha = true, },
+ { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub =
1, .vsub = 1,
+ .has_alpha = true, },
+ { .format = DRM_FORMAT_BGRA, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub =
1, .vsub = 1,
+ .has_alpha = true, },
+ { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
+ .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub =
1, .vsub = 1, },
+ { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
+ .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub =
1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
+ .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub =
1, .vsub = 1,
+ .has_alpha = true, },
+ { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
+ .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub =
1, .vsub = 1,
+ .has_alpha = true, },
+ { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
+ .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub =
1, .vsub = 1, },
+};
+
+static const struct drm_format_info dcc_retile_formats[] = {
+ { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub
= 1, .vsub = 1, },
+{ .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub
= 1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub
= 1, .vsub = 1,
+ .has_alpha = true, },
+ { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub
= 1, .vsub = 1,
+ .has_alpha = true, },
+ { .format = DRM_FORMAT_BGRA, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub
= 1, .vsub = 1,
+ .has_alpha = true, },
+ { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
+ .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub
= 1, .vsub = 1, },
+ { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
+ .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub
= 1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
+ .cpp = {
[PATCH v4 05/11] drm/amd/display: Store tiling_flags in the framebuffer.
This moves the tiling_flags to the framebuffer creation.
This way the time of the "tiling" decision is the same as it
would be with modifiers.
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 48 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 73 +++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 -
4 files changed, 59 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 9e92d2a070ac..1a2664c3fc26 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -541,6 +541,39 @@ uint32_t amdgpu_display_supported_domains(struct
amdgpu_device *adev,
return domain;
}
+static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer
*amdgpu_fb,
+ uint64_t *tiling_flags, bool *tmz_surface)
+{
+ struct amdgpu_bo *rbo;
+ int r;
+
+ if (!amdgpu_fb) {
+ *tiling_flags = 0;
+ *tmz_surface = false;
+ return 0;
+ }
+
+ rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
+ r = amdgpu_bo_reserve(rbo, false);
+
+ if (unlikely(r)) {
+ /* Don't show error message when returning -ERESTARTSYS */
+ if (r != -ERESTARTSYS)
+ DRM_ERROR("Unable to reserve buffer: %d\n", r);
+ return r;
+ }
+
+ if (tiling_flags)
+ amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
+
+ if (tmz_surface)
+ *tmz_surface = amdgpu_bo_encrypted(rbo);
+
+ amdgpu_bo_unreserve(rbo);
+
+ return r;
+}
+
int amdgpu_display_framebuffer_init(struct drm_device *dev,
struct amdgpu_framebuffer *rfb,
const struct drm_mode_fb_cmd2 *mode_cmd,
@@ -550,11 +583,18 @@ int amdgpu_display_framebuffer_init(struct drm_device
*dev,
rfb->base.obj[0] = obj;
drm_helper_mode_fill_fb_struct(dev, >base, mode_cmd);
ret = drm_framebuffer_init(dev, >base, _fb_funcs);
- if (ret) {
- rfb->base.obj[0] = NULL;
- return ret;
- }
+ if (ret)
+ goto fail;
+
+ ret = amdgpu_display_get_fb_info(rfb, >tiling_flags,
>tmz_surface);
+ if (ret)
+ goto fail;
+
return 0;
+
+fail:
+ rfb->base.obj[0] = NULL;
+ return ret;
}
struct drm_framebuffer *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 345cb0464370..39866ed81c16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -304,6 +304,9 @@ struct amdgpu_display_funcs {
struct amdgpu_framebuffer {
struct drm_framebuffer base;
+ uint64_t tiling_flags;
+ bool tmz_surface;
+
/* caching for later use */
uint64_t address;
};
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 833887b9b0ad..5a0efaefbd7f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3839,39 +3839,6 @@ static int fill_dc_scaling_info(const struct
drm_plane_state *state,
return 0;
}
-static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
- uint64_t *tiling_flags, bool *tmz_surface)
-{
- struct amdgpu_bo *rbo;
- int r;
-
- if (!amdgpu_fb) {
- *tiling_flags = 0;
- *tmz_surface = false;
- return 0;
- }
-
- rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
- r = amdgpu_bo_reserve(rbo, false);
-
- if (unlikely(r)) {
- /* Don't show error message when returning -ERESTARTSYS */
- if (r != -ERESTARTSYS)
- DRM_ERROR("Unable to reserve buffer: %d\n", r);
- return r;
- }
-
- if (tiling_flags)
- amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
-
- if (tmz_surface)
- *tmz_surface = amdgpu_bo_encrypted(rbo);
-
- amdgpu_bo_unreserve(rbo);
-
- return r;
-}
-
static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
{
uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
@@ -4287,7 +4254,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device
*adev,
struct drm_crtc_state *crtc_state)
{
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
- struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
+ struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer
*)plane_state->fb;
RE: [PATCH] drm/amd/display: allow 18 bit dp output on DCN3
Reviewed-by: Nikola Cornij
-Original Message-
From: Siqueira, Rodrigo
Sent: Wednesday, October 28, 2020 6:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: Cornij, Nikola ; Liu, Zhan ;
Lakha, Bhawanpreet ; Wentland, Harry
; Laktyushkin, Dmytro ;
Park, Chris
Subject: [PATCH] drm/amd/display: allow 18 bit dp output on DCN3
From: Dmytro Laktyushkin
We need this to pass dp compliance.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 14 --
.../amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2 +-
2 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index d1ed2a99bf65..d65496917e93 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2020,20 +2020,6 @@ static bool dcn30_internal_validate_bw(
dml_log_mode_support_params(>bw_ctx.dml);
- /* TODO: Need to check calculated vlevel why that fails validation of
below resolutions */
- if (context->res_ctx.pipe_ctx[0].stream != NULL) {
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable
== 640 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 480)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable
== 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 800)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable
== 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 768)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable
== 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1024)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable
== 2048 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1536)
- vlevel = 0;
- }
-
if (vlevel == context->bw_ctx.dml.soc.num_states)
goto validate_fail;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 9e0ae18e71fa..0f668699809d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3628,7 +3628,7 @@ static double TruncToValidBPP(
}
}
} else {
- if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 ||
DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) ||
+ if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 ||
DesiredBPP
+== NonDSCBPP1 || DesiredBPP == NonDSCBPP0 || DesiredBPP == 18)) ||
(DSCEnable && DesiredBPP >= MinDSCBPP &&
DesiredBPP <= MaxDSCBPP))) {
return BPP_INVALID;
} else {
--
2.29.1
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[PATCH] drm/amd/display: allow 18 bit dp output on DCN3
From: Dmytro Laktyushkin
We need this to pass dp compliance.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 14 --
.../amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2 +-
2 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index d1ed2a99bf65..d65496917e93 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2020,20 +2020,6 @@ static bool dcn30_internal_validate_bw(
dml_log_mode_support_params(>bw_ctx.dml);
- /* TODO: Need to check calculated vlevel why that fails validation of
below resolutions */
- if (context->res_ctx.pipe_ctx[0].stream != NULL) {
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable
== 640 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 480)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable
== 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 800)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable
== 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 768)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable
== 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1024)
- vlevel = 0;
- if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable
== 2048 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1536)
- vlevel = 0;
- }
-
if (vlevel == context->bw_ctx.dml.soc.num_states)
goto validate_fail;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 9e0ae18e71fa..0f668699809d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3628,7 +3628,7 @@ static double TruncToValidBPP(
}
}
} else {
- if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 ||
DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) ||
+ if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 ||
DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0 || DesiredBPP == 18)) ||
(DSCEnable && DesiredBPP >= MinDSCBPP &&
DesiredBPP <= MaxDSCBPP))) {
return BPP_INVALID;
} else {
--
2.29.1
___
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[PATCH v6 00/10] Support GEM object mappings from I/O memory
DRM's fbdev console uses regular load and store operations to update
framebuffer memory. The bochs driver on sparc64 requires the use of
I/O-specific load and store operations. We have a workaround, but need
a long-term solution to the problem.
This patchset changes GEM's vmap/vunmap interfaces to forward pointers
of type struct dma_buf_map and updates the generic fbdev emulation to
use them correctly. This enables I/O-memory operations on all framebuffers
that require and support them.
Patches #1 to #4 prepare VRAM helpers and drivers.
Next is the update of the GEM vmap functions. Patch #5 adds vmap and vunmap
that is usable with TTM-based GEM drivers, and patch #6 updates GEM's
vmap/vunmap callback to forward instances of type struct dma_buf_map. While
the patch touches many files throughout the DRM modules, the applied changes
are mostly trivial interface fixes. Several TTM-based GEM drivers now use
the new vmap code. Patch #7 updates GEM's internal vmap/vunmap functions to
forward struct dma_buf_map.
With struct dma_buf_map propagated through the layers, patches #8 to #10
convert DRM clients and generic fbdev emulation to use it. Updating the
fbdev framebuffer will select the correct functions, either for system or
I/O memory.
v6:
* don't call page_to_phys() on fbdev framebuffers in I/O memory;
warn instead (Daniel)
v5:
* rebase onto latest TTM changes (Christian)
* support TTM premapped memory correctly (Christian)
* implement fb_read/fb_write internally (Sam, Daniel)
* cleanups
v4:
* provide TTM vmap/vunmap plus GEM helpers and convert drivers
over (Christian, Daniel)
* remove several empty functions
* more TODOs and documentation (Daniel)
v3:
* recreate the whole patchset on top of struct dma_buf_map
v2:
* RFC patchset
Thomas Zimmermann (10):
drm/vram-helper: Remove invariant parameters from internal kmap
function
drm/cma-helper: Remove empty drm_gem_cma_prime_vunmap()
drm/etnaviv: Remove empty etnaviv_gem_prime_vunmap()
drm/exynos: Remove empty exynos_drm_gem_prime_{vmap,vunmap}()
drm/ttm: Add vmap/vunmap to TTM and TTM GEM helpers
drm/gem: Use struct dma_buf_map in GEM vmap ops and convert GEM
backends
drm/gem: Update internal GEM vmap/vunmap interfaces to use struct
dma_buf_map
drm/gem: Store client buffer mappings as struct dma_buf_map
dma-buf-map: Add memcpy and pointer-increment interfaces
drm/fb_helper: Support framebuffers in I/O memory
Documentation/gpu/todo.rst | 37 ++-
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 36 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 -
drivers/gpu/drm/ast/ast_cursor.c| 27 +-
drivers/gpu/drm/ast/ast_drv.h | 7 +-
drivers/gpu/drm/bochs/bochs_kms.c | 1 -
drivers/gpu/drm/drm_client.c| 38 +--
drivers/gpu/drm/drm_fb_helper.c | 257 ++--
drivers/gpu/drm/drm_gem.c | 29 ++-
drivers/gpu/drm/drm_gem_cma_helper.c| 27 +-
drivers/gpu/drm/drm_gem_shmem_helper.c | 48 ++--
drivers/gpu/drm/drm_gem_ttm_helper.c| 38 +++
drivers/gpu/drm/drm_gem_vram_helper.c | 117 -
drivers/gpu/drm/drm_internal.h | 5 +-
drivers/gpu/drm/drm_prime.c | 14 +-
drivers/gpu/drm/etnaviv/etnaviv_drv.h | 3 +-
drivers/gpu/drm/etnaviv/etnaviv_gem.c | 1 -
drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 12 +-
drivers/gpu/drm/exynos/exynos_drm_gem.c | 12 -
drivers/gpu/drm/exynos/exynos_drm_gem.h | 2 -
drivers/gpu/drm/lima/lima_gem.c | 6 +-
drivers/gpu/drm/lima/lima_sched.c | 11 +-
drivers/gpu/drm/mgag200/mgag200_mode.c | 10 +-
drivers/gpu/drm/nouveau/Kconfig | 1 +
drivers/gpu/drm/nouveau/nouveau_bo.h| 2 -
drivers/gpu/drm/nouveau/nouveau_gem.c | 6 +-
drivers/gpu/drm/nouveau/nouveau_gem.h | 2 -
drivers/gpu/drm/nouveau/nouveau_prime.c | 20 --
drivers/gpu/drm/panfrost/panfrost_perfcnt.c | 14 +-
drivers/gpu/drm/qxl/qxl_display.c | 11 +-
drivers/gpu/drm/qxl/qxl_draw.c | 14 +-
drivers/gpu/drm/qxl/qxl_drv.h | 11 +-
drivers/gpu/drm/qxl/qxl_object.c| 31 ++-
drivers/gpu/drm/qxl/qxl_object.h| 2 +-
drivers/gpu/drm/qxl/qxl_prime.c | 12 +-
drivers/gpu/drm/radeon/radeon.h | 1 -
drivers/gpu/drm/radeon/radeon_gem.c | 7 +-
drivers/gpu/drm/radeon/radeon_prime.c | 20 --
drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 22 +-
drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 4 +-
drivers/gpu/drm/tiny/cirrus.c | 10 +-
drivers/gpu/drm/tiny/gm12u320.c | 10 +-
[PATCH v6 04/10] drm/exynos: Remove empty exynos_drm_gem_prime_{vmap, vunmap}()
The functions exynos_drm_gem_prime_{vmap,vunmap}() are empty. Remove
them before changing the interface to use struct drm_buf_map. As a side
effect of removing drm_gem_prime_vmap(), the error code changes from
ENOMEM to EOPNOTSUPP.
Signed-off-by: Thomas Zimmermann
Acked-by: Christian König
Tested-by: Sam Ravnborg
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 12
drivers/gpu/drm/exynos/exynos_drm_gem.h | 2 --
2 files changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c
b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index e7a6eb96f692..13a35623ac04 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -137,8 +137,6 @@ static const struct vm_operations_struct
exynos_drm_gem_vm_ops = {
static const struct drm_gem_object_funcs exynos_drm_gem_object_funcs = {
.free = exynos_drm_gem_free_object,
.get_sg_table = exynos_drm_gem_prime_get_sg_table,
- .vmap = exynos_drm_gem_prime_vmap,
- .vunmap = exynos_drm_gem_prime_vunmap,
.vm_ops = _drm_gem_vm_ops,
};
@@ -471,16 +469,6 @@ exynos_drm_gem_prime_import_sg_table(struct drm_device
*dev,
return _gem->base;
}
-void *exynos_drm_gem_prime_vmap(struct drm_gem_object *obj)
-{
- return NULL;
-}
-
-void exynos_drm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
-{
- /* Nothing to do */
-}
-
int exynos_drm_gem_prime_mmap(struct drm_gem_object *obj,
struct vm_area_struct *vma)
{
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h
b/drivers/gpu/drm/exynos/exynos_drm_gem.h
index 74e926abeff0..a23272fb96fb 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h
@@ -107,8 +107,6 @@ struct drm_gem_object *
exynos_drm_gem_prime_import_sg_table(struct drm_device *dev,
struct dma_buf_attachment *attach,
struct sg_table *sgt);
-void *exynos_drm_gem_prime_vmap(struct drm_gem_object *obj);
-void exynos_drm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
int exynos_drm_gem_prime_mmap(struct drm_gem_object *obj,
struct vm_area_struct *vma);
--
2.29.0
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[PATCH v6 08/10] drm/gem: Store client buffer mappings as struct dma_buf_map
Kernel DRM clients now store their framebuffer address in an instance
of struct dma_buf_map. Depending on the buffer's location, the address
refers to system or I/O memory.
Callers of drm_client_buffer_vmap() receive a copy of the value in
the call's supplied arguments. It can be accessed and modified with
dma_buf_map interfaces.
v6:
* don't call page_to_phys() on framebuffers in I/O memory;
warn instead (Daniel)
Signed-off-by: Thomas Zimmermann
Reviewed-by: Daniel Vetter
Tested-by: Sam Ravnborg
---
drivers/gpu/drm/drm_client.c| 34 +++--
drivers/gpu/drm/drm_fb_helper.c | 32 ---
include/drm/drm_client.h| 7 ---
3 files changed, 45 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c
index ac0082bed966..fe573acf1067 100644
--- a/drivers/gpu/drm/drm_client.c
+++ b/drivers/gpu/drm/drm_client.c
@@ -235,7 +235,7 @@ static void drm_client_buffer_delete(struct
drm_client_buffer *buffer)
{
struct drm_device *dev = buffer->client->dev;
- drm_gem_vunmap(buffer->gem, buffer->vaddr);
+ drm_gem_vunmap(buffer->gem, >map);
if (buffer->gem)
drm_gem_object_put(buffer->gem);
@@ -291,25 +291,31 @@ drm_client_buffer_create(struct drm_client_dev *client,
u32 width, u32 height, u
/**
* drm_client_buffer_vmap - Map DRM client buffer into address space
* @buffer: DRM client buffer
+ * @map_copy: Returns the mapped memory's address
*
* This function maps a client buffer into kernel address space. If the
- * buffer is already mapped, it returns the mapping's address.
+ * buffer is already mapped, it returns the existing mapping's address.
*
* Client buffer mappings are not ref'counted. Each call to
* drm_client_buffer_vmap() should be followed by a call to
* drm_client_buffer_vunmap(); or the client buffer should be mapped
* throughout its lifetime.
*
+ * The returned address is a copy of the internal value. In contrast to
+ * other vmap interfaces, you don't need it for the client's vunmap
+ * function. So you can modify it at will during blit and draw operations.
+ *
* Returns:
- * The mapped memory's address
+ * 0 on success, or a negative errno code otherwise.
*/
-void *drm_client_buffer_vmap(struct drm_client_buffer *buffer)
+int
+drm_client_buffer_vmap(struct drm_client_buffer *buffer, struct dma_buf_map
*map_copy)
{
- struct dma_buf_map map;
+ struct dma_buf_map *map = >map;
int ret;
- if (buffer->vaddr)
- return buffer->vaddr;
+ if (dma_buf_map_is_set(map))
+ goto out;
/*
* FIXME: The dependency on GEM here isn't required, we could
@@ -319,13 +325,14 @@ void *drm_client_buffer_vmap(struct drm_client_buffer
*buffer)
* fd_install step out of the driver backend hooks, to make that
* final step optional for internal users.
*/
- ret = drm_gem_vmap(buffer->gem, );
+ ret = drm_gem_vmap(buffer->gem, map);
if (ret)
- return ERR_PTR(ret);
+ return ret;
- buffer->vaddr = map.vaddr;
+out:
+ *map_copy = *map;
- return map.vaddr;
+ return 0;
}
EXPORT_SYMBOL(drm_client_buffer_vmap);
@@ -339,10 +346,9 @@ EXPORT_SYMBOL(drm_client_buffer_vmap);
*/
void drm_client_buffer_vunmap(struct drm_client_buffer *buffer)
{
- struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(buffer->vaddr);
+ struct dma_buf_map *map = >map;
- drm_gem_vunmap(buffer->gem, );
- buffer->vaddr = NULL;
+ drm_gem_vunmap(buffer->gem, map);
}
EXPORT_SYMBOL(drm_client_buffer_vunmap);
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index c2f72bb6afb1..6ce0b9119ef2 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -378,7 +378,7 @@ static void drm_fb_helper_dirty_blit_real(struct
drm_fb_helper *fb_helper,
unsigned int cpp = fb->format->cpp[0];
size_t offset = clip->y1 * fb->pitches[0] + clip->x1 * cpp;
void *src = fb_helper->fbdev->screen_buffer + offset;
- void *dst = fb_helper->buffer->vaddr + offset;
+ void *dst = fb_helper->buffer->map.vaddr + offset;
size_t len = (clip->x2 - clip->x1) * cpp;
unsigned int y;
@@ -400,7 +400,8 @@ static void drm_fb_helper_dirty_work(struct work_struct
*work)
struct drm_clip_rect *clip = >dirty_clip;
struct drm_clip_rect clip_copy;
unsigned long flags;
- void *vaddr;
+ struct dma_buf_map map;
+ int ret;
spin_lock_irqsave(>dirty_lock, flags);
clip_copy = *clip;
@@ -413,8 +414,8 @@ static void drm_fb_helper_dirty_work(struct work_struct
*work)
/* Generic fbdev uses a shadow buffer */
if (helper->buffer) {
- vaddr = drm_client_buffer_vmap(helper->buffer);
-
[PATCH v6 10/10] drm/fb_helper: Support framebuffers in I/O memory
At least sparc64 requires I/O-specific access to framebuffers. This
patch updates the fbdev console accordingly.
For drivers with direct access to the framebuffer memory, the callback
functions in struct fb_ops test for the type of memory and call the rsp
fb_sys_ of fb_cfb_ functions. Read and write operations are implemented
internally by DRM's fbdev helper.
For drivers that employ a shadow buffer, fbdev's blit function retrieves
the framebuffer address as struct dma_buf_map, and uses dma_buf_map
interfaces to access the buffer.
The bochs driver on sparc64 uses a workaround to flag the framebuffer as
I/O memory and avoid a HW exception. With the introduction of struct
dma_buf_map, this is not required any longer. The patch removes the rsp
code from both, bochs and fbdev.
v5:
* implement fb_read/fb_write internally (Daniel, Sam)
v4:
* move dma_buf_map changes into separate patch (Daniel)
* TODO list: comment on fbdev updates (Daniel)
Signed-off-by: Thomas Zimmermann
Reviewed-by: Daniel Vetter
Reviewed-by: Sam Ravnborg
Tested-by: Sam Ravnborg
---
Documentation/gpu/todo.rst| 19 ++-
drivers/gpu/drm/bochs/bochs_kms.c | 1 -
drivers/gpu/drm/drm_fb_helper.c | 227 --
include/drm/drm_mode_config.h | 12 --
4 files changed, 230 insertions(+), 29 deletions(-)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 7e6fc3c04add..638b7f704339 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -197,13 +197,28 @@ Convert drivers to use drm_fbdev_generic_setup()
Most drivers can use drm_fbdev_generic_setup(). Driver have to implement
-atomic modesetting and GEM vmap support. Current generic fbdev emulation
-expects the framebuffer in system memory (or system-like memory).
+atomic modesetting and GEM vmap support. Historically, generic fbdev emulation
+expected the framebuffer in system memory or system-like memory. By employing
+struct dma_buf_map, drivers with frambuffers in I/O memory can be supported
+as well.
Contact: Maintainer of the driver you plan to convert
Level: Intermediate
+Reimplement functions in drm_fbdev_fb_ops without fbdev
+---
+
+A number of callback functions in drm_fbdev_fb_ops could benefit from
+being rewritten without dependencies on the fbdev module. Some of the
+helpers could further benefit from using struct dma_buf_map instead of
+raw pointers.
+
+Contact: Thomas Zimmermann , Daniel Vetter
+
+Level: Advanced
+
+
drm_framebuffer_funcs and drm_mode_config_funcs.fb_create cleanup
-
diff --git a/drivers/gpu/drm/bochs/bochs_kms.c
b/drivers/gpu/drm/bochs/bochs_kms.c
index 13d0d04c4457..853081d186d5 100644
--- a/drivers/gpu/drm/bochs/bochs_kms.c
+++ b/drivers/gpu/drm/bochs/bochs_kms.c
@@ -151,7 +151,6 @@ int bochs_kms_init(struct bochs_device *bochs)
bochs->dev->mode_config.preferred_depth = 24;
bochs->dev->mode_config.prefer_shadow = 0;
bochs->dev->mode_config.prefer_shadow_fbdev = 1;
- bochs->dev->mode_config.fbdev_use_iomem = true;
bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = true;
bochs->dev->mode_config.funcs = _mode_funcs;
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 6ce0b9119ef2..714ce3bd6221 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -372,24 +372,22 @@ static void drm_fb_helper_resume_worker(struct
work_struct *work)
}
static void drm_fb_helper_dirty_blit_real(struct drm_fb_helper *fb_helper,
- struct drm_clip_rect *clip)
+ struct drm_clip_rect *clip,
+ struct dma_buf_map *dst)
{
struct drm_framebuffer *fb = fb_helper->fb;
unsigned int cpp = fb->format->cpp[0];
size_t offset = clip->y1 * fb->pitches[0] + clip->x1 * cpp;
void *src = fb_helper->fbdev->screen_buffer + offset;
- void *dst = fb_helper->buffer->map.vaddr + offset;
size_t len = (clip->x2 - clip->x1) * cpp;
unsigned int y;
- for (y = clip->y1; y < clip->y2; y++) {
- if (!fb_helper->dev->mode_config.fbdev_use_iomem)
- memcpy(dst, src, len);
- else
- memcpy_toio((void __iomem *)dst, src, len);
+ dma_buf_map_incr(dst, offset); /* go to first pixel within clip rect */
+ for (y = clip->y1; y < clip->y2; y++) {
+ dma_buf_map_memcpy_to(dst, src, len);
+ dma_buf_map_incr(dst, fb->pitches[0]);
src += fb->pitches[0];
- dst += fb->pitches[0];
}
}
@@ -417,8 +415,9 @@ static void drm_fb_helper_dirty_work(struct work_struct
*work)
ret =
[PATCH v6 09/10] dma-buf-map: Add memcpy and pointer-increment interfaces
To do framebuffer updates, one needs memcpy from system memory and a
pointer-increment function. Add both interfaces with documentation.
v5:
* include to build on sparc64 (Sam)
Signed-off-by: Thomas Zimmermann
Reviewed-by: Sam Ravnborg
Tested-by: Sam Ravnborg
---
include/linux/dma-buf-map.h | 73 -
1 file changed, 63 insertions(+), 10 deletions(-)
diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
index 2e8bbecb5091..583a3a1f9447 100644
--- a/include/linux/dma-buf-map.h
+++ b/include/linux/dma-buf-map.h
@@ -7,6 +7,7 @@
#define __DMA_BUF_MAP_H__
#include
+#include
/**
* DOC: overview
@@ -32,6 +33,14 @@
* accessing the buffer. Use the returned instance and the helper functions
* to access the buffer's memory in the correct way.
*
+ * The type :c:type:`struct dma_buf_map ` and its helpers are
+ * actually independent from the dma-buf infrastructure. When sharing buffers
+ * among devices, drivers have to know the location of the memory to access
+ * the buffers in a safe way. :c:type:`struct dma_buf_map `
+ * solves this problem for dma-buf and its users. If other drivers or
+ * sub-systems require similar functionality, the type could be generalized
+ * and moved to a more prominent header file.
+ *
* Open-coding access to :c:type:`struct dma_buf_map ` is
* considered bad style. Rather then accessing its fields directly, use one
* of the provided helper functions, or implement your own. For example,
@@ -51,6 +60,14 @@
*
* dma_buf_map_set_vaddr_iomem( 0xdeadbeaf);
*
+ * Instances of struct dma_buf_map do not have to be cleaned up, but
+ * can be cleared to NULL with dma_buf_map_clear(). Cleared mappings
+ * always refer to system memory.
+ *
+ * .. code-block:: c
+ *
+ * dma_buf_map_clear();
+ *
* Test if a mapping is valid with either dma_buf_map_is_set() or
* dma_buf_map_is_null().
*
@@ -73,17 +90,19 @@
* if (dma_buf_map_is_equal(_map, _map))
* // always false
*
- * Instances of struct dma_buf_map do not have to be cleaned up, but
- * can be cleared to NULL with dma_buf_map_clear(). Cleared mappings
- * always refer to system memory.
+ * A set up instance of struct dma_buf_map can be used to access or manipulate
+ * the buffer memory. Depending on the location of the memory, the provided
+ * helpers will pick the correct operations. Data can be copied into the memory
+ * with dma_buf_map_memcpy_to(). The address can be manipulated with
+ * dma_buf_map_incr().
*
- * The type :c:type:`struct dma_buf_map ` and its helpers are
- * actually independent from the dma-buf infrastructure. When sharing buffers
- * among devices, drivers have to know the location of the memory to access
- * the buffers in a safe way. :c:type:`struct dma_buf_map `
- * solves this problem for dma-buf and its users. If other drivers or
- * sub-systems require similar functionality, the type could be generalized
- * and moved to a more prominent header file.
+ * .. code-block:: c
+ *
+ * const void *src = ...; // source buffer
+ * size_t len = ...; // length of src
+ *
+ * dma_buf_map_memcpy_to(, src, len);
+ * dma_buf_map_incr(, len); // go to first byte after the memcpy
*/
/**
@@ -210,4 +229,38 @@ static inline void dma_buf_map_clear(struct dma_buf_map
*map)
}
}
+/**
+ * dma_buf_map_memcpy_to - Memcpy into dma-buf mapping
+ * @dst: The dma-buf mapping structure
+ * @src: The source buffer
+ * @len: The number of byte in src
+ *
+ * Copies data into a dma-buf mapping. The source buffer is in system
+ * memory. Depending on the buffer's location, the helper picks the correct
+ * method of accessing the memory.
+ */
+static inline void dma_buf_map_memcpy_to(struct dma_buf_map *dst, const void
*src, size_t len)
+{
+ if (dst->is_iomem)
+ memcpy_toio(dst->vaddr_iomem, src, len);
+ else
+ memcpy(dst->vaddr, src, len);
+}
+
+/**
+ * dma_buf_map_incr - Increments the address stored in a dma-buf mapping
+ * @map: The dma-buf mapping structure
+ * @incr: The number of bytes to increment
+ *
+ * Increments the address stored in a dma-buf mapping. Depending on the
+ * buffer's location, the correct value will be updated.
+ */
+static inline void dma_buf_map_incr(struct dma_buf_map *map, size_t incr)
+{
+ if (map->is_iomem)
+ map->vaddr_iomem += incr;
+ else
+ map->vaddr += incr;
+}
+
#endif /* __DMA_BUF_MAP_H__ */
--
2.29.0
___
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[PATCH v6 01/10] drm/vram-helper: Remove invariant parameters from internal kmap function
The parameters map and is_iomem are always of the same value. Removed them
to prepares the function for conversion to struct dma_buf_map.
v4:
* don't check for !kmap->virtual; will always be false
Signed-off-by: Thomas Zimmermann
Reviewed-by: Daniel Vetter
Reviewed-by: Christian König
Tested-by: Sam Ravnborg
---
drivers/gpu/drm/drm_gem_vram_helper.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
b/drivers/gpu/drm/drm_gem_vram_helper.c
index 9da823eb0edd..f445b84c43c4 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -379,32 +379,22 @@ int drm_gem_vram_unpin(struct drm_gem_vram_object *gbo)
}
EXPORT_SYMBOL(drm_gem_vram_unpin);
-static void *drm_gem_vram_kmap_locked(struct drm_gem_vram_object *gbo,
- bool map, bool *is_iomem)
+static void *drm_gem_vram_kmap_locked(struct drm_gem_vram_object *gbo)
{
int ret;
struct ttm_bo_kmap_obj *kmap = >kmap;
+ bool is_iomem;
if (gbo->kmap_use_count > 0)
goto out;
- if (kmap->virtual || !map)
- goto out;
-
ret = ttm_bo_kmap(>bo, 0, gbo->bo.num_pages, kmap);
if (ret)
return ERR_PTR(ret);
out:
- if (!kmap->virtual) {
- if (is_iomem)
- *is_iomem = false;
- return NULL; /* not mapped; don't increment ref */
- }
++gbo->kmap_use_count;
- if (is_iomem)
- return ttm_kmap_obj_virtual(kmap, is_iomem);
- return kmap->virtual;
+ return ttm_kmap_obj_virtual(kmap, _iomem);
}
static void drm_gem_vram_kunmap_locked(struct drm_gem_vram_object *gbo)
@@ -449,7 +439,7 @@ void *drm_gem_vram_vmap(struct drm_gem_vram_object *gbo)
ret = drm_gem_vram_pin_locked(gbo, 0);
if (ret)
goto err_ttm_bo_unreserve;
- base = drm_gem_vram_kmap_locked(gbo, true, NULL);
+ base = drm_gem_vram_kmap_locked(gbo);
if (IS_ERR(base)) {
ret = PTR_ERR(base);
goto err_drm_gem_vram_unpin_locked;
--
2.29.0
___
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[PATCH v6 05/10] drm/ttm: Add vmap/vunmap to TTM and TTM GEM helpers
The new functions ttm_bo_{vmap,vunmap}() map and unmap a TTM BO in kernel
address space. The mapping's address is returned as struct dma_buf_map.
Each function is a simplified version of TTM's existing kmap code. Both
functions respect the memory's location ani/or writecombine flags.
On top TTM's functions, GEM TTM helpers got drm_gem_ttm_{vmap,vunmap}(),
two helpers that convert a GEM object into the TTM BO and forward the call
to TTM's vmap/vunmap. These helpers can be dropped into the rsp GEM object
callbacks.
v5:
* use size_t for storing mapping size (Christian)
* ignore premapped memory areas correctly in ttm_bo_vunmap()
* rebase onto latest TTM interfaces (Christian)
* remove BUG() from ttm_bo_vmap() (Christian)
v4:
* drop ttm_kmap_obj_to_dma_buf() in favor of vmap helpers (Daniel,
Christian)
Signed-off-by: Thomas Zimmermann
Reviewed-by: Christian König
Acked-by: Daniel Vetter
Tested-by: Sam Ravnborg
---
drivers/gpu/drm/drm_gem_ttm_helper.c | 38 +++
drivers/gpu/drm/ttm/ttm_bo_util.c| 72
include/drm/drm_gem_ttm_helper.h | 6 +++
include/drm/ttm/ttm_bo_api.h | 28 +++
include/linux/dma-buf-map.h | 20
5 files changed, 164 insertions(+)
diff --git a/drivers/gpu/drm/drm_gem_ttm_helper.c
b/drivers/gpu/drm/drm_gem_ttm_helper.c
index 0e4fb9ba43ad..db4c14d78a30 100644
--- a/drivers/gpu/drm/drm_gem_ttm_helper.c
+++ b/drivers/gpu/drm/drm_gem_ttm_helper.c
@@ -49,6 +49,44 @@ void drm_gem_ttm_print_info(struct drm_printer *p, unsigned
int indent,
}
EXPORT_SYMBOL(drm_gem_ttm_print_info);
+/**
+ * drm_gem_ttm_vmap() - vmap _buffer_object
+ * @gem: GEM object.
+ * @map: [out] returns the dma-buf mapping.
+ *
+ * Maps a GEM object with ttm_bo_vmap(). This function can be used as
+ * _gem_object_funcs.vmap callback.
+ *
+ * Returns:
+ * 0 on success, or a negative errno code otherwise.
+ */
+int drm_gem_ttm_vmap(struct drm_gem_object *gem,
+struct dma_buf_map *map)
+{
+ struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem);
+
+ return ttm_bo_vmap(bo, map);
+
+}
+EXPORT_SYMBOL(drm_gem_ttm_vmap);
+
+/**
+ * drm_gem_ttm_vunmap() - vunmap _buffer_object
+ * @gem: GEM object.
+ * @map: dma-buf mapping.
+ *
+ * Unmaps a GEM object with ttm_bo_vunmap(). This function can be used as
+ * _gem_object_funcs.vmap callback.
+ */
+void drm_gem_ttm_vunmap(struct drm_gem_object *gem,
+ struct dma_buf_map *map)
+{
+ struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem);
+
+ ttm_bo_vunmap(bo, map);
+}
+EXPORT_SYMBOL(drm_gem_ttm_vunmap);
+
/**
* drm_gem_ttm_mmap() - mmap _buffer_object
* @gem: GEM object.
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index ecb54415d1ca..7ccb2295cac1 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -471,6 +472,77 @@ void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map)
}
EXPORT_SYMBOL(ttm_bo_kunmap);
+int ttm_bo_vmap(struct ttm_buffer_object *bo, struct dma_buf_map *map)
+{
+ struct ttm_resource *mem = >mem;
+ int ret;
+
+ ret = ttm_mem_io_reserve(bo->bdev, mem);
+ if (ret)
+ return ret;
+
+ if (mem->bus.is_iomem) {
+ void __iomem *vaddr_iomem;
+ size_t size = bo->num_pages << PAGE_SHIFT;
+
+ if (mem->bus.addr)
+ vaddr_iomem = (void __iomem *)mem->bus.addr;
+ else if (mem->bus.caching == ttm_write_combined)
+ vaddr_iomem = ioremap_wc(mem->bus.offset, size);
+ else
+ vaddr_iomem = ioremap(mem->bus.offset, size);
+
+ if (!vaddr_iomem)
+ return -ENOMEM;
+
+ dma_buf_map_set_vaddr_iomem(map, vaddr_iomem);
+
+ } else {
+ struct ttm_operation_ctx ctx = {
+ .interruptible = false,
+ .no_wait_gpu = false
+ };
+ struct ttm_tt *ttm = bo->ttm;
+ pgprot_t prot;
+ void *vaddr;
+
+ ret = ttm_tt_populate(bo->bdev, ttm, );
+ if (ret)
+ return ret;
+
+ /*
+* We need to use vmap to get the desired page protection
+* or to make the buffer object look contiguous.
+*/
+ prot = ttm_io_prot(bo, mem, PAGE_KERNEL);
+ vaddr = vmap(ttm->pages, bo->num_pages, 0, prot);
+ if (!vaddr)
+ return -ENOMEM;
+
+ dma_buf_map_set_vaddr(map, vaddr);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ttm_bo_vmap);
+
+void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct dma_buf_map *map)
+{
+ struct ttm_resource *mem =
[PATCH v6 06/10] drm/gem: Use struct dma_buf_map in GEM vmap ops and convert GEM backends
This patch replaces the vmap/vunmap's use of raw pointers in GEM object
functions with instances of struct dma_buf_map. GEM backends are
converted as well. For most of them, this simply changes the returned type.
TTM-based drivers now return information about the location of the memory,
either system or I/O memory. GEM VRAM helpers and qxl now use ttm_bo_vmap()
et al. Amdgpu, nouveau and radeon use drm_gem_ttm_vmap() et al instead of
implementing their own vmap callbacks.
v5:
* update vkms after switch to shmem
v4:
* use ttm_bo_vmap(), drm_gem_ttm_vmap(), et al. (Daniel, Christian)
* fix a trailing { in drm_gem_vmap()
* remove several empty functions instead of converting them (Daniel)
* comment uses of raw pointers with a TODO (Daniel)
* TODO list: convert more helpers to use struct dma_buf_map
Signed-off-by: Thomas Zimmermann
Acked-by: Christian König
Tested-by: Sam Ravnborg
---
Documentation/gpu/todo.rst | 18
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 36 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 -
drivers/gpu/drm/ast/ast_cursor.c| 27 +++--
drivers/gpu/drm/ast/ast_drv.h | 7 +-
drivers/gpu/drm/drm_gem.c | 23 +++--
drivers/gpu/drm/drm_gem_cma_helper.c| 10 +-
drivers/gpu/drm/drm_gem_shmem_helper.c | 48 +
drivers/gpu/drm/drm_gem_vram_helper.c | 107 ++--
drivers/gpu/drm/etnaviv/etnaviv_drv.h | 2 +-
drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 9 +-
drivers/gpu/drm/lima/lima_gem.c | 6 +-
drivers/gpu/drm/lima/lima_sched.c | 11 +-
drivers/gpu/drm/mgag200/mgag200_mode.c | 10 +-
drivers/gpu/drm/nouveau/Kconfig | 1 +
drivers/gpu/drm/nouveau/nouveau_bo.h| 2 -
drivers/gpu/drm/nouveau/nouveau_gem.c | 6 +-
drivers/gpu/drm/nouveau/nouveau_gem.h | 2 -
drivers/gpu/drm/nouveau/nouveau_prime.c | 20
drivers/gpu/drm/panfrost/panfrost_perfcnt.c | 14 +--
drivers/gpu/drm/qxl/qxl_display.c | 11 +-
drivers/gpu/drm/qxl/qxl_draw.c | 14 ++-
drivers/gpu/drm/qxl/qxl_drv.h | 11 +-
drivers/gpu/drm/qxl/qxl_object.c| 31 +++---
drivers/gpu/drm/qxl/qxl_object.h| 2 +-
drivers/gpu/drm/qxl/qxl_prime.c | 12 +--
drivers/gpu/drm/radeon/radeon.h | 1 -
drivers/gpu/drm/radeon/radeon_gem.c | 7 +-
drivers/gpu/drm/radeon/radeon_prime.c | 20
drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 22 ++--
drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 4 +-
drivers/gpu/drm/tiny/cirrus.c | 10 +-
drivers/gpu/drm/tiny/gm12u320.c | 10 +-
drivers/gpu/drm/udl/udl_modeset.c | 8 +-
drivers/gpu/drm/vboxvideo/vbox_mode.c | 11 +-
drivers/gpu/drm/vc4/vc4_bo.c| 6 +-
drivers/gpu/drm/vc4/vc4_drv.h | 2 +-
drivers/gpu/drm/vgem/vgem_drv.c | 16 ++-
drivers/gpu/drm/vkms/vkms_plane.c | 15 ++-
drivers/gpu/drm/vkms/vkms_writeback.c | 22 ++--
drivers/gpu/drm/xen/xen_drm_front_gem.c | 18 ++--
drivers/gpu/drm/xen/xen_drm_front_gem.h | 6 +-
include/drm/drm_gem.h | 5 +-
include/drm/drm_gem_cma_helper.h| 2 +-
include/drm/drm_gem_shmem_helper.h | 4 +-
include/drm/drm_gem_vram_helper.h | 14 +--
49 files changed, 345 insertions(+), 308 deletions(-)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 700637e25ecd..7e6fc3c04add 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -446,6 +446,24 @@ Contact: Ville Syrjälä, Daniel Vetter
Level: Intermediate
+Use struct dma_buf_map throughout codebase
+--
+
+Pointers to shared device memory are stored in struct dma_buf_map. Each
+instance knows whether it refers to system or I/O memory. Most of the DRM-wide
+interface have been converted to use struct dma_buf_map, but implementations
+often still use raw pointers.
+
+The task is to use struct dma_buf_map where it makes sense.
+
+* Memory managers should use struct dma_buf_map for dma-buf-imported buffers.
+* TTM might benefit from using struct dma_buf_map internally.
+* Framebuffer copying and blitting helpers should operate on struct
dma_buf_map.
+
+Contact: Thomas Zimmermann , Christian König, Daniel
Vetter
+
+Level: Intermediate
+
Core refactorings
=
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 32257189e09b..e479b04e955e 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -239,6 +239,7 @@ config DRM_RADEON
select FW_LOADER
select DRM_KMS_HELPER
[PATCH v6 03/10] drm/etnaviv: Remove empty etnaviv_gem_prime_vunmap()
The function etnaviv_gem_prime_vunmap() is empty. Remove it before
changing the interface to use struct drm_buf_map.
Signed-off-by: Thomas Zimmermann
Acked-by: Christian König
Tested-by: Sam Ravnborg
---
drivers/gpu/drm/etnaviv/etnaviv_drv.h | 1 -
drivers/gpu/drm/etnaviv/etnaviv_gem.c | 1 -
drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 5 -
3 files changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
index 914f0867ff71..9682c26d89bb 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
@@ -52,7 +52,6 @@ int etnaviv_gem_mmap(struct file *filp, struct vm_area_struct
*vma);
int etnaviv_gem_mmap_offset(struct drm_gem_object *obj, u64 *offset);
struct sg_table *etnaviv_gem_prime_get_sg_table(struct drm_gem_object *obj);
void *etnaviv_gem_prime_vmap(struct drm_gem_object *obj);
-void etnaviv_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
int etnaviv_gem_prime_mmap(struct drm_gem_object *obj,
struct vm_area_struct *vma);
struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device
*dev,
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
index 67d9a2b9ea6a..bbd235473645 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
@@ -571,7 +571,6 @@ static const struct drm_gem_object_funcs
etnaviv_gem_object_funcs = {
.unpin = etnaviv_gem_prime_unpin,
.get_sg_table = etnaviv_gem_prime_get_sg_table,
.vmap = etnaviv_gem_prime_vmap,
- .vunmap = etnaviv_gem_prime_vunmap,
.vm_ops = _ops,
};
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
index 135fbff6fecf..a6d9932a32ae 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
@@ -27,11 +27,6 @@ void *etnaviv_gem_prime_vmap(struct drm_gem_object *obj)
return etnaviv_gem_vmap(obj);
}
-void etnaviv_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
-{
- /* TODO msm_gem_vunmap() */
-}
-
int etnaviv_gem_prime_mmap(struct drm_gem_object *obj,
struct vm_area_struct *vma)
{
--
2.29.0
___
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[PATCH v6 07/10] drm/gem: Update internal GEM vmap/vunmap interfaces to use struct dma_buf_map
GEM's vmap and vunmap interfaces now wrap memory pointers in struct
dma_buf_map.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Daniel Vetter
Tested-by: Sam Ravnborg
---
drivers/gpu/drm/drm_client.c | 18 +++---
drivers/gpu/drm/drm_gem.c | 26 +-
drivers/gpu/drm/drm_internal.h | 5 +++--
drivers/gpu/drm/drm_prime.c| 14 --
4 files changed, 31 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c
index 495f47d23d87..ac0082bed966 100644
--- a/drivers/gpu/drm/drm_client.c
+++ b/drivers/gpu/drm/drm_client.c
@@ -3,6 +3,7 @@
* Copyright 2018 Noralf Trønnes
*/
+#include
#include
#include
#include
@@ -304,7 +305,8 @@ drm_client_buffer_create(struct drm_client_dev *client, u32
width, u32 height, u
*/
void *drm_client_buffer_vmap(struct drm_client_buffer *buffer)
{
- void *vaddr;
+ struct dma_buf_map map;
+ int ret;
if (buffer->vaddr)
return buffer->vaddr;
@@ -317,13 +319,13 @@ void *drm_client_buffer_vmap(struct drm_client_buffer
*buffer)
* fd_install step out of the driver backend hooks, to make that
* final step optional for internal users.
*/
- vaddr = drm_gem_vmap(buffer->gem);
- if (IS_ERR(vaddr))
- return vaddr;
+ ret = drm_gem_vmap(buffer->gem, );
+ if (ret)
+ return ERR_PTR(ret);
- buffer->vaddr = vaddr;
+ buffer->vaddr = map.vaddr;
- return vaddr;
+ return map.vaddr;
}
EXPORT_SYMBOL(drm_client_buffer_vmap);
@@ -337,7 +339,9 @@ EXPORT_SYMBOL(drm_client_buffer_vmap);
*/
void drm_client_buffer_vunmap(struct drm_client_buffer *buffer)
{
- drm_gem_vunmap(buffer->gem, buffer->vaddr);
+ struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(buffer->vaddr);
+
+ drm_gem_vunmap(buffer->gem, );
buffer->vaddr = NULL;
}
EXPORT_SYMBOL(drm_client_buffer_vunmap);
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index a89ad4570e3c..4d5fff4bd821 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -1206,32 +1206,32 @@ void drm_gem_unpin(struct drm_gem_object *obj)
obj->funcs->unpin(obj);
}
-void *drm_gem_vmap(struct drm_gem_object *obj)
+int drm_gem_vmap(struct drm_gem_object *obj, struct dma_buf_map *map)
{
- struct dma_buf_map map;
int ret;
if (!obj->funcs->vmap)
- return ERR_PTR(-EOPNOTSUPP);
+ return -EOPNOTSUPP;
- ret = obj->funcs->vmap(obj, );
+ ret = obj->funcs->vmap(obj, map);
if (ret)
- return ERR_PTR(ret);
- else if (dma_buf_map_is_null())
- return ERR_PTR(-ENOMEM);
+ return ret;
+ else if (dma_buf_map_is_null(map))
+ return -ENOMEM;
- return map.vaddr;
+ return 0;
}
-void drm_gem_vunmap(struct drm_gem_object *obj, void *vaddr)
+void drm_gem_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map)
{
- struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(vaddr);
-
- if (!vaddr)
+ if (dma_buf_map_is_null(map))
return;
if (obj->funcs->vunmap)
- obj->funcs->vunmap(obj, );
+ obj->funcs->vunmap(obj, map);
+
+ /* Always set the mapping to NULL. Callers may rely on this. */
+ dma_buf_map_clear(map);
}
/**
diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 2bdac3557765..81d386b5b92a 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -33,6 +33,7 @@
struct dentry;
struct dma_buf;
+struct dma_buf_map;
struct drm_connector;
struct drm_crtc;
struct drm_framebuffer;
@@ -187,8 +188,8 @@ void drm_gem_print_info(struct drm_printer *p, unsigned int
indent,
int drm_gem_pin(struct drm_gem_object *obj);
void drm_gem_unpin(struct drm_gem_object *obj);
-void *drm_gem_vmap(struct drm_gem_object *obj);
-void drm_gem_vunmap(struct drm_gem_object *obj, void *vaddr);
+int drm_gem_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
+void drm_gem_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
/* drm_debugfs.c drm_debugfs_crc.c */
#if defined(CONFIG_DEBUG_FS)
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 89e2a2496734..cb8fbeeb731b 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -667,21 +667,15 @@ EXPORT_SYMBOL(drm_gem_unmap_dma_buf);
*
* Sets up a kernel virtual mapping. This can be used as the _buf_ops.vmap
* callback. Calls into _gem_object_funcs.vmap for device specific
handling.
+ * The kernel virtual address is returned in map.
*
- * Returns the kernel virtual address or NULL on failure.
+ * Returns 0 on success or a negative errno code otherwise.
*/
int drm_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct dma_buf_map *map)
{
struct drm_gem_object *obj
[PATCH v6 02/10] drm/cma-helper: Remove empty drm_gem_cma_prime_vunmap()
The function drm_gem_cma_prime_vunmap() is empty. Remove it before
changing the interface to use struct drm_buf_map.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Christian König
Tested-by: Sam Ravnborg
---
drivers/gpu/drm/drm_gem_cma_helper.c | 17 -
drivers/gpu/drm/vc4/vc4_bo.c | 1 -
include/drm/drm_gem_cma_helper.h | 1 -
3 files changed, 19 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c
b/drivers/gpu/drm/drm_gem_cma_helper.c
index 2165633c9b9e..d527485ea0b7 100644
--- a/drivers/gpu/drm/drm_gem_cma_helper.c
+++ b/drivers/gpu/drm/drm_gem_cma_helper.c
@@ -537,23 +537,6 @@ void *drm_gem_cma_prime_vmap(struct drm_gem_object *obj)
}
EXPORT_SYMBOL_GPL(drm_gem_cma_prime_vmap);
-/**
- * drm_gem_cma_prime_vunmap - unmap a CMA GEM object from the kernel's virtual
- * address space
- * @obj: GEM object
- * @vaddr: kernel virtual address where the CMA GEM object was mapped
- *
- * This function removes a buffer exported via DRM PRIME from the kernel's
- * virtual address space. This is a no-op because CMA buffers cannot be
- * unmapped from kernel space. Drivers using the CMA helpers should set this
- * as their _gem_object_funcs.vunmap callback.
- */
-void drm_gem_cma_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
-{
- /* Nothing to do */
-}
-EXPORT_SYMBOL_GPL(drm_gem_cma_prime_vunmap);
-
static const struct drm_gem_object_funcs drm_gem_cma_default_funcs = {
.free = drm_gem_cma_free_object,
.print_info = drm_gem_cma_print_info,
diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
index f432278173cd..557f0d1e6437 100644
--- a/drivers/gpu/drm/vc4/vc4_bo.c
+++ b/drivers/gpu/drm/vc4/vc4_bo.c
@@ -387,7 +387,6 @@ static const struct drm_gem_object_funcs
vc4_gem_object_funcs = {
.export = vc4_prime_export,
.get_sg_table = drm_gem_cma_prime_get_sg_table,
.vmap = vc4_prime_vmap,
- .vunmap = drm_gem_cma_prime_vunmap,
.vm_ops = _vm_ops,
};
diff --git a/include/drm/drm_gem_cma_helper.h b/include/drm/drm_gem_cma_helper.h
index 2bfa2502607a..a064b0d1c480 100644
--- a/include/drm/drm_gem_cma_helper.h
+++ b/include/drm/drm_gem_cma_helper.h
@@ -104,7 +104,6 @@ drm_gem_cma_prime_import_sg_table(struct drm_device *dev,
int drm_gem_cma_prime_mmap(struct drm_gem_object *obj,
struct vm_area_struct *vma);
void *drm_gem_cma_prime_vmap(struct drm_gem_object *obj);
-void drm_gem_cma_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
struct drm_gem_object *
drm_gem_cma_create_object_default_funcs(struct drm_device *dev, size_t size);
--
2.29.0
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RE: [PATCH] drm/amdgpu: Add kernel parameter to force no xgmi
[AMD Public Use]
Please ignore this patch, it should be in a different branch. As PCIe p2p is
not supported in upstream.
Regards,
Alex Sierra
> -Original Message-
> From: amd-gfx On Behalf Of
> Sierra Guiza, Alejandro (Alex)
> Sent: Wednesday, October 28, 2020 1:09 PM
> To: Koenig, Christian ; amd-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Add kernel parameter to force no xgmi
>
>
> On 10/28/2020 9:58 AM, Christian König wrote:
> > Am 28.10.20 um 15:55 schrieb Alex Sierra:
> >> By enabling this parameter, the system will be forced to use pcie
> >> interface only for p2p transactions.
> >
> > Better name that amdgpu_xgmi with a default value of enabled.
> >
> > Or maybe add another bit value for amdgpu_vm_debug instead.
>
> Ack
>
> Regards,
> Alex Sierra
>
> >
> >
> >>
> >> Signed-off-by: Alex Sierra
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +
> >> 3 files changed, 11 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> index ba65d4f2ab67..3645f00e9f61 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> @@ -188,6 +188,7 @@ extern int amdgpu_discovery;
> >> extern int amdgpu_mes;
> >> extern int amdgpu_noretry;
> >> extern int amdgpu_force_asic_type;
> >> +extern int amdgpu_force_no_xgmi;
> >> #ifdef CONFIG_HSA_AMD
> >> extern int sched_policy;
> >> extern bool debug_evictions;
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> index 1fe850e0a94d..0a5d97a84017 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> @@ -2257,7 +2257,7 @@ static int amdgpu_device_ip_init(struct
> >> amdgpu_device *adev)
> >> if (r)
> >> goto init_failed;
> >> - if (adev->gmc.xgmi.num_physical_nodes > 1)
> >> + if (!amdgpu_force_no_xgmi && adev-
> >gmc.xgmi.num_physical_nodes >
> >> +1)
> >
> > Mhm, this will most likely cause problems. You still need to add the
> > device to the hive because otherwise GPU won't work.
>
> What kind of problems? So far, I have validated this using a system with
> multiple devices and running ./rocm_bandwidth_test -t. With and without
> the parameter set.
>
> Regards,
> Alex Sierra
>
> >
> > Apart from that sounds like a good idea in general.
> >
> > Christian.
> >
> >> amdgpu_xgmi_add_device(adev);
> >> amdgpu_amdkfd_device_init(adev);
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> index 4b78ecfd35f7..22485067cf31 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> @@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
> >> int amdgpu_tmz = 0;
> >> int amdgpu_reset_method = -1; /* auto */
> >> int amdgpu_num_kcq = -1;
> >> +int amdgpu_force_no_xgmi = 0;
> >> struct amdgpu_mgpu_info mgpu_info = {
> >> .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
> >> @@ -522,6 +523,14 @@ module_param_named(ras_enable,
> >> amdgpu_ras_enable, int, 0444);
> >> MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable
> (default
> >> 0x), only valid when ras_enable == 1");
> >> module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
> >> +/**
> >> + * DOC: force_no_xgmi (uint)
> >> + * Forces not to use xgmi interface (0 = disable, 1 = enable).
> >> + * Default is 0 (disabled).
> >> + */
> >> +MODULE_PARM_DESC(force_no_xgmi, "Force not to use xgmi
> interface");
> >> +module_param_named(force_no_xgmi, amdgpu_force_no_xgmi, int,
> 0600);
> >> +
> >> /**
> >> * DOC: si_support (int)
> >> * Set SI support driver. This parameter works after set config
> >> CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
> >
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[PATCH][next] drm/amd/pm: fix out-of-bound read on pptable->SkuReserved
From: Colin Ian King
A recent change added two uint16_t elements to PPTable_t and reduced the
uint32_t array down to 8 elements. This results in the dev_info printing
of pptable->SkuReserved[8] accessing a value that is out-of-range on
array SkuReserved. The array has been shrunk by 1 element, so remove
this extraneous dev_info message.
Addresses-Coverity: ("Out-of-bounds read")
Fixes: 1dc3c5a95b08 ("drm/amd/pm: update driver if file for sienna cichlid")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index fa3842f460fc..0600befc6e4c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2279,7 +2279,6 @@ static void sienna_cichlid_dump_pptable(struct
smu_context *smu)
dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n",
pptable->SkuReserved[5]);
dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n",
pptable->SkuReserved[6]);
dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n",
pptable->SkuReserved[7]);
- dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n",
pptable->SkuReserved[8]);
dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n",
pptable->GamingClk[0]);
dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n",
pptable->GamingClk[1]);
--
2.27.0
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[PATCH -next] drm/amd/display: remove useless if/else
Fix the following coccinelle report:
./drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:1367:3-5:
WARNING: possible condition with no effect (if == else)
Both branches are the same, so remove the if/else altogether.
Fixes: 81875979f0b2 ("drm/amd/display: Remove extra pairs of parentheses in
dce_calcs.c")
Reported-by: Hulk Robot
Signed-off-by: Zou Wei
---
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 2c6db37..e4f29cd 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -1364,13 +1364,10 @@ static void calculate_bandwidth(
/*if stutter and dram clock state change are gated before cursor then
the cursor latency hiding does not limit stutter or dram clock state change*/
for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
if (data->enable[i]) {
- if
(dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1) {
- data->maximum_latency_hiding[i] =
bw_add(data->minimum_latency_hiding[i], bw_mul(bw_frc_to_fixed(5, 10),
data->total_dmifmc_urgent_latency));
- }
- else {
- /*maximum_latency_hiding(i) =
minimum_latency_hiding(i) + 1 / vsr(i) * h_total(i) / pixel_rate(i) + 0.5 *
total_dmifmc_urgent_latency*/
- data->maximum_latency_hiding[i] =
bw_add(data->minimum_latency_hiding[i], bw_mul(bw_frc_to_fixed(5, 10),
data->total_dmifmc_urgent_latency));
- }
+ /*maximum_latency_hiding(i) = minimum_latency_hiding(i)
+ 1 / vsr(i) **/
+ /* h_total(i) / pixel_rate(i) + 0.5 *
total_dmifmc_urgent_latency*/
+ data->maximum_latency_hiding[i] =
bw_add(data->minimum_latency_hiding[i],
+ bw_mul(bw_frc_to_fixed(5, 10),
data->total_dmifmc_urgent_latency));
data->maximum_latency_hiding_with_cursor[i] =
bw_min2(data->maximum_latency_hiding[i], data->cursor_latency_hiding[i]);
}
}
--
2.6.2
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Potential freesync Arithmetic Issue
While looking at the following commit, I noticed what might be an arithmetic issue potentially stemming from some merge/patch conflict resolution. commit ad339f69114a6a145fc94d44376851c53dee3475 Author: Jaehyun Chung Date: Thu Jun 18 15:27:35 2020 -0400 drm/amd/display: Fix incorrect rounding for 10Hz refresh range [Why] In cases where refresh range is slightly below 10, FreeSync is not active or supported. Need to round values before checking refresh range in order to have FreeSync supported in these cases. [How] Remove redundant values and round values before checking valid refresh range. Signed-off-by: Jaehyun Chung Reviewed-by: Aric Cyr Acked-by: Anthony Koo Acked-by: Eryk Brol Signed-off-by: Alex Deucher There appears to be an errant plus sign when calculating the refresh_range - https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/amd/display/modules/freesync/freesync.c?h=v5.10-rc1#n948 refresh_range = div_u64(in_out_vrr->max_refresh_in_uhz + 50, 100) - + div_u64(in_out_vrr->min_refresh_in_uhz + 50, 100); I am unfamiliar with the freesync codebase so I opted to present the potential issue here as opposed to preparing a patch. Thanks. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Add kernel parameter to force no xgmi
On 10/28/2020 9:58 AM, Christian König wrote:
Am 28.10.20 um 15:55 schrieb Alex Sierra:
By enabling this parameter, the system will be forced to use pcie
interface only for p2p transactions.
Better name that amdgpu_xgmi with a default value of enabled.
Or maybe add another bit value for amdgpu_vm_debug instead.
Ack
Regards,
Alex Sierra
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ba65d4f2ab67..3645f00e9f61 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -188,6 +188,7 @@ extern int amdgpu_discovery;
extern int amdgpu_mes;
extern int amdgpu_noretry;
extern int amdgpu_force_asic_type;
+extern int amdgpu_force_no_xgmi;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
extern bool debug_evictions;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1fe850e0a94d..0a5d97a84017 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2257,7 +2257,7 @@ static int amdgpu_device_ip_init(struct
amdgpu_device *adev)
if (r)
goto init_failed;
- if (adev->gmc.xgmi.num_physical_nodes > 1)
+ if (!amdgpu_force_no_xgmi && adev->gmc.xgmi.num_physical_nodes > 1)
Mhm, this will most likely cause problems. You still need to add the
device to the hive because otherwise GPU won't work.
What kind of problems? So far, I have validated this using a system with
multiple devices and running ./rocm_bandwidth_test -t. With and without
the parameter set.
Regards,
Alex Sierra
Apart from that sounds like a good idea in general.
Christian.
amdgpu_xgmi_add_device(adev);
amdgpu_amdkfd_device_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 4b78ecfd35f7..22485067cf31 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
int amdgpu_tmz = 0;
int amdgpu_reset_method = -1; /* auto */
int amdgpu_num_kcq = -1;
+int amdgpu_force_no_xgmi = 0;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -522,6 +523,14 @@ module_param_named(ras_enable,
amdgpu_ras_enable, int, 0444);
MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default
0x), only valid when ras_enable == 1");
module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
+/**
+ * DOC: force_no_xgmi (uint)
+ * Forces not to use xgmi interface (0 = disable, 1 = enable).
+ * Default is 0 (disabled).
+ */
+MODULE_PARM_DESC(force_no_xgmi, "Force not to use xgmi interface");
+module_param_named(force_no_xgmi, amdgpu_force_no_xgmi, int, 0600);
+
/**
* DOC: si_support (int)
* Set SI support driver. This parameter works after set config
CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
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Re: [PATCH] drm/amdkfd: Fix getting unique_id in topology
Am 2020-10-28 um 1:11 p.m. schrieb Kent Russell:
> Since the unique_id is now obtained in amdgpu in smu_late_init,
> topology misses getting the value during KFD device initialization.
> To work around this, we use amdgpu_amdkfd_get_unique_id to get
> the unique_id at read time. Due to this, we can remove unique_id from
> the kfd_dev structure, since we only need it in the KFD node properties
> struct
>
> Signed-off-by: Kent Russell
Reviewed-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 --
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ---
> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +-
> 3 files changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index 14c3f148735b..50922ff2927b 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -757,8 +757,6 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
>
> kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd);
>
> - kfd->unique_id = amdgpu_amdkfd_get_unique_id(kfd->kgd);
> -
> kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd);
>
> if (kfd_interrupt_init(kfd)) {
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> index b7be5c5751b7..e2ebd5a1d4de 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> @@ -292,9 +292,6 @@ struct kfd_dev {
> /* xGMI */
> uint64_t hive_id;
>
> - /* UUID */
> - uint64_t unique_id;
> -
> bool pci_atomic_requested;
>
> /* Use IOMMU v2 flag */
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> index 3f2aa055c32c..a3fc23873819 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> @@ -1340,7 +1340,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
> dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ?
> amdgpu_amdkfd_get_num_gws(dev->gpu->kgd) : 0;
> dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm);
> - dev->node_props.unique_id = gpu->unique_id;
> + dev->node_props.unique_id = amdgpu_amdkfd_get_unique_id(dev->gpu->kgd);
>
> kfd_fill_mem_clk_max_info(dev);
> kfd_fill_iolink_non_crat_info(dev);
___
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Re: [PATCH] drm/amdgpu/powerplay: Only apply optimized mclk dpm policy on polaris
Reviewed-by: Luben Tuikov
I assume that the default ("else") case is what is wanted
by this patch and has been vetted-i.e. it what fixes it.
Regards,
Luben
On 2020-10-28 11:08, Alex Deucher wrote:
> Leads to improper dpm on older parts.
>
> Bug:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1353data=04%7C01%7Cluben.tuikov%40amd.com%7C154766ca87eb40cce45508d87b534dba%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637394945025356066%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=RB%2FDlyoqyasJWWkmB6dL0jxzVM9Auc223YNkEmpIj54%3Dreserved=0
> Fixes: 8d89b96fe797 ("drm/amd/powerplay: optimize the mclk dpm policy
> settings")
> Signed-off-by: Alex Deucher
> ---
> .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 30 +++
> 1 file changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index 49db61a89505..d642dc95e9ea 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -1713,18 +1713,24 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr
> *hwmgr)
> data->current_profile_setting.sclk_down_hyst = 100;
> data->current_profile_setting.sclk_activity =
> SMU7_SCLK_TARGETACTIVITY_DFLT;
> data->current_profile_setting.bupdate_mclk = 1;
> - if (adev->gmc.vram_width == 256) {
> - data->current_profile_setting.mclk_up_hyst = 10;
> - data->current_profile_setting.mclk_down_hyst = 60;
> - data->current_profile_setting.mclk_activity = 25;
> - } else if (adev->gmc.vram_width == 128) {
> - data->current_profile_setting.mclk_up_hyst = 5;
> - data->current_profile_setting.mclk_down_hyst = 16;
> - data->current_profile_setting.mclk_activity = 20;
> - } else if (adev->gmc.vram_width == 64) {
> - data->current_profile_setting.mclk_up_hyst = 3;
> - data->current_profile_setting.mclk_down_hyst = 16;
> - data->current_profile_setting.mclk_activity = 20;
> + if (hwmgr->chip_id >= CHIP_POLARIS10) {
> + if (adev->gmc.vram_width == 256) {
> + data->current_profile_setting.mclk_up_hyst = 10;
> + data->current_profile_setting.mclk_down_hyst = 60;
> + data->current_profile_setting.mclk_activity = 25;
> + } else if (adev->gmc.vram_width == 128) {
> + data->current_profile_setting.mclk_up_hyst = 5;
> + data->current_profile_setting.mclk_down_hyst = 16;
> + data->current_profile_setting.mclk_activity = 20;
> + } else if (adev->gmc.vram_width == 64) {
> + data->current_profile_setting.mclk_up_hyst = 3;
> + data->current_profile_setting.mclk_down_hyst = 16;
> + data->current_profile_setting.mclk_activity = 20;
> + }
> + } else {
> + data->current_profile_setting.mclk_up_hyst = 0;
> + data->current_profile_setting.mclk_down_hyst = 100;
> + data->current_profile_setting.mclk_activity =
> SMU7_MCLK_TARGETACTIVITY_DFLT;
> }
> hwmgr->workload_mask = 1 <<
> hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
> hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
>
___
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[PATCH] drm/amdkfd: Fix getting unique_id in topology
Since the unique_id is now obtained in amdgpu in smu_late_init,
topology misses getting the value during KFD device initialization.
To work around this, we use amdgpu_amdkfd_get_unique_id to get
the unique_id at read time. Due to this, we can remove unique_id from
the kfd_dev structure, since we only need it in the KFD node properties
struct
Signed-off-by: Kent Russell
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 --
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +-
3 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 14c3f148735b..50922ff2927b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -757,8 +757,6 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd);
- kfd->unique_id = amdgpu_amdkfd_get_unique_id(kfd->kgd);
-
kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd);
if (kfd_interrupt_init(kfd)) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index b7be5c5751b7..e2ebd5a1d4de 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -292,9 +292,6 @@ struct kfd_dev {
/* xGMI */
uint64_t hive_id;
- /* UUID */
- uint64_t unique_id;
-
bool pci_atomic_requested;
/* Use IOMMU v2 flag */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 3f2aa055c32c..a3fc23873819 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1340,7 +1340,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ?
amdgpu_amdkfd_get_num_gws(dev->gpu->kgd) : 0;
dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm);
- dev->node_props.unique_id = gpu->unique_id;
+ dev->node_props.unique_id = amdgpu_amdkfd_get_unique_id(dev->gpu->kgd);
kfd_fill_mem_clk_max_info(dev);
kfd_fill_iolink_non_crat_info(dev);
--
2.17.1
___
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RE: [PATCH 2/2] drm/amdkfd: Change unique_id to print hex format
[AMD Public Use]
amdgpu actually prints it as hex:
return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
But either way, we can address it in rocminfo if anyone complains. Thanks for
the review!
Kent
> -Original Message-
> From: Kuehling, Felix
> Sent: Wednesday, October 28, 2020 12:11 PM
> To: Russell, Kent ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/2] drm/amdkfd: Change unique_id to print hex format
>
> So rocm-smi reads the decimal and converts it to hex? Then changing KFD
> will break rocm-smi. If you want to fix rocminfo, you'll need to fix it
> in the rocminfo code to do the conversion to hex.
>
> Regards,
> Felix
>
> Am 2020-10-28 um 12:02 p.m. schrieb Russell, Kent:
> > [AMD Public Use]
> >
> > rocminfo uses it, but that's all that I am aware of. I can drop this though
> > and stick with
> patch1, I just didn't know if we'd end up getting complaints of:
> > "Well, rocm-smi (amdgpu) says that the unique_id is F, while rocminfo
> > (amdkfd) says that
> the unique_id is 16" . Probably too late to try to change it now though, as
> you pointed out.
> >
> > Kent
> >
> >> -Original Message-
> >> From: Kuehling, Felix
> >> Sent: Wednesday, October 28, 2020 11:55 AM
> >> To: amd-gfx@lists.freedesktop.org; Russell, Kent
> >> Subject: Re: [PATCH 2/2] drm/amdkfd: Change unique_id to print hex format
> >>
> >> This is an ABI-breaking change. Is any user mode code using this already?
> >>
> >> Regards,
> >> Felix
> >>
> >> Am 2020-10-28 um 11:22 a.m. schrieb Kent Russell:
> >>> amdgpu's unique_id prints in hex format, so change topology's printout
> >>> to hex by adding a new sysfs_print macro specifically for hex output,
> >>> and use it for unique_id
> >>>
> >>> Signed-off-by: Kent Russell
> >>> ---
> >>> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 +++-
> >>> 1 file changed, 3 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> >> b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> >>> index a3fc23873819..d13c68c52bbc 100644
> >>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> >>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> >>> @@ -217,6 +217,8 @@ struct kfd_topology_device
> >>> *kfd_create_topology_device(
> >>> sysfs_show_gen_prop(buffer, offs, "%s %u\n", name, value)
> >>> #define sysfs_show_64bit_prop(buffer, offs, name, value) \
> >>> sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value)
> >>> +#define sysfs_show_64bit_prop_hex(buffer, offs, name, value) \
> >>> + sysfs_show_gen_prop(buffer, offs, "%s %llx\n", name, value)
> >>> #define sysfs_show_32bit_val(buffer, offs, value) \
> >>> sysfs_show_gen_prop(buffer, offs, "%u\n", value)
> >>> #define sysfs_show_str_val(buffer, offs, value) \
> >>> @@ -497,7 +499,7 @@ static ssize_t node_show(struct kobject *kobj, struct
> >>> attribute
> >> *attr,
> >>> dev->node_props.num_sdma_queues_per_engine);
> >>> sysfs_show_32bit_prop(buffer, offs, "num_cp_queues",
> >>> dev->node_props.num_cp_queues);
> >>> - sysfs_show_64bit_prop(buffer, offs, "unique_id",
> >>> + sysfs_show_64bit_prop_hex(buffer, offs, "unique_id",
> >>> dev->node_props.unique_id);
> >>>
> >>> if (dev->gpu) {
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RE: [PATCH 1/2] drm/amdkfd: Fix getting unique_id in topology
[AMD Public Use] Right, will do! Kent > -Original Message- > From: Kuehling, Felix > Sent: Wednesday, October 28, 2020 12:16 PM > To: Russell, Kent ; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 1/2] drm/amdkfd: Fix getting unique_id in topology > > Please also remove the broken code that initializes gpu->unique_id and > remove the unique_id field from the structure. > > Regards, > Felix > > Am 2020-10-28 um 11:22 a.m. schrieb Kent Russell: > > Since the unique_id is now obtained in amdgpu in smu_late_init, > > topology's device addition is now happening before the unique_id is > > saved, thus topology misses it. To work around this, we use the > > amdgpu_amdkfd_get_unique_id to get the unique_id at read time. > > > > Signed-off-by: Kent Russell > > --- > > drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > > index 3f2aa055c32c..a3fc23873819 100644 > > --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > > @@ -1340,7 +1340,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu) > > dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ? > > amdgpu_amdkfd_get_num_gws(dev->gpu->kgd) : 0; > > dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm); > > - dev->node_props.unique_id = gpu->unique_id; > > + dev->node_props.unique_id = amdgpu_amdkfd_get_unique_id(dev->gpu->kgd); > > > > kfd_fill_mem_clk_max_info(dev); > > kfd_fill_iolink_non_crat_info(dev); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amdkfd: Fix getting unique_id in topology
Please also remove the broken code that initializes gpu->unique_id and remove the unique_id field from the structure. Regards, Felix Am 2020-10-28 um 11:22 a.m. schrieb Kent Russell: > Since the unique_id is now obtained in amdgpu in smu_late_init, > topology's device addition is now happening before the unique_id is > saved, thus topology misses it. To work around this, we use the > amdgpu_amdkfd_get_unique_id to get the unique_id at read time. > > Signed-off-by: Kent Russell > --- > drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > index 3f2aa055c32c..a3fc23873819 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > @@ -1340,7 +1340,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu) > dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ? > amdgpu_amdkfd_get_num_gws(dev->gpu->kgd) : 0; > dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm); > - dev->node_props.unique_id = gpu->unique_id; > + dev->node_props.unique_id = amdgpu_amdkfd_get_unique_id(dev->gpu->kgd); > > kfd_fill_mem_clk_max_info(dev); > kfd_fill_iolink_non_crat_info(dev); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdkfd: Change unique_id to print hex format
So rocm-smi reads the decimal and converts it to hex? Then changing KFD
will break rocm-smi. If you want to fix rocminfo, you'll need to fix it
in the rocminfo code to do the conversion to hex.
Regards,
Felix
Am 2020-10-28 um 12:02 p.m. schrieb Russell, Kent:
> [AMD Public Use]
>
> rocminfo uses it, but that's all that I am aware of. I can drop this though
> and stick with patch1, I just didn't know if we'd end up getting complaints
> of:
> "Well, rocm-smi (amdgpu) says that the unique_id is F, while rocminfo
> (amdkfd) says that the unique_id is 16" . Probably too late to try to change
> it now though, as you pointed out.
>
> Kent
>
>> -Original Message-
>> From: Kuehling, Felix
>> Sent: Wednesday, October 28, 2020 11:55 AM
>> To: amd-gfx@lists.freedesktop.org; Russell, Kent
>> Subject: Re: [PATCH 2/2] drm/amdkfd: Change unique_id to print hex format
>>
>> This is an ABI-breaking change. Is any user mode code using this already?
>>
>> Regards,
>> Felix
>>
>> Am 2020-10-28 um 11:22 a.m. schrieb Kent Russell:
>>> amdgpu's unique_id prints in hex format, so change topology's printout
>>> to hex by adding a new sysfs_print macro specifically for hex output,
>>> and use it for unique_id
>>>
>>> Signed-off-by: Kent Russell
>>> ---
>>> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 +++-
>>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
>>> index a3fc23873819..d13c68c52bbc 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
>>> @@ -217,6 +217,8 @@ struct kfd_topology_device *kfd_create_topology_device(
>>> sysfs_show_gen_prop(buffer, offs, "%s %u\n", name, value)
>>> #define sysfs_show_64bit_prop(buffer, offs, name, value) \
>>> sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value)
>>> +#define sysfs_show_64bit_prop_hex(buffer, offs, name, value) \
>>> + sysfs_show_gen_prop(buffer, offs, "%s %llx\n", name, value)
>>> #define sysfs_show_32bit_val(buffer, offs, value) \
>>> sysfs_show_gen_prop(buffer, offs, "%u\n", value)
>>> #define sysfs_show_str_val(buffer, offs, value) \
>>> @@ -497,7 +499,7 @@ static ssize_t node_show(struct kobject *kobj, struct
>>> attribute
>> *attr,
>>> dev->node_props.num_sdma_queues_per_engine);
>>> sysfs_show_32bit_prop(buffer, offs, "num_cp_queues",
>>> dev->node_props.num_cp_queues);
>>> - sysfs_show_64bit_prop(buffer, offs, "unique_id",
>>> + sysfs_show_64bit_prop_hex(buffer, offs, "unique_id",
>>> dev->node_props.unique_id);
>>>
>>> if (dev->gpu) {
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RE: [PATCH 2/2] drm/amdkfd: Change unique_id to print hex format
[AMD Public Use]
rocminfo uses it, but that's all that I am aware of. I can drop this though and
stick with patch1, I just didn't know if we'd end up getting complaints of:
"Well, rocm-smi (amdgpu) says that the unique_id is F, while rocminfo (amdkfd)
says that the unique_id is 16" . Probably too late to try to change it now
though, as you pointed out.
Kent
> -Original Message-
> From: Kuehling, Felix
> Sent: Wednesday, October 28, 2020 11:55 AM
> To: amd-gfx@lists.freedesktop.org; Russell, Kent
> Subject: Re: [PATCH 2/2] drm/amdkfd: Change unique_id to print hex format
>
> This is an ABI-breaking change. Is any user mode code using this already?
>
> Regards,
> Felix
>
> Am 2020-10-28 um 11:22 a.m. schrieb Kent Russell:
> > amdgpu's unique_id prints in hex format, so change topology's printout
> > to hex by adding a new sysfs_print macro specifically for hex output,
> > and use it for unique_id
> >
> > Signed-off-by: Kent Russell
> > ---
> > drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > index a3fc23873819..d13c68c52bbc 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > @@ -217,6 +217,8 @@ struct kfd_topology_device *kfd_create_topology_device(
> > sysfs_show_gen_prop(buffer, offs, "%s %u\n", name, value)
> > #define sysfs_show_64bit_prop(buffer, offs, name, value) \
> > sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value)
> > +#define sysfs_show_64bit_prop_hex(buffer, offs, name, value) \
> > + sysfs_show_gen_prop(buffer, offs, "%s %llx\n", name, value)
> > #define sysfs_show_32bit_val(buffer, offs, value) \
> > sysfs_show_gen_prop(buffer, offs, "%u\n", value)
> > #define sysfs_show_str_val(buffer, offs, value) \
> > @@ -497,7 +499,7 @@ static ssize_t node_show(struct kobject *kobj, struct
> > attribute
> *attr,
> > dev->node_props.num_sdma_queues_per_engine);
> > sysfs_show_32bit_prop(buffer, offs, "num_cp_queues",
> > dev->node_props.num_cp_queues);
> > - sysfs_show_64bit_prop(buffer, offs, "unique_id",
> > + sysfs_show_64bit_prop_hex(buffer, offs, "unique_id",
> > dev->node_props.unique_id);
> >
> > if (dev->gpu) {
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Re: [PATCH 2/2] drm/amdkfd: Change unique_id to print hex format
This is an ABI-breaking change. Is any user mode code using this already?
Regards,
Felix
Am 2020-10-28 um 11:22 a.m. schrieb Kent Russell:
> amdgpu's unique_id prints in hex format, so change topology's printout
> to hex by adding a new sysfs_print macro specifically for hex output,
> and use it for unique_id
>
> Signed-off-by: Kent Russell
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> index a3fc23873819..d13c68c52bbc 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> @@ -217,6 +217,8 @@ struct kfd_topology_device *kfd_create_topology_device(
> sysfs_show_gen_prop(buffer, offs, "%s %u\n", name, value)
> #define sysfs_show_64bit_prop(buffer, offs, name, value) \
> sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value)
> +#define sysfs_show_64bit_prop_hex(buffer, offs, name, value) \
> + sysfs_show_gen_prop(buffer, offs, "%s %llx\n", name, value)
> #define sysfs_show_32bit_val(buffer, offs, value) \
> sysfs_show_gen_prop(buffer, offs, "%u\n", value)
> #define sysfs_show_str_val(buffer, offs, value) \
> @@ -497,7 +499,7 @@ static ssize_t node_show(struct kobject *kobj, struct
> attribute *attr,
> dev->node_props.num_sdma_queues_per_engine);
> sysfs_show_32bit_prop(buffer, offs, "num_cp_queues",
> dev->node_props.num_cp_queues);
> - sysfs_show_64bit_prop(buffer, offs, "unique_id",
> + sysfs_show_64bit_prop_hex(buffer, offs, "unique_id",
> dev->node_props.unique_id);
>
> if (dev->gpu) {
___
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RE: [PATCH] drm/amdgpu: Add kernel parameter to force no xgmi
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: amd-gfx On Behalf Of
> Luben Tuikov
> Sent: Wednesday, October 28, 2020 11:12 AM
> To: Sierra Guiza, Alejandro (Alex) ; amd-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Add kernel parameter to force no xgmi
>
> [CAUTION: External Email]
>
> On 2020-10-28 10:55, Alex Sierra wrote:
> > By enabling this parameter, the system will be forced to use pcie
> > interface only for p2p transactions.
> >
> > Signed-off-by: Alex Sierra
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 9 +
> > 3 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index ba65d4f2ab67..3645f00e9f61 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -188,6 +188,7 @@ extern int amdgpu_discovery; extern int
> > amdgpu_mes; extern int amdgpu_noretry; extern int
> > amdgpu_force_asic_type;
> > +extern int amdgpu_force_no_xgmi;
> > #ifdef CONFIG_HSA_AMD
> > extern int sched_policy;
> > extern bool debug_evictions;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 1fe850e0a94d..0a5d97a84017 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -2257,7 +2257,7 @@ static int amdgpu_device_ip_init(struct
> amdgpu_device *adev)
> > if (r)
> > goto init_failed;
> >
> > - if (adev->gmc.xgmi.num_physical_nodes > 1)
> > + if (!amdgpu_force_no_xgmi && adev->gmc.xgmi.num_physical_nodes
> >
> > + 1)
> > amdgpu_xgmi_add_device(adev);
> > amdgpu_amdkfd_device_init(adev);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > index 4b78ecfd35f7..22485067cf31 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > @@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1; int amdgpu_tmz
> =
> > 0; int amdgpu_reset_method = -1; /* auto */ int amdgpu_num_kcq = -1;
> > +int amdgpu_force_no_xgmi = 0;
> >
> > struct amdgpu_mgpu_info mgpu_info = {
> > .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
> > @@ -522,6 +523,14 @@ module_param_named(ras_enable,
> amdgpu_ras_enable,
> > int, 0444); MODULE_PARM_DESC(ras_mask, "Mask of RAS features to
> > enable (default 0x), only valid when ras_enable == 1");
> > module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
> >
> > +/**
> > + * DOC: force_no_xgmi (uint)
> > + * Forces not to use xgmi interface (0 = disable, 1 = enable).
>
> How about using human English here? Perhaps something like,
>
> "Forces not to use" ==> "Disables the use of the XGMI interface ..."
>
> Or, if you use the suggestion Christian posted, you could say something like,
>
> "Enable XGMI for P2P transactions."
I second the use of enable. The fact that we can prevent xGMI init means we
enable it by default.
Thanks,
Jon
>
> Regards,
> Luben
>
> > + * Default is 0 (disabled).
> > + */
> > +MODULE_PARM_DESC(force_no_xgmi, "Force not to use xgmi
> interface");
> > +module_param_named(force_no_xgmi, amdgpu_force_no_xgmi, int,
> 0600);
> > +
> > /**
> > * DOC: si_support (int)
> > * Set SI support driver. This parameter works after set config
> > CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
> >
>
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[PATCH 1/2] drm/amdkfd: Fix getting unique_id in topology
Since the unique_id is now obtained in amdgpu in smu_late_init, topology's device addition is now happening before the unique_id is saved, thus topology misses it. To work around this, we use the amdgpu_amdkfd_get_unique_id to get the unique_id at read time. Signed-off-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 3f2aa055c32c..a3fc23873819 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1340,7 +1340,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu) dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ? amdgpu_amdkfd_get_num_gws(dev->gpu->kgd) : 0; dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm); - dev->node_props.unique_id = gpu->unique_id; + dev->node_props.unique_id = amdgpu_amdkfd_get_unique_id(dev->gpu->kgd); kfd_fill_mem_clk_max_info(dev); kfd_fill_iolink_non_crat_info(dev); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amdkfd: Change unique_id to print hex format
amdgpu's unique_id prints in hex format, so change topology's printout
to hex by adding a new sysfs_print macro specifically for hex output,
and use it for unique_id
Signed-off-by: Kent Russell
---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index a3fc23873819..d13c68c52bbc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -217,6 +217,8 @@ struct kfd_topology_device *kfd_create_topology_device(
sysfs_show_gen_prop(buffer, offs, "%s %u\n", name, value)
#define sysfs_show_64bit_prop(buffer, offs, name, value) \
sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value)
+#define sysfs_show_64bit_prop_hex(buffer, offs, name, value) \
+ sysfs_show_gen_prop(buffer, offs, "%s %llx\n", name, value)
#define sysfs_show_32bit_val(buffer, offs, value) \
sysfs_show_gen_prop(buffer, offs, "%u\n", value)
#define sysfs_show_str_val(buffer, offs, value) \
@@ -497,7 +499,7 @@ static ssize_t node_show(struct kobject *kobj, struct
attribute *attr,
dev->node_props.num_sdma_queues_per_engine);
sysfs_show_32bit_prop(buffer, offs, "num_cp_queues",
dev->node_props.num_cp_queues);
- sysfs_show_64bit_prop(buffer, offs, "unique_id",
+ sysfs_show_64bit_prop_hex(buffer, offs, "unique_id",
dev->node_props.unique_id);
if (dev->gpu) {
--
2.17.1
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Re: [PATCH] drm/amdgpu: Add kernel parameter to force no xgmi
On 2020-10-28 10:55, Alex Sierra wrote:
> By enabling this parameter, the system will be forced to use pcie
> interface only for p2p transactions.
>
> Signed-off-by: Alex Sierra
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 9 +
> 3 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index ba65d4f2ab67..3645f00e9f61 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -188,6 +188,7 @@ extern int amdgpu_discovery;
> extern int amdgpu_mes;
> extern int amdgpu_noretry;
> extern int amdgpu_force_asic_type;
> +extern int amdgpu_force_no_xgmi;
> #ifdef CONFIG_HSA_AMD
> extern int sched_policy;
> extern bool debug_evictions;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 1fe850e0a94d..0a5d97a84017 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2257,7 +2257,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device
> *adev)
> if (r)
> goto init_failed;
>
> - if (adev->gmc.xgmi.num_physical_nodes > 1)
> + if (!amdgpu_force_no_xgmi && adev->gmc.xgmi.num_physical_nodes > 1)
> amdgpu_xgmi_add_device(adev);
> amdgpu_amdkfd_device_init(adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 4b78ecfd35f7..22485067cf31 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
> int amdgpu_tmz = 0;
> int amdgpu_reset_method = -1; /* auto */
> int amdgpu_num_kcq = -1;
> +int amdgpu_force_no_xgmi = 0;
>
> struct amdgpu_mgpu_info mgpu_info = {
> .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
> @@ -522,6 +523,14 @@ module_param_named(ras_enable, amdgpu_ras_enable, int,
> 0444);
> MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default
> 0x), only valid when ras_enable == 1");
> module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
>
> +/**
> + * DOC: force_no_xgmi (uint)
> + * Forces not to use xgmi interface (0 = disable, 1 = enable).
How about using human English here? Perhaps something like,
"Forces not to use" ==> "Disables the use of the XGMI interface ..."
Or, if you use the suggestion Christian posted, you could say something like,
"Enable XGMI for P2P transactions."
Regards,
Luben
> + * Default is 0 (disabled).
> + */
> +MODULE_PARM_DESC(force_no_xgmi, "Force not to use xgmi interface");
> +module_param_named(force_no_xgmi, amdgpu_force_no_xgmi, int, 0600);
> +
> /**
> * DOC: si_support (int)
> * Set SI support driver. This parameter works after set config
> CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
>
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[PATCH] drm/amdgpu/powerplay: Only apply optimized mclk dpm policy on polaris
Leads to improper dpm on older parts.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1353
Fixes: 8d89b96fe797 ("drm/amd/powerplay: optimize the mclk dpm policy settings")
Signed-off-by: Alex Deucher
---
.../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 30 +++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 49db61a89505..d642dc95e9ea 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1713,18 +1713,24 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr
*hwmgr)
data->current_profile_setting.sclk_down_hyst = 100;
data->current_profile_setting.sclk_activity =
SMU7_SCLK_TARGETACTIVITY_DFLT;
data->current_profile_setting.bupdate_mclk = 1;
- if (adev->gmc.vram_width == 256) {
- data->current_profile_setting.mclk_up_hyst = 10;
- data->current_profile_setting.mclk_down_hyst = 60;
- data->current_profile_setting.mclk_activity = 25;
- } else if (adev->gmc.vram_width == 128) {
- data->current_profile_setting.mclk_up_hyst = 5;
- data->current_profile_setting.mclk_down_hyst = 16;
- data->current_profile_setting.mclk_activity = 20;
- } else if (adev->gmc.vram_width == 64) {
- data->current_profile_setting.mclk_up_hyst = 3;
- data->current_profile_setting.mclk_down_hyst = 16;
- data->current_profile_setting.mclk_activity = 20;
+ if (hwmgr->chip_id >= CHIP_POLARIS10) {
+ if (adev->gmc.vram_width == 256) {
+ data->current_profile_setting.mclk_up_hyst = 10;
+ data->current_profile_setting.mclk_down_hyst = 60;
+ data->current_profile_setting.mclk_activity = 25;
+ } else if (adev->gmc.vram_width == 128) {
+ data->current_profile_setting.mclk_up_hyst = 5;
+ data->current_profile_setting.mclk_down_hyst = 16;
+ data->current_profile_setting.mclk_activity = 20;
+ } else if (adev->gmc.vram_width == 64) {
+ data->current_profile_setting.mclk_up_hyst = 3;
+ data->current_profile_setting.mclk_down_hyst = 16;
+ data->current_profile_setting.mclk_activity = 20;
+ }
+ } else {
+ data->current_profile_setting.mclk_up_hyst = 0;
+ data->current_profile_setting.mclk_down_hyst = 100;
+ data->current_profile_setting.mclk_activity =
SMU7_MCLK_TARGETACTIVITY_DFLT;
}
hwmgr->workload_mask = 1 <<
hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
--
2.25.4
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Re: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
On Wed, 28 Oct 2020 at 14:03, Quan, Evan wrote: > > [AMD Official Use Only - Internal Distribution Only] > > If it turns out "PCI CONFIG reset" is used, please try the new patch series I > just sent. > https://lists.freedesktop.org/archives/amd-gfx/2020-October/055327.html > https://lists.freedesktop.org/archives/amd-gfx/2020-October/055328.html > https://lists.freedesktop.org/archives/amd-gfx/2020-October/055329.html > https://lists.freedesktop.org/archives/amd-gfx/2020-October/055330.html > https://lists.freedesktop.org/archives/amd-gfx/2020-October/055331.html > > BR > Evan I tested out this patchset, and can confirm that both suspend and hibernate work as expected. - Sandeep ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Add kernel parameter to force no xgmi
Am 28.10.20 um 15:55 schrieb Alex Sierra:
By enabling this parameter, the system will be forced to use pcie
interface only for p2p transactions.
Better name that amdgpu_xgmi with a default value of enabled.
Or maybe add another bit value for amdgpu_vm_debug instead.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 9 +
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ba65d4f2ab67..3645f00e9f61 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -188,6 +188,7 @@ extern int amdgpu_discovery;
extern int amdgpu_mes;
extern int amdgpu_noretry;
extern int amdgpu_force_asic_type;
+extern int amdgpu_force_no_xgmi;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
extern bool debug_evictions;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1fe850e0a94d..0a5d97a84017 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2257,7 +2257,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
if (r)
goto init_failed;
- if (adev->gmc.xgmi.num_physical_nodes > 1)
+ if (!amdgpu_force_no_xgmi && adev->gmc.xgmi.num_physical_nodes > 1)
Mhm, this will most likely cause problems. You still need to add the
device to the hive because otherwise GPU won't work.
Apart from that sounds like a good idea in general.
Christian.
amdgpu_xgmi_add_device(adev);
amdgpu_amdkfd_device_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 4b78ecfd35f7..22485067cf31 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
int amdgpu_tmz = 0;
int amdgpu_reset_method = -1; /* auto */
int amdgpu_num_kcq = -1;
+int amdgpu_force_no_xgmi = 0;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -522,6 +523,14 @@ module_param_named(ras_enable, amdgpu_ras_enable, int,
0444);
MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0x),
only valid when ras_enable == 1");
module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
+/**
+ * DOC: force_no_xgmi (uint)
+ * Forces not to use xgmi interface (0 = disable, 1 = enable).
+ * Default is 0 (disabled).
+ */
+MODULE_PARM_DESC(force_no_xgmi, "Force not to use xgmi interface");
+module_param_named(force_no_xgmi, amdgpu_force_no_xgmi, int, 0600);
+
/**
* DOC: si_support (int)
* Set SI support driver. This parameter works after set config
CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
___
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[PATCH] drm/amdgpu: Add kernel parameter to force no xgmi
By enabling this parameter, the system will be forced to use pcie
interface only for p2p transactions.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 9 +
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ba65d4f2ab67..3645f00e9f61 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -188,6 +188,7 @@ extern int amdgpu_discovery;
extern int amdgpu_mes;
extern int amdgpu_noretry;
extern int amdgpu_force_asic_type;
+extern int amdgpu_force_no_xgmi;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
extern bool debug_evictions;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1fe850e0a94d..0a5d97a84017 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2257,7 +2257,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
if (r)
goto init_failed;
- if (adev->gmc.xgmi.num_physical_nodes > 1)
+ if (!amdgpu_force_no_xgmi && adev->gmc.xgmi.num_physical_nodes > 1)
amdgpu_xgmi_add_device(adev);
amdgpu_amdkfd_device_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 4b78ecfd35f7..22485067cf31 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
int amdgpu_tmz = 0;
int amdgpu_reset_method = -1; /* auto */
int amdgpu_num_kcq = -1;
+int amdgpu_force_no_xgmi = 0;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -522,6 +523,14 @@ module_param_named(ras_enable, amdgpu_ras_enable, int,
0444);
MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default
0x), only valid when ras_enable == 1");
module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
+/**
+ * DOC: force_no_xgmi (uint)
+ * Forces not to use xgmi interface (0 = disable, 1 = enable).
+ * Default is 0 (disabled).
+ */
+MODULE_PARM_DESC(force_no_xgmi, "Force not to use xgmi interface");
+module_param_named(force_no_xgmi, amdgpu_force_no_xgmi, int, 0600);
+
/**
* DOC: si_support (int)
* Set SI support driver. This parameter works after set config
CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
--
2.17.1
___
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Re: [PATCH 1/4] drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINE
On 2020-10-28 10:44, Luben Tuikov wrote:
> On 2020-10-27 11:19, Alex Deucher wrote:
>> On Mon, Oct 26, 2020 at 7:06 PM Luben Tuikov wrote:
>>>
>>> Consolidating DCN seems like a good idea.
>>>
>>> Reviewed-by: Luben Tuikov
>>
>> Is this for the whole series or just this patch?
>
> Sorry, whose series!
"whole" :-)
>
> Regards,
> Luben
>
>>
>> Thanks!
>>
>> Alex
>>
>>>
>>> Regards,
>>> Luben
>>>
>>> On 2020-10-26 12:35 p.m., Alex Deucher wrote:
Ping again?
On Thu, Oct 22, 2020 at 1:31 AM Alex Deucher wrote:
>
> Ping on this series?
>
> Alex
>
> On Fri, Oct 16, 2020 at 12:50 PM Alex Deucher
> wrote:
>>
>> No need for a separate config option at this point.
>>
>> Signed-off-by: Alex Deucher
>> ---
>> drivers/gpu/drm/amd/display/Kconfig | 8
>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 --
>> drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 --
>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 --
>> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 --
>> 5 files changed, 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/Kconfig
>> b/drivers/gpu/drm/amd/display/Kconfig
>> index 93cdcd1ee9ff..cf87133f88e6 100644
>> --- a/drivers/gpu/drm/amd/display/Kconfig
>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>> @@ -17,14 +17,6 @@ config DRM_AMD_DC_DCN
>> help
>> Raven, Navi and Renoir family support for display engine
>>
>> -config DRM_AMD_DC_GREEN_SARDINE
>> - bool "Green Sardine support"
>> - default y
>> - depends on DRM_AMD_DC_DCN
>> -help
>> -Choose this option if you want to have
>> -Green Sardine support for display engine
>> -
>> config DRM_AMD_DC_DCN3_0
>> bool "DCN 3.0 family"
>> depends on DRM_AMD_DC && X86
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 8a90063ac08a..2aa810d3554b 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -100,10 +100,8 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
>> #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
>> MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
>> #endif
>> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
>> #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
>> MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
>> -#endif
>> #if defined(CONFIG_DRM_AMD_DC_DCN3_01)
>> #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
>> MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
>> @@ -985,10 +983,8 @@ static int amdgpu_dm_init(struct amdgpu_device
>> *adev)
>> case CHIP_RAVEN:
>> case CHIP_RENOIR:
>> init_data.flags.gpu_vm_support = true;
>> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
>> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
>> init_data.flags.disable_dmcu = true;
>> -#endif
>> break;
>> default:
>> break;
>> @@ -1289,10 +1285,8 @@ static int dm_dmub_sw_init(struct amdgpu_device
>> *adev)
>> case CHIP_RENOIR:
>> dmub_asic = DMUB_ASIC_DCN21;
>> fw_name_dmub = FIRMWARE_RENOIR_DMUB;
>> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
>> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
>> fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
>> -#endif
>> break;
>> #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
>> case CHIP_SIENNA_CICHLID:
>> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
>> b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
>> index b361dc6c3489..19d97ed6beb8 100644
>> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
>> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
>> @@ -170,12 +170,10 @@ struct clk_mgr *dc_clk_mgr_create(struct
>> dc_context *ctx, struct pp_smu_funcs *p
>> break;
>> }
>>
>> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
>> if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
>> rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
>> break;
>> }
>> -#endif
>> if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
>> rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
>> break;
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>
Re: [PATCH 1/4] drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINE
On 2020-10-27 11:19, Alex Deucher wrote:
> On Mon, Oct 26, 2020 at 7:06 PM Luben Tuikov wrote:
>>
>> Consolidating DCN seems like a good idea.
>>
>> Reviewed-by: Luben Tuikov
>
> Is this for the whole series or just this patch?
Sorry, whose series!
Regards,
Luben
>
> Thanks!
>
> Alex
>
>>
>> Regards,
>> Luben
>>
>> On 2020-10-26 12:35 p.m., Alex Deucher wrote:
>>> Ping again?
>>>
>>> On Thu, Oct 22, 2020 at 1:31 AM Alex Deucher wrote:
Ping on this series?
Alex
On Fri, Oct 16, 2020 at 12:50 PM Alex Deucher
wrote:
>
> No need for a separate config option at this point.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/display/Kconfig | 8
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 --
> drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 --
> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 --
> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 --
> 5 files changed, 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/Kconfig
> b/drivers/gpu/drm/amd/display/Kconfig
> index 93cdcd1ee9ff..cf87133f88e6 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -17,14 +17,6 @@ config DRM_AMD_DC_DCN
> help
> Raven, Navi and Renoir family support for display engine
>
> -config DRM_AMD_DC_GREEN_SARDINE
> - bool "Green Sardine support"
> - default y
> - depends on DRM_AMD_DC_DCN
> -help
> -Choose this option if you want to have
> -Green Sardine support for display engine
> -
> config DRM_AMD_DC_DCN3_0
> bool "DCN 3.0 family"
> depends on DRM_AMD_DC && X86
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 8a90063ac08a..2aa810d3554b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -100,10 +100,8 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
> #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
> MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
> #endif
> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
> #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
> MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
> -#endif
> #if defined(CONFIG_DRM_AMD_DC_DCN3_01)
> #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
> MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
> @@ -985,10 +983,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> case CHIP_RAVEN:
> case CHIP_RENOIR:
> init_data.flags.gpu_vm_support = true;
> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> init_data.flags.disable_dmcu = true;
> -#endif
> break;
> default:
> break;
> @@ -1289,10 +1285,8 @@ static int dm_dmub_sw_init(struct amdgpu_device
> *adev)
> case CHIP_RENOIR:
> dmub_asic = DMUB_ASIC_DCN21;
> fw_name_dmub = FIRMWARE_RENOIR_DMUB;
> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
> -#endif
> break;
> #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
> case CHIP_SIENNA_CICHLID:
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> index b361dc6c3489..19d97ed6beb8 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> @@ -170,12 +170,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context
> *ctx, struct pp_smu_funcs *p
> break;
> }
>
> -#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
> if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
> rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
> break;
> }
> -#endif
> if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
> rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
> break;
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index ab105f26b511..419c0df08602 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++
Re: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
On Wed, 28 Oct 2020 at 07:01, Quan, Evan wrote: > > [AMD Official Use Only - Internal Distribution Only] > > Hi Sandeep, > > Did you run the tests on Hawaii? > And can you help to confirm which method is used for gpu reset? "BACO reset" > or " PCI CONFIG reset" (you can grep these keywords in dmesg)? > > BR > Evan Yes, I ran the tests on Hawaii. The reset method isn't printed out in dmesg. Is it only printed out during hibernate? When I run the kernel with the above patch, the computer hangs when I attempt to hibernate, and kernel logs don't get written to disk, so I'm unable to figure out which method it's using with your patches. However, I did look at the reset method for earlier kernels, and I believe it's using the PCI config reset method. I will try your other patchset to see if it fixes the issue. - Sandeep ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: cleanup gmc_v9_0_process_interrupt
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Christian
König
Sent: Wednesday, October 28, 2020 9:49 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: cleanup gmc_v9_0_process_interrupt
First of all don't snprintf into a char buffer allocated on the stack with
a constant hubname.
Then cleanup to exit the function early in case of a ratelimit or SRIOV.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 183 +-
1 file changed, 91 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a9929d1b6b3d..0c3421d587e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -510,15 +510,16 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct
amdgpu_device *adev,
}
static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
- struct amdgpu_irq_src *source,
- struct amdgpu_iv_entry *entry)
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
{
- struct amdgpu_vmhub *hub;
bool retry_fault = !!(entry->src_data[1] & 0x80);
uint32_t status = 0, cid = 0, rw = 0;
- u64 addr;
- char hub_name[10];
+ struct amdgpu_task_info task_info;
+ struct amdgpu_vmhub *hub;
const char *mmhub_cid;
+ const char *hub_name;
+ u64 addr;
addr = (u64)entry->src_data[0] << 12;
addr |= ((u64)entry->src_data[1] & 0xf) << 44;
@@ -527,105 +528,103 @@ static int gmc_v9_0_process_interrupt(struct
amdgpu_device *adev,
entry->timestamp))
return 1; /* This also prevents sending it to KFD */
+ /* If it's the first fault for this address, process it normally */
+ if (retry_fault && !in_interrupt() &&
+ amdgpu_vm_handle_fault(adev, entry->pasid, addr))
+ return 1; /* This also prevents sending it to KFD */
+
+ if (!printk_ratelimit())
+ return 0;
+
if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
- snprintf(hub_name, sizeof(hub_name), "mmhub0");
+ hub_name = "mmhub0";
hub = >vmhub[AMDGPU_MMHUB_0];
} else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
- snprintf(hub_name, sizeof(hub_name), "mmhub1");
+ hub_name = "mmhub1";
hub = >vmhub[AMDGPU_MMHUB_1];
} else {
- snprintf(hub_name, sizeof(hub_name), "gfxhub0");
+ hub_name = "gfxhub0";
hub = >vmhub[AMDGPU_GFXHUB_0];
}
- /* If it's the first fault for this address, process it normally */
- if (retry_fault && !in_interrupt() &&
- amdgpu_vm_handle_fault(adev, entry->pasid, addr))
- return 1; /* This also prevents sending it to KFD */
+ memset(_info, 0, sizeof(struct amdgpu_task_info));
+ amdgpu_vm_get_task_info(adev, entry->pasid, _info);
- if (!amdgpu_sriov_vf(adev)) {
- /*
-* Issue a dummy read to wait for the status register to
-* be updated to avoid reading an incorrect value due to
-* the new fast GRBM interface.
-*/
- if (entry->vmid_src == AMDGPU_GFXHUB_0)
- RREG32(hub->vm_l2_pro_fault_status);
-
- status = RREG32(hub->vm_l2_pro_fault_status);
- cid = REG_GET_FIELD(status,
- VM_L2_PROTECTION_FAULT_STATUS, CID);
- rw = REG_GET_FIELD(status,
- VM_L2_PROTECTION_FAULT_STATUS, RW);
- WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
- }
+ dev_err(adev->dev,
+ "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
+ "pasid:%u, for process %s pid %d thread %s pid %d)\n",
+ hub_name, retry_fault ? "retry" : "no-retry",
+ entry->src_id, entry->ring_id, entry->vmid,
+ entry->pasid, task_info.process_name, task_info.tgid,
+ task_info.task_name, task_info.pid);
+ dev_err(adev->dev, " in page starting at address 0x%016llx from client
%d\n",
+ addr, entry->client_id);
- if (printk_ratelimit()) {
- struct amdgpu_task_info task_info;
-
- memset(_info, 0, sizeof(struct amdgpu_task_info));
- amdgpu_vm_get_task_info(adev, entry->pasid, _info);
-
- dev_err(adev->dev,
- "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
- "pasid:%u, for process %s pid %d thread %s pid %d)\n",
- hub_name,
[PATCH] drm/amdgpu: cleanup gmc_v9_0_process_interrupt
First of all don't snprintf into a char buffer allocated on the stack with
a constant hubname.
Then cleanup to exit the function early in case of a ratelimit or SRIOV.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 183 +-
1 file changed, 91 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a9929d1b6b3d..0c3421d587e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -510,15 +510,16 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct
amdgpu_device *adev,
}
static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
- struct amdgpu_irq_src *source,
- struct amdgpu_iv_entry *entry)
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
{
- struct amdgpu_vmhub *hub;
bool retry_fault = !!(entry->src_data[1] & 0x80);
uint32_t status = 0, cid = 0, rw = 0;
- u64 addr;
- char hub_name[10];
+ struct amdgpu_task_info task_info;
+ struct amdgpu_vmhub *hub;
const char *mmhub_cid;
+ const char *hub_name;
+ u64 addr;
addr = (u64)entry->src_data[0] << 12;
addr |= ((u64)entry->src_data[1] & 0xf) << 44;
@@ -527,105 +528,103 @@ static int gmc_v9_0_process_interrupt(struct
amdgpu_device *adev,
entry->timestamp))
return 1; /* This also prevents sending it to KFD */
+ /* If it's the first fault for this address, process it normally */
+ if (retry_fault && !in_interrupt() &&
+ amdgpu_vm_handle_fault(adev, entry->pasid, addr))
+ return 1; /* This also prevents sending it to KFD */
+
+ if (!printk_ratelimit())
+ return 0;
+
if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
- snprintf(hub_name, sizeof(hub_name), "mmhub0");
+ hub_name = "mmhub0";
hub = >vmhub[AMDGPU_MMHUB_0];
} else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
- snprintf(hub_name, sizeof(hub_name), "mmhub1");
+ hub_name = "mmhub1";
hub = >vmhub[AMDGPU_MMHUB_1];
} else {
- snprintf(hub_name, sizeof(hub_name), "gfxhub0");
+ hub_name = "gfxhub0";
hub = >vmhub[AMDGPU_GFXHUB_0];
}
- /* If it's the first fault for this address, process it normally */
- if (retry_fault && !in_interrupt() &&
- amdgpu_vm_handle_fault(adev, entry->pasid, addr))
- return 1; /* This also prevents sending it to KFD */
+ memset(_info, 0, sizeof(struct amdgpu_task_info));
+ amdgpu_vm_get_task_info(adev, entry->pasid, _info);
- if (!amdgpu_sriov_vf(adev)) {
- /*
-* Issue a dummy read to wait for the status register to
-* be updated to avoid reading an incorrect value due to
-* the new fast GRBM interface.
-*/
- if (entry->vmid_src == AMDGPU_GFXHUB_0)
- RREG32(hub->vm_l2_pro_fault_status);
-
- status = RREG32(hub->vm_l2_pro_fault_status);
- cid = REG_GET_FIELD(status,
- VM_L2_PROTECTION_FAULT_STATUS, CID);
- rw = REG_GET_FIELD(status,
- VM_L2_PROTECTION_FAULT_STATUS, RW);
- WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
- }
+ dev_err(adev->dev,
+ "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
+ "pasid:%u, for process %s pid %d thread %s pid %d)\n",
+ hub_name, retry_fault ? "retry" : "no-retry",
+ entry->src_id, entry->ring_id, entry->vmid,
+ entry->pasid, task_info.process_name, task_info.tgid,
+ task_info.task_name, task_info.pid);
+ dev_err(adev->dev, " in page starting at address 0x%016llx from client
%d\n",
+ addr, entry->client_id);
- if (printk_ratelimit()) {
- struct amdgpu_task_info task_info;
-
- memset(_info, 0, sizeof(struct amdgpu_task_info));
- amdgpu_vm_get_task_info(adev, entry->pasid, _info);
-
- dev_err(adev->dev,
- "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
- "pasid:%u, for process %s pid %d thread %s pid %d)\n",
- hub_name, retry_fault ? "retry" : "no-retry",
- entry->src_id, entry->ring_id, entry->vmid,
- entry->pasid, task_info.process_name, task_info.tgid,
- task_info.task_name, task_info.pid);
- dev_err(adev->dev, " in page starting at address
Re: [PATCH 5/5] drm/amd/pm: do not use ixFEATURE_STATUS for checking smc running
[AMD Public Use]
Series is:
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Wednesday, October 28, 2020 4:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; sandy.8...@gmail.com
; Quan, Evan
Subject: [PATCH 5/5] drm/amd/pm: do not use ixFEATURE_STATUS for checking smc
running
This reverts commit f87812284172a9809820d10143b573d833cd3f75 "drm/amdgpu:
Fix bug where DPM is not enabled after hibernate and resume".
It was intended to fix Hawaii S4(hibernation) issue but break S3. As
ixFEATURE_STATUS is filled with garbage data on resume which can be
only cleared by reloading smc firmware(but that will involve many
changes). So, we will revert this S4 fix and seek a new way.
Change-Id: If9eed2f5a9c1168fb20be92057b583d854ad779e
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
index 09128122b493..329bf4d44bbc 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
@@ -2726,10 +2726,7 @@ static int ci_initialize_mc_reg_table(struct pp_hwmgr
*hwmgr)
static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
{
- return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
-CGS_IND_REG__SMC, FEATURE_STATUS,
-VOLTAGE_CONTROLLER_ON))
- ? true : false;
+ return ci_is_smc_ram_running(hwmgr);
}
static int ci_smu_init(struct pp_hwmgr *hwmgr)
--
2.29.0
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Re: [PATCH] amdgpu:Add flag for updating MGCG on GFX10
On Wed, Oct 28, 2020 at 06:12:36PM +0800, Su, Jinzhou (Joe) wrote: > Add RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK > > Change-Id: I4c1cc30bec81953d29c86d0fd9b5d7cff15a8cb0 > Signed-off-by: Jinzhou.Su Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 3256d6b368c8..e4c69125805d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -7520,6 +7520,7 @@ static void > gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade > /* 1 - RLC_CGTT_MGCG_OVERRIDE */ > def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); > data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | > + RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | > RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | > RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | > RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); > -- > 2.17.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] amdgpu: Add GFX MGCG and MGLS for vangogh
On Wed, Oct 28, 2020 at 05:59:45PM +0800, Su, Jinzhou (Joe) wrote: > add GFX Medium Grain Light Sleep support for vangogh > > add AMD_CG_SUPPORT_GFX_CP_LS and AMD_CG_SUPPORT_GFX_RLC_LS > > v2: > add GFX Medium Grain Clock Gating > > Signed-off-by: Jinzhou.Su > Change-Id: I38f4e36a896915f39fd7c2673e0041244006d1b8 > --- Reviewed-by: Huang Rui > drivers/gpu/drm/amd/amdgpu/nv.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c > index c65b4462bf5e..026e0a8fd526 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nv.c > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c > @@ -943,7 +943,11 @@ static int nv_common_early_init(void *handle) > > case CHIP_VANGOGH: > adev->apu_flags |= AMD_APU_IS_VANGOGH; > - adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | > + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | > + AMD_CG_SUPPORT_GFX_MGLS | > + AMD_CG_SUPPORT_GFX_CP_LS | > + AMD_CG_SUPPORT_GFX_RLC_LS | > + AMD_CG_SUPPORT_GFX_CGCG | > AMD_CG_SUPPORT_GFX_CGLS | > AMD_CG_SUPPORT_GFX_3D_CGCG | > AMD_CG_SUPPORT_GFX_3D_CGLS | > -- > 2.17.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/amdgpu: simplify pa_sc_tile_steering_override check
[AMD Public Use] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: Chengming Gui Sent: Wednesday, October 28, 2020 17:48 To: amd-gfx@lists.freedesktop.org Cc: Gui, Jack ; Zhou1, Tao ; Xiong, Yang (Felix) ; Zhang, Hawking Subject: [PATCH] drm/amd/amdgpu: simplify pa_sc_tile_steering_override check Use ">= CHIP_SIENNA_CICHLID" to replace per asic check Signed-off-by: Chengming Gui Change-Id: Iddb3bf1ceb79ecba69a07daba1c2e33d94eac24b --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 3256d6b368c8..df1b111df9dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4756,10 +4756,7 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade /* for ASICs that integrates GFX v10.3 * pa_sc_tile_steering_override should be set to 0 */ - if (adev->asic_type == CHIP_SIENNA_CICHLID || - adev->asic_type == CHIP_NAVY_FLOUNDER || - adev->asic_type == CHIP_DIMGREY_CAVEFISH || - adev->asic_type == CHIP_VANGOGH) + if (adev->asic_type >= CHIP_SIENNA_CICHLID) return 0; /* init num_sc */ -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] amdgpu:Add flag for updating MGCG on GFX10
Add RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK Change-Id: I4c1cc30bec81953d29c86d0fd9b5d7cff15a8cb0 Signed-off-by: Jinzhou.Su --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 3256d6b368c8..e4c69125805d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7520,6 +7520,7 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade /* 1 - RLC_CGTT_MGCG_OVERRIDE */ def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] amdgpu: Add GFX MGCG and MGLS for vangogh
add GFX Medium Grain Light Sleep support for vangogh add AMD_CG_SUPPORT_GFX_CP_LS and AMD_CG_SUPPORT_GFX_RLC_LS v2: add GFX Medium Grain Clock Gating Signed-off-by: Jinzhou.Su Change-Id: I38f4e36a896915f39fd7c2673e0041244006d1b8 --- drivers/gpu/drm/amd/amdgpu/nv.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index c65b4462bf5e..026e0a8fd526 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -943,7 +943,11 @@ static int nv_common_early_init(void *handle) case CHIP_VANGOGH: adev->apu_flags |= AMD_APU_IS_VANGOGH; - adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_CP_LS | + AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS | -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
[AMD Official Use Only - Internal Distribution Only]
If it turns out "PCI CONFIG reset" is used, please try the new patch series I
just sent.
https://lists.freedesktop.org/archives/amd-gfx/2020-October/055327.html
https://lists.freedesktop.org/archives/amd-gfx/2020-October/055328.html
https://lists.freedesktop.org/archives/amd-gfx/2020-October/055329.html
https://lists.freedesktop.org/archives/amd-gfx/2020-October/055330.html
https://lists.freedesktop.org/archives/amd-gfx/2020-October/055331.html
BR
Evan
-Original Message-
From: Quan, Evan
Sent: Wednesday, October 28, 2020 9:31 AM
To: Sandeep
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
Subject: RE: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
Hi Sandeep,
Did you run the tests on Hawaii?
And can you help to confirm which method is used for gpu reset? "BACO reset" or
" PCI CONFIG reset" (you can grep these keywords in dmesg)?
BR
Evan
-Original Message-
From: Sandeep
Sent: Tuesday, October 27, 2020 10:33 PM
To: Quan, Evan
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
Subject: Re: [PATCH 1/2] drm/amd/pm: enable baco reset for Hawaii
On Tue, 27 Oct 2020 at 17:04, Sandeep wrote:
>
>
>
> On Tue, 27 Oct, 2020, 17:01 Sandeep, wrote:
>>
>>
>> On Tue, 27 Oct, 2020, 08:10 Evan Quan, wrote:
>>>
>>> Which can be used for S4(hibernation) support.
>>>
>>> Change-Id: I6e4962c120a3baed14cea04ed1742ff11a273d34
>>> Signed-off-by: Evan Quan
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/cik.c | 4 +++-
>>> drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c | 7 ---
>>> 2 files changed, 7 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
>>> b/drivers/gpu/drm/amd/amdgpu/cik.c
>>> index 03ff8bd1fee8..5442df094102 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
>>> @@ -1336,11 +1336,13 @@ cik_asic_reset_method(struct amdgpu_device
>>> *adev)
>>>
>>> switch (adev->asic_type) {
>>> case CHIP_BONAIRE:
>>> - case CHIP_HAWAII:
>>> /* disable baco reset until it works */
>>> /* smu7_asic_get_baco_capability(adev, _reset); */
>>> baco_reset = false;
>>> break;
>>> + case CHIP_HAWAII:
>>> + baco_reset = cik_asic_supports_baco(adev);
>>> + break;
>>> default:
>>> baco_reset = false;
>>> break;
>>> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> index 3be40114e63d..45f608838f6e 100644
>>> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
>>> @@ -142,12 +142,12 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK,
>>> BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK,
>>> BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
>>> { CMD_DELAY_MS, 0, 0, 0, 20, 0 },
>>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
>>> 0x, 0x20 },
>>> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0,
>>> + 0x, 0x200 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK,
>>> BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
>>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
>>> + { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5,
>>> + 0x1c00 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL,
>>> BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0,
>>> 0x01 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK,
>>> BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
>>> - { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0,
>>> 5, 0x10 },
>>> + { CMD_WAITFOR, mmBACO_CNTL,
>>> + BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
>>> { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK,
>>> BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
>>> { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0,
>>> 0x, 0x00 } }; @@ -155,6 +155,7 @@ static const struct
>>> baco_cmd_entry exit_baco_tbl[] = static const struct baco_cmd_entry
>>> clean_baco_tbl[] = {
>>> { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
>>> + { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
>>> { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 } };
>>>
>>> --
>>> 2.29.0
>>
>>
>>
>> Not sure why I'm cc'd on this, I'm not a maintainer, nor does this patch
>> seem related to any patches I've contributed.
>>
>> - Sandeep
>
>
> Ok, I just saw the other email. I'll try testing the patch and see if it
> fixes the hibernation bug.
>
> - Sandeep
I tested and while suspend works correctly, hibernation is completely broken.
[PATCH 2/5] drm/amd/pm: correct the baco reset sequence for CI ASICs
Correct some registers bitmasks and add mmBIOS_SCRATCH_7
reset.
Change-Id: I416d7bee7e7ddd7b726dd921d0bb442da6ff4b93
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
index 3be40114e63d..45f608838f6e 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
@@ -142,12 +142,12 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK,
BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK,
BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
{ CMD_DELAY_MS, 0, 0, 0, 20, 0 },
- { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0x,
0x20 },
+ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0x,
0x200 },
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK,
BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
- { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
+ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK,
BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK,
BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
- { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5,
0x10 },
+ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5,
0x100 },
{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK,
BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0x,
0x00 }
};
@@ -155,6 +155,7 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
static const struct baco_cmd_entry clean_baco_tbl[] =
{
{ CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
+ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
{ CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
};
--
2.29.0
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[PATCH 4/5] drm/amd/pm: perform SMC reset on suspend/hibernation
So that the succeeding resume can be performed based on
a clean state.
Change-Id: I82f16eb2d1a6e389f171784e6e56e41892e1725e
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/hwmgr.h| 1 +
drivers/gpu/drm/amd/pm/inc/smumgr.h | 2 ++
.../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 4
.../drm/amd/pm/powerplay/smumgr/ci_smumgr.c | 24 +++
.../gpu/drm/amd/pm/powerplay/smumgr/smumgr.c | 8 +++
5 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/hwmgr.h
b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
index 0e4707a76f6d..7e29ec2902dc 100644
--- a/drivers/gpu/drm/amd/pm/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
@@ -229,6 +229,7 @@ struct pp_smumgr_func {
bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void
*profile_setting);
int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table,
uint16_t table_id, bool rw); /*rw: true for read, false for write */
+ int (*stop_smc)(struct pp_hwmgr *hwmgr);
};
struct pp_hwmgr_func {
diff --git a/drivers/gpu/drm/amd/pm/inc/smumgr.h
b/drivers/gpu/drm/amd/pm/inc/smumgr.h
index ad100b533d04..5f46f1a4f38e 100644
--- a/drivers/gpu/drm/amd/pm/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/pm/inc/smumgr.h
@@ -113,4 +113,6 @@ extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr,
void *profile_settin
extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
uint16_t table_id, bool rw);
+extern int smum_stop_smc(struct pp_hwmgr *hwmgr);
+
#endif
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 5937150e6b37..0879cd7df59f 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1667,6 +1667,10 @@ static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to reset to default!", result = tmp_result);
+ tmp_result = smum_stop_smc(hwmgr);
+ PP_ASSERT_WITH_CODE((tmp_result == 0),
+ "Failed to stop smc!", result = tmp_result);
+
tmp_result = smu7_force_switch_to_arbf0(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to force to switch arbf0!", result =
tmp_result);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
index e4d1f3d66ef4..09128122b493 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
@@ -2939,6 +2939,29 @@ static int ci_update_smc_table(struct pp_hwmgr *hwmgr,
uint32_t type)
return 0;
}
+static void ci_reset_smc(struct pp_hwmgr *hwmgr)
+{
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+ SMC_SYSCON_RESET_CNTL,
+ rst_reg, 1);
+}
+
+
+static void ci_stop_smc_clock(struct pp_hwmgr *hwmgr)
+{
+ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+ SMC_SYSCON_CLOCK_CNTL_0,
+ ck_disable, 1);
+}
+
+static int ci_stop_smc(struct pp_hwmgr *hwmgr)
+{
+ ci_reset_smc(hwmgr);
+ ci_stop_smc_clock(hwmgr);
+
+ return 0;
+}
+
const struct pp_smumgr_func ci_smu_funcs = {
.name = "ci_smu",
.smu_init = ci_smu_init,
@@ -2964,4 +2987,5 @@ const struct pp_smumgr_func ci_smu_funcs = {
.is_dpm_running = ci_is_dpm_running,
.update_dpm_settings = ci_update_dpm_settings,
.update_smc_table = ci_update_smc_table,
+ .stop_smc = ci_stop_smc,
};
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c
index b6fb48066841..b6921db3c130 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c
@@ -245,3 +245,11 @@ int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t
*table, uint16_t tabl
return -EINVAL;
}
+
+int smum_stop_smc(struct pp_hwmgr *hwmgr)
+{
+ if (hwmgr->smumgr_funcs->stop_smc)
+ return hwmgr->smumgr_funcs->stop_smc(hwmgr);
+
+ return 0;
+}
--
2.29.0
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[PATCH 1/5] drm/amdgpu: perform srbm soft reset always on SDMA resume
This can address the random SDMA hang after pci config reset
seen on Hawaii.
Change-Id: I2d6147600636cbc90d1be7f3d9a011f050708fbd
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 20f108818b2b..a3c3fe96515f 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1071,22 +1071,19 @@ static int cik_sdma_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- u32 tmp = RREG32(mmSRBM_STATUS2);
+ u32 tmp;
- if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
- /* sdma0 */
- tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
- tmp |= SDMA0_F32_CNTL__HALT_MASK;
- WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
- srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
- }
- if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
- /* sdma1 */
- tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
- tmp |= SDMA0_F32_CNTL__HALT_MASK;
- WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
- srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
- }
+ /* sdma0 */
+ tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
+ tmp |= SDMA0_F32_CNTL__HALT_MASK;
+ WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
+ srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
+
+ /* sdma1 */
+ tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
+ tmp |= SDMA0_F32_CNTL__HALT_MASK;
+ WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
+ srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
if (srbm_soft_reset) {
tmp = RREG32(mmSRBM_SOFT_RESET);
--
2.29.0
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[PATCH 5/5] drm/amd/pm: do not use ixFEATURE_STATUS for checking smc running
This reverts commit f87812284172a9809820d10143b573d833cd3f75 "drm/amdgpu:
Fix bug where DPM is not enabled after hibernate and resume".
It was intended to fix Hawaii S4(hibernation) issue but break S3. As
ixFEATURE_STATUS is filled with garbage data on resume which can be
only cleared by reloading smc firmware(but that will involve many
changes). So, we will revert this S4 fix and seek a new way.
Change-Id: If9eed2f5a9c1168fb20be92057b583d854ad779e
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
index 09128122b493..329bf4d44bbc 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
@@ -2726,10 +2726,7 @@ static int ci_initialize_mc_reg_table(struct pp_hwmgr
*hwmgr)
static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
{
- return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
-CGS_IND_REG__SMC, FEATURE_STATUS,
-VOLTAGE_CONTROLLER_ON))
- ? true : false;
+ return ci_is_smc_ram_running(hwmgr);
}
static int ci_smu_init(struct pp_hwmgr *hwmgr)
--
2.29.0
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[PATCH 3/5] drm/amd/pm: enable baco reset for Hawaii
Which can be used for S4(hibernation) support.
Change-Id: I9c90c916bdd6e128b7cf7f5c6c2c6ca5b7cfc0ef
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/cik.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 03ff8bd1fee8..5442df094102 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1336,11 +1336,13 @@ cik_asic_reset_method(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_BONAIRE:
- case CHIP_HAWAII:
/* disable baco reset until it works */
/* smu7_asic_get_baco_capability(adev, _reset); */
baco_reset = false;
break;
+ case CHIP_HAWAII:
+ baco_reset = cik_asic_supports_baco(adev);
+ break;
default:
baco_reset = false;
break;
--
2.29.0
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Re: [RFC] clang tooling cleanups
On Tue, 27 Oct 2020, t...@redhat.com wrote: > This rfc will describe > An upcoming treewide cleanup. > How clang tooling was used to programatically do the clean up. > Solicit opinions on how to generally use clang tooling. > This tooling is very impressive. It makes possible an idea that I had a while ago, to help make code review more efficient. It works like this. Suppose a patch, p, is the difference between the new tree, n, and the old tree, o. That is, p = n - o. Now let clang-tidy be the transformation 't'. This gets you a much more readable patch submission, P = t(n) - t(o). The only difficulty is that, if I submit P intead of p then 'git am' will probably reject it. This is solved by a little tooling around git, such that, should a patch P fail to apply, the relevant files are automatically reformatted with the officially endorsed transformation t, to generate a minimal cleanup patch, such that P can be automatically applied on top. If the patch submission process required* that every patch submission was generated like P and not like p, it would immediately eliminate all clean-up patches from the workload of all reviewers, and also make the reviewers' job easier because all submissions are now formatted correctly, and also avoid time lost to round-trips, such as, "you can have a reviewed-by if you respin to fix some minor style issues". * Enforcing this, e.g. with checkpatch, is slightly more complicated, but it works the same way: generate a minimal cleanup patch for the relevant files, apply the patch-to-be-submitted, and finally confirm that the modified files are unchanged under t. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh
On Tue, Oct 27, 2020 at 05:41:24PM +0800, Du, Xiaojian wrote: > This patch is to update the smu v11.5 smc header for vangogh. > > Signed-off-by: Xiaojian Du > Reviewed-by: Huang Rui > Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 114 +++ > 1 file changed, 68 insertions(+), 46 deletions(-) Series are Reviewed-by: Huang Rui > > diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h > b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h > index 55c1b151a68d..1ada0eb64663 100644 > --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h > +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h > @@ -32,55 +32,77 @@ > #define PPSMC_Result_CmdRejectedBusy 0xFC > > // Message Definitions: > -#define PPSMC_MSG_TestMessage 0x1 > -#define PPSMC_MSG_GetSmuVersion 0x2 > -#define PPSMC_MSG_GetDriverIfVersion 0x3 > -#define PPSMC_MSG_EnableGfxOff 0x4 > -#define PPSMC_MSG_DisableGfxOff 0x5 > -#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default > -#define PPSMC_MSG_PowerUpIspByTile 0x7 > -#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default > -#define PPSMC_MSG_PowerUpVcn 0x9 > -#define PPSMC_MSG_spare 0xA > -#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display > -#define PPSMC_MSG_SetMinVideoGfxclkFreq 0xC //Sets SoftMin for GFXCLK. > Arg is in MHz > -#define PPSMC_MSG_ActiveProcessNotify 0xD > -#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE > -#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF > -#define PPSMC_MSG_SetDriverDramAddrHigh 0x10 > -#define PPSMC_MSG_SetDriverDramAddrLow 0x11 > -#define PPSMC_MSG_TransferTableSmu2Dram 0x12 > -#define PPSMC_MSG_TransferTableDram2Smu 0x13 > -#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR > -#define PPSMC_MSG_GetEnabledSmuFeatures 0x15 > -#define PPSMC_MSG_spare1 0x16 > -#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17 > -#define PPSMC_MSG_SetMinVideoFclkFreq 0x18 > -#define PPSMC_MSG_SetSoftMinVcn 0x19 > -#define PPSMC_MSG_EnablePostCode 0x1A > -#define PPSMC_MSG_GetGfxclkFrequency 0x1B > -#define PPSMC_MSG_GetFclkFrequency 0x1C > -#define PPSMC_MSG_AllowGfxOff 0x1D > -#define PPSMC_MSG_DisallowGfxOff 0x1E > -#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F > -#define PPSMC_MSG_SetHardMinGfxClk 0x20 > -#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21 > -#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22 > -#define PPSMC_MSG_SetSoftMaxVcn 0x23 > -#define PPSMC_MSG_GpuChangeState 0x24 //FIXME AHOLLA - check how to do for > VGM > -#define PPSMC_MSG_SetPowerLimitPercentage 0x25 > -#define PPSMC_MSG_PowerDownJpeg 0x26 > -#define PPSMC_MSG_PowerUpJpeg 0x27 > -#define PPSMC_MSG_SetHardMinFclkByFreq 0x28 > -#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29 > -#define PPSMC_MSG_PowerUpCvip 0x2A > -#define PPSMC_MSG_PowerDownCvip 0x2B > -#define PPSMC_Message_Count 0x2C > +#define PPSMC_MSG_TestMessage 0x1 > +#define PPSMC_MSG_GetSmuVersion0x2 > +#define PPSMC_MSG_GetDriverIfVersion 0x3 > +#define PPSMC_MSG_EnableGfxOff 0x4 > +#define PPSMC_MSG_DisableGfxOff0x5 > +#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power > gated by default > +#define PPSMC_MSG_PowerUpIspByTile 0x7 > +#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power > gated by default > +#define PPSMC_MSG_PowerUpVcn 0x9 > +#define PPSMC_MSG_spare0xA > +#define PPSMC_MSG_SetHardMinVcn0xB // For wireless > display > +#define PPSMC_MSG_SetSoftMinGfxclk 0xC //Sets SoftMin > for GFXCLK. Arg is in MHz > +#define PPSMC_MSG_ActiveProcessNotify 0xD > +#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE > +#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF > +#define PPSMC_MSG_SetDriverDramAddrHigh0x10 > +#define PPSMC_MSG_SetDriverDramAddrLow 0x11 > +#define PPSMC_MSG_TransferTableSmu2Dram0x12 > +#define PPSMC_MSG_TransferTableDram2Smu0x13 > +#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset > during TDR > +#define PPSMC_MSG_GetEnabledSmuFeatures0x15 > +#define PPSMC_MSG_spare1 0x16 > +#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17 > +#define PPSMC_MSG_SetSoftMinFclk 0x18 //Used to be > PPSMC_MSG_SetMinVideoFclkFreq > +#define PPSMC_MSG_SetSoftMinVcn0x19 > +#define PPSMC_MSG_EnablePostCode 0x1A > +#define PPSMC_MSG_GetGfxclkFrequency 0x1B > +#define PPSMC_MSG_GetFclkFrequency 0x1C > +#define PPSMC_MSG_AllowGfxOff 0x1D > +#define PPSMC_MSG_DisallowGfxOff 0x1E > +#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F > +#define
RE: [PATCH 2/2] drm/amdgpu: rename nv_is_headless_sku()
[AMD Public Use]
Series is: Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Cui, Flora
Sent: Wednesday, October 28, 2020 2:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ;
Chen, Guchun ; Cui, Flora ; Teng, Rui
; Long, Gang ; Yin, Tianci (Rico)
; Cui, Flora
Subject: [PATCH 2/2] drm/amdgpu: rename nv_is_headless_sku()
for headless NAVI ASICs
Signed-off-by: Flora Cui
---
drivers/gpu/drm/amd/amdgpu/nv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 23446aceea1d..c65b4462bf5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -493,7 +493,7 @@ void nv_set_virt_ops(struct amdgpu_device *adev)
adev->virt.ops = _nv_virt_ops;
}
-static bool nv_is_blockchain_sku(struct pci_dev *pdev)
+static bool nv_is_headless_sku(struct pci_dev *pdev)
{
if ((pdev->device == 0x731E &&
(pdev->revision == 0xC6 || pdev->revision == 0xC7)) || @@ -536,7
+536,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev,
_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev) &&
-!nv_is_blockchain_sku(adev->pdev))
+!nv_is_headless_sku(adev->pdev))
amdgpu_device_ip_block_add(adev, _ip_block); #endif
amdgpu_device_ip_block_add(adev, _v10_0_ip_block); @@
-544,7 +544,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
- if (!nv_is_blockchain_sku(adev->pdev))
+ if (!nv_is_headless_sku(adev->pdev))
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
if (adev->enable_mes)
--
2.25.1
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[PATCH 1/2] drm/amdgpu: disable DCN and VCN for Navi14 0x7340/C9 SKU
Navi14 0x7340/C9 SKU has no display and video support, remove them.
Signed-off-by: Flora Cui
---
drivers/gpu/drm/amd/amdgpu/nv.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index b7fc9ebdf1c1..23446aceea1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -495,8 +495,9 @@ void nv_set_virt_ops(struct amdgpu_device *adev)
static bool nv_is_blockchain_sku(struct pci_dev *pdev)
{
- if (pdev->device == 0x731E &&
- (pdev->revision == 0xC6 || pdev->revision == 0xC7))
+ if ((pdev->device == 0x731E &&
+ (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
+ (pdev->device == 0x7340 && pdev->revision == 0xC9))
return true;
return false;
}
--
2.25.1
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[PATCH 2/2] drm/amdgpu: rename nv_is_headless_sku()
for headless NAVI ASICs
Signed-off-by: Flora Cui
---
drivers/gpu/drm/amd/amdgpu/nv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 23446aceea1d..c65b4462bf5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -493,7 +493,7 @@ void nv_set_virt_ops(struct amdgpu_device *adev)
adev->virt.ops = _nv_virt_ops;
}
-static bool nv_is_blockchain_sku(struct pci_dev *pdev)
+static bool nv_is_headless_sku(struct pci_dev *pdev)
{
if ((pdev->device == 0x731E &&
(pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
@@ -536,7 +536,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev) &&
-!nv_is_blockchain_sku(adev->pdev))
+!nv_is_headless_sku(adev->pdev))
amdgpu_device_ip_block_add(adev, _ip_block);
#endif
amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
@@ -544,7 +544,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
- if (!nv_is_blockchain_sku(adev->pdev))
+ if (!nv_is_headless_sku(adev->pdev))
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
amdgpu_device_ip_block_add(adev, _v2_0_ip_block);
if (adev->enable_mes)
--
2.25.1
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