Re: [PATCH 2/2] drm/amdgpu/powerplay/smu10: drop unused variable
For the series:
Reviewed-by: Luben Tuikov
On 2020-11-13 3:40 p.m., Alex Deucher wrote:
> Never used so drop it.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index 50308a5573e4..04226b1544e4 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1441,8 +1441,6 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr
> *hwmgr,
>
> static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
> {
> - struct amdgpu_device *adev = hwmgr->adev;
> -
> smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState,
> state, NULL);
>
> return 0;
>
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Re: [PATCH v2] drm/amdgpu: fix SI UVD firmware validate resume fail
[AMD Official Use Only - Internal Distribution Only]
Ping.
From: Jiang, Sonny
Sent: Monday, November 9, 2020 2:41 PM
To: amd-gfx@lists.freedesktop.org
Cc: Jiang, Sonny
Subject: [PATCH v2] drm/amdgpu: fix SI UVD firmware validate resume fail
The SI UVD firmware validate key is stored at the end of firmware,
which is changed during resume while playing video. So get the key
at sw_init and store it for fw validate using.
Signed-off-by: Sonny Jiang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 20 +++-
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index 5eb63288d157..edbb8194ee81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -67,6 +67,7 @@ struct amdgpu_uvd {
unsignedharvest_config;
/* store image width to adjust nb memory state */
unsigneddecode_image_width;
+ uint32_tkeyselect;
};
int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index 7cf4b11a65c5..3a5dce634cda 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -277,15 +277,8 @@ static void uvd_v3_1_mc_resume(struct amdgpu_device *adev)
*/
static int uvd_v3_1_fw_validate(struct amdgpu_device *adev)
{
- void *ptr;
- uint32_t ucode_len, i;
- uint32_t keysel;
-
- ptr = adev->uvd.inst[0].cpu_addr;
- ptr += 192 + 16;
- memcpy(_len, ptr, 4);
- ptr += ucode_len;
- memcpy(, ptr, 4);
+ int i;
+ uint32_t keysel = adev->uvd.keyselect;
WREG32(mmUVD_FW_START, keysel);
@@ -550,6 +543,8 @@ static int uvd_v3_1_sw_init(void *handle)
struct amdgpu_ring *ring;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
+ void *ptr;
+ uint32_t ucode_len;
/* UVD TRAP */
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124,
>uvd.inst->irq);
@@ -560,6 +555,13 @@ static int uvd_v3_1_sw_init(void *handle)
if (r)
return r;
+ /* Retrieval firmware validate key */
+ ptr = adev->uvd.inst[0].cpu_addr;
+ ptr += 192 + 16;
+ memcpy(_len, ptr, 4);
+ ptr += ucode_len;
+ memcpy(>uvd.keyselect, ptr, 4);
+
ring = >uvd.inst->ring;
sprintf(ring->name, "uvd");
r = amdgpu_ring_init(adev, ring, 512, >uvd.inst->irq, 0,
--
2.25.1
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Re: [PATCH] drm/amd/display: Update dmub code
On 2020-11-13 3:27 p.m., Bhawanpreet Lakha wrote:
There is a delta in the dmub code
- add boot options
- add boot status
- remove unused auto_load_is_done func pointer
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 20 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++-
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 23
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 6 +
.../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 5
.../gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 2 --
.../gpu/drm/amd/display/dmub/src/dmub_dcn30.c | 5
.../gpu/drm/amd/display/dmub/src/dmub_dcn30.h | 1 -
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 26 ++-
9 files changed, 70 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ac41ae2d261b..b82a46890846 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -265,8 +265,12 @@ struct dmub_srv_hw_funcs {
bool (*is_hw_init)(struct dmub_srv *dmub);
bool (*is_phy_init)(struct dmub_srv *dmub);
+ void (*enable_dmub_boot_options)(struct dmub_srv *dmub);
+
+ void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool
skip);
+
+ union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub);
- bool (*is_auto_load_done)(struct dmub_srv *dmub);
void (*set_gpint)(struct dmub_srv *dmub,
union dmub_gpint_data_register reg);
@@ -309,6 +313,7 @@ struct dmub_srv_hw_params {
uint64_t fb_offset;
uint32_t psp_version;
bool load_inst_const;
+ bool skip_panel_power_sequence;
};
/**
@@ -590,6 +595,19 @@ enum dmub_status dmub_srv_get_gpint_response(struct
dmub_srv *dmub,
*/
void dmub_flush_buffer_mem(const struct dmub_fb *fb);
+/**
+ * dmub_srv_get_fw_boot_status() - Returns the DMUB boot status bits.
+ *
+ * @dmub: the dmub service
+ * @status: out pointer for firmware status
+ *
+ * Return:
+ * DMUB_STATUS_OK - success
+ * DMUB_STATUS_INVALID - unspecified error, unsupported
+ */
+enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
+union dmub_fw_boot_status *status);
+
#if defined(__cplusplus)
}
#endif
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b0d1347d13f0..9fd24f93a216 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -191,7 +191,8 @@ union dmub_fw_boot_options {
uint32_t optimized_init : 1;
uint32_t skip_phy_access : 1;
uint32_t disable_clk_gate: 1;
- uint32_t reserved : 27;
+ uint32_t skip_phy_init_panel_sequence: 1;
+ uint32_t reserved : 26;
} bits;
uint32_t all;
};
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 2c4a2fe9311d..cafba1d23c6a 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -312,3 +312,26 @@ uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv
*dmub)
{
return REG_READ(DMCUB_SCRATCH7);
}
+
+union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
+{
+ union dmub_fw_boot_status status;
+
+ status.all = REG_READ(DMCUB_SCRATCH0);
+ return status;
+}
+
+void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub)
+{
+ union dmub_fw_boot_options boot_options = {0};
+
+ REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool
skip)
+{
+ union dmub_fw_boot_options boot_options;
+ boot_options.all = REG_READ(DMCUB_SCRATCH14);
+ boot_options.bits.skip_phy_init_panel_sequence = skip;
+ REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
index a316f260f6ac..d438f365cbb0 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
@@ -192,4 +192,10 @@ bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);
+void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub);
+
+void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool
skip);
+
+union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub);
+
#endif /* _DMUB_DCN20_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
[PATCH 05/17] drm/amd/display: remove unused dml variables
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 2 --
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 --
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 -
3 files changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 162464261205..dd0c3b1780d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -334,7 +334,6 @@ struct _vcs_dpi_display_pipe_dest_params_st {
unsigned int vblank_end;
unsigned int htotal;
unsigned int vtotal;
- unsigned int refresh_rate;
unsigned int vfront_porch;
unsigned int vactive;
unsigned int hactive;
@@ -345,7 +344,6 @@ struct _vcs_dpi_display_pipe_dest_params_st {
unsigned char interlaced;
double pixel_rate_mhz;
unsigned char synchronized_vblank_all_planes;
- unsigned char synchronize_timing_if_single_refresh_rate;
unsigned char otg_inst;
unsigned int odm_combine;
unsigned char use_maximum_vstartup;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 3ae72e379402..c9fbb33f05a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -659,10 +659,8 @@ static void fetch_pipe_params(struct display_mode_lib
*mode_lib)
// TODO: ODMCombineEnabled => 2 * DPPPerPlane...actually maybe not
since all pipes are specified
// Do we want the dscclk to automatically be halved? Guess not since
the value is specified
- mode_lib->vba.SynchronizeTimingsIfSingleRefreshRate =
pipes[0].pipe.dest.synchronize_timing_if_single_refresh_rate;
mode_lib->vba.SynchronizedVBlank =
pipes[0].pipe.dest.synchronized_vblank_all_planes;
for (k = 1; k < mode_lib->vba.cache_num_pipes; ++k) {
- ASSERT(mode_lib->vba.SynchronizeTimingsIfSingleRefreshRate ==
pipes[k].pipe.dest.synchronize_timing_if_single_refresh_rate);
ASSERT(mode_lib->vba.SynchronizedVBlank ==
pipes[k].pipe.dest.synchronized_vblank_all_planes);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 4d4ed1287673..3529fedc4c52 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -921,7 +921,6 @@ struct vba_vars_st {
bool UseMinimumRequiredDCFCLK;
bool ClampMinDCFCLK;
bool AllowDramClockChangeOneDisplayVactive;
- bool SynchronizeTimingsIfSingleRefreshRate;
};
--
2.25.1
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[PATCH 16/17] drm/amd/display: Increase sr enter/exit in rn ddr4 watermark table
From: Wyatt Wood
[Why]
After removing added latency for HostVM by default, DDR4 sr exit
latencies were no longer large enough for some panels and caused
underflow.
[How]
Add 1us to sr enter/exit watermark.
Signed-off-by: Wyatt Wood
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 8d8ee4b9fee1..458dab9e813b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -618,8 +618,8 @@ static struct wm_table ddr4_wm_table = {
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
- .sr_exit_time_us = 6.09,
- .sr_enter_plus_exit_time_us = 7.14,
+ .sr_exit_time_us = 7.09,
+ .sr_enter_plus_exit_time_us = 8.14,
.valid = true,
},
{
--
2.25.1
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[PATCH 14/17] drm/amd/display: correct data type
From: Raymond Yang
[Why]
We should use int for counting variable
[How]
Change type from bool to uint32_t
Signed-off-by: Raymond Yang
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index e282c2211f42..96ff556e2567 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -483,7 +483,7 @@ struct dc_debug_options {
bool scl_reset_length10;
bool hdmi20_disable;
bool skip_detection_link_training;
- bool edid_read_retry_times;
+ uint32_t edid_read_retry_times;
bool remove_disconnect_edp;
unsigned int force_odm_combine; //bit vector based on otg inst
#if defined(CONFIG_DRM_AMD_DC_DCN)
--
2.25.1
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[PATCH 01/17] drm/amd/display: Program dpp dto based on actual dpp clk
From: Yongqiang Sun
[Why]
dpp dto phase and modulo are programmed with actual dpp global clk
and pipe clk. Need to use actual dpp clk to prgoram dpp dto modulo
to get more accuracy ratio.
[How]
assign actual dpp clk to dccg for dpp modulo programming.
Signed-off-by: Yongqiang Sun
Acked-by: Bindu Ramamurthy
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 29 +--
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index ec394e3d8367..9e3d8af3895f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -103,6 +103,30 @@ void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
}
+static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
+ struct dc_state *context, bool safe_to_lower)
+{
+ int i;
+
+ clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.actual_dppclk_khz;
+ for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+ int dpp_inst, dppclk_khz, prev_dppclk_khz;
+
+ /* Loop index will match dpp->inst if resource exists,
+* and we want to avoid dependency on dpp object
+*/
+ dpp_inst = i;
+ dppclk_khz =
context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
+
+ prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
+
+ if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
+ clk_mgr->dccg->funcs->update_dpp_dto(
+ clk_mgr->dccg,
dpp_inst, dppclk_khz);
+ }
+}
+
+
void rn_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
@@ -177,7 +201,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
if (dpp_clock_lowered) {
// increase per DPP DTO before lowering global dppclk
- dcn20_update_clocks_update_dpp_dto(clk_mgr, context,
safe_to_lower);
+ rn_update_clocks_update_dpp_dto(clk_mgr, context,
safe_to_lower);
clk_mgr_base->clks.actual_dppclk_khz =
rn_vbios_smu_set_dppclk(clk_mgr,
clk_mgr_base->clks.dppclk_khz);
@@ -188,7 +212,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
rn_vbios_smu_set_dppclk(clk_mgr,
clk_mgr_base->clks.dppclk_khz);
// always update dtos unless clock is lowered and not safe to
lower
if (new_clocks->dppclk_khz >=
dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
- dcn20_update_clocks_update_dpp_dto(clk_mgr, context,
safe_to_lower);
+ rn_update_clocks_update_dpp_dto(clk_mgr, context,
safe_to_lower);
}
if (update_dispclk &&
@@ -199,7 +223,6 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
}
}
-
static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
{
/* get FbMult value */
--
2.25.1
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[PATCH 17/17] drm/amd/display: update vgh bounding box
From: Yongqiang Sun
[Why & How]
Update bounding box as per spread sheet.
Signed-off-by: Yongqiang Sun
Acked-by: Roman Li
---
.../amd/display/dc/dcn301/dcn301_resource.c | 60 +++
1 file changed, 47 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 8824dbce6f4a..0006d805b3b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -164,29 +164,63 @@ struct _vcs_dpi_ip_params_st dcn3_01_ip = {
struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
.clock_limits = {
- /*TODO: fill out defaults once wm plociy is settled*/
{
.state = 0,
- .dcfclk_mhz = 810.0,
- .fabricclk_mhz = 1200.0,
+ .dram_speed_mts = 2400.0,
+ .fabricclk_mhz = 600,
+ .socclk_mhz = 278.0,
+ .dcfclk_mhz = 400.0,
+ .dscclk_mhz = 206.0,
+ .dppclk_mhz = 1015.0,
+ .dispclk_mhz = 1015.0,
+ .phyclk_mhz = 600.0,
+ },
+ {
+ .state = 1,
+ .dram_speed_mts = 2400.0,
+ .fabricclk_mhz = 688,
+ .socclk_mhz = 278.0,
+ .dcfclk_mhz = 400.0,
+ .dscclk_mhz = 206.0,
+ .dppclk_mhz = 1015.0,
.dispclk_mhz = 1015.0,
+ .phyclk_mhz = 600.0,
+ },
+ {
+ .state = 2,
+ .dram_speed_mts = 4267.0,
+ .fabricclk_mhz = 1067,
+ .socclk_mhz = 278.0,
+ .dcfclk_mhz = 608.0,
+ .dscclk_mhz = 296.0,
.dppclk_mhz = 1015.0,
+ .dispclk_mhz = 1015.0,
.phyclk_mhz = 810.0,
- .socclk_mhz = 1000.0,
+ },
+
+ {
+ .state = 3,
+ .dram_speed_mts = 4267.0,
+ .fabricclk_mhz = 1067,
+ .socclk_mhz = 715.0,
+ .dcfclk_mhz = 676.0,
.dscclk_mhz = 338.0,
- .dram_speed_mts = 4266.0,
+ .dppclk_mhz = 1015.0,
+ .dispclk_mhz = 1015.0,
+ .phyclk_mhz = 810.0,
},
+
{
- .state = 1,
+ .state = 4,
+ .dram_speed_mts = 4267.0,
+ .fabricclk_mhz = 1067,
+ .socclk_mhz = 953.0,
.dcfclk_mhz = 810.0,
- .fabricclk_mhz = 1200.0,
- .dispclk_mhz = 1015.0,
+ .dscclk_mhz = 338.0,
.dppclk_mhz = 1015.0,
+ .dispclk_mhz = 1015.0,
.phyclk_mhz = 810.0,
- .socclk_mhz = 1000.0,
- .dscclk_mhz = 338.0,
- .dram_speed_mts = 4266.0,
- }
+ },
},
.sr_exit_time_us = 9.0,
@@ -226,7 +260,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
.xfc_bus_transport_time_us = 20, // ?
.xfc_xbuf_latency_tolerance_us = 4, // ?
.use_urgent_burst_bw = 1,// ?
- .num_states = 2,
+ .num_states = 5,
.do_urgent_latency_adjustment = false,
.urgent_latency_adjustment_fabric_clock_component_us = 0,
.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
--
2.25.1
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[PATCH 15/17] drm/amd/display: 3.2.112
From: Aric Cyr Signed-off-by: Aric Cyr Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 96ff556e2567..443b1f1ad546 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.111" +#define DC_VER "3.2.112" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 03/17] drm/amd/display: Populate hostvm parameter before DML calculation
From: Sung Lee
[Why]
If the system does not have hostvm enabled, disabling it for
DML validation will allow more modes to pass at lower voltage
levels.
[How]
When initializing HostVM save state to hubbub and read back
when populating DML pipes from context.
Signed-off-by: Sung Lee
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index 129f0b62f751..42fbb5e6d505 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -99,6 +99,8 @@ void dcn21_dchvm_init(struct hubbub *hubbub)
//Poll until HOSTVM_PREFETCH_DONE = 1
REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
+
+ hubbub->riommu_active = true;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index ed3f62535301..1c88d2edd381 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1886,7 +1886,7 @@ static int dcn21_populate_dml_pipes_from_context(
for (i = 0; i < pipe_cnt; i++) {
- pipes[i].pipe.src.hostvm = 1;
+ pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
pipes[i].pipe.src.gpuvm = 1;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index 5425e92efcb8..d9fd28b34f2a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -157,6 +157,7 @@ struct hubbub_funcs {
struct hubbub {
const struct hubbub_funcs *funcs;
struct dc_context *ctx;
+ bool riommu_active;
};
#endif
--
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[PATCH 10/17] drm/amd/display: set dpp dto as per requested clk for lower case.
From: Yongqiang Sun
[Why]
Blue screen when PNP with multiple monitor or hotplug external monitor when
playing video
due to dpp dto isn't programmed properly.
If lower dpp clock, dpp dto need to be programmed first, and actual dpp clk not
avalable yet.
[How]
set dpp dto as per request clk for lower case before dpp clk update, and after
dpp clk updated
set dpp dto again with actual dpp clk.
Signed-off-by: Yongqiang Sun
Acked-by: Bindu Ramamurthy
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 28 +++
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 9e3d8af3895f..8d8ee4b9fee1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -104,11 +104,12 @@ void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
}
static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
- struct dc_state *context, bool safe_to_lower)
+ struct dc_state *context, int ref_dpp_clk, bool safe_to_lower)
{
int i;
- clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.actual_dppclk_khz;
+ clk_mgr->dccg->ref_dppclk = ref_dpp_clk;
+
for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
int dpp_inst, dppclk_khz, prev_dppclk_khz;
@@ -200,19 +201,36 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
}
if (dpp_clock_lowered) {
- // increase per DPP DTO before lowering global dppclk
- rn_update_clocks_update_dpp_dto(clk_mgr, context,
safe_to_lower);
+ // increase per DPP DTO before lowering global dppclk with
requested dppclk
+ rn_update_clocks_update_dpp_dto(
+ clk_mgr,
+ context,
+ clk_mgr_base->clks.dppclk_khz,
+ safe_to_lower);
+
clk_mgr_base->clks.actual_dppclk_khz =
rn_vbios_smu_set_dppclk(clk_mgr,
clk_mgr_base->clks.dppclk_khz);
+ //update dpp dto with actual dpp clk.
+ rn_update_clocks_update_dpp_dto(
+ clk_mgr,
+ context,
+ clk_mgr_base->clks.actual_dppclk_khz,
+ safe_to_lower);
+
} else {
// increase global DPPCLK before lowering per DPP DTO
if (update_dppclk || update_dispclk)
clk_mgr_base->clks.actual_dppclk_khz =
rn_vbios_smu_set_dppclk(clk_mgr,
clk_mgr_base->clks.dppclk_khz);
+
// always update dtos unless clock is lowered and not safe to
lower
if (new_clocks->dppclk_khz >=
dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
- rn_update_clocks_update_dpp_dto(clk_mgr, context,
safe_to_lower);
+ rn_update_clocks_update_dpp_dto(
+ clk_mgr,
+ context,
+ clk_mgr_base->clks.actual_dppclk_khz,
+ safe_to_lower);
}
if (update_dispclk &&
--
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[PATCH 06/17] drm/amd/display: fix cursor calculation for 1xnY rotated display groups
From: Samson Tam
[Why]
Cursor is missing on displays 2 and up when doing rotated
display groups in 1xnY setup. Calculation puts cursor
out of bounds so it is not enabled.
[How]
In dcn10_set_cursor_position(), add in viewport.y into cursor
calculations for 1xnY rotated display groups.
For pipe split, check viewport.y for both pipes and use lower one
to normalize cursor position before calculations.
Add odm 2:1 support ( using same calculations as pipe split ).
Signed-off-by: Samson Tam
Acked-by: Bindu Ramamurthy
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 64 +--
1 file changed, 58 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 8eb88a50af51..1e18f0bb40b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3279,6 +3279,8 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
};
bool pipe_split_on = (pipe_ctx->top_pipe != NULL) ||
(pipe_ctx->bottom_pipe != NULL);
+ bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||
+ (pipe_ctx->prev_odm_pipe != NULL);
int x_plane = pipe_ctx->plane_state->dst_rect.x;
int y_plane = pipe_ctx->plane_state->dst_rect.y;
@@ -3362,16 +3364,56 @@ void dcn10_set_cursor_position(struct pipe_ctx
*pipe_ctx)
uint32_t temp_y = pos_cpy.y;
int viewport_height =
pipe_ctx->plane_res.scl_data.viewport.height;
-
- if (pipe_split_on) {
+ int viewport_y =
+ pipe_ctx->plane_res.scl_data.viewport.y;
+
+ /**
+* Display groups that are 1xnY, have pos_cpy.x > 2 *
viewport.height
+* For pipe split cases:
+* - apply offset of viewport.y to normalize pos_cpy.x
+* - calculate the pos_cpy.y as before
+* - shift pos_cpy.y back by same offset to get final value
+* - since we iterate through both pipes, use the lower
+* viewport.y for offset
+* For non pipe split cases, use the same calculation for
+* pos_cpy.y as the 180 degree rotation case below,
+* but use pos_cpy.x as our input because we are rotating
+* 270 degrees
+*/
+ if (pipe_split_on || odm_combine_on) {
+ int pos_cpy_x_offset;
+ int other_pipe_viewport_y;
+
+ if (pipe_split_on) {
+ if (pipe_ctx->bottom_pipe) {
+ other_pipe_viewport_y =
+
pipe_ctx->bottom_pipe->plane_res.scl_data.viewport.y;
+ } else {
+ other_pipe_viewport_y =
+
pipe_ctx->top_pipe->plane_res.scl_data.viewport.y;
+ }
+ } else {
+ if (pipe_ctx->next_odm_pipe) {
+ other_pipe_viewport_y =
+
pipe_ctx->next_odm_pipe->plane_res.scl_data.viewport.y;
+ } else {
+ other_pipe_viewport_y =
+
pipe_ctx->prev_odm_pipe->plane_res.scl_data.viewport.y;
+ }
+ }
+ pos_cpy_x_offset = (viewport_y > other_pipe_viewport_y)
?
+ other_pipe_viewport_y : viewport_y;
+ pos_cpy.x -= pos_cpy_x_offset;
if (pos_cpy.x > viewport_height) {
pos_cpy.x = pos_cpy.x - viewport_height;
pos_cpy.y = viewport_height - pos_cpy.x;
} else {
pos_cpy.y = 2 * viewport_height - pos_cpy.x;
}
- } else
- pos_cpy.y = viewport_height - pos_cpy.x;
+ pos_cpy.y += pos_cpy_x_offset;
+ } else {
+ pos_cpy.y = (2 * viewport_y) + viewport_height -
pos_cpy.x;
+ }
pos_cpy.x = temp_y;
}
// Mirror horizontally and vertically
@@ -3381,7 +3423,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
int viewport_x =
pipe_ctx->plane_res.scl_data.viewport.x;
- if (pipe_split_on) {
+ if (pipe_split_on || odm_combine_on) {
if (pos_cpy.x >= viewport_width + viewport_x) {
pos_cpy.x =
[PATCH 12/17] drm/amd/display: [FW Promotion] Release 0.0.42
From: Anthony Koo Signed-off-by: Anthony Koo Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 9e6a4b4f2f1f..a49641c0f90f 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -36,10 +36,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x821097815 +#define DMUB_FW_VERSION_GIT_HASH 0x52d68b82f #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 41 +#define DMUB_FW_VERSION_REVISION 42 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/17] drm/amd/display: Add dual edp optimization flag.
From: Yongqiang Sun
[Why & How]
Add a dual edp power optimization flag, so driver will
notify this flag to dmub FW to determine if apply the
power optimization.
Signed-off-by: Yongqiang Sun
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 +
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++-
4 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 165fd2f3c80b..f522b664d3c6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2757,6 +2757,7 @@ bool dc_link_setup_psr(struct dc_link *link,
* (Always set for DAL2, did not check ASIC)
*/
psr_context->allow_smu_optimizations =
psr_config->allow_smu_optimizations;
+ psr_context->allow_multi_disp_optimizations =
psr_config->allow_multi_disp_optimizations;
/* Complete PSR entry before aborting to prevent intermittent
* freezes on certain eDPs
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 86406b42572c..80757a0ea7c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -697,6 +697,7 @@ struct psr_config {
bool psr_frame_capture_indication_req;
unsigned int psr_sdp_transmit_line_num_deadline;
bool allow_smu_optimizations;
+ bool allow_multi_disp_optimizations;
};
union dmcu_psr_level {
@@ -799,6 +800,7 @@ struct psr_context {
*/
unsigned int frame_delay;
bool allow_smu_optimizations;
+ bool allow_multi_disp_optimizations;
};
struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 0d6fe7c29c20..17e84f34ceba 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -261,6 +261,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
// Misc
copy_settings_data->psr_level =
psr_context->psr_level.u32all;
copy_settings_data->smu_optimizations_en=
psr_context->allow_smu_optimizations;
+ copy_settings_data->multi_disp_optimizations_en =
psr_context->allow_multi_disp_optimizations;
copy_settings_data->frame_delay =
psr_context->frame_delay;
copy_settings_data->frame_cap_ind =
psr_context->psrFrameCaptureIndicationReq;
copy_settings_data->init_sdp_deadline =
psr_context->sdpTransmitLineNumDeadline;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b0d1347d13f0..9e6a4b4f2f1f 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -612,7 +612,8 @@ struct dmub_cmd_psr_copy_settings_data {
uint8_t smu_optimizations_en;
uint8_t frame_delay;
uint8_t frame_cap_ind;
- uint8_t pad[3];
+ uint8_t pad[2];
+ uint8_t multi_disp_optimizations_en;
uint16_t init_sdp_deadline;
uint16_t pad2;
};
--
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[PATCH 04/17] drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1
From: Sung Lee [WHY & HOW] Currently if VBIOSSMC_Result_UnknownCmd is returned as result of smu msg there is no way to know. Put 1 in param so if 1 is returned, this unknown case is handled. Signed-off-by: Sung Lee Acked-by: Bindu Ramamurthy --- .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c| 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c index ab2b9c61e565..11a7b583d561 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c @@ -247,5 +247,6 @@ int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mg return rn_vbios_smu_send_msg_with_param( clk_mgr, VBIOSSMC_MSG_IsPeriodicRetrainingDisabled, - 0); + 1); // if PMFW doesn't support this message, assume retraining is disabled + // so we only use most optimal watermark if we know retraining is enabled. } -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/17] drm/amd/display: Expose new CRC window property
From: Wayne Lin
[Why]
Instead of calculating CRC on whole frame, add flexibility to calculate
CRC on specific frame region.
[How]
Add few crc window coordinate properties. By default, CRC is calculated
on whole frame unless user space specifies the CRC calculation window.
Signed-off-by: Wayne Lin
Acked-by: Bindu Ramamurthy
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 19 +++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 43 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 3 +
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +
5 files changed, 201 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 77c06f999040..f81c49f28bc9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -943,6 +943,41 @@ static void mmhub_read_system_context(struct amdgpu_device
*adev, struct dc_phy_
}
#endif
+#ifdef CONFIG_DEBUG_FS
+static int create_crtc_crc_properties(struct amdgpu_display_manager *dm)
+{
+ dm->crc_win_x_start_property =
+ drm_property_create_range(adev_to_drm(dm->adev),
+ DRM_MODE_PROP_ATOMIC,
+ "AMD_CRC_WIN_X_START", 0, U16_MAX);
+ if (!dm->crc_win_x_start_property)
+ return -ENOMEM;
+
+ dm->crc_win_y_start_property =
+ drm_property_create_range(adev_to_drm(dm->adev),
+ DRM_MODE_PROP_ATOMIC,
+ "AMD_CRC_WIN_Y_START", 0, U16_MAX);
+ if (!dm->crc_win_y_start_property)
+ return -ENOMEM;
+
+ dm->crc_win_x_end_property =
+ drm_property_create_range(adev_to_drm(dm->adev),
+ DRM_MODE_PROP_ATOMIC,
+ "AMD_CRC_WIN_X_END", 0, U16_MAX);
+ if (!dm->crc_win_x_end_property)
+ return -ENOMEM;
+
+ dm->crc_win_y_end_property =
+ drm_property_create_range(adev_to_drm(dm->adev),
+ DRM_MODE_PROP_ATOMIC,
+ "AMD_CRC_WIN_Y_END", 0, U16_MAX);
+ if (!dm->crc_win_y_end_property)
+ return -ENOMEM;
+
+ return 0;
+}
+#endif
+
static int amdgpu_dm_init(struct amdgpu_device *adev)
{
struct dc_init_data init_data;
@@ -1084,6 +1119,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
dc_init_callbacks(adev->dm.dc, _params);
}
+#endif
+#ifdef CONFIG_DEBUG_FS
+ if (create_crtc_crc_properties(>dm))
+ DRM_ERROR("amdgpu: failed to create crc property.\n");
#endif
if (amdgpu_dm_initialize_drm_device(adev)) {
DRM_ERROR(
@@ -5409,12 +5448,64 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
state->crc_src = cur->crc_src;
state->cm_has_degamma = cur->cm_has_degamma;
state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
-
+#ifdef CONFIG_DEBUG_FS
+ state->crc_window = cur->crc_window;
+#endif
/* TODO Duplicate dc_stream after objects are stream object is
flattened */
return >base;
}
+#ifdef CONFIG_DEBUG_FS
+int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state,
+ struct drm_property *property,
+ uint64_t val)
+{
+ struct drm_device *dev = crtc->dev;
+ struct amdgpu_device *adev = drm_to_adev(dev);
+ struct dm_crtc_state *dm_new_state =
+ to_dm_crtc_state(crtc_state);
+
+ if (property == adev->dm.crc_win_x_start_property)
+ dm_new_state->crc_window.x_start = val;
+ else if (property == adev->dm.crc_win_y_start_property)
+ dm_new_state->crc_window.y_start = val;
+ else if (property == adev->dm.crc_win_x_end_property)
+ dm_new_state->crc_window.x_end = val;
+ else if (property == adev->dm.crc_win_y_end_property)
+ dm_new_state->crc_window.y_end = val;
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
+int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc,
+ const struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t *val)
+{
+ struct drm_device *dev = crtc->dev;
+ struct amdgpu_device *adev = drm_to_adev(dev);
+ struct dm_crtc_state *dm_state =
+ to_dm_crtc_state(state);
+
+ if (property == adev->dm.crc_win_x_start_property)
+ *val = dm_state->crc_window.x_start;
+ else
[PATCH 07/17] drm/amd/display: minor restructuring of pbn calculation functions
From: Wenjing Liu
Signed-off-by: Wenjing Liu
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 858acd3df2bc..165fd2f3c80b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2818,15 +2818,12 @@ static struct fixed31_32 get_pbn_per_slot(struct
dc_stream_state *stream)
return dc_fixpt_div_int(mbytes_per_sec, 54);
}
-static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
+static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
{
- uint64_t kbps;
struct fixed31_32 peak_kbps;
uint32_t numerator;
uint32_t denominator;
- kbps = dc_bandwidth_in_kbps_from_timing(_ctx->stream->timing);
-
/*
* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
@@ -2846,6 +2843,14 @@ static struct fixed31_32 get_pbn_from_timing(struct
pipe_ctx *pipe_ctx)
return peak_kbps;
}
+static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
+{
+ uint64_t kbps;
+
+ kbps = dc_bandwidth_in_kbps_from_timing(_ctx->stream->timing);
+ return get_pbn_from_bw_in_kbps(kbps);
+}
+
static void update_mst_stream_alloc_table(
struct dc_link *link,
struct stream_encoder *stream_enc,
@@ -2873,6 +2878,7 @@ static void update_mst_stream_alloc_table(
proposed_table->stream_allocations[i].vcp_id) {
work_table[i] = *dc_alloc;
+ work_table[i].slot_count =
proposed_table->stream_allocations[i].slot_count;
break; /* exit j loop */
}
}
--
2.25.1
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[PATCH 00/17] DC Patches November 16, 2020
This DC patchset brings improvements in multiple areas. In summary, we have: Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.42 Aric Cyr (1): drm/amd/display: 3.2.112 Dmytro Laktyushkin (1): drm/amd/display: remove unused dml variables Jacky Liao (1): drm/amd/display: Add I2C memory low power support Raymond Yang (1): drm/amd/display: correct data type Roy Chan (1): drm/amd/display: Detect dynamic backlight support in eDP sink Samson Tam (1): drm/amd/display: fix cursor calculation for 1xnY rotated display groups Sung Lee (2): drm/amd/display: Populate hostvm parameter before DML calculation drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1 Wayne Lin (1): drm/amd/display: Expose new CRC window property Wenjing Liu (1): drm/amd/display: minor restructuring of pbn calculation functions Wyatt Wood (2): drm/amd/display: Hook up PSR residency command to DSAT drm/amd/display: Increase sr enter/exit in rn ddr4 watermark table Yongqiang Sun (4): drm/amd/display: Program dpp dto based on actual dpp clk drm/amd/display: set dpp dto as per requested clk for lower case. drm/amd/display: Add dual edp optimization flag. drm/amd/display: update vgh bounding box .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 19 +++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 43 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 3 + .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 53 ++- .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 3 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 30 +++- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 + drivers/gpu/drm/amd/display/dc/dc.h | 6 +- drivers/gpu/drm/amd/display/dc/dc_link.h | 2 + drivers/gpu/drm/amd/display/dc/dc_types.h | 2 + .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 12 ++ .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 16 ++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 15 ++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 1 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 64 +++- .../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 6 +- .../amd/display/dc/dcn301/dcn301_resource.c | 60 ++-- .../amd/display/dc/dml/display_mode_structs.h | 2 - .../drm/amd/display/dc/dml/display_mode_vba.c | 2 - .../drm/amd/display/dc/dml/display_mode_vba.h | 1 - .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 1 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 7 +- 25 files changed, 448 insertions(+), 53 deletions(-) -- 2.25.1 Thanks, Bindu R ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/17] drm/amd/display: Detect dynamic backlight support in eDP sink
From: Roy Chan
[Why]
Check if the eDP sink supports the dynamic backlight control
[How]
Query the dynamic backlight capability in DPCD (eDP case only)
Signed-off-by: Roy Chan
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 6c60c1fdebdc..c9f4f2d3bed6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3740,6 +3740,7 @@ void detect_edp_sink_caps(struct dc_link *link)
uint32_t entry;
uint32_t link_rate_in_khz;
enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
+ uint8_t backlight_adj_cap;
retrieve_link_cap(link);
link->dpcd_caps.edp_supported_link_rates_count = 0;
@@ -3770,6 +3771,12 @@ void detect_edp_sink_caps(struct dc_link *link)
}
link->verified_link_cap = link->reported_link_cap;
+ core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
+ _adj_cap,
sizeof(backlight_adj_cap));
+
+ link->dpcd_caps.dynamic_backlight_capable_edp =
+ (backlight_adj_cap &
DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
+
dc_link_set_default_brightness_aux(link);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 4c57cf099b5e..52e819678ecd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1091,6 +1091,7 @@ struct dpcd_caps {
bool panel_mode_edp;
bool dpcd_display_control_capable;
bool ext_receiver_cap_field_present;
+ bool dynamic_backlight_capable_edp;
union dpcd_fec_capability fec_cap;
struct dpcd_dsc_capabilities dsc_caps;
struct dc_lttpr_caps lttpr_caps;
--
2.25.1
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[PATCH 09/17] drm/amd/display: Add I2C memory low power support
From: Jacky Liao
[Why]
The I2C memory blocks should be powered down when they are not in use.
This will reduce power consumption.
[How]
1. Write to I2C_LIGHT_SLEEP_FORCE to put memory in light sleep when
released
2. Added a debug option to allow this behaviour to be turned off
Signed-off-by: Jacky Liao
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 12
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 16
.../drm/amd/display/dc/dcn30/dcn30_resource.c| 6 +++---
4 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 52e819678ecd..e282c2211f42 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -419,6 +419,7 @@ struct dc_bw_validation_profile {
union mem_low_power_enable_options {
struct {
+ bool i2c: 1;
bool mpc: 1;
bool optc: 1;
} bits;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 3e34afe8c504..7fbd92fbc63a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -293,6 +293,14 @@ static bool setup_engine(
{
uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
uint32_t reset_length = 0;
+
+if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
+if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL) {
+REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0);
+REG_WAIT(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, 0, 0, 5);
+}
+}
+
/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to
indicate SW using it*/
REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
@@ -369,6 +377,10 @@ static void release_engine(
REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1,
DC_I2C_SW_USE_I2C_REG_REQ, 0);
+ if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
+ if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL)
+ REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
+ }
}
struct dce_i2c_hw *acquire_i2c_hw_engine(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
index fb055e6883c0..2309f2bb162c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
@@ -95,6 +95,11 @@ enum {
SR(DC_I2C_DATA),\
SR(MICROSECOND_TIME_BASE_DIV)
+#define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id)\
+ I2C_HW_ENGINE_COMMON_REG_LIST(id),\
+ SR(DIO_MEM_PWR_CTRL),\
+ SR(DIO_MEM_PWR_STATUS)
+
#define I2C_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -179,6 +184,8 @@ struct dce_i2c_shift {
uint8_t XTAL_REF_DIV;
uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
uint8_t DC_I2C_REG_RW_CNTL_STATUS;
+ uint8_t I2C_LIGHT_SLEEP_FORCE;
+ uint8_t I2C_MEM_PWR_STATE;
};
struct dce_i2c_mask {
@@ -220,12 +227,19 @@ struct dce_i2c_mask {
uint32_t XTAL_REF_DIV;
uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
uint32_t DC_I2C_REG_RW_CNTL_STATUS;
+ uint32_t I2C_LIGHT_SLEEP_FORCE;
+ uint32_t I2C_MEM_PWR_STATE;
};
#define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\
I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh)
+#define I2C_COMMON_MASK_SH_LIST_DCN30(mask_sh)\
+ I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh),\
+ I2C_SF(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh),\
+ I2C_SF(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, mask_sh)
+
struct dce_i2c_registers {
uint32_t SETUP;
uint32_t SPEED;
@@ -239,6 +253,8 @@ struct dce_i2c_registers {
uint32_t DC_I2C_TRANSACTION3;
uint32_t DC_I2C_DATA;
uint32_t MICROSECOND_TIME_BASE_DIV;
+ uint32_t DIO_MEM_PWR_CTRL;
+ uint32_t DIO_MEM_PWR_STATUS;
};
enum dce_i2c_transaction_address_space {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index b379057e669c..eb067034ad45 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -933,7 +933,7 @@ static struct dce_aux *dcn30_aux_engine_create(
return _engine->base;
}
-#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
static const struct dce_i2c_registers i2c_hw_regs[] = {
i2c_inst_regs(1),
@@ -945,11 +945,11 @@ static const struct dce_i2c_registers
[PATCH 02/17] drm/amd/display: Hook up PSR residency command to DSAT
From: Wyatt Wood
[Why]
Use GPINT command to get PSR residency from FW.
[How]
Hook up PSR residency command to DSAT.
Since PSR Count Request is deprecated, we will use this.
Signed-off-by: Wyatt Wood
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 12
drivers/gpu/drm/amd/display/dc/dc_link.h | 2 ++
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 14 ++
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 1 +
4 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ee2a51b7a2ee..858acd3df2bc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2783,6 +2783,18 @@ bool dc_link_setup_psr(struct dc_link *link,
}
+void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
+{
+ struct dc *dc = link->ctx->dc;
+ struct dmub_psr *psr = dc->res_pool->psr;
+
+ // PSR residency measurements only supported on DMCUB
+ if (psr != NULL && link->psr_settings.psr_feature_enabled)
+ psr->funcs->psr_get_residency(psr, residency);
+ else
+ *residency = 0;
+}
+
const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
{
return >link_status;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 39277aaa3e62..65b083e64131 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -228,6 +228,8 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
const struct dc_stream_state *stream, struct psr_config
*psr_config,
struct psr_context *psr_context);
+void dc_link_get_psr_residency(const struct dc_link *link, uint32_t
*residency);
+
/* Request DC to detect if there is a Panel connected.
* boot - If this call is during initial boot.
* Return false for any type of detection failure or MST detection
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index df3879c713c5..0d6fe7c29c20 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -293,12 +293,26 @@ static void dmub_psr_force_static(struct dmub_psr *dmub)
dc_dmub_srv_wait_idle(dc->dmub_srv);
}
+/**
+ * Get PSR residency from firmware.
+ */
+static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency)
+{
+ struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
+
+ // Send gpint command and wait for ack
+ dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, 0, 30);
+
+ dmub_srv_get_gpint_response(srv, residency);
+}
+
static const struct dmub_psr_funcs psr_funcs = {
.psr_copy_settings = dmub_psr_copy_settings,
.psr_enable = dmub_psr_enable,
.psr_get_state = dmub_psr_get_state,
.psr_set_level = dmub_psr_set_level,
.psr_force_static = dmub_psr_force_static,
+ .psr_get_residency = dmub_psr_get_residency,
};
/**
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index 4e113ac5a56b..fe747c20a0d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -40,6 +40,7 @@ struct dmub_psr_funcs {
void (*psr_get_state)(struct dmub_psr *dmub, enum dc_psr_state
*dc_psr_state);
void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level);
void (*psr_force_static)(struct dmub_psr *dmub);
+ void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency);
};
struct dmub_psr *dmub_psr_create(struct dc_context *ctx);
--
2.25.1
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Re: [PATCH v2 1/8] drm: Add dummy page per device or GEM object
On 6/22/20 1:50 PM, Daniel Vetter wrote:
On Mon, Jun 22, 2020 at 7:45 PM Christian König
wrote:
Am 22.06.20 um 16:32 schrieb Andrey Grodzovsky:
On 6/22/20 9:18 AM, Christian König wrote:
Am 21.06.20 um 08:03 schrieb Andrey Grodzovsky:
Will be used to reroute CPU mapped BO's page faults once
device is removed.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/drm_file.c | 8
drivers/gpu/drm/drm_prime.c | 10 ++
include/drm/drm_file.h | 2 ++
include/drm/drm_gem.h | 2 ++
4 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c
index c4c704e..67c0770 100644
--- a/drivers/gpu/drm/drm_file.c
+++ b/drivers/gpu/drm/drm_file.c
@@ -188,6 +188,12 @@ struct drm_file *drm_file_alloc(struct
drm_minor *minor)
goto out_prime_destroy;
}
+file->dummy_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+if (!file->dummy_page) {
+ret = -ENOMEM;
+goto out_prime_destroy;
+}
+
return file;
out_prime_destroy:
@@ -284,6 +290,8 @@ void drm_file_free(struct drm_file *file)
if (dev->driver->postclose)
dev->driver->postclose(dev, file);
+__free_page(file->dummy_page);
+
drm_prime_destroy_file_private(>prime);
WARN_ON(!list_empty(>event_list));
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 1de2cde..c482e9c 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -335,6 +335,13 @@ int drm_gem_prime_fd_to_handle(struct
drm_device *dev,
ret = drm_prime_add_buf_handle(_priv->prime,
dma_buf, *handle);
+
+if (!ret) {
+obj->dummy_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+if (!obj->dummy_page)
+ret = -ENOMEM;
+}
+
While the per file case still looks acceptable this is a clear NAK
since it will massively increase the memory needed for a prime
exported object.
I think that this is quite overkill in the first place and for the
hot unplug case we can just use the global dummy page as well.
Christian.
Global dummy page is good for read access, what do you do on write
access ? My first approach was indeed to map at first global dummy
page as read only and mark the vma->vm_flags as !VM_SHARED assuming
that this would trigger Copy On Write flow in core mm
(https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv5.7-rc7%2Fsource%2Fmm%2Fmemory.c%23L3977data=02%7C01%7CAndrey.Grodzovsky%40amd.com%7C3753451d037544e7495408d816d4c4ee%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637284450384586120sdata=ZpRaQgqA5K4jRfidOiedey0AleeYQ97WNUkGA29ERA0%3Dreserved=0)
on the next page fault to same address triggered by a write access but
then i realized a new COW page will be allocated for each such mapping
and this is much more wasteful then having a dedicated page per GEM
object.
Yeah, but this is only for a very very small corner cases. What we need
to prevent is increasing the memory usage during normal operation to much.
Using memory during the unplug is completely unproblematic because we
just released quite a bunch of it by releasing all those system memory
buffers.
And I'm pretty sure that COWed pages are correctly accounted towards the
used memory of a process.
So I think if that approach works as intended and the COW pages are
released again on unmapping it would be the perfect solution to the problem.
Daniel what do you think?
If COW works, sure sounds reasonable. And if we can make sure we
managed to drop all the system allocations (otherwise suddenly 2x
memory usage, worst case). But I have no idea whether we can
retroshoehorn that into an established vma, you might have fun stuff
like a mkwrite handler there (which I thought is the COW handler
thing, but really no idea).
If we need to massively change stuff then I think rw dummy page,
allocated on first fault after hotunplug (maybe just make it one per
object, that's simplest) seems like the much safer option. Much less
code that can go wrong.
-Daniel
Regarding COW, i was looking into how to properly implement it from within the
fault handler (i.e. ttm_bo_vm_fault)
and the main obstacle I hit is that of exclusive access to the vm_area_struct, i
need to be able to modify
vma->vm_flags (and vm_page_prot) to remove VM_SHARED bit so COW can be
triggered on subsequent write access
fault (here https://elixir.bootlin.com/linux/latest/source/mm/memory.c#L4128)
but core mm takes only read side mm_sem (here for example
https://elixir.bootlin.com/linux/latest/source/drivers/iommu/amd/iommu_v2.c#L488)
and so I am not supposed to modify vm_area_struct in this case. I am not sure if
it's legit to write lock tthe mm_sem from this point.
I found some discussions about this here
http://lkml.iu.edu/hypermail/linux/kernel/1909.1/02754.html but it wasn't really
clear to me
what's the solution.
In any case, seems to me that easier and more memory
[PATCH 1/2] drm/amdgpu/swsmu: add missing callback for gfx state change
The function was added, but the callback was not registered,
possibly lost in a rebase.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index c4e205c33aef..46c44f0abdfb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -1177,6 +1177,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = renoir_get_gpu_metrics,
+ .gfx_state_change_set = renoir_gfx_state_change_set,
};
void renoir_set_ppt_funcs(struct smu_context *smu)
--
2.25.4
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[PATCH 2/2] drm/amdgpu/powerplay/smu10: drop unused variable
Never used so drop it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 50308a5573e4..04226b1544e4 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1441,8 +1441,6 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr
*hwmgr,
static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
{
- struct amdgpu_device *adev = hwmgr->adev;
-
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState,
state, NULL);
return 0;
--
2.25.4
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[PATCH] drm/amd/display: Update dmub code
There is a delta in the dmub code
- add boot options
- add boot status
- remove unused auto_load_is_done func pointer
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 20 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++-
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 23
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 6 +
.../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 5
.../gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 2 --
.../gpu/drm/amd/display/dmub/src/dmub_dcn30.c | 5
.../gpu/drm/amd/display/dmub/src/dmub_dcn30.h | 1 -
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 26 ++-
9 files changed, 70 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ac41ae2d261b..b82a46890846 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -265,8 +265,12 @@ struct dmub_srv_hw_funcs {
bool (*is_hw_init)(struct dmub_srv *dmub);
bool (*is_phy_init)(struct dmub_srv *dmub);
+ void (*enable_dmub_boot_options)(struct dmub_srv *dmub);
+
+ void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool
skip);
+
+ union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub);
- bool (*is_auto_load_done)(struct dmub_srv *dmub);
void (*set_gpint)(struct dmub_srv *dmub,
union dmub_gpint_data_register reg);
@@ -309,6 +313,7 @@ struct dmub_srv_hw_params {
uint64_t fb_offset;
uint32_t psp_version;
bool load_inst_const;
+ bool skip_panel_power_sequence;
};
/**
@@ -590,6 +595,19 @@ enum dmub_status dmub_srv_get_gpint_response(struct
dmub_srv *dmub,
*/
void dmub_flush_buffer_mem(const struct dmub_fb *fb);
+/**
+ * dmub_srv_get_fw_boot_status() - Returns the DMUB boot status bits.
+ *
+ * @dmub: the dmub service
+ * @status: out pointer for firmware status
+ *
+ * Return:
+ * DMUB_STATUS_OK - success
+ * DMUB_STATUS_INVALID - unspecified error, unsupported
+ */
+enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
+union dmub_fw_boot_status *status);
+
#if defined(__cplusplus)
}
#endif
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b0d1347d13f0..9fd24f93a216 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -191,7 +191,8 @@ union dmub_fw_boot_options {
uint32_t optimized_init : 1;
uint32_t skip_phy_access : 1;
uint32_t disable_clk_gate: 1;
- uint32_t reserved : 27;
+ uint32_t skip_phy_init_panel_sequence: 1;
+ uint32_t reserved : 26;
} bits;
uint32_t all;
};
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 2c4a2fe9311d..cafba1d23c6a 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -312,3 +312,26 @@ uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv
*dmub)
{
return REG_READ(DMCUB_SCRATCH7);
}
+
+union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
+{
+ union dmub_fw_boot_status status;
+
+ status.all = REG_READ(DMCUB_SCRATCH0);
+ return status;
+}
+
+void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub)
+{
+ union dmub_fw_boot_options boot_options = {0};
+
+ REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool
skip)
+{
+ union dmub_fw_boot_options boot_options;
+ boot_options.all = REG_READ(DMCUB_SCRATCH14);
+ boot_options.bits.skip_phy_init_panel_sequence = skip;
+ REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
index a316f260f6ac..d438f365cbb0 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
@@ -192,4 +192,10 @@ bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);
+void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub);
+
+void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool
skip);
+
+union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub);
+
#endif /* _DMUB_DCN20_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
index e8f488232e34..1cf67b3e4771 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+++
Re: [PATCH] drm/amd/pm: fix smu_v11_0_init_power power_context allocation
On Thu, Nov 12, 2020 at 5:23 PM Ryan Taylor wrote:
>
> Allocate smu_power->power_context to size of smu_11_0_power_context instead of
> smu_11_0_dpm_context.
>
> Signed-off-by: Ryan Taylor
> Reviewed-by: Alex Deucher
> Reviewed-by: Evan Quan
Looks good to me.
Thanks!
Alex
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index b880c72c322c..9ec5e30edbee 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -469,11 +469,11 @@ int smu_v11_0_init_power(struct smu_context *smu)
> {
> struct smu_power_context *smu_power = >smu_power;
>
> - smu_power->power_context = kzalloc(sizeof(struct
> smu_11_0_dpm_context),
> + smu_power->power_context = kzalloc(sizeof(struct
> smu_11_0_power_context),
>GFP_KERNEL);
> if (!smu_power->power_context)
> return -ENOMEM;
> - smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
> + smu_power->power_context_size = sizeof(struct smu_11_0_power_context);
>
> return 0;
> }
> --
> 2.29.2
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH] drm/amdgpu/display: fix FP handling in DCN30
On 2020-11-12 5:06 p.m., Bhawanpreet Lakha wrote:
From: Alex Deucher
Adjust the FP handling to avoid nested calls.
The nested calls cause the warning below
WARNING: CPU: 3 PID: 384 at arch/x86/kernel/fpu/core.c:129 kernel_fpu_begin
Fixes: 26803606c5d6 ("drm/amdgpu/display: FP fixes for DCN3.x (v4)")
Signed-off-by: Alex Deucher
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Nicholas Kazlauskas
I guess dropping the noinline is fine if we're just calling it via the
function pointer.
Regards,
Nicholas Kazlauskas
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 43 +++
1 file changed, 6 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index b379057e669c..d5c81ad55045 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1470,20 +1470,8 @@ int dcn30_populate_dml_pipes_from_context(
return pipe_cnt;
}
-/*
- * This must be noinline to ensure anything that deals with FP registers
- * is contained within this call; previously our compiling with hard-float
- * would result in fp instructions being emitted outside of the boundaries
- * of the DC_FP_START/END macros, which makes sense as the compiler has no
- * idea about what is wrapped and what is not
- *
- * This is largely just a workaround to avoid breakage introduced with 5.6,
- * ideally all fp-using code should be moved into its own file, only that
- * should be compiled with hard-float, and all code exported from there
- * should be strictly wrapped with DC_FP_START/END
- */
-static noinline void dcn30_populate_dml_writeback_from_context_fp(
- struct dc *dc, struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes)
+void dcn30_populate_dml_writeback_from_context(
+ struct dc *dc, struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes)
{
int pipe_cnt, i, j;
double max_calc_writeback_dispclk;
@@ -1571,14 +1559,6 @@ static noinline void
dcn30_populate_dml_writeback_from_context_fp(
}
-void dcn30_populate_dml_writeback_from_context(
- struct dc *dc, struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes)
-{
- DC_FP_START();
- dcn30_populate_dml_writeback_from_context_fp(dc, res_ctx, pipes);
- DC_FP_END();
-}
-
unsigned int dcn30_calc_max_scaled_time(
unsigned int time_per_pixel,
enum mmhubbub_wbif_mode mode,
@@ -1977,7 +1957,7 @@ static struct pipe_ctx *dcn30_find_split_pipe(
return pipe;
}
-static bool dcn30_internal_validate_bw(
+static noinline bool dcn30_internal_validate_bw(
struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
@@ -1999,6 +1979,7 @@ static bool dcn30_internal_validate_bw(
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
+ DC_FP_START();
if (!pipe_cnt) {
out = true;
goto validate_out;
@@ -,6 +2203,7 @@ static bool dcn30_internal_validate_bw(
out = false;
validate_out:
+ DC_FP_END();
return out;
}
@@ -2404,7 +2386,7 @@ void dcn30_calculate_wm_and_dlg(
DC_FP_END();
}
-static noinline bool dcn30_validate_bandwidth_fp(struct dc *dc,
+bool dcn30_validate_bandwidth(struct dc *dc,
struct dc_state *context,
bool fast_validate)
{
@@ -2455,19 +2437,6 @@ static noinline bool dcn30_validate_bandwidth_fp(struct
dc *dc,
return out;
}
-bool dcn30_validate_bandwidth(struct dc *dc,
- struct dc_state *context,
- bool fast_validate)
-{
- bool out;
-
- DC_FP_START();
- out = dcn30_validate_bandwidth_fp(dc, context, fast_validate);
- DC_FP_END();
-
- return out;
-}
-
static noinline void get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
unsigned int
*optimal_dcfclk,
unsigned int
*optimal_fclk)
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Re: [PATCH] drm/fourcc: add table describing AMD modifiers bit layout
On Fri, Nov 13, 2020 at 12:21 PM Simon Ser wrote: > > The table describes how each bit in the u64 value is used. Explicitly > state which values a field can take if we have defines for them. Also > add a note when a field isn't always populated. > > Forcing people to update the table when changing the bit layout should > make it more obvious when there's a mistake, I hope. > > If we get to the point where the bit layout gets more complicated, it > might be worth it to split the table into multiple tables (e.g. one for > GFX8, one for GFX9+, and so on). > > Signed-off-by: Simon Ser > Cc: Bas Nieuwenhuizen > Cc: Alex Deucher > Cc: Daniel Vetter Applied. Thanks! Alex > --- > > This already contains the fix in [1]. > > [1]: https://lists.freedesktop.org/archives/amd-gfx/2020-November/056073.html > > include/uapi/drm/drm_fourcc.h | 19 +++ > 1 file changed, 19 insertions(+) > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index ca48ed0e6bc1..253386b7bc6a 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -1114,6 +1114,25 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 > modifier) > * > * For multi-plane formats the above surfaces get merged into one plane for > * each format plane, based on the required alignment only. > + * > + * Bits ParameterNotes > + * - > - > + * > + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* > + * 12:8 TILE Values are AMD_FMT_MOD_TILE__* > + *13 DCC > + *14 DCC_RETILE > + *15 DCC_PIPE_ALIGN > + *16 DCC_INDEPENDENT_64B > + *17 DCC_INDEPENDENT_128B > + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* > + *20 DCC_CONSTANT_ENCODE > + * 23:21 PIPE_XOR_BITSOnly for some chips > + * 26:24 BANK_XOR_BITSOnly for some chips > + * 29:27 PACKERS Only for some chips > + * 32:30 RB Only for some chips > + * 35:33 PIPE Only for some chips > + * 55:36 -Reserved for future use, must be zero > */ > #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) > > -- > 2.29.2 > > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2] drm/fourcc: Fix modifier field mask for AMD modifiers.
On Fri, Nov 13, 2020 at 12:55 PM Bas Nieuwenhuizen
wrote:
>
> The DCC_MAX_COMPRESSED_BLOCK has to contain one of
> AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't
> fit in 1 bit.
>
> Fix this cleanly while it is only in drm-next.
>
> Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.")
> Reviewed-by: Alex Deucher
> Signed-off-by: Bas Nieuwenhuizen
Applied. Thanks!
Alex
> ---
> include/uapi/drm/drm_fourcc.h | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index df56e71a7380..a878664ba41c 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -1129,7 +1129,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
> modifier)
> #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
> #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
> #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
> -#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1
> +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
>
> /*
> * DCC supports embedding some clear colors directly in the DCC surface.
> @@ -1140,7 +1140,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
> modifier)
> * If this bit is set that means the fastclear eliminate is not needed for
> these
> * embeddable colors.
> */
> -#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19
> +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
> #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
>
> /*
> @@ -1153,15 +1153,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
> modifier)
> * RB = only for TILE_VER_GFX9 & DCC
> * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
> */
> -#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20
> +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
> #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
> -#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23
> +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
> #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
> -#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */
> +#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */
> #define AMD_FMT_MOD_PACKERS_MASK 0x7
> -#define AMD_FMT_MOD_RB_SHIFT 29
> +#define AMD_FMT_MOD_RB_SHIFT 30
> #define AMD_FMT_MOD_RB_MASK 0x7
> -#define AMD_FMT_MOD_PIPE_SHIFT 32
> +#define AMD_FMT_MOD_PIPE_SHIFT 33
> #define AMD_FMT_MOD_PIPE_MASK 0x7
>
> #define AMD_FMT_MOD_SET(field, value) \
> --
> 2.29.2
>
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Re: [PATCH 0/3] amdgpu getfb2+modifier improvements
On Fri, Nov 13, 2020 at 12:56 PM Bas Nieuwenhuizen wrote: > > On Fri, Nov 13, 2020 at 6:53 PM Alex Deucher wrote: > > > > On Tue, Nov 10, 2020 at 9:48 PM Bas Nieuwenhuizen > > wrote: > > > > > > This has some more improvements for the addfb2 code in amdgpu. > > > > > > These patches make ffmpeg work with DCC compressed and YUV surfaces > > > with kmsgrab, both in the modifier and non-modifier case. > > > > Looks good to me. Series is: > > Reviewed-by: Alex Deucher > > Thanks! Do you need me to apply the r-b tags or can you apply as is? I will apply them. Just wanted to see if anyone else had any comments before I land them. Thanks, Alex > > > > > > > > Bas Nieuwenhuizen (3): > > > drm/amd/display: Store gem objects for planes 1-3 > > > drm/amd/display: Set new format info for converted metadata. > > > drm/amd/display: Extract 3rd plane from metadata > > > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 211 +- > > > drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 2 + > > > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 88 +--- > > > 3 files changed, 207 insertions(+), 94 deletions(-) > > > > > > -- > > > 2.29.2 > > > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 0/3] amdgpu getfb2+modifier improvements
On Fri, Nov 13, 2020 at 6:53 PM Alex Deucher wrote: > > On Tue, Nov 10, 2020 at 9:48 PM Bas Nieuwenhuizen > wrote: > > > > This has some more improvements for the addfb2 code in amdgpu. > > > > These patches make ffmpeg work with DCC compressed and YUV surfaces > > with kmsgrab, both in the modifier and non-modifier case. > > Looks good to me. Series is: > Reviewed-by: Alex Deucher Thanks! Do you need me to apply the r-b tags or can you apply as is? > > > > > Bas Nieuwenhuizen (3): > > drm/amd/display: Store gem objects for planes 1-3 > > drm/amd/display: Set new format info for converted metadata. > > drm/amd/display: Extract 3rd plane from metadata > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 211 +- > > drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 2 + > > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 88 +--- > > 3 files changed, 207 insertions(+), 94 deletions(-) > > > > -- > > 2.29.2 > > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/fourcc: Fix modifier field mask for AMD modifiers.
The DCC_MAX_COMPRESSED_BLOCK has to contain one of
AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't
fit in 1 bit.
Fix this cleanly while it is only in drm-next.
Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.")
Reviewed-by: Alex Deucher
Signed-off-by: Bas Nieuwenhuizen
---
include/uapi/drm/drm_fourcc.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index df56e71a7380..a878664ba41c 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -1129,7 +1129,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
-#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1
+#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
/*
* DCC supports embedding some clear colors directly in the DCC surface.
@@ -1140,7 +1140,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
* If this bit is set that means the fastclear eliminate is not needed for
these
* embeddable colors.
*/
-#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19
+#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
/*
@@ -1153,15 +1153,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
modifier)
* RB = only for TILE_VER_GFX9 & DCC
* PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
*/
-#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20
+#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
-#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23
+#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
-#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */
+#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */
#define AMD_FMT_MOD_PACKERS_MASK 0x7
-#define AMD_FMT_MOD_RB_SHIFT 29
+#define AMD_FMT_MOD_RB_SHIFT 30
#define AMD_FMT_MOD_RB_MASK 0x7
-#define AMD_FMT_MOD_PIPE_SHIFT 32
+#define AMD_FMT_MOD_PIPE_SHIFT 33
#define AMD_FMT_MOD_PIPE_MASK 0x7
#define AMD_FMT_MOD_SET(field, value) \
--
2.29.2
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Re: [PATCH 0/3] amdgpu getfb2+modifier improvements
On Tue, Nov 10, 2020 at 9:48 PM Bas Nieuwenhuizen wrote: > > This has some more improvements for the addfb2 code in amdgpu. > > These patches make ffmpeg work with DCC compressed and YUV surfaces > with kmsgrab, both in the modifier and non-modifier case. Looks good to me. Series is: Reviewed-by: Alex Deucher > > Bas Nieuwenhuizen (3): > drm/amd/display: Store gem objects for planes 1-3 > drm/amd/display: Set new format info for converted metadata. > drm/amd/display: Extract 3rd plane from metadata > > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 211 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 2 + > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 88 +--- > 3 files changed, 207 insertions(+), 94 deletions(-) > > -- > 2.29.2 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/1] drm/amdgpu: fix usable gart size calculation
On Fri, Nov 13, 2020 at 12:34 PM Nirmoy Das wrote: > > amdgpu_do_test_moves() is failing because of wrong > usable gart size calculation and throwing: > > [drm:amdgpu_do_test_moves [amdgpu]] *ERROR* 20bdc9f3 bind failed > > Signed-off-by: Nirmoy Das Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 13 - > 1 file changed, 4 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c > index 6042b3b81a4c..7b230bcbf2c6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c > @@ -42,16 +42,11 @@ static void amdgpu_do_test_moves(struct amdgpu_device > *adev) > size = 1024 * 1024; > > /* Number of tests = > -* (Total GTT - IB pool - writeback page - ring buffers) / test size > +* (Total GTT - gart_pin_size - (2 transfer windows for buffer > moves)) / test size > */ > - n = adev->gmc.gart_size - AMDGPU_IB_POOL_SIZE; > - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) > - if (adev->rings[i]) > - n -= adev->rings[i]->ring_size; > - if (adev->wb.wb_obj) > - n -= AMDGPU_GPU_PAGE_SIZE; > - if (adev->irq.ih.ring_obj) > - n -= adev->irq.ih.ring_size; > + n = adev->gmc.gart_size - atomic64_read(>gart_pin_size); > + n -= AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS * > + AMDGPU_GPU_PAGE_SIZE; > n /= size; > > gtt_obj = kcalloc(n, sizeof(*gtt_obj), GFP_KERNEL); > -- > 2.29.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/fourcc: Fix modifier field mask for AMD modifiers.
On Fri, Nov 13, 2020 at 11:25 AM Bas Nieuwenhuizen
wrote:
>
> The DCC_MAX_COMPRESSED_BLOCK has to contain one of
> AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't
> fit in 1 bit.
>
> Fix this cleanly while it is only in drm-next.
>
> Fixes: 8ba16d5993749c3f31fd2b49e16f0dc1e1770b9c
Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.")
Also missing your signed-off-by. With those things fixed:
Reviewed-by: Alex Deucher
> ---
>
> Found while reviewing Simon's drm_info PR:
> https://github.com/ascent12/drm_info/pull/63/commits/eaeae6ee78764a03d959cbc97c8b514f81a94c63
>
> include/uapi/drm/drm_fourcc.h | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index df56e71a7380..a878664ba41c 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -1129,7 +1129,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
> modifier)
> #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
> #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
> #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
> -#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1
> +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
>
> /*
> * DCC supports embedding some clear colors directly in the DCC surface.
> @@ -1140,7 +1140,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
> modifier)
> * If this bit is set that means the fastclear eliminate is not needed for
> these
> * embeddable colors.
> */
> -#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19
> +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
> #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
>
> /*
> @@ -1153,15 +1153,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
> modifier)
> * RB = only for TILE_VER_GFX9 & DCC
> * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
> */
> -#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20
> +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
> #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
> -#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23
> +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
> #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
> -#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */
> +#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */
> #define AMD_FMT_MOD_PACKERS_MASK 0x7
> -#define AMD_FMT_MOD_RB_SHIFT 29
> +#define AMD_FMT_MOD_RB_SHIFT 30
> #define AMD_FMT_MOD_RB_MASK 0x7
> -#define AMD_FMT_MOD_PIPE_SHIFT 32
> +#define AMD_FMT_MOD_PIPE_SHIFT 33
> #define AMD_FMT_MOD_PIPE_MASK 0x7
>
> #define AMD_FMT_MOD_SET(field, value) \
> --
> 2.29.2
>
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Re: [PATCH 40/40] drm/amd/amdgpu/gfx_v7_0: Remove unused struct definition
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:5211:45: warning: ‘gfx_v7_0_ip_block’
> defined but not used [-Wunused-const-variable=]
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Sumit Semwal
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Cc: linux-me...@vger.kernel.org
> Cc: linaro-mm-...@lists.linaro.org
> Signed-off-by: Lee Jones
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 9 -
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h | 1 -
> 2 files changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index cb07bc21dcbe5..04e1e92f5f3cf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -5208,15 +5208,6 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device
> *adev)
> cu_info->lds_size = 64;
> }
>
> -static const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
> -{
> - .type = AMD_IP_BLOCK_TYPE_GFX,
> - .major = 7,
> - .minor = 0,
> - .rev = 0,
> - .funcs = _v7_0_ip_funcs,
> -};
> -
> const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
> {
> .type = AMD_IP_BLOCK_TYPE_GFX,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
> index 6fb9c1524691f..eedce7d007f1d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
> @@ -24,7 +24,6 @@
> #ifndef __GFX_V7_0_H__
> #define __GFX_V7_0_H__
>
> -extern const struct amdgpu_ip_block_version gfx_v7_0_ip_block;
> extern const struct amdgpu_ip_block_version gfx_v7_1_ip_block;
> extern const struct amdgpu_ip_block_version gfx_v7_2_ip_block;
> extern const struct amdgpu_ip_block_version gfx_v7_3_ip_block;
> --
> 2.25.1
>
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Re: [PATCH 37/40] drm/amd/amdgpu/smu_v11_0_i2c: Provide descriptions for 'control' and 'data' params
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c:225: warning: Function parameter > or member 'control' not described in 'smu_v11_0_i2c_transmit' > drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c:325: warning: Function parameter > or member 'control' not described in 'smu_v11_0_i2c_receive' > drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c:325: warning: Function parameter > or member 'data' not described in 'smu_v11_0_i2c_receive' > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c > b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c > index 7fb240c4990ca..5c7d769aee3fb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c > +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c > @@ -212,6 +212,7 @@ static uint32_t smu_v11_0_i2c_poll_rx_status(struct > i2c_adapter *control) > /** > * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave > device. > * > + * @control: I2C adapter reference > * @address: The I2C address of the slave device. > * @data: The data to transmit over the bus. > * @numbytes: The amount of data to transmit. > @@ -313,7 +314,9 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter > *control, > /** > * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a > slave device. > * > + * @control: I2C adapter reference > * @address: The I2C address of the slave device. > + * @data: Placeholder to store received data. > * @numbytes: The amount of data to transmit. > * @i2c_flag: Flags for transmission > * > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 36/40] drm/amd/amdgpu/amdgpu_fw_attestation: Consume our own header containing prototypes
On Fri, Nov 13, 2020 at 8:51 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c:130:6: warning: no > previous prototype for ‘amdgpu_fw_attestation_debugfs_init’ > [-Wmissing-prototypes] > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Hawking Zhang > Cc: John Clements > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c > index c6947d6c7ff51..e47bca1c76359 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c > @@ -26,6 +26,7 @@ > #include > > #include "amdgpu.h" > +#include "amdgpu_fw_attestation.h" > #include "amdgpu_psp.h" > #include "amdgpu_ucode.h" > #include "soc15_common.h" > @@ -139,4 +140,4 @@ void amdgpu_fw_attestation_debugfs_init(struct > amdgpu_device *adev) > adev, > _fw_attestation_debugfs_ops); > #endif > -} > \ No newline at end of file > +} > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/1] drm/amdgpu: fix usable gart size calculation
amdgpu_do_test_moves() is failing because of wrong usable gart size calculation and throwing: [drm:amdgpu_do_test_moves [amdgpu]] *ERROR* 20bdc9f3 bind failed Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 13 - 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c index 6042b3b81a4c..7b230bcbf2c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c @@ -42,16 +42,11 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) size = 1024 * 1024; /* Number of tests = -* (Total GTT - IB pool - writeback page - ring buffers) / test size +* (Total GTT - gart_pin_size - (2 transfer windows for buffer moves)) / test size */ - n = adev->gmc.gart_size - AMDGPU_IB_POOL_SIZE; - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) - if (adev->rings[i]) - n -= adev->rings[i]->ring_size; - if (adev->wb.wb_obj) - n -= AMDGPU_GPU_PAGE_SIZE; - if (adev->irq.ih.ring_obj) - n -= adev->irq.ih.ring_size; + n = adev->gmc.gart_size - atomic64_read(>gart_pin_size); + n -= AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS * + AMDGPU_GPU_PAGE_SIZE; n /= size; gtt_obj = kcalloc(n, sizeof(*gtt_obj), GFP_KERNEL); -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 31/40] drm/amd/amdgpu/amdgpu_vm_sdma: Fix 'amdgpu_vm_sdma_prepare()'s doc-rot
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c:63: warning: Function parameter > or member 'resv' not described in 'amdgpu_vm_sdma_prepare' > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c:63: warning: Function parameter > or member 'sync_mode' not described in 'amdgpu_vm_sdma_prepare' > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c:63: warning: Excess function > parameter 'owner' description in 'amdgpu_vm_sdma_prepare' > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c:63: warning: Excess function > parameter 'exclusive' description in 'amdgpu_vm_sdma_prepare' > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Sumit Semwal > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Cc: linux-me...@vger.kernel.org > Cc: linaro-mm-...@lists.linaro.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c > index db790574dc2e8..a83a646759c58 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c > @@ -51,8 +51,8 @@ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo *table) > * amdgpu_vm_sdma_prepare - prepare SDMA command submission > * > * @p: see amdgpu_vm_update_params definition > - * @owner: owner we need to sync to > - * @exclusive: exclusive move fence we need to sync to > + * @resv: reservation object with embedded fence > + * @sync_mode: synchronization mode > * > * Returns: > * Negativ errno, 0 for success. > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 30/40] drm/amd/amdgpu/amdgpu_vm_cpu: Fix 'amdgpu_vm_cpu_prepare()'s doc-rot
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Function parameter > or member 'resv' not described in 'amdgpu_vm_cpu_prepare' > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Function parameter > or member 'sync_mode' not described in 'amdgpu_vm_cpu_prepare' > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Excess function > parameter 'owner' description in 'amdgpu_vm_cpu_prepare' > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Excess function > parameter 'exclusive' description in 'amdgpu_vm_cpu_prepare' > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Sumit Semwal > Cc: Felix Kuehling > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Cc: linux-me...@vger.kernel.org > Cc: linaro-mm-...@lists.linaro.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c > index 0786e754b..ac45d9c7a4e94 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c > @@ -38,8 +38,8 @@ static int amdgpu_vm_cpu_map_table(struct amdgpu_bo *table) > * amdgpu_vm_cpu_prepare - prepare page table update with the CPU > * > * @p: see amdgpu_vm_update_params definition > - * @owner: owner we need to sync to > - * @exclusive: exclusive move fence we need to sync to > + * @resv: reservation object with embedded fence > + * @sync_mode: synchronization mode > * > * Returns: > * Negativ errno, 0 for success. > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 27/40] drm/amd/amdgpu/amdgpu_ras: Remove unused function 'amdgpu_ras_error_cure'
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:908:5: warning: no previous
> prototype for ‘amdgpu_ras_error_cure’ [-Wmissing-prototypes]
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index b96267068a72d..f89a991999428 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -905,13 +905,6 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
> return ret;
> }
>
> -int amdgpu_ras_error_cure(struct amdgpu_device *adev,
> - struct ras_cure_if *info)
> -{
> - /* psp fw has no cure interface for now. */
> - return 0;
> -}
> -
> /* get the total error counts on all IPs */
> unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
> bool is_ce)
> --
> 2.25.1
>
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Re: [PATCH 26/40] drm/amd/amdgpu/amdgpu_gmc: Demote one and fix another function header
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:69: warning: Function parameter or
> member 'bo' not described in 'amdgpu_gmc_pd_addr'
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:121: warning: Function parameter or
> member 'bo' not described in 'amdgpu_gmc_agp_addr'
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:121: warning: Excess function
> parameter 'tbo' description in 'amdgpu_gmc_agp_addr'
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 056cb87d09ea3..fede84509dbca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -61,9 +61,8 @@ void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int
> level,
> amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
> }
>
> -/**
> +/*
> * amdgpu_gmc_pd_addr - return the address of the root directory
> - *
> */
> uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
> {
> @@ -112,7 +111,7 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev,
> void *cpu_pt_addr,
> /**
> * amdgpu_gmc_agp_addr - return the address in the AGP address space
> *
> - * @tbo: TTM BO which needs the address, must be in GTT domain
> + * @bo: TTM BO which needs the address, must be in GTT domain
> *
> * Tries to figure out how to access the BO through the AGP aperture. Returns
> * AMDGPU_BO_INVALID_OFFSET if that is not possible.
> --
> 2.25.1
>
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Re: [PATCH 25/40] drm/amd/amdgpu/amdgpu_debugfs: Demote obvious abuse of kernel-doc formatting
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:308: warning: Function parameter > or member 'f' not described in 'amdgpu_debugfs_regs_read' > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:308: warning: Function parameter > or member 'buf' not described in 'amdgpu_debugfs_regs_read' > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:308: warning: Function parameter > or member 'size' not described in 'amdgpu_debugfs_regs_read' > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:308: warning: Function parameter > or member 'pos' not described in 'amdgpu_debugfs_regs_read' > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:317: warning: Function parameter > or member 'f' not described in 'amdgpu_debugfs_regs_write' > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:317: warning: Function parameter > or member 'buf' not described in 'amdgpu_debugfs_regs_write' > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:317: warning: Function parameter > or member 'size' not described in 'amdgpu_debugfs_regs_write' > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:317: warning: Function parameter > or member 'pos' not described in 'amdgpu_debugfs_regs_write' > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Sumit Semwal > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Cc: linux-me...@vger.kernel.org > Cc: linaro-mm-...@lists.linaro.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > index 5c1f3725c7410..a6667a2ca0db3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > @@ -300,7 +300,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, > struct file *f, > return result; > } > > -/** > +/* > * amdgpu_debugfs_regs_read - Callback for reading MMIO registers > */ > static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, > @@ -309,7 +309,7 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, > char __user *buf, > return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos); > } > > -/** > +/* > * amdgpu_debugfs_regs_write - Callback for writing MMIO registers > */ > static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user > *buf, > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 24/40] drm/amd/amdgpu/amdgpu_ids: Supply missing docs for 'id' and 'vmhub'
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:271: warning: Function parameter or > member 'id' not described in 'amdgpu_vmid_grab_reserved' > drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:523: warning: Function parameter or > member 'vmhub' not described in 'amdgpu_vmid_reset' > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Sumit Semwal > Cc: Felix Kuehling > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Cc: linux-me...@vger.kernel.org > Cc: linaro-mm-...@lists.linaro.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c > index 6e9a9e5dbea07..61a1331f482c5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c > @@ -259,6 +259,7 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm, > * @sync: sync object where we add dependencies > * @fence: fence protecting ID from reuse > * @job: job who wants to use the VMID > + * @id: resulting VMID > * > * Try to assign a reserved VMID. > */ > @@ -514,6 +515,7 @@ void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, > * amdgpu_vmid_reset - reset VMID to zero > * > * @adev: amdgpu device structure > + * @vmhub: vmhub type > * @vmid: vmid number to use > * > * Reset saved GDW, GWS and OA to force switch on next flush. > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 22/40] drm/amd/amdgpu/amdgpu_sched: Consume our own header containing prototypes
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c:35:5: warning: no previous > prototype for ‘amdgpu_to_sched_priority’ [-Wmissing-prototypes] > drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c:122:5: warning: no previous > prototype for ‘amdgpu_sched_ioctl’ [-Wmissing-prototypes] > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Luben Tuikov > Cc: Andres Rodriguez > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c > index 0da0a0d986720..b7d861ed52849 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c > @@ -29,7 +29,7 @@ > #include > > #include "amdgpu.h" > - > +#include "amdgpu_sched.h" > #include "amdgpu_vm.h" > > int amdgpu_to_sched_priority(int amdgpu_priority, > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 29/40] drm/amd/amdgpu/amdgpu_csa: Remove set but unused variable 'r'
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c: In function
> ‘amdgpu_allocate_static_csa’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c:40:6: warning: variable ‘r’ set but
> not used [-Wunused-but-set-variable]
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: monk@amd.com
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
> index 08047bc4d5886..da21e60bb8272 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
> @@ -37,10 +37,9 @@ uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
> int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
> **bo,
> u32 domain, uint32_t size)
> {
> - int r;
> void *ptr;
>
> - r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
> + amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
> domain, bo,
> NULL, );
> if (!*bo)
> --
> 2.25.1
>
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[PATCH] drm/fourcc: add table describing AMD modifiers bit layout
The table describes how each bit in the u64 value is used. Explicitly state which values a field can take if we have defines for them. Also add a note when a field isn't always populated. Forcing people to update the table when changing the bit layout should make it more obvious when there's a mistake, I hope. If we get to the point where the bit layout gets more complicated, it might be worth it to split the table into multiple tables (e.g. one for GFX8, one for GFX9+, and so on). Signed-off-by: Simon Ser Cc: Bas Nieuwenhuizen Cc: Alex Deucher Cc: Daniel Vetter --- This already contains the fix in [1]. [1]: https://lists.freedesktop.org/archives/amd-gfx/2020-November/056073.html include/uapi/drm/drm_fourcc.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index ca48ed0e6bc1..253386b7bc6a 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -1114,6 +1114,25 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * * For multi-plane formats the above surfaces get merged into one plane for * each format plane, based on the required alignment only. + * + * Bits ParameterNotes + * - - + * + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* + * 12:8 TILE Values are AMD_FMT_MOD_TILE__* + *13 DCC + *14 DCC_RETILE + *15 DCC_PIPE_ALIGN + *16 DCC_INDEPENDENT_64B + *17 DCC_INDEPENDENT_128B + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* + *20 DCC_CONSTANT_ENCODE + * 23:21 PIPE_XOR_BITSOnly for some chips + * 26:24 BANK_XOR_BITSOnly for some chips + * 29:27 PACKERS Only for some chips + * 32:30 RB Only for some chips + * 35:33 PIPE Only for some chips + * 55:36 -Reserved for future use, must be zero */ #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) -- 2.29.2 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 21/40] drm/amd/amdgpu/amdgpu_virt: Make local function 'amdgpu_virt_update_vf2pf_work_item()' static
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:560:6: warning: no previous
> prototype for ‘amdgpu_virt_update_vf2pf_work_item’ [-Wmissing-prototypes]
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 8aff6ef50f918..905b85391e64a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -557,7 +557,7 @@ static int amdgpu_virt_write_vf2pf_data(struct
> amdgpu_device *adev)
> return 0;
> }
>
> -void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
> +static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
> {
> struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
> virt.vf2pf_work.work);
>
> --
> 2.25.1
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 19/40] drm/amd/amdgpu/amdgpu_vram_mgr: Add missing descriptions for 'dev' and 'dir'
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:648: warning: Function > parameter or member 'dev' not described in 'amdgpu_vram_mgr_free_sgt' > drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:648: warning: Function > parameter or member 'dir' not described in 'amdgpu_vram_mgr_free_sgt' > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c > index c99c2180785fe..d2de2a720a3d8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c > @@ -637,6 +637,8 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, > * amdgpu_vram_mgr_free_sgt - allocate and fill a sg table > * > * @adev: amdgpu device pointer > + * @dev: device pointer > + * @dir: data direction of resource to unmap > * @sgt: sg table to free > * > * Free a previously allocate sg table. > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 16/40] drm/amd/amdgpu/amdgpu_sync: Fix misnamed, missing and extra param descriptions
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c:86: warning: Function parameter or > member 'f' not described in 'amdgpu_sync_get_owner' > drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c:86: warning: Excess function > parameter 'fence' description in 'amdgpu_sync_get_owner' > drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c:182: warning: Excess function > parameter 'adev' description in 'amdgpu_sync_vm_fence' > drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c:203: warning: Function parameter or > member 'adev' not described in 'amdgpu_sync_resv' > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Sumit Semwal > Cc: Felix Kuehling > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Cc: linux-me...@vger.kernel.org > Cc: linaro-mm-...@lists.linaro.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c > index 8ea6c49529e7d..4e558632a5d2b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c > @@ -78,7 +78,7 @@ static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, > /** > * amdgpu_sync_get_owner - extract the owner of a fence > * > - * @fence: fence get the owner from > + * @f: fence get the owner from > * > * Extract who originally created the fence. > */ > @@ -172,7 +172,6 @@ int amdgpu_sync_fence(struct amdgpu_sync *sync, struct > dma_fence *f) > /** > * amdgpu_sync_vm_fence - remember to sync to this VM fence > * > - * @adev: amdgpu device > * @sync: sync object to add fence to > * @fence: the VM fence to add > * > @@ -190,6 +189,7 @@ int amdgpu_sync_vm_fence(struct amdgpu_sync *sync, struct > dma_fence *fence) > /** > * amdgpu_sync_resv - sync to a reservation object > * > + * @adev: amdgpu device > * @sync: sync object to add fences from reservation object to > * @resv: reservation object with embedded fence > * @mode: how owner affects which fences we sync to > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 11/40] drm/amd/amdgpu/amdgpu_pll: Fix kernel-doc formatting, missing and extra params
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:121: warning: Function parameter or > member 'freq' not described in 'amdgpu_pll_compute' > drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:121: warning: Function parameter or > member 'fb_div_p' not described in 'amdgpu_pll_compute' > drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:121: warning: Function parameter or > member 'frac_fb_div_p' not described in 'amdgpu_pll_compute' > drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:121: warning: Function parameter or > member 'ref_div_p' not described in 'amdgpu_pll_compute' > drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:121: warning: Function parameter or > member 'post_div_p' not described in 'amdgpu_pll_compute' > drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:317: warning: Excess function > parameter 'encoder' description in 'amdgpu_pll_get_shared_nondp_ppll' > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c > index 1f2305b7bd135..f2e20666c9c1b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c > @@ -102,11 +102,12 @@ static void amdgpu_pll_get_fb_ref_div(unsigned nom, > unsigned den, unsigned post_ > * amdgpu_pll_compute - compute PLL paramaters > * > * @pll: information about the PLL > + * @freq: requested frequency > * @dot_clock_p: resulting pixel clock > - * fb_div_p: resulting feedback divider > - * frac_fb_div_p: fractional part of the feedback divider > - * ref_div_p: resulting reference divider > - * post_div_p: resulting reference divider > + * @fb_div_p: resulting feedback divider > + * @frac_fb_div_p: fractional part of the feedback divider > + * @ref_div_p: resulting reference divider > + * @post_div_p: resulting reference divider > * > * Try to calculate the PLL parameters to generate the given frequency: > * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) > @@ -308,7 +309,6 @@ int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc) > * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP > crtc > * > * @crtc: drm crtc > - * @encoder: drm encoder > * > * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can > * be shared (i.e., same clock). > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 08/40] drm/amd/amdgpu/amdgpu_ib: Fix some incorrect/incomplete function documentation
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:66: warning: Function parameter or > member 'adev' not described in 'amdgpu_ib_get' > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:66: warning: Function parameter or > member 'vm' not described in 'amdgpu_ib_get' > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:66: warning: Function parameter or > member 'pool_type' not described in 'amdgpu_ib_get' > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:66: warning: Excess function > parameter 'ring' description in 'amdgpu_ib_get' > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:125: warning: Function parameter or > member 'ring' not described in 'amdgpu_ib_schedule' > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:125: warning: Function parameter or > member 'job' not described in 'amdgpu_ib_schedule' > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:125: warning: Excess function > parameter 'adev' description in 'amdgpu_ib_schedule' > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Sumit Semwal > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Cc: linux-me...@vger.kernel.org > Cc: linaro-mm-...@lists.linaro.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > index 2f53fa0ae9a62..c69af9b86cc60 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > @@ -52,8 +52,10 @@ > /** > * amdgpu_ib_get - request an IB (Indirect Buffer) > * > - * @ring: ring index the IB is associated with > + * @adev: amdgpu_device pointer > + * @vm: amdgpu_vm pointer > * @size: requested IB size > + * @pool_type: IB pool type (delayed, immediate, direct) > * @ib: IB object returned > * > * Request an IB (all asics). IBs are allocated using the > @@ -101,7 +103,7 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct > amdgpu_ib *ib, > /** > * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring > * > - * @adev: amdgpu_device pointer > + * @ring: ring index the IB is associated with > * @num_ibs: number of IBs to schedule > * @ibs: IB objects to schedule > * @f: fence created during this submission > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: enable 48-bit IH timestamp counter
I'd feel better with wrap-around handling. I think having a system up
for that long is not likely but not impossible. Having a known hard
limit on uptime is probably a bad thing. Imagine someone trying to
reproduce the problem ...
Regards,
Felix
Am 2020-11-16 um 6:31 a.m. schrieb Christian König:
> Feel free to keep my rb for this, but is 455 days enough in general or
> should we add wrap around handling?
>
> Christian.
>
> Am 10.11.20 um 18:57 schrieb Sierra Guiza, Alejandro (Alex):
>> [AMD Public Use]
>>
>> I just added support for vega10_ih too.
>>
>> Regards,
>> Alex
>>
>>> -Original Message-
>>> From: Sierra Guiza, Alejandro (Alex)
>>> Sent: Tuesday, November 10, 2020 11:55 AM
>>> To: amd-gfx@lists.freedesktop.org
>>> Cc: Koenig, Christian ; Kuehling, Felix
>>> ; Sierra Guiza, Alejandro (Alex)
>>>
>>> Subject: [PATCH] drm/amdgpu: enable 48-bit IH timestamp counter
>>>
>>> By default this timestamp is based on a 32 bit counter.
>>> This is used by the amdgpu_gmc_filter_faults, to avoid process the same
>>> interrupt in retry configuration.
>>> Apparently there's a problem when the timestamp coming from IH
>>> overflows
>>> and compares against timestamp coming from the the hash table.
>>> This patch only extends the time overflow from 10 minutes to aprx
>>> 455 days.
>>>
>>> Signed-off-by: Alex Sierra
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 6 ++
>>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 6 ++
>>> 2 files changed, 12 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> index 837769fcb35b..bda916f33805 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>>> @@ -94,6 +94,8 @@ static void navi10_ih_enable_interrupts(struct
>>> amdgpu_device *adev)
>>>
>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR,
>>> 1);
>>> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
>>> + RB_GPU_TS_ENABLE, 1);
>>> if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
>>> if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL,
>>> ih_rb_cntl)) {
>>> DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
>>> @@ -109,6 +111,8 @@ static void navi10_ih_enable_interrupts(struct
>>> amdgpu_device *adev)
>>> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
>>> mmIH_RB_CNTL_RING1);
>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>>> RB_ENABLE, 1);
>>> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>>> + RB_GPU_TS_ENABLE, 1);
>>> if (amdgpu_sriov_vf(adev) && adev->asic_type <
>>> CHIP_NAVI10) {
>>> if (psp_reg_program(>psp,
>>> PSP_REG_IH_RB_CNTL_RING1,
>>> ih_rb_cntl)) {
>>> @@ -125,6 +129,8 @@ static void navi10_ih_enable_interrupts(struct
>>> amdgpu_device *adev)
>>> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
>>> mmIH_RB_CNTL_RING2);
>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>>> RB_ENABLE, 1);
>>> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>>> + RB_GPU_TS_ENABLE, 1);
>>> if (amdgpu_sriov_vf(adev) && adev->asic_type <
>>> CHIP_NAVI10) {
>>> if (psp_reg_program(>psp,
>>> PSP_REG_IH_RB_CNTL_RING2,
>>> ih_rb_cntl)) {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>> index 407c6093c2ec..35d68bc5d95e 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>> @@ -50,6 +50,8 @@ static void vega10_ih_enable_interrupts(struct
>>> amdgpu_device *adev)
>>>
>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR,
>>> 1);
>>> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
>>> + RB_GPU_TS_ENABLE, 1);
>>> if (amdgpu_sriov_vf(adev)) {
>>> if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL,
>>> ih_rb_cntl)) {
>>> DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
>>> @@ -64,6 +66,8 @@ static void vega10_ih_enable_interrupts(struct
>>> amdgpu_device *adev)
>>> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
>>> mmIH_RB_CNTL_RING1);
>>> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>>> RB_ENABLE, 1);
>>> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>>> + RB_GPU_TS_ENABLE, 1);
>>> if (amdgpu_sriov_vf(adev)) {
>>> if (psp_reg_program(>psp,
>>> PSP_REG_IH_RB_CNTL_RING1,
>>> ih_rb_cntl)) {
>>> @@ -80,6 +84,8 @@ static void vega10_ih_enable_interrupts(struct
>>> amdgpu_device *adev)
>>>
Re: [PATCH 05/40] drm/amd/amdgpu/amdgpu_ring: Fix misnaming of param 'max_dw'
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c:168: warning: Function parameter or > member 'max_dw' not described in 'amdgpu_ring_init' > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c:168: warning: Excess function > parameter 'max_ndw' description in 'amdgpu_ring_init' > > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Sumit Semwal > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Cc: linux-me...@vger.kernel.org > Cc: linaro-mm-...@lists.linaro.org > Signed-off-by: Lee Jones Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > index a23b2079696a1..1a612f51ecd9e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > @@ -154,7 +154,7 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) > * > * @adev: amdgpu_device pointer > * @ring: amdgpu_ring structure holding ring information > - * @max_ndw: maximum number of dw for ring alloc > + * @max_dw: maximum number of dw for ring alloc > * @irq_src: interrupt source to use for this ring > * @irq_type: interrupt type to use for this ring > * @hw_prio: ring priority (NORMAL/HIGH) > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: enable 48-bit IH timestamp counter
[AMD Public Use]
This give us time for the rest of the enablement we're doing. However, we
should fix the fundamental problem in the near future.
Regards,
Alejandro S.
> -Original Message-
> From: amd-gfx On Behalf Of
> Christian König
> Sent: Monday, November 16, 2020 5:31 AM
> To: Sierra Guiza, Alejandro (Alex) ; amd-
> g...@lists.freedesktop.org; Koenig, Christian
> Cc: Kuehling, Felix
> Subject: Re: [PATCH] drm/amdgpu: enable 48-bit IH timestamp counter
>
> Feel free to keep my rb for this, but is 455 days enough in general or should
> we add wrap around handling?
>
> Christian.
>
> Am 10.11.20 um 18:57 schrieb Sierra Guiza, Alejandro (Alex):
> > [AMD Public Use]
> >
> > I just added support for vega10_ih too.
> >
> > Regards,
> > Alex
> >
> >> -Original Message-
> >> From: Sierra Guiza, Alejandro (Alex)
> >> Sent: Tuesday, November 10, 2020 11:55 AM
> >> To: amd-gfx@lists.freedesktop.org
> >> Cc: Koenig, Christian ; Kuehling, Felix
> >> ; Sierra Guiza, Alejandro (Alex)
> >>
> >> Subject: [PATCH] drm/amdgpu: enable 48-bit IH timestamp counter
> >>
> >> By default this timestamp is based on a 32 bit counter.
> >> This is used by the amdgpu_gmc_filter_faults, to avoid process the
> >> same interrupt in retry configuration.
> >> Apparently there's a problem when the timestamp coming from IH
> >> overflows and compares against timestamp coming from the the hash
> table.
> >> This patch only extends the time overflow from 10 minutes to aprx 455
> days.
> >>
> >> Signed-off-by: Alex Sierra
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 6 ++
> >> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 6 ++
> >> 2 files changed, 12 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> index 837769fcb35b..bda916f33805 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> @@ -94,6 +94,8 @@ static void navi10_ih_enable_interrupts(struct
> >> amdgpu_device *adev)
> >>
> >>ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
> >>ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR,
> >> 1);
> >> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> >> + RB_GPU_TS_ENABLE, 1);
> >>if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
> >>if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL,
> >> ih_rb_cntl)) {
> >>DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> @@ -109,6 +111,8
> >> @@ static void navi10_ih_enable_interrupts(struct
> >> amdgpu_device *adev)
> >>ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
> mmIH_RB_CNTL_RING1);
> >>ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> >> RB_ENABLE, 1);
> >> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> >> + RB_GPU_TS_ENABLE, 1);
> >>if (amdgpu_sriov_vf(adev) && adev->asic_type <
> >> CHIP_NAVI10) {
> >>if (psp_reg_program(>psp,
> >> PSP_REG_IH_RB_CNTL_RING1,
> >>ih_rb_cntl)) {
> >> @@ -125,6 +129,8 @@ static void navi10_ih_enable_interrupts(struct
> >> amdgpu_device *adev)
> >>ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
> mmIH_RB_CNTL_RING2);
> >>ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> >> RB_ENABLE, 1);
> >> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> >> + RB_GPU_TS_ENABLE, 1);
> >>if (amdgpu_sriov_vf(adev) && adev->asic_type <
> >> CHIP_NAVI10) {
> >>if (psp_reg_program(>psp,
> >> PSP_REG_IH_RB_CNTL_RING2,
> >>ih_rb_cntl)) {
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> index 407c6093c2ec..35d68bc5d95e 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> @@ -50,6 +50,8 @@ static void vega10_ih_enable_interrupts(struct
> >> amdgpu_device *adev)
> >>
> >>ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
> >>ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR,
> >> 1);
> >> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> >> + RB_GPU_TS_ENABLE, 1);
> >>if (amdgpu_sriov_vf(adev)) {
> >>if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL,
> >> ih_rb_cntl)) {
> >>DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> @@ -64,6 +66,8 @@
> >> static void vega10_ih_enable_interrupts(struct
> >> amdgpu_device *adev)
> >>ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
> mmIH_RB_CNTL_RING1);
> >>ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> >>
Re: [RFC PATCH 1/1] drm/amdgpu: fix usable gart size calculation
On 11/13/20 5:21 PM, Christian König wrote: Am 13.11.20 um 17:17 schrieb Nirmoy Das: amdgpu_do_test_moves() is failing because of wrong usable gart size calculation and throwing: [drm:amdgpu_do_test_moves [amdgpu]] *ERROR* 20bdc9f3 bind failed Signed-off-by: Nirmoy Das --- This still doesn't work. As per my calculation 1st 4MB of GART is not accounted for in adev->gmc.gart_size - atomic64_read(>gart_pin_size). The member gart_pin_size should probably be renamed to gtt_pin_size, but since a gtt pin is also automatically visible in the GART that should probably be ok for now. What am I missing ? The two 2MB windows in the GART which are used for buffer moves. See AMDGPU_GTT_MAX_TRANSFER_SIZE and AMDGPU_GTT_NUM_TRANSFER_WINDOWS. Thanks, I should've asked much earlier :) Nirmoy Regards, Christian. drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c index 6042b3b81a4c..d983c729997f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c @@ -42,16 +42,9 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) size = 1024 * 1024; /* Number of tests = - * (Total GTT - IB pool - writeback page - ring buffers) / test size + * (Total GTT - gart_pin_size) / test size */ - n = adev->gmc.gart_size - AMDGPU_IB_POOL_SIZE; - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) - if (adev->rings[i]) - n -= adev->rings[i]->ring_size; - if (adev->wb.wb_obj) - n -= AMDGPU_GPU_PAGE_SIZE; - if (adev->irq.ih.ring_obj) - n -= adev->irq.ih.ring_size; + n = adev->gmc.gart_size - atomic64_read(>gart_pin_size); n /= size; gtt_obj = kcalloc(n, sizeof(*gtt_obj), GFP_KERNEL); -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Cnirmoy.das%40amd.com%7Cc9c61fcfe5b744b494c208d887f0430e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637408813271687888%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=o9w4aKiHNAZvkcWPHTiZQZC5nrOYdjs7TqMpZ3d8AJ0%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 4/7] drm/radeon: Pin buffers while they are vmap'ed
Hi
Am 16.11.20 um 12:28 schrieb Christian König:
> Am 13.11.20 um 08:59 schrieb Thomas Zimmermann:
>> Hi Christian
>>
>> Am 12.11.20 um 18:16 schrieb Christian König:
>>> Am 12.11.20 um 14:21 schrieb Thomas Zimmermann:
In order to avoid eviction of vmap'ed buffers, pin them in their GEM
object's vmap implementation. Unpin them in the vunmap implementation.
This is needed to make generic fbdev support work reliably. Without,
the buffer object could be evicted while fbdev flushed its shadow
buffer.
In difference to the PRIME pin/unpin functions, the vmap code does not
modify the BOs prime_shared_count, so a vmap-pinned BO does not
count as
shared.
The actual pin location is not important as the vmap call returns
information on how to access the buffer. Callers that require a
specific location should explicitly pin the BO before vmapping it.
>>> Well is the buffer supposed to be scanned out?
>> No, not by the fbdev helper.
>
> Ok in this case that should work.
>
>>> If yes then the pin location is actually rather important since the
>>> hardware can only scan out from VRAM.
>> For relocatable BOs, fbdev uses a shadow buffer that makes all any
>> relocation transparent to userspace. It flushes the shadow fb into the
>> BO's memory if there are updates. The code is in
>> drm_fb_helper_dirty_work(). [1] During the flush operation, the vmap
>> call now pins the BO to wherever it is. The actual location does not
>> matter. It's vunmap'ed immediately afterwards.
>
> The problem is what happens when it is prepared for scanout, but can't
> be moved to VRAM because it is vmapped?
>
> When the shadow is never scanned out that isn't a problem, but we need
> to keep that in mind.
If this is a problem is practice, it has never shown up with the drivers
that use it already.
I think here's a modeset lock somewhere that could serialize these
operations. The fbdev console is not double buffered, so there's no
frequent pageflipping; hence interference should be small.
Best regards
Thomas
>
> Regards,
> Christian.
>
>>
>> For dma-buf sharing, the regular procedure of pin + vmap still apply.
>> This should always move the BO into GTT-managed memory.
>>
>> Best regards
>> Thomas
>>
>> [1]
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ftorvalds%2Flinux.git%2Ftree%2Fdrivers%2Fgpu%2Fdrm%2Fdrm_fb_helper.c%23n432data=04%7C01%7Cchristian.koenig%40amd.com%7C31b890664ca7429fc45808d887aa0842%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637408511650629569%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=RLauuAuXkcl0rXwWWJ%2FrKP%2BsCr2wAzU1ejGV1bnQ80w%3Dreserved=0
>>
>>
>>> Regards,
>>> Christian.
>>>
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/radeon/radeon_gem.c | 51
+++--
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c
b/drivers/gpu/drm/radeon/radeon_gem.c
index d2876ce3bc9e..eaf7fc9a7b07 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -226,6 +226,53 @@ static int radeon_gem_handle_lockup(struct
radeon_device *rdev, int r)
return r;
}
+static int radeon_gem_object_vmap(struct drm_gem_object *obj,
struct dma_buf_map *map)
+{
+ static const uint32_t any_domain = RADEON_GEM_DOMAIN_VRAM |
+ RADEON_GEM_DOMAIN_GTT |
+ RADEON_GEM_DOMAIN_CPU;
+
+ struct radeon_bo *bo = gem_to_radeon_bo(obj);
+ int ret;
+
+ ret = radeon_bo_reserve(bo, false);
+ if (ret)
+ return ret;
+
+ /* pin buffer at its current location */
+ ret = radeon_bo_pin(bo, any_domain, NULL);
+ if (ret)
+ goto err_radeon_bo_unreserve;
+
+ ret = drm_gem_ttm_vmap(obj, map);
+ if (ret)
+ goto err_radeon_bo_unpin;
+
+ radeon_bo_unreserve(bo);
+
+ return 0;
+
+err_radeon_bo_unpin:
+ radeon_bo_unpin(bo);
+err_radeon_bo_unreserve:
+ radeon_bo_unreserve(bo);
+ return ret;
+}
+
+static void radeon_gem_object_vunmap(struct drm_gem_object *obj,
struct dma_buf_map *map)
+{
+ struct radeon_bo *bo = gem_to_radeon_bo(obj);
+ int ret;
+
+ ret = radeon_bo_reserve(bo, false);
+ if (ret)
+ return;
+
+ drm_gem_ttm_vunmap(obj, map);
+ radeon_bo_unpin(bo);
+ radeon_bo_unreserve(bo);
+}
+
static const struct drm_gem_object_funcs radeon_gem_object_funcs = {
.free = radeon_gem_object_free,
.open = radeon_gem_object_open,
@@ -234,8 +281,8 @@ static const struct
[PATCH] drm/fourcc: Fix modifier field mask for AMD modifiers.
The DCC_MAX_COMPRESSED_BLOCK has to contain one of AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't fit in 1 bit. Fix this cleanly while it is only in drm-next. Fixes: 8ba16d5993749c3f31fd2b49e16f0dc1e1770b9c --- Found while reviewing Simon's drm_info PR: https://github.com/ascent12/drm_info/pull/63/commits/eaeae6ee78764a03d959cbc97c8b514f81a94c63 include/uapi/drm/drm_fourcc.h | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index df56e71a7380..a878664ba41c 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -1129,7 +1129,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 -#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* * DCC supports embedding some clear colors directly in the DCC surface. @@ -1140,7 +1140,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * If this bit is set that means the fastclear eliminate is not needed for these * embeddable colors. */ -#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19 +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 /* @@ -1153,15 +1153,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * RB = only for TILE_VER_GFX9 & DCC * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) */ -#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20 +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 -#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23 +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 -#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */ +#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */ #define AMD_FMT_MOD_PACKERS_MASK 0x7 -#define AMD_FMT_MOD_RB_SHIFT 29 +#define AMD_FMT_MOD_RB_SHIFT 30 #define AMD_FMT_MOD_RB_MASK 0x7 -#define AMD_FMT_MOD_PIPE_SHIFT 32 +#define AMD_FMT_MOD_PIPE_SHIFT 33 #define AMD_FMT_MOD_PIPE_MASK 0x7 #define AMD_FMT_MOD_SET(field, value) \ -- 2.29.2 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [RFC PATCH 1/1] drm/amdgpu: fix usable gart size calculation
Am 13.11.20 um 17:17 schrieb Nirmoy Das: amdgpu_do_test_moves() is failing because of wrong usable gart size calculation and throwing: [drm:amdgpu_do_test_moves [amdgpu]] *ERROR* 20bdc9f3 bind failed Signed-off-by: Nirmoy Das --- This still doesn't work. As per my calculation 1st 4MB of GART is not accounted for in adev->gmc.gart_size - atomic64_read(>gart_pin_size). The member gart_pin_size should probably be renamed to gtt_pin_size, but since a gtt pin is also automatically visible in the GART that should probably be ok for now. What am I missing ? The two 2MB windows in the GART which are used for buffer moves. See AMDGPU_GTT_MAX_TRANSFER_SIZE and AMDGPU_GTT_NUM_TRANSFER_WINDOWS. Regards, Christian. drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c index 6042b3b81a4c..d983c729997f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c @@ -42,16 +42,9 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) size = 1024 * 1024; /* Number of tests = -* (Total GTT - IB pool - writeback page - ring buffers) / test size +* (Total GTT - gart_pin_size) / test size */ - n = adev->gmc.gart_size - AMDGPU_IB_POOL_SIZE; - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) - if (adev->rings[i]) - n -= adev->rings[i]->ring_size; - if (adev->wb.wb_obj) - n -= AMDGPU_GPU_PAGE_SIZE; - if (adev->irq.ih.ring_obj) - n -= adev->irq.ih.ring_size; + n = adev->gmc.gart_size - atomic64_read(>gart_pin_size); n /= size; gtt_obj = kcalloc(n, sizeof(*gtt_obj), GFP_KERNEL); -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[RFC PATCH 1/1] drm/amdgpu: fix usable gart size calculation
amdgpu_do_test_moves() is failing because of wrong usable gart size calculation and throwing: [drm:amdgpu_do_test_moves [amdgpu]] *ERROR* 20bdc9f3 bind failed Signed-off-by: Nirmoy Das --- This still doesn't work. As per my calculation 1st 4MB of GART is not accounted for in adev->gmc.gart_size - atomic64_read(>gart_pin_size). What am I missing ? drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c index 6042b3b81a4c..d983c729997f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c @@ -42,16 +42,9 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) size = 1024 * 1024; /* Number of tests = -* (Total GTT - IB pool - writeback page - ring buffers) / test size +* (Total GTT - gart_pin_size) / test size */ - n = adev->gmc.gart_size - AMDGPU_IB_POOL_SIZE; - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) - if (adev->rings[i]) - n -= adev->rings[i]->ring_size; - if (adev->wb.wb_obj) - n -= AMDGPU_GPU_PAGE_SIZE; - if (adev->irq.ih.ring_obj) - n -= adev->irq.ih.ring_size; + n = adev->gmc.gart_size - atomic64_read(>gart_pin_size); n /= size; gtt_obj = kcalloc(n, sizeof(*gtt_obj), GFP_KERNEL); -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Add missing pflip irq for dcn2.0
On 2020-11-13 2:23 a.m., Alex Deucher wrote:
If we have more than 4 displays we will run
into dummy irq calls or flip timout issues.
Signed-off-by: Alex Deucher
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
index 2a1fea501f8c..3f1e7a196a23 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
@@ -299,8 +299,8 @@ irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
pflip_int_entry(1),
pflip_int_entry(2),
pflip_int_entry(3),
- [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
- [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
+ pflip_int_entry(4),
+ pflip_int_entry(5),
[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
gpio_pad_int_entry(0),
gpio_pad_int_entry(1),
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Re: [PATCH 02/40] drm/amd/display/dc/core/dc_link_dp: Move DP_VGA_LVDS_CONVERTER_ID_{2, 3} to where they're used
On Fri, 13 Nov 2020, Alex Deucher wrote:
> On Fri, Nov 13, 2020 at 8:49 AM Lee Jones wrote:
> >
> > This patch fixes >200 warnings.
> >
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:123:22:
> > warning: ‘DP_VGA_LVDS_CONVERTER_ID_3’ defined but not used
> > [-Wunused-const-variable=]
> > 123 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> > | ^~
> > drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:121:22:
> > warning: ‘DP_VGA_LVDS_CONVERTER_ID_2’ defined but not used
> > [-Wunused-const-variable=]
> > 121 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
> >
> > NB: Repeated ~100 times - snipped for brevity
> >
> > Cc: Harry Wentland
> > Cc: Leo Li
> > Cc: Alex Deucher
> > Cc: "Christian König"
> > Cc: David Airlie
> > Cc: Daniel Vetter
> > Cc: amd-gfx@lists.freedesktop.org
> > Cc: dri-de...@lists.freedesktop.org
> > Signed-off-by: Lee Jones
> > ---
> > drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c| 5 +
> > drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4
> > 2 files changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > index 6c60c1fdebdc1..f2023d2b53234 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > @@ -15,6 +15,11 @@
> > #include "dc_dmub_srv.h"
> > #include "dce/dmub_hw_lock_mgr.h"
> >
> > +/*Travis*/
> > +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
> > +/*Nutmeg*/
> > +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> > +
> > #define DC_LOGGER \
> > link->ctx->logger
> > #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
> > diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> > b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> > index c9be899cd25cd..b453ce5a9bfdb 100644
> > --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> > +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> > @@ -117,10 +117,6 @@ struct av_sync_data {
> > uint8_t aud_del_ins3;/* DPCD 0002Dh */
> > };
> >
> > -/*Travis*/
> > -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
> > -/*Nutmeg*/
> > -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> > /*DP to Dual link DVI converter*/
> > static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
> > static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
>
> Can we keep all of these strings together?
I don't think so. They are consumed by different files.
Oh, one way to do it would be to mark them as __maybe_unused, but
I only tend to do that a last resort.
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [PATCH] drm/amd/display: add cursor pitch check
On Thu, Nov 12, 2020 at 9:07 PM Simon Ser wrote:
>
> CC Daniel Vetter and Bas, see below…
>
> On Thursday, November 12, 2020 8:56 PM, Kazlauskas, Nicholas
> wrote:
>
> > Reviewed-by: Nicholas kazlauskasnicholas.kazlaus...@amd.com
>
> Thanks for the review!
>
> > > Couple questions:
> > >
> > > - This implements a single check for all GPU generations. Is my
> > > assumption correct here? It seems like this check is OK for at least
> > > DCN 1.0 and DCN 2.0.
> > >
> > > - We should really implement better checks. What features are supported
> > > on the cursor plane? Is scaling supported? Is cropping supported? Is
> > > rotation always supported?
> > >
> >
> > On DCE and DCN there is no dedicated hardware cursor plane. You get a
> > cursor per pipe but it's going to inherit the scaling and positioning
> > from the underlying pipe.
> >
> > There's software logic to ensure we position the cursor in the correct
> > location in CRTC space independent on the underlying DRM plane's scaling
> > and positioning but there's no way for us to correct the scaling. Cursor
> > will always be 64, 128, or 256 in the pipe's destination space.
>
> Interesting.
>
> Daniel Vetter: what would be the best way to expose this to user-space?
> Maybe we should just make atomic commits with a cursor plane fail when
> scaling is used on the primary plane?
I think there's been discussion for a pipe scaling property on the
crtc. As long as we don't have that, and you're using the pipe scaling
to scale the primary plane, then I guess you have to reject the cursor
if it's enabled. Except maybe if the scaling is the same one, dunno
whether that ever happens.
-Daniel
> Disabling the cursor plane sounds better than displaying the wrong
> image.
>
> > Cursor can be independently rotated in hardware but this isn't something
> > we expose support for to userspace.
>
> Hmm, I see that cursor planes have the "rotation" property exposed:
>
> "rotation": bitmask {rotate-0, rotate-90, rotate-180, rotate-270}
>
> In fact all planes have it. It's done in amdgpu_dm_plane_init (behind a
> `dm->adev->asic_type >= CHIP_BONAIRE` condition).
>
> Is this an oversight?
>
> > The pitch check of 64/128/256 is OK but we don't support 256 on DCE.
>
> Yeah, I've noticed that. The size check right above should catch it
> in most cases I think, because max_cursor_size is 128 on DCE. Side
> note, max_cursor_size is 64 on DCE 6.0.
--
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 04/40] drm/amd/amdgpu/amdgpu_drv: Move 'amdgpu_info_ioctl()'s prototype to shared header
On Fri, Nov 13, 2020 at 8:49 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:486:5: warning: no previous
> prototype for ‘amdgpu_info_ioctl’ [-Wmissing-prototypes]
> 486 | int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct
> drm_file *filp)
> | ^
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
Luben already sent a patch to fix this one. I'll be picking up that one.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h | 31 +
> 3 files changed, 33 insertions(+), 3 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 1dfea15bbec36..afd357df0f886 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -43,7 +43,7 @@
> #include "amdgpu_sched.h"
>
> #include "amdgpu_amdkfd.h"
> -
> +#include "amdgpu_kms.h"
> #include "amdgpu_ras.h"
>
> /*
> @@ -1521,8 +1521,6 @@ int amdgpu_file_to_fpriv(struct file *filp, struct
> amdgpu_fpriv **fpriv)
> return 0;
> }
>
> -int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
> *filp);
> -
> const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl,
> DRM_AUTH|DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl,
> DRM_AUTH|DRM_RENDER_ALLOW),
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 98721ae931841..54c4ee6d230d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -41,6 +41,7 @@
> #include "amdgpu_amdkfd.h"
> #include "amdgpu_gem.h"
> #include "amdgpu_display.h"
> +#include "amdgpu_kms.h"
> #include "amdgpu_ras.h"
>
> void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h
> new file mode 100644
> index 0..f3111aef76cae
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h
> @@ -0,0 +1,31 @@
> +/* amdgpu_kms.h -- Private header for radeon driver -*- linux-c -*-
> + *
> + * Copyright 2008 Advanced Micro Devices, Inc.
> + * Copyright 2008 Red Hat Inc.
> + * Copyright 2009 Jerome Glisse.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef __AMDGPU_KMS_H__
> +#define __AMDGPU_KMS_H__
> +
> +int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
> *filp);
> +
> +#endif /* __AMDGPU_KMS_H__ */
> --
> 2.25.1
>
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Re: [PATCH 3/5] drm/amdgpu/vcn: add test for dec vcn software ring
Am 11.11.20 um 23:27 schrieb James Zhu:
Add vcn software ring decode ring test and decode ib test.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 138 ++--
1 file changed, 132 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 7e19a66..e3d54fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -456,6 +456,37 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
return r;
}
+int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t rptr;
+ unsigned int i;
+ int r;
+
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+ r = amdgpu_ring_alloc(ring, 16);
+ if (r)
+ return r;
+
+ rptr = amdgpu_ring_get_rptr(ring);
+
+ amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
+ amdgpu_ring_commit(ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (amdgpu_ring_get_rptr(ring) != rptr)
+ break;
+ udelay(1);
+ }
+
+ if (i >= adev->usec_timeout)
+ r = -ETIMEDOUT;
+
+ return r;
+}
+
static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
struct amdgpu_bo *bo,
struct dma_fence **fence)
@@ -510,7 +541,10 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring
*ring,
}
static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct dma_fence **fence)
+ struct dma_fence **fence,
+ int (*send_msg)(struct amdgpu_ring *,
+ struct amdgpu_bo *,
+ struct dma_fence **))
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_bo *bo = NULL;
@@ -540,13 +574,17 @@ static int amdgpu_vcn_dec_get_create_msg(struct
amdgpu_ring *ring, uint32_t hand
for (i = 14; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
- return amdgpu_vcn_dec_send_msg(ring, bo, fence);
+ return send_msg(ring, bo, fence);
}
static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct dma_fence **fence)
+ struct dma_fence **fence,
+ int (*send_msg)(struct amdgpu_ring *,
+ struct amdgpu_bo *,
+ struct dma_fence **))
{
struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_send_msg *dec;
struct amdgpu_bo *bo = NULL;
uint32_t *msg;
int r, i;
@@ -566,19 +604,107 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct
amdgpu_ring *ring, uint32_t han
for (i = 6; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
- return amdgpu_vcn_dec_send_msg(ring, bo, fence);
+ return send_msg(ring, bo, fence);
You can avoid the send_msg parameter altogether by just doing this in
the caller of the function.
Christian.
}
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
+ struct amdgpu_device *adev = ring->adev;
struct dma_fence *fence;
long r;
- r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
+ r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL,
+ amdgpu_vcn_dec_send_msg);
+ if (r)
+ goto error;
+
+ r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, ,
+ amdgpu_vcn_dec_send_msg);
+ if (r)
+ goto error;
+
+ r = dma_fence_wait_timeout(fence, false, timeout);
+ if (r == 0)
+ r = -ETIMEDOUT;
+ else if (r > 0)
+ r = 0;
+
+ dma_fence_put(fence);
+error:
+ return r;
+}
+
+static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
+ struct amdgpu_bo *bo,
+ struct dma_fence **fence)
+{
+ struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
+ const unsigned int ib_size_dw = 64;
+ struct amdgpu_device *adev = ring->adev;
+ struct dma_fence *f = NULL;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ uint64_t addr;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
+ AMDGPU_IB_POOL_DIRECT, );
+ if (r)
+ goto err;
+
+ ib = >ibs[0];
+ addr = amdgpu_bo_gpu_offset(bo);
+ ib->length_dw = 0;
+
+ ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
+ ib->ptr[ib->length_dw++] =
Re: [PATCH 1/5] drm/amdgpu: add vcn dec software ring enabled parameter
Am 11.11.20 um 23:27 schrieb James Zhu:
This allows us to enable dec software ring feature on VCN.
The default is 0 for all asics, and it is only valid for
asics with vcn3.0 and above.
Is that only supposed to be used for testing or do you really want to
upstream this?
A module parameter is always something the end user should be able to
change to get a certain result.
But if this is only used by a developer for testing then a define
somewhere in the code would be the more appropriate approach.
Christian.
Signed-off-by: James Zhu
Reviewed-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 20400ec..cc47da6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -209,6 +209,7 @@ extern int amdgpu_si_support;
extern int amdgpu_cik_support;
#endif
extern int amdgpu_num_kcq;
+extern int amdgpu_dec_sw_ring_enabled;
#define AMDGPU_VM_MAX_NUM_CTX 4096
#define AMDGPU_SG_THRESHOLD (256*1024*1024)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 999f84d..570088f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -160,6 +160,7 @@ int amdgpu_force_asic_type = -1;
int amdgpu_tmz;
int amdgpu_reset_method = -1; /* auto */
int amdgpu_num_kcq = -1;
+int amdgpu_dec_sw_ring_enabled;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -806,6 +807,13 @@ module_param_named(bad_page_threshold,
amdgpu_bad_page_threshold, int, 0444);
MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if
set to greater than 8 or less than 0, only affect gfx 8+)");
module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
+/**
+ * DOC: dec_sw_ring_enabled (uint)
+ * Override vcn decode software ring features enabled.
+ */
+MODULE_PARM_DESC(dec_sw_ring_enabled, "vcn dec sw ring support (1 = enable, 0 =
disable (default))");
+module_param_named(dec_sw_ring_enabled, amdgpu_dec_sw_ring_enabled, int, 0444);
+
static const struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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Re: [PATCH] drm/amdgpu: enable 48-bit IH timestamp counter
Feel free to keep my rb for this, but is 455 days enough in general or
should we add wrap around handling?
Christian.
Am 10.11.20 um 18:57 schrieb Sierra Guiza, Alejandro (Alex):
[AMD Public Use]
I just added support for vega10_ih too.
Regards,
Alex
-Original Message-
From: Sierra Guiza, Alejandro (Alex)
Sent: Tuesday, November 10, 2020 11:55 AM
To: amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; Kuehling, Felix
; Sierra Guiza, Alejandro (Alex)
Subject: [PATCH] drm/amdgpu: enable 48-bit IH timestamp counter
By default this timestamp is based on a 32 bit counter.
This is used by the amdgpu_gmc_filter_faults, to avoid process the same
interrupt in retry configuration.
Apparently there's a problem when the timestamp coming from IH overflows
and compares against timestamp coming from the the hash table.
This patch only extends the time overflow from 10 minutes to aprx 455 days.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 6 ++
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 6 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 837769fcb35b..bda916f33805 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -94,6 +94,8 @@ static void navi10_ih_enable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR,
1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+ RB_GPU_TS_ENABLE, 1);
if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL,
ih_rb_cntl)) {
DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
@@ -109,6 +111,8 @@ static void navi10_ih_enable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
mmIH_RB_CNTL_RING1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
RB_ENABLE, 1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
+ RB_GPU_TS_ENABLE, 1);
if (amdgpu_sriov_vf(adev) && adev->asic_type <
CHIP_NAVI10) {
if (psp_reg_program(>psp,
PSP_REG_IH_RB_CNTL_RING1,
ih_rb_cntl)) {
@@ -125,6 +129,8 @@ static void navi10_ih_enable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
RB_ENABLE, 1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
+ RB_GPU_TS_ENABLE, 1);
if (amdgpu_sriov_vf(adev) && adev->asic_type <
CHIP_NAVI10) {
if (psp_reg_program(>psp,
PSP_REG_IH_RB_CNTL_RING2,
ih_rb_cntl)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 407c6093c2ec..35d68bc5d95e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -50,6 +50,8 @@ static void vega10_ih_enable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR,
1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+ RB_GPU_TS_ENABLE, 1);
if (amdgpu_sriov_vf(adev)) {
if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL,
ih_rb_cntl)) {
DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
@@ -64,6 +66,8 @@ static void vega10_ih_enable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
mmIH_RB_CNTL_RING1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
RB_ENABLE, 1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
+ RB_GPU_TS_ENABLE, 1);
if (amdgpu_sriov_vf(adev)) {
if (psp_reg_program(>psp,
PSP_REG_IH_RB_CNTL_RING1,
ih_rb_cntl)) {
@@ -80,6 +84,8 @@ static void vega10_ih_enable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
RB_ENABLE, 1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
+ RB_GPU_TS_ENABLE, 1);
if
Re: [PATCH 03/40] drm/amd/display/dc/core/dc_link_ddc: Move DP_DVI_CONVERTER_ID_{4, 5} to where they're used
On Fri, Nov 13, 2020 at 8:50 AM Lee Jones wrote:
>
> This patch fixes >200 warnings.
>
> Fixes the following W=1 kernel build warning(s):
>
> from drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31:
> drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:126:22:
> warning: ‘DP_DVI_CONVERTER_ID_5’ defined but not used
> [-Wunused-const-variable=]
> 126 | static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
> | ^
> drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:125:22:
> warning: ‘DP_DVI_CONVERTER_ID_4’ defined but not used
> [-Wunused-const-variable=]
> 125 | static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
> | ^
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 4
> drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> index 54beda4d4e85d..c5936e0643606 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> @@ -37,6 +37,10 @@
> #include "dc_link_ddc.h"
> #include "dce/dce_aux.h"
>
> +/*DP to Dual link DVI converter*/
> +static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
> +static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
> +
> #define AUX_POWER_UP_WA_DELAY 500
> #define I2C_OVER_AUX_DEFER_WA_DELAY 70
> #define I2C_OVER_AUX_DEFER_WA_DELAY_1MS 1
> diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> index b453ce5a9bfdb..4de59b66bb1a3 100644
> --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> @@ -117,8 +117,4 @@ struct av_sync_data {
> uint8_t aud_del_ins3;/* DPCD 0002Dh */
> };
>
> -/*DP to Dual link DVI converter*/
> -static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
> -static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
> -
> #endif /* __DAL_DDC_SERVICE_TYPES_H__ */
> --
> 2.25.1
>
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Re: [PATCH 4/7] drm/radeon: Pin buffers while they are vmap'ed
Am 13.11.20 um 08:59 schrieb Thomas Zimmermann:
Hi Christian
Am 12.11.20 um 18:16 schrieb Christian König:
Am 12.11.20 um 14:21 schrieb Thomas Zimmermann:
In order to avoid eviction of vmap'ed buffers, pin them in their GEM
object's vmap implementation. Unpin them in the vunmap implementation.
This is needed to make generic fbdev support work reliably. Without,
the buffer object could be evicted while fbdev flushed its shadow buffer.
In difference to the PRIME pin/unpin functions, the vmap code does not
modify the BOs prime_shared_count, so a vmap-pinned BO does not count as
shared.
The actual pin location is not important as the vmap call returns
information on how to access the buffer. Callers that require a
specific location should explicitly pin the BO before vmapping it.
Well is the buffer supposed to be scanned out?
No, not by the fbdev helper.
Ok in this case that should work.
If yes then the pin location is actually rather important since the
hardware can only scan out from VRAM.
For relocatable BOs, fbdev uses a shadow buffer that makes all any
relocation transparent to userspace. It flushes the shadow fb into the
BO's memory if there are updates. The code is in
drm_fb_helper_dirty_work(). [1] During the flush operation, the vmap
call now pins the BO to wherever it is. The actual location does not
matter. It's vunmap'ed immediately afterwards.
The problem is what happens when it is prepared for scanout, but can't
be moved to VRAM because it is vmapped?
When the shadow is never scanned out that isn't a problem, but we need
to keep that in mind.
Regards,
Christian.
For dma-buf sharing, the regular procedure of pin + vmap still apply.
This should always move the BO into GTT-managed memory.
Best regards
Thomas
[1]
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ftorvalds%2Flinux.git%2Ftree%2Fdrivers%2Fgpu%2Fdrm%2Fdrm_fb_helper.c%23n432data=04%7C01%7Cchristian.koenig%40amd.com%7C31b890664ca7429fc45808d887aa0842%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637408511650629569%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=RLauuAuXkcl0rXwWWJ%2FrKP%2BsCr2wAzU1ejGV1bnQ80w%3Dreserved=0
Regards,
Christian.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/radeon/radeon_gem.c | 51 +++--
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c
b/drivers/gpu/drm/radeon/radeon_gem.c
index d2876ce3bc9e..eaf7fc9a7b07 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -226,6 +226,53 @@ static int radeon_gem_handle_lockup(struct
radeon_device *rdev, int r)
return r;
}
+static int radeon_gem_object_vmap(struct drm_gem_object *obj,
struct dma_buf_map *map)
+{
+ static const uint32_t any_domain = RADEON_GEM_DOMAIN_VRAM |
+ RADEON_GEM_DOMAIN_GTT |
+ RADEON_GEM_DOMAIN_CPU;
+
+ struct radeon_bo *bo = gem_to_radeon_bo(obj);
+ int ret;
+
+ ret = radeon_bo_reserve(bo, false);
+ if (ret)
+ return ret;
+
+ /* pin buffer at its current location */
+ ret = radeon_bo_pin(bo, any_domain, NULL);
+ if (ret)
+ goto err_radeon_bo_unreserve;
+
+ ret = drm_gem_ttm_vmap(obj, map);
+ if (ret)
+ goto err_radeon_bo_unpin;
+
+ radeon_bo_unreserve(bo);
+
+ return 0;
+
+err_radeon_bo_unpin:
+ radeon_bo_unpin(bo);
+err_radeon_bo_unreserve:
+ radeon_bo_unreserve(bo);
+ return ret;
+}
+
+static void radeon_gem_object_vunmap(struct drm_gem_object *obj,
struct dma_buf_map *map)
+{
+ struct radeon_bo *bo = gem_to_radeon_bo(obj);
+ int ret;
+
+ ret = radeon_bo_reserve(bo, false);
+ if (ret)
+ return;
+
+ drm_gem_ttm_vunmap(obj, map);
+ radeon_bo_unpin(bo);
+ radeon_bo_unreserve(bo);
+}
+
static const struct drm_gem_object_funcs radeon_gem_object_funcs = {
.free = radeon_gem_object_free,
.open = radeon_gem_object_open,
@@ -234,8 +281,8 @@ static const struct drm_gem_object_funcs
radeon_gem_object_funcs = {
.pin = radeon_gem_prime_pin,
.unpin = radeon_gem_prime_unpin,
.get_sg_table = radeon_gem_prime_get_sg_table,
- .vmap = drm_gem_ttm_vmap,
- .vunmap = drm_gem_ttm_vunmap,
+ .vmap = radeon_gem_object_vmap,
+ .vunmap = radeon_gem_object_vunmap,
};
/*
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Re: [PATCH 02/40] drm/amd/display/dc/core/dc_link_dp: Move DP_VGA_LVDS_CONVERTER_ID_{2, 3} to where they're used
On Fri, Nov 13, 2020 at 8:49 AM Lee Jones wrote:
>
> This patch fixes >200 warnings.
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:123:22:
> warning: ‘DP_VGA_LVDS_CONVERTER_ID_3’ defined but not used
> [-Wunused-const-variable=]
> 123 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> | ^~
> drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:121:22:
> warning: ‘DP_VGA_LVDS_CONVERTER_ID_2’ defined but not used
> [-Wunused-const-variable=]
> 121 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
>
> NB: Repeated ~100 times - snipped for brevity
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
Applied. thanks!
Alex
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c| 5 +
> drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 6c60c1fdebdc1..f2023d2b53234 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -15,6 +15,11 @@
> #include "dc_dmub_srv.h"
> #include "dce/dmub_hw_lock_mgr.h"
>
> +/*Travis*/
> +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
> +/*Nutmeg*/
> +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> +
> #define DC_LOGGER \
> link->ctx->logger
> #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
> diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> index c9be899cd25cd..b453ce5a9bfdb 100644
> --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> @@ -117,10 +117,6 @@ struct av_sync_data {
> uint8_t aud_del_ins3;/* DPCD 0002Dh */
> };
>
> -/*Travis*/
> -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
> -/*Nutmeg*/
> -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> /*DP to Dual link DVI converter*/
> static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
> static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
> --
> 2.25.1
>
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Re: [PATCH 02/40] drm/amd/display/dc/core/dc_link_dp: Move DP_VGA_LVDS_CONVERTER_ID_{2, 3} to where they're used
On Fri, Nov 13, 2020 at 10:23 AM Alex Deucher wrote:
>
> On Fri, Nov 13, 2020 at 8:49 AM Lee Jones wrote:
> >
> > This patch fixes >200 warnings.
> >
> > Fixes the following W=1 kernel build warning(s):
> >
> > drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:123:22:
> > warning: ‘DP_VGA_LVDS_CONVERTER_ID_3’ defined but not used
> > [-Wunused-const-variable=]
> > 123 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> > | ^~
> > drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:121:22:
> > warning: ‘DP_VGA_LVDS_CONVERTER_ID_2’ defined but not used
> > [-Wunused-const-variable=]
> > 121 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
> >
> > NB: Repeated ~100 times - snipped for brevity
> >
> > Cc: Harry Wentland
> > Cc: Leo Li
> > Cc: Alex Deucher
> > Cc: "Christian König"
> > Cc: David Airlie
> > Cc: Daniel Vetter
> > Cc: amd-gfx@lists.freedesktop.org
> > Cc: dri-de...@lists.freedesktop.org
> > Signed-off-by: Lee Jones
> > ---
> > drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c| 5 +
> > drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4
> > 2 files changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > index 6c60c1fdebdc1..f2023d2b53234 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > @@ -15,6 +15,11 @@
> > #include "dc_dmub_srv.h"
> > #include "dce/dmub_hw_lock_mgr.h"
> >
> > +/*Travis*/
> > +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
> > +/*Nutmeg*/
> > +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> > +
> > #define DC_LOGGER \
> > link->ctx->logger
> > #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
> > diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> > b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> > index c9be899cd25cd..b453ce5a9bfdb 100644
> > --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> > +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> > @@ -117,10 +117,6 @@ struct av_sync_data {
> > uint8_t aud_del_ins3;/* DPCD 0002Dh */
> > };
> >
> > -/*Travis*/
> > -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
> > -/*Nutmeg*/
> > -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> > /*DP to Dual link DVI converter*/
> > static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
> > static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
>
> Can we keep all of these strings together?
Nevermind, I hadn't seen the later patch that deals with the later ones.
Alex
>
> Alex
>
> > --
> > 2.25.1
> >
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Re: [PATCH 02/40] drm/amd/display/dc/core/dc_link_dp: Move DP_VGA_LVDS_CONVERTER_ID_{2, 3} to where they're used
On Fri, Nov 13, 2020 at 8:49 AM Lee Jones wrote:
>
> This patch fixes >200 warnings.
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:123:22:
> warning: ‘DP_VGA_LVDS_CONVERTER_ID_3’ defined but not used
> [-Wunused-const-variable=]
> 123 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> | ^~
> drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:121:22:
> warning: ‘DP_VGA_LVDS_CONVERTER_ID_2’ defined but not used
> [-Wunused-const-variable=]
> 121 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
>
> NB: Repeated ~100 times - snipped for brevity
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c| 5 +
> drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 6c60c1fdebdc1..f2023d2b53234 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -15,6 +15,11 @@
> #include "dc_dmub_srv.h"
> #include "dce/dmub_hw_lock_mgr.h"
>
> +/*Travis*/
> +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
> +/*Nutmeg*/
> +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> +
> #define DC_LOGGER \
> link->ctx->logger
> #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
> diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> index c9be899cd25cd..b453ce5a9bfdb 100644
> --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
> @@ -117,10 +117,6 @@ struct av_sync_data {
> uint8_t aud_del_ins3;/* DPCD 0002Dh */
> };
>
> -/*Travis*/
> -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
> -/*Nutmeg*/
> -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
> /*DP to Dual link DVI converter*/
> static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
> static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
Can we keep all of these strings together?
Alex
> --
> 2.25.1
>
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Re: [PATCH 01/40] drm/amd/include/vega10_ip_offset: Mark _BASE structs as __maybe_unused
On Fri, Nov 13, 2020 at 8:49 AM Lee Jones wrote:
>
> This patch fixes nearly 400 warnings!
>
> These structures are too widely used in too many varying
> configurations to be split-up into different headers or moved into
> source files.
>
> Instead, we'll mark them as __maybe_unused which tells the compiler
> that we're aware they're being included into source files which do not
> make use of them - but we've looked into it, and it's okay.
>
> Let's tidy-up whilst were here. Just alignment stuff.
>
> Fixes the following W=1 kernel build warning(s):
>
> In file included from drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c:27:
> drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:179:29: warning:
> ‘USB0_BASE’ defined but not used [-Wunused-const-variable=]
> 179 | static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B0,
> 0, 0, 0 } },
> | ^
> drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:172:29: warning:
> ‘UMC_BASE’ defined but not used [-Wunused-const-variable=]
> 172 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800,
> 0, 0, 0 } },
> | ^~~~
> drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:151:29: warning:
> ‘SDMA_BASE’ defined but not used [-Wunused-const-variable=]
> 151 | static const struct IP_BASE SDMA_BASE ={ { { { 0x1260, 0xA000,
> 0x02402C00, 0, 0 } },
> | ^
> drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:144:29: warning:
> ‘PCIE0_BASE’ defined but not used [-Wunused-const-variable=]
> 144 | static const struct IP_BASE PCIE0_BASE ={ { { { 0x,
> 0x0014, 0x0D20, 0x00010400, 0x0241B000 } },
> | ^~
>
> NB: Snipped for brevity
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
Applied. Thanks!
Alex
> ---
> .../gpu/drm/amd/include/vega10_ip_offset.h| 76 +--
> 1 file changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/vega10_ip_offset.h
> b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
> index 976dd2d565ba4..bb5463152f6b0 100644
> --- a/drivers/gpu/drm/amd/include/vega10_ip_offset.h
> +++ b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
> @@ -35,177 +35,177 @@ struct IP_BASE
> };
>
>
> -static const struct IP_BASE NBIF_BASE = { { { { 0x,
> 0x0014, 0x0D20, 0x00010400, 0 } },
> +static const struct IP_BASE __maybe_unused NBIF_BASE = { { { { 0x,
> 0x0014, 0x0D20, 0x00010400, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } } } };
> -static const struct IP_BASE NBIO_BASE = { { { { 0x,
> 0x0014, 0x0D20, 0x00010400, 0 } },
> +static const struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x,
> 0x0014, 0x0D20, 0x00010400, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } } } };
> -static const struct IP_BASE DCE_BASE = { { { { 0x0012,
> 0x00C0, 0x34C0, 0, 0 } },
> +static const struct IP_BASE __maybe_unused DCE_BASE= { { { { 0x0012,
> 0x00C0, 0x34C0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } } } };
> -static const struct IP_BASE DCN_BASE = { { { { 0x0012,
> 0x00C0, 0x34C0, 0, 0 } },
> +static const struct IP_BASE __maybe_unused DCN_BASE= { { { { 0x0012,
> 0x00C0, 0x34C0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
> { { 0, 0, 0, 0, 0 } },
>
Re: [PATCH] drm/amdgpu/display: fix FP handling in DCN30
On Thu, Nov 12, 2020 at 5:06 PM Bhawanpreet Lakha
wrote:
>
> From: Alex Deucher
>
> Adjust the FP handling to avoid nested calls.
>
> The nested calls cause the warning below
> WARNING: CPU: 3 PID: 384 at arch/x86/kernel/fpu/core.c:129 kernel_fpu_begin
>
> Fixes: 26803606c5d6 ("drm/amdgpu/display: FP fixes for DCN3.x (v4)")
> Signed-off-by: Alex Deucher
> Signed-off-by: Bhawanpreet Lakha
Looks good to me. Thanks!
Alex
> ---
> .../drm/amd/display/dc/dcn30/dcn30_resource.c | 43 +++
> 1 file changed, 6 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> index b379057e669c..d5c81ad55045 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> @@ -1470,20 +1470,8 @@ int dcn30_populate_dml_pipes_from_context(
> return pipe_cnt;
> }
>
> -/*
> - * This must be noinline to ensure anything that deals with FP registers
> - * is contained within this call; previously our compiling with hard-float
> - * would result in fp instructions being emitted outside of the boundaries
> - * of the DC_FP_START/END macros, which makes sense as the compiler has no
> - * idea about what is wrapped and what is not
> - *
> - * This is largely just a workaround to avoid breakage introduced with 5.6,
> - * ideally all fp-using code should be moved into its own file, only that
> - * should be compiled with hard-float, and all code exported from there
> - * should be strictly wrapped with DC_FP_START/END
> - */
> -static noinline void dcn30_populate_dml_writeback_from_context_fp(
> - struct dc *dc, struct resource_context *res_ctx,
> display_e2e_pipe_params_st *pipes)
> +void dcn30_populate_dml_writeback_from_context(
> + struct dc *dc, struct resource_context *res_ctx,
> display_e2e_pipe_params_st *pipes)
> {
> int pipe_cnt, i, j;
> double max_calc_writeback_dispclk;
> @@ -1571,14 +1559,6 @@ static noinline void
> dcn30_populate_dml_writeback_from_context_fp(
>
> }
>
> -void dcn30_populate_dml_writeback_from_context(
> - struct dc *dc, struct resource_context *res_ctx,
> display_e2e_pipe_params_st *pipes)
> -{
> - DC_FP_START();
> - dcn30_populate_dml_writeback_from_context_fp(dc, res_ctx, pipes);
> - DC_FP_END();
> -}
> -
> unsigned int dcn30_calc_max_scaled_time(
> unsigned int time_per_pixel,
> enum mmhubbub_wbif_mode mode,
> @@ -1977,7 +1957,7 @@ static struct pipe_ctx *dcn30_find_split_pipe(
> return pipe;
> }
>
> -static bool dcn30_internal_validate_bw(
> +static noinline bool dcn30_internal_validate_bw(
> struct dc *dc,
> struct dc_state *context,
> display_e2e_pipe_params_st *pipes,
> @@ -1999,6 +1979,7 @@ static bool dcn30_internal_validate_bw(
>
> pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context,
> pipes, fast_validate);
>
> + DC_FP_START();
> if (!pipe_cnt) {
> out = true;
> goto validate_out;
> @@ -,6 +2203,7 @@ static bool dcn30_internal_validate_bw(
> out = false;
>
> validate_out:
> + DC_FP_END();
> return out;
> }
>
> @@ -2404,7 +2386,7 @@ void dcn30_calculate_wm_and_dlg(
> DC_FP_END();
> }
>
> -static noinline bool dcn30_validate_bandwidth_fp(struct dc *dc,
> +bool dcn30_validate_bandwidth(struct dc *dc,
> struct dc_state *context,
> bool fast_validate)
> {
> @@ -2455,19 +2437,6 @@ static noinline bool
> dcn30_validate_bandwidth_fp(struct dc *dc,
> return out;
> }
>
> -bool dcn30_validate_bandwidth(struct dc *dc,
> - struct dc_state *context,
> - bool fast_validate)
> -{
> - bool out;
> -
> - DC_FP_START();
> - out = dcn30_validate_bandwidth_fp(dc, context, fast_validate);
> - DC_FP_END();
> -
> - return out;
> -}
> -
> static noinline void get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
> unsigned int
> *optimal_dcfclk,
> unsigned int
> *optimal_fclk)
> --
> 2.25.1
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 27/40] drm/amd/amdgpu/amdgpu_ras: Remove unused function 'amdgpu_ras_error_cure'
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:908:5: warning: no previous prototype
for ‘amdgpu_ras_error_cure’ [-Wmissing-prototypes]
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index b96267068a72d..f89a991999428 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -905,13 +905,6 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
return ret;
}
-int amdgpu_ras_error_cure(struct amdgpu_device *adev,
- struct ras_cure_if *info)
-{
- /* psp fw has no cure interface for now. */
- return 0;
-}
-
/* get the total error counts on all IPs */
unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
bool is_ce)
--
2.25.1
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[PATCH 30/40] drm/amd/amdgpu/amdgpu_vm_cpu: Fix 'amdgpu_vm_cpu_prepare()'s doc-rot
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Function parameter or member 'resv' not described in 'amdgpu_vm_cpu_prepare' drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Function parameter or member 'sync_mode' not described in 'amdgpu_vm_cpu_prepare' drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Excess function parameter 'owner' description in 'amdgpu_vm_cpu_prepare' drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Excess function parameter 'exclusive' description in 'amdgpu_vm_cpu_prepare' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Sumit Semwal Cc: Felix Kuehling Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Cc: linux-me...@vger.kernel.org Cc: linaro-mm-...@lists.linaro.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index 0786e754b..ac45d9c7a4e94 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -38,8 +38,8 @@ static int amdgpu_vm_cpu_map_table(struct amdgpu_bo *table) * amdgpu_vm_cpu_prepare - prepare page table update with the CPU * * @p: see amdgpu_vm_update_params definition - * @owner: owner we need to sync to - * @exclusive: exclusive move fence we need to sync to + * @resv: reservation object with embedded fence + * @sync_mode: synchronization mode * * Returns: * Negativ errno, 0 for success. -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 22/40] drm/amd/amdgpu/amdgpu_sched: Consume our own header containing prototypes
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c:35:5: warning: no previous prototype for ‘amdgpu_to_sched_priority’ [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c:122:5: warning: no previous prototype for ‘amdgpu_sched_ioctl’ [-Wmissing-prototypes] Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Luben Tuikov Cc: Andres Rodriguez Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c index 0da0a0d986720..b7d861ed52849 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c @@ -29,7 +29,7 @@ #include #include "amdgpu.h" - +#include "amdgpu_sched.h" #include "amdgpu_vm.h" int amdgpu_to_sched_priority(int amdgpu_priority, -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 03/40] drm/amd/display/dc/core/dc_link_ddc: Move DP_DVI_CONVERTER_ID_{4, 5} to where they're used
This patch fixes >200 warnings.
Fixes the following W=1 kernel build warning(s):
from drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31:
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:126:22:
warning: ‘DP_DVI_CONVERTER_ID_5’ defined but not used [-Wunused-const-variable=]
126 | static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
| ^
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:125:22:
warning: ‘DP_DVI_CONVERTER_ID_4’ defined but not used [-Wunused-const-variable=]
125 | static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
| ^
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 4
drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 54beda4d4e85d..c5936e0643606 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -37,6 +37,10 @@
#include "dc_link_ddc.h"
#include "dce/dce_aux.h"
+/*DP to Dual link DVI converter*/
+static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
+static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
+
#define AUX_POWER_UP_WA_DELAY 500
#define I2C_OVER_AUX_DEFER_WA_DELAY 70
#define I2C_OVER_AUX_DEFER_WA_DELAY_1MS 1
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index b453ce5a9bfdb..4de59b66bb1a3 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -117,8 +117,4 @@ struct av_sync_data {
uint8_t aud_del_ins3;/* DPCD 0002Dh */
};
-/*DP to Dual link DVI converter*/
-static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
-static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
-
#endif /* __DAL_DDC_SERVICE_TYPES_H__ */
--
2.25.1
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[PATCH 08/40] drm/amd/amdgpu/amdgpu_ib: Fix some incorrect/incomplete function documentation
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:66: warning: Function parameter or member 'adev' not described in 'amdgpu_ib_get' drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:66: warning: Function parameter or member 'vm' not described in 'amdgpu_ib_get' drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:66: warning: Function parameter or member 'pool_type' not described in 'amdgpu_ib_get' drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:66: warning: Excess function parameter 'ring' description in 'amdgpu_ib_get' drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:125: warning: Function parameter or member 'ring' not described in 'amdgpu_ib_schedule' drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:125: warning: Function parameter or member 'job' not described in 'amdgpu_ib_schedule' drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:125: warning: Excess function parameter 'adev' description in 'amdgpu_ib_schedule' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Sumit Semwal Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Cc: linux-me...@vger.kernel.org Cc: linaro-mm-...@lists.linaro.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 2f53fa0ae9a62..c69af9b86cc60 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -52,8 +52,10 @@ /** * amdgpu_ib_get - request an IB (Indirect Buffer) * - * @ring: ring index the IB is associated with + * @adev: amdgpu_device pointer + * @vm: amdgpu_vm pointer * @size: requested IB size + * @pool_type: IB pool type (delayed, immediate, direct) * @ib: IB object returned * * Request an IB (all asics). IBs are allocated using the @@ -101,7 +103,7 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, /** * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring * - * @adev: amdgpu_device pointer + * @ring: ring index the IB is associated with * @num_ibs: number of IBs to schedule * @ibs: IB objects to schedule * @f: fence created during this submission -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 21/40] drm/amd/amdgpu/amdgpu_virt: Make local function 'amdgpu_virt_update_vf2pf_work_item()' static
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:560:6: warning: no previous prototype
for ‘amdgpu_virt_update_vf2pf_work_item’ [-Wmissing-prototypes]
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 8aff6ef50f918..905b85391e64a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -557,7 +557,7 @@ static int amdgpu_virt_write_vf2pf_data(struct
amdgpu_device *adev)
return 0;
}
-void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
+static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
{
struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
virt.vf2pf_work.work);
--
2.25.1
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[PATCH 05/40] drm/amd/amdgpu/amdgpu_ring: Fix misnaming of param 'max_dw'
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c:168: warning: Function parameter or member 'max_dw' not described in 'amdgpu_ring_init' drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c:168: warning: Excess function parameter 'max_ndw' description in 'amdgpu_ring_init' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Sumit Semwal Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Cc: linux-me...@vger.kernel.org Cc: linaro-mm-...@lists.linaro.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index a23b2079696a1..1a612f51ecd9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -154,7 +154,7 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) * * @adev: amdgpu_device pointer * @ring: amdgpu_ring structure holding ring information - * @max_ndw: maximum number of dw for ring alloc + * @max_dw: maximum number of dw for ring alloc * @irq_src: interrupt source to use for this ring * @irq_type: interrupt type to use for this ring * @hw_prio: ring priority (NORMAL/HIGH) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 26/40] drm/amd/amdgpu/amdgpu_gmc: Demote one and fix another function header
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:69: warning: Function parameter or
member 'bo' not described in 'amdgpu_gmc_pd_addr'
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:121: warning: Function parameter or
member 'bo' not described in 'amdgpu_gmc_agp_addr'
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:121: warning: Excess function
parameter 'tbo' description in 'amdgpu_gmc_agp_addr'
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 056cb87d09ea3..fede84509dbca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -61,9 +61,8 @@ void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int
level,
amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
}
-/**
+/*
* amdgpu_gmc_pd_addr - return the address of the root directory
- *
*/
uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
{
@@ -112,7 +111,7 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void
*cpu_pt_addr,
/**
* amdgpu_gmc_agp_addr - return the address in the AGP address space
*
- * @tbo: TTM BO which needs the address, must be in GTT domain
+ * @bo: TTM BO which needs the address, must be in GTT domain
*
* Tries to figure out how to access the BO through the AGP aperture. Returns
* AMDGPU_BO_INVALID_OFFSET if that is not possible.
--
2.25.1
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[PATCH 19/40] drm/amd/amdgpu/amdgpu_vram_mgr: Add missing descriptions for 'dev' and 'dir'
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:648: warning: Function parameter or member 'dev' not described in 'amdgpu_vram_mgr_free_sgt' drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:648: warning: Function parameter or member 'dir' not described in 'amdgpu_vram_mgr_free_sgt' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index c99c2180785fe..d2de2a720a3d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -637,6 +637,8 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, * amdgpu_vram_mgr_free_sgt - allocate and fill a sg table * * @adev: amdgpu device pointer + * @dev: device pointer + * @dir: data direction of resource to unmap * @sgt: sg table to free * * Free a previously allocate sg table. -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/40] drm/amd/amdgpu/amdgpu_drv: Move 'amdgpu_info_ioctl()'s prototype to shared header
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c:486:5: warning: no previous prototype
for ‘amdgpu_info_ioctl’ [-Wmissing-prototypes]
486 | int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct
drm_file *filp)
| ^
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h | 31 +
3 files changed, 33 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 1dfea15bbec36..afd357df0f886 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -43,7 +43,7 @@
#include "amdgpu_sched.h"
#include "amdgpu_amdkfd.h"
-
+#include "amdgpu_kms.h"
#include "amdgpu_ras.h"
/*
@@ -1521,8 +1521,6 @@ int amdgpu_file_to_fpriv(struct file *filp, struct
amdgpu_fpriv **fpriv)
return 0;
}
-int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
*filp);
-
const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 98721ae931841..54c4ee6d230d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -41,6 +41,7 @@
#include "amdgpu_amdkfd.h"
#include "amdgpu_gem.h"
#include "amdgpu_display.h"
+#include "amdgpu_kms.h"
#include "amdgpu_ras.h"
void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h
new file mode 100644
index 0..f3111aef76cae
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h
@@ -0,0 +1,31 @@
+/* amdgpu_kms.h -- Private header for radeon driver -*- linux-c -*-
+ *
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __AMDGPU_KMS_H__
+#define __AMDGPU_KMS_H__
+
+int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
*filp);
+
+#endif /* __AMDGPU_KMS_H__ */
--
2.25.1
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[PATCH 40/40] drm/amd/amdgpu/gfx_v7_0: Remove unused struct definition
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:5211:45: warning: ‘gfx_v7_0_ip_block’
defined but not used [-Wunused-const-variable=]
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Sumit Semwal
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 9 -
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h | 1 -
2 files changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index cb07bc21dcbe5..04e1e92f5f3cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -5208,15 +5208,6 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device
*adev)
cu_info->lds_size = 64;
}
-static const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
-{
- .type = AMD_IP_BLOCK_TYPE_GFX,
- .major = 7,
- .minor = 0,
- .rev = 0,
- .funcs = _v7_0_ip_funcs,
-};
-
const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
{
.type = AMD_IP_BLOCK_TYPE_GFX,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
index 6fb9c1524691f..eedce7d007f1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
@@ -24,7 +24,6 @@
#ifndef __GFX_V7_0_H__
#define __GFX_V7_0_H__
-extern const struct amdgpu_ip_block_version gfx_v7_0_ip_block;
extern const struct amdgpu_ip_block_version gfx_v7_1_ip_block;
extern const struct amdgpu_ip_block_version gfx_v7_2_ip_block;
extern const struct amdgpu_ip_block_version gfx_v7_3_ip_block;
--
2.25.1
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[PATCH 00/40] [Set 7] Rid W=1 warnings from GPU
This set is part of a larger effort attempting to clean-up W=1
kernel builds, which are currently overwhelmingly riddled with
niggly little warnings.
This brings the running total from 5000 (in v5.9) down to 1400!
Hopefully not too much more to go now.
Lee Jones (40):
drm/amd/include/vega10_ip_offset: Mark _BASE structs as __maybe_unused
drm/amd/display/dc/core/dc_link_dp: Move
DP_VGA_LVDS_CONVERTER_ID_{2,3} to where they're used
drm/amd/display/dc/core/dc_link_ddc: Move DP_DVI_CONVERTER_ID_{4,5} to
where they're used
drm/amd/amdgpu/amdgpu_drv: Move 'amdgpu_info_ioctl()'s prototype to
shared header
drm/amd/amdgpu/amdgpu_ring: Fix misnaming of param 'max_dw'
drm/msm/adreno/a6xx_gpu: Staticise local function 'a6xx_idle'
drm/mediatek/mtk_disp_rdma: Fix formatting and supply missing struct
member description
drm/amd/amdgpu/amdgpu_ib: Fix some incorrect/incomplete function
documentation
drm/mediatek/mtk_drm_crtc: Demote seriously out-of-date struct header
drm/mediatek/mtk_drm_drv: Staticise local function invoked by
reference
drm/amd/amdgpu/amdgpu_pll: Fix kernel-doc formatting, missing and
extra params
drm/pl111/pl111_display: Make local function static
drm/panel/panel-tpo-tpg110: Correct misnaming and supply missing param
description
drm/meson/meson_venc: Make local function
'meson_venc_hdmi_get_dmt_vmode' static
drm/lima/lima_drv: Demote kernel-doc formatting abuse
drm/amd/amdgpu/amdgpu_sync: Fix misnamed, missing and extra param
descriptions
drm/meson/meson_vclk: Make two local functions static
drm/mediatek/mtk_dpi: Remove unused struct definition
'mtk_dpi_encoder_funcs'
drm/amd/amdgpu/amdgpu_vram_mgr: Add missing descriptions for 'dev' and
'dir'
drm/pl111/pl111_debugfs: Make local function 'pl111_debugfs_regs()'
static
drm/amd/amdgpu/amdgpu_virt: Make local function
'amdgpu_virt_update_vf2pf_work_item()' static
drm/amd/amdgpu/amdgpu_sched: Consume our own header containing
prototypes
drm/lima/lima_sched: Remove unused and unnecessary variable 'ret'
drm/amd/amdgpu/amdgpu_ids: Supply missing docs for 'id' and 'vmhub'
drm/amd/amdgpu/amdgpu_debugfs: Demote obvious abuse of kernel-doc
formatting
drm/amd/amdgpu/amdgpu_gmc: Demote one and fix another function header
drm/amd/amdgpu/amdgpu_ras: Remove unused function
'amdgpu_ras_error_cure'
drm/amd/amdgpu/amdgpu_ras: Make local function
'amdgpu_ras_error_status_query' static
drm/amd/amdgpu/amdgpu_csa: Remove set but unused variable 'r'
drm/amd/amdgpu/amdgpu_vm_cpu: Fix 'amdgpu_vm_cpu_prepare()'s doc-rot
drm/amd/amdgpu/amdgpu_vm_sdma: Fix 'amdgpu_vm_sdma_prepare()'s doc-rot
drm/msm/disp/mdp5/mdp5_crtc: Make local function
'mdp5_crtc_setup_pipeline()' static
drm/drm_dp_mst_topology: Remove set but never used variable 'len'
drm/msm/disp/mdp5/mdp5_ctl: Demote non-conformant kernel-doc headers
drm/msm/disp/mdp5/mdp5_kms: Make local functions 'mdp5_{en,dis}able()'
static
drm/amd/amdgpu/amdgpu_fw_attestation: Consume our own header
containing prototypes
drm/amd/amdgpu/smu_v11_0_i2c: Provide descriptions for 'control' and
'data' params
drm/msm/disp/dpu1/dpu_core_perf: Remove set but unused variable
'dpu_cstate'
drm/msm/disp/dpu1/dpu_encoder: Remove a bunch of unused variables
drm/amd/amdgpu/gfx_v7_0: Remove unused struct definition
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +-
.../drm/amd/amdgpu/amdgpu_fw_attestation.c| 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c| 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.h | 31
drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c | 10 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 11 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 +
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 9 ---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h | 1 -
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c| 3 +
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 4 +
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 5 ++
.../amd/display/include/ddc_service_types.h | 8 --
.../gpu/drm/amd/include/vega10_ip_offset.h| 76 +--
drivers/gpu/drm/drm_dp_mst_topology.c | 4 +-
drivers/gpu/drm/lima/lima_drv.c | 2 +-
drivers/gpu/drm/lima/lima_sched.c | 3 +-
[PATCH 11/40] drm/amd/amdgpu/amdgpu_pll: Fix kernel-doc formatting, missing and extra params
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:121: warning: Function parameter or member 'freq' not described in 'amdgpu_pll_compute' drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:121: warning: Function parameter or member 'fb_div_p' not described in 'amdgpu_pll_compute' drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:121: warning: Function parameter or member 'frac_fb_div_p' not described in 'amdgpu_pll_compute' drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:121: warning: Function parameter or member 'ref_div_p' not described in 'amdgpu_pll_compute' drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:121: warning: Function parameter or member 'post_div_p' not described in 'amdgpu_pll_compute' drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c:317: warning: Excess function parameter 'encoder' description in 'amdgpu_pll_get_shared_nondp_ppll' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c index 1f2305b7bd135..f2e20666c9c1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c @@ -102,11 +102,12 @@ static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_ * amdgpu_pll_compute - compute PLL paramaters * * @pll: information about the PLL + * @freq: requested frequency * @dot_clock_p: resulting pixel clock - * fb_div_p: resulting feedback divider - * frac_fb_div_p: fractional part of the feedback divider - * ref_div_p: resulting reference divider - * post_div_p: resulting reference divider + * @fb_div_p: resulting feedback divider + * @frac_fb_div_p: fractional part of the feedback divider + * @ref_div_p: resulting reference divider + * @post_div_p: resulting reference divider * * Try to calculate the PLL parameters to generate the given frequency: * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) @@ -308,7 +309,6 @@ int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc) * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc * * @crtc: drm crtc - * @encoder: drm encoder * * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can * be shared (i.e., same clock). -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 28/40] drm/amd/amdgpu/amdgpu_ras: Make local function 'amdgpu_ras_error_status_query' static
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1482:6: warning: no previous prototype
for ‘amdgpu_ras_error_status_query’ [-Wmissing-prototypes]
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index f89a991999428..9d11b847e6efe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1472,8 +1472,8 @@ static void amdgpu_ras_log_on_err_counter(struct
amdgpu_device *adev)
}
/* Parse RdRspStatus and WrRspStatus */
-void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
- struct ras_query_if *info)
+static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
+ struct ras_query_if *info)
{
/*
* Only two block need to query read/write
--
2.25.1
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[PATCH 31/40] drm/amd/amdgpu/amdgpu_vm_sdma: Fix 'amdgpu_vm_sdma_prepare()'s doc-rot
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c:63: warning: Function parameter or member 'resv' not described in 'amdgpu_vm_sdma_prepare' drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c:63: warning: Function parameter or member 'sync_mode' not described in 'amdgpu_vm_sdma_prepare' drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c:63: warning: Excess function parameter 'owner' description in 'amdgpu_vm_sdma_prepare' drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c:63: warning: Excess function parameter 'exclusive' description in 'amdgpu_vm_sdma_prepare' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Sumit Semwal Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Cc: linux-me...@vger.kernel.org Cc: linaro-mm-...@lists.linaro.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index db790574dc2e8..a83a646759c58 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -51,8 +51,8 @@ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo *table) * amdgpu_vm_sdma_prepare - prepare SDMA command submission * * @p: see amdgpu_vm_update_params definition - * @owner: owner we need to sync to - * @exclusive: exclusive move fence we need to sync to + * @resv: reservation object with embedded fence + * @sync_mode: synchronization mode * * Returns: * Negativ errno, 0 for success. -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 29/40] drm/amd/amdgpu/amdgpu_csa: Remove set but unused variable 'r'
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c: In function
‘amdgpu_allocate_static_csa’:
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c:40:6: warning: variable ‘r’ set but
not used [-Wunused-but-set-variable]
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: monk@amd.com
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index 08047bc4d5886..da21e60bb8272 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -37,10 +37,9 @@ uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo
**bo,
u32 domain, uint32_t size)
{
- int r;
void *ptr;
- r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
+ amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
domain, bo,
NULL, );
if (!*bo)
--
2.25.1
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[PATCH 16/40] drm/amd/amdgpu/amdgpu_sync: Fix misnamed, missing and extra param descriptions
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c:86: warning: Function parameter or member 'f' not described in 'amdgpu_sync_get_owner' drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c:86: warning: Excess function parameter 'fence' description in 'amdgpu_sync_get_owner' drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c:182: warning: Excess function parameter 'adev' description in 'amdgpu_sync_vm_fence' drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c:203: warning: Function parameter or member 'adev' not described in 'amdgpu_sync_resv' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Sumit Semwal Cc: Felix Kuehling Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Cc: linux-me...@vger.kernel.org Cc: linaro-mm-...@lists.linaro.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 8ea6c49529e7d..4e558632a5d2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -78,7 +78,7 @@ static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, /** * amdgpu_sync_get_owner - extract the owner of a fence * - * @fence: fence get the owner from + * @f: fence get the owner from * * Extract who originally created the fence. */ @@ -172,7 +172,6 @@ int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f) /** * amdgpu_sync_vm_fence - remember to sync to this VM fence * - * @adev: amdgpu device * @sync: sync object to add fence to * @fence: the VM fence to add * @@ -190,6 +189,7 @@ int amdgpu_sync_vm_fence(struct amdgpu_sync *sync, struct dma_fence *fence) /** * amdgpu_sync_resv - sync to a reservation object * + * @adev: amdgpu device * @sync: sync object to add fences from reservation object to * @resv: reservation object with embedded fence * @mode: how owner affects which fences we sync to -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 36/40] drm/amd/amdgpu/amdgpu_fw_attestation: Consume our own header containing prototypes
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c:130:6: warning: no previous prototype for ‘amdgpu_fw_attestation_debugfs_init’ [-Wmissing-prototypes] Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Hawking Zhang Cc: John Clements Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c index c6947d6c7ff51..e47bca1c76359 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c @@ -26,6 +26,7 @@ #include #include "amdgpu.h" +#include "amdgpu_fw_attestation.h" #include "amdgpu_psp.h" #include "amdgpu_ucode.h" #include "soc15_common.h" @@ -139,4 +140,4 @@ void amdgpu_fw_attestation_debugfs_init(struct amdgpu_device *adev) adev, _fw_attestation_debugfs_ops); #endif -} \ No newline at end of file +} -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 24/40] drm/amd/amdgpu/amdgpu_ids: Supply missing docs for 'id' and 'vmhub'
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:271: warning: Function parameter or member 'id' not described in 'amdgpu_vmid_grab_reserved' drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:523: warning: Function parameter or member 'vmhub' not described in 'amdgpu_vmid_reset' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Sumit Semwal Cc: Felix Kuehling Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Cc: linux-me...@vger.kernel.org Cc: linaro-mm-...@lists.linaro.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index 6e9a9e5dbea07..61a1331f482c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -259,6 +259,7 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm, * @sync: sync object where we add dependencies * @fence: fence protecting ID from reuse * @job: job who wants to use the VMID + * @id: resulting VMID * * Try to assign a reserved VMID. */ @@ -514,6 +515,7 @@ void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, * amdgpu_vmid_reset - reset VMID to zero * * @adev: amdgpu device structure + * @vmhub: vmhub type * @vmid: vmid number to use * * Reset saved GDW, GWS and OA to force switch on next flush. -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 25/40] drm/amd/amdgpu/amdgpu_debugfs: Demote obvious abuse of kernel-doc formatting
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:308: warning: Function parameter or member 'f' not described in 'amdgpu_debugfs_regs_read' drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:308: warning: Function parameter or member 'buf' not described in 'amdgpu_debugfs_regs_read' drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:308: warning: Function parameter or member 'size' not described in 'amdgpu_debugfs_regs_read' drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:308: warning: Function parameter or member 'pos' not described in 'amdgpu_debugfs_regs_read' drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:317: warning: Function parameter or member 'f' not described in 'amdgpu_debugfs_regs_write' drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:317: warning: Function parameter or member 'buf' not described in 'amdgpu_debugfs_regs_write' drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:317: warning: Function parameter or member 'size' not described in 'amdgpu_debugfs_regs_write' drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:317: warning: Function parameter or member 'pos' not described in 'amdgpu_debugfs_regs_write' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Sumit Semwal Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Cc: linux-me...@vger.kernel.org Cc: linaro-mm-...@lists.linaro.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 5c1f3725c7410..a6667a2ca0db3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -300,7 +300,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, return result; } -/** +/* * amdgpu_debugfs_regs_read - Callback for reading MMIO registers */ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, @@ -309,7 +309,7 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos); } -/** +/* * amdgpu_debugfs_regs_write - Callback for writing MMIO registers */ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 00/19] [Set 2] Rid W=1 warnings from GPU
On Fri, 13 Nov 2020, Alex Deucher wrote:
> On Fri, Nov 13, 2020 at 2:19 AM Lee Jones wrote:
> >
> > On Fri, 06 Nov 2020, Lee Jones wrote:
> >
> > > This set is part of a larger effort attempting to clean-up W=1
> > > kernel builds, which are currently overwhelmingly riddled with
> > > niggly little warnings.
> > >
> > > There are 5000 warnings to work through. It will take a couple more
> > > sets. Although, ("drm/amd/display/dc/basics/fixpt31_32: Move
> > > variables to where they're used") does take care of 2000 of them!
> > >
> > > Lee Jones (19):
> > > drm/ttm/ttm_range_manager: Demote non-conformant kernel-doc header
> > > drm/r128/ati_pcigart: Source file headers are not good candidates for
> > > kernel-doc
> > > drm/selftests/test-drm_dp_mst_helper: Move
> > > 'sideband_msg_req_encode_decode' onto the heap
> > > drm/mga/mga_dma: Demote kernel-doc abusers to standard comment blocks
> > > drm/mga/mga_state: Remove unused variable 'buf_priv'
> > > drm/radeon/atom: Move prototype into shared location
> > > drm/radeon/radeon_kms: Include header containing our own prototypes
> > > drm/omapdrm/omap_gem: Fix misnamed and missing parameter descriptions
> > > drm/omapdrm/omap_dmm_tiler: Demote abusive use of kernel-doc format
> > > drm/radeon/radeon: Move prototype into shared header
> > > drm/radeon/radeon_drv: Source file headers are not good candidates for
> > > kernel-doc
> > > drm/amd/display/dc/basics/fixpt31_32: Move variables to where they're
> > > used
> > > drm/radeon/radeon_drv: Move prototypes to a shared headerfile
> > > drm/amd/amdgpu/amdgpu_device: Provide documentation for 'reg_addr'
> > > params
> > > drm/radeon: Move prototypes to shared header
> > > drm/amd/amdgpu/amdgpu_kms: Remove 'struct drm_amdgpu_info_device
> > > dev_info' from the stack
> > > drm/radeon/radeon_kms: Fix misnaming of 'radeon_info_ioctl's dev param
> > > drm/radeon/atombios_crtc: Remove description of non-existent function
> > > param 'encoder'
> > > drm/v3d/v3d_drv: Remove unused static variable 'v3d_v3d_pm_ops'
> > >
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 +
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 104 +-
> > > .../drm/amd/display/dc/basics/fixpt31_32.c| 5 +
> > > .../gpu/drm/amd/display/include/fixed31_32.h | 6 -
> > > drivers/gpu/drm/mga/mga_dma.c | 10 +-
> > > drivers/gpu/drm/mga/mga_state.c | 2 -
> > > drivers/gpu/drm/omapdrm/omap_dmm_tiler.c | 6 +-
> > > drivers/gpu/drm/omapdrm/omap_gem.c| 3 +-
> > > drivers/gpu/drm/r128/ati_pcigart.c| 2 +-
> > > drivers/gpu/drm/radeon/atom.h | 6 +
> > > drivers/gpu/drm/radeon/atombios_crtc.c| 1 -
> > > drivers/gpu/drm/radeon/atombios_encoders.c| 4 -
> > > drivers/gpu/drm/radeon/radeon.h | 6 +
> > > drivers/gpu/drm/radeon/radeon_device.c| 1 +
> > > drivers/gpu/drm/radeon/radeon_device.h| 32 ++
> > > drivers/gpu/drm/radeon/radeon_display.c | 4 -
> > > drivers/gpu/drm/radeon/radeon_drv.c | 11 +-
> > > drivers/gpu/drm/radeon/radeon_drv.h | 7 ++
> > > drivers/gpu/drm/radeon/radeon_kms.c | 3 +-
> > > .../drm/selftests/test-drm_dp_mst_helper.c| 11 +-
> > > drivers/gpu/drm/ttm/ttm_range_manager.c | 2 +-
> > > drivers/gpu/drm/v3d/v3d_drv.c | 36 --
> > > 22 files changed, 138 insertions(+), 126 deletions(-)
> > > create mode 100644 drivers/gpu/drm/radeon/radeon_device.h
> >
> > Still no Radeon patches in today's -next.
> >
> > I really wanted to have had this set rebased by now.
> >
> > How long do they take to peculate through?
>
> Usually a day or two, but I was swamped the last couple of days. I
> pushed an updated -next branch today:
> https://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next
Ah, wonderful.
I'll rebase all of the sets on Monday and see what we're left with.
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
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[PATCH 02/40] drm/amd/display/dc/core/dc_link_dp: Move DP_VGA_LVDS_CONVERTER_ID_{2, 3} to where they're used
This patch fixes >200 warnings.
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:123:22:
warning: ‘DP_VGA_LVDS_CONVERTER_ID_3’ defined but not used
[-Wunused-const-variable=]
123 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
| ^~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:121:22:
warning: ‘DP_VGA_LVDS_CONVERTER_ID_2’ defined but not used
[-Wunused-const-variable=]
121 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
NB: Repeated ~100 times - snipped for brevity
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c| 5 +
drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 6c60c1fdebdc1..f2023d2b53234 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -15,6 +15,11 @@
#include "dc_dmub_srv.h"
#include "dce/dmub_hw_lock_mgr.h"
+/*Travis*/
+static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
+/*Nutmeg*/
+static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
+
#define DC_LOGGER \
link->ctx->logger
#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index c9be899cd25cd..b453ce5a9bfdb 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -117,10 +117,6 @@ struct av_sync_data {
uint8_t aud_del_ins3;/* DPCD 0002Dh */
};
-/*Travis*/
-static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
-/*Nutmeg*/
-static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
/*DP to Dual link DVI converter*/
static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
--
2.25.1
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[PATCH 01/40] drm/amd/include/vega10_ip_offset: Mark _BASE structs as __maybe_unused
This patch fixes nearly 400 warnings!
These structures are too widely used in too many varying
configurations to be split-up into different headers or moved into
source files.
Instead, we'll mark them as __maybe_unused which tells the compiler
that we're aware they're being included into source files which do not
make use of them - but we've looked into it, and it's okay.
Let's tidy-up whilst were here. Just alignment stuff.
Fixes the following W=1 kernel build warning(s):
In file included from drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c:27:
drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:179:29: warning:
‘USB0_BASE’ defined but not used [-Wunused-const-variable=]
179 | static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B0,
0, 0, 0 } },
| ^
drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:172:29: warning:
‘UMC_BASE’ defined but not used [-Wunused-const-variable=]
172 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0,
0, 0 } },
| ^~~~
drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:151:29: warning:
‘SDMA_BASE’ defined but not used [-Wunused-const-variable=]
151 | static const struct IP_BASE SDMA_BASE ={ { { { 0x1260, 0xA000,
0x02402C00, 0, 0 } },
| ^
drivers/gpu/drm/amd/amdgpu/../include/navi14_ip_offset.h:144:29: warning:
‘PCIE0_BASE’ defined but not used [-Wunused-const-variable=]
144 | static const struct IP_BASE PCIE0_BASE ={ { { { 0x, 0x0014,
0x0D20, 0x00010400, 0x0241B000 } },
| ^~
NB: Snipped for brevity
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../gpu/drm/amd/include/vega10_ip_offset.h| 76 +--
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/vega10_ip_offset.h
b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
index 976dd2d565ba4..bb5463152f6b0 100644
--- a/drivers/gpu/drm/amd/include/vega10_ip_offset.h
+++ b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
@@ -35,177 +35,177 @@ struct IP_BASE
};
-static const struct IP_BASE NBIF_BASE = { { { { 0x,
0x0014, 0x0D20, 0x00010400, 0 } },
+static const struct IP_BASE __maybe_unused NBIF_BASE = { { { { 0x,
0x0014, 0x0D20, 0x00010400, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE NBIO_BASE = { { { { 0x,
0x0014, 0x0D20, 0x00010400, 0 } },
+static const struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x,
0x0014, 0x0D20, 0x00010400, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DCE_BASE = { { { { 0x0012,
0x00C0, 0x34C0, 0, 0 } },
+static const struct IP_BASE __maybe_unused DCE_BASE= { { { { 0x0012,
0x00C0, 0x34C0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DCN_BASE = { { { { 0x0012,
0x00C0, 0x34C0, 0, 0 } },
+static const struct IP_BASE __maybe_unused DCN_BASE= { { { { 0x0012,
0x00C0, 0x34C0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP0_BASE = { { { { 0x00016000,
0, 0, 0, 0 } },
+static const struct IP_BASE __maybe_unused MP0_BASE= { { { { 0x00016000,
0, 0, 0, 0 } },
[PATCH 37/40] drm/amd/amdgpu/smu_v11_0_i2c: Provide descriptions for 'control' and 'data' params
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c:225: warning: Function parameter or member 'control' not described in 'smu_v11_0_i2c_transmit' drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c:325: warning: Function parameter or member 'control' not described in 'smu_v11_0_i2c_receive' drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c:325: warning: Function parameter or member 'data' not described in 'smu_v11_0_i2c_receive' Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c index 7fb240c4990ca..5c7d769aee3fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c @@ -212,6 +212,7 @@ static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control) /** * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device. * + * @control: I2C adapter reference * @address: The I2C address of the slave device. * @data: The data to transmit over the bus. * @numbytes: The amount of data to transmit. @@ -313,7 +314,9 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control, /** * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device. * + * @control: I2C adapter reference * @address: The I2C address of the slave device. + * @data: Placeholder to store received data. * @numbytes: The amount of data to transmit. * @i2c_flag: Flags for transmission * -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: add cursor pitch check
Hmm. I've written new patches to check the remaining plane state [1],
but I'm confused. On my RX 580 machine, it turns out the pitch used by
my cursor is not 128 or 256, it's 512. Here's a drm_info excerpt:
├───DRM_CAP_CURSOR_WIDTH = 128
├───DRM_CAP_CURSOR_HEIGHT = 128
[…]
├───Plane 6
│ ├───Object ID: 52
│ ├───CRTCs: {0}
│ ├───Formats:
│ │ └───ARGB (0x34325241)
│ └───Properties
│ ├───"type" (immutable): enum {Overlay, Primary, Cursor} = Cursor
│ ├───"FB_ID" (atomic): object framebuffer = 106
│ │ ├───Object ID: 106
│ │ ├───Size: 128x128
│ │ ├───Format: ARGB (0x34325241)
│ │ └───Planes:
│ │ └───Plane 0: offset = 0, pitch = 512
│ ├───"IN_FENCE_FD" (atomic): srange [-1, INT32_MAX] = -1
│ ├───"CRTC_ID" (atomic): object CRTC = 54
│ ├───"CRTC_X" (atomic): srange [INT32_MIN, INT32_MAX] = 792
│ ├───"CRTC_Y" (atomic): srange [INT32_MIN, INT32_MAX] = 1302
│ ├───"CRTC_W" (atomic): range [0, INT32_MAX] = 128
│ ├───"CRTC_H" (atomic): range [0, INT32_MAX] = 128
│ ├───"SRC_X" (atomic): range [0, UINT32_MAX] = 0
│ ├───"SRC_Y" (atomic): range [0, UINT32_MAX] = 0
│ ├───"SRC_W" (atomic): range [0, UINT32_MAX] = 128
│ ├───"SRC_H" (atomic): range [0, UINT32_MAX] = 128
However the cursor is displayed just fine. It seems like amdgpu sets
dc_cursor_attributes.pitch to the FB width in handle_cursor_update:
attributes.pitch = attributes.width;
Is this expected? Did I get the cursor pitch constraint wrong? Should
we check for alignment instead?
Thanks,
Simon
[1]: https://github.com/emersion/linux/commits/amdgpu-cursor-pitch
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