[PATCH] drm/amdgpu: Fix a potential sdma invalid access

[Qu Huang]

Before dma_resv_lock(bo->base.resv, NULL) in amdgpu_bo_release_notify(),
the bo->base.resv lock may be held by ttm_mem_evict_first(),
and the VRAM mem will be evicted, mem region was replaced
by Gtt mem region. amdgpu_bo_release_notify() will then
hold the bo->base.resv lock, and SDMA will get an invalid
address in amdgpu_fill_buffer(), resulting in a VMFAULT
or memory corruption.

To avoid it, we have to hold bo->base.resv lock first, and
check whether the mem.mem_type is TTM_PL_VRAM.

Signed-off-by: Qu Huang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 4b29b82..8018574 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1300,12 +1300,16 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object 
*bo)
if (bo->base.resv == >base._resv)
amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);

-   if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node ||
-   !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
+   if (!(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
return;

dma_resv_lock(bo->base.resv, NULL);

+   if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node) {
+   dma_resv_unlock(bo->base.resv);
+   return;
+   }
+
r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, );
if (!WARN_ON(r)) {
amdgpu_bo_fence(abo, fence, false);
--
1.8.3.1

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Boot error on Gfx 9 with latest amd-staging-drm-next

[Bhardwaj, Rajneesh]

Hi Everyone,

On latest amd-staging-drm-next, the below patch is causing errors at 
boot time and should be reverted.


Error on boot on Vega 10.

[ +0.007084] loop1: detected capacity change from 327992 to 0
[ +0.244709] amdgpu :63:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] 
*ERROR* ring kiq_2.1.0 test failed (-110)

[ +0.000220] [drm:amdgpu_gfx_enable_kcq [amdgpu]] *ERROR* KCQ enable failed
[ +0.000164] [drm:amdgpu_device_init [amdgpu]] *ERROR* hw_init of IP 
block  failed -110

[ +0.000143] amdgpu :63:00.0: amdgpu: amdgpu_device_ip_init failed
[ +0.30] amdgpu :63:00.0: amdgpu: Fatal error during GPU init
[ +0.000237] amdgpu: probe of :63:00.0 failed with error -110


Culprit:

commit 08410e955066bb65c258ed1409f3fcbaa0b83209
Author: Peng Ju Zhou 
Date: Mon Mar 22 15:18:01 2021 +0800


drm/amdgpu: indirect register access for nv12 sriov


1. expand rlcg interface for gc & mmhub indirect access
2. add rlcg interface for no kiq


Signed-off-by: Peng Ju Zhou 
Reviewed-by: Emily.Deng 


Please revert this commit.


Thanks

Rajneesh


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Re: [PATCH 19/34] drm/amdkfd: HMM migrate vram to ram

[kernel test robot]

Hi Felix,

I love your patch! Perhaps something to improve:

[auto build test WARNING on next-20210331]
[cannot apply to drm-intel/for-linux-next drm-tip/drm-tip 
drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master 
drm/drm-next v5.12-rc5 v5.12-rc4 v5.12-rc3 v5.12-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
base:7a43c78d0573e00456b033e2b9a895b89464
config: x86_64-randconfig-a011-20210401 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# 
https://github.com/0day-ci/linux/commit/31c45957000fde18a71d7e93c0d6be26bc45a239
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
git checkout 31c45957000fde18a71d7e93c0d6be26bc45a239
# save the attached .config to linux build tree
make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c:194:1: warning: no 
previous prototype for 'svm_migrate_copy_done' [-Wmissing-prototypes]
 194 | svm_migrate_copy_done(struct amdgpu_device *adev, struct dma_fence 
*mfence)
 | ^
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c:283:6: warning: no 
>> previous prototype for 'svm_migrate_put_sys_page' [-Wmissing-prototypes]
 283 | void svm_migrate_put_sys_page(unsigned long addr)
 |  ^~~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c: In function 
'svm_migrate_fini':
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c:875:2: error: implicit 
declaration of function 'memunmap_pages'; did you mean 'memcmp_pages'? 
[-Werror=implicit-function-declaration]
 875 |  memunmap_pages(>kfd.dev->pgmap);
 |  ^~
 |  memcmp_pages
   cc1: some warnings being treated as errors

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for DEVICE_PRIVATE
   Depends on ZONE_DEVICE
   Selected by
   - HSA_AMD && HAS_IOMEM && DRM_AMDGPU && (X86_64 || ARM64 || PPC64)


vim +/svm_migrate_put_sys_page +283 
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c

   282  
 > 283  void svm_migrate_put_sys_page(unsigned long addr)
   284  {
   285  struct page *page;
   286  
   287  page = pfn_to_page(addr >> PAGE_SHIFT);
   288  unlock_page(page);
   289  put_page(page);
   290  }
   291  

---
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https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org


.config.gz
Description: application/gzip
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[pull] amdgpu, radeon, ttm, sched drm-next-5.13

[Alex Deucher]

Hi Dave, Daniel,

New stuff for 5.13.  There are two small patches for ttm and scheduler
that were dependencies for amdgpu changes.

The following changes since commit 2cbcb78c9ee5520c8d836c7ff57d1b60ebe8e9b7:

  Merge tag 'amd-drm-next-5.13-2021-03-23' of 
https://gitlab.freedesktop.org/agd5f/linux into drm-next (2021-03-26 15:53:21 
+0100)

are available in the Git repository at:

  https://gitlab.freedesktop.org/agd5f/linux.git 
tags/amd-drm-next-5.13-2021-04-01

for you to fetch changes up to ef95d2a98d642a537190d73c45ae3c308afee890:

  drm/amdgpu/display: fix warning on 32 bit in dmub (2021-04-01 17:32:32 -0400)


amd-drm-next-5.13-2021-04-01:

amdgpu:
- Re-enable GPU reset on VanGogh
- Enable DPM flags for SMART_SUSPEND and MAY_SKIP_RESUME
- Disentangle HG from vga_switcheroo
- S0ix fixes
- W=1 fixes
- Resource iterator fixes
- DMCUB updates
- UBSAN fixes
- More PM API cleanup
- Aldebaran updates
- Modifier fixes
- Enable VCN load balancing with asymmetric engines
- Rework BO structs
- Aldebaran reset support
- Initial LTTPR display work
- Display MALL fixes
- Fall back to YCbCr420 when YCbCr444 fails
- SR-IOV fixes
- Misc cleanups and fixes

radeon:
- Typo fixes

ttm:
- Handle cached requests (required for Aldebaran)

scheduler:
- Fix runqueue selection when changing priorities (required to fix VCN
  load balancing)


Alex Deucher (20):
  drm/amdgpu/display/dm: add missing parameter documentation
  drm/amdgpu: Add additional Sienna Cichlid PCI ID
  drm/amdgpu: add a dev_pm_ops prepare callback (v2)
  drm/amdgpu: enable DPM_FLAG_MAY_SKIP_RESUME and DPM_FLAG_SMART_SUSPEND 
flags (v2)
  drm/amdgpu: disentangle HG systems from vgaswitcheroo
  drm/amdgpu: rework S3/S4/S0ix state handling
  drm/amdgpu: don't evict vram on APUs for suspend to ram (v4)
  drm/amdgpu: clean up non-DC suspend/resume handling
  drm/amdgpu: move s0ix check into amdgpu_device_ip_suspend_phase2 (v3)
  drm/amdgpu: re-enable suspend phase 2 for S0ix
  drm/amdgpu/swsmu: skip gfx cgpg on s0ix suspend
  drm/amdgpu: update comments about s0ix suspend/resume
  drm/amdgpu: drop S0ix checks around CG/PG in suspend
  drm/amdgpu: skip kfd suspend/resume for S0ix
  drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x
  drm/amdgpu/display: fix memory leak for dimgrey cavefish
  drm/amdgpu/pm: mark pcie link/speed arrays as const
  drm/amdgpu/pm: bail on sysfs/debugfs queries during platform suspend
  drm/amdgpu/vangogh: don't check for dpm in is_dpm_running when in suspend
  drm/amdgpu/display: fix warning on 32 bit in dmub

Alex Sierra (2):
  drm/amdgpu: replace per_device_list by array
  drm/amdgpu: ih reroute for newer asics than vega20

Alvin Lee (1):
  drm/amd/display: Change input parameter for set_drr

Anson Jacob (2):
  drm/amd/display: Fix UBSAN: shift-out-of-bounds warning
  drm/amd/display: Removing unused code from dmub_cmd.h

Anthony Koo (2):
  drm/amd/display: [FW Promotion] Release 0.0.57
  drm/amd/display: [FW Promotion] Release 0.0.58

Aric Cyr (2):
  drm/amd/display: 3.2.128
  drm/amd/display: 3.2.129

Arnd Bergmann (3):
  amdgpu: avoid incorrect %hu format string
  amdgpu: fix gcc -Wrestrict warning
  amdgpu: securedisplay: simplify i2c hexdump output

Bhaskar Chowdhury (6):
  drm/amdgpu: Fix a typo
  drm/amdgpu: Fix a typo
  drm/atomic: Couple of typo fixes
  drm/radeon/r600_cs: Few typo fixes
  drm/amd/amdgpu/gfx_v7_0: Trivial typo fixes
  drm/amd: Fix a typo in two different sentences

Bindu Ramamurthy (1):
  drm/amd/display: Allow idle optimization based on vblank.

Chengming Gui (1):
  drm/amd/amdgpu: set MP1 state to UNLOAD before reload its FW for 
vega20/ALDEBARAN

Chris Park (1):
  drm/amd/display: Disable MALL when SMU not present

Christian König (5):
  drm/amdgpu: remove irq_src->data handling
  drm/amdgpu: add the sched_score to amdgpu_ring_init
  drm/amdgpu: share scheduler score on VCN3 instances
  drm/sched: select new rq even if there is only one v3
  drm/amdgpu: load balance VCN3 decode as well v8

Daniel Gomez (2):
  drm/amdgpu/ttm: Fix memory leak userptr pages
  drm/radeon/ttm: Fix memory leak userptr pages

David Galiffi (1):
  drm/amd/display: Fixed Clock Recovery Sequence

Dennis Li (1):
  drm/amdgpu: add codes to capture invalid hardware access when recovery

Diego Viola (1):
  drm/amd/display: fix typo: liason -> liaison

Dmytro Laktyushkin (3):
  drm/amd/display: hide VGH asic specific structs
  drm/amd/display: revert max lb lines change
  drm/amd/display: revert max lb use by default for n10

Eryk Brol (1):
  drm/amd/display: Fix MST topology debugfs

Evan Quan (9):
  drm/amd/pm: fix Navi1x runtime resume failure V2
  drm/amd/pm: make DAL 

Re: [PATCH] amd: display: modules: Remove repeated struct declaration

[Alex Deucher]

Applied.  Thanks!

Alex

On Thu, Apr 1, 2021 at 11:26 AM Wan Jiabing  wrote:
>
> struct mod_hdcp is declared twice. One is declared at 33rd line.
> The blew one is not needed. Remove the duplicate.
>
> Signed-off-by: Wan Jiabing 
> ---
>  drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h 
> b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
> index d223ed3be5d3..03fe49c5b7d0 100644
> --- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
> +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
> @@ -255,8 +255,6 @@ struct mod_hdcp_config {
> uint8_t index;
>  };
>
> -struct mod_hdcp;
> -
>  /* dm allocates memory of mod_hdcp per dc_link on dm init based on memory 
> size*/
>  size_t mod_hdcp_get_memory_size(void);
>
> --
> 2.25.1
>
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Re: [PATCH] drm/ttm: add __user annotation in radeon_ttm_vram_read

[Alex Deucher]

Current code already contains the fix.

Alex


On Thu, Apr 1, 2021 at 9:09 AM Christian König
 wrote:
>
> Am 24.10.20 um 02:47 schrieb Rasmus Villemoes:
> > Keep sparse happy by preserving the __user annotation when casting.
> >
> > Reported-by: kernel test robot 
> > Signed-off-by: Rasmus Villemoes 
>
> Reviewed-by: Christian König 
>
> Going over old patches and stumbled over that once.
>
> Alex did you missed to pick it up?
>
> Regards,
> Christian.
>
> > ---
> >
> > kernel test robot has already started spamming me due to 9c5743dff. If
> > I don't fix those warnings I'll keep getting those emails for
> > months, so let me do the easy ones.
> >
> >
> >   drivers/gpu/drm/radeon/radeon_ttm.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
> > b/drivers/gpu/drm/radeon/radeon_ttm.c
> > index 36150b7f31a90aa1eece..ecfe88b0a35d8f317712 100644
> > --- a/drivers/gpu/drm/radeon/radeon_ttm.c
> > +++ b/drivers/gpu/drm/radeon/radeon_ttm.c
> > @@ -1005,7 +1005,7 @@ static ssize_t radeon_ttm_vram_read(struct file *f, 
> > char __user *buf,
> >   value = RREG32(RADEON_MM_DATA);
> >   spin_unlock_irqrestore(>mmio_idx_lock, flags);
> >
> > - r = put_user(value, (uint32_t *)buf);
> > + r = put_user(value, (uint32_t __user *)buf);
> >   if (r)
> >   return r;
> >
>
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Re: [PATCH] amd/amdgpu: code refactoring to clean code style a bit

[Alex Deucher]

This code has been dropped.

Alex

On Wed, Mar 31, 2021 at 9:36 AM Bernard Zhao  wrote:
>
> Fix checkpatch.pl warning:
> Too many leading tabs - consider code refactoring
> WARNING: Too many leading tabs - consider code refactoring
> +   for (j = 0; j < 
> profile->ucLeakageBinNum; j++) {
>
> WARNING: Too many leading tabs - consider code refactoring
> +   if (vbios_voltage_id 
> <= leakage_bin[j]) {
>
> WARNING: Too many leading tabs - consider code refactoring
> +   for (j = 0; j < 
> profile->ucLeakageBinNum; j++) {
>
> WARNING: Too many leading tabs - consider code refactoring
> +   if (vbios_voltage_id 
> <= leakage_bin[j]) {
>
> Signed-off-by: Bernard Zhao 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 84 
>  1 file changed, 35 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> index 86add0f4ea4d..9968ff8ddc9c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> @@ -1283,65 +1283,51 @@ int 
> amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_devic
> profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
> (adev->mode_info.atom_context->bios + data_offset);
>
> -   switch (frev) {
> -   case 1:
> +   if ((frev != 2) || (crev != 1)) {
> +   DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
> return -EINVAL;
> -   case 2:
> -   switch (crev) {
> -   case 1:
> -   if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
> -   return -EINVAL;
> -   leakage_bin = (u16 *)
> -   (adev->mode_info.atom_context->bios + 
> data_offset +
> -
> le16_to_cpu(profile->usLeakageBinArrayOffset));
> -   vddc_id_buf = (u16 *)
> -   (adev->mode_info.atom_context->bios + 
> data_offset +
> -
> le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
> -   vddc_buf = (u16 *)
> -   (adev->mode_info.atom_context->bios + 
> data_offset +
> -
> le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
> -   vddci_id_buf = (u16 *)
> -   (adev->mode_info.atom_context->bios + 
> data_offset +
> -
> le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
> -   vddci_buf = (u16 *)
> -   (adev->mode_info.atom_context->bios + 
> data_offset +
> -
> le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
> -
> -   if (profile->ucElbVDDC_Num > 0) {
> -   for (i = 0; i < profile->ucElbVDDC_Num; i++) {
> -   if (vddc_id_buf[i] == 
> virtual_voltage_id) {
> -   for (j = 0; j < 
> profile->ucLeakageBinNum; j++) {
> -   if (vbios_voltage_id 
> <= leakage_bin[j]) {
> -   *vddc = 
> vddc_buf[j * profile->ucElbVDDC_Num + i];
> -   break;
> -   }
> -   }
> +   }
> +
> +   if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
> +   return -EINVAL;
> +
> +   leakage_bin = (u16 *)(adev->mode_info.atom_context->bios + 
> data_offset +
> +le16_to_cpu(profile->usLeakageBinArrayOffset));
> +   vddc_id_buf = (u16 *)(adev->mode_info.atom_context->bios + 
> data_offset +
> +le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
> +   vddc_buf = (u16 *)(adev->mode_info.atom_context->bios + data_offset +
> +le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
> +   vddci_id_buf = (u16 *)(adev->mode_info.atom_context->bios + 
> data_offset +
> +le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
> +   vddci_buf = (u16 *)(adev->mode_info.atom_context->bios + data_offset +
> +le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
> +
> +   if (profile->ucElbVDDC_Num > 0) {
> +   for (i = 0; i < profile->ucElbVDDC_Num; i++) {
> +   if (vddc_id_buf[i] == virtual_voltage_id) {
> +   for (j = 0; j < profile->ucLeakageBinNum; 
> j++) {
> +   if (vbios_voltage_id <= 
> leakage_bin[j]) {
> +   

Re: [PATCH] drm/amd: cleanup coding style a bit

[Alex Deucher]

Applied.  Thanks!

Alex

On Wed, Mar 31, 2021 at 9:36 AM Bernard Zhao  wrote:
>
> Fix patch check warning:
> WARNING: suspect code indent for conditional statements (8, 17)
> +   if (obj && obj->use < 0) {
> +DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", 
> obj->head.name);
>
> WARNING: braces {} are not necessary for single statement blocks
> +   if (obj && obj->use < 0) {
> +DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", 
> obj->head.name);
> +   }
>
> Signed-off-by: Bernard Zhao 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 +++
>  1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index 1fb2a91ad30a..43d17b72c265 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -449,11 +449,10 @@ static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
>
>  static inline void put_obj(struct ras_manager *obj)
>  {
> -   if (obj && --obj->use == 0)
> +   if (obj && (--obj->use == 0))
> list_del(>node);
> -   if (obj && obj->use < 0) {
> -DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", 
> obj->head.name);
> -   }
> +   if (obj && (obj->use < 0))
> +   DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", 
> obj->head.name);
>  }
>
>  /* make one obj and return it. */
> --
> 2.31.0
>
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Re: [PATCH] drm/amd: use kmalloc_array over kmalloc with multiply

[Alex Deucher]

Applied.  Thanks!

On Wed, Mar 31, 2021 at 9:36 AM Bernard Zhao  wrote:
>
> Fix patch check warning:
> WARNING: Prefer kmalloc_array over kmalloc with multiply
> +   buf = kmalloc(MAX_KFIFO_SIZE * sizeof(*buf), GFP_KERNEL);
>
> Signed-off-by: Bernard Zhao 
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
> index 17d1736367ea..246522423559 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
> @@ -81,7 +81,7 @@ static ssize_t kfd_smi_ev_read(struct file *filep, char 
> __user *user,
> struct kfd_smi_client *client = filep->private_data;
> unsigned char *buf;
>
> -   buf = kmalloc(MAX_KFIFO_SIZE * sizeof(*buf), GFP_KERNEL);
> +   buf = kmalloc_array(MAX_KFIFO_SIZE, sizeof(*buf), GFP_KERNEL);
> if (!buf)
> return -ENOMEM;
>
> --
> 2.31.0
>
> ___
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Re: [PATCH] drm/amdgpu/display: fix warning on 32 bit in dmub

[Harry Wentland]

On 2021-04-01 10:22 a.m., Alex Deucher wrote:

Use uintptr_t rather than uint64_t.

Signed-off-by: Alex Deucher 
Cc: Dave Airlie 
Cc: Harry Wentland 


Reviewed-by: Harry Wentland 

Harry


---
  drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 743d3b7f6f24..e36e89157703 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -510,7 +510,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
  
  	dmub_memset(_rb_params, 0, sizeof(outbox0_rb_params));

outbox0_rb_params.ctx = dmub;
-   outbox0_rb_params.base_address = (void 
*)((uint64_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
+   outbox0_rb_params.base_address = (void 
*)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
outbox0_rb_params.capacity = tracebuff_fb->size - 
dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
dmub_rb_init(>outbox0_rb, _rb_params);
  



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[PATCH 4/4] Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"

[Oak Zeng]

This reverts commit 34a33d4683cba7ba63c894132efb1998c0217631.
34a33d4683cba7ba63c894132efb1998c0217631 was a driver workaround
when PSP firmware was not ready. Now the PSP fw is ready so we
revert this driver workaround.

Signed-off-by: Oak Zeng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h  |  9 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c  | 10 --
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 21 ++---
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c  | 10 --
 4 files changed, 10 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index bc374bc..59bbe59 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -209,15 +209,6 @@ struct amdgpu_gmc {
 */
u64 fb_start;
u64 fb_end;
-   /* In the case of use GART table for vmid0 FB access, [fb_start, fb_end]
-* will be squeezed to GART aperture. But we have a PSP FW issue to fix
-* for now. To temporarily workaround the PSP FW issue, added below two
-* variables to remember the original fb_start/end to re-enable FB
-* aperture to workaround the PSP FW issue. Will delete it after we
-* get a proper PSP FW fix.
-*/
-   u64 fb_start_original;
-   u64 fb_end_original;
unsignedvram_width;
u64 real_vram_size;
int vram_mtrr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 123ab31..5298698 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -414,16 +414,6 @@ static int psp_tmr_init(struct psp_context *psp)
  AMDGPU_GEM_DOMAIN_VRAM,
  >tmr_bo, >tmr_mc_addr, pptr);
 
-   /* workaround the tmr_mc_addr:
-* PSP requires an address in FB aperture. Right now driver produce
-* tmr_mc_addr in the GART aperture. Convert it back to FB aperture
-* for PSP. Will revert it after we get a fix from PSP FW.
-*/
-   if (psp->adev->asic_type == CHIP_ALDEBARAN) {
-   psp->tmr_mc_addr -= psp->adev->gmc.fb_start;
-   psp->tmr_mc_addr += psp->adev->gmc.fb_start_original;
-   }
-
return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 9b78891..561b32e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -140,21 +140,12 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
 * FB aperture and AGP aperture. Disable them.
 */
if (adev->gmc.pdb0_bo) {
-   if (adev->asic_type == CHIP_ALDEBARAN) {
-   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 
adev->gmc.fb_end_original >> 24);
-   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 
adev->gmc.fb_start_original >> 24);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFF);
-   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 
adev->gmc.fb_start_original >> 18);
-   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 
adev->gmc.fb_end_original >> 18);
-   } else {
-   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
-   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 
0x00FF);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFF);
-   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 
0x3FFF);
-   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 
0);
-   }
+   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
+   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FF);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFF);
+   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 
0x3FFF);
+   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
index d341d17..71914f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
@@ -47,8 +47,6 @@ static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device 
*adev)
 
adev->gmc.fb_start = base;
adev->gmc.fb_end = top;
-   adev->gmc.fb_start_original = base;
-   adev->gmc.fb_end_original = top;
 
return base;
 }
@@ -126,10 +124,10 @@ 

Re: [PATCH 14/34] drm/amdkfd: register HMM device private zone

[kernel test robot]

Hi Felix,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20210331]
[cannot apply to drm-intel/for-linux-next drm-tip/drm-tip 
drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master 
drm/drm-next v5.12-rc5 v5.12-rc4 v5.12-rc3 v5.12-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
base:7a43c78d0573e00456b033e2b9a895b89464
config: x86_64-randconfig-a011-20210401 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# 
https://github.com/0day-ci/linux/commit/1b956676a808da2199942fd64b49fd1cec2c12be
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
git checkout 1b956676a808da2199942fd64b49fd1cec2c12be
# save the attached .config to linux build tree
make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c: In function 
'svm_migrate_fini':
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c:102:2: error: implicit 
>> declaration of function 'memunmap_pages'; did you mean 'memcmp_pages'? 
>> [-Werror=implicit-function-declaration]
 102 |  memunmap_pages(>kfd.dev->pgmap);
 |  ^~
 |  memcmp_pages
   cc1: some warnings being treated as errors

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for DEVICE_PRIVATE
   Depends on ZONE_DEVICE
   Selected by
   - HSA_AMD && HAS_IOMEM && DRM_AMDGPU && (X86_64 || ARM64 || PPC64)


vim +102 drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.c

99  
   100  void svm_migrate_fini(struct amdgpu_device *adev)
   101  {
 > 102  memunmap_pages(>kfd.dev->pgmap);

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org


.config.gz
Description: application/gzip
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[PATCH 2/4] drm/amdgpu: Calling address translation functions to simplify codes

[Oak Zeng]

Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa
to simplify codes. No logic change.

Signed-off-by: Oak Zeng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c   | 4 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c  | 3 +--
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 3 +--
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 3 +--
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 3 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c   | 3 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 3 +--
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 3 +--
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c  | 3 +--
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c  | 3 +--
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c  | 3 +--
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c  | 3 +--
 12 files changed, 12 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 4c5c198..4f10c45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -205,7 +205,6 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
struct drm_gem_object *gobj = NULL;
struct amdgpu_bo *abo = NULL;
int ret;
-   unsigned long tmp;
 
memset(_cmd, 0, sizeof(mode_cmd));
mode_cmd.width = sizes->surface_width;
@@ -246,8 +245,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
 
info->fbops = _ops;
 
-   tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
-   info->fix.smem_start = adev->gmc.aper_base + tmp;
+   info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo);
info->fix.smem_len = amdgpu_bo_size(abo);
info->screen_base = amdgpu_bo_kptr(abo);
info->screen_size = amdgpu_bo_size(abo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index ca16649..238082f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -641,8 +641,7 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
u64 vram_addr = adev->vm_manager.vram_base_offset -
adev->gmc.xgmi.physical_node_id * 
adev->gmc.xgmi.node_segment_size;
u64 vram_end = vram_addr + vram_size;
-   u64 gart_ptb_gpu_pa = amdgpu_bo_gpu_offset(adev->gart.bo) +
-   adev->vm_manager.vram_base_offset - adev->gmc.vram_start;
+   u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);
 
flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
flags |= AMDGPU_PTE_WRITEABLE;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 5bb9856..9b78891 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -120,8 +120,7 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
/* Set default page address. */
-   value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
-   adev->vm_manager.vram_base_offset;
+   value = amdgpu_gmc_vram_pa(adev, adev->vram_scratch.robj);
WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 (u32)(value >> 12));
WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index 2aecc6a..ab41c8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -165,8 +165,7 @@ static void gfxhub_v2_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
/* Set default page address. */
-   value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
-   + adev->vm_manager.vram_base_offset;
+   value = amdgpu_gmc_vram_pa(adev, adev->vram_scratch.robj);
WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 (u32)(value >> 12));
WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 410fd3a..4badd73 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -164,8 +164,7 @@ static void gfxhub_v2_1_init_system_aperture_regs(struct 
amdgpu_device *adev)
 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
/* Set default page address. */
-   value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
-   + adev->vm_manager.vram_base_offset;
+   value = amdgpu_gmc_vram_pa(adev, adev->vram_scratch.robj);
WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 (u32)(value >> 12));
   

[PATCH 1/4] drm/amdgpu: Introduce functions for vram physical addr calculation

[Oak Zeng]

Add one function to calculate BO's GPU physical address.
And another function to calculate BO's CPU physical address.

v2: Use functions vs macros (Christian)
Use more proper function names (Christian)

Signed-off-by: Oak Zeng 
Suggested-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 34 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  3 +++
 2 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index b9d68fd..ca16649 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -665,3 +665,37 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
/* Requires gart_ptb_gpu_pa to be 4K aligned */
amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, 
flags);
 }
+
+/**
+ * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC
+ * address
+ *
+ * @adev: amdgpu_device pointer
+ * @mc_addr: MC address of buffer
+ */
+uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr)
+{
+   return mc_addr - adev->gmc.vram_start + 
adev->vm_manager.vram_base_offset;
+}
+/**
+ * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from
+ * GPU's view
+ *
+ * @adev: amdgpu_device pointer
+ * @bo: amdgpu buffer object
+ */
+uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
+{
+   return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo));
+}
+/**
+ * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address
+ * from CPU's view
+ *
+ * @adev: amdgpu_device pointer
+ * @bo: amdgpu buffer object
+ */
+uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo 
*bo)
+{
+   return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + 
adev->gmc.aper_base;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 7e248a4..bc374bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -332,4 +332,7 @@ amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, 
int hub_type,
 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev);
 
 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
+uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
+uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
+uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo 
*bo);
 #endif
-- 
2.7.4

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[PATCH 4/4] Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"

[Oak Zeng]

This reverts commit 34a33d4683cba7ba63c894132efb1998c0217631.

Signed-off-by: Oak Zeng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h  |  9 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c  | 10 --
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 21 ++---
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c  | 10 --
 4 files changed, 10 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index bc374bc..59bbe59 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -209,15 +209,6 @@ struct amdgpu_gmc {
 */
u64 fb_start;
u64 fb_end;
-   /* In the case of use GART table for vmid0 FB access, [fb_start, fb_end]
-* will be squeezed to GART aperture. But we have a PSP FW issue to fix
-* for now. To temporarily workaround the PSP FW issue, added below two
-* variables to remember the original fb_start/end to re-enable FB
-* aperture to workaround the PSP FW issue. Will delete it after we
-* get a proper PSP FW fix.
-*/
-   u64 fb_start_original;
-   u64 fb_end_original;
unsignedvram_width;
u64 real_vram_size;
int vram_mtrr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 123ab31..5298698 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -414,16 +414,6 @@ static int psp_tmr_init(struct psp_context *psp)
  AMDGPU_GEM_DOMAIN_VRAM,
  >tmr_bo, >tmr_mc_addr, pptr);
 
-   /* workaround the tmr_mc_addr:
-* PSP requires an address in FB aperture. Right now driver produce
-* tmr_mc_addr in the GART aperture. Convert it back to FB aperture
-* for PSP. Will revert it after we get a fix from PSP FW.
-*/
-   if (psp->adev->asic_type == CHIP_ALDEBARAN) {
-   psp->tmr_mc_addr -= psp->adev->gmc.fb_start;
-   psp->tmr_mc_addr += psp->adev->gmc.fb_start_original;
-   }
-
return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 9b78891..561b32e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -140,21 +140,12 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
 * FB aperture and AGP aperture. Disable them.
 */
if (adev->gmc.pdb0_bo) {
-   if (adev->asic_type == CHIP_ALDEBARAN) {
-   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 
adev->gmc.fb_end_original >> 24);
-   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 
adev->gmc.fb_start_original >> 24);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFF);
-   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 
adev->gmc.fb_start_original >> 18);
-   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 
adev->gmc.fb_end_original >> 18);
-   } else {
-   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
-   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 
0x00FF);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
-   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFF);
-   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 
0x3FFF);
-   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 
0);
-   }
+   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
+   WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FF);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
+   WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFF);
+   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 
0x3FFF);
+   WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
index d341d17..71914f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
@@ -47,8 +47,6 @@ static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device 
*adev)
 
adev->gmc.fb_start = base;
adev->gmc.fb_end = top;
-   adev->gmc.fb_start_original = base;
-   adev->gmc.fb_end_original = top;
 
return base;
 }
@@ -126,10 +124,10 @@ static void mmhub_v1_7_init_system_aperture_regs(struct 
amdgpu_device *adev)
if (adev->gmc.pdb0_bo) {
WREG32_SOC15(MMHUB, 0, 

[PATCH 3/4] drm/amdgpu: Introduce new SETUP_TMR interface

[Oak Zeng]

This new interface passes both virtual and physical address
to PSP. It is backword compatible with old interface.

v2: use a function to simply tmr physical address calc (Lijo)

Signed-off-by: Oak Zeng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 12 +---
 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 11 ++-
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 9e769cf..123ab31 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -328,8 +328,12 @@ psp_cmd_submit_buf(struct psp_context *psp,
 
 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 struct psp_gfx_cmd_resp *cmd,
-uint64_t tmr_mc, uint32_t size)
+uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 {
+   struct amdgpu_device *adev = psp->adev;
+   uint32_t size = amdgpu_bo_size(tmr_bo);
+   uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
+
if (amdgpu_sriov_vf(psp->adev))
cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
else
@@ -337,6 +341,9 @@ static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
cmd->cmd.cmd_setup_tmr.buf_size = size;
+   cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
+   cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
+   cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 }
 
 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
@@ -466,8 +473,7 @@ static int psp_tmr_load(struct psp_context *psp)
if (!cmd)
return -ENOMEM;
 
-   psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
-amdgpu_bo_size(psp->tmr_bo));
+   psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h 
b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index dd4d65f..96064c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -185,10 +185,19 @@ struct psp_gfx_cmd_setup_tmr
 uint32_tbuf_phy_addr_lo;   /* bits [31:0] of GPU Virtual 
address of TMR buffer (must be 4 KB aligned) */
 uint32_tbuf_phy_addr_hi;   /* bits [63:32] of GPU Virtual 
address of TMR buffer */
 uint32_tbuf_size;  /* buffer size in bytes (must be 
multiple of 4 KB) */
+union {
+   struct {
+   uint32_tsriov_enabled:1; /* whether the device runs 
under SR-IOV*/
+   uint32_tvirt_phy_addr:1; /* driver passes both virtual 
and physical address to PSP*/
+   uint32_treserved:30;
+   } bitfield;
+   uint32_ttmr_flags;
+};
+uint32_tsystem_phy_addr_lo;/* bits [31:0] of system 
physical address of TMR buffer (must be 4 KB aligned) */
+uint32_tsystem_phy_addr_hi;/* bits [63:32] of system 
physical address of TMR buffer */
 
 };
 
-
 /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
 enum psp_gfx_fw_type {
GFX_FW_TYPE_NONE= 0,/* */
-- 
2.7.4

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Re: [PATCH] drm/amdgpu/display: guard ttu_regs with CONFIG_DRM_AMD_DC_DCN

[Harry Wentland]

On 2021-03-30 10:28 p.m., Alex Deucher wrote:

Missing check for CONFIG_DRM_AMD_DC_DCN.

Fixes: 752106f5c5cd ("drm/amd/display: Set max TTU on DPG enable")
Signed-off-by: Alex Deucher 
Cc: Wesley Chalmers 
Cc: Stephen Rothwell 


Reviewed-by: Harry Wentland 

Harry


---
  drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d9ab134a178f..a270879cbaba 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2599,6 +2599,7 @@ static void commit_planes_for_stream(struct dc *dc,
}
}
  
+#ifdef CONFIG_DRM_AMD_DC_DCN

if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
struct pipe_ctx *mpcc_pipe;
struct pipe_ctx *odm_pipe;
@@ -2607,7 +2608,7 @@ static void commit_planes_for_stream(struct dc *dc,
for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = 
odm_pipe->next_odm_pipe)
odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
}
-
+#endif
  
  	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)

if 
(top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {



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RE: [PATCH] drm/amdkfd: Avoid null pointer in SMI event

[Joshi, Mukul]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Mukul Joshi 

Regards,
Mukul

-Original Message-
From: Lin, Amber  
Sent: Tuesday, March 30, 2021 5:03 PM
To: amd-gfx@lists.freedesktop.org
Cc: Joshi, Mukul ; Lin, Amber 
Subject: [PATCH] drm/amdkfd: Avoid null pointer in SMI event

Power Management IP is initialized/enabled before KFD init. When a thermal 
throttling happens before kfd_smi_init is done, calling the KFD SMI update 
function causes a stack dump by referring a NULL pointer ( smi_clients list). 
Check if kfd_init is completed before calling the function.

Signed-off-by: Amber Lin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 72c893fff61a..3cd46d7190b3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -1297,7 +1297,7 @@ void kfd_dec_compute_active(struct kfd_dev *kfd)
 
 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t 
throttle_bitmask)  {
-   if (kfd)
+   if (kfd && kfd->init_complete)
kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 
 }
 
--
2.17.1
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Re: [amdgpu] Compute kernels still run when the host process exit?

[Alex Deucher]

On Thu, Apr 1, 2021 at 10:08 AM Smith John  wrote:
>
> Hi, when I killed an OpenCL host process, the kernels it launched were not 
> terminated, and still run.
>
> My OpenCL runtime is AMDGPU-PRO 20.20. OS Ubuntu 18.04.5 with  Linux Kernel 
> 5.4.53
>
> I was wondering if it was a bug or the driver did not implement this 
> "watchdog" mechanism.

In general, once you issue work on the GPU it has to run to
completion.  It is not stopped if the application that issued it goes
away.

Alex
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Re: [PATCH] drm/amdgpu/display: guard ttu_regs with CONFIG_DRM_AMD_DC_DCN

[Alex Deucher]

Ping?

On Tue, Mar 30, 2021 at 10:28 PM Alex Deucher  wrote:
>
> Missing check for CONFIG_DRM_AMD_DC_DCN.
>
> Fixes: 752106f5c5cd ("drm/amd/display: Set max TTU on DPG enable")
> Signed-off-by: Alex Deucher 
> Cc: Wesley Chalmers 
> Cc: Stephen Rothwell 
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index d9ab134a178f..a270879cbaba 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -2599,6 +2599,7 @@ static void commit_planes_for_stream(struct dc *dc,
> }
> }
>
> +#ifdef CONFIG_DRM_AMD_DC_DCN
> if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
> struct pipe_ctx *mpcc_pipe;
> struct pipe_ctx *odm_pipe;
> @@ -2607,7 +2608,7 @@ static void commit_planes_for_stream(struct dc *dc,
> for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = 
> odm_pipe->next_odm_pipe)
> odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
> }
> -
> +#endif
>
> if ((update_type != UPDATE_TYPE_FAST) && 
> stream->update_flags.bits.dsc_changed)
> if 
> (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
> --
> 2.30.2
>
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RE: [PATCH 00/21] DC Patches April 5, 2021

[Wheeler, Daniel]

[AMD Public Use]

Hi all,

This week this patchset was tested on a HP Envy 360, with Ryzen 5 4500U, on the 
following display types (via usb-c to dp/dvi/hdmi/vga):
4k 60z, 1440p 144hz, 1680*1050 60hz, internal eDP 1080p 60hz

Tested on a Sapphire Pulse RX5700XT on the following display types (via DP):
4k60 60hz, 1440p 144hz, 1680x1050 60hz.

Also tested on a Reference AMD RX6800 on the following display types (via DP):
4k60 60hz, 1440p 144hz. 

Tested using a MST hub at 2x 4k 30hz on all systems.

Tested by Dan Wheeler 

Thank you,

Dan Wheeler
Technologist  |  AMD
SW Display
O +(1) 905-882-2600 ext. 74665
--
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook |  Twitter |  amd.com  


-Original Message-
From: amd-gfx  On Behalf Of Qingqing Zhuo
Sent: April 1, 2021 12:45 PM
To: amd-gfx@lists.freedesktop.org
Cc: Brol, Eryk ; Li, Sun peng (Leo) ; 
Wentland, Harry ; Zhuo, Qingqing 
; Siqueira, Rodrigo ; Li, 
Roman ; Jacob, Anson ; Pillai, Aurabindo 
; Lakha, Bhawanpreet ; R, 
Bindu 
Subject: [PATCH 00/21] DC Patches April 5, 2021

This DC patchset brings improvements in multiple areas.
In summary, we highlight:

* Firmware release 0.0.59
* Fixes on display experiences for 4k TVs, register mask missing, etc.
* Enhancements on MST, code cleaning and debug messages.

---

Anson Jacob (1):
  drm/amd/display: Fix 32 bit compilation of dmub_srv.c

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.59

Aric Cyr (1):
  drm/amd/display: 3.2.130

Aurabindo Pillai (1):
  drm/amd/display: Add debugfs entry for LTTPR register status

David (Dingchen) Zhang (1):
  drm/amd/display: use MST downstream AUX to dump DPRX CRCs

Harry VanZyllDeJong (1):
  drm/amd/display: Fixed corruption on 4K tvs

Harry Wentland (2):
  drm/amd/display: Add debug prints for SMU messages
  drm/amd/display: Add dc_debug flag to disable min fclk

Jake Wang (1):
  drm/amd/display: Added dc_edp_id_count to dc_context

Leo Li (1):
  drm/amd/display: Move vupdate keepout programming from DCN20 to DCN10

Mikita Lipski (4):
  drm/amd/display: Set initial value to a divider
  drm/amd/display: Directly retrain link from debugfs
  drm/amd/display: Add MST capability to trigger_hotplug interface
  drm/amd/display: Determine synchronization edge based on master's
vsync

Nicholas Kazlauskas (1):
  drm/amd/display: Cleanup DML DSC input bpc validation

Qingqing Zhuo (1):
  drm/amd/display: Add missing mask for DCN3

Robin Singh (1):
  drm/amd/display: add NULL check to avoid kernel crash in DC.

Victor Lu (1):
  drm/amd/display: Add function and debugfs to dump DCC_EN bit

Wayne Lin (1):
  drm/amd/display: Tweak the kernel doc for crc_rd_wrk

Wyatt Wood (2):
  drm/amd/display: Retry getting PSR state if command times out
  drm/amd/display: Add delay in dmub_srv_send_gpint_command

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  21 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   2 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c |   2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 207 +-
 .../display/dc/clk_mgr/dcn301/dcn301_smu.c|  29 ++-
 .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c|   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |   3 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  14 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h |   4 +-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  29 ++-  
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  16 ++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   4 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |  16 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   3 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   1 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  16 --
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   3 -
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   2 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h |   1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |   3 +-
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |   3 +-
 .../amd/display/dc/dcn301/dcn301_resource.c   |   2 +-
 .../drm/amd/display/dc/dml/display_mode_lib.c |   2 +-
 .../amd/display/dc/dml/display_mode_structs.h |   4 +-
 .../drm/amd/display/dc/dml/display_mode_vba.c |   8 +-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   2 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  17 +-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |   4 +-
 .../amd/display/modules/freesync/freesync.c   |   4 +-
 32 files changed, 364 insertions(+), 71 deletions(-)

--
2.17.1

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[PATCH 21/21] drm/amd/display: 3.2.130

[Qingqing Zhuo]

From: Aric Cyr 

DC version 3.2.130 brings improvements in multiple areas.
In summary, we highlight:

- Firmware release 0.0.59
- Fixes on display experiences for 4k TVs, register mask missing, etc.
- Enhancements on MST, code cleaning and debug messages.

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index cf5abcb74601..8108b82bac60 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@
 /* forward declaration */
 struct aux_payload;
 
-#define DC_VER "3.2.129"
+#define DC_VER "3.2.130"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 20/21] drm/amd/display: [FW Promotion] Release 0.0.59

[Qingqing Zhuo]

From: Anthony Koo 

[How]
add params to send FEC status to firmware

Signed-off-by: Anthony Koo 
Reviewed-by: Anthony Koo 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index c5776a55e2a5..44003836fafd 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x8bb402f5a
+#define DMUB_FW_VERSION_GIT_HASH 0x7f2db1846
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 58
+#define DMUB_FW_VERSION_REVISION 59
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -1229,6 +1229,19 @@ struct dmub_cmd_psr_copy_settings_data {
 * Length of each horizontal line in us.
 */
uint32_t line_time_in_us;
+   /**
+* FEC enable status in driver
+*/
+   uint8_t fec_enable_status;
+   /**
+* FEC re-enable delay when PSR exit.
+* unit is 100us, range form 0~255(0xFF).
+*/
+   uint8_t fec_enable_delay_in100us;
+   /**
+* Explicit padding to 4 byte boundary.
+*/
+   uint8_t pad3[2];
 };
 
 /**
-- 
2.17.1

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[PATCH 19/21] drm/amd/display: Cleanup DML DSC input bpc validation

[Qingqing Zhuo]

From: Nicholas Kazlauskas 

[Why & How]
Pipe input DSC bpc has a type mismatch with maximum DSC
input bpc - align the maximum with the pipe input type,
unsigned integer.

When checking the type we shoudl also check for an
implicit value of 0 and align with what the spreadsheet
does - default to max.

Rename output_bpc to dsc_input_bpc to reflect what the
field is actually used for.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 4 ++--
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 8 +++-
 4 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 8fb29f754e44..f65a6904d09c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2216,7 +2216,7 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].dout.output_bpp = 
res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
 
/* todo: default max for now, until there is logic reflecting 
this in dc*/
-   pipes[pipe_cnt].dout.output_bpc = 12;
+   pipes[pipe_cnt].dout.dsc_input_bpc = 12;
/*fill up the audio sample rate (unit in kHz)*/
get_audio_check(_ctx->pipe_ctx[i].stream->audio_info, 
_check);
pipes[pipe_cnt].dout.max_audio_sample_rate = 
aud_check.max_audiosample_rate / 1000;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index 098d6433f7f3..1f7b6ddf3020 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -226,7 +226,7 @@ void dml_log_pipe_params(
dml_print("DML PARAMS: PIPE [%d] DISPLAY OUTPUT PARAMS:\n", i);
dml_print("DML PARAMS: output_type= %d\n", 
dout->output_type);
dml_print("DML PARAMS: output_format  = %d\n", 
dout->output_format);
-   dml_print("DML PARAMS: output_bpc = %d\n", 
dout->output_bpc);
+   dml_print("DML PARAMS: dsc_input_bpc  = %d\n", 
dout->dsc_input_bpc);
dml_print("DML PARAMS: output_bpp = 
%3.4f\n", dout->output_bpp);
dml_print("DML PARAMS: dp_lanes   = %d\n", 
dout->dp_lanes);
dml_print("DML PARAMS: dsc_enable = %d\n", 
dout->dsc_enable);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 0c5128187e08..2ece3690bfa3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -164,7 +164,7 @@ struct _vcs_dpi_ip_params_st {
double writeback_max_vscl_ratio;
double writeback_min_hscl_ratio;
double writeback_min_vscl_ratio;
-   double maximum_dsc_bits_per_component;
+   unsigned int maximum_dsc_bits_per_component;
unsigned int writeback_max_hscl_taps;
unsigned int writeback_max_vscl_taps;
unsigned int writeback_line_buffer_luma_buffer_size;
@@ -292,10 +292,10 @@ struct writeback_st {
 struct _vcs_dpi_display_output_params_st {
int dp_lanes;
double output_bpp;
+   unsigned int dsc_input_bpc;
int dsc_enable;
int wb_enable;
int num_active_wb;
-   int output_bpc;
int output_type;
int is_virtual;
int output_format;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 94036a9612cf..2a967458065b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -471,7 +471,13 @@ static void fetch_pipe_params(struct display_mode_lib 
*mode_lib)
mode_lib->vba.DSCEnable[mode_lib->vba.NumberOfActivePlanes] = 
dout->dsc_enable;

mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] =
dout->dsc_slices;
-   
mode_lib->vba.DSCInputBitPerComponent[mode_lib->vba.NumberOfActivePlanes] = 
dout->output_bpc;
+   if (!dout->dsc_input_bpc) {
+   
mode_lib->vba.DSCInputBitPerComponent[mode_lib->vba.NumberOfActivePlanes] =
+   ip->maximum_dsc_bits_per_component;
+   } else {
+   
mode_lib->vba.DSCInputBitPerComponent[mode_lib->vba.NumberOfActivePlanes] =
+

[PATCH 15/21] drm/amd/display: Directly retrain link from debugfs

[Qingqing Zhuo]

From: Mikita Lipski 

[why/how]
Skip logic that sets preffered link settings
and just retrain with new link_settings from Debugfs

Signed-off-by: Mikita Lipski 
Reviewed-by: Mikita Lipski 
Acked-by: Harry Wentland 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 4a95d02ce933..6659e7c181c3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -34,6 +34,7 @@
 #include "resource.h"
 #include "dsc.h"
 #include "dc_link_dp.h"
+#include "link_hwss.h"
 #include "dc/dc_dmub_srv.h"
 
 struct dmub_debugfs_trace_header {
@@ -246,7 +247,6 @@ static ssize_t dp_link_settings_write(struct file *f, const 
char __user *buf,
 {
struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
struct dc_link *link = connector->dc_link;
-   struct dc *dc = (struct dc *)link->dc;
struct dc_link_settings prefer_link_settings;
char *wr_buf = NULL;
const uint32_t wr_buf_size = 40;
@@ -313,7 +313,7 @@ static ssize_t dp_link_settings_write(struct file *f, const 
char __user *buf,
prefer_link_settings.lane_count = param[0];
prefer_link_settings.link_rate = param[1];
 
-   dc_link_set_preferred_training_settings(dc, _link_settings, 
NULL, link, true);
+   dp_retrain_link_dp_test(link, _link_settings, false);
 
kfree(wr_buf);
return size;
-- 
2.17.1

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[PATCH 14/21] drm/amd/display: Add missing mask for DCN3

[Qingqing Zhuo]

[Why]
DCN3 is not reusing DCN1 mask_sh_list, causing
SURFACE_FLIP_INT_MASK missing in the mapping.

[How]
Add the corresponding entry to DCN3 list.

Signed-off-by: Qingqing Zhuo 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
index 705fbfc37502..8a32772d4e91 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
@@ -134,6 +134,7 @@
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, 
mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK, 
mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, 
SECONDARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
+   HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, 
mask_sh),\
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, 
mask_sh),\
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
-- 
2.17.1

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[PATCH 11/21] drm/amd/display: Add function and debugfs to dump DCC_EN bit

[Qingqing Zhuo]

From: Victor Lu 

[why]
Currently to view the DCC_EN bit the entire DTN log
must be dumped. A compact method to view the DCC_EN
bit is desirable.

[how]
Introduce new debugfs interface that only dumps the
DCC_EN bit.

Example usage:
cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en

Signed-off-by: Victor Lu 
Reviewed-by: Harry Wentland 
Acked-by: Qingqing Zhuo 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 66 +++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  4 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |  3 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |  1 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |  3 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |  3 +-
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |  3 +-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  2 +
 9 files changed, 96 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 32f05aefda17..4a95d02ce933 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -3043,6 +3043,64 @@ DEFINE_SHOW_ATTRIBUTE(mst_topo);
 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
 visual_confirm_set, "%llu\n");
 
+/*
+ * Dumps the DCC_EN bit for each pipe.
+ * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
+ */
+static ssize_t dcc_en_bits_read(
+   struct file *f,
+   char __user *buf,
+   size_t size,
+   loff_t *pos)
+{
+   struct amdgpu_device *adev = file_inode(f)->i_private;
+   struct dc *dc = adev->dm.dc;
+   char *rd_buf = NULL;
+   const uint32_t rd_buf_size = 32;
+   uint32_t result = 0;
+   int offset = 0;
+   int num_pipes = dc->res_pool->pipe_count;
+   int *dcc_en_bits;
+   int i, r;
+
+   dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
+   if (!dcc_en_bits)
+   return -ENOMEM;
+
+   if (!dc->hwss.get_dcc_en_bits) {
+   kfree(dcc_en_bits);
+   return 0;
+   }
+
+   dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
+
+   rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
+   if (!rd_buf)
+   return -ENOMEM;
+
+   for (i = 0; i < num_pipes; i++)
+   offset += snprintf(rd_buf + offset, rd_buf_size - offset,
+  "%d  ", dcc_en_bits[i]);
+   rd_buf[strlen(rd_buf)] = '\n';
+
+   kfree(dcc_en_bits);
+
+   while (size) {
+   if (*pos >= rd_buf_size)
+   break;
+   r = put_user(*(rd_buf + result), buf);
+   if (r)
+   return r; /* r = -EFAULT */
+   buf += 1;
+   size -= 1;
+   *pos += 1;
+   result += 1;
+   }
+
+   kfree(rd_buf);
+   return result;
+}
+
 void dtn_debugfs_init(struct amdgpu_device *adev)
 {
static const struct file_operations dtn_log_fops = {
@@ -3051,6 +3109,11 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
.write = dtn_log_write,
.llseek = default_llseek
};
+   static const struct file_operations dcc_en_bits_fops = {
+   .owner = THIS_MODULE,
+   .read = dcc_en_bits_read,
+   .llseek = default_llseek
+   };
 
struct drm_minor *minor = adev_to_drm(adev)->primary;
struct dentry *root = minor->debugfs_root;
@@ -3078,4 +3141,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
 
debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
   adev, _trace_event_state_fops);
+
+   debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
+  _en_bits_fops);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e1f33f908b5b..7c939c0a977b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3979,3 +3979,19 @@ void dcn10_get_clock(struct dc *dc,
dc->clk_mgr->funcs->get_clock(dc->clk_mgr, 
context, clock_type, clock_cfg);
 
 }
+
+void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits)
+{
+   struct resource_pool *pool = dc->res_pool;
+   int i;
+
+   for (i = 0; i < pool->pipe_count; i++) {
+   struct hubp *hubp = pool->hubps[i];
+   struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
+
+   hubp->funcs->hubp_read_state(hubp);
+
+   if (!s->blank_en)
+   dcc_en_bits[i] = s->dcc_en ? 1 : 0;
+   }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h 

[PATCH 17/21] drm/amd/display: Determine synchronization edge based on master's vsync

[Qingqing Zhuo]

From: Mikita Lipski 

[Why]
The driver always wants to synchronize streams
to the first edge of master's vsync pulse.
In order to determine that we can read timing
flags that are used to program vsync.

Master stream's vsync polarity - Multi Display Stream Synchronization edge:

Negative   -  Falling Edge

Positive   -  Rising Edge

Signed-off-by: Mikita Lipski 
Reviewed-by: Mikita Lipski 
Reviewed-by: Sun peng Li 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 ---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 92cee957b424..a57cbdb2c7a9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5394,9 +5394,14 @@ create_fake_sink(struct amdgpu_dm_connector *aconnector)
 static void set_multisync_trigger_params(
struct dc_stream_state *stream)
 {
+   struct dc_stream_state *master = NULL;
+
if (stream->triggered_crtc_reset.enabled) {
-   stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
-   stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
+   master = stream->triggered_crtc_reset.event_source;
+   stream->triggered_crtc_reset.event =
+   master->timing.flags.VSYNC_POSITIVE_POLARITY ?
+   CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
+   stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
}
 }
 
@@ -5426,6 +5431,7 @@ static void set_master_stream(struct dc_stream_state 
*stream_set[],
 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
 {
int i = 0;
+   struct dc_stream_state *stream;
 
if (context->stream_count < 2)
return;
@@ -5437,9 +5443,18 @@ static void dm_enable_per_frame_crtc_master_sync(struct 
dc_state *context)
 * crtc_sync_master.multi_sync_enabled flag
 * For now it's set to false
 */
-   set_multisync_trigger_params(context->streams[i]);
}
+
set_master_stream(context->streams, context->stream_count);
+
+   for (i = 0; i < context->stream_count ; i++) {
+   stream = context->streams[i];
+
+   if (!stream)
+   continue;
+
+   set_multisync_trigger_params(stream);
+   }
 }
 
 static struct drm_display_mode *
-- 
2.17.1

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[PATCH 18/21] drm/amd/display: Fixed corruption on 4K tvs

[Qingqing Zhuo]

From: Harry VanZyllDeJong 

[WHY]
When on the desktop freesync is not enabled,
doing a frame stretch causes the TV to display
undesired output.

[HOW]
By changing the logic so that when ever fresync
is supported the TV is notified we are in fressync
instead on a non fresync state.

Signed-off-by: Harry VanZyllDeJong 
Reviewed-by: Tony Cheng 
Acked-by: Anthony Koo 
Acked-by: Jun Lei 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 4287be79c11a..3f4f44b44e6a 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -543,8 +543,8 @@ static void build_vrr_infopacket_data_v1(const struct 
mod_vrr_params *vrr,
infopacket->sb[6] |= 0x02;
 
/* PB6 = [Bit 2 = FreeSync Active] */
-   if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
-   vrr->state == VRR_STATE_ACTIVE_FIXED)
+   if (vrr->state != VRR_STATE_DISABLED &&
+   vrr->state != VRR_STATE_UNSUPPORTED)
infopacket->sb[6] |= 0x04;
 
// For v1 & 2 infoframes program nominal if non-fs mode, otherwise full 
range
-- 
2.17.1

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[PATCH 16/21] drm/amd/display: Add MST capability to trigger_hotplug interface

[Qingqing Zhuo]

From: Mikita Lipski 

[Why]
Need to be able to trigger software hotplug for MST connectors

[How]
For unplug the driver calls to disable topologies manager
that connector is attached to. For plugging in it does the
whole rediscovery of all connectors in drm device and enbles their
topologies if attached.

The interface for MST connectors works in the following way:

1. To disconnect all MST topologies currently connected:
   echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst

2. To reconnect/rediscover all topologies that are physically
connected to the card:
   echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst

A related fix which has been merged with this patch
Leo Ma(Hanghong Ma)'s work:

Set power states before disable MST topology
[Why]
When we try to disable MST topology from the
debugfs entry, some receiver will hang.
[How]
Set DPCD 600h power states to
2(power down mode)before disable MST topology.

Signed-off-by: Mikita Lipski 
Reviewed-by: Mikita Lipski 
Reviewed-by: Sun peng Li 
Acked-by: Qingqing Zhuo 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 71 ++-
 1 file changed, 70 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 6659e7c181c3..9a13f47022df 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2980,7 +2980,73 @@ static int mst_topo_show(struct seq_file *m, void 
*unused)
 }
 
 /*
- * Sets the force_timing_sync debug optino from the given string.
+ * Sets trigger hpd for MST topologies.
+ * All connected connectors will be rediscovered and re started as needed if 
val of 1 is sent.
+ * All topologies will be disconnected if val of 0 is set .
+ * Usage to enable topologies: echo 1 > 
/sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
+ * Usage to disable topologies: echo 0 > 
/sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
+ */
+static int trigger_hpd_mst_set(void *data, u64 val)
+{
+   struct amdgpu_device *adev = data;
+   struct drm_device *dev = adev_to_drm(adev);
+   struct drm_connector_list_iter iter;
+   struct amdgpu_dm_connector *aconnector;
+   struct drm_connector *connector;
+   struct dc_link *link = NULL;
+
+   if (val == 1) {
+   drm_connector_list_iter_begin(dev, );
+   drm_for_each_connector_iter(connector, ) {
+   aconnector = to_amdgpu_dm_connector(connector);
+   if (aconnector->dc_link->type == 
dc_connection_mst_branch &&
+   aconnector->mst_mgr.aux) {
+   dc_link_detect(aconnector->dc_link, 
DETECT_REASON_HPD);
+   
drm_dp_mst_topology_mgr_set_mst(>mst_mgr, true);
+   }
+   }
+   } else if (val == 0) {
+   drm_connector_list_iter_begin(dev, );
+   drm_for_each_connector_iter(connector, ) {
+   aconnector = to_amdgpu_dm_connector(connector);
+   if (!aconnector->dc_link)
+   continue;
+
+   if (!(aconnector->port && 
>mst_port->mst_mgr))
+   continue;
+
+   link = aconnector->dc_link;
+   dp_receiver_power_ctrl(link, false);
+   
drm_dp_mst_topology_mgr_set_mst(>mst_port->mst_mgr, false);
+   link->mst_stream_alloc_table.stream_count = 0;
+   memset(link->mst_stream_alloc_table.stream_allocations, 
0,
+   
sizeof(link->mst_stream_alloc_table.stream_allocations));
+   }
+   } else {
+   return 0;
+   }
+   drm_kms_helper_hotplug_event(dev);
+
+   return 0;
+}
+
+/*
+ * The interface doesn't need get function, so it will return the
+ * value of zero
+ * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
+ */
+static int trigger_hpd_mst_get(void *data, u64 *val)
+{
+   *val = 0;
+   return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
+trigger_hpd_mst_set, "%llu\n");
+
+
+/*
+ * Sets the force_timing_sync debug option from the given string.
  * All connected displays will be force synchronized immediately.
  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
  */
@@ -3142,6 +3208,9 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
   adev, _trace_event_state_fops);
 
+   debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
+  adev, _hpd_mst_ops);
+
debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
  

[PATCH 12/21] drm/amd/display: Set initial value to a divider

[Qingqing Zhuo]

From: Mikita Lipski 

[why/how]
Due to compiler optimization the values would be
passed to the division function uninitialized
causing a div by zero. Initialize the numerator
and denominator to 0 and 1 to prevent division
by zero.

Signed-off-by: Mikita Lipski 
Reviewed-by: Mikita Lipski 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b2b6e26f160a..29bc2874f6a7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2891,8 +2891,8 @@ static struct fixed31_32 get_pbn_per_slot(struct 
dc_stream_state *stream)
 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
 {
struct fixed31_32 peak_kbps;
-   uint32_t numerator;
-   uint32_t denominator;
+   uint32_t numerator = 0;
+   uint32_t denominator = 1;
 
/*
 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
-- 
2.17.1

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[PATCH 13/21] drm/amd/display: Tweak the kernel doc for crc_rd_wrk

[Qingqing Zhuo]

From: Wayne Lin 

[Why]
Commit 04f6f5baec25ce76b8b6e1af63c54b6042c16716
("drm/amd/display: Add kernel doc to crc_rd_wrk
field") adds kernel doc for crc_rd_wrk field in
amdgpu_dm.h but it's incorrectly formatted.
Make htmldocs warns:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:398: warning:
Incorrect use of kernel-doc format:  * @crc_rd_wrk

[How]
Tweak the kernel doc for crc_rd_wrk.

Signed-off-by: Wayne Lin 
Reviewed-by: Rodrigo Siqueira 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index c5f5f62cf591..13f3db14b265 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -396,7 +396,7 @@ struct amdgpu_display_manager {
 
 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
/**
-* @crc_rd_wrk
+* @crc_rd_wrk:
 *
 * Work to be executed in a separate thread to communicate with PSP.
 */
-- 
2.17.1

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[PATCH 10/21] drm/amd/display: Add dc_debug flag to disable min fclk

[Qingqing Zhuo]

From: Harry Wentland 

[Why]
Add debug flag for an option to disable min fclk.

Signed-off-by: Harry Wentland 
Reviewed-by: Harry Wentland 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 4 ++--
 drivers/gpu/drm/amd/display/dc/dc.h| 1 +
 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c| 2 +-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index b47e3558e176..c636b589d69d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -136,13 +136,13 @@ void vg_update_clocks(struct clk_mgr *clk_mgr_base,
}
}
 
-   if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, 
clk_mgr_base->clks.dcfclk_khz)) {
+   if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, 
clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) {
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
dcn301_smu_set_hard_min_dcfclk(clk_mgr, 
clk_mgr_base->clks.dcfclk_khz);
}
 
if (should_set_clock(safe_to_lower,
-   new_clocks->dcfclk_deep_sleep_khz, 
clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
+   new_clocks->dcfclk_deep_sleep_khz, 
clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable_min_fclk) {
clk_mgr_base->clks.dcfclk_deep_sleep_khz = 
new_clocks->dcfclk_deep_sleep_khz;
dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, 
clk_mgr_base->clks.dcfclk_deep_sleep_khz);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 8b725347e2ed..cf5abcb74601 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -460,6 +460,7 @@ struct dc_debug_options {
enum pipe_split_policy pipe_split_policy;
bool force_single_disp_pipe_split;
bool voltage_align_fclk;
+   bool disable_min_fclk;
 
bool disable_dfs_bypass;
bool disable_dpp_power_gate;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 10c1884e3d30..2127399cf464 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 Advanced Micro Devices, Inc.
+ * Copyright 2019-2021 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
-- 
2.17.1

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[PATCH 07/21] drm/amd/display: Add debugfs entry for LTTPR register status

[Qingqing Zhuo]

From: Aurabindo Pillai 

[Why]
Functionality of LTTPR is reporter through the DPCD register

[How]
Expose a interface in debugfs to read the current status of
LTTPR as reported from the device's DPCD register

Signed-off-by: Aurabindo Pillai 
Reviewed-by: Rodrigo Siqueira 
Acked-by: Qingqing Zhuo 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 66 +++
 1 file changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 5a9809e33af8..32f05aefda17 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -400,6 +400,70 @@ static ssize_t dp_phy_settings_read(struct file *f, char 
__user *buf,
return result;
 }
 
+static int dp_lttpr_status_show(struct seq_file *m, void *d)
+{
+   char *data;
+   struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private;
+   struct dc_link *link = connector->dc_link;
+   uint32_t read_size = 1;
+   uint8_t repeater_count = 0;
+
+   data = kzalloc(read_size, GFP_KERNEL);
+   if (!data)
+   return 0;
+
+   dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size);
+
+   switch ((uint8_t)*data) {
+   case 0x80:
+   repeater_count = 1;
+   break;
+   case 0x40:
+   repeater_count = 2;
+   break;
+   case 0x20:
+   repeater_count = 3;
+   break;
+   case 0x10:
+   repeater_count = 4;
+   break;
+   case 0x8:
+   repeater_count = 5;
+   break;
+   case 0x4:
+   repeater_count = 6;
+   break;
+   case 0x2:
+   repeater_count = 7;
+   break;
+   case 0x1:
+   repeater_count = 8;
+   break;
+   case 0x0:
+   repeater_count = 0;
+   break;
+   default:
+   repeater_count = (uint8_t)*data;
+   break;
+   }
+
+   seq_printf(m, "phy repeater count: %d\n", repeater_count);
+
+   dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size);
+
+   if ((uint8_t)*data == 0x55)
+   seq_printf(m, "phy repeater mode: transparent\n");
+   else if ((uint8_t)*data == 0xAA)
+   seq_printf(m, "phy repeater mode: non-transparent\n");
+   else if ((uint8_t)*data == 0x00)
+   seq_printf(m, "phy repeater mode: non lttpr\n");
+   else
+   seq_printf(m, "phy repeater mode: read error\n");
+
+   kfree(data);
+   return 0;
+}
+
 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 size_t size, loff_t *pos)
 {
@@ -2301,6 +2365,7 @@ DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
 DEFINE_SHOW_ATTRIBUTE(output_bpc);
+DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
 #ifdef CONFIG_DRM_AMD_DC_HDCP
 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
 #endif
@@ -2421,6 +2486,7 @@ static const struct {
 } dp_debugfs_entries[] = {
{"link_settings", _link_settings_debugfs_fops},
{"phy_settings", _phy_settings_debugfs_fop},
+   {"lttpr_status", _lttpr_status_fops},
{"test_pattern", _phy_test_pattern_fops},
 #ifdef CONFIG_DRM_AMD_DC_HDCP
{"hdcp_sink_capability", _sink_capability_fops},
-- 
2.17.1

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[PATCH 09/21] drm/amd/display: Add debug prints for SMU messages

[Qingqing Zhuo]

From: Harry Wentland 

[Why]
Add debug prints for SMU messages with regard to
versions, clocks, and more.

Signed-off-by: Harry Wentland 
Reviewed-by: Harry Wentland 
Reviewed-by: Robin Singh 
Acked-by: Qingqing Zhuo 
---
 .../display/dc/clk_mgr/dcn301/dcn301_smu.c| 29 ---
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
index 68942bbc7472..07774fa2c2cf 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
@@ -113,10 +113,13 @@ int dcn301_smu_send_msg_with_param(
 
 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
 {
-   return dcn301_smu_send_msg_with_param(
-   clk_mgr,
-   VBIOSSMC_MSG_GetSmuVersion,
-   0);
+   int smu_version = dcn301_smu_send_msg_with_param(clk_mgr,
+
VBIOSSMC_MSG_GetSmuVersion,
+0);
+
+   DC_LOG_DEBUG("%s %x\n", __func__, smu_version);
+
+   return smu_version;
 }
 
 
@@ -124,6 +127,8 @@ int dcn301_smu_set_dispclk(struct clk_mgr_internal 
*clk_mgr, int requested_dispc
 {
int actual_dispclk_set_mhz = -1;
 
+   DC_LOG_DEBUG("%s(%d)\n", __func__, requested_dispclk_khz);
+
/*  Unit of SMU msg parameter is Mhz */
actual_dispclk_set_mhz = dcn301_smu_send_msg_with_param(
clk_mgr,
@@ -137,6 +142,8 @@ int dcn301_smu_set_dprefclk(struct clk_mgr_internal 
*clk_mgr)
 {
int actual_dprefclk_set_mhz = -1;
 
+   DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000);
+
actual_dprefclk_set_mhz = dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDprefclkFreq,
@@ -151,6 +158,8 @@ int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal 
*clk_mgr, int request
 {
int actual_dcfclk_set_mhz = -1;
 
+   DC_LOG_DEBUG("%s(%d)\n", __func__, requested_dcfclk_khz);
+
actual_dcfclk_set_mhz = dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
@@ -163,6 +172,8 @@ int dcn301_smu_set_min_deep_sleep_dcfclk(struct 
clk_mgr_internal *clk_mgr, int r
 {
int actual_min_ds_dcfclk_mhz = -1;
 
+   DC_LOG_DEBUG("%s(%d)\n", __func__, requested_min_ds_dcfclk_khz);
+
actual_min_ds_dcfclk_mhz = dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
@@ -175,6 +186,8 @@ int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, 
int requested_dpp_kh
 {
int actual_dppclk_set_mhz = -1;
 
+   DC_LOG_DEBUG("%s(%d)\n", __func__, requested_dpp_khz);
+
actual_dppclk_set_mhz = dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDppclkFreq,
@@ -187,6 +200,8 @@ void dcn301_smu_set_display_idle_optimization(struct 
clk_mgr_internal *clk_mgr,
 {
//TODO: Work with smu team to define optimization options.
 
+   DC_LOG_DEBUG("%s(%x)\n", __func__, idle_info);
+
dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDisplayIdleOptimizations,
@@ -202,6 +217,8 @@ void dcn301_smu_enable_phy_refclk_pwrdwn(struct 
clk_mgr_internal *clk_mgr, bool
idle_info.idle_info.phy_ref_clk_off = 1;
}
 
+   DC_LOG_DEBUG("%s(%d)\n", __func__, enable);
+
dcn301_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDisplayIdleOptimizations,
@@ -218,12 +235,16 @@ void dcn301_smu_enable_pme_wa(struct clk_mgr_internal 
*clk_mgr)
 
 void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t 
addr_high)
 {
+   DC_LOG_DEBUG("%s(%x)\n", __func__, addr_high);
+
dcn301_smu_send_msg_with_param(clk_mgr,
VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
 }
 
 void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t 
addr_low)
 {
+   DC_LOG_DEBUG("%s(%x)\n", __func__, addr_low);
+
dcn301_smu_send_msg_with_param(clk_mgr,
VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
 }
-- 
2.17.1

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[PATCH 08/21] drm/amd/display: Added dc_edp_id_count to dc_context

[Qingqing Zhuo]

From: Jake Wang 

[Why]
We need to keep track of the number of eDP links to
properly enumerate edp panel control instance.

[How]
Added dc_edp_id_count to dc_context to keep track of
number of eDP links.

Signed-off-by: Jake Wang 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 10 +++---
 drivers/gpu/drm/amd/display/dc/dc_types.h |  1 +
 2 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 719fc6b502b6..b2b6e26f160a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1386,8 +1386,6 @@ static bool dc_link_construct(struct dc_link *link,
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
-   struct dc_link *edp_links[MAX_NUM_EDP];
-   int edp_num;
 
DC_LOGGER_INIT(dc_ctx->logger);
 
@@ -1513,14 +1511,12 @@ static bool dc_link_construct(struct dc_link *link,
(link->link_id.id == CONNECTOR_ID_EDP ||
link->link_id.id == CONNECTOR_ID_LVDS)) {
panel_cntl_init_data.ctx = dc_ctx;
-   get_edp_links(panel_cntl_init_data.ctx->dc, edp_links, 
_num);
-   if ((edp_num > 1) && (link->link_index > 
edp_links[0]->link_index))
-   panel_cntl_init_data.inst = 1;
-   else
-   panel_cntl_init_data.inst = 0;
+   panel_cntl_init_data.inst =
+   panel_cntl_init_data.ctx->dc_edp_id_count;
link->panel_cntl =
link->dc->res_pool->funcs->panel_cntl_create(

_cntl_init_data);
+   panel_cntl_init_data.ctx->dc_edp_id_count++;
 
if (link->panel_cntl == NULL) {
DC_ERROR("Failed to create link panel_cntl!\n");
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index d8912a4de3b1..432754eaf10b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -113,6 +113,7 @@ struct dc_context {
struct gpio_service *gpio_service;
uint32_t dc_sink_id_count;
uint32_t dc_stream_id_count;
+   uint32_t dc_edp_id_count;
uint64_t fbc_gpu_addr;
struct dc_dmub_srv *dmub_srv;
 
-- 
2.17.1

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[PATCH 06/21] drm/amd/display: Move vupdate keepout programming from DCN20 to DCN10

[Qingqing Zhuo]

From: Leo Li 

[Why]

The OTG_VUPDATE_KEEPOUT register and fields is
available on DCN10, and named the same in DCN20.

[How]

Move register definition and programming function
to dcn10 optc.

There is no functional change.

Signed-off-by: Leo Li 
Reviewed-by: Harry Wentland 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c| 16 
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h|  3 +++
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c| 16 
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h|  3 ---
 4 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 6138f4887de7..677663cc7bff 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -131,6 +131,22 @@ void optc1_setup_vertical_interrupt2(
OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
 }
 
+/**
+ * Vupdate keepout can be set to a window to block the update lock for that 
pipe from changing.
+ * Start offset begins with vstartup and goes for x number of clocks,
+ * end offset starts from end of vupdate to x number of clocks.
+ */
+void optc1_set_vupdate_keepout(struct timing_generator *optc,
+  struct vupdate_keepout_params *params)
+{
+   struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+   REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
+ MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 
params->start_offset,
+ MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 
params->end_offset,
+ OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, params->enable);
+}
+
 /**
  * program_timing_generator   used by mode timing set
  * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 2529723beeb1..cabfe83fd634 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -194,6 +194,9 @@ struct dcn_optc_registers {
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 
mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, 
mask_sh),\
+   SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 
mask_sh), \
+   SF(OTG0_OTG_VUPDATE_KEEPOUT, 
MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+   SF(OTG0_OTG_VUPDATE_KEEPOUT, 
MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index ea7eaf7d755f..3139d90017ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -134,22 +134,6 @@ void optc2_set_gsl_window(struct timing_generator *optc,
OTG_GSL_WINDOW_END_Y, params->gsl_window_end_y);
 }
 
-/**
- * Vupdate keepout can be set to a window to block the update lock for that 
pipe from changing.
- * Start offset begins with vstartup and goes for x number of clocks,
- * end offset starts from end of vupdate to x number of clocks.
- */
-void optc2_set_vupdate_keepout(struct timing_generator *optc,
-  const struct vupdate_keepout_params *params)
-{
-   struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-   REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
-   MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 
params->start_offset,
-   MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 
params->end_offset,
-   OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, params->enable);
-}
-
 void optc2_set_gsl_source_select(
struct timing_generator *optc,
int group_idx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index e0a0a8a8e2c6..3dee2ec2a1bb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -56,9 +56,6 @@
SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
-   SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 
mask_sh), \
-   SF(OTG0_OTG_VUPDATE_KEEPOUT, 
MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
-   SF(OTG0_OTG_VUPDATE_KEEPOUT, 
MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \

[PATCH 05/21] drm/amd/display: add NULL check to avoid kernel crash in DC.

[Qingqing Zhuo]

From: Robin Singh 

[why]
There is case when the userspace like IGT test updates the custom
timings, i.e. the number of active lines CRTC property value,
and without committing the change, followed by
resetting the display, creating FB and plane to the pipe
and committing. The NULL pointer of pipe_ctx->plane_state
occurs and result in kernel crash. We need to avoid that.

[how]
add pointer check for the dc_plane_state of the pipe context in
the call of committing planes for stream in DC component.

Signed-off-by: Robin Singh 
Reviewed-by: Harry Wentland 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d9ab134a178f..c0ecedac83a4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2815,6 +2815,9 @@ static void commit_planes_for_stream(struct dc *dc,
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
 
+   if (!pipe_ctx->plane_state)
+   continue;
+
if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
!pipe_ctx->stream || pipe_ctx->stream != stream 
||

!pipe_ctx->plane_state->update_flags.bits.addr_update)
-- 
2.17.1

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[PATCH 04/21] drm/amd/display: use MST downstream AUX to dump DPRX CRCs

[Qingqing Zhuo]

From: "David (Dingchen) Zhang" 

[why]
 In MST setup, we'd use MST downstream AUX to
 dump the DPRX CRCs from sink device.

[how]
 Assign the mst_port->aux to read DPCD registers.

Signed-off-by: David (Dingchen) Zhang 
Reviewed-by: Harry Wentland 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index c6d6baab106e..5cd788b20c21 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -307,7 +307,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, 
const char *src_name)
goto cleanup;
}
 
-   aux = >dm_dp_aux.aux;
+   aux = (aconn->port) ? >port->aux : >dm_dp_aux.aux;
 
if (!aux) {
DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
-- 
2.17.1

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[PATCH 01/21] drm/amd/display: Fix 32 bit compilation of dmub_srv.c

[Qingqing Zhuo]

From: Anson Jacob 

[Why/How]
Fix cast from pointer to integer of different size error
from dmub/src/dmub_srv.c

Signed-off-by: Anson Jacob 
Reviewed-by: Rodrigo Siqueira 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 743d3b7f6f24..e36e89157703 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -510,7 +510,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 
dmub_memset(_rb_params, 0, sizeof(outbox0_rb_params));
outbox0_rb_params.ctx = dmub;
-   outbox0_rb_params.base_address = (void 
*)((uint64_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
+   outbox0_rb_params.base_address = (void 
*)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
outbox0_rb_params.capacity = tracebuff_fb->size - 
dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
dmub_rb_init(>outbox0_rb, _rb_params);
 
-- 
2.17.1

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[PATCH 03/21] drm/amd/display: Add delay in dmub_srv_send_gpint_command

[Qingqing Zhuo]

From: Wyatt Wood 

[Why]
Today a parameter is passed to dmub_srv_send_gpint_command
which specifies the max amount of time to wait for the command
to be acked.
This parameter instead specifies the number of times to check if
the command was acked.
We wish to add a lower bound to the timeout, which can be
accomplished by using a delay or a timestamp.
It has been decided to use udelay instead of a timestamp simply
because we don't want to expose a high precision counter if it
doesn't yield large benefits.

[How]
Add udelay(1) between each for loop iteration.

Signed-off-by: Wyatt Wood 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index e36e89157703..1cbb125b4063 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -647,6 +647,8 @@ dmub_srv_send_gpint_command(struct dmub_srv *dmub,
dmub->hw_funcs.set_gpint(dmub, reg);
 
for (i = 0; i < timeout_us; ++i) {
+   udelay(1);
+
if (dmub->hw_funcs.is_gpint_acked(dmub, reg))
return DMUB_STATUS_OK;
}
-- 
2.17.1

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[PATCH 02/21] drm/amd/display: Retry getting PSR state if command times out

[Qingqing Zhuo]

From: Wyatt Wood 

[Why]
GPINT command to get PSR state from FW times out.

[How]
Add retry to get valid PSR state.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dc_types.h |  3 +-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 29 ---
 2 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index b5e875ee9027..d8912a4de3b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -687,7 +687,8 @@ enum dc_psr_state {
PSR_STATE5,
PSR_STATE5a,
PSR_STATE5b,
-   PSR_STATE5c
+   PSR_STATE5c,
+   PSR_STATE_INVALID = 0xFF
 };
 
 struct psr_config {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 15ed09b7a452..28ff059aa7f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -80,19 +80,26 @@ static enum dc_psr_state convert_psr_state(uint32_t 
raw_state)
 static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state)
 {
struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
-   uint32_t raw_state;
+   uint32_t raw_state = 0;
+   uint32_t retry_count = 0;
enum dmub_status status;
 
-   // Send gpint command and wait for ack
-   status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 
30);
-
-   if (status == DMUB_STATUS_OK) {
-   // GPINT was executed, get response
-   dmub_srv_get_gpint_response(srv, _state);
-   *state = convert_psr_state(raw_state);
-   } else
-   // Return invalid state when GPINT times out
-   *state = 0xFF;
+   do {
+   // Send gpint command and wait for ack
+   status = dmub_srv_send_gpint_command(srv, 
DMUB_GPINT__GET_PSR_STATE, 0, 30);
+
+   if (status == DMUB_STATUS_OK) {
+   // GPINT was executed, get response
+   dmub_srv_get_gpint_response(srv, _state);
+   *state = convert_psr_state(raw_state);
+   } else
+   // Return invalid state when GPINT times out
+   *state = PSR_STATE_INVALID;
+
+   // Assert if max retry hit
+   if (retry_count >= 1000)
+   ASSERT(0);
+   } while (++retry_count <= 1000 && *state == PSR_STATE_INVALID);
 }
 
 /*
-- 
2.17.1

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[PATCH 00/21] DC Patches April 5, 2021

[Qingqing Zhuo]

This DC patchset brings improvements in multiple areas.
In summary, we highlight:

* Firmware release 0.0.59
* Fixes on display experiences for 4k TVs, register mask missing, etc.
* Enhancements on MST, code cleaning and debug messages.

---

Anson Jacob (1):
  drm/amd/display: Fix 32 bit compilation of dmub_srv.c

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.59

Aric Cyr (1):
  drm/amd/display: 3.2.130

Aurabindo Pillai (1):
  drm/amd/display: Add debugfs entry for LTTPR register status

David (Dingchen) Zhang (1):
  drm/amd/display: use MST downstream AUX to dump DPRX CRCs

Harry VanZyllDeJong (1):
  drm/amd/display: Fixed corruption on 4K tvs

Harry Wentland (2):
  drm/amd/display: Add debug prints for SMU messages
  drm/amd/display: Add dc_debug flag to disable min fclk

Jake Wang (1):
  drm/amd/display: Added dc_edp_id_count to dc_context

Leo Li (1):
  drm/amd/display: Move vupdate keepout programming from DCN20 to DCN10

Mikita Lipski (4):
  drm/amd/display: Set initial value to a divider
  drm/amd/display: Directly retrain link from debugfs
  drm/amd/display: Add MST capability to trigger_hotplug interface
  drm/amd/display: Determine synchronization edge based on master's
vsync

Nicholas Kazlauskas (1):
  drm/amd/display: Cleanup DML DSC input bpc validation

Qingqing Zhuo (1):
  drm/amd/display: Add missing mask for DCN3

Robin Singh (1):
  drm/amd/display: add NULL check to avoid kernel crash in DC.

Victor Lu (1):
  drm/amd/display: Add function and debugfs to dump DCC_EN bit

Wayne Lin (1):
  drm/amd/display: Tweak the kernel doc for crc_rd_wrk

Wyatt Wood (2):
  drm/amd/display: Retry getting PSR state if command times out
  drm/amd/display: Add delay in dmub_srv_send_gpint_command

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  21 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   2 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c |   2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 207 +-
 .../display/dc/clk_mgr/dcn301/dcn301_smu.c|  29 ++-
 .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c|   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |   3 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  14 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h |   4 +-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  29 ++-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  16 ++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   4 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |  16 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   3 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   1 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  16 --
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   3 -
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   2 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h |   1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |   3 +-
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |   3 +-
 .../amd/display/dc/dcn301/dcn301_resource.c   |   2 +-
 .../drm/amd/display/dc/dml/display_mode_lib.c |   2 +-
 .../amd/display/dc/dml/display_mode_structs.h |   4 +-
 .../drm/amd/display/dc/dml/display_mode_vba.c |   8 +-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   2 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  17 +-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |   4 +-
 .../amd/display/modules/freesync/freesync.c   |   4 +-
 32 files changed, 364 insertions(+), 71 deletions(-)

-- 
2.17.1

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[PATCH] amd: display: modules: Remove repeated struct declaration

[Wan Jiabing]

struct mod_hdcp is declared twice. One is declared at 33rd line.
The blew one is not needed. Remove the duplicate.

Signed-off-by: Wan Jiabing 
---
 drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h 
b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
index d223ed3be5d3..03fe49c5b7d0 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
@@ -255,8 +255,6 @@ struct mod_hdcp_config {
uint8_t index;
 };
 
-struct mod_hdcp;
-
 /* dm allocates memory of mod_hdcp per dc_link on dm init based on memory 
size*/
 size_t mod_hdcp_get_memory_size(void);
 
-- 
2.25.1

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Re: Interlaced resolutions hang the desktop

[Alberto Salvia Novella]

There's no "xorg.conf" on my system.

On Wed, 31 Mar 2021 at 20:01, Alex Deucher  wrote:

> Does disabling pageflipping via the xorg.conf help?
>
> Alex
>
> On Wed, Mar 31, 2021 at 1:40 PM Christian König
>  wrote:
> >
> > Yeah, agree that must be some kind of bug in the upper layer of the
> stack.
> >
> > Most likely some userspace component is not handling the specialties of
> interlacing correctly (different vblank timing every other frame).
> >
> > It probably only works on Intel and after restarting the display manager
> by coincident.
> >
> > Sorry, but as I said this is a use case which basically nobody is using
> any more and because of this the different parts of the stack are not
> tested well enough for this.
> >
> > Christian.
> >
> > Am 31.03.21 um 17:47 schrieb Alberto Salvia Novella:
> >
> > Restarting the display manager service works and, more importantly,
> makes the bug no longer reproducible.
> >
> > Restarting the window manager doesn't work.
> >
> > Changing display manager makes the bug still reproducible.
> >
> > Maybe this is due to xorg-server, isn't it?
> >
> > On Wed, 31 Mar 2021 at 16:55, Christian König <
> ckoenig.leichtzumer...@gmail.com> wrote:
> >>
> >> Well the hardware is working fine as far as I can see.
> >>
> >> Can you try to kill the X server over SSH and see if you then get some
> screen update?
> >>
> >> Regards,
> >> Christian.
> >>
> >> Am 31.03.21 um 16:52 schrieb Alberto Salvia Novella:
> >>
> >> Output.
> >>
> >> On Wed, 31 Mar 2021 at 16:36, Christian König 
> wrote:
> >>>
> >>> Mhm strange.
> >>>
> >>> Can you get me the output of "sudo cat
> /sys/kernel/debug/dri/0/radeon_fence_info" when the problem happens?
> >>>
> >>> Thanks,
> >>> Christian.
> >>>
> >>> Am 31.03.21 um 16:33 schrieb Alberto Salvia Novella:
> >>>
> >>> - The computer still replies to ping.
> >>> - The journal shows no errors, but a few warnings.
> >>> - The mouse doesn't freeze.
> >>>
> >>> On Wed, 31 Mar 2021 at 10:09, Christian König <
> christian.koe...@amd.com> wrote:
> 
>  Can you access the system over the network and see if there is
> anything in the system log?
> 
>  It sounds like the display stack has crashed, but when the sound
> keeps playing the system is most likely still responsive over network.
> 
>  Thanks,
>  Christian.
> 
>  Am 31.03.21 um 10:05 schrieb Alberto Salvia Novella:
> 
>  What happens is this simple: after a few minutes, about 6 or so, the
> entire content of the screen stays still. In some minor situations only the
> applications panel of KDE Plasma.
> 
>  If music is playing it continues playing, so only graphics are hung.
> Yet in most cases the power button won't shut down the computer, as it
> usually does.
> 
>  At least this is the case using kwin on x11, and not on wayland. It
> only happens on "radeon" and not on Intel or "radeonhd".
> 
>  On Wed, 31 Mar 2021 at 09:48, Christian König <
> christian.koe...@amd.com> wrote:
> >
> > Correct, but a TV is intended for videos only. That's why it
> implements only the lower HDMI standard.
> >
> > Interlaced transmits only halve the lines with each frame, so a 60Hz
> mode effectively either becomes a 30Hz mode, halving the vertical
> resolution or adaptive motion compensated which the know visual artifacts.
> Depending on what the deinterlacing setting on your TV is.
> >
> > You could just add a progressive 1920x540@60 or 1920x1080@30 mode
> manually and would have the same effect with probably better quality. See
> https://de.wikipedia.org/wiki/Deinterlacing for reference.
> >
> > If you can give us some more information what is happening when the
> system freeze we could try to narrow this down, but we can't spend much
> time on a very specific use case in a driver which is in maintenance mode.
> >
> > Regards,
> > Christian.
> >
> > Am 31.03.21 um 09:21 schrieb Alberto Salvia Novella:
> >
> > 24fps is intended for video only. Anything interactive at 24fps, as
> just moving the mouse around, is extremely choppy.
> >
> > No way anyone would prefer that over an interlaced resolution or a
> lower resolution. That is, by far, the worst option.
> >
> > Just try it on your screen, set it to 24Hz or alike, and tell me
> your experience. You can't even tell where the mouse is going to go.
> >
> > On Wed, 31 Mar 2021 at 08:44, Christian König <
> christian.koe...@amd.com> wrote:
> >>
> >> Hi Alberto,
> >>
> >> well a frame rate of 24Hz is perfectly reasonable for a TV and
> desktop usage.
> >>
> >> This is probably caused by the TVs limited HDMI bandwidth and a
> refresh rate of 30/25 Hz for the interlaced mode isn't much better either.
> >>
> >> Regards,
> >> Christian.
> >>
> >> Am 30.03.21 um 22:59 schrieb Alberto Salvia Novella:
> >>
> >> The frame-rate at 24Hz is extremely poor for normal desktop usage.
> 

Re: [PATCH 10/34] drm/amdkfd: svm range eviction and restore

[kernel test robot]

Hi Felix,

I love your patch! Perhaps something to improve:

[auto build test WARNING on next-20210331]
[cannot apply to drm-intel/for-linux-next drm-tip/drm-tip 
drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master 
drm/drm-next v5.12-rc5 v5.12-rc4 v5.12-rc3 v5.12-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
base:7a43c78d0573e00456b033e2b9a895b89464
config: x86_64-randconfig-a011-20210401 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# 
https://github.com/0day-ci/linux/commit/07dfb6a9dad338dae38a3a840ce14f77e7498b1f
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
git checkout 07dfb6a9dad338dae38a3a840ce14f77e7498b1f
# save the attached .config to linux build tree
make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:170:6: warning: no previous 
prototype for 'svm_range_dma_unmap' [-Wmissing-prototypes]
 170 | void svm_range_dma_unmap(struct device *dev, dma_addr_t *dma_addr,
 |  ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:603:6: warning: no previous 
prototype for 'svm_range_add_child' [-Wmissing-prototypes]
 603 | void svm_range_add_child(struct svm_range *prange, struct mm_struct 
*mm,
 |  ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:799:5: warning: no previous 
prototype for 'svm_range_reserve_bos' [-Wmissing-prototypes]
 799 | int svm_range_reserve_bos(struct svm_validate_context *ctx)
 | ^
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:853:6: warning: no previous 
prototype for 'svm_range_unreserve_bos' [-Wmissing-prototypes]
 853 | void svm_range_unreserve_bos(struct svm_validate_context *ctx)
 |  ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c: In function 
'svm_range_evict':
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:1071:6: warning: variable 
>> 'invalid' set but not used [-Wunused-but-set-variable]
1071 |  int invalid, evicted_ranges;
 |  ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c: At top level:
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:1094:19: warning: no previous 
prototype for 'svm_range_clone' [-Wmissing-prototypes]
1094 | struct svm_range *svm_range_clone(struct svm_range *old)
 |   ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:1349:1: warning: no previous 
prototype for 'svm_range_add_list_work' [-Wmissing-prototypes]
1349 | svm_range_add_list_work(struct svm_range_list *svms, struct 
svm_range *prange,
 | ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:1371:6: warning: no previous 
prototype for 'schedule_deferred_list_work' [-Wmissing-prototypes]
1371 | void schedule_deferred_list_work(struct svm_range_list *svms)
 |  ^~~


vim +/invalid +1071 drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c

  1054  
  1055  /**
  1056   * svm_range_evict - evict svm range
  1057   *
  1058   * Stop all queues of the process to ensure GPU doesn't access the 
memory, then
  1059   * return to let CPU evict the buffer and proceed CPU pagetable update.
  1060   *
  1061   * Don't need use lock to sync cpu pagetable invalidation with GPU 
execution.
  1062   * If invalidation happens while restore work is running, restore work 
will
  1063   * restart to ensure to get the latest CPU pages mapping to GPU, then 
start
  1064   * the queues.
  1065   */
  1066  static int
  1067  svm_range_evict(struct svm_range *prange, struct mm_struct *mm,
  1068  unsigned long start, unsigned long last)
  1069  {
  1070  struct svm_range_list *svms = prange->svms;
> 1071  int invalid, evicted_ranges;
  1072  int r = 0;
  1073  
  1074  invalid = atomic_inc_return(>invalid);
  1075  evicted_ranges = atomic_inc_return(>evicted_ranges);
  1076  if (evicted_ranges != 1)
  1077  return r;
  1078  
  1079  pr_debug("evicting svms 0x%p range [0x%lx 0x%lx]\n",
  1080   prange->svms, prange->start, prange->last);
  1081  
  1082  /* First eviction, stop the queues */
  1083  r = kgd2kfd_quiesce_mm(mm);
  1084  if (r)
  1085  pr_debug("failed to quiesc

[PATCH] drm/amdgpu/display: fix warning on 32 bit in dmub

[Alex Deucher]

Use uintptr_t rather than uint64_t.

Signed-off-by: Alex Deucher 
Cc: Dave Airlie 
Cc: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 743d3b7f6f24..e36e89157703 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -510,7 +510,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 
dmub_memset(_rb_params, 0, sizeof(outbox0_rb_params));
outbox0_rb_params.ctx = dmub;
-   outbox0_rb_params.base_address = (void 
*)((uint64_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
+   outbox0_rb_params.base_address = (void 
*)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
outbox0_rb_params.capacity = tracebuff_fb->size - 
dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
dmub_rb_init(>outbox0_rb, _rb_params);
 
-- 
2.30.2

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[amdgpu] Compute kernels still run when the host process exit?

[Smith John]

Hi, when I killed an OpenCL host process, the kernels it launched were not
terminated, and still run.

My OpenCL runtime is AMDGPU-PRO 20.20. OS Ubuntu 18.04.5 with  Linux Kernel
5.4.53

I was wondering if it was a bug or the driver did not implement this
"watchdog" mechanism.
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Re: [Intel-gfx] [PATCH v2 00/20] drm: Use new DRM printk funcs (like drm_dbg_*()) in DP helpers

[Jani Nikula]

On Fri, 26 Mar 2021, Lyude Paul  wrote:
> Since it's been asked quite a few times on some of the various DP
> related patch series I've submitted to use the new DRM printk helpers,
> and it technically wasn't really trivial to do this before due to the
> lack of a consistent way to find a drm_device for an AUX channel, this
> patch series aims to address this. In this series we:
>
> * Clean-up potentially erroneous usages of drm_dp_aux_init() and
>   drm_dp_aux_register() so that actual AUX registration doesn't happen
>   until we have an associated DRM device
> * Clean-up any obvious errors in drivers we find along the way
> * Add a backpointer to the respective drm_device for an AUX channel in
>   drm_dp_aux.drm_dev, and hook it up in every driver with an AUX channel
>   across the tree
> * Add a new ratelimited print helper we'll need for converting the DP
>   helpers over to using the new DRM printk helpers
> * Fix any inconsistencies with logging in drm_dp_helper.c so we always
>   have the aux channel name printed
> * Prepare the various DP helpers so they can find the correct drm_device
>   to use for logging
> * And finally, convert all of the DP helpers over to using drm_dbg_*()
>   and drm_err().
>
> Series-wide changes in v2:
> * Address most checkpatch issues ('most' as in all except for one line
>   going two chars over 100 in "drm/dp_mst: Pass drm_dp_mst_topology_mgr
>   to drm_dp_get_vc_payload_bw()" as this was the style in use
>   previously, and 2 chars over the limit looks nicer then trying to
>   line-wrap this
> * Don't rewrap comments

For anything touching i915, and for merging via whichever tree or branch
seems best,

Acked-by: Jani Nikula 

That said, gut feeling says there will be conflicts before latest
drm-misc-next and drm-intel-next have been merged to drm-next, and
drm-next has been backmerged to drm-misc-next and drm-intel-next.

It just might be a good idea to wait for those (as well as other driver
feature pulls) to settle, do a topic branch with a common ancestor
between drm-next and drm-misc-next, apply there, merge the topic branch
to drm-misc-next, and let all drivers merge the topic branch as
needed. Due to the timing, otherwise we might have to carry the
conflicts for quite a while.

BR,
Jani.


>
> Lyude Paul (20):
>   drm/dp: Fixup kernel docs for struct drm_dp_aux
>   drm/tegra: Don't register DP AUX channels before connectors
>   drm/bridge/cdns-mhdp8546: Register DP aux channel with userspace
>   drm/nouveau/kms/nv50-: Move AUX adapter reg to connector late
> register/early unregister
>   drm/dp: Add backpointer to drm_device in drm_dp_aux
>   drm/dp: Clarify DP AUX registration time
>   drm/print: Fixup DRM_DEBUG_KMS_RATELIMITED()
>   drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay()
>   drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay()
>   drm/dp: Always print aux channel name in logs
>   drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_detect()
>   drm/dp_dual_mode: Pass drm_device to
> drm_dp_dual_mode_set_tmds_output()
>   drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_max_tmds_clock()
>   drm/dp_dual_mode: Pass drm_device to
> drm_dp_dual_mode_get_tmds_output()
>   drm/dp_dual_mode: Pass drm_device to drm_lspcon_(get|set)_mode()
>   drm/dp_mst: Pass drm_dp_mst_topology_mgr to drm_dp_get_vc_payload_bw()
>   drm/dp: Convert drm_dp_helper.c to using drm_err/drm_dbg_*()
>   drm/dp_dual_mode: Convert drm_dp_dual_mode_helper.c to using
> drm_err/drm_dbg_kms()
>   drm/dp_mst: Drop DRM_ERROR() on kzalloc() fail in
> drm_dp_mst_handle_up_req()
>   drm/dp_mst: Convert drm_dp_mst_topology.c to drm_err()/drm_dbg*()
>
>  drivers/gpu/drm/amd/amdgpu/atombios_dp.c  |   5 +-
>  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |   1 +
>  .../drm/bridge/analogix/analogix-anx6345.c|   1 +
>  .../drm/bridge/analogix/analogix-anx78xx.c|   1 +
>  .../drm/bridge/analogix/analogix_dp_core.c|   1 +
>  .../drm/bridge/cadence/cdns-mhdp8546-core.c   |  12 +-
>  drivers/gpu/drm/bridge/tc358767.c |   1 +
>  drivers/gpu/drm/bridge/ti-sn65dsi86.c |   1 +
>  drivers/gpu/drm/drm_dp_aux_dev.c  |   6 +
>  drivers/gpu/drm/drm_dp_dual_mode_helper.c |  68 ++--
>  drivers/gpu/drm/drm_dp_helper.c   | 181 +
>  drivers/gpu/drm/drm_dp_mst_topology.c | 381 +-
>  drivers/gpu/drm/i915/display/intel_dp_aux.c   |   1 +
>  .../drm/i915/display/intel_dp_link_training.c |   6 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |   3 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c |   7 +-
>  drivers/gpu/drm/i915/display/intel_lspcon.c   |  17 +-
>  drivers/gpu/drm/msm/dp/dp_ctrl.c  |   6 +-
>  drivers/gpu/drm/msm/edp/edp.h |   3 +-
>  drivers/gpu/drm/msm/edp/edp_aux.c |   5 +-
>  drivers/gpu/drm/msm/edp/edp_ctrl.c|   8 +-
>  drivers/gpu/drm/nouveau/nouveau_connector.c   |  27 +-
>  

Re: [PATCH v2 05/20] drm/dp: Add backpointer to drm_device in drm_dp_aux

[Jani Nikula]

On Fri, 26 Mar 2021, Lyude Paul  wrote:
>   * The @dev field should be set to a pointer to the device that implements 
> the
> - * AUX channel.
> + * AUX channel. As well, the @drm_dev field should be set to the _device
> + * that will be using this AUX channel as early as possible. For many 
> graphics
> + * drivers this should happen before drm_dp_aux_init(), however it's 
> perfectly
> + * fine to set this field later so long as it's assigned before calling
> + * drm_dp_aux_register().

Perhaps add a follow-up patch to actually ensure this is the case in
drm_dp_aux_register()?

>   *
>   * The @name field may be used to specify the name of the I2C adapter. If 
> set to
>   * %NULL, dev_name() of @dev will be used.
> @@ -1877,6 +1883,7 @@ struct drm_dp_aux {
>   const char *name;
>   struct i2c_adapter ddc;
>   struct device *dev;
> + struct drm_device *drm_dev;

Bikeshed, I would probably have called it just drm for brevity, but no
strong feelings.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 09/34] drm/amdkfd: map svm range to GPUs

[kernel test robot]

Hi Felix,

I love your patch! Perhaps something to improve:

[auto build test WARNING on next-20210331]
[cannot apply to drm-intel/for-linux-next drm-tip/drm-tip 
drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master 
drm/drm-next v5.12-rc5 v5.12-rc4 v5.12-rc3 v5.12-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
base:7a43c78d0573e00456b033e2b9a895b89464
config: x86_64-randconfig-a011-20210401 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# 
https://github.com/0day-ci/linux/commit/bb9c90022dd6afd456d4b40a20d007e57efc35ed
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
git checkout bb9c90022dd6afd456d4b40a20d007e57efc35ed
# save the attached .config to linux build tree
make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:167:6: warning: no previous 
prototype for 'svm_range_dma_unmap' [-Wmissing-prototypes]
 167 | void svm_range_dma_unmap(struct device *dev, dma_addr_t *dma_addr,
 |  ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:599:6: warning: no previous 
prototype for 'svm_range_add_child' [-Wmissing-prototypes]
 599 | void svm_range_add_child(struct svm_range *prange, struct mm_struct 
*mm,
 |  ^~~
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:795:5: warning: no previous 
>> prototype for 'svm_range_reserve_bos' [-Wmissing-prototypes]
 795 | int svm_range_reserve_bos(struct svm_validate_context *ctx)
 | ^
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:849:6: warning: no previous 
>> prototype for 'svm_range_unreserve_bos' [-Wmissing-prototypes]
 849 | void svm_range_unreserve_bos(struct svm_validate_context *ctx)
 |  ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:967:19: warning: no previous 
prototype for 'svm_range_clone' [-Wmissing-prototypes]
 967 | struct svm_range *svm_range_clone(struct svm_range *old)
 |   ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:1222:1: warning: no previous 
prototype for 'svm_range_add_list_work' [-Wmissing-prototypes]
1222 | svm_range_add_list_work(struct svm_range_list *svms, struct 
svm_range *prange,
 | ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:1244:6: warning: no previous 
prototype for 'schedule_deferred_list_work' [-Wmissing-prototypes]
1244 | void schedule_deferred_list_work(struct svm_range_list *svms)
 |  ^~~


vim +/svm_range_reserve_bos +795 drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c

   794  
 > 795  int svm_range_reserve_bos(struct svm_validate_context *ctx)
   796  {
   797  struct kfd_process_device *pdd;
   798  struct amdgpu_device *adev;
   799  struct amdgpu_vm *vm;
   800  uint32_t gpuidx;
   801  int r;
   802  
   803  INIT_LIST_HEAD(>validate_list);
   804  for_each_set_bit(gpuidx, ctx->bitmap, MAX_GPU_INSTANCE) {
   805  pdd = kfd_process_device_from_gpuidx(ctx->process, 
gpuidx);
   806  if (!pdd) {
   807  pr_debug("failed to find device idx %d\n", 
gpuidx);
   808  return -EINVAL;
   809  }
   810  adev = (struct amdgpu_device *)pdd->dev->kgd;
   811  vm = pdd->vm;
   812  
   813  ctx->tv[gpuidx].bo = >root.base.bo->tbo;
   814  ctx->tv[gpuidx].num_shared = 4;
   815  list_add(>tv[gpuidx].head, >validate_list);
   816  }
   817  
   818  r = ttm_eu_reserve_buffers(>ticket, >validate_list,
   819 ctx->intr, NULL);
   820  if (r) {
   821  pr_debug("failed %d to reserve bo\n", r);
   822  return r;
   823  }
   824  
   825  for_each_set_bit(gpuidx, ctx->bitmap, MAX_GPU_INSTANCE) {
   826  pdd = kfd_process_device_from_gpuidx(ctx->process, 
gpuidx);
   827  if (!pdd) {
   828  pr_debug("failed to find device idx %d\n", 
gpuidx);
   829  r = -EINVAL;
   830 

Re: [PATCH] drm/ttm: add __user annotation in radeon_ttm_vram_read

[Christian König]

Am 24.10.20 um 02:47 schrieb Rasmus Villemoes:

Keep sparse happy by preserving the __user annotation when casting.

Reported-by: kernel test robot 
Signed-off-by: Rasmus Villemoes 


Reviewed-by: Christian König 

Going over old patches and stumbled over that once.

Alex did you missed to pick it up?

Regards,
Christian.


---

kernel test robot has already started spamming me due to 9c5743dff. If
I don't fix those warnings I'll keep getting those emails for
months, so let me do the easy ones.


  drivers/gpu/drm/radeon/radeon_ttm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
b/drivers/gpu/drm/radeon/radeon_ttm.c
index 36150b7f31a90aa1eece..ecfe88b0a35d8f317712 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -1005,7 +1005,7 @@ static ssize_t radeon_ttm_vram_read(struct file *f, char 
__user *buf,
value = RREG32(RADEON_MM_DATA);
spin_unlock_irqrestore(>mmio_idx_lock, flags);
  
-		r = put_user(value, (uint32_t *)buf);

+   r = put_user(value, (uint32_t __user *)buf);
if (r)
return r;
  


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Re: [PATCH] drm/amd/display: Try YCbCr420 color when YCbCr444 fails

[Werner Sembach]

Am 29.03.21 um 17:28 schrieb Alex Deucher:
> Applied.  Thanks!
>
> Alex
Nice to hear that ^^

One quick question: Here do I find the amd-gfx dev branch?

Kind regards,

Werner Sembach
>
> On Fri, Mar 26, 2021 at 10:59 AM Harry Wentland  
> wrote:
>>
>>
>> On 2021-03-24 4:23 p.m., Alex Deucher wrote:
>>> On Wed, Mar 17, 2021 at 11:25 AM Werner Sembach  
>>> wrote:
 When encoder validation of a display mode fails, retry with less bandwidth
 heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups
 to support 4k60Hz output, which previously failed silently.

 On some setups, while the monitor and the gpu support display modes with
 pixel clocks of up to 600MHz, the link encoder might not. This prevents
 YCbCr444 and RGB encoding for 4k60Hz, but YCbCr420 encoding might still be
 possible. However, which color mode is used is decided before the link
 encoder capabilities are checked. This patch fixes the problem by retrying
 to find a display mode with YCbCr420 enforced and using it, if it is
 valid.

 Signed-off-by: Werner Sembach 
 Cc: 
>>>
>>> This seems reasonable to me.  Harry, Leo, Any objections?
>>>
>> Looks good to me.
>>
>> Reviewed-by: Harry Wentland 
>>
>> Harry
>>
>>> Alex
>>>
 ---

  From c9398160caf4ff20e63b8ba3a4366d6ef95c4ac3 Mon Sep 17 00:00:00 2001
 From: Werner Sembach 
 Date: Wed, 17 Mar 2021 12:52:22 +0100
 Subject: [PATCH] Retry forcing YCbCr420 color on failed encoder validation

 ---
   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
   1 file changed, 9 insertions(+)

 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
 b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
 index 961abf1cf040..2d16389b5f1e 100644
 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
 +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
 @@ -5727,6 +5727,15 @@ create_validate_stream_for_sink(struct 
 amdgpu_dm_connector *aconnector,

  } while (stream == NULL && requested_bpc >= 6);

 +   if (dc_result == DC_FAIL_ENC_VALIDATE && 
 !aconnector->force_yuv420_output) {
 +   DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
 +
 +   aconnector->force_yuv420_output = true;
 +   stream = create_validate_stream_for_sink(aconnector, 
 drm_mode,
 +   dm_state, old_stream);
 +   aconnector->force_yuv420_output = false;
 +   }
 +
  return stream;
   }

 --
 2.25.1

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RE: [PATCH Review 1/1] drm/amdgpu: support sdma error injection

[Li, Dennis]

[AMD Official Use Only - Internal Distribution Only]

Reivewed-by: Dennis Li 

-Original Message-
From: Stanley.Yang  
Sent: Thursday, April 1, 2021 7:14 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Clements, John 
; Li, Dennis ; Yang, Stanley 

Subject: [PATCH Review 1/1] drm/amdgpu: support sdma error injection

Signed-off-by: Stanley.Yang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 0e16683876aa..d9d292c79cfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -927,6 +927,7 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
ret = -EINVAL;
break;
case AMDGPU_RAS_BLOCK__UMC:
+   case AMDGPU_RAS_BLOCK__SDMA:
case AMDGPU_RAS_BLOCK__MMHUB:
case AMDGPU_RAS_BLOCK__PCIE_BIF:
ret = psp_ras_trigger_error(>psp, _info);
-- 
2.17.1
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Re: [PATCH 07/34] drm/amdkfd: deregister svm range

[kernel test robot]

Hi Felix,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20210331]
[cannot apply to drm-intel/for-linux-next drm-tip/drm-tip 
drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master 
drm/drm-next v5.12-rc5 v5.12-rc4 v5.12-rc3 v5.12-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
base:7a43c78d0573e00456b033e2b9a895b89464
config: x86_64-randconfig-a011-20210401 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# 
https://github.com/0day-ci/linux/commit/545d8003c8da8397f0fa9657f97ed67441dd1087
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
git checkout 545d8003c8da8397f0fa9657f97ed67441dd1087
# save the attached .config to linux build tree
make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:417:6: warning: no previous 
>> prototype for 'svm_range_add_child' [-Wmissing-prototypes]
 417 | void svm_range_add_child(struct svm_range *prange, struct mm_struct 
*mm,
 |  ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:511:19: warning: no previous 
prototype for 'svm_range_clone' [-Wmissing-prototypes]
 511 | struct svm_range *svm_range_clone(struct svm_range *old)
 |   ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:766:1: warning: no previous 
prototype for 'svm_range_add_list_work' [-Wmissing-prototypes]
 766 | svm_range_add_list_work(struct svm_range_list *svms, struct 
svm_range *prange,
 | ^~~
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:788:6: warning: no previous 
prototype for 'schedule_deferred_list_work' [-Wmissing-prototypes]
 788 | void schedule_deferred_list_work(struct svm_range_list *svms)
 |  ^~~


vim +/svm_range_add_child +417 drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c

   416  
 > 417  void svm_range_add_child(struct svm_range *prange, struct mm_struct *mm,
   418   struct svm_range *pchild, enum 
svm_work_list_ops op)
   419  {
   420  pr_debug("add child 0x%p [0x%lx 0x%lx] to prange 0x%p child 
list %d\n",
   421   pchild, pchild->start, pchild->last, prange, op);
   422  
   423  pchild->work_item.mm = mm;
   424  pchild->work_item.op = op;
   425  list_add_tail(>child_list, >child_list);
   426  }
   427  

---
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[PATCH Review 1/1] drm/amdgpu: support sdma error injection

[Stanley . Yang]

Signed-off-by: Stanley.Yang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 0e16683876aa..d9d292c79cfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -927,6 +927,7 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
ret = -EINVAL;
break;
case AMDGPU_RAS_BLOCK__UMC:
+   case AMDGPU_RAS_BLOCK__SDMA:
case AMDGPU_RAS_BLOCK__MMHUB:
case AMDGPU_RAS_BLOCK__PCIE_BIF:
ret = psp_ras_trigger_error(>psp, _info);
-- 
2.17.1

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Re: [PATCH 03/34] drm/amdkfd: register svm range

[kernel test robot]

Hi Felix,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20210331]
[cannot apply to drm-intel/for-linux-next drm-tip/drm-tip 
drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master 
drm/drm-next v5.12-rc5 v5.12-rc4 v5.12-rc3 v5.12-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
base:7a43c78d0573e00456b033e2b9a895b89464
config: x86_64-randconfig-a011-20210401 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# 
https://github.com/0day-ci/linux/commit/55f4d035262443207d455427967806e33fb85c06
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Felix-Kuehling/Add-HMM-based-SVM-memory-manager-to-KFD-v3/20210401-122712
git checkout 55f4d035262443207d455427967806e33fb85c06
# save the attached .config to linux build tree
make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:380:19: warning: no previous 
>> prototype for 'svm_range_clone' [-Wmissing-prototypes]
 380 | struct svm_range *svm_range_clone(struct svm_range *old)
 |   ^~~


vim +/svm_range_clone +380 drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c

   379  
 > 380  struct svm_range *svm_range_clone(struct svm_range *old)
   381  {
   382  struct svm_range *new;
   383  
   384  new = svm_range_new(old->svms, old->start, old->last);
   385  if (!new)
   386  return NULL;
   387  
   388  new->flags = old->flags;
   389  new->preferred_loc = old->preferred_loc;
   390  new->prefetch_loc = old->prefetch_loc;
   391  new->actual_loc = old->actual_loc;
   392  new->granularity = old->granularity;
   393  bitmap_copy(new->bitmap_access, old->bitmap_access, 
MAX_GPU_INSTANCE);
   394  bitmap_copy(new->bitmap_aip, old->bitmap_aip, MAX_GPU_INSTANCE);
   395  
   396  return new;
   397  }
   398  

---
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RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov

[Liu, Monk]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Monk Liu 

Thanks 

--
Monk Liu | Cloud-GPU Core team
--

-Original Message-
From: Deng, Emily  
Sent: Thursday, April 1, 2021 2:04 PM
To: Liu, Monk 
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov

[AMD Official Use Only - Internal Distribution Only]

Hi Monk,
 Could you help to review this patch?

Best wishes
Emily Deng

>-Original Message-
>From: Deng, Emily 
>Sent: Wednesday, March 31, 2021 5:02 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Ping ..
>
>>-Original Message-
>>From: Emily Deng 
>>Sent: Tuesday, March 30, 2021 5:43 PM
>>To: amd-gfx@lists.freedesktop.org
>>Cc: Deng, Emily 
>>Subject: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>>
>>From: "Emily.Deng" 
>>
>>For vf assigned to guest VM, after FLR, the msix table will be reset.
>>As the flr is done on host driver. The qemu and vfio driver don't know 
>>this, and the msix is still enable from qemu and vfio driver side.
>>So if want to  re-setup the msix table, first need to disable and 
>>re-enable the msix from guest VM side or the qemu will do nothing as 
>>it thought the msix is already enabled.
>>
>>v2:
>>Change name with amdgpu_irq prefix, remove #ifdef.
>>
>>Signed-off-by: Emily.Deng 
>>---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++
>> 1 file changed, 14 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>index 03412543427a..3045f52e613d 100644
>>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>@@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device
>>*adev)
>> return true;
>> }
>>
>>+static void amdgpu_irq_restore_msix(struct amdgpu_device *adev) {
>>+u16 ctrl;
>>+
>>+pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
>>PCI_MSIX_FLAGS, );
>>+ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
>>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>>PCI_MSIX_FLAGS, ctrl);
>>+ctrl |= PCI_MSIX_FLAGS_ENABLE;
>>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap + 
>>+PCI_MSIX_FLAGS, ctrl); }
>>+
>> /**
>>  * amdgpu_irq_init - initialize interrupt handling
>>  *
>>@@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
>>amdgpu_device *adev)  {
>> int i, j, k;
>>
>>+if (amdgpu_sriov_vf(adev))
>>+amdgpu_irq_restore_msix(adev);
>>+
>> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {  if
>>(!adev->irq.client[i].sources)  continue;
>>--
>>2.25.1
>

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Re: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov

[Nirmoy]

Acked-by: Nirmoy Das

On 3/30/21 11:42 AM, Emily Deng wrote:

From: "Emily.Deng" 

For vf assigned to guest VM, after FLR, the msix table will be reset.
As the flr is done on host driver. The qemu and vfio driver don't know
this, and the msix is still enable from qemu and vfio driver side.
So if want to  re-setup the msix table, first need to disable and
re-enable the msix from guest VM side or the qemu will do nothing as
it thought the msix is already enabled.

v2:
Change name with amdgpu_irq prefix, remove #ifdef.

Signed-off-by: Emily.Deng 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++
  1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 03412543427a..3045f52e613d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev)
return true;
  }
  
+static void amdgpu_irq_restore_msix(struct amdgpu_device *adev)

+{
+   u16 ctrl;
+
+   pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, 
);
+   ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
+   pci_write_config_word(adev->pdev, adev->pdev->msix_cap + 
PCI_MSIX_FLAGS, ctrl);
+   ctrl |= PCI_MSIX_FLAGS_ENABLE;
+   pci_write_config_word(adev->pdev, adev->pdev->msix_cap + 
PCI_MSIX_FLAGS, ctrl);
+}
+
  /**
   * amdgpu_irq_init - initialize interrupt handling
   *
@@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct 
amdgpu_device *adev)
  {
int i, j, k;
  
+	if (amdgpu_sriov_vf(adev))

+   amdgpu_irq_restore_msix(adev);
+
for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
if (!adev->irq.client[i].sources)
continue;

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Re: Interlaced resolutions hang the desktop

[Alberto Salvia Novella]

Restarting the *display manager* service works and, more importantly, makes
the bug no longer reproducible.

Restarting the *window manager* doesn't work.

*Changing* display manager makes the bug still reproducible.

Maybe this is due to xorg-server, isn't it?

On Wed, 31 Mar 2021 at 16:55, Christian König <
ckoenig.leichtzumer...@gmail.com> wrote:

> Well the hardware is working fine as far as I can see.
>
> Can you try to kill the X server over SSH and see if you then get some
> screen update?
>
> Regards,
> Christian.
>
> Am 31.03.21 um 16:52 schrieb Alberto Salvia Novella:
>
> Output
> 
> .
>
> On Wed, 31 Mar 2021 at 16:36, Christian König 
> wrote:
>
>> Mhm strange.
>>
>> Can you get me the output of "sudo cat
>> /sys/kernel/debug/dri/0/radeon_fence_info" when the problem happens?
>>
>> Thanks,
>> Christian.
>>
>> Am 31.03.21 um 16:33 schrieb Alberto Salvia Novella:
>>
>> - The computer still replies to *ping*.
>> - The *journal* shows no errors, but a few warnings
>> 
>> .
>> - The *mouse* doesn't freeze.
>>
>> On Wed, 31 Mar 2021 at 10:09, Christian König 
>> wrote:
>>
>>> Can you access the system over the network and see if there is anything
>>> in the system log?
>>>
>>> It sounds like the display stack has crashed, but when the sound keeps
>>> playing the system is most likely still responsive over network.
>>>
>>> Thanks,
>>> Christian.
>>>
>>> Am 31.03.21 um 10:05 schrieb Alberto Salvia Novella:
>>>
>>> What happens is this simple: after a few minutes, about 6 or so, the
>>> entire content of the screen stays still. In some minor situations only the
>>> applications panel of KDE Plasma.
>>>
>>> If music is playing it continues playing, so only graphics are hung. Yet
>>> in most cases the power button won't shut down the computer, as it usually
>>> does.
>>>
>>> At least this is the case using kwin on x11, and not on wayland. It only
>>> happens on "radeon" and not on Intel or "radeonhd".
>>>
>>> On Wed, 31 Mar 2021 at 09:48, Christian König 
>>> wrote:
>>>
 Correct, but a TV is intended for videos only. That's why it implements
 only the lower HDMI standard.

 Interlaced transmits only halve the lines with each frame, so a 60Hz
 mode effectively either becomes a 30Hz mode, halving the vertical
 resolution or adaptive motion compensated which the know visual artifacts.
 Depending on what the deinterlacing setting on your TV is.

 You could just add a progressive 1920x540@60 or 1920x1080@30 mode
 manually and would have the same effect with probably better quality. See
 https://de.wikipedia.org/wiki/Deinterlacing
 
 for reference.

 If you can give us some more information what is happening when the
 system freeze we could try to narrow this down, but we can't spend much
 time on a very specific use case in a driver which is in maintenance mode.

 Regards,
 Christian.

 Am 31.03.21 um 09:21 schrieb Alberto Salvia Novella:

 24fps is intended for video only. Anything interactive at 24fps, as
 just moving the mouse around, is extremely choppy.

 No way anyone would prefer that over an interlaced resolution or a
 lower resolution. That is, by far, the worst option.

 Just try it on your screen, set it to 24Hz or alike, and tell me your
 experience. You can't even tell where the mouse is going to go.

 On Wed, 31 Mar 2021 at 08:44, Christian König 
 wrote:

> Hi Alberto,
>
> well a frame rate of 24Hz is perfectly reasonable for a TV and desktop
> usage.
>
> This is probably caused by the TVs limited HDMI bandwidth and a
> refresh rate of 30/25 Hz for the interlaced mode isn't much better either.
>
> Regards,
> Christian.
>
> Am 30.03.21 um 22:59 schrieb Alberto Salvia Novella:
>
> The frame-rate at 24Hz is extremely poor for normal desktop usage.
>
> If the highest resolution, aka 1080p, uses that refresh rate then the
> desktop will default to that frame-rate.
>
> Other 

RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Hi Monk,
 Could you help to review this patch?

Best wishes
Emily Deng

>-Original Message-
>From: Deng, Emily 
>Sent: Wednesday, March 31, 2021 5:02 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: RE: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Ping ..
>
>>-Original Message-
>>From: Emily Deng 
>>Sent: Tuesday, March 30, 2021 5:43 PM
>>To: amd-gfx@lists.freedesktop.org
>>Cc: Deng, Emily 
>>Subject: [PATCH] drm/amdgpu: Toggle msix after FLR for sriov
>>
>>From: "Emily.Deng" 
>>
>>For vf assigned to guest VM, after FLR, the msix table will be reset.
>>As the flr is done on host driver. The qemu and vfio driver don't know
>>this, and the msix is still enable from qemu and vfio driver side.
>>So if want to  re-setup the msix table, first need to disable and
>>re-enable the msix from guest VM side or the qemu will do nothing as it
>>thought the msix is already enabled.
>>
>>v2:
>>Change name with amdgpu_irq prefix, remove #ifdef.
>>
>>Signed-off-by: Emily.Deng 
>>---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 ++
>> 1 file changed, 14 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>index 03412543427a..3045f52e613d 100644
>>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>@@ -277,6 +277,17 @@ static bool amdgpu_msi_ok(struct amdgpu_device
>>*adev)
>> return true;
>> }
>>
>>+static void amdgpu_irq_restore_msix(struct amdgpu_device *adev) {
>>+u16 ctrl;
>>+
>>+pci_read_config_word(adev->pdev, adev->pdev->msix_cap +
>>PCI_MSIX_FLAGS, );
>>+ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
>>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>>PCI_MSIX_FLAGS, ctrl);
>>+ctrl |= PCI_MSIX_FLAGS_ENABLE;
>>+pci_write_config_word(adev->pdev, adev->pdev->msix_cap +
>>+PCI_MSIX_FLAGS, ctrl); }
>>+
>> /**
>>  * amdgpu_irq_init - initialize interrupt handling
>>  *
>>@@ -558,6 +569,9 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
>>amdgpu_device *adev)  {
>> int i, j, k;
>>
>>+if (amdgpu_sriov_vf(adev))
>>+amdgpu_irq_restore_msix(adev);
>>+
>> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {  if
>>(!adev->irq.client[i].sources)  continue;
>>--
>>2.25.1
>

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RE: [PATCH 4/6] drm/amdgpu: Disable fetch discovery data from vram for navi12 sriov

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Hi Monk,
 Could you help to review this patch?

Best wishes
Emily Deng

>-Original Message-
>From: Deng, Emily 
>Sent: Wednesday, March 31, 2021 5:01 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: RE: [PATCH 4/6] drm/amdgpu: Disable fetch discovery data from
>vram for navi12 sriov
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Ping .
>
>>-Original Message-
>>From: Emily Deng 
>>Sent: Tuesday, March 30, 2021 12:42 PM
>>To: amd-gfx@lists.freedesktop.org
>>Cc: Deng, Emily 
>>Subject: [PATCH 4/6] drm/amdgpu: Disable fetch discovery data from vram
>>for
>>navi12 sriov
>>
>>To fix the board disappear issue.
>>
>>Signed-off-by: Emily Deng 
>>---
>> drivers/gpu/drm/amd/amdgpu/nv.c | 4 
>> 1 file changed, 4 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>>b/drivers/gpu/drm/amd/amdgpu/nv.c index 46d4bbabce75..48dc171bc759
>>100644
>>--- a/drivers/gpu/drm/amd/amdgpu/nv.c
>>+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>>@@ -693,6 +693,10 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
>> adev->nbio.funcs = _v2_3_funcs;
>> adev->nbio.hdp_flush_reg = _v2_3_hdp_flush_reg;
>> }
>>+
>>+if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_NAVI12)
>>+amdgpu_discovery = 0;
>>+
>> adev->hdp.funcs = _v5_0_funcs;
>>
>> if (adev->asic_type >= CHIP_SIENNA_CICHLID)
>>--
>>2.25.1
>

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RE: [PATCH 2/6] drm/amdgpu: Correct the irq numbers for virtual ctrc

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Hi Monk,
 Could you help to review this patch?

Best wishes
Emily Deng

>-Original Message-
>From: Deng, Emily 
>Sent: Wednesday, March 31, 2021 5:01 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: RE: [PATCH 2/6] drm/amdgpu: Correct the irq numbers for virtual ctrc
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Ping..
>
>>-Original Message-
>>From: Emily Deng 
>>Sent: Tuesday, March 30, 2021 12:42 PM
>>To: amd-gfx@lists.freedesktop.org
>>Cc: Deng, Emily 
>>Subject: [PATCH 2/6] drm/amdgpu: Correct the irq numbers for virtual
>>ctrc
>>
>>Set the num_types equal to the enabled num_crtc.
>>
>>Signed-off-by: Emily Deng 
>>---
>> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>>b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>>index 5c11144da051..c03a83a2b7cd 100644
>>--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>>+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>>@@ -768,7 +768,7 @@ static const struct amdgpu_irq_src_funcs
>>dce_virtual_crtc_irq_funcs = {
>>
>> static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)  {
>>-adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1;
>>+adev->crtc_irq.num_types = adev->mode_info.num_crtc;
>> adev->crtc_irq.funcs = _virtual_crtc_irq_funcs;  }
>>
>>--
>>2.25.1
>

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RE: [PATCH 1/6] drm/amdgpu: Disable vcn decode ring for sriov navi12

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Hi Monk,
 Could you help to review this patch?

Best wishes
Emily Deng


>-Original Message-
>From: Deng, Emily 
>Sent: Wednesday, March 31, 2021 5:01 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Cc: Min, Frank 
>Subject: RE: [PATCH 1/6] drm/amdgpu: Disable vcn decode ring for sriov
>navi12
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Ping..
>
>>-Original Message-
>>From: Emily Deng 
>>Sent: Tuesday, March 30, 2021 12:42 PM
>>To: amd-gfx@lists.freedesktop.org
>>Cc: Deng, Emily ; Min, Frank 
>>Subject: [PATCH 1/6] drm/amdgpu: Disable vcn decode ring for sriov
>>navi12
>>
>>Since vcn decoding ring is not required, so just disable it.
>>
>>Signed-off-by: Frank.Min 
>>Signed-off-by: Emily Deng 
>>---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  4 +++-
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c   | 29 -
>> 2 files changed, 17 insertions(+), 16 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>index 8844f650b17f..5d5c41c9d5aa 100644
>>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>@@ -427,7 +427,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device
>>*adev,  if (adev->uvd.harvest_config & (1 << i))  continue;
>>
>>-if (adev->vcn.inst[i].ring_dec.sched.ready)
>>+if (adev->vcn.inst[i].ring_dec.sched.ready || (adev->asic_type ==
>>+CHIP_NAVI12 &&
>>+amdgpu_sriov_vf(adev)))
>> ++num_rings;
>> }
>> ib_start_alignment = 16;
>>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>index 116b9643d5ba..e4b61f3a45fb 100644
>>--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>@@ -220,21 +220,20 @@ static int vcn_v2_0_hw_init(void *handle)  {
>>struct amdgpu_device *adev = (struct amdgpu_device *)handle;  struct
>>amdgpu_ring *ring = >vcn.inst->ring_dec; -int i, r;
>>+int i, r = -1;
>>
>> adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
>>  ring->doorbell_index, 0);
>>
>>-if (amdgpu_sriov_vf(adev))
>>+if (amdgpu_sriov_vf(adev)) {
>> vcn_v2_0_start_sriov(adev);
>>-
>>-r = amdgpu_ring_test_helper(ring);
>>-if (r)
>>-goto done;
>>-
>>-//Disable vcn decode for sriov
>>-if (amdgpu_sriov_vf(adev))
>>-ring->sched.ready = false;
>>+if (adev->asic_type == CHIP_NAVI12)
>>+ring->sched.ready = false;
>>+} else {
>>+r = amdgpu_ring_test_helper(ring);
>>+if (r)
>>+goto done;
>>+}
>>
>> for (i = 0; i < adev->vcn.num_enc_rings; ++i) {  ring =
>>>vcn.inst->ring_enc[i]; @@ -245,8 +244,11 @@ static int
>>vcn_v2_0_hw_init(void *handle)
>>
>> done:
>> if (!r)
>>-DRM_INFO("VCN decode and encode initialized successfully(under
>>%s).\n", -(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG
>Mode":"SPG
>>Mode");
>>+DRM_INFO("VCN %s encode initialized
>>successfully(under %s).\n",
>>+(adev->asic_type == CHIP_NAVI12 &&
>>+amdgpu_sriov_vf(adev))?"":"decode and", (adev->pg_flags &
>>+AMD_PG_SUPPORT_VCN_DPG)?"DPG
>>Mode":"SPG Mode");
>>
>> return r;
>> }
>>@@ -1719,9 +1721,6 @@ int vcn_v2_0_dec_ring_test_ring(struct
>>amdgpu_ring *ring)
>> unsigned i;
>> int r;
>>
>>-if (amdgpu_sriov_vf(adev))
>>-return 0;
>>-
>> WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);  r =
>>amdgpu_ring_alloc(ring, 4);  if (r)
>>--
>>2.25.1
>

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RE: [PATCH 4/4] drm/amdgpu: indirect register access for nv12 sriov

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Series Reviewed-by: Emily.Deng 

>-Original Message-
>From: amd-gfx  On Behalf Of Peng
>Ju Zhou
>Sent: Wednesday, March 31, 2021 1:20 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Zhao, Jiange 
>Subject: [PATCH 4/4] drm/amdgpu: indirect register access for nv12 sriov
>
>1. expand rlcg interface for gc & mmhub indirect access 2. add rlcg interface
>for no kiq
>
>Signed-off-by: Peng Ju Zhou 
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h|   3 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 131 ++---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |   2 +-
> drivers/gpu/drm/amd/amdgpu/soc15_common.h  |  75 ++--
> 5 files changed, 150 insertions(+), 63 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>index 060d0ae99453..438e2f732377 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>@@ -490,7 +490,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct
>amdgpu_device *adev,
> adev->gfx.rlc.funcs &&
> adev->gfx.rlc.funcs->is_rlcg_access_range) {
> if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
>-return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v);
>+return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0);
> } else {
> writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
> }
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
>index aeaaae713c59..4fc2ce8ce8ab 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
>@@ -127,7 +127,8 @@ struct amdgpu_rlc_funcs {
> void (*reset)(struct amdgpu_device *adev);
> void (*start)(struct amdgpu_device *adev);
> void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned
>vmid);
>-void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v);
>+void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
>flag);
>+u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 flag);
> bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t
>reg);  };
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>index b4fd0394cd08..85a6a10e048f 100644
>--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>@@ -177,6 +177,11 @@
> #define mmGC_THROTTLE_CTRL_Sienna_Cichlid  0x2030
> #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
>
>+#define GFX_RLCG_GC_WRITE_OLD(0x8 << 28)
>+#define GFX_RLCG_GC_WRITE(0x0 << 28)
>+#define GFX_RLCG_GC_READ(0x1 << 28)
>+#define GFX_RLCG_MMHUB_WRITE(0x2 << 28)
>+
> MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
> MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
> MODULE_FIRMWARE("amdgpu/navi10_me.bin");
>@@ -1422,38 +1427,127 @@ static const struct soc15_reg_golden
>golden_settings_gc_10_1_2[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x,
>0x0080)  };
>
>-static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
>+static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset,
>+uint32_t *flag, bool write) {
>+/* always programed by rlcg, only for gc */
>+if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
>+offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
>+offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
>+offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
>+offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
>+offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
>+if (!amdgpu_sriov_reg_indirect_gc(adev))
>+*flag = GFX_RLCG_GC_WRITE_OLD;
>+else
>+*flag = write ? GFX_RLCG_GC_WRITE :
>GFX_RLCG_GC_READ;
>+
>+return true;
>+}
>+
>+/* currently support gc read/write, mmhub write */
>+if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) &&
>+offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) {
>+if (amdgpu_sriov_reg_indirect_gc(adev))
>+*flag = write ? GFX_RLCG_GC_WRITE :
>GFX_RLCG_GC_READ;
>+else
>+return false;
>+} else {
>+if (amdgpu_sriov_reg_indirect_mmhub(adev))
>+*flag = GFX_RLCG_MMHUB_WRITE;
>+else
>+return false;
>+}
>+
>+return true;
>+}
>+
>+static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32
>+v, uint32_t flag)
> {
> static void *scratch_reg0;
> static void *scratch_reg1;
>+static void *scratch_reg2;
>+static void *scratch_reg3;
> static void *spare_int;
>+static uint32_t grbm_cntl;
>+static uint32_t grbm_idx;
> uint32_t i = 0;
> uint32_t retries = 5;
>+u32 ret = 0;
>+
>+scratch_reg0 = adev->rmmio +
>+   (adev-
>>reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] +
>mmSCRATCH_REG0) * 4;
>+scratch_reg1 = adev->rmmio +
>+   (adev-
>>reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] +
>mmSCRATCH_REG1) * 4;
>+scratch_reg2 = adev->rmmio +
>+   (adev-
>>reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] +
>mmSCRATCH_REG2) * 4;
>+scratch_reg3 = adev->rmmio +
>+