[PATCH 7/8] drm/amdgpu: Change GC register access from MMIO to RLCG
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index b1d5b08e4f06..0265a082d791 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5016,17 +5016,17 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device
*adev)
}
}
- tmp = RREG32_SOC15(GC, 0,
mmUTCL1_UTCL0_INVREQ_DISABLE);
+ tmp = RREG32_SOC15_RLC(GC, 0,
mmUTCL1_UTCL0_INVREQ_DISABLE);
/* only override TCP & SQC bits */
tmp &= 0x << (4 * max_wgp_per_sh);
tmp |= (utcl_invreq_disable &
utcl_invreq_disable_mask);
- WREG32_SOC15(GC, 0,
mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
+ WREG32_SOC15_RLC(GC, 0,
mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
- tmp = RREG32_SOC15(GC, 0,
mmGCRD_SA_TARGETS_DISABLE);
+ tmp = RREG32_SOC15_RLC(GC, 0,
mmGCRD_SA_TARGETS_DISABLE);
/* only override TCP bits */
tmp &= 0x << (2 * max_wgp_per_sh);
tmp |= (gcrd_targets_disable_tcp &
gcrd_targets_disable_mask);
- WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE,
tmp);
+ WREG32_SOC15_RLC(GC, 0,
mmGCRD_SA_TARGETS_DISABLE, tmp);
}
}
@@ -5044,8 +5044,8 @@ static void gfx_v10_0_get_tcc_info(struct amdgpu_device
*adev)
tcc_disable = RREG32_SOC15_RLC(GC, 0,
mmCGTS_TCC_DISABLE_gc_10_3) |
RREG32_SOC15_RLC(GC, 0,
mmCGTS_USER_TCC_DISABLE_gc_10_3);
} else {
- tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
- RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
+ tcc_disable = RREG32_SOC15_RLC(GC, 0, mmCGTS_TCC_DISABLE) |
+ RREG32_SOC15_RLC(GC, 0, mmCGTS_USER_TCC_DISABLE);
}
adev->gfx.config.tcc_disabled_mask =
@@ -5058,7 +5058,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device
*adev)
u32 tmp;
int i;
- WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
+ WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
gfx_v10_0_setup_rb(adev);
gfx_v10_0_get_cu_info(adev, >gfx.cu_info);
@@ -6794,10 +6794,10 @@ static int gfx_v10_0_kiq_init_register(struct
amdgpu_ring *ring)
/* inactivate the queue */
if (amdgpu_sriov_vf(adev))
- WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
+ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0);
/* disable wptr polling */
- WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
+ WREG32_FIELD15_RLC(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
/* write the EOP addr */
WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
@@ -7103,15 +7103,15 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct
amdgpu_device *adev)
case CHIP_VANGOGH:
return true;
default:
- data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
- WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
- WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
+ data = RREG32_SOC15_RLC(GC, 0, mmVGT_ESGS_RING_SIZE);
+ WREG32_SOC15_RLC(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
+ WREG32_SOC15_RLC(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
- if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
- WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
+ if (RREG32_SOC15_RLC(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
+ WREG32_SOC15_RLC(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
return true;
} else {
- WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
+ WREG32_SOC15_RLC(GC, 0, mmVGT_ESGS_RING_SIZE, data);
return false;
}
break;
@@ -7358,9 +7358,9 @@ static int gfx_v10_0_hw_fini(void *handle)
if (amdgpu_sriov_vf(adev)) {
gfx_v10_0_cp_gfx_enable(adev, false);
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
- tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
+ tmp = RREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS);
[PATCH 8/8] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers
use psp to program IH_RB_CNTL* if indirect access
for ih enabled in SRIOV environment.
Signed-off-by: Victor
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +--
drivers/gpu/drm/amd/amdgpu/nv.c| 2 +-
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index f4e4040bbd25..903772b37759 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct
amdgpu_device *adev,
/* enable_intr field is only valid in ring0 */
if (ih == >irq.ih)
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 :
0));
- WREG32(ih_regs->ih_rb_cntl, tmp);
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL, tmp)) {
+ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ WREG32(ih_regs->ih_rb_cntl, tmp);
+ }
if (enable) {
ih->enabled = true;
@@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device
*adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
}
- WREG32(ih_regs->ih_rb_cntl, tmp);
+
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL, tmp)) {
+ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ WREG32(ih_regs->ih_rb_cntl, tmp);
+ }
if (ih == >irq.ih) {
/* set the ih ring 0 writeback address whether it's enabled or
not */
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index c848b9470f66..0fc30afb4d61 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -738,8 +738,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_NAVI12:
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
- amdgpu_device_ip_block_add(adev, _ih_ip_block);
amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
+ amdgpu_device_ip_block_add(adev, _ih_ip_block);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 6/8] drm/amdgpu: Change GC register access from MMIO to RLCG
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 36
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index a96be9acb9b4..f71644f25df6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -174,12 +174,12 @@ static void gfxhub_v2_0_init_system_aperture_regs(struct
amdgpu_device *adev)
}
/* Program "protection fault". */
- WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
(u32)(adev->dummy_page_addr >> 12));
- WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
(u32)((u64)adev->dummy_page_addr >> 44));
- WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
+ WREG32_FIELD15_RLC(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
}
@@ -213,7 +213,7 @@ static void gfxhub_v2_0_init_cache_regs(struct
amdgpu_device *adev)
return;
/* Setup L2 cache */
- tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
+ tmp = RREG32_SOC15_RLC(GC, 0, mmGCVM_L2_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING,
0);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
@@ -224,12 +224,12 @@ static void gfxhub_v2_0_init_cache_regs(struct
amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE,
1);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_L2_CNTL, tmp);
- tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
+ tmp = RREG32_SOC15_RLC(GC, 0, mmGCVM_L2_CNTL2);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_L2_CNTL2, tmp);
tmp = mmGCVM_L2_CNTL3_DEFAULT;
if (adev->gmc.translate_further) {
@@ -241,16 +241,16 @@ static void gfxhub_v2_0_init_cache_regs(struct
amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
}
- WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_L2_CNTL3, tmp);
tmp = mmGCVM_L2_CNTL4_DEFAULT;
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL,
0);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL,
0);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_L2_CNTL4, tmp);
tmp = mmGCVM_L2_CNTL5_DEFAULT;
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE,
0);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_L2_CNTL5, tmp);
}
static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
@@ -267,18 +267,18 @@ static void gfxhub_v2_0_enable_system_domain(struct
amdgpu_device *adev)
static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
{
- WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
+ WREG32_SOC15_RLC(GC, 0,
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0x);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
+ WREG32_SOC15_RLC(GC, 0,
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0x000F);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
+ WREG32_SOC15_RLC(GC, 0,
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
0);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
+ WREG32_SOC15_RLC(GC, 0,
mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
0);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
- WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
+ WREG32_SOC15_RLC(GC, 0,
mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
+ WREG32_SOC15_RLC(GC, 0,
mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
}
@@ -393,7 +393,7 @@ static void gfxhub_v2_0_set_fault_enable_default(struct
[PATCH 5/8] drm/amdgpu: Change GC register access from MMIO to RLCG
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 44 ++-
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 8 ++--
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 22 --
drivers/gpu/drm/amd/amdgpu/nv.c | 4 +-
drivers/gpu/drm/amd/amdgpu/soc15.c| 13 ++
7 files changed, 47 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 9394dbf504de..7dcb94364448 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -239,7 +239,7 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd,
uint32_t pipe_id,
for (reg = hqd_base;
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
- WREG32(reg, mqd_hqd[reg - hqd_base]);
+ WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
/* Activate doorbell logic before triggering WPTR poll. */
@@ -365,7 +365,7 @@ static int kgd_hqd_dump(struct kgd_dev *kgd,
if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
break; \
(*dump)[i][0] = (addr) << 2;\
- (*dump)[i++][1] = RREG32(addr); \
+ (*dump)[i++][1] = RREG32_RLC(addr); \
} while (0)
*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 4d32233cde92..10e2fbb0cb5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -578,13 +578,13 @@ void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device
*adev, int hub_type,
for (i = 0; i < 16; i++) {
reg = hub->vm_context0_cntl + hub->ctx_distance * i;
- tmp = RREG32(reg);
+ tmp = (hub_type == AMDGPU_GFXHUB_0) ? RREG32_RLC(reg) :
RREG32(reg);
if (enable)
tmp |= hub->vm_cntx_cntl_vm_fault;
else
tmp &= ~hub->vm_cntx_cntl_vm_fault;
- WREG32(reg, tmp);
+ WREG32_RLC(reg, tmp);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8a54d5f27671..b1d5b08e4f06 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1435,6 +1435,10 @@ static bool gfx_v10_is_rlcg_rw(struct amdgpu_device
*adev, u32 offset, uint32_t
offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
+ offset == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
+ offset == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
+ offset == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
+ offset == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG) ||
offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
if (!amdgpu_sriov_reg_indirect_gc(adev))
*flag = GFX_RLCG_GC_WRITE_OLD;
@@ -4935,8 +4939,8 @@ static void gfx_v10_0_init_compute_vmid(struct
amdgpu_device *adev)
/* Initialize all compute VMIDs to have no GDS, GWS, or OA
acccess. These should be enabled by FW for target VMIDs. */
for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
- WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
- WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+ WREG32_SOC15_OFFSET_RLC(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+ WREG32_SOC15_OFFSET_RLC(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
WREG32_SOC15_OFFSET_RLC(GC, 0, mmGDS_GWS_VMID0, i, 0);
WREG32_SOC15_OFFSET_RLC(GC, 0, mmGDS_OA_VMID0, i, 0);
}
@@ -4953,8 +4957,8 @@ static void gfx_v10_0_init_gds_vmid(struct amdgpu_device
*adev)
* access so that HWS firmware can save/restore entries.
*/
for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
- WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
- WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
+ WREG32_SOC15_OFFSET_RLC(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
+ WREG32_SOC15_OFFSET_RLC(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
WREG32_SOC15_OFFSET_RLC(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
WREG32_SOC15_OFFSET_RLC(GC, 0, mmGDS_OA_VMID0, vmid, 0);
}
@@
[PATCH 4/8] drm/amdgpu: Change GC register access from MMIO to RLCG
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 38
2 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 376c92b1f938..8a54d5f27671 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6811,7 +6811,7 @@ static int gfx_v10_0_kiq_init_register(struct amdgpu_ring
*ring)
/* disable the queue if it's active */
if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
- WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
+ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
for (j = 0; j < adev->usec_timeout; j++) {
if (!(RREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE) & 1))
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index 2aecc6a243e8..30ff10953831 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -104,7 +104,7 @@ gfxhub_v2_0_print_l2_protection_fault_status(struct
amdgpu_device *adev,
static u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)
{
- u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
+ u64 base = RREG32_SOC15_RLC(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
base <<= 24;
@@ -114,7 +114,7 @@ static u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device
*adev)
static u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)
{
- return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
+ return (u64)RREG32_SOC15_RLC(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
}
static void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t
vmid,
@@ -122,11 +122,11 @@ static void gfxhub_v2_0_setup_vm_pt_regs(struct
amdgpu_device *adev, uint32_t vm
{
struct amdgpu_vmhub *hub = >vmhub[AMDGPU_GFXHUB_0];
- WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+ WREG32_SOC15_OFFSET_RLC(GC, 0,
mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
hub->ctx_addr_distance * vmid,
lower_32_bits(page_table_base));
- WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+ WREG32_SOC15_OFFSET_RLC(GC, 0,
mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
hub->ctx_addr_distance * vmid,
upper_32_bits(page_table_base));
}
@@ -137,14 +137,14 @@ static void gfxhub_v2_0_init_gart_aperture_regs(struct
amdgpu_device *adev)
gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
- WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
(u32)(adev->gmc.gart_start >> 12));
- WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
(u32)(adev->gmc.gart_start >> 44));
- WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
(u32)(adev->gmc.gart_end >> 12));
- WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+ WREG32_SOC15_RLC(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
(u32)(adev->gmc.gart_end >> 44));
}
@@ -189,7 +189,7 @@ static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device
*adev)
uint32_t tmp;
/* Setup TLB control */
- tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
+ tmp = RREG32_SOC15_RLC(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
@@ -201,7 +201,7 @@ static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device
*adev)
tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
MTYPE, MTYPE_UC); /* UC, uncached */
- WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
+ WREG32_SOC15_RLC(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
}
static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
@@ -257,12 +257,12 @@ static void gfxhub_v2_0_enable_system_domain(struct
amdgpu_device *adev)
{
uint32_t tmp;
- tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
+ tmp = RREG32_SOC15_RLC(GC, 0, mmGCVM_CONTEXT0_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
tmp = REG_SET_FIELD(tmp,
[PATCH 3/8] drm/amdgpu: Change GC(SDMA) register access from MMIO to RLCG
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 78 ++
1 file changed, 42 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 920fc6d4a127..f72faa132419 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -324,9 +324,9 @@ static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring
*ring)
wptr = READ_ONCE(*((u64 *)>wb.wb[ring->wptr_offs]));
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
} else {
- wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me,
mmSDMA0_GFX_RB_WPTR_HI));
+ wptr = RREG32_RLC(sdma_v5_0_get_reg_offset(adev, ring->me,
mmSDMA0_GFX_RB_WPTR_HI));
wptr = wptr << 32;
- wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me,
mmSDMA0_GFX_RB_WPTR));
+ wptr |= RREG32_RLC(sdma_v5_0_get_reg_offset(adev, ring->me,
mmSDMA0_GFX_RB_WPTR));
DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
ring->me, wptr);
}
@@ -367,9 +367,9 @@ static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring
*ring)
lower_32_bits(ring->wptr << 2),
ring->me,
upper_32_bits(ring->wptr << 2));
- WREG32(sdma_v5_0_get_reg_offset(adev, ring->me,
mmSDMA0_GFX_RB_WPTR),
+ WREG32_RLC(sdma_v5_0_get_reg_offset(adev, ring->me,
mmSDMA0_GFX_RB_WPTR),
lower_32_bits(ring->wptr << 2));
- WREG32(sdma_v5_0_get_reg_offset(adev, ring->me,
mmSDMA0_GFX_RB_WPTR_HI),
+ WREG32_RLC(sdma_v5_0_get_reg_offset(adev, ring->me,
mmSDMA0_GFX_RB_WPTR_HI),
upper_32_bits(ring->wptr << 2));
}
}
@@ -530,12 +530,12 @@ static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
amdgpu_ttm_set_buffer_funcs_status(adev, false);
for (i = 0; i < adev->sdma.num_instances; i++) {
- rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_CNTL));
+ rb_cntl = RREG32_RLC(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE,
0);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL),
rb_cntl);
- ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_GFX_IB_CNTL));
+ WREG32_RLC(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_CNTL), rb_cntl);
+ ib_cntl = RREG32_RLC(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_GFX_IB_CNTL));
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE,
0);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL),
ib_cntl);
+ WREG32_RLC(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_GFX_IB_CNTL), ib_cntl);
}
}
@@ -596,11 +596,11 @@ static void sdma_v5_0_ctx_switch_enable(struct
amdgpu_device *adev, bool enable)
}
if (enable && amdgpu_sdma_phase_quantum) {
- WREG32(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_PHASE0_QUANTUM),
+ WREG32_RLC(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_PHASE0_QUANTUM),
phase_quantum);
- WREG32(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_PHASE1_QUANTUM),
+ WREG32_RLC(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_PHASE1_QUANTUM),
phase_quantum);
- WREG32(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_PHASE2_QUANTUM),
+ WREG32_RLC(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_PHASE2_QUANTUM),
phase_quantum);
}
if (!amdgpu_sriov_vf(adev))
@@ -667,58 +667,63 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device
*adev)
/* Set ring buffer size in dwords */
rb_bufsz = order_base_2(ring->ring_size / 4);
- rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_CNTL));
+ rb_cntl = RREG32_RLC(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE,
rb_bufsz);
#ifdef __BIG_ENDIAN
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
RB_SWAP_ENABLE, 1);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
RPTR_WRITEBACK_SWAP_ENABLE, 1);
#endif
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL),
rb_cntl);
+
[PATCH 2/8] drm/amdgpu: Change GC register access from MMIO to RLCG
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Change GC register access from MMIO to RLCG.
Signed-off-by: Peng Ju Zhou
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 38 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 205 +-
drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
3 files changed, 124 insertions(+), 121 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 62aa1a6f64ed..9394dbf504de 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -96,8 +96,8 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd,
uint32_t vmid,
lock_srbm(kgd, 0, 0, 0, vmid);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
/* APE1 no longer exists on GFX9 */
unlock_srbm(kgd);
@@ -161,7 +161,7 @@ static int kgd_init_interrupts(struct kgd_dev *kgd,
uint32_t pipe_id)
lock_srbm(kgd, mec, pipe, 0, 0);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
@@ -245,7 +245,7 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd,
uint32_t pipe_id,
/* Activate doorbell logic before triggering WPTR poll. */
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
if (wptr) {
/* Don't read wptr with get_user because the user
@@ -274,17 +274,17 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd,
uint32_t pipe_id,
guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
lower_32_bits(guessed_wptr));
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
upper_32_bits(guessed_wptr));
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
lower_32_bits((uint64_t)wptr));
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0,
mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
upper_32_bits((uint64_t)wptr));
pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
(uint32_t)get_queue_mask(adev, pipe_id, queue_id));
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
(uint32_t)get_queue_mask(adev, pipe_id, queue_id));
}
@@ -294,7 +294,7 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd,
uint32_t pipe_id,
CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
release_queue(kgd);
@@ -497,13 +497,13 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd,
uint64_t queue_address,
uint32_t low, high;
acquire_queue(kgd, pipe_id, queue_id);
- act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+ act = RREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
if (act) {
low = lower_32_bits(queue_address >> 8);
high = upper_32_bits(queue_address >> 8);
- if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
- high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
+ if (low == RREG32_RLC(SOC15_REG_OFFSET(GC, 0,
mmCP_HQD_PQ_BASE)) &&
+ high == RREG32_RLC(SOC15_REG_OFFSET(GC, 0,
mmCP_HQD_PQ_BASE_HI)))
retval = true;
}
release_queue(kgd);
@@ -551,7 +551,7 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
acquire_queue(kgd, pipe_id, queue_id);
if (m->cp_hqd_vmid == 0)
-
[PATCH 1/8] drm/amdgpu: change MMHUB register access from MMIO to RLCG
From: pengzhou
In SRIOV environment, KMD should access MMHUB registers
with RLCG if MMHUB indirect access bit enabled.
Change MMHUB register access from MMIO to RLCG.
Signed-off-by: pengzhou
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 12 ++--
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 39 +
2 files changed, 29 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 2bfd620576f2..42818c40d08c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -38,6 +38,7 @@
#include "soc15.h"
#include "soc15d.h"
#include "soc15_common.h"
+#include "gc/gc_10_1_0_offset.h"
#include "nbio_v2_3.h"
@@ -253,7 +254,10 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device
*adev, uint32_t vmid,
DRM_ERROR("Timeout waiting for sem acquire in VM
flush!\n");
}
- WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
+ if (vmhub == AMDGPU_MMHUB_0)
+ WREG32_RLC_NO_KIQ((hub->vm_inv_eng0_req + eng), inv_req);
+ else
+ WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req);
/*
* Issue a dummy read to wait for the ACK register to be cleared
@@ -280,8 +284,10 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device
*adev, uint32_t vmid,
* add semaphore release after invalidation,
* write with 0 means semaphore release
*/
- WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
- hub->eng_distance * eng, 0);
+ if (vmhub == AMDGPU_MMHUB_0)
+ WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
+ else
+ WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
spin_unlock(>gmc.invalidate_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index da7edd1ed6b2..e8ecdf383192 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -29,6 +29,7 @@
#include "mmhub/mmhub_2_0_0_default.h"
#include "navi10_enum.h"
+#include "gc/gc_10_1_0_offset.h"
#include "soc15_common.h"
#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d
@@ -165,11 +166,11 @@ static void mmhub_v2_0_setup_vm_pt_regs(struct
amdgpu_device *adev, uint32_t vmi
{
struct amdgpu_vmhub *hub = >vmhub[AMDGPU_MMHUB_0];
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0,
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
hub->ctx_addr_distance * vmid,
lower_32_bits(page_table_base));
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0,
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
hub->ctx_addr_distance * vmid,
upper_32_bits(page_table_base));
}
@@ -180,14 +181,14 @@ static void mmhub_v2_0_init_gart_aperture_regs(struct
amdgpu_device *adev)
mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
(u32)(adev->gmc.gart_start >> 12));
- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
(u32)(adev->gmc.gart_start >> 44));
- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
(u32)(adev->gmc.gart_end >> 12));
- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
(u32)(adev->gmc.gart_end >> 44));
}
@@ -197,9 +198,9 @@ static void mmhub_v2_0_init_system_aperture_regs(struct
amdgpu_device *adev)
uint32_t tmp;
/* Program the AGP BAR */
- WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
- WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
- WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >>
24);
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
if (!amdgpu_sriov_vf(adev)) {
/* Program the system aperture low logical page number. */
@@ -304,12 +305,12 @@ static void mmhub_v2_0_enable_system_domain(struct
amdgpu_device *adev)
{
uint32_t tmp;
- tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
+
[pull] amdgpu, radeon drm-fixes-5.12
Hi Dave, Daniel, Fixes for 5.12. The following changes since commit 6fdb8e5aba6a33fe5f1a0bd1bcf0cf2884437ead: Merge tag 'imx-drm-fixes-2021-04-01' of git://git.pengutronix.de/git/pza/linux into drm-fixes (2021-04-02 04:53:16 +1000) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-5.12-2021-04-08 for you to fetch changes up to cdcc108a2aced5f9cbc45920e29bf49819e5477f: drm/amdgpu/smu7: fix CAC setting on TOPAZ (2021-04-08 00:36:40 -0400) amd-drm-fixes-5.12-2021-04-08: amdgpu: - DCN3 fix - Fix CAC setting regression for TOPAZ - Fix ttm regression radeon: - Fix ttm regression Alex Deucher (1): drm/amdgpu/smu7: fix CAC setting on TOPAZ Qingqing Zhuo (1): drm/amd/display: Add missing mask for DCN3 xinhui pan (2): drm/amdgpu: Fix size overflow drm/radeon: Fix size overflow drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h | 1 + drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 3 ++- drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++-- 4 files changed, 6 insertions(+), 4 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 3/8] drm/amdgpu: Implement mmap as GEM object function
Hi Am 07.04.21 um 21:49 schrieb Felix Kuehling: On 2021-04-07 3:34 p.m., Felix Kuehling wrote: On 2021-04-07 7:25 a.m., Christian König wrote: + /* + * Don't verify access for KFD BOs. They don't have a GEM + * object associated with them. + */ + if (bo->kfd_bo) + goto out; Who does the access verification now? This is somewhat confusing. I took this check as-is, including the comment, from amdgpu's verify_access function. The verify_access function was called by ttm_bo_mmap. It returned 0 and ttm_bo_mmap did the mapping. This is probably a left-over from when we mapped BOs using /dev/kfd. We changed this to use /dev/dri/renderD* a long time ago to fix CPU mapping invalidations on memory evictions. I think we can let GEM do the access check. Ok, good to know. Thomas can you remove the extra handling in a separate prerequisite patch? If anybody then bisects to this patch we at least know what to do to get it working again. FWIW, I ran KFDTest test with this shortcut removed on current amd-staging-drm-next + my HMM patch series, and it didn't seem to cause any issues. Wait, I celebrated too soon. I was running the wrong kernel. I do see some failures where access is being denied. I need to do more debugging to figure out what's causing that. OK, thanks for looking into this. I'll wait a bit before sending out the new patchset. Best regards Thomas Regards, Felix Regards, Felix Regards, Christian. -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer OpenPGP_signature Description: OpenPGP digital signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu/smu7: fix CAC setting on TOPAZ
[AMD Public Use]
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Wednesday, April 7, 2021 9:39 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu/smu7: fix CAC setting on TOPAZ
>
> We need to enable MC CAC for mclk switching to work.
>
> Fixes: d765129a719f ("drm/amd/pm: correct sclk/mclk dpm enablement")
> Bug:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla
> b.freedesktop.org%2Fdrm%2Famd%2F-
> %2Fissues%2F1561data=04%7C01%7Cevan.quan%40amd.com%7C00a
> 251035e6f4c16d63608d8f9ca9928%7C3dd8961fe4884e608e11a82d994e183d%
> 7C0%7C0%7C637533995857826102%7CUnknown%7CTWFpbGZsb3d8eyJWIjoi
> MC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C100
> 0sdata=gMvcwYRiSFSyYhzXm5OGBxdRGIiPC4%2BkVBmN17dJR8w%3D
> reserved=0
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index 301b6769f007..0541bfc81c1b 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -1224,7 +1224,8 @@ static int smu7_enable_sclk_mclk_dpm(struct
> pp_hwmgr *hwmgr)
> (hwmgr->chip_id == CHIP_POLARIS10) ||
> (hwmgr->chip_id == CHIP_POLARIS11) ||
> (hwmgr->chip_id == CHIP_POLARIS12) ||
> - (hwmgr->chip_id == CHIP_TONGA))
> + (hwmgr->chip_id == CHIP_TONGA) ||
> + (hwmgr->chip_id == CHIP_TOPAZ))
> PHM_WRITE_FIELD(hwmgr->device,
> MC_SEQ_CNTL_3, CAC_EN, 0x1);
>
>
> --
> 2.30.2
>
> ___
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> gfxdata=04%7C01%7Cevan.quan%40amd.com%7C00a251035e6f4c16d
> 63608d8f9ca9928%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63
> 7533995857826102%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD
> AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=
> AJFxsTzMjqU8IW7%2FL%2BtsPIWFmJb95dyr5pZ7EXnk20g%3Dreserve
> d=0
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RE: [0001-increase-time-out-2s-send-msg-to-smu.patch] drm/amd/pm: increase time out value when sending msg to SMU
[AMD Public Use]
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> charles sun
> Sent: Thursday, April 8, 2021 11:42 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Su, Jinzhou (Joe)
> ; Liu, Zhan ; Sun, Charles
>
> Subject: [0001-increase-time-out-2s-send-msg-to-smu.patch] drm/amd/pm:
> increase time out value when sending msg to SMU
>
> when do S3 stress, low rate that PowerUpVcn message will get response
> more than 1s, so here increase the timeout to 2s
>
> Signed-off-by: Sun, Charles charles@amd.com
> Acked-by: Deucher, Alexander alexander.deuc...@amd.com
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> index b725f263092b..dc7d2e71aa6f 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> @@ -79,7 +79,7 @@ static void smu_cmn_read_arg(struct smu_context
> *smu, int smu_cmn_wait_for_response(struct smu_context *smu) {
> struct amdgpu_device *adev = smu->adev;
> - uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
> + uint32_t cur_value, i, timeout = adev->usec_timeout * 20;
>
> for (i = 0; i < timeout; i++) {
> cur_value = RREG32_SOC15(MP1, 0,
> mmMP1_SMN_C2PMSG_90);
> --
> 2.25.1
>
> ___
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> freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfxdata=04%7C01%7Cevan.quan%40amd.com%7C9924c6be21724c736
> b7208d8fa40576b%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63
> 7534501546436504%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD
> AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=
> nyya88jiGFYBVvr4fuZfiO9SZpspw2KxP0o9xaiaTig%3Dreserved=0
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[0001-increase-time-out-2s-send-msg-to-smu.patch] drm/amd/pm: increase time out value when sending msg to SMU
when do S3 stress, low rate that PowerUpVcn message will get response
more than 1s, so here increase the timeout to 2s
Signed-off-by: Sun, Charles charles@amd.com
Acked-by: Deucher, Alexander alexander.deuc...@amd.com
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index b725f263092b..dc7d2e71aa6f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -79,7 +79,7 @@ static void smu_cmn_read_arg(struct smu_context *smu,
int smu_cmn_wait_for_response(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
- uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
+ uint32_t cur_value, i, timeout = adev->usec_timeout * 20;
for (i = 0; i < timeout; i++) {
cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
--
2.25.1
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Re: [0001-increase-time-out-2s-send-msg-to-smu.patch] drm/amd/pm: increase time out value when sending msg to SMU
[AMD Official Use Only - Internal Distribution Only]
You wrote the patch, it should be signed-off-by you, not me E.g.,
Signed-off-by: Charles Sun
From: Sun, Charles
Sent: Wednesday, April 7, 2021 11:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Liu, Zhan
; Su, Jinzhou (Joe) ; Sun, Charles
; Deucher, Alexander
Subject: [0001-increase-time-out-2s-send-msg-to-smu.patch] drm/amd/pm: increase
time out value when sending msg to SMU
when do S3 stress, low rate that PowerUpVcn message will get response
more than 1s, so here increase the timeout to 2s
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index b725f263092b..dc7d2e71aa6f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -79,7 +79,7 @@ static void smu_cmn_read_arg(struct smu_context *smu,
int smu_cmn_wait_for_response(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
- uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
+ uint32_t cur_value, i, timeout = adev->usec_timeout * 20;
for (i = 0; i < timeout; i++) {
cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
--
2.25.1
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[0001-increase-time-out-2s-send-msg-to-smu.patch] drm/amd/pm: increase time out value when sending msg to SMU
when do S3 stress, low rate that PowerUpVcn message will get response
more than 1s, so here increase the timeout to 2s
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index b725f263092b..dc7d2e71aa6f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -79,7 +79,7 @@ static void smu_cmn_read_arg(struct smu_context *smu,
int smu_cmn_wait_for_response(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
- uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
+ uint32_t cur_value, i, timeout = adev->usec_timeout * 20;
for (i = 0; i < timeout; i++) {
cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
--
2.25.1
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[PATCH 4/4] drm/amdgpu: Remove verify_access shortcut for KFD BOs
This shortcut is no longer needed with access managed progerly by KFD.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 936b3cfdde55..4947dfe9aa70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -165,13 +165,6 @@ static int amdgpu_verify_access(struct ttm_buffer_object
*bo, struct file *filp)
{
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
- /*
-* Don't verify access for KFD BOs. They don't have a GEM
-* object associated with them.
-*/
- if (abo->kfd_bo)
- return 0;
-
if (amdgpu_ttm_tt_get_usermm(bo->ttm))
return -EPERM;
return drm_vma_node_verify_access(>tbo.base.vma_node,
--
2.31.1
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[PATCH 3/4] drm/amdkfd: Allow access for mmapping KFD BOs
DRM allows access automatically when it creates a GEM handle for a BO.
KFD BOs don't have GEM handles, so KFD needs to manage access manually.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 3 ++-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 19 ++-
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 8 +---
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 7 ---
4 files changed, 29 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 0d59bebd92af..7c8c5e469707 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -245,7 +245,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
void *drm_priv, struct kgd_mem **mem,
uint64_t *offset, uint32_t flags);
int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
- struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size);
+ struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
+ uint64_t *size);
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 95442bcd60fb..e7d61ec966b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1232,6 +1232,12 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
domain_string(alloc_domain), ret);
goto err_bo_create;
}
+ ret = drm_vma_node_allow(>vma_node, drm_priv);
+ if (ret) {
+ pr_debug("Failed to allow vma node access. ret %d\n",
+ret);
+ goto err_node_allow;
+ }
bo = gem_to_amdgpu_bo(gobj);
if (bo_type == ttm_bo_type_sg) {
bo->tbo.sg = sg;
@@ -1261,6 +1267,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
allocate_init_user_pages_failed:
remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
+ drm_vma_node_revoke(>vma_node, drm_priv);
+err_node_allow:
amdgpu_bo_unref();
/* Don't unreserve system mem limit twice */
goto err_reserve_limit;
@@ -1278,7 +1286,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
}
int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
- struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size)
+ struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
+ uint64_t *size)
{
struct amdkfd_process_info *process_info = mem->process_info;
unsigned long bo_size = mem->bo->tbo.base.size;
@@ -1355,6 +1364,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
}
/* Free the BO*/
+ drm_vma_node_revoke(>bo->tbo.base.vma_node, drm_priv);
drm_gem_object_put(>bo->tbo.base);
mutex_destroy(>lock);
kfree(mem);
@@ -1666,6 +1676,7 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
struct drm_gem_object *obj;
struct amdgpu_bo *bo;
+ int ret;
if (dma_buf->ops != _dmabuf_ops)
/* Can't handle non-graphics buffers */
@@ -1686,6 +1697,12 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev
*kgd,
if (!*mem)
return -ENOMEM;
+ ret = drm_vma_node_allow(>vma_node, drm_priv);
+ if (ret) {
+ kfree(mem);
+ return ret;
+ }
+
if (size)
*size = amdgpu_bo_size(bo);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 43de260b2230..8fc18de7cff4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1328,7 +1328,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file
*filep,
return 0;
err_free:
- amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem,
NULL);
+ amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem,
+ pdd->vm, NULL);
err_unlock:
mutex_unlock(>mutex);
return err;
@@ -1365,7 +1366,7 @@ static int kfd_ioctl_free_memory_of_gpu(struct file
*filep,
}
ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd,
- (struct kgd_mem *)mem, );
+ (struct kgd_mem *)mem, pdd->vm, );
/* If freeing the buffer failed, leave the handle in place for
* clean-up during process tear-down.
@@ -1721,7 +1722,8 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,
return 0;
err_free:
- amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem
[PATCH 1/4] drm/amdkfd: Remove legacy code not acquiring VMs
ROCm user mode has acquired VMs from DRM file descriptors for as long
as it supported the upstream KFD. Legacy code to support older versions
of ROCm is not needed any more.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 4 --
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 50 ---
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 27 --
3 files changed, 10 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 14f68c028126..5ffb07b02810 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -234,14 +234,10 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev
*dst, struct kgd_dev *s
})
/* GPUVM API */
-int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, u32 pasid,
- void **vm, void **process_info,
- struct dma_fence **ef);
int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
struct file *filp, u32 pasid,
void **vm, void **process_info,
struct dma_fence **ef);
-void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm);
void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm);
uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index e93850f2f3b1..36012229ccc1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1037,41 +1037,6 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void
**process_info,
return ret;
}
-int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, u32 pasid,
- void **vm, void **process_info,
- struct dma_fence **ef)
-{
- struct amdgpu_device *adev = get_amdgpu_device(kgd);
- struct amdgpu_vm *new_vm;
- int ret;
-
- new_vm = kzalloc(sizeof(*new_vm), GFP_KERNEL);
- if (!new_vm)
- return -ENOMEM;
-
- /* Initialize AMDGPU part of the VM */
- ret = amdgpu_vm_init(adev, new_vm, AMDGPU_VM_CONTEXT_COMPUTE, pasid);
- if (ret) {
- pr_err("Failed init vm ret %d\n", ret);
- goto amdgpu_vm_init_fail;
- }
-
- /* Initialize KFD part of the VM and process info */
- ret = init_kfd_vm(new_vm, process_info, ef);
- if (ret)
- goto init_kfd_vm_fail;
-
- *vm = (void *) new_vm;
-
- return 0;
-
-init_kfd_vm_fail:
- amdgpu_vm_fini(adev, new_vm);
-amdgpu_vm_init_fail:
- kfree(new_vm);
- return ret;
-}
-
int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
struct file *filp, u32 pasid,
void **vm, void **process_info,
@@ -1138,21 +1103,6 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device
*adev,
}
}
-void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm)
-{
- struct amdgpu_device *adev = get_amdgpu_device(kgd);
- struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
-
- if (WARN_ON(!kgd || !vm))
- return;
-
- pr_debug("Destroying process vm %p\n", vm);
-
- /* Release the VM context */
- amdgpu_vm_fini(adev, avm);
- kfree(vm);
-}
-
void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index d4241d29ea94..d97e330a5022 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -935,9 +935,6 @@ static void kfd_process_destroy_pdds(struct kfd_process *p)
pdd->dev->kgd, pdd->vm);
fput(pdd->drm_file);
}
- else if (pdd->vm)
- amdgpu_amdkfd_gpuvm_destroy_process_vm(
- pdd->dev->kgd, pdd->vm);
if (pdd->qpd.cwsr_kaddr && !pdd->qpd.cwsr_base)
free_pages((unsigned long)pdd->qpd.cwsr_kaddr,
@@ -1375,19 +1372,18 @@ int kfd_process_device_init_vm(struct
kfd_process_device *pdd,
struct kfd_dev *dev;
int ret;
+ if (!drm_file)
+ return -EINVAL;
+
if (pdd->vm)
- return drm_file ? -EBUSY : 0;
+ return -EBUSY;
p = pdd->process;
dev = pdd->dev;
- if (drm_file)
- ret =
[PATCH 2/4] drm/amdkfd: Use drm_priv to pass VM from KFD to amdgpu
amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu needs the drm_priv to allow mmap
to access the BO through the corresponding file descriptor.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 14 ++--
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 69 +++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 5 +-
3 files changed, 50 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 5ffb07b02810..0d59bebd92af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -236,20 +236,20 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev
*dst, struct kgd_dev *s
/* GPUVM API */
int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
struct file *filp, u32 pasid,
- void **vm, void **process_info,
+ void **process_info,
struct dma_fence **ef);
-void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm);
-uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
+void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void
*drm_priv);
+uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
struct kgd_dev *kgd, uint64_t va, uint64_t size,
- void *vm, struct kgd_mem **mem,
+ void *drm_priv, struct kgd_mem **mem,
uint64_t *offset, uint32_t flags);
int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size);
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
- struct kgd_dev *kgd, struct kgd_mem *mem, void *vm);
+ struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
- struct kgd_dev *kgd, struct kgd_mem *mem, void *vm);
+ struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
int amdgpu_amdkfd_gpuvm_sync_memory(
struct kgd_dev *kgd, struct kgd_mem *mem, bool intr);
int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
@@ -260,7 +260,7 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev
*kgd,
struct kfd_vm_fault_info *info);
int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
struct dma_buf *dmabuf,
- uint64_t va, void *vm,
+ uint64_t va, void *drm_priv,
struct kgd_mem **mem, uint64_t *size,
uint64_t *mmap_offset);
int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 36012229ccc1..95442bcd60fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -951,6 +951,13 @@ static int process_update_pds(struct amdkfd_process_info
*process_info,
return 0;
}
+static struct amdgpu_vm *drm_priv_to_vm(struct drm_file *drm_priv)
+{
+ struct amdgpu_fpriv *fpriv = drm_priv->driver_priv;
+
+ return >vm;
+}
+
static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
struct dma_fence **ef)
{
@@ -1039,15 +1046,19 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void
**process_info,
int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
struct file *filp, u32 pasid,
- void **vm, void **process_info,
+ void **process_info,
struct dma_fence **ef)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
- struct drm_file *drm_priv = filp->private_data;
- struct amdgpu_fpriv *drv_priv = drm_priv->driver_priv;
- struct amdgpu_vm *avm = _priv->vm;
+ struct amdgpu_fpriv *drv_priv;
+ struct amdgpu_vm *avm;
int ret;
+ ret = amdgpu_file_to_fpriv(filp, _priv);
+ if (ret)
+ return ret;
+ avm = _priv->vm;
+
/* Already a compute VM? */
if (avm->process_info)
return -EINVAL;
@@ -1062,7 +1073,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev
*kgd,
if (ret)
return ret;
- *vm = (void *)avm;
+ amdgpu_vm_set_task_info(avm);
return 0;
}
@@ -1103,15 +1114,17 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct
amdgpu_device *adev,
}
}
-void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm)
+void
[PATCH] drm/amd/display: Fix two cursor duplication when using overlay
Our driver supports overlay planes, and as expected, some userspace
compositor takes advantage of these features. If the userspace is not
enabling the cursor, they can use multiple planes as they please.
Nevertheless, we start to have constraints when userspace tries to
enable hardware cursor with various planes. Basically, we cannot draw
the cursor at the same size and position on two separated pipes since it
uses extra bandwidth and DML only run with one cursor.
For those reasons, when we enable hardware cursor and multiple planes,
our driver should accept variations like the ones described below:
+-+ +--+
| +-+ | | |
| |Primary | | | Primary |
| | | | | Overlay |
| +-+ | | |
|Overlay | | |
+-+ +--+
In this scenario, we can have the desktop UI in the overlay and some
other framebuffer attached to the primary plane (e.g., video). However,
userspace needs to obey some rules and avoid scenarios like the ones
described below (when enabling hw cursor):
++
|Overlay |
+-++-+---+ +-||--+
| ++ | ++ | | ++ |
| |Overlay | | |Overlay | | | |
| || | || | | |
| ++ | ++ | | |
| Primary || Primary | | Primary |
+-++-+ +-+
+-+ +-+
| ++ | Primary|
| |Overlay | | |
| || | |
| ++ | ++ |
| Primary | | |Overlay | |
+-+ +-||--+
++
If the userspace violates some of the above scenarios, our driver needs
to reject the commit; otherwise, we can have unexpected behavior. Since
we don't have a proper driver validation for the above case, we can see
some problems like a duplicate cursor in applications that use multiple
planes. This commit fixes the cursor issue and others by adding adequate
verification for multiple planes.
Cc: Louis Li
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Hersen Wu
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 59 +++
1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ac6ab35f89b2..5ae6d61e83f1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9939,6 +9939,61 @@ static int add_affected_mst_dsc_crtcs(struct
drm_atomic_state *state, struct drm
}
#endif
+static int validate_overlay(struct drm_atomic_state *state)
+{
+ int i;
+ struct drm_plane *plane;
+ struct drm_plane_state *old_plane_state, *new_plane_state;
+ struct drm_plane_state *primary_state, *cursor_state, *overlay_state =
NULL;
+
+ /* Check if primary plane is contained inside overlay */
+ for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state,
new_plane_state, i) {
+ if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
+ if (drm_atomic_plane_disabling(plane->state,
new_plane_state))
+ return 0;
+
+ overlay_state = new_plane_state;
+ continue;
+ }
+ }
+
+ /* check if we're making changes to the overlay plane */
+ if (!overlay_state)
+ return 0;
+
+ /* check if overlay plane is enabled */
+ if (!overlay_state->crtc)
+ return 0;
+
+ /* find the primary plane for the CRTC that the overlay is enabled on */
+ primary_state = drm_atomic_get_plane_state(state,
overlay_state->crtc->primary);
+ if (IS_ERR(primary_state))
+ return PTR_ERR(primary_state);
+
+ /* check if primary plane is enabled */
+ if (!primary_state->crtc)
+ return 0;
+
+ /* check if cursor plane is enabled */
+ cursor_state = drm_atomic_get_plane_state(state,
overlay_state->crtc->cursor);
+ if (IS_ERR(cursor_state))
+ return PTR_ERR(cursor_state);
+
+ if (drm_atomic_plane_disabling(plane->state, cursor_state))
+ return 0;
+
+ /* Perform the bounds check to ensure the overlay plane covers the
primary */
+ if (primary_state->crtc_x < overlay_state->crtc_x ||
+ primary_state->crtc_y < overlay_state->crtc_y ||
+ primary_state->crtc_x + primary_state->crtc_w >
overlay_state->crtc_x + overlay_state->crtc_w ||
+ primary_state->crtc_y + primary_state->crtc_h >
overlay_state->crtc_y + overlay_state->crtc_h) {
+ DRM_DEBUG_ATOMIC("Overlay plane
Re: [PATCH] drm/amd/pm: convert sysfs snprintf to sysfs_emit
On Tue, Apr 6, 2021 at 10:13 AM Carlis wrote: > > From: Xuezhi Zhang > > Fix the following coccicheck warning: > drivers/gpu/drm/amd/pm//amdgpu_pm.c:1940:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:1978:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2022:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:294:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:154:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:496:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:512:9-17: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:1740:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:1667:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2074:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2047:9-17: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2768:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2738:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2442:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:3246:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:3253:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2458:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:3047:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:3133:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:3209:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:3216:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2410:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2496:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2470:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2426:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2965:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:2972:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:3006:8-16: > WARNING: use scnprintf or sprintf > drivers/gpu/drm/amd/pm//amdgpu_pm.c:3013:8-16: > WARNING: use scnprintf or sprintf > > Signed-off-by: Xuezhi Zhang I already applied a similar patch last week. Thanks, Alex > --- > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 58 +++--- > 1 file changed, 29 insertions(+), 29 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > index 5fa65f191a37..2777966ec1ca 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > @@ -151,7 +151,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device > *dev, > pm_runtime_mark_last_busy(ddev->dev); > pm_runtime_put_autosuspend(ddev->dev); > > - return snprintf(buf, PAGE_SIZE, "%s\n", > + return sysfs_emit(buf, "%s\n", > (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : > (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : > "performance"); > } > @@ -291,7 +291,7 @@ static ssize_t > amdgpu_get_power_dpm_force_performance_level(struct device *dev, > pm_runtime_mark_last_busy(ddev->dev); > pm_runtime_put_autosuspend(ddev->dev); > > - return snprintf(buf, PAGE_SIZE, "%s\n", > + return sysfs_emit(buf, "%s\n", > (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : > (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : > (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : > @@ -493,7 +493,7 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev, > if (i == data.nums) > i = -EINVAL; > > - return snprintf(buf, PAGE_SIZE, "%d\n", i); > + return sysfs_emit(buf, "%d\n", i); > } > > static ssize_t amdgpu_get_pp_force_state(struct device *dev, > @@ -509,7 +509,7 @@ static ssize_t amdgpu_get_pp_force_state(struct device > *dev, > if (adev->pp_force_state_enabled) > return amdgpu_get_pp_cur_state(dev, attr, buf); > else > - return snprintf(buf, PAGE_SIZE, "\n"); > + return sysfs_emit(buf, "\n"); > } > > static ssize_t amdgpu_set_pp_force_state(struct device *dev, > @@ -1664,7 +1664,7 @@ static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, > pm_runtime_mark_last_busy(ddev->dev); > pm_runtime_put_autosuspend(ddev->dev); > > - return snprintf(buf, PAGE_SIZE, "%d\n", value); > + return sysfs_emit(buf, "%d\n", value); > } > > static
Re: [PATCH 3/8] drm/amdgpu: Implement mmap as GEM object function
On 2021-04-07 3:34 p.m., Felix Kuehling wrote: On 2021-04-07 7:25 a.m., Christian König wrote: + /* + * Don't verify access for KFD BOs. They don't have a GEM + * object associated with them. + */ + if (bo->kfd_bo) + goto out; Who does the access verification now? This is somewhat confusing. I took this check as-is, including the comment, from amdgpu's verify_access function. The verify_access function was called by ttm_bo_mmap. It returned 0 and ttm_bo_mmap did the mapping. This is probably a left-over from when we mapped BOs using /dev/kfd. We changed this to use /dev/dri/renderD* a long time ago to fix CPU mapping invalidations on memory evictions. I think we can let GEM do the access check. Ok, good to know. Thomas can you remove the extra handling in a separate prerequisite patch? If anybody then bisects to this patch we at least know what to do to get it working again. FWIW, I ran KFDTest test with this shortcut removed on current amd-staging-drm-next + my HMM patch series, and it didn't seem to cause any issues. Wait, I celebrated too soon. I was running the wrong kernel. I do see some failures where access is being denied. I need to do more debugging to figure out what's causing that. Regards, Felix Regards, Felix Regards, Christian. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 0/4] Refine GPU recovery sequence to enhance its stability
On 2021-04-07 6:28 a.m., Christian König wrote: Hi Andrey, Am 06.04.21 um 23:22 schrieb Andrey Grodzovsky: Hey Christian, Denis, see bellow - On 2021-04-06 6:34 a.m., Christian König wrote: Hi Andrey, well good question. My job is to watch over the implementation and design and while I always help I can adjust anybodies schedule. Is the patch to print a warning when the hardware is accessed without holding the locks merged yet? If not then that would probably be a good starting point. It's merged into amd-staging-drm-next and since I work on drm-misc-next I will cherry-pick it into there. Ok good to know, I haven't tracked that one further. Then we would need to unify this with the SRCU to make sure that we have both the reset lock as well as block the hotplug code from reusing the MMIO space. In my understanding there is a significant difference between handling of GPU reset and unplug - while GPU reset use case requires any HW accessing code to block and wait for the reset to finish and then proceed, hot-unplug is permanent and hence no need to wait and proceed but rather abort at once. Yes, absolutely correct. This why I think that in any place we already check for device reset we should also add a check for hot-unplug but the handling would be different in that for hot-unplug we would abort instead of keep waiting. Yes, that's the rough picture in my head as well. Essentially Daniels patch of having an amdgpu_device_hwaccess_begin()/_end() was the right approach. You just can't do it in the top level IOCTL handler, but rather need it somewhere between front end and backend. Can you point me to what patch was it ? Can't find. Similar to handling device reset for unplug we obviously also need to stop and block any MMIO accesses once device is unplugged and, as Daniel Vetter mentioned - we have to do it before finishing pci_remove (early device fini) and not later (when last device reference is dropped from user space) in order to prevent reuse of MMIO space we still access by other hot plugging devices. As in device reset case we need to cancel all delay works, stop drm schedule, complete all unfinished fences(both HW and scheduler fences). While you stated strong objection to force signalling scheduler fences from GPU reset, quote: "you can't signal the dma_fence waiting. Waiting for a dma_fence also means you wait for the GPU reset to finish. When we would signal the dma_fence during the GPU reset then we would run into memory corruption because the hardware jobs running after the GPU reset would access memory which is already freed." To my understating this is a key difference with hot-unplug, the device is gone, all those concerns are irrelevant and hence we can actually force signal scheduler fences (setting and error to them before) to force completion of any waiting clients such as possibly IOCTLs or async page flips e.t.c. Yes, absolutely correct. That's what I also mentioned to Daniel. When we are able to nuke the device and any memory access it might do we can also signal the fences. Beyond blocking all delayed works and scheduler threads we also need to guarantee no IOCTL can access MMIO post device unplug OR in flight IOCTLs are done before we finish pci_remove (amdgpu_pci_remove for us). For this I suggest we do something like what we worked on with Takashi Iwai the ALSA maintainer recently when he helped implementing PCI BARs move support for snd_hda_intel. Take a look at https://cgit.freedesktop.org/~agrodzov/linux/commit/?h=yadro/pcie_hotplug/movable_bars_v9.1=cbaa324799718e2b828a8c7b5b001dd896748497 and https://cgit.freedesktop.org/~agrodzov/linux/commit/?h=yadro/pcie_hotplug/movable_bars_v9.1=e36365d9ab5bbc30bdc221ab4b3437de34492440 We also had same issue there, how to prevent MMIO accesses while the BARs are migrating. What was done there is a refcount was added to count all IOCTLs in flight, for any in flight IOCTL the BAR migration handler would block for the refcount to drop to 0 before it would proceed, for any later IOCTL it stops and wait if device is in migration state. We even don't need the wait part, nothing to wait for, we just return with -ENODEV for this case. This is essentially what the DRM SRCU is doing as well. For the hotplug case we could do this in the toplevel since we can signal the fence and don't need to block memory management. To make SRCU 'wait for' all IOCTLs in flight we would need to wrap every IOCTL ( practically - just drm_ioctl function) with drm_dev_enter/drm_dev_exit - can we do it ? But I'm not sure, maybe we should handle it the same way as reset or maybe we should have it at the top level. If by top level you mean checking for device unplugged and bailing out at the entry to IOCTL or right at start of any work_item/timer function we have then seems to me it's better and more clear. Once we flushed all of them in flight there is
Re: [PATCH 3/8] drm/amdgpu: Implement mmap as GEM object function
On 2021-04-07 7:25 a.m., Christian König wrote: + /* + * Don't verify access for KFD BOs. They don't have a GEM + * object associated with them. + */ + if (bo->kfd_bo) + goto out; Who does the access verification now? This is somewhat confusing. I took this check as-is, including the comment, from amdgpu's verify_access function. The verify_access function was called by ttm_bo_mmap. It returned 0 and ttm_bo_mmap did the mapping. This is probably a left-over from when we mapped BOs using /dev/kfd. We changed this to use /dev/dri/renderD* a long time ago to fix CPU mapping invalidations on memory evictions. I think we can let GEM do the access check. Ok, good to know. Thomas can you remove the extra handling in a separate prerequisite patch? If anybody then bisects to this patch we at least know what to do to get it working again. FWIW, I ran KFDTest test with this shortcut removed on current amd-staging-drm-next + my HMM patch series, and it didn't seem to cause any issues. Regards, Felix Regards, Christian. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [pull] amdgpu, radeon, ttm, sched drm-next-5.13
On Wed, Apr 7, 2021 at 3:23 AM Dave Airlie wrote: > > On Wed, 7 Apr 2021 at 06:54, Alex Deucher wrote: > > > > On Fri, Apr 2, 2021 at 12:22 PM Christian König > > wrote: > > > > > > Hey Alex, > > > > > > the TTM and scheduler changes should already be in the drm-misc-next > > > branch (not 100% sure about the TTM patch, need to double check next > > > week). > > > > > > > The TTM change is not in drm-misc yet. > > > > > Could that cause problems when both are merged into drm-next? > > > > Dave, Daniel, how do you want to handle this? The duplicated patch is this > > one: > > https://cgit.freedesktop.org/drm/drm-misc/commit/?id=ac4eb83ab255de9c31184df51fd1534ba36fd212 > > amdgpu has changes which depend on it. The same patch is included in this > > PR. > > Ouch not sure how best to sync up here, maybe get misc-next into my > tree then rebase your tree on top of it? I can do that. Alex > > Dave. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Unexpected multihop in swaput - likely driver bug.
On Wed, 7 Apr 2021 at 15:46, Christian König wrote: > > What hardware are you using $ inxi -bM System:Host: fedora Kernel: 5.12.0-0.rc6.184.fc35.x86_64+debug x86_64 bits: 64 Desktop: GNOME 40.0 Distro: Fedora release 35 (Rawhide) Machine: Type: Desktop Mobo: ASUSTeK model: ROG STRIX X570-I GAMING v: Rev X.0x serial: UEFI: American Megatrends v: 3603 date: 03/20/2021 Battery: ID-1: hidpp_battery_0 charge: N/A condition: N/A CPU: Info: 16-Core (2-Die) AMD Ryzen 9 3950X [MT MCP MCM] speed: 2365 MHz min/max: 2200/3500 MHz Graphics: Device-1: Advanced Micro Devices [AMD/ATI] Navi 21 [Radeon RX 6800/6800 XT / 6900 XT] driver: amdgpu v: kernel Device-2: AVerMedia Live Streamer CAM 513 type: USB driver: hid-generic,usbhid,uvcvideo Device-3: AVerMedia Live Gamer Ultra-Video type: USB driver: hid-generic,snd-usb-audio,usbhid,uvcvideo Display: wayland server: X.Org 1.21.1 driver: loaded: amdgpu,ati unloaded: fbdev,modesetting,radeon,vesa resolution: 3840x2160~60Hz OpenGL: renderer: AMD SIENNA_CICHLID (DRM 3.40.0 5.12.0-0.rc6.184.fc35.x86_64+debug LLVM 12.0.0) v: 4.6 Mesa 21.1.0-devel Network: Device-1: Intel Wi-Fi 6 AX200 driver: iwlwifi Device-2: Intel I211 Gigabit Network driver: igb Drives:Local Storage: total: 11.35 TiB used: 10.82 TiB (95.3%) Info: Processes: 805 Uptime: 12h 56m Memory: 31.18 GiB used: 21.88 GiB (70.2%) Shell: Bash inxi: 3.3.02 > and how do you exactly trigger this? I am running heavy games like "Zombie Army 4: Dead War" and switching to Gnome Activities and other applications while the game is running. -- Best Regards, Mike Gavrilov. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 7/8] drm/vmwgfx: Inline vmw_verify_access()
On 4/6/21 5:09 AM, Thomas Zimmermann wrote:
Vmwgfx is the only user of the TTM's verify_access callback. Inline
the call and avoid the indirection through the function pointer.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 9 -
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c | 7 ++-
2 files changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
index 2dc031fe4a90..a079734f9d68 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
@@ -658,14 +658,6 @@ static void vmw_evict_flags(struct ttm_buffer_object *bo,
*placement = vmw_sys_placement;
}
-static int vmw_verify_access(struct ttm_buffer_object *bo, struct file *filp)
-{
- struct ttm_object_file *tfile =
- vmw_fpriv((struct drm_file *)filp->private_data)->tfile;
-
- return vmw_user_bo_verify_access(bo, tfile);
-}
-
static int vmw_ttm_io_mem_reserve(struct ttm_device *bdev, struct
ttm_resource *mem)
{
struct vmw_private *dev_priv = container_of(bdev, struct vmw_private,
bdev);
@@ -768,7 +760,6 @@ struct ttm_device_funcs vmw_bo_driver = {
.eviction_valuable = ttm_bo_eviction_valuable,
.evict_flags = vmw_evict_flags,
.move = vmw_move,
- .verify_access = vmw_verify_access,
.swap_notify = vmw_swap_notify,
.io_mem_reserve = _ttm_io_mem_reserve,
};
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c
index 3eaad00668f2..2574d4707407 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c
@@ -65,6 +65,7 @@ int vmw_mmap(struct file *filp, struct vm_area_struct *vma)
};
struct drm_file *file_priv = filp->private_data;
struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev);
+ struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
struct ttm_device *bdev = _priv->bdev;
struct ttm_buffer_object *bo;
int ret;
@@ -76,11 +77,7 @@ int vmw_mmap(struct file *filp, struct vm_area_struct *vma)
if (unlikely(!bo))
return -EINVAL;
- if (unlikely(!bo->bdev->funcs->verify_access)) {
- ret = -EPERM;
- goto out_unref;
- }
- ret = bo->bdev->funcs->verify_access(bo, filp);
+ ret = vmw_user_bo_verify_access(bo, tfile);
if (unlikely(ret != 0))
goto out_unref;
Looks great.
Reviewed-by: Zack Rusin
z
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Re: [PATCH 6/8] drm/vmwgfx: Inline ttm_bo_mmap() into vmwgfx driver
On 4/6/21 5:09 AM, Thomas Zimmermann wrote:
The vmwgfx driver is the only remaining user of ttm_bo_mmap(). Inline
the code. The internal helper ttm_bo_vm_lookup() is now also part of
vmwgfx as vmw_bo_vm_lookup().
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c | 54 ++--
1 file changed, 51 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c
index cb9975889e2f..3eaad00668f2 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c
@@ -27,6 +27,30 @@
#include "vmwgfx_drv.h"
+static struct ttm_buffer_object *vmw_bo_vm_lookup(struct ttm_device *bdev,
+ unsigned long offset,
+ unsigned long pages)
+{
+ struct drm_vma_offset_node *node;
+ struct ttm_buffer_object *bo = NULL;
+
+ drm_vma_offset_lock_lookup(bdev->vma_manager);
+
+ node = drm_vma_offset_lookup_locked(bdev->vma_manager, offset, pages);
+ if (likely(node)) {
+ bo = container_of(node, struct ttm_buffer_object,
+ base.vma_node);
+ bo = ttm_bo_get_unless_zero(bo);
+ }
+
+ drm_vma_offset_unlock_lookup(bdev->vma_manager);
+
+ if (!bo)
+ pr_err("Could not find buffer object to map\n");
It's not a big deal and I know it's been in the original, but since
you're already in there if you could change this to DRM_ERR that'd be
great. Either way:
Reviewed-by: Zack Rusin
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Re: [PATCH 2/2] drm/scheduler: Change scheduled fence track
+ dri-devel since GPU scheduler is a shared component.
On Wed, Apr 7, 2021 at 9:31 AM Roy Sun wrote:
>
> Update the timestamp of scheduled fence on HW
> completion of the previous fences
>
> This allow more accurate tracking of the fence
> execution in HW
>
> Signed-off-by: David M Nieto
> Signed-off-by: Roy Sun
> ---
> drivers/gpu/drm/scheduler/sched_main.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/scheduler/sched_main.c
> b/drivers/gpu/drm/scheduler/sched_main.c
> index 92d8de24d0a1..4e5d8d4af010 100644
> --- a/drivers/gpu/drm/scheduler/sched_main.c
> +++ b/drivers/gpu/drm/scheduler/sched_main.c
> @@ -515,7 +515,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler
> *sched)
> EXPORT_SYMBOL(drm_sched_resubmit_jobs);
>
> /**
> - * drm_sched_resubmit_jobs_ext - helper to relunch certain number of jobs
> from mirror ring list
> + * drm_sched_resubmit_jobs_ext - helper to relunch certain number of jobs
> from pending list
> *
> * @sched: scheduler instance
> * @max: job numbers to relaunch
> @@ -671,7 +671,7 @@ drm_sched_select_entity(struct drm_gpu_scheduler *sched)
> static struct drm_sched_job *
> drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
> {
> - struct drm_sched_job *job;
> + struct drm_sched_job *job, *next;
>
> /*
> * Don't destroy jobs while the timeout worker is running OR thread
> @@ -690,6 +690,13 @@ drm_sched_get_cleanup_job(struct drm_gpu_scheduler
> *sched)
> if (job && dma_fence_is_signaled(>s_fence->finished)) {
> /* remove job from pending_list */
> list_del_init(>list);
> + /* account for the next fence in the queue */
> + next = list_first_entry_or_null(>pending_list,
> + struct drm_sched_job, list);
> + if (next) {
> + next->s_fence->scheduled.timestamp =
> + job->s_fence->finished.timestamp;
> + }
> } else {
> job = NULL;
> /* queue timeout for next job */
> --
> 2.31.1
>
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Re: [PATCH] drm/amdgpu: add DMUB outbox event IRQ source define/complete/debug flag
On 2021-04-07 4:34 a.m., Jude Shih wrote:
[Why & How]
We use outbox interrupt that allows us to do the AUX via DMUB
Therefore, we need to add some irq source related definition
in the header files;
Signed-off-by: Jude Shih
Reviewed-by: Harry Wentland
Harry
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 963ecfd84347..480e07d83492 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -923,6 +923,7 @@ struct amdgpu_device {
struct amdgpu_irq_src pageflip_irq;
struct amdgpu_irq_src hpd_irq;
struct amdgpu_irq_src dmub_trace_irq;
+ struct amdgpu_irq_src dmub_outbox_irq;
/* rings */
u64 fence_context;
diff --git a/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
index e2bffcae273a..754170a86ea4 100644
--- a/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
+++ b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
@@ -1132,5 +1132,7 @@
#define DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 0x68
#define DCN_1_0__CTXID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 6
+#define DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT0x68 //
DMCUB_IHC_outbox1_ready_int IHC_DMCUB_outbox1_ready_int_ack
DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE24
Level/Pulse
+#define DCN_1_0__CTXID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT8
#endif // __IRQSRCS_DCN_1_0_H__
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[ANNOUNCE] libdrm 2.4.105
Alex Deucher (1): amdgpu: update marketing names Alistair Delva (1): xf86drm: fix null pointer deref in drmGetBufInfo Ashutosh Dixit (1): intel: Keep libdrm working without pread/pwrite ioctls Emil Velikov (3): xf86drm: cap number of reported devices by drmGetDevice(2) Revert "xf86drm: cap number of reported devices by drmGetDevice(2)" xf86drm: cap number of reported devices by drmGetDevice(2) Fabio Estevam (1): tests/util: Add mxsfb-drm driver Fang Tan (1): meson: use library() instead of shared_library(). Heiko Becker (1): meson: Also search for rst2man.py James Zhu (1): tests/amdgpu: add vcn test support for dimgrey_cavefish Jinzhou Su (1): test/amdgpu: remove static varible in Syncobj test Lang Yu (2): drm/tests/amdgpu: fix Metadata test failed issue tests/amdgpu: fix bo eviction test issue Leo Liu (4): amdgpu_drm: sync up with the latest amdgpu_drm.h based on drm-next (https://cgit.freedesktop.org/drm/drm) amdgpu: sync up amdgpu_drm.h with latest from kernel amdgpu: add function of INFO ioctl for querying video caps Bump version to 2.4.105 Simon Ser (4): xf86drmMode: add drmIsKMS xf86drm: warn about GEM handle reference counting xf86drmMode: introduce drmModeGetPropertyType xf86drmMode: set FB_MODIFIERS flag when modifiers are supplied Sonny Jiang (1): tests/amdgpu/vcn: clean abundant codes Tao Zhou (1): tests/amdgpu: add vcn test support for navy_flounder Tejas Upadhyay (3): intel: sync i915_pciids.h with kernel intel: add INTEL_ADLS_IDS to the pciids list intel: Add support for JSL Valentin Churavy (1): Use dep_rt in amdgpu/meson.build Victor Hugo Vianna Silva (1): Avoid some compiler errors for tests/util/pattern.c git tag: libdrm-2.4.105 https://dri.freedesktop.org/libdrm/libdrm-2.4.105.tar.xz SHA256: 1d1d024b7cadc63e2b59cddaca94f78864940ab440843841113fbac6afaf2a46 libdrm-2.4.105.tar.xz SHA512: 083a04af7208e58be21b89c6ebdbe2db3ba00cd29f0d271bd38bfe97dfca741edafddaaf9b5b95c20fac2c9b700434ea5b21397de26f7073169ad6f5b090f715 libdrm-2.4.105.tar.xz PGP: https://dri.freedesktop.org/libdrm/libdrm-2.4.105.tar.xz.sig ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amdgpu: Add show_fdinfo() interface
Am 07.04.21 um 15:31 schrieb Roy Sun:
Tracking devices, process info and fence info using
/proc/pid/fdinfo
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 247 +
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h | 51 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 1 +
6 files changed, 306 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index ee85e8aba636..d216b7ecb5d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -58,6 +58,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o
+amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
+
amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
# add asic specific block
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 616c85a01299..c2338a0dd1f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
#include "amdgpu_gfxhub.h"
#include "amdgpu_df.h"
#include "amdgpu_smuio.h"
+#include "amdgpu_fdinfo.h"
#define MAX_GPU_INSTANCE 16
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 4bcc03c4c6c5..07aed377dec8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -42,7 +42,7 @@
#include "amdgpu_irq.h"
#include "amdgpu_dma_buf.h"
#include "amdgpu_sched.h"
-
+#include "amdgpu_fdinfo.h"
#include "amdgpu_amdkfd.h"
#include "amdgpu_ras.h"
@@ -1691,6 +1691,9 @@ static const struct file_operations
amdgpu_driver_kms_fops = {
#ifdef CONFIG_COMPAT
.compat_ioctl = amdgpu_kms_compat_ioctl,
#endif
+#ifdef CONFIG_PROC_FS
+ .show_fdinfo = amdgpu_show_fdinfo
+#endif
};
int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
new file mode 100644
index ..72e61a89c0ea
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
@@ -0,0 +1,247 @@
Still no SPDX license tag.
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: David Nieto
+ * Roy Sun
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "amdgpu.h"
+#include "amdgpu_fdinfo.h"
+
+
+static const char *amdgpu_ip_name[AMDGPU_HW_IP_NUM] = {
+ [AMDGPU_HW_IP_GFX] = "gfx",
+ [AMDGPU_HW_IP_COMPUTE] = "compute",
+ [AMDGPU_HW_IP_DMA] = "dma",
+ [AMDGPU_HW_IP_UVD] = "dec",
+ [AMDGPU_HW_IP_VCE] = "enc",
+ [AMDGPU_HW_IP_UVD_ENC] = "enc_1",
+ [AMDGPU_HW_IP_VCN_DEC] = "dec",
+ [AMDGPU_HW_IP_VCN_ENC] = "enc",
+ [AMDGPU_HW_IP_VCN_JPEG] = "jpeg",
+};
+
+uint64_t amdgpu_get_proc_mem(struct drm_file *file, struct amdgpu_fpriv *fpriv)
+{
+ int id;
+ struct drm_gem_object *gobj;
+ uint64_t total = 0;
+
+ spin_lock(>table_lock);
+ idr_for_each_entry(>object_idr, gobj, id) {
+ struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
+ unsigned int domain = amdgpu_mem_type_to_domain(
+ bo->tbo.mem.mem_type);
+
+ if (domain == AMDGPU_GEM_DOMAIN_VRAM)
+ total += amdgpu_bo_size(bo);
Why
Re: [PATCH 2/2] drm/scheduler: Change scheduled fence track
Am 07.04.21 um 15:31 schrieb Roy Sun:
Update the timestamp of scheduled fence on HW
completion of the previous fences
This allow more accurate tracking of the fence
execution in HW
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
drivers/gpu/drm/scheduler/sched_main.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index 92d8de24d0a1..4e5d8d4af010 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -515,7 +515,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler
*sched)
EXPORT_SYMBOL(drm_sched_resubmit_jobs);
/**
- * drm_sched_resubmit_jobs_ext - helper to relunch certain number of jobs from
mirror ring list
+ * drm_sched_resubmit_jobs_ext - helper to relunch certain number of jobs from
pending list
s/relunch/relaunch/
With that nit pick fixed the patch is Reviewed-by: Christian König
*
* @sched: scheduler instance
* @max: job numbers to relaunch
@@ -671,7 +671,7 @@ drm_sched_select_entity(struct drm_gpu_scheduler *sched)
static struct drm_sched_job *
drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
{
- struct drm_sched_job *job;
+ struct drm_sched_job *job, *next;
/*
* Don't destroy jobs while the timeout worker is running OR thread
@@ -690,6 +690,13 @@ drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
if (job && dma_fence_is_signaled(>s_fence->finished)) {
/* remove job from pending_list */
list_del_init(>list);
+ /* account for the next fence in the queue */
+ next = list_first_entry_or_null(>pending_list,
+ struct drm_sched_job, list);
+ if (next) {
+ next->s_fence->scheduled.timestamp =
+ job->s_fence->finished.timestamp;
+ }
} else {
job = NULL;
/* queue timeout for next job */
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Re: [PATCH 1/2] drm/amdgpu: Fix size overflow
Am 07.04.21 um 15:04 schrieb xinhui pan: ttm->num_pages is uint32. Hit overflow when << PAGE_SHIFT directly Fix: 230c079fd (drm/ttm: make num_pages uint32_t) Signed-off-by: xinhui pan Reviewed-by: Christian König for the series. --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index fbaa4c148cca..936b3cfdde55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -830,7 +830,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, /* Allocate an SG array and squash pages into it */ r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, - ttm->num_pages << PAGE_SHIFT, + (u64)ttm->num_pages << PAGE_SHIFT, GFP_KERNEL); if (r) goto release_sg; ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/smu7: fix CAC setting on TOPAZ
We need to enable MC CAC for mclk switching to work.
Fixes: d765129a719f ("drm/amd/pm: correct sclk/mclk dpm enablement")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1561
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 301b6769f007..0541bfc81c1b 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1224,7 +1224,8 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr)
(hwmgr->chip_id == CHIP_POLARIS10) ||
(hwmgr->chip_id == CHIP_POLARIS11) ||
(hwmgr->chip_id == CHIP_POLARIS12) ||
- (hwmgr->chip_id == CHIP_TONGA))
+ (hwmgr->chip_id == CHIP_TONGA) ||
+ (hwmgr->chip_id == CHIP_TOPAZ))
PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN,
0x1);
--
2.30.2
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[PATCH 2/2] drm/scheduler: Change scheduled fence track
Update the timestamp of scheduled fence on HW
completion of the previous fences
This allow more accurate tracking of the fence
execution in HW
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
drivers/gpu/drm/scheduler/sched_main.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index 92d8de24d0a1..4e5d8d4af010 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -515,7 +515,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler
*sched)
EXPORT_SYMBOL(drm_sched_resubmit_jobs);
/**
- * drm_sched_resubmit_jobs_ext - helper to relunch certain number of jobs from
mirror ring list
+ * drm_sched_resubmit_jobs_ext - helper to relunch certain number of jobs from
pending list
*
* @sched: scheduler instance
* @max: job numbers to relaunch
@@ -671,7 +671,7 @@ drm_sched_select_entity(struct drm_gpu_scheduler *sched)
static struct drm_sched_job *
drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
{
- struct drm_sched_job *job;
+ struct drm_sched_job *job, *next;
/*
* Don't destroy jobs while the timeout worker is running OR thread
@@ -690,6 +690,13 @@ drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
if (job && dma_fence_is_signaled(>s_fence->finished)) {
/* remove job from pending_list */
list_del_init(>list);
+ /* account for the next fence in the queue */
+ next = list_first_entry_or_null(>pending_list,
+ struct drm_sched_job, list);
+ if (next) {
+ next->s_fence->scheduled.timestamp =
+ job->s_fence->finished.timestamp;
+ }
} else {
job = NULL;
/* queue timeout for next job */
--
2.31.1
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[PATCH 1/2] drm/amdgpu: Add show_fdinfo() interface
Tracking devices, process info and fence info using
/proc/pid/fdinfo
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 247 +
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h | 51 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 1 +
6 files changed, 306 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index ee85e8aba636..d216b7ecb5d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -58,6 +58,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o
+amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
+
amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
# add asic specific block
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 616c85a01299..c2338a0dd1f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
#include "amdgpu_gfxhub.h"
#include "amdgpu_df.h"
#include "amdgpu_smuio.h"
+#include "amdgpu_fdinfo.h"
#define MAX_GPU_INSTANCE 16
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 4bcc03c4c6c5..07aed377dec8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -42,7 +42,7 @@
#include "amdgpu_irq.h"
#include "amdgpu_dma_buf.h"
#include "amdgpu_sched.h"
-
+#include "amdgpu_fdinfo.h"
#include "amdgpu_amdkfd.h"
#include "amdgpu_ras.h"
@@ -1691,6 +1691,9 @@ static const struct file_operations
amdgpu_driver_kms_fops = {
#ifdef CONFIG_COMPAT
.compat_ioctl = amdgpu_kms_compat_ioctl,
#endif
+#ifdef CONFIG_PROC_FS
+ .show_fdinfo = amdgpu_show_fdinfo
+#endif
};
int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
new file mode 100644
index ..72e61a89c0ea
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
@@ -0,0 +1,247 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: David Nieto
+ * Roy Sun
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "amdgpu.h"
+#include "amdgpu_fdinfo.h"
+
+
+static const char *amdgpu_ip_name[AMDGPU_HW_IP_NUM] = {
+ [AMDGPU_HW_IP_GFX] = "gfx",
+ [AMDGPU_HW_IP_COMPUTE] = "compute",
+ [AMDGPU_HW_IP_DMA] = "dma",
+ [AMDGPU_HW_IP_UVD] = "dec",
+ [AMDGPU_HW_IP_VCE] = "enc",
+ [AMDGPU_HW_IP_UVD_ENC] = "enc_1",
+ [AMDGPU_HW_IP_VCN_DEC] = "dec",
+ [AMDGPU_HW_IP_VCN_ENC] = "enc",
+ [AMDGPU_HW_IP_VCN_JPEG] = "jpeg",
+};
+
+uint64_t amdgpu_get_proc_mem(struct drm_file *file, struct amdgpu_fpriv *fpriv)
+{
+ int id;
+ struct drm_gem_object *gobj;
+ uint64_t total = 0;
+
+ spin_lock(>table_lock);
+ idr_for_each_entry(>object_idr, gobj, id) {
+ struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
+ unsigned int domain = amdgpu_mem_type_to_domain(
+ bo->tbo.mem.mem_type);
+
+ if (domain == AMDGPU_GEM_DOMAIN_VRAM)
+ total += amdgpu_bo_size(bo);
+ }
+ spin_unlock(>table_lock);
+
+ if (fpriv->vm.process_info) {
+
[PATCH 2/2] drm/radeon: Fix size overflow
ttm->num_pages is uint32. Hit overflow when << PAGE_SHIFT directly
Signed-off-by: xinhui pan
---
drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
index 2a61cff325e4..b3fb84b45923 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -360,7 +360,7 @@ static int radeon_ttm_tt_pin_userptr(struct ttm_device
*bdev, struct ttm_tt *ttm
if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
/* check that we only pin down anonymous memory
to prevent problems with writeback */
- unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
+ unsigned long end = gtt->userptr + (u64)ttm->num_pages *
PAGE_SIZE;
struct vm_area_struct *vma;
vma = find_vma(gtt->usermm, gtt->userptr);
if (!vma || vma->vm_file || vma->vm_end < end)
@@ -382,7 +382,7 @@ static int radeon_ttm_tt_pin_userptr(struct ttm_device
*bdev, struct ttm_tt *ttm
} while (pinned < ttm->num_pages);
r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
- ttm->num_pages << PAGE_SHIFT,
+ (u64)ttm->num_pages << PAGE_SHIFT,
GFP_KERNEL);
if (r)
goto release_sg;
--
2.25.1
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[PATCH 1/2] drm/amdgpu: Fix size overflow
ttm->num_pages is uint32. Hit overflow when << PAGE_SHIFT directly Fix: 230c079fd (drm/ttm: make num_pages uint32_t) Signed-off-by: xinhui pan --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index fbaa4c148cca..936b3cfdde55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -830,7 +830,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, /* Allocate an SG array and squash pages into it */ r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, - ttm->num_pages << PAGE_SHIFT, + (u64)ttm->num_pages << PAGE_SHIFT, GFP_KERNEL); if (r) goto release_sg; -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Fix size overflow
We need this for radeon too. On 4/7/21 2:00 PM, Christian König wrote: Am 07.04.21 um 13:35 schrieb xinhui pan: ttm->num_pages is uint32. Hit overflow when << PAGE_SHIFT directly Fix: 230c079fd (drm/ttm: make num_pages uint32_t) Signed-off-by: xinhui pan --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index fbaa4c148cca..01a5c487505c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -830,7 +830,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, /* Allocate an SG array and squash pages into it */ r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, - ttm->num_pages << PAGE_SHIFT, + ttm->num_pages * (1ULL << PAGE_SHIFT), Good catch, but please make this ((u64)ttm->num_pages) << PAGE_SHIFT Christian. GFP_KERNEL); if (r) goto release_sg; ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Cnirmoy.das%40amd.com%7Cbc310f437f814ed8f93b08d8f9bcbb55%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637533936286970681%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=8Q2Qbnd0JK288d5PXys%2B%2B8ADCKa9xshtE5kLwRprhJc%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Fix size overflow
Am 07.04.21 um 13:35 schrieb xinhui pan: ttm->num_pages is uint32. Hit overflow when << PAGE_SHIFT directly Fix: 230c079fd (drm/ttm: make num_pages uint32_t) Signed-off-by: xinhui pan --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index fbaa4c148cca..01a5c487505c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -830,7 +830,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, /* Allocate an SG array and squash pages into it */ r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, - ttm->num_pages << PAGE_SHIFT, + ttm->num_pages * (1ULL << PAGE_SHIFT), Good catch, but please make this ((u64)ttm->num_pages) << PAGE_SHIFT Christian. GFP_KERNEL); if (r) goto release_sg; ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: Fix size overflow
ttm->num_pages is uint32. Hit overflow when << PAGE_SHIFT directly Fix: 230c079fd (drm/ttm: make num_pages uint32_t) Signed-off-by: xinhui pan --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index fbaa4c148cca..01a5c487505c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -830,7 +830,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, /* Allocate an SG array and squash pages into it */ r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, - ttm->num_pages << PAGE_SHIFT, + ttm->num_pages * (1ULL << PAGE_SHIFT), GFP_KERNEL); if (r) goto release_sg; -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 3/8] drm/amdgpu: Implement mmap as GEM object function
Hi,
Am 06.04.21 um 17:27 schrieb Felix Kuehling:
Am 2021-04-06 um 6:38 a.m. schrieb Thomas Zimmermann:
Hi
Am 06.04.21 um 11:35 schrieb Christian König:
Am 06.04.21 um 11:08 schrieb Thomas Zimmermann:
Moving the driver-specific mmap code into a GEM object function allows
for using DRM helpers for various mmap callbacks.
This change resolves several inconsistencies between regular mmap and
prime-based mmap. The vm_ops field in vma is now set for all mmap'ed
areas. Previously it way only set for regular mmap calls, prime-based
mmap used TTM's default vm_ops. The check for kfd_bo has been taken
from amdgpu_verify_access(), which is not called any longer and has
been removed.
As a side effect, amdgpu_ttm_vm_ops and amdgpu_ttm_fault() are now
implemented in amdgpu's GEM code.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 46 -
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 64 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 71
-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 -
6 files changed, 66 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index e0c4f7c7f1b9..19c5ab08d9ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -42,52 +42,6 @@
#include
#include
-/**
- * amdgpu_gem_prime_mmap - _driver.gem_prime_mmap implementation
- * @obj: GEM BO
- * @vma: Virtual memory area
- *
- * Sets up a userspace mapping of the BO's memory in the given
- * virtual memory area.
- *
- * Returns:
- * 0 on success or a negative error code on failure.
- */
-int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
- struct vm_area_struct *vma)
-{
- struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
- struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
- unsigned asize = amdgpu_bo_size(bo);
- int ret;
-
- if (!vma->vm_file)
- return -ENODEV;
-
- if (adev == NULL)
- return -ENODEV;
-
- /* Check for valid size. */
- if (asize < vma->vm_end - vma->vm_start)
- return -EINVAL;
-
- if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
- (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
- return -EPERM;
- }
- vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
-
- /* prime mmap does not need to check access, so allow here */
- ret = drm_vma_node_allow(>vma_node,
vma->vm_file->private_data);
- if (ret)
- return ret;
-
- ret = ttm_bo_mmap(vma->vm_file, vma, >mman.bdev);
- drm_vma_node_revoke(>vma_node, vma->vm_file->private_data);
-
- return ret;
-}
-
static int
__dma_resv_make_exclusive(struct dma_resv *obj)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
index 39b5b9616fd8..3e93b9b407a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
@@ -31,8 +31,6 @@ struct drm_gem_object
*amdgpu_gem_prime_import(struct drm_device *dev,
struct dma_buf *dma_buf);
bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
struct amdgpu_bo *bo);
-int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
- struct vm_area_struct *vma);
extern const struct dma_buf_ops amdgpu_dmabuf_ops;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 76f48f79c70b..e96d2758f4bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1656,7 +1656,7 @@ static const struct file_operations
amdgpu_driver_kms_fops = {
.flush = amdgpu_flush,
.release = drm_release,
.unlocked_ioctl = amdgpu_drm_ioctl,
- .mmap = amdgpu_mmap,
+ .mmap = drm_gem_mmap,
.poll = drm_poll,
.read = drm_read,
#ifdef CONFIG_COMPAT
@@ -1719,7 +1719,7 @@ static const struct drm_driver
amdgpu_kms_driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = amdgpu_gem_prime_import,
- .gem_prime_mmap = amdgpu_gem_prime_mmap,
+ .gem_prime_mmap = drm_gem_prime_mmap,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index fb7171e5507c..fe93faad05f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -41,6 +41,36 @@
static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
+static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
Please name that function amdgpu_gem_fault or amdgpu_gem_object_fault
+{
+ struct ttm_buffer_object *bo =
Re: [PATCH] drm/amd/pm: convert sysfs snprintf to sysfs_emit
Am 06.04.21 um 16:11 schrieb Carlis: From: Xuezhi Zhang Fix the following coccicheck warning: drivers/gpu/drm/amd/pm//amdgpu_pm.c:1940:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:1978:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2022:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:294:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:154:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:496:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:512:9-17: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:1740:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:1667:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2074:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2047:9-17: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2768:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2738:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2442:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:3246:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:3253:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2458:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:3047:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:3133:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:3209:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:3216:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2410:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2496:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2470:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2426:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2965:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:2972:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:3006:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm//amdgpu_pm.c:3013:8-16: WARNING: use scnprintf or sprintf Signed-off-by: Xuezhi Zhang Acked-by: Christian König --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 58 +++--- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 5fa65f191a37..2777966ec1ca 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -151,7 +151,7 @@ static ssize_t amdgpu_get_power_dpm_state(struct device *dev, pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); - return snprintf(buf, PAGE_SIZE, "%s\n", + return sysfs_emit(buf, "%s\n", (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); } @@ -291,7 +291,7 @@ static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); - return snprintf(buf, PAGE_SIZE, "%s\n", + return sysfs_emit(buf, "%s\n", (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : @@ -493,7 +493,7 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev, if (i == data.nums) i = -EINVAL; - return snprintf(buf, PAGE_SIZE, "%d\n", i); + return sysfs_emit(buf, "%d\n", i); } static ssize_t amdgpu_get_pp_force_state(struct device *dev, @@ -509,7 +509,7 @@ static ssize_t amdgpu_get_pp_force_state(struct device *dev, if (adev->pp_force_state_enabled) return amdgpu_get_pp_cur_state(dev, attr, buf); else - return snprintf(buf, PAGE_SIZE, "\n"); + return sysfs_emit(buf, "\n"); } static ssize_t amdgpu_set_pp_force_state(struct device *dev, @@ -1664,7 +1664,7 @@ static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); - return snprintf(buf, PAGE_SIZE, "%d\n", value); + return sysfs_emit(buf, "%d\n", value); } static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, @@ -1737,7 +1737,7 @@ static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, pm_runtime_mark_last_busy(ddev->dev); pm_runtime_put_autosuspend(ddev->dev); - return snprintf(buf, PAGE_SIZE, "%d\n", value);
Re: Unexpected multihop in swaput - likely driver bug.
What hardware are you using and how do you exactly trigger this? Thanks, Christian. Am 07.04.21 um 11:30 schrieb Mikhail Gavrilov: Hi! During the 5.12 testing cycle I observed the repeatable bug when launching heavy graphic applications. The kernel log is flooded with the message "Unexpected multihop in swaput - likely driver bug.". Trace: [ 8707.814899] [ cut here ] [ 8707.814920] Unexpected multihop in swaput - likely driver bug. [ 8707.814998] WARNING: CPU: 19 PID: 28231 at drivers/gpu/drm/ttm/ttm_bo.c:1484 ttm_bo_swapout+0x40b/0x420 [ttm] [ 8707.815011] Modules linked in: tun uinput snd_seq_dummy rfcomm snd_hrtimer netconsole nft_objref nf_conntrack_netbios_ns nf_conntrack_broadcast nft_fib_inet nft_fib_ipv4 nft_fib_ipv6 nft_fib nft_reject_inet nf_reject_ipv4 nf_reject_ipv6 nft_reject nft_ct nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ip_set nf_tables nfnetlink cmac bnep sunrpc vfat fat hid_logitech_hidpp hid_logitech_dj intel_rapl_msr snd_hda_codec_realtek intel_rapl_common mt76x2u snd_hda_codec_generic mt76x2_common mt76x02_usb iwlmvm ledtrig_audio snd_hda_codec_hdmi mt76_usb mt76x02_lib snd_hda_intel mt76 snd_intel_dspcfg snd_intel_sdw_acpi mac80211 joydev snd_usb_audio snd_hda_codec uvcvideo edac_mce_amd videobuf2_vmalloc snd_hda_core snd_usbmidi_lib videobuf2_memops snd_hwdep iwlwifi snd_rawmidi btusb videobuf2_v4l2 kvm_amd snd_seq videobuf2_common btrtl btbcm videodev btintel snd_seq_device kvm mc cfg80211 bluetooth snd_pcm libarc4 eeepc_wmi snd_timer asus_wmi irqbypass xpad sp5100_tco [ 8707.815065] sparse_keymap ecdh_generic ff_memless video ecc wmi_bmof i2c_piix4 snd rapl k10temp soundcore rfkill acpi_cpufreq ip_tables amdgpu drm_ttm_helper ttm iommu_v2 gpu_sched drm_kms_helper crct10dif_pclmul crc32_pclmul crc32c_intel cec drm ghash_clmulni_intel igb ccp nvme dca nvme_core i2c_algo_bit wmi pinctrl_amd fuse [ 8707.815096] CPU: 19 PID: 28231 Comm: kworker/u64:1 Tainted: G W- --- 5.12.0-0.rc6.184.fc35.x86_64+debug #1 [ 8707.815101] Hardware name: System manufacturer System Product Name/ROG STRIX X570-I GAMING, BIOS 3603 03/20/2021 [ 8707.815106] Workqueue: ttm_swap ttm_shrink_work [ttm] [ 8707.815114] RIP: 0010:ttm_bo_swapout+0x40b/0x420 [ttm] [ 8707.815122] Code: 10 00 00 48 c1 e2 0c 48 c1 e6 0c e8 3f 37 fa c8 e9 71 fe ff ff 83 f8 b8 0f 85 a9 fe ff ff 48 c7 c7 28 32 37 c0 e8 02 2b 98 c9 <0f> 0b e9 96 fe ff ff 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 0f [ 8707.815126] RSP: 0018:a306d20e7d58 EFLAGS: 00010292 [ 8707.815130] RAX: 0032 RBX: c0379260 RCX: 0027 [ 8707.815133] RDX: 918c091daae8 RSI: 0001 RDI: 918c091daae0 [ 8707.815136] RBP: 918602210058 R08: R09: [ 8707.815138] R10: a306d20e7b90 R11: 918c2e2fffe8 R12: ffb8 [ 8707.815141] R13: c03792a0 R14: 9186022102c0 R15: 0001 [ 8707.815145] FS: () GS:918c0900() knlGS: [ 8707.815148] CS: 0010 DS: ES: CR0: 80050033 [ 8707.815151] CR2: 325c84d12000 CR3: 000776c28000 CR4: 00350ee0 [ 8707.815154] Call Trace: [ 8707.815164] ttm_shrink+0xa6/0xe0 [ttm] [ 8707.815171] ttm_shrink_work+0x36/0x40 [ttm] [ 8707.815177] process_one_work+0x2b0/0x5e0 [ 8707.815185] worker_thread+0x55/0x3c0 [ 8707.815188] ? process_one_work+0x5e0/0x5e0 [ 8707.815192] kthread+0x13a/0x150 [ 8707.815196] ? __kthread_bind_mask+0x60/0x60 [ 8707.815199] ret_from_fork+0x22/0x30 [ 8707.815207] irq event stamp: 0 [ 8707.815209] hardirqs last enabled at (0): [<>] 0x0 [ 8707.815213] hardirqs last disabled at (0): [] copy_process+0x91b/0x1e10 [ 8707.815218] softirqs last enabled at (0): [] copy_process+0x91b/0x1e10 [ 8707.815222] softirqs last disabled at (0): [<>] 0x0 [ 8707.815224] ---[ end trace 29252aa87289bbaa ]--- Full kernel log: https://pastebin.com/mmAxwBYc $ /usr/src/kernels/`uname -r`/scripts/faddr2line /lib/debug/lib/modules/`uname -r`/kernel/drivers/gpu/drm/ttm/ttm.ko.debug ttm_bo_swapout+0x40b ttm_bo_swapout+0x40b/0x420: ttm_bo_swapout at /usr/src/debug/kernel-5.12-rc6/linux-5.12.0-0.rc6.184.fc35.x86_64/drivers/gpu/drm/ttm/ttm_bo.c:1484 (discriminator 1) $ git blame drivers/gpu/drm/ttm/ttm_bo.c -L 1475,1494 Blaming lines: 1% (20/1530), done. ebdf565169af0 (Dave Airlie 2020-10-29 13:58:52 +1000 1475) memset(, 0, sizeof(hop)); ba4e7d973dd09 (Thomas Hellstrom 2009-06-10 15:20:19 +0200 1476) ba4e7d973dd09 (Thomas Hellstrom 2009-06-10 15:20:19 +0200 1477) evict_mem = bo->mem; ba4e7d973dd09 (Thomas Hellstrom 2009-06-10 15:20:19 +0200 1478) evict_mem.mm_node = NULL; ce65b874001d7 (Christian König 2020-09-30 16:44:16 +0200 1479) evict_mem.placement = 0; ba4e7d973dd09 (Thomas Hellstrom 2009-06-10 15:20:19 +0200 1480) evict_mem.mem_type = TTM_PL_SYSTEM; ba4e7d973dd09 (Thomas Hellstrom 2009-06-10
Re: [pull] amdgpu, radeon, ttm, sched drm-next-5.13
Yes, that was the one I was talking about. Ok, good to know that this is fixed. Regards, Christian. Am 07.04.21 um 10:50 schrieb Chen, Guchun: [AMD Public Use] Hi Felix and Christian, If the regression you are talking about is the NULL pointer problem when running KFD tests, it should fixed by below patch in this series. drm/amdgpu: fix NULL pointer dereference Regards, Guchun -Original Message- From: amd-gfx On Behalf Of Christian König Sent: Wednesday, April 7, 2021 2:57 PM To: Kuehling, Felix ; Deucher, Alexander ; amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; airl...@gmail.com; daniel.vet...@ffwll.ch Subject: Re: [pull] amdgpu, radeon, ttm, sched drm-next-5.13 Am 06.04.21 um 17:42 schrieb Felix Kuehling: Am 2021-04-01 um 6:29 p.m. schrieb Alex Deucher: Hi Dave, Daniel, New stuff for 5.13. There are two small patches for ttm and scheduler that were dependencies for amdgpu changes. The following changes since commit 2cbcb78c9ee5520c8d836c7ff57d1b60ebe8e9b7: Merge tag 'amd-drm-next-5.13-2021-03-23' of https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit lab.freedesktop.org%2Fagd5f%2Flinuxdata=04%7C01%7Cguchun.chen%40 amd.com%7C51d1cbcf7ccc43854abb08d8f99250d8%7C3dd8961fe4884e608e11a82d 994e183d%7C0%7C0%7C637533754128113017%7CUnknown%7CTWFpbGZsb3d8eyJWIjo iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000 p;sdata=FcdoL9w5LhBZ849ctXPudr%2BBQnnm7Oiq3pz5X7LGGk4%3Dreserved =0 into drm-next (2021-03-26 15:53:21 +0100) are available in the Git repository at: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit lab.freedesktop.org%2Fagd5f%2Flinux.gitdata=04%7C01%7Cguchun.che n%40amd.com%7C51d1cbcf7ccc43854abb08d8f99250d8%7C3dd8961fe4884e608e11 a82d994e183d%7C0%7C0%7C637533754128113017%7CUnknown%7CTWFpbGZsb3d8eyJ WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C100 0sdata=N4JIk%2BEgzleaKYaxvdtT7TR1ZsS6FGsIGpDDUqiQiLw%3Drese rved=0 tags/amd-drm-next-5.13-2021-04-01 for you to fetch changes up to ef95d2a98d642a537190d73c45ae3c308afee890: drm/amdgpu/display: fix warning on 32 bit in dmub (2021-04-01 17:32:32 -0400) amd-drm-next-5.13-2021-04-01: amdgpu: - Re-enable GPU reset on VanGogh - Enable DPM flags for SMART_SUSPEND and MAY_SKIP_RESUME - Disentangle HG from vga_switcheroo - S0ix fixes - W=1 fixes - Resource iterator fixes - DMCUB updates - UBSAN fixes - More PM API cleanup - Aldebaran updates - Modifier fixes - Enable VCN load balancing with asymmetric engines - Rework BO structs - Aldebaran reset support - Initial LTTPR display work - Display MALL fixes - Fall back to YCbCr420 when YCbCr444 fails - SR-IOV fixes - Misc cleanups and fixes radeon: - Typo fixes ttm: - Handle cached requests (required for Aldebaran) scheduler: - Fix runqueue selection when changing priorities (required to fix VCN load balancing) Alex Deucher (20): drm/amdgpu/display/dm: add missing parameter documentation drm/amdgpu: Add additional Sienna Cichlid PCI ID drm/amdgpu: add a dev_pm_ops prepare callback (v2) drm/amdgpu: enable DPM_FLAG_MAY_SKIP_RESUME and DPM_FLAG_SMART_SUSPEND flags (v2) drm/amdgpu: disentangle HG systems from vgaswitcheroo drm/amdgpu: rework S3/S4/S0ix state handling drm/amdgpu: don't evict vram on APUs for suspend to ram (v4) drm/amdgpu: clean up non-DC suspend/resume handling drm/amdgpu: move s0ix check into amdgpu_device_ip_suspend_phase2 (v3) drm/amdgpu: re-enable suspend phase 2 for S0ix drm/amdgpu/swsmu: skip gfx cgpg on s0ix suspend drm/amdgpu: update comments about s0ix suspend/resume drm/amdgpu: drop S0ix checks around CG/PG in suspend drm/amdgpu: skip kfd suspend/resume for S0ix drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x drm/amdgpu/display: fix memory leak for dimgrey cavefish drm/amdgpu/pm: mark pcie link/speed arrays as const drm/amdgpu/pm: bail on sysfs/debugfs queries during platform suspend drm/amdgpu/vangogh: don't check for dpm in is_dpm_running when in suspend drm/amdgpu/display: fix warning on 32 bit in dmub Alex Sierra (2): drm/amdgpu: replace per_device_list by array drm/amdgpu: ih reroute for newer asics than vega20 Alvin Lee (1): drm/amd/display: Change input parameter for set_drr Anson Jacob (2): drm/amd/display: Fix UBSAN: shift-out-of-bounds warning drm/amd/display: Removing unused code from dmub_cmd.h Anthony Koo (2): drm/amd/display: [FW Promotion] Release 0.0.57 drm/amd/display: [FW Promotion] Release 0.0.58 Aric Cyr (2): drm/amd/display: 3.2.128 drm/amd/display: 3.2.129 Arnd Bergmann (3): amdgpu: avoid incorrect %hu format string amdgpu: fix gcc
Re: [PATCH 0/4] Refine GPU recovery sequence to enhance its stability
Hi Andrey, Am 06.04.21 um 23:22 schrieb Andrey Grodzovsky: Hey Christian, Denis, see bellow - On 2021-04-06 6:34 a.m., Christian König wrote: Hi Andrey, well good question. My job is to watch over the implementation and design and while I always help I can adjust anybodies schedule. Is the patch to print a warning when the hardware is accessed without holding the locks merged yet? If not then that would probably be a good starting point. It's merged into amd-staging-drm-next and since I work on drm-misc-next I will cherry-pick it into there. Ok good to know, I haven't tracked that one further. Then we would need to unify this with the SRCU to make sure that we have both the reset lock as well as block the hotplug code from reusing the MMIO space. In my understanding there is a significant difference between handling of GPU reset and unplug - while GPU reset use case requires any HW accessing code to block and wait for the reset to finish and then proceed, hot-unplug is permanent and hence no need to wait and proceed but rather abort at once. Yes, absolutely correct. This why I think that in any place we already check for device reset we should also add a check for hot-unplug but the handling would be different in that for hot-unplug we would abort instead of keep waiting. Yes, that's the rough picture in my head as well. Essentially Daniels patch of having an amdgpu_device_hwaccess_begin()/_end() was the right approach. You just can't do it in the top level IOCTL handler, but rather need it somewhere between front end and backend. Similar to handling device reset for unplug we obviously also need to stop and block any MMIO accesses once device is unplugged and, as Daniel Vetter mentioned - we have to do it before finishing pci_remove (early device fini) and not later (when last device reference is dropped from user space) in order to prevent reuse of MMIO space we still access by other hot plugging devices. As in device reset case we need to cancel all delay works, stop drm schedule, complete all unfinished fences(both HW and scheduler fences). While you stated strong objection to force signalling scheduler fences from GPU reset, quote: "you can't signal the dma_fence waiting. Waiting for a dma_fence also means you wait for the GPU reset to finish. When we would signal the dma_fence during the GPU reset then we would run into memory corruption because the hardware jobs running after the GPU reset would access memory which is already freed." To my understating this is a key difference with hot-unplug, the device is gone, all those concerns are irrelevant and hence we can actually force signal scheduler fences (setting and error to them before) to force completion of any waiting clients such as possibly IOCTLs or async page flips e.t.c. Yes, absolutely correct. That's what I also mentioned to Daniel. When we are able to nuke the device and any memory access it might do we can also signal the fences. Beyond blocking all delayed works and scheduler threads we also need to guarantee no IOCTL can access MMIO post device unplug OR in flight IOCTLs are done before we finish pci_remove (amdgpu_pci_remove for us). For this I suggest we do something like what we worked on with Takashi Iwai the ALSA maintainer recently when he helped implementing PCI BARs move support for snd_hda_intel. Take a look at https://cgit.freedesktop.org/~agrodzov/linux/commit/?h=yadro/pcie_hotplug/movable_bars_v9.1=cbaa324799718e2b828a8c7b5b001dd896748497 and https://cgit.freedesktop.org/~agrodzov/linux/commit/?h=yadro/pcie_hotplug/movable_bars_v9.1=e36365d9ab5bbc30bdc221ab4b3437de34492440 We also had same issue there, how to prevent MMIO accesses while the BARs are migrating. What was done there is a refcount was added to count all IOCTLs in flight, for any in flight IOCTL the BAR migration handler would block for the refcount to drop to 0 before it would proceed, for any later IOCTL it stops and wait if device is in migration state. We even don't need the wait part, nothing to wait for, we just return with -ENODEV for this case. This is essentially what the DRM SRCU is doing as well. For the hotplug case we could do this in the toplevel since we can signal the fence and don't need to block memory management. But I'm not sure, maybe we should handle it the same way as reset or maybe we should have it at the top level. Regards, Christian. The above approach should allow us to wait for all the IOCTLs in flight, together with stopping scheduler threads and cancelling and flushing all in flight work items and timers i think It should give as full solution for the hot-unplug case of preventing any MMIO accesses post device pci_remove. Let me know what you think guys. Andrey And then testing, testing, testing to see if we have missed something. Christian. Am 05.04.21 um 19:58 schrieb Andrey Grodzovsky: Denis, Christian, are there
Re: [amdgpu] Compute kernels still run when the host process exit?
Am 01.04.21 um 20:22 schrieb Alex Deucher: On Thu, Apr 1, 2021 at 10:08 AM Smith John wrote: Hi, when I killed an OpenCL host process, the kernels it launched were not terminated, and still run. My OpenCL runtime is AMDGPU-PRO 20.20. OS Ubuntu 18.04.5 with Linux Kernel 5.4.53 I was wondering if it was a bug or the driver did not implement this "watchdog" mechanism. In general, once you issue work on the GPU it has to run to completion. It is not stopped if the application that issued it goes away. Well that is not 100% correct. When the job has already been pushed to the hardware it indeed runs till the end. But when the job is still in the scheduler and the process which has submitted it is killed we also throw away the job. This obviously only counts for the classic stack and not for the KFD. Christian. Alex ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Unexpected multihop in swaput - likely driver bug.
Hi! During the 5.12 testing cycle I observed the repeatable bug when launching heavy graphic applications. The kernel log is flooded with the message "Unexpected multihop in swaput - likely driver bug.". Trace: [ 8707.814899] [ cut here ] [ 8707.814920] Unexpected multihop in swaput - likely driver bug. [ 8707.814998] WARNING: CPU: 19 PID: 28231 at drivers/gpu/drm/ttm/ttm_bo.c:1484 ttm_bo_swapout+0x40b/0x420 [ttm] [ 8707.815011] Modules linked in: tun uinput snd_seq_dummy rfcomm snd_hrtimer netconsole nft_objref nf_conntrack_netbios_ns nf_conntrack_broadcast nft_fib_inet nft_fib_ipv4 nft_fib_ipv6 nft_fib nft_reject_inet nf_reject_ipv4 nf_reject_ipv6 nft_reject nft_ct nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ip_set nf_tables nfnetlink cmac bnep sunrpc vfat fat hid_logitech_hidpp hid_logitech_dj intel_rapl_msr snd_hda_codec_realtek intel_rapl_common mt76x2u snd_hda_codec_generic mt76x2_common mt76x02_usb iwlmvm ledtrig_audio snd_hda_codec_hdmi mt76_usb mt76x02_lib snd_hda_intel mt76 snd_intel_dspcfg snd_intel_sdw_acpi mac80211 joydev snd_usb_audio snd_hda_codec uvcvideo edac_mce_amd videobuf2_vmalloc snd_hda_core snd_usbmidi_lib videobuf2_memops snd_hwdep iwlwifi snd_rawmidi btusb videobuf2_v4l2 kvm_amd snd_seq videobuf2_common btrtl btbcm videodev btintel snd_seq_device kvm mc cfg80211 bluetooth snd_pcm libarc4 eeepc_wmi snd_timer asus_wmi irqbypass xpad sp5100_tco [ 8707.815065] sparse_keymap ecdh_generic ff_memless video ecc wmi_bmof i2c_piix4 snd rapl k10temp soundcore rfkill acpi_cpufreq ip_tables amdgpu drm_ttm_helper ttm iommu_v2 gpu_sched drm_kms_helper crct10dif_pclmul crc32_pclmul crc32c_intel cec drm ghash_clmulni_intel igb ccp nvme dca nvme_core i2c_algo_bit wmi pinctrl_amd fuse [ 8707.815096] CPU: 19 PID: 28231 Comm: kworker/u64:1 Tainted: G W- --- 5.12.0-0.rc6.184.fc35.x86_64+debug #1 [ 8707.815101] Hardware name: System manufacturer System Product Name/ROG STRIX X570-I GAMING, BIOS 3603 03/20/2021 [ 8707.815106] Workqueue: ttm_swap ttm_shrink_work [ttm] [ 8707.815114] RIP: 0010:ttm_bo_swapout+0x40b/0x420 [ttm] [ 8707.815122] Code: 10 00 00 48 c1 e2 0c 48 c1 e6 0c e8 3f 37 fa c8 e9 71 fe ff ff 83 f8 b8 0f 85 a9 fe ff ff 48 c7 c7 28 32 37 c0 e8 02 2b 98 c9 <0f> 0b e9 96 fe ff ff 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 0f [ 8707.815126] RSP: 0018:a306d20e7d58 EFLAGS: 00010292 [ 8707.815130] RAX: 0032 RBX: c0379260 RCX: 0027 [ 8707.815133] RDX: 918c091daae8 RSI: 0001 RDI: 918c091daae0 [ 8707.815136] RBP: 918602210058 R08: R09: [ 8707.815138] R10: a306d20e7b90 R11: 918c2e2fffe8 R12: ffb8 [ 8707.815141] R13: c03792a0 R14: 9186022102c0 R15: 0001 [ 8707.815145] FS: () GS:918c0900() knlGS: [ 8707.815148] CS: 0010 DS: ES: CR0: 80050033 [ 8707.815151] CR2: 325c84d12000 CR3: 000776c28000 CR4: 00350ee0 [ 8707.815154] Call Trace: [ 8707.815164] ttm_shrink+0xa6/0xe0 [ttm] [ 8707.815171] ttm_shrink_work+0x36/0x40 [ttm] [ 8707.815177] process_one_work+0x2b0/0x5e0 [ 8707.815185] worker_thread+0x55/0x3c0 [ 8707.815188] ? process_one_work+0x5e0/0x5e0 [ 8707.815192] kthread+0x13a/0x150 [ 8707.815196] ? __kthread_bind_mask+0x60/0x60 [ 8707.815199] ret_from_fork+0x22/0x30 [ 8707.815207] irq event stamp: 0 [ 8707.815209] hardirqs last enabled at (0): [<>] 0x0 [ 8707.815213] hardirqs last disabled at (0): [] copy_process+0x91b/0x1e10 [ 8707.815218] softirqs last enabled at (0): [] copy_process+0x91b/0x1e10 [ 8707.815222] softirqs last disabled at (0): [<>] 0x0 [ 8707.815224] ---[ end trace 29252aa87289bbaa ]--- Full kernel log: https://pastebin.com/mmAxwBYc $ /usr/src/kernels/`uname -r`/scripts/faddr2line /lib/debug/lib/modules/`uname -r`/kernel/drivers/gpu/drm/ttm/ttm.ko.debug ttm_bo_swapout+0x40b ttm_bo_swapout+0x40b/0x420: ttm_bo_swapout at /usr/src/debug/kernel-5.12-rc6/linux-5.12.0-0.rc6.184.fc35.x86_64/drivers/gpu/drm/ttm/ttm_bo.c:1484 (discriminator 1) $ git blame drivers/gpu/drm/ttm/ttm_bo.c -L 1475,1494 Blaming lines: 1% (20/1530), done. ebdf565169af0 (Dave Airlie 2020-10-29 13:58:52 +1000 1475) memset(, 0, sizeof(hop)); ba4e7d973dd09 (Thomas Hellstrom 2009-06-10 15:20:19 +0200 1476) ba4e7d973dd09 (Thomas Hellstrom 2009-06-10 15:20:19 +0200 1477) evict_mem = bo->mem; ba4e7d973dd09 (Thomas Hellstrom 2009-06-10 15:20:19 +0200 1478) evict_mem.mm_node = NULL; ce65b874001d7 (Christian König 2020-09-30 16:44:16 +0200 1479) evict_mem.placement = 0; ba4e7d973dd09 (Thomas Hellstrom 2009-06-10 15:20:19 +0200 1480) evict_mem.mem_type = TTM_PL_SYSTEM; ba4e7d973dd09 (Thomas Hellstrom 2009-06-10 15:20:19 +0200 1481) ebdf565169af0 (Dave Airlie 2020-10-29 13:58:52 +1000 1482) ret = ttm_bo_handle_move_mem(bo, _mem, true, , );
Re: [PATCH] drm/radeon/ttm: Fix memory leak userptr pages
Am 07.04.21 um 09:47 schrieb Daniel Gomez: On Tue, 6 Apr 2021 at 22:56, Alex Deucher wrote: On Mon, Mar 22, 2021 at 6:34 AM Christian König wrote: Hi Daniel, Am 22.03.21 um 10:38 schrieb Daniel Gomez: On Fri, 19 Mar 2021 at 21:29, Felix Kuehling wrote: This caused a regression in kfdtest in a large-buffer stress test after memory allocation for user pages fails: I'm sorry to hear that. BTW, I guess you meant amdgpu leak patch and not this one. Just some background for the mem leak patch if helps to understand this: The leak was introduce here: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ftorvalds%2Flinux.git%2Fcommit%2F%3Fid%3D0b988ca1c7c4c73983b4ea96ef7c2af2263c87ebdata=04%7C01%7CChristian.Koenig%40amd.com%7C65d21b6f02da409ac7b508d8f9997367%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637533784761980218%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=%2FeOQf12NBkC3YGZ7QW66%2FT%2FpyM3DjEb9IMbqUvISMfo%3Dreserved=0 where the bound status was introduced for all drm drivers including radeon and amdgpu. So this patch just reverts the logic to the original code but keeping the bound status. In my case, the binding code allocates the user pages memory and returns without bounding (at amdgpu_gtt_mgr_has_gart_addr). So, when the unbinding happens, the memory needs to be cleared to prevent the leak. Ah, now I understand what's happening here. Daniel your patch is not really correct. The problem is rather that we don't set the tt object to bound if it doesn't have a GTT address. Going to provide a patch for this. Did this patch ever land? I don't think so but I might send a v2 following Christian's comment if you guys agree. Somebody else already provided a patch which I reviewed, but I'm not sure if that landed either. Also, the patch here is for radeon but the pagefault issue reported by Felix is affected by the amdgpu one: radeon patch: drm/radeon/ttm: Fix memory leak userptr pages https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fproject%2Fdri-devel%2Fpatch%2F20210318083236.43578-1-daniel%40qtec.com%2Fdata=04%7C01%7CChristian.Koenig%40amd.com%7C65d21b6f02da409ac7b508d8f9997367%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637533784761980218%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=HSMK%2FqYz%2Bzz9qbKc%2FITUWluBDeaW9YrgyH8p0L640%2F0%3Dreserved=0 amdgpu patch: drm/amdgpu/ttm: Fix memory leak userptr pages https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fproject%2Fdri-devel%2Fpatch%2F20210317160840.36019-1-daniel%40qtec.com%2Fdata=04%7C01%7CChristian.Koenig%40amd.com%7C65d21b6f02da409ac7b508d8f9997367%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637533784761980218%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=UsUZ4YjCSjHmzlPB07oTaGrsntTrQSwlGk%2BxUjwDiag%3Dreserved=0 I assume both need to be fixed with the same approach. Yes correct. Let me double check where that fix went. Thanks, Christian. Daniel Alex Regards, Christian. [17359.536303] amdgpu: init_user_pages: Failed to get user pages: -16 [17359.543746] BUG: kernel NULL pointer dereference, address: [17359.551494] #PF: supervisor read access in kernel mode [17359.557375] #PF: error_code(0x) - not-present page [17359.563247] PGD 0 P4D 0 [17359.566514] Oops: [#1] SMP PTI [17359.570728] CPU: 8 PID: 5944 Comm: kfdtest Not tainted 5.11.0-kfd-fkuehlin #193 [17359.578760] Hardware name: ASUS All Series/X99-E WS/USB 3.1, BIOS 3201 06/17/2016 [17359.586971] RIP: 0010:amdgpu_ttm_backend_unbind+0x52/0x110 [amdgpu] [17359.594075] Code: 48 39 c6 74 1b 8b 53 0c 48 8d bd 80 a1 ff ff e8 24 62 00 00 85 c0 0f 85 ab 00 00 00 c6 43 54 00 5b 5d c3 48 8b 46 10 8b 4e 50 <48> 8b 30 48 85 f6 74 ba 8b 50 0c 48 8b bf 80 a1 ff ff 83 e1 01 45 [17359.614340] RSP: 0018:a4764971fc98 EFLAGS: 00010206 [17359.620315] RAX: RBX: 950e8d4edf00 RCX: [17359.628204] RDX: RSI: 950e8d4edf00 RDI: 950eadec5e80 [17359.636084] RBP: 950eadec5e80 R08: R09: [17359.643958] R10: 0246 R11: 0001 R12: 950c03377800 [17359.651833] R13: 950eadec5e80 R14: 950c03377858 R15: [17359.659701] FS: 7febb20cb740() GS:950ebfc0() knlGS: [17359.668528] CS: 0010 DS: ES: CR0: 80050033 [17359.675012] CR2: CR3: 0006d700e005 CR4: 001706e0 [17359.682883] Call Trace: [17359.686063] amdgpu_ttm_backend_destroy+0x12/0x70 [amdgpu] [17359.692349] ttm_bo_cleanup_memtype_use+0x37/0x60 [ttm] [17359.698307] ttm_bo_release+0x278/0x5e0 [ttm] [17359.703385] amdgpu_bo_unref+0x1a/0x30 [amdgpu] [17359.708701]
RE: [pull] amdgpu, radeon, ttm, sched drm-next-5.13
[AMD Public Use] Hi Felix and Christian, If the regression you are talking about is the NULL pointer problem when running KFD tests, it should fixed by below patch in this series. drm/amdgpu: fix NULL pointer dereference Regards, Guchun -Original Message- From: amd-gfx On Behalf Of Christian König Sent: Wednesday, April 7, 2021 2:57 PM To: Kuehling, Felix ; Deucher, Alexander ; amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; airl...@gmail.com; daniel.vet...@ffwll.ch Subject: Re: [pull] amdgpu, radeon, ttm, sched drm-next-5.13 Am 06.04.21 um 17:42 schrieb Felix Kuehling: > Am 2021-04-01 um 6:29 p.m. schrieb Alex Deucher: >> Hi Dave, Daniel, >> >> New stuff for 5.13. There are two small patches for ttm and >> scheduler that were dependencies for amdgpu changes. >> >> The following changes since commit 2cbcb78c9ee5520c8d836c7ff57d1b60ebe8e9b7: >> >>Merge tag 'amd-drm-next-5.13-2021-03-23' of >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit >> lab.freedesktop.org%2Fagd5f%2Flinuxdata=04%7C01%7Cguchun.chen%40 >> amd.com%7C51d1cbcf7ccc43854abb08d8f99250d8%7C3dd8961fe4884e608e11a82d >> 994e183d%7C0%7C0%7C637533754128113017%7CUnknown%7CTWFpbGZsb3d8eyJWIjo >> iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000 >> p;sdata=FcdoL9w5LhBZ849ctXPudr%2BBQnnm7Oiq3pz5X7LGGk4%3Dreserved >> =0 into drm-next (2021-03-26 15:53:21 +0100) >> >> are available in the Git repository at: >> >> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit >> lab.freedesktop.org%2Fagd5f%2Flinux.gitdata=04%7C01%7Cguchun.che >> n%40amd.com%7C51d1cbcf7ccc43854abb08d8f99250d8%7C3dd8961fe4884e608e11 >> a82d994e183d%7C0%7C0%7C637533754128113017%7CUnknown%7CTWFpbGZsb3d8eyJ >> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C100 >> 0sdata=N4JIk%2BEgzleaKYaxvdtT7TR1ZsS6FGsIGpDDUqiQiLw%3Drese >> rved=0 tags/amd-drm-next-5.13-2021-04-01 >> >> for you to fetch changes up to ef95d2a98d642a537190d73c45ae3c308afee890: >> >>drm/amdgpu/display: fix warning on 32 bit in dmub (2021-04-01 >> 17:32:32 -0400) >> >> >> amd-drm-next-5.13-2021-04-01: >> >> amdgpu: >> - Re-enable GPU reset on VanGogh >> - Enable DPM flags for SMART_SUSPEND and MAY_SKIP_RESUME >> - Disentangle HG from vga_switcheroo >> - S0ix fixes >> - W=1 fixes >> - Resource iterator fixes >> - DMCUB updates >> - UBSAN fixes >> - More PM API cleanup >> - Aldebaran updates >> - Modifier fixes >> - Enable VCN load balancing with asymmetric engines >> - Rework BO structs >> - Aldebaran reset support >> - Initial LTTPR display work >> - Display MALL fixes >> - Fall back to YCbCr420 when YCbCr444 fails >> - SR-IOV fixes >> - Misc cleanups and fixes >> >> radeon: >> - Typo fixes >> >> ttm: >> - Handle cached requests (required for Aldebaran) >> >> scheduler: >> - Fix runqueue selection when changing priorities (required to fix VCN >>load balancing) >> >> >> Alex Deucher (20): >>drm/amdgpu/display/dm: add missing parameter documentation >>drm/amdgpu: Add additional Sienna Cichlid PCI ID >>drm/amdgpu: add a dev_pm_ops prepare callback (v2) >>drm/amdgpu: enable DPM_FLAG_MAY_SKIP_RESUME and >> DPM_FLAG_SMART_SUSPEND flags (v2) >>drm/amdgpu: disentangle HG systems from vgaswitcheroo >>drm/amdgpu: rework S3/S4/S0ix state handling >>drm/amdgpu: don't evict vram on APUs for suspend to ram (v4) >>drm/amdgpu: clean up non-DC suspend/resume handling >>drm/amdgpu: move s0ix check into amdgpu_device_ip_suspend_phase2 (v3) >>drm/amdgpu: re-enable suspend phase 2 for S0ix >>drm/amdgpu/swsmu: skip gfx cgpg on s0ix suspend >>drm/amdgpu: update comments about s0ix suspend/resume >>drm/amdgpu: drop S0ix checks around CG/PG in suspend >>drm/amdgpu: skip kfd suspend/resume for S0ix >>drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x >>drm/amdgpu/display: fix memory leak for dimgrey cavefish >>drm/amdgpu/pm: mark pcie link/speed arrays as const >>drm/amdgpu/pm: bail on sysfs/debugfs queries during platform suspend >>drm/amdgpu/vangogh: don't check for dpm in is_dpm_running when in >> suspend >>drm/amdgpu/display: fix warning on 32 bit in dmub >> >> Alex Sierra (2): >>drm/amdgpu: replace per_device_list by array >>drm/amdgpu: ih reroute for newer asics than vega20 >> >> Alvin Lee (1): >>drm/amd/display: Change input parameter for set_drr >> >> Anson Jacob (2): >>drm/amd/display: Fix UBSAN: shift-out-of-bounds warning >>drm/amd/display: Removing unused code from dmub_cmd.h >> >> Anthony Koo (2): >>drm/amd/display: [FW Promotion] Release 0.0.57 >>drm/amd/display: [FW Promotion] Release 0.0.58 >> >> Aric Cyr (2): >>drm/amd/display: 3.2.128 >>
[PATCH] drm/amdgpu: add DMUB outbox event IRQ source define/complete/debug flag
[Why & How]
We use outbox interrupt that allows us to do the AUX via DMUB
Therefore, we need to add some irq source related definition
in the header files;
Signed-off-by: Jude Shih
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 963ecfd84347..480e07d83492 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -923,6 +923,7 @@ struct amdgpu_device {
struct amdgpu_irq_src pageflip_irq;
struct amdgpu_irq_src hpd_irq;
struct amdgpu_irq_src dmub_trace_irq;
+ struct amdgpu_irq_src dmub_outbox_irq;
/* rings */
u64 fence_context;
diff --git a/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
index e2bffcae273a..754170a86ea4 100644
--- a/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
+++ b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
@@ -1132,5 +1132,7 @@
#define DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 0x68
#define DCN_1_0__CTXID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 6
+#define DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT0x68 //
DMCUB_IHC_outbox1_ready_int IHC_DMCUB_outbox1_ready_int_ack
DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE24
Level/Pulse
+#define DCN_1_0__CTXID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT8
#endif // __IRQSRCS_DCN_1_0_H__
--
2.25.1
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RE: [PATCH] drm/amd/pm: add the callback to get vbios bootup values for vangogh
[AMD Public Use]
Reviewed-by: Evan Quan
> -Original Message-
> From: Du, Xiaojian
> Sent: Wednesday, April 7, 2021 4:26 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Quan, Evan
> ; Wang, Kevin(Yang) ; Du,
> Xiaojian
> Subject: [PATCH] drm/amd/pm: add the callback to get vbios bootup values
> for vangogh
>
> This patch is to add the callback to get vbios bootup values for
> vangogh, it will get the bootup values of gfxclk, mclk, socclk and so
> on.
>
> Signed-off-by: Xiaojian Du
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 1 +
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index 0d137af1a78a..6274cae4a065 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -561,6 +561,7 @@ int smu_v11_0_get_vbios_bootup_values(struct
> smu_context *smu)
> smu->smu_table.boot_values.firmware_caps = v_3_1-
> >firmware_capability;
> break;
> case 3:
> + case 4:
> default:
> v_3_3 = (struct atom_firmware_info_v3_3 *)header;
> smu->smu_table.boot_values.revision = v_3_3-
> >firmware_revision;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 5aea67637bd8..7bcd35840bf2 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -1894,6 +1894,7 @@ static const struct pptable_funcs
> vangogh_ppt_funcs = {
> .get_ppt_limit = vangogh_get_ppt_limit,
> .get_power_limit = vangogh_get_power_limit,
> .set_power_limit = vangogh_set_power_limit,
> + .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
> };
>
> void vangogh_set_ppt_funcs(struct smu_context *smu)
> --
> 2.25.1
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[PATCH] drm/amd/pm: add the callback to get vbios bootup values for vangogh
This patch is to add the callback to get vbios bootup values for
vangogh, it will get the bootup values of gfxclk, mclk, socclk and so
on.
Signed-off-by: Xiaojian Du
---
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 0d137af1a78a..6274cae4a065 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -561,6 +561,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context
*smu)
smu->smu_table.boot_values.firmware_caps =
v_3_1->firmware_capability;
break;
case 3:
+ case 4:
default:
v_3_3 = (struct atom_firmware_info_v3_3 *)header;
smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 5aea67637bd8..7bcd35840bf2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -1894,6 +1894,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
.get_ppt_limit = vangogh_get_ppt_limit,
.get_power_limit = vangogh_get_power_limit,
.set_power_limit = vangogh_set_power_limit,
+ .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
};
void vangogh_set_ppt_funcs(struct smu_context *smu)
--
2.25.1
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Re: [PATCH] drm/radeon/ttm: Fix memory leak userptr pages
On Tue, 6 Apr 2021 at 22:56, Alex Deucher wrote: > > On Mon, Mar 22, 2021 at 6:34 AM Christian König > wrote: > > > > Hi Daniel, > > > > Am 22.03.21 um 10:38 schrieb Daniel Gomez: > > > On Fri, 19 Mar 2021 at 21:29, Felix Kuehling > > > wrote: > > >> This caused a regression in kfdtest in a large-buffer stress test after > > >> memory allocation for user pages fails: > > > I'm sorry to hear that. BTW, I guess you meant amdgpu leak patch and > > > not this one. > > > Just some background for the mem leak patch if helps to understand this: > > > The leak was introduce here: > > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0b988ca1c7c4c73983b4ea96ef7c2af2263c87eb > > > where the bound status was introduced for all drm drivers including > > > radeon and amdgpu. So this patch just reverts the logic to the > > > original code but keeping the bound status. In my case, the binding > > > code allocates the user pages memory and returns without bounding (at > > > amdgpu_gtt_mgr_has_gart_addr). So, > > > when the unbinding happens, the memory needs to be cleared to prevent the > > > leak. > > > > Ah, now I understand what's happening here. Daniel your patch is not > > really correct. > > > > The problem is rather that we don't set the tt object to bound if it > > doesn't have a GTT address. > > > > Going to provide a patch for this. > > Did this patch ever land? I don't think so but I might send a v2 following Christian's comment if you guys agree. Also, the patch here is for radeon but the pagefault issue reported by Felix is affected by the amdgpu one: radeon patch: drm/radeon/ttm: Fix memory leak userptr pages https://patchwork.kernel.org/project/dri-devel/patch/20210318083236.43578-1-dan...@qtec.com/ amdgpu patch: drm/amdgpu/ttm: Fix memory leak userptr pages https://patchwork.kernel.org/project/dri-devel/patch/20210317160840.36019-1-dan...@qtec.com/ I assume both need to be fixed with the same approach. Daniel > > Alex > > > > > Regards, > > Christian. > > > > > > > >> [17359.536303] amdgpu: init_user_pages: Failed to get user pages: -16 > > >> [17359.543746] BUG: kernel NULL pointer dereference, address: > > >> > > >> [17359.551494] #PF: supervisor read access in kernel mode > > >> [17359.557375] #PF: error_code(0x) - not-present page > > >> [17359.563247] PGD 0 P4D 0 > > >> [17359.566514] Oops: [#1] SMP PTI > > >> [17359.570728] CPU: 8 PID: 5944 Comm: kfdtest Not tainted > > >> 5.11.0-kfd-fkuehlin #193 > > >> [17359.578760] Hardware name: ASUS All Series/X99-E WS/USB 3.1, BIOS > > >> 3201 06/17/2016 > > >> [17359.586971] RIP: 0010:amdgpu_ttm_backend_unbind+0x52/0x110 [amdgpu] > > >> [17359.594075] Code: 48 39 c6 74 1b 8b 53 0c 48 8d bd 80 a1 ff ff e8 24 > > >> 62 00 00 85 c0 0f 85 ab 00 00 00 c6 43 54 00 5b 5d c3 48 8b 46 10 8b 4e > > >> 50 <48> 8b 30 48 85 f6 74 ba 8b 50 0c 48 8b bf 80 a1 ff ff 83 e1 01 45 > > >> [17359.614340] RSP: 0018:a4764971fc98 EFLAGS: 00010206 > > >> [17359.620315] RAX: RBX: 950e8d4edf00 RCX: > > >> > > >> [17359.628204] RDX: RSI: 950e8d4edf00 RDI: > > >> 950eadec5e80 > > >> [17359.636084] RBP: 950eadec5e80 R08: R09: > > >> > > >> [17359.643958] R10: 0246 R11: 0001 R12: > > >> 950c03377800 > > >> [17359.651833] R13: 950eadec5e80 R14: 950c03377858 R15: > > >> > > >> [17359.659701] FS: 7febb20cb740() GS:950ebfc0() > > >> knlGS: > > >> [17359.668528] CS: 0010 DS: ES: CR0: 80050033 > > >> [17359.675012] CR2: CR3: 0006d700e005 CR4: > > >> 001706e0 > > >> [17359.682883] Call Trace: > > >> [17359.686063] amdgpu_ttm_backend_destroy+0x12/0x70 [amdgpu] > > >> [17359.692349] ttm_bo_cleanup_memtype_use+0x37/0x60 [ttm] > > >> [17359.698307] ttm_bo_release+0x278/0x5e0 [ttm] > > >> [17359.703385] amdgpu_bo_unref+0x1a/0x30 [amdgpu] > > >> [17359.708701] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x7e5/0x910 > > >> [amdgpu] > > >> [17359.716307] kfd_ioctl_alloc_memory_of_gpu+0x11a/0x220 [amdgpu] > > >> [17359.723036] kfd_ioctl+0x223/0x400 [amdgpu] > > >> [17359.728017] ? kfd_dev_is_large_bar+0x90/0x90 [amdgpu] > > >> [17359.734152] __x64_sys_ioctl+0x8b/0xd0 > > >> [17359.738796] do_syscall_64+0x2d/0x40 > > >> [17359.743259] entry_SYSCALL_64_after_hwframe+0x44/0xa9 > > >> [17359.749205] RIP: 0033:0x7febb083b6d7 > > >> [17359.753681] Code: b3 66 90 48 8b 05 b1 47 2d 00 64 c7 00 26 00 00 00 > > >> 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f > > >> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 81 47 2d 00 f7 d8 64 89 01 48 > > >> [17359.774340] RSP: 002b:7ffdb5522cd8 EFLAGS: 0202 ORIG_RAX: > > >> 0010 > > >> [17359.782668] RAX: ffda RBX: 0001 RCX: > > >> 7febb083b6d7 > > >> [17359.790566] RDX:
Re: [pull] amdgpu, radeon, ttm, sched drm-next-5.13
On Wed, 7 Apr 2021 at 06:54, Alex Deucher wrote: > > On Fri, Apr 2, 2021 at 12:22 PM Christian König > wrote: > > > > Hey Alex, > > > > the TTM and scheduler changes should already be in the drm-misc-next > > branch (not 100% sure about the TTM patch, need to double check next week). > > > > The TTM change is not in drm-misc yet. > > > Could that cause problems when both are merged into drm-next? > > Dave, Daniel, how do you want to handle this? The duplicated patch is this > one: > https://cgit.freedesktop.org/drm/drm-misc/commit/?id=ac4eb83ab255de9c31184df51fd1534ba36fd212 > amdgpu has changes which depend on it. The same patch is included in this PR. Ouch not sure how best to sync up here, maybe get misc-next into my tree then rebase your tree on top of it? Dave. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v1] drm/radeon: Fix a missing check bug in radeon_dp_mst_detect()
From: Yingjie Wang
In radeon_dp_mst_detect(), We should check whether or not @connector
has been unregistered from userspace. If the connector is unregistered,
we should return disconnected status.
Fixes: 9843ead08f18 ("drm/radeon: add DisplayPort MST support (v2)")
Signed-off-by: Yingjie Wang
---
drivers/gpu/drm/radeon/radeon_dp_mst.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c
b/drivers/gpu/drm/radeon/radeon_dp_mst.c
index 2c32186c4acd..4e4c937c36c6 100644
--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
+++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
@@ -242,6 +242,9 @@ radeon_dp_mst_detect(struct drm_connector *connector,
to_radeon_connector(connector);
struct radeon_connector *master = radeon_connector->mst_port;
+ if (drm_connector_is_unregistered(connector))
+ return connector_status_disconnected;
+
return drm_dp_mst_detect_port(connector, ctx, >mst_mgr,
radeon_connector->port);
}
--
2.7.4
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Re: [pull] amdgpu, radeon, ttm, sched drm-next-5.13
Am 06.04.21 um 17:42 schrieb Felix Kuehling: Am 2021-04-01 um 6:29 p.m. schrieb Alex Deucher: Hi Dave, Daniel, New stuff for 5.13. There are two small patches for ttm and scheduler that were dependencies for amdgpu changes. The following changes since commit 2cbcb78c9ee5520c8d836c7ff57d1b60ebe8e9b7: Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next (2021-03-26 15:53:21 +0100) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-5.13-2021-04-01 for you to fetch changes up to ef95d2a98d642a537190d73c45ae3c308afee890: drm/amdgpu/display: fix warning on 32 bit in dmub (2021-04-01 17:32:32 -0400) amd-drm-next-5.13-2021-04-01: amdgpu: - Re-enable GPU reset on VanGogh - Enable DPM flags for SMART_SUSPEND and MAY_SKIP_RESUME - Disentangle HG from vga_switcheroo - S0ix fixes - W=1 fixes - Resource iterator fixes - DMCUB updates - UBSAN fixes - More PM API cleanup - Aldebaran updates - Modifier fixes - Enable VCN load balancing with asymmetric engines - Rework BO structs - Aldebaran reset support - Initial LTTPR display work - Display MALL fixes - Fall back to YCbCr420 when YCbCr444 fails - SR-IOV fixes - Misc cleanups and fixes radeon: - Typo fixes ttm: - Handle cached requests (required for Aldebaran) scheduler: - Fix runqueue selection when changing priorities (required to fix VCN load balancing) Alex Deucher (20): drm/amdgpu/display/dm: add missing parameter documentation drm/amdgpu: Add additional Sienna Cichlid PCI ID drm/amdgpu: add a dev_pm_ops prepare callback (v2) drm/amdgpu: enable DPM_FLAG_MAY_SKIP_RESUME and DPM_FLAG_SMART_SUSPEND flags (v2) drm/amdgpu: disentangle HG systems from vgaswitcheroo drm/amdgpu: rework S3/S4/S0ix state handling drm/amdgpu: don't evict vram on APUs for suspend to ram (v4) drm/amdgpu: clean up non-DC suspend/resume handling drm/amdgpu: move s0ix check into amdgpu_device_ip_suspend_phase2 (v3) drm/amdgpu: re-enable suspend phase 2 for S0ix drm/amdgpu/swsmu: skip gfx cgpg on s0ix suspend drm/amdgpu: update comments about s0ix suspend/resume drm/amdgpu: drop S0ix checks around CG/PG in suspend drm/amdgpu: skip kfd suspend/resume for S0ix drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x drm/amdgpu/display: fix memory leak for dimgrey cavefish drm/amdgpu/pm: mark pcie link/speed arrays as const drm/amdgpu/pm: bail on sysfs/debugfs queries during platform suspend drm/amdgpu/vangogh: don't check for dpm in is_dpm_running when in suspend drm/amdgpu/display: fix warning on 32 bit in dmub Alex Sierra (2): drm/amdgpu: replace per_device_list by array drm/amdgpu: ih reroute for newer asics than vega20 Alvin Lee (1): drm/amd/display: Change input parameter for set_drr Anson Jacob (2): drm/amd/display: Fix UBSAN: shift-out-of-bounds warning drm/amd/display: Removing unused code from dmub_cmd.h Anthony Koo (2): drm/amd/display: [FW Promotion] Release 0.0.57 drm/amd/display: [FW Promotion] Release 0.0.58 Aric Cyr (2): drm/amd/display: 3.2.128 drm/amd/display: 3.2.129 Arnd Bergmann (3): amdgpu: avoid incorrect %hu format string amdgpu: fix gcc -Wrestrict warning amdgpu: securedisplay: simplify i2c hexdump output Bhaskar Chowdhury (6): drm/amdgpu: Fix a typo drm/amdgpu: Fix a typo drm/atomic: Couple of typo fixes drm/radeon/r600_cs: Few typo fixes drm/amd/amdgpu/gfx_v7_0: Trivial typo fixes drm/amd: Fix a typo in two different sentences Bindu Ramamurthy (1): drm/amd/display: Allow idle optimization based on vblank. Chengming Gui (1): drm/amd/amdgpu: set MP1 state to UNLOAD before reload its FW for vega20/ALDEBARAN Chris Park (1): drm/amd/display: Disable MALL when SMU not present Christian König (5): drm/amdgpu: remove irq_src->data handling drm/amdgpu: add the sched_score to amdgpu_ring_init drm/amdgpu: share scheduler score on VCN3 instances drm/sched: select new rq even if there is only one v3 drm/amdgpu: load balance VCN3 decode as well v8 Daniel Gomez (2): drm/amdgpu/ttm: Fix memory leak userptr pages This introduced a regression for KFD, which I pointed out at the time. Was there ever a fix for that. This was fixed recently by somebody else. I've reviewed the patch, but I'm not sure if it landed inside the branch. Regards, Christian. Regards, Felix drm/radeon/ttm: Fix memory leak userptr pages David Galiffi (1): drm/amd/display: Fixed Clock Recovery Sequence Dennis Li (1): drm/amdgpu: add codes to capture invalid hardware access when recovery
