[PATCH 4/4] drm/amdkfd: Make TLB flush conditional on mapping
It is to optimize memory mapping latency, and to aviod
a page fault in a corner case of changing valid PDE into
PTE.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 2 +-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 19 --
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 25 +++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 3 ++-
4 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 2560977760b3..8f2d6711e12f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -280,7 +280,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
uint64_t *size);
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
- struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
+ struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool
*flush_tlb);
int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
int amdgpu_amdkfd_gpuvm_sync_memory(
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 1fcfa172911a..585b50b6009f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1117,7 +1117,8 @@ static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
static int update_gpuvm_pte(struct kgd_mem *mem,
struct kfd_mem_attachment *entry,
- struct amdgpu_sync *sync)
+ struct amdgpu_sync *sync,
+ bool *flush_tlb)
{
struct amdgpu_bo_va *bo_va = entry->bo_va;
struct amdgpu_device *adev = entry->adev;
@@ -1128,7 +1129,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
return ret;
/* Update the page tables */
- ret = amdgpu_vm_bo_update(adev, bo_va, false);
+ ret = amdgpu_vm_bo_update(adev, bo_va, false, flush_tlb);
if (ret) {
pr_err("amdgpu_vm_bo_update failed\n");
return ret;
@@ -1140,7 +1141,8 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
static int map_bo_to_gpuvm(struct kgd_mem *mem,
struct kfd_mem_attachment *entry,
struct amdgpu_sync *sync,
- bool no_update_pte)
+ bool no_update_pte,
+ bool *flush_tlb)
{
int ret;
@@ -1157,7 +1159,7 @@ static int map_bo_to_gpuvm(struct kgd_mem *mem,
if (no_update_pte)
return 0;
- ret = update_gpuvm_pte(mem, entry, sync);
+ ret = update_gpuvm_pte(mem, entry, sync, flush_tlb);
if (ret) {
pr_err("update_gpuvm_pte() failed\n");
goto update_gpuvm_pte_failed;
@@ -1687,7 +1689,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
}
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
- struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
+ struct kgd_dev *kgd, struct kgd_mem *mem,
+ void *drm_priv, bool *flush_tlb)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
@@ -1775,7 +1778,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
entry->va, entry->va + bo_size, entry);
ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
- is_invalid_userptr);
+ is_invalid_userptr, flush_tlb);
if (ret) {
pr_err("Failed to map bo to gpuvm\n");
goto out_unreserve;
@@ -2469,7 +2472,7 @@ static int validate_invalid_user_pages(struct
amdkfd_process_info *process_info)
continue;
kfd_mem_dmaunmap_attachment(mem, attachment);
- ret = update_gpuvm_pte(mem, attachment, );
+ ret = update_gpuvm_pte(mem, attachment, , NULL);
if (ret) {
pr_err("%s: update PTE failed\n", __func__);
/* make sure this gets validated again */
@@ -2675,7 +2678,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info,
struct dma_fence **ef)
continue;
kfd_mem_dmaunmap_attachment(mem, attachment);
- ret = update_gpuvm_pte(mem, attachment, _obj);
+ ret = update_gpuvm_pte(mem, attachment, _obj,
NULL);
if (ret) {
pr_debug("Memory eviction: update PTE failed.
Try again\n");
[PATCH 2/4] drm/amdkfd: Add heavy-weight TLB flush after unmapping
It is a part of memory mapping optimization. Signed-off-by: Eric Huang --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 4da8aff3df27..98f1d2b586c5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1766,6 +1766,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, amdgpu_read_unlock(peer->ddev); goto unmap_memory_from_gpu_failed; } + kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); amdgpu_read_unlock(peer->ddev); args->n_success = i+1; } -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/4] drm/amdkfd: Add flush-type parameter to kfd_flush_tlb
It is to provide more tlb flush types opotion for different
case scenario.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 6 +++---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 960913a35ee4..4da8aff3df27 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1666,7 +1666,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
if (WARN_ON_ONCE(!peer_pdd))
continue;
if (!amdgpu_read_lock(peer->ddev, true)) {
- kfd_flush_tlb(peer_pdd);
+ kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
amdgpu_read_unlock(peer->ddev);
}
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 2bd621eee4e0..904b8178c1d7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -278,7 +278,7 @@ static int allocate_vmid(struct device_queue_manager *dqm,
qpd->vmid,
qpd->page_table_base);
/* invalidate the VM context after pasid and vmid mapping is set up */
- kfd_flush_tlb(qpd_to_pdd(qpd));
+ kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
if (dqm->dev->kfd2kgd->set_scratch_backing_va)
dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd,
@@ -314,7 +314,7 @@ static void deallocate_vmid(struct device_queue_manager
*dqm,
if (flush_texture_cache_nocpsch(q->device, qpd))
pr_err("Failed to flush TC\n");
- kfd_flush_tlb(qpd_to_pdd(qpd));
+ kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
/* Release the vmid mapping */
set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
@@ -885,7 +885,7 @@ static int restore_process_queues_nocpsch(struct
device_queue_manager *dqm,
dqm->dev->kgd,
qpd->vmid,
qpd->page_table_base);
- kfd_flush_tlb(pdd);
+ kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
}
/* Take a safe reference to the mm_struct, which may otherwise
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index ecdd5e782b81..edce3ecf207d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -1338,7 +1338,7 @@ void kfd_signal_reset_event(struct kfd_dev *dev);
void kfd_signal_poison_consumed_event(struct kfd_dev *dev, u32 pasid);
-void kfd_flush_tlb(struct kfd_process_device *pdd);
+void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type);
int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 3995002c582b..72741f6579d3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -2159,7 +2159,7 @@ int kfd_reserved_mem_mmap(struct kfd_dev *dev, struct
kfd_process *process,
KFD_CWSR_TBA_TMA_SIZE, vma->vm_page_prot);
}
-void kfd_flush_tlb(struct kfd_process_device *pdd)
+void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type)
{
struct kfd_dev *dev = pdd->dev;
@@ -2172,7 +2172,7 @@ void kfd_flush_tlb(struct kfd_process_device *pdd)
pdd->qpd.vmid);
} else {
amdgpu_amdkfd_flush_gpu_tlb_pasid(dev->kgd,
- pdd->process->pasid, TLB_FLUSH_LEGACY);
+ pdd->process->pasid, type);
}
}
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/4] drm/amdgpu: Add flush_tlb parameter to amdgpu_vm_bo_update
It is to pass the flag to KFD, and optimize table_freed in
amdgpu_vm_bo_update_mapping.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index e9f9f462a652..e3df132e53a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -916,7 +916,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
if (r)
return r;
- r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
+ r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false, NULL);
if (r)
return r;
@@ -927,7 +927,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
bo_va = fpriv->csa_va;
BUG_ON(!bo_va);
- r = amdgpu_vm_bo_update(adev, bo_va, false);
+ r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
if (r)
return r;
@@ -946,7 +946,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
if (bo_va == NULL)
continue;
- r = amdgpu_vm_bo_update(adev, bo_va, false);
+ r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 2120a87a949f..eac2fd0048cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -696,7 +696,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device
*adev,
if (operation == AMDGPU_VA_OP_MAP ||
operation == AMDGPU_VA_OP_REPLACE) {
- r = amdgpu_vm_bo_update(adev, bo_va, false);
+ r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
if (r)
goto error;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 2c20bba7dc1a..fed3d44b5ded 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1729,7 +1729,7 @@ int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev,
r = vm->update_funcs->commit(, fence);
if (table_freed)
- *table_freed = params.table_freed;
+ *table_freed = *table_freed || params.table_freed;
error_unlock:
amdgpu_vm_eviction_unlock(vm);
@@ -1793,7 +1793,7 @@ void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t
*vram_mem,
* 0 for success, -EINVAL for failure.
*/
int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
- bool clear)
+ bool clear, bool *flush_tlb)
{
struct amdgpu_bo *bo = bo_va->base.bo;
struct amdgpu_vm *vm = bo_va->base.vm;
@@ -1887,7 +1887,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va,
resv, mapping->start,
mapping->last, update_flags,
mapping->offset, mem,
- pages_addr, last_update, NULL,
+ pages_addr, last_update,
flush_tlb,
vram_base_offset);
if (r)
return r;
@@ -2141,7 +2141,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
list_for_each_entry_safe(bo_va, tmp, >moved, base.vm_status) {
/* Per VM BOs never need to bo cleared in the page tables */
- r = amdgpu_vm_bo_update(adev, bo_va, false);
+ r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
if (r)
return r;
}
@@ -2160,7 +2160,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
else
clear = true;
- r = amdgpu_vm_bo_update(adev, bo_va, clear);
+ r = amdgpu_vm_bo_update(adev, bo_va, clear, NULL);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 67bba8462e7d..24a63e284a69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -419,7 +419,7 @@ int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va,
- bool clear);
+
Re: [PATCH -next] drm/amdgpu: Remove unneeded semicolon
Applied. Thanks! On Tue, Jun 1, 2021 at 10:07 AM Zheng Yongjun wrote: > > Remove unneeded semicolon. > > Signed-off-by: Zheng Yongjun > --- > drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c > b/drivers/gpu/drm/amd/amdgpu/aldebaran.c > index 65b1dca4b02e..148f6c3343ab 100644 > --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c > +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c > @@ -227,7 +227,7 @@ static int aldebaran_mode2_restore_ip(struct > amdgpu_device *adev) > break; > default: > break; > - }; > + } > } > > /* Reinit NBIF block */ > -- > 2.25.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime
On Tue, Jun 1, 2021 at 12:28 PM shaoyunl wrote: > > On SRIOV, driver should only access register through RLC in runtime > > Signed-off-by: shaoyunl Acked-by: Alex Deucher > Change-Id: Iecaa52436a2985a18ede9c86cb00cc197a717bd6 > --- > drivers/gpu/drm/amd/amdgpu/soc15_common.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h > b/drivers/gpu/drm/amd/amdgpu/soc15_common.h > index c781808e4dc3..f6cf70e69cce 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h > +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h > @@ -28,12 +28,12 @@ > #define SOC15_REG_OFFSET(ip, inst, reg) > (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) > > #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \ > - ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \ > + ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \ > adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \ > WREG32(reg, value)) > > #define __RREG32_SOC15_RLC__(reg, flag, hwip) \ > - ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \ > + ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \ > adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \ > RREG32(reg)) > > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH -next] drm/amd/display: fix warning: ‘update_dsc_caps’ and ‘apply_dsc_policy_for_stream’ defined but not used
Applied. Thanks!
On Tue, Jun 1, 2021 at 4:04 AM Baokun Li wrote:
>
> Fixes gcc '-Wunused-function' warning:
>
> ‘update_dsc_caps’ and ‘apply_dsc_policy_for_stream’ are only used
> if 'CONFIG_DRM_AMD_DC_DCN' is defined,
>
> however, it's defined even if 'CONFIG_DRM_AMD_DC_DCN' is not defined.
> Thus gcc will report following warning
> if 'CONFIG_DRM_AMD_DC_DCN' is not defined:
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5572:13: warning:
> ‘apply_dsc_policy_for_stream’ defined but not used [-Wunused-function]
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5556:13: warning:
> ‘update_dsc_caps’ defined but not used [-Wunused-function]
>
> Thus move the definition of ‘update_dsc_caps’ and
> ‘apply_dsc_policy_for_stream’ inside define macro to fix it.
>
> Signed-off-by: Baokun Li
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index f0adfda32213..e0af394103aa 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -5553,6 +5553,7 @@ static void dm_enable_per_frame_crtc_master_sync(struct
> dc_state *context)
> }
> }
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
> struct dc_sink *sink,
> struct dc_stream_state *stream,
> struct
> dsc_dec_dpcd_caps *dsc_caps)
> @@ -5560,12 +5561,10 @@ static void update_dsc_caps(struct
> amdgpu_dm_connector *aconnector,
> stream->timing.flags.DSC = 0;
>
> if (aconnector->dc_link && sink->sink_signal ==
> SIGNAL_TYPE_DISPLAY_PORT) {
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
>
> aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
>
> aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
> dsc_caps);
> -#endif
> }
> }
>
> @@ -5578,7 +5577,6 @@ static void apply_dsc_policy_for_stream(struct
> amdgpu_dm_connector *aconnector,
>
> link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
>
> dc_link_get_link_cap(aconnector->dc_link));
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> /* Set DSC policy according to dsc_clock_en */
> dc_dsc_policy_set_enable_dsc_when_not_needed(
> aconnector->dsc_settings.dsc_force_enable ==
> DSC_CLK_FORCE_ENABLE);
> @@ -5609,8 +5607,8 @@ static void apply_dsc_policy_for_stream(struct
> amdgpu_dm_connector *aconnector,
>
> if (stream->timing.flags.DSC &&
> aconnector->dsc_settings.dsc_bits_per_pixel)
> stream->timing.dsc_cfg.bits_per_pixel =
> aconnector->dsc_settings.dsc_bits_per_pixel;
> -#endif
> }
> +#endif
>
> static struct drm_display_mode *
> get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
> --
> 2.31.1
>
___
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Re: [PATCH] drm/amd/display: Remove the redundant initialization of local variable
Applied. Thanks!
Alex
On Mon, May 31, 2021 at 5:30 AM Shaokun Zhang
wrote:
>
> Local variable 'i' and 'j' will be initialized in the for loop, so
> remove the redundant initialization.
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Signed-off-by: Shaokun Zhang
> ---
> drivers/gpu/drm/amd/display/dc/core/dc.c | 17 -
> 1 file changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 4713f09bcbf1..e4f2a2d3a819 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -304,7 +304,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
> struct dc_stream_state *stream,
> struct dc_crtc_timing_adjust *adjust)
> {
> - int i = 0;
> + int i;
> bool ret = false;
>
> stream->adjust.v_total_max = adjust->v_total_max;
> @@ -332,7 +332,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
> {
> /* TODO: Support multiple streams */
> const struct dc_stream_state *stream = streams[0];
> - int i = 0;
> + int i;
> bool ret = false;
> struct crtc_position position;
>
> @@ -539,7 +539,7 @@ void dc_stream_set_dyn_expansion(struct dc *dc, struct
> dc_stream_state *stream,
> enum dc_dynamic_expansion option)
> {
> /* OPP FMT dyn expansion updates*/
> - int i = 0;
> + int i;
> struct pipe_ctx *pipe_ctx;
>
> for (i = 0; i < MAX_PIPES; i++) {
> @@ -597,7 +597,7 @@ void dc_stream_set_dither_option(struct dc_stream_state
> *stream,
>
> bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state
> *stream)
> {
> - int i = 0;
> + int i;
> bool ret = false;
> struct pipe_ctx *pipes;
>
> @@ -614,7 +614,7 @@ bool dc_stream_set_gamut_remap(struct dc *dc, const
> struct dc_stream_state *stre
>
> bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state
> *stream)
> {
> - int i = 0;
> + int i;
> bool ret = false;
> struct pipe_ctx *pipes;
>
> @@ -640,8 +640,7 @@ void dc_stream_set_static_screen_params(struct dc *dc,
> int num_streams,
> const struct dc_static_screen_params *params)
> {
> - int i = 0;
> - int j = 0;
> + int i, j;
> struct pipe_ctx *pipes_affected[MAX_PIPES];
> int num_pipes_affected = 0;
>
> @@ -896,7 +895,7 @@ static void disable_all_writeback_pipes_for_stream(
> static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state
> *context,
> struct dc_stream_state *stream,
> bool lock)
> {
> - int i = 0;
> + int i;
>
> /* Checks if interdependent update function pointer is NULL or not,
> takes care of DCE110 case */
> if (dc->hwss.interdependent_update_lock)
> @@ -1156,7 +1155,7 @@ static void enable_timing_multisync(
> struct dc *dc,
> struct dc_state *ctx)
> {
> - int i = 0, multisync_count = 0;
> + int i, multisync_count = 0;
> int pipe_count = dc->res_pool->pipe_count;
> struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
>
> --
> 2.7.4
>
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Re: [PATCH] drm/amd/display: fix gcc set but not used warning of variable 'old_plane_state'
Applied. Thanks!
Alex
On Sat, May 29, 2021 at 5:19 AM Yu Kuai wrote:
>
> define a new macro for_each_new_plane_in_state_reverse to replace
> for_each_oldnew_plane_in_state_reverse, so that the unused variable
> 'old_plane_state' can be removed.
>
> Fix gcc warning:
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:10066:26: warning:
> variable ‘old_plane_state’ set but not used [-Wunused-but-set-variable]
>
> Signed-off-by: Yu Kuai
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
> include/drm/drm_atomic.h | 12
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index f7a5e5b48ea6..9f4b334bc071 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -10063,11 +10063,11 @@ static int validate_overlay(struct drm_atomic_state
> *state)
> {
> int i;
> struct drm_plane *plane;
> - struct drm_plane_state *old_plane_state, *new_plane_state;
> + struct drm_plane_state *new_plane_state;
> struct drm_plane_state *primary_state, *cursor_state, *overlay_state
> = NULL;
>
> /* Check if primary plane is contained inside overlay */
> - for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state,
> new_plane_state, i) {
> + for_each_new_plane_in_state_reverse(state, plane, new_plane_state, i)
> {
> if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
> if (drm_atomic_plane_disabling(plane->state,
> new_plane_state))
> return 0;
> diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
> index ac5a28eff2c8..8f1350e599eb 100644
> --- a/include/drm/drm_atomic.h
> +++ b/include/drm/drm_atomic.h
> @@ -895,6 +895,18 @@ void drm_state_dump(struct drm_device *dev, struct
> drm_printer *p);
> (old_plane_state) =
> (__state)->planes[__i].old_state,\
> (new_plane_state) =
> (__state)->planes[__i].new_state, 1))
>
> +/**
> + * for_each_new_plane_in_state_reverse - other than only tracking new state,
> + * it's the same as for_each_oldnew_plane_in_state_reverse
> + */
> +#define for_each_new_plane_in_state_reverse(__state, plane, new_plane_state,
> __i) \
> + for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1); \
> +(__i) >= 0;\
> +(__i)--) \
> + for_each_if ((__state)->planes[__i].ptr && \
> +((plane) = (__state)->planes[__i].ptr, \
> + (new_plane_state) =
> (__state)->planes[__i].new_state, 1))
> +
> /**
> * for_each_old_plane_in_state - iterate over all planes in an atomic update
> * @__state: drm_atomic_state pointer
> --
> 2.25.4
>
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Re: [PATCH] drm/amd/display: Avoid HDCP over-read and corruption
On Fri, May 28, 2021 at 1:54 PM Kees Cook wrote:
>
> Instead of reading the desired 5 bytes of the actual target field,
> the code was reading 8. This could result in a corrupted value if the
> trailing 3 bytes were non-zero, so instead use an appropriately sized
> and zero-initialized bounce buffer, and read only 5 bytes before casting
> to u64.
>
> Signed-off-by: Kees Cook
Applied. Thanks!
> ---
> drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
> b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
> index 2cbd931363bd..6d26d9c63ab2 100644
> --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
> +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
> @@ -29,8 +29,10 @@ static inline enum mod_hdcp_status validate_bksv(struct
> mod_hdcp *hdcp)
> {
> uint64_t n = 0;
> uint8_t count = 0;
> + u8 bksv[sizeof(n)] = { };
>
> - memcpy(, hdcp->auth.msg.hdcp1.bksv, sizeof(uint64_t));
> + memcpy(bksv, hdcp->auth.msg.hdcp1.bksv,
> sizeof(hdcp->auth.msg.hdcp1.bksv));
> + n = *(uint64_t *)bksv;
>
> while (n) {
> count++;
> --
> 2.25.1
>
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Re: [PATCH v3] amdgpu: remove unreachable code
Applied. Thanks!
On Fri, May 28, 2021 at 8:18 AM Christian König
wrote:
>
> Am 28.05.21 um 11:29 schrieb Jiapeng Chong:
> > In the function amdgpu_uvd_cs_msg(), every branch in the switch
> > statement will have a return, so the code below the switch statement
> > will not be executed.
> >
> > Eliminate the follow smatch warning:
> >
> > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c:845 amdgpu_uvd_cs_msg() warn:
> > ignoring unreachable code.
> >
> > Reported-by: Abaci Robot
> > Signed-off-by: Jiapeng Chong
>
> Reviewed-by: Christian König
>
> > ---
> > Changes in v2:
> >-For the follow advice: https://lore.kernel.org/patchwork/patch/1435968/
> >
> > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> > index c6dbc08..35f6874 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> > @@ -829,9 +829,8 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx
> > *ctx,
> >
> > default:
> > DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
> > - return -EINVAL;
> > }
> > - BUG();
> > +
> > return -EINVAL;
> > }
> >
>
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Re: [PATCH v3] drm/amdkfd: optimize memory mapping latency
Am 2021-06-01 um 5:30 p.m. schrieb Eric Huang:
> 1. conditionally flush TLBs after map.
> 2. add heavy weight TLBs flush after unmap.
>
> Signed-off-by: Eric Huang
The code looks good to me. But it's mixing a bit too much in a single
commit, which makes it hard to see what's really changing. We should
break this into a few commits to separate refactoring from actual
functional changes:
1. Add flush-type parameter to kfd_flush_tlb
2. Add heavy-weight TLB flush after unmapping
3. Add table_freed parameter to amdgpu_vm_bo_update mapping
4. Make TLB-flush after mapping conditional on table_freed parameter
1 and 3 are just refactoring. 2 and 4 change functionality. When
reviewing those four commits, it should be easy to see that 1 and 3
don't change any functionality. And the functional changes in 2 and 4
should be really clear and obvious.
Regards,
Felix
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 2 +-
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 19 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 6 ++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 10 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 27 +++
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++---
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 7 ++---
> 10 files changed, 46 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 2560977760b3..8f2d6711e12f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -280,7 +280,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
> struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
> uint64_t *size);
> int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
> - struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
> + struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool
> *flush_tlb);
> int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
> struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
> int amdgpu_amdkfd_gpuvm_sync_memory(
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 1fcfa172911a..585b50b6009f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1117,7 +1117,8 @@ static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
>
> static int update_gpuvm_pte(struct kgd_mem *mem,
> struct kfd_mem_attachment *entry,
> - struct amdgpu_sync *sync)
> + struct amdgpu_sync *sync,
> + bool *flush_tlb)
> {
> struct amdgpu_bo_va *bo_va = entry->bo_va;
> struct amdgpu_device *adev = entry->adev;
> @@ -1128,7 +1129,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
> return ret;
>
> /* Update the page tables */
> - ret = amdgpu_vm_bo_update(adev, bo_va, false);
> + ret = amdgpu_vm_bo_update(adev, bo_va, false, flush_tlb);
> if (ret) {
> pr_err("amdgpu_vm_bo_update failed\n");
> return ret;
> @@ -1140,7 +1141,8 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
> static int map_bo_to_gpuvm(struct kgd_mem *mem,
> struct kfd_mem_attachment *entry,
> struct amdgpu_sync *sync,
> -bool no_update_pte)
> +bool no_update_pte,
> +bool *flush_tlb)
> {
> int ret;
>
> @@ -1157,7 +1159,7 @@ static int map_bo_to_gpuvm(struct kgd_mem *mem,
> if (no_update_pte)
> return 0;
>
> - ret = update_gpuvm_pte(mem, entry, sync);
> + ret = update_gpuvm_pte(mem, entry, sync, flush_tlb);
> if (ret) {
> pr_err("update_gpuvm_pte() failed\n");
> goto update_gpuvm_pte_failed;
> @@ -1687,7 +1689,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
> }
>
> int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
> - struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
> + struct kgd_dev *kgd, struct kgd_mem *mem,
> + void *drm_priv, bool *flush_tlb)
> {
> struct amdgpu_device *adev = get_amdgpu_device(kgd);
> struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
> @@ -1775,7 +1778,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
>entry->va, entry->va + bo_size, entry);
>
> ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
> - is_invalid_userptr);
> + is_invalid_userptr, flush_tlb);
> if (ret) {
>
Re: [PATCH -next] drm/radeon/radeon_pm: use DEVICE_ATTR_RW macro
On Fri, May 28, 2021 at 3:18 AM YueHaibing wrote:
>
> Use DEVICE_ATTR_RW() helper instead of plain DEVICE_ATTR(),
> which makes the code a bit shorter and easier to read.
>
> Signed-off-by: YueHaibing
I'm not convinced this really buys us anything other than code churn,
but I don't have a particularly strong opinion of others feel
differently.
Alex
> ---
> drivers/gpu/drm/radeon/radeon_pm.c | 56 --
> 1 file changed, 23 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
> b/drivers/gpu/drm/radeon/radeon_pm.c
> index 3861c0b98fcf..edf10cc3947e 100644
> --- a/drivers/gpu/drm/radeon/radeon_pm.c
> +++ b/drivers/gpu/drm/radeon/radeon_pm.c
> @@ -352,9 +352,8 @@ static void radeon_pm_print_states(struct radeon_device
> *rdev)
> }
> }
>
> -static ssize_t radeon_get_pm_profile(struct device *dev,
> -struct device_attribute *attr,
> -char *buf)
> +static ssize_t power_profile_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> {
> struct drm_device *ddev = dev_get_drvdata(dev);
> struct radeon_device *rdev = ddev->dev_private;
> @@ -366,10 +365,8 @@ static ssize_t radeon_get_pm_profile(struct device *dev,
> (cp == PM_PROFILE_HIGH) ? "high" : "default");
> }
>
> -static ssize_t radeon_set_pm_profile(struct device *dev,
> -struct device_attribute *attr,
> -const char *buf,
> -size_t count)
> +static ssize_t power_profile_store(struct device *dev, struct
> device_attribute *attr,
> + const char *buf, size_t count)
> {
> struct drm_device *ddev = dev_get_drvdata(dev);
> struct radeon_device *rdev = ddev->dev_private;
> @@ -406,9 +403,8 @@ static ssize_t radeon_set_pm_profile(struct device *dev,
> return count;
> }
>
> -static ssize_t radeon_get_pm_method(struct device *dev,
> - struct device_attribute *attr,
> - char *buf)
> +static ssize_t power_method_show(struct device *dev,
> +struct device_attribute *attr, char *buf)
> {
> struct drm_device *ddev = dev_get_drvdata(dev);
> struct radeon_device *rdev = ddev->dev_private;
> @@ -418,10 +414,9 @@ static ssize_t radeon_get_pm_method(struct device *dev,
> (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
> }
>
> -static ssize_t radeon_set_pm_method(struct device *dev,
> - struct device_attribute *attr,
> - const char *buf,
> - size_t count)
> +static ssize_t power_method_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> {
> struct drm_device *ddev = dev_get_drvdata(dev);
> struct radeon_device *rdev = ddev->dev_private;
> @@ -462,9 +457,8 @@ static ssize_t radeon_set_pm_method(struct device *dev,
> return count;
> }
>
> -static ssize_t radeon_get_dpm_state(struct device *dev,
> - struct device_attribute *attr,
> - char *buf)
> +static ssize_t power_dpm_state_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> {
> struct drm_device *ddev = dev_get_drvdata(dev);
> struct radeon_device *rdev = ddev->dev_private;
> @@ -475,10 +469,9 @@ static ssize_t radeon_get_dpm_state(struct device *dev,
> (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" :
> "performance");
> }
>
> -static ssize_t radeon_set_dpm_state(struct device *dev,
> - struct device_attribute *attr,
> - const char *buf,
> - size_t count)
> +static ssize_t power_dpm_state_store(struct device *dev,
> +struct device_attribute *attr,
> +const char *buf, size_t count)
> {
> struct drm_device *ddev = dev_get_drvdata(dev);
> struct radeon_device *rdev = ddev->dev_private;
> @@ -506,9 +499,9 @@ static ssize_t radeon_set_dpm_state(struct device *dev,
> return count;
> }
>
> -static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
> - struct
> device_attribute *attr,
> - char *buf)
> +static ssize_t power_dpm_force_performance_level_show(struct device *dev,
> + struct device_attribute
> *attr,
> +
Re: [PATCH] drm/amdkfd: use resource cursor in svm_migrate_copy_to_vram v2
One change inline, with that fixed,
Reviewed-by and Tested-by: Philip Yang
On 2021-05-28 11:52 a.m., Christian
König wrote:
Access to the mm_node is now forbidden. So instead of hand wiring that
use the cursor functionality.
v2: fix handling as pointed out by Philip.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 68
1 file changed, 10 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index fd8f544f0de2..5ce8fa2ddab0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -29,6 +29,7 @@
#include "amdgpu_object.h"
#include "amdgpu_vm.h"
#include "amdgpu_mn.h"
+#include "amdgpu_res_cursor.h"
#include "kfd_priv.h"
#include "kfd_svm.h"
#include "kfd_migrate.h"
@@ -205,34 +206,6 @@ svm_migrate_copy_done(struct amdgpu_device *adev, struct dma_fence *mfence)
return r;
}
-static uint64_t
-svm_migrate_node_physical_addr(struct amdgpu_device *adev,
- struct drm_mm_node **mm_node, uint64_t *offset)
-{
- struct drm_mm_node *node = *mm_node;
- uint64_t pos = *offset;
-
- if (node->start == AMDGPU_BO_INVALID_OFFSET) {
- pr_debug("drm node is not validated\n");
- return 0;
- }
-
- pr_debug("vram node start 0x%llx npages 0x%llx\n", node->start,
- node->size);
-
- if (pos >= node->size) {
- do {
- pos -= node->size;
- node++;
- } while (pos >= node->size);
-
- *mm_node = node;
- *offset = pos;
- }
-
- return (node->start + pos) << PAGE_SHIFT;
-}
-
unsigned long
svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr)
{
@@ -297,11 +270,9 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
{
uint64_t npages = migrate->cpages;
struct device *dev = adev->dev;
- struct drm_mm_node *node;
+ struct amdgpu_res_cursor cursor;
dma_addr_t *src;
uint64_t *dst;
- uint64_t vram_addr;
- uint64_t offset;
uint64_t i, j;
int r;
@@ -317,19 +288,12 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
goto out;
}
- node = prange->ttm_res->mm_node;
- offset = prange->offset;
- vram_addr = svm_migrate_node_physical_addr(adev, , );
- if (!vram_addr) {
- WARN_ONCE(1, "vram node address is 0\n");
- r = -ENOMEM;
- goto out;
- }
-
+ amdgpu_res_first(prange->ttm_res, prange->offset << PAGE_SHIFT,
+ npages << PAGE_SHIFT, );
for (i = j = 0; i < npages; i++) {
struct page *spage;
- dst[i] = vram_addr + (j << PAGE_SHIFT);
+ dst[i] = cursor.start + (j << PAGE_SHIFT);
migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]);
svm_migrate_get_vram_page(prange, migrate->dst[i]);
@@ -354,18 +318,10 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
mfence);
if (r)
goto out_free_vram_pages;
-offset += j;
-vram_addr = (node->start + offset) << PAGE_SHIFT;
+amdgpu_res_next(, j << PAGE_SHIFT);
j = 0;
} else {
-offset++;
-vram_addr += PAGE_SIZE;
- }
- if (offset >= node->size) {
-node++;
-pr_debug("next node size 0x%llx\n", node->size);
-vram_addr = node->start << PAGE_SHIFT;
-offset = 0;
+amdgpu_res_next(, PAGE_SIZE);
}
continue;
}
@@ -373,19 +329,15 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
pr_debug("dma mapping src to 0x%llx, page_to_pfn 0x%lx\n",
src[i] >> PAGE_SHIFT, page_to_pfn(spage));
- if (j + offset >= node->size - 1 && i < npages - 1) {
+ if (j << PAGE_SHIFT >= cursor.size - 1 && i < npages - 1) {
if (j >= (cursor.size >> PAGE_SHIFT) - 1 && i <
npages - 1) {
r = svm_migrate_copy_memory_gart(adev, src + i - j,
dst + i - j, j + 1,
FROM_RAM_TO_VRAM,
mfence);
if (r)
goto out_free_vram_pages;
-
- node++;
- pr_debug("next node size 0x%llx\n", node->size);
- vram_addr = node->start << PAGE_SHIFT;
- offset = 0;
- j = 0;
+ amdgpu_res_next(, (j + 1) * PAGE_SIZE);
+ j= 0;
} else {
j++;
}
___
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Re: [PATCH RESEND] amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomic
Applied. Thanks!
Alex
On Wed, May 26, 2021 at 10:00 AM Bas Nieuwenhuizen
wrote:
>
> Reviewed-by: Bas Nieuwenhuizen
>
> I think there are plenty more occurrences too or did I miss the
> cleanup of those?
>
> On Wed, May 26, 2021 at 3:56 PM Simon Ser wrote:
> >
> > This allows to tie the log message to a specific DRM device.
> >
> > Signed-off-by: Simon Ser
> > Cc: Alex Deucher
> > Cc: Harry Wentland
> > Cc: Nicholas Kazlauskas
> > ---
> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 2c9d099adfc2..4dd811816cba 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -10089,7 +10089,7 @@ static int dm_check_crtc_cursor(struct
> > drm_atomic_state *state,
> >
> > if (cursor_scale_w != primary_scale_w ||
> > cursor_scale_h != primary_scale_h) {
> > - DRM_DEBUG_ATOMIC("Cursor plane scaling doesn't match
> > primary plane\n");
> > + drm_dbg_atomic(crtc->dev, "Cursor plane scaling doesn't
> > match primary plane\n");
> > return -EINVAL;
> > }
> >
> > --
> > 2.31.1
> >
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH v3] drm/amdkfd: optimize memory mapping latency
1. conditionally flush TLBs after map.
2. add heavy weight TLBs flush after unmap.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 2 +-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 19 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 6 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 10 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 27 +++
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 7 ++---
10 files changed, 46 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 2560977760b3..8f2d6711e12f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -280,7 +280,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
uint64_t *size);
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
- struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
+ struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool
*flush_tlb);
int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
int amdgpu_amdkfd_gpuvm_sync_memory(
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 1fcfa172911a..585b50b6009f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1117,7 +1117,8 @@ static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
static int update_gpuvm_pte(struct kgd_mem *mem,
struct kfd_mem_attachment *entry,
- struct amdgpu_sync *sync)
+ struct amdgpu_sync *sync,
+ bool *flush_tlb)
{
struct amdgpu_bo_va *bo_va = entry->bo_va;
struct amdgpu_device *adev = entry->adev;
@@ -1128,7 +1129,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
return ret;
/* Update the page tables */
- ret = amdgpu_vm_bo_update(adev, bo_va, false);
+ ret = amdgpu_vm_bo_update(adev, bo_va, false, flush_tlb);
if (ret) {
pr_err("amdgpu_vm_bo_update failed\n");
return ret;
@@ -1140,7 +1141,8 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
static int map_bo_to_gpuvm(struct kgd_mem *mem,
struct kfd_mem_attachment *entry,
struct amdgpu_sync *sync,
- bool no_update_pte)
+ bool no_update_pte,
+ bool *flush_tlb)
{
int ret;
@@ -1157,7 +1159,7 @@ static int map_bo_to_gpuvm(struct kgd_mem *mem,
if (no_update_pte)
return 0;
- ret = update_gpuvm_pte(mem, entry, sync);
+ ret = update_gpuvm_pte(mem, entry, sync, flush_tlb);
if (ret) {
pr_err("update_gpuvm_pte() failed\n");
goto update_gpuvm_pte_failed;
@@ -1687,7 +1689,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
}
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
- struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
+ struct kgd_dev *kgd, struct kgd_mem *mem,
+ void *drm_priv, bool *flush_tlb)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
@@ -1775,7 +1778,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
entry->va, entry->va + bo_size, entry);
ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
- is_invalid_userptr);
+ is_invalid_userptr, flush_tlb);
if (ret) {
pr_err("Failed to map bo to gpuvm\n");
goto out_unreserve;
@@ -2469,7 +2472,7 @@ static int validate_invalid_user_pages(struct
amdkfd_process_info *process_info)
continue;
kfd_mem_dmaunmap_attachment(mem, attachment);
- ret = update_gpuvm_pte(mem, attachment, );
+ ret = update_gpuvm_pte(mem, attachment, , NULL);
if (ret) {
pr_err("%s: update PTE failed\n", __func__);
/* make sure this gets validated again */
@@ -2675,7 +2678,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info,
struct dma_fence **ef)
continue;
kfd_mem_dmaunmap_attachment(mem,
[PATCH 2/7] xf86drm: Add function to retrieve char device path
Used to access device controls
Signed-off-by: Andrey Grodzovsky
---
xf86drm.c | 23 +++
xf86drm.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/xf86drm.c b/xf86drm.c
index edfeb347..a5ecd323 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4361,6 +4361,29 @@ drm_public char *drmGetDeviceNameFromFd2(int fd)
#endif
}
+drm_public char *drmGetCharDeviceFromFd(int fd)
+{
+#ifdef __linux__
+struct stat sbuf;
+char path[PATH_MAX + 1];
+unsigned int maj, min;
+
+if (fstat(fd, ))
+return NULL;
+
+maj = major(sbuf.st_rdev);
+min = minor(sbuf.st_rdev);
+
+if (!drmNodeIsDRM(maj, min) || !S_ISCHR(sbuf.st_mode))
+return NULL;
+
+snprintf(path, sizeof(path), "/sys/dev/char/%d:%d", maj, min);
+return strdup(path);
+#else
+return NULL;
+#endif
+}
+
drm_public int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle)
{
struct drm_syncobj_create args;
diff --git a/xf86drm.h b/xf86drm.h
index 9fc06ab8..c172dbc1 100644
--- a/xf86drm.h
+++ b/xf86drm.h
@@ -812,6 +812,7 @@ extern char *drmGetDeviceNameFromFd(int fd);
*/
extern char *drmGetDeviceNameFromFd2(int fd);
extern int drmGetNodeTypeFromFd(int fd);
+extern char *drmGetCharDeviceFromFd(int fd);
/* Convert between GEM handles and DMA-BUF file descriptors.
*
--
2.25.1
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[PATCH 4/7] test/amdgpu/hotunplug: Add test suite for GPU unplug
Add just the test suite skeleton.
Signed-off-by: Andrey Grodzovsky
---
tests/amdgpu/amdgpu_test.c | 11
tests/amdgpu/amdgpu_test.h | 23 +++
tests/amdgpu/hotunplug_tests.c | 116 +
tests/amdgpu/meson.build | 1 +
4 files changed, 151 insertions(+)
create mode 100644 tests/amdgpu/hotunplug_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 2864eaff..a10a031a 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -59,6 +59,7 @@
#define RAS_TESTS_STR "RAS Tests"
#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
#define SECURITY_TESTS_STR "Security Tests"
+#define HOTUNPLUG_TESTS_STR "Hotunplug Tests"
/**
* Open handles for amdgpu devices
@@ -137,6 +138,12 @@ static CU_SuiteInfo suites[] = {
.pCleanupFunc = suite_security_tests_clean,
.pTests = security_tests,
},
+ {
+ .pName = HOTUNPLUG_TESTS_STR,
+ .pInitFunc = suite_hotunplug_tests_init,
+ .pCleanupFunc = suite_hotunplug_tests_clean,
+ .pTests = hotunplug_tests,
+ },
CU_SUITE_INFO_NULL,
};
@@ -198,6 +205,10 @@ static Suites_Active_Status suites_active_stat[] = {
.pName = SECURITY_TESTS_STR,
.pActive = suite_security_tests_enable,
},
+ {
+ .pName = HOTUNPLUG_TESTS_STR,
+ .pActive = suite_hotunplug_tests_enable,
+ },
};
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index 107134a5..e2e35fec 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -273,6 +273,29 @@
amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
unsigned ip_type,
bool secure);
+
+
+/**
+ * Initialize hotunplug test suite
+ */
+int suite_hotunplug_tests_init();
+
+/**
+ * Deinitialize hotunplug test suite
+ */
+int suite_hotunplug_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_hotunplug_tests_enable(void);
+
+/**
+ * Tests in uvd enc test suite
+ */
+extern CU_TestInfo hotunplug_tests[];
+
+
/**
* Helper functions
*/
diff --git a/tests/amdgpu/hotunplug_tests.c b/tests/amdgpu/hotunplug_tests.c
new file mode 100644
index ..9d11dae4
--- /dev/null
+++ b/tests/amdgpu/hotunplug_tests.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#include
+#include
+#include
+#if HAVE_ALLOCA_H
+# include
+#endif
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+
+#include
+
+
+static amdgpu_device_handle device_handle;
+static uint32_t major_version;
+static uint32_t minor_version;
+
+static uint32_t family_id;
+static uint32_t chip_rev;
+static uint32_t chip_id;
+
+CU_BOOL suite_hotunplug_tests_enable(void)
+{
+ CU_BOOL enable = CU_TRUE;
+
+ if (amdgpu_device_initialize(drm_amdgpu[0], _version,
+_version, _handle))
+ return CU_FALSE;
+
+ family_id = device_handle->info.family_id;
+ chip_id = device_handle->info.chip_external_rev;
+ chip_rev = device_handle->info.chip_rev;
+
+ /*
+* Only enable for ASICs supporting GPU reset and for which it's enabled
+* by default (currently GFX8/9 dGPUS)
+*/
+ if (family_id != AMDGPU_FAMILY_VI &&
+ family_id != AMDGPU_FAMILY_AI &&
+ family_id != AMDGPU_FAMILY_CI) {
+ printf("\n\nGPU reset is not enabled for the ASIC, hotunplug
suite disabled\n");
+ enable = CU_FALSE;
+ }
+
+ if
[PATCH 3/7] test/amdgpu: Add helper functions for hot unplug
Expose close device and add open device wich preserves
test index.
Signed-off-by: Andrey Grodzovsky
---
tests/amdgpu/amdgpu_test.c | 31 ---
tests/amdgpu/amdgpu_test.h | 3 +++
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 60f3a508..2864eaff 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -339,12 +339,13 @@ static int amdgpu_open_devices(int open_render_node)
/* Close AMD devices.
*/
-static void amdgpu_close_devices()
+void amdgpu_close_devices()
{
int i;
for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
- if (drm_amdgpu[i] >=0)
+ if (drm_amdgpu[i] >=0) {
close(drm_amdgpu[i]);
+ }
}
/* Print AMD devices information */
@@ -520,6 +521,31 @@ static void amdgpu_disable_suites()
fprintf(stderr, "test deactivation failed - %s\n",
CU_get_error_msg());
}
+int test_device_index;
+
+int amdgpu_open_device_on_test_index(int render_node)
+{
+ int i;
+
+ if (amdgpu_open_devices(open_render_node) <= 0) {
+ perror("Cannot open AMDGPU device");
+ return -1;
+ }
+
+ if (test_device_index >= 0) {
+ /* Most tests run on device of drm_amdgpu[0].
+* Swap the chosen device to drm_amdgpu[0].
+*/
+ i = drm_amdgpu[0];
+ drm_amdgpu[0] = drm_amdgpu[test_device_index];
+ drm_amdgpu[test_device_index] = i;
+ }
+
+ return 0;
+
+
+}
+
/* The main() function for setting up and running the tests.
* Returns a CUE_SUCCESS on successful running, another
* CUnit error code on failure.
@@ -535,7 +561,6 @@ int main(int argc, char **argv)
int display_devices = 0;/* By default not to display devices' info */
CU_pSuite pSuite = NULL;
CU_pTest pTest = NULL;
- int test_device_index;
int display_list = 0;
int force_run = 0;
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index 4970d0dd..107134a5 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -476,4 +476,7 @@ void amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle
device_handle,
struct amdgpu_cs_request *ibs_request,
bool secure);
+void amdgpu_close_devices();
+int amdgpu_open_device_on_test_index(int render_node);
+
#endif /* #ifdef _AMDGPU_TEST_H_ */
--
2.25.1
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[PATCH 7/7] tests/amdgpu/hotunplug: Add hotunplug with exported bo test
Disconnect device while BO is exported.
Signed-off-by: Andrey Grodzovsky
---
tests/amdgpu/hotunplug_tests.c | 46 --
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/tests/amdgpu/hotunplug_tests.c b/tests/amdgpu/hotunplug_tests.c
index 6e133a07..01ac6c62 100644
--- a/tests/amdgpu/hotunplug_tests.c
+++ b/tests/amdgpu/hotunplug_tests.c
@@ -306,10 +306,52 @@ static void amdgpu_hotunplug_with_cs(void)
amdgpu_hotunplug_test(true);
}
+static void amdgpu_hotunplug_with_exported_bo(void)
+{
+ int r;
+ uint32_t dma_buf_fd;
+ unsigned int *ptr;
+ amdgpu_bo_handle bo_handle;
+
+ struct amdgpu_bo_alloc_request request = {
+ .alloc_size = 4096,
+ .phys_alignment = 4096,
+ .preferred_heap = AMDGPU_GEM_DOMAIN_GTT,
+ .flags = 0,
+ };
+
+ r = amdgpu_hotunplug_setup_test();
+ CU_ASSERT_EQUAL(r , 0);
+
+ amdgpu_bo_alloc(device_handle, , _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_export(bo_handle, amdgpu_bo_handle_type_dma_buf_fd,
_buf_fd);
+ CU_ASSERT_EQUAL(r, 0);
+
+ ptr = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, dma_buf_fd,
0);
+ CU_ASSERT_NOT_EQUAL(ptr, MAP_FAILED);
+
+ r = amdgpu_hotunplug_remove();
+ CU_ASSERT_EQUAL(r > 0, 1);
+
+ amdgpu_bo_free(bo_handle);
+
+ r = amdgpu_hotunplug_teardown_test();
+ CU_ASSERT_EQUAL(r , 0);
+
+ *ptr = 0xdeafbeef;
+
+ munmap(ptr, 4096);
+ close (dma_buf_fd);
+
+ r = amdgpu_hotunplug_rescan();
+ CU_ASSERT_EQUAL(r > 0, 1);
+}
+
CU_TestInfo hotunplug_tests[] = {
{ "Unplug card and rescan the bus to plug it back",
amdgpu_hotunplug_simple },
{ "Same as first test but with command submission",
amdgpu_hotunplug_with_cs },
+ { "Unplug with exported bo", amdgpu_hotunplug_with_exported_bo },
CU_TEST_INFO_NULL,
};
-
-
--
2.25.1
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[PATCH 5/7] test/amdgpu/hotunplug: Add basic test
Add plug/unplug device and open/close device file
infrastrucutre.
Add basic test - unplug device while device file still
open. Close device file afterwards and replug the device.
Signed-off-by: Andrey Grodzovsky
---
tests/amdgpu/hotunplug_tests.c | 135 +
1 file changed, 105 insertions(+), 30 deletions(-)
diff --git a/tests/amdgpu/hotunplug_tests.c b/tests/amdgpu/hotunplug_tests.c
index 9d11dae4..c2bc1cf2 100644
--- a/tests/amdgpu/hotunplug_tests.c
+++ b/tests/amdgpu/hotunplug_tests.c
@@ -21,9 +21,11 @@
*
*/
-#include
#include
#include
+#include
+#include
+#include
#if HAVE_ALLOCA_H
# include
#endif
@@ -33,40 +35,40 @@
#include "amdgpu_test.h"
#include "amdgpu_drm.h"
#include "amdgpu_internal.h"
-
+#include "xf86drm.h"
#include
static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
-
-static uint32_t family_id;
-static uint32_t chip_rev;
-static uint32_t chip_id;
+static char *sysfs_remove = NULL;
CU_BOOL suite_hotunplug_tests_enable(void)
{
CU_BOOL enable = CU_TRUE;
+ drmDevicePtr device;
+
+ if (drmGetDevice2(drm_amdgpu[0], DRM_DEVICE_GET_PCI_REVISION, ))
{
+ printf("\n\nGPU Failed to get DRM device PCI info!\n");
+ return CU_FALSE;
+ }
+
+ if (device->bustype != DRM_BUS_PCI) {
+ printf("\n\nGPU device is not on PCI bus!\n");
+ amdgpu_device_deinitialize(device_handle);
+ return CU_FALSE;
+ }
+
+ /* Disable until the hot-unplug support in kernel gets into drm-next */
+ if (major_version < 0xff)
+ enable = false;
if (amdgpu_device_initialize(drm_amdgpu[0], _version,
_version, _handle))
return CU_FALSE;
- family_id = device_handle->info.family_id;
- chip_id = device_handle->info.chip_external_rev;
- chip_rev = device_handle->info.chip_rev;
-
- /*
-* Only enable for ASICs supporting GPU reset and for which it's enabled
-* by default (currently GFX8/9 dGPUS)
-*/
- if (family_id != AMDGPU_FAMILY_VI &&
- family_id != AMDGPU_FAMILY_AI &&
- family_id != AMDGPU_FAMILY_CI) {
- printf("\n\nGPU reset is not enabled for the ASIC, hotunplug
suite disabled\n");
- enable = CU_FALSE;
- }
+ /* TODO Once DRM version for unplug feature ready compare here agains
it*/
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
@@ -75,8 +77,46 @@ CU_BOOL suite_hotunplug_tests_enable(void)
}
int suite_hotunplug_tests_init(void)
+{
+ /* We need to open/close device at each test manually */
+ amdgpu_close_devices();
+
+ return CUE_SUCCESS;
+}
+
+int suite_hotunplug_tests_clean(void)
+{
+
+
+ return CUE_SUCCESS;
+}
+
+static int amdgpu_hotunplug_trigger(const char *pathname)
+{
+ int fd, len;
+
+ fd = open(pathname, O_WRONLY);
+ if (fd < 0)
+ return -errno;
+
+ len = write(fd, "1", 1);
+ close(fd);
+
+ return len;
+}
+
+static int amdgpu_hotunplug_setup_test()
{
int r;
+ char *tmp_str;
+
+ if (amdgpu_open_device_on_test_index(open_render_node) <= 0) {
+ printf("\n\n Failed to reopen device file!\n");
+ return CUE_SINIT_FAILED;
+
+
+
+ }
r = amdgpu_device_initialize(drm_amdgpu[0], _version,
_version, _handle);
@@ -89,27 +129,62 @@ int suite_hotunplug_tests_init(void)
return CUE_SINIT_FAILED;
}
- return CUE_SUCCESS;
+ tmp_str = drmGetCharDeviceFromFd(drm_amdgpu[0]);
+ if (!tmp_str){
+ printf("\n\n Device path not found!\n");
+ return CUE_SINIT_FAILED;
+ }
+
+ sysfs_remove = realloc(tmp_str, strlen(tmp_str) * 2);
+ strcat(sysfs_remove, "/device/remove");
+
+ return 0;
+
}
-int suite_hotunplug_tests_clean(void)
+static int amdgpu_hotunplug_teardown_test()
{
- int r = amdgpu_device_deinitialize(device_handle);
-
- if (r == 0)
- return CUE_SUCCESS;
- else
+ if (amdgpu_device_deinitialize(device_handle))
return CUE_SCLEAN_FAILED;
+
+ amdgpu_close_devices();
+
+ if (sysfs_remove)
+ free(sysfs_remove);
+
+ return 0;
+}
+
+static inline int amdgpu_hotunplug_remove()
+{
+ return amdgpu_hotunplug_trigger(sysfs_remove);
+}
+
+static inline int amdgpu_hotunplug_rescan()
+{
+ return amdgpu_hotunplug_trigger("/sys/bus/pci/rescan");
}
-static void amdgpu_hotunplug_gfx(void)
+static void amdgpu_hotunplug_simple(void)
{
- printf("Hello!\n");
+ int r;
+
+ r = amdgpu_hotunplug_setup_test();
+ CU_ASSERT_EQUAL(r , 0);
+
+ r = amdgpu_hotunplug_remove();
+ CU_ASSERT_EQUAL(r
[PATCH 1/7] tests/amdgpu: Fix valgrind warning
Struct access after free
Signed-off-by: Andrey Grodzovsky
---
tests/amdgpu/basic_tests.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 8e7c4916..8b7fd0f6 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -626,13 +626,14 @@ CU_BOOL suite_basic_tests_enable(void)
_version, _handle))
return CU_FALSE;
- if (amdgpu_device_deinitialize(device_handle))
- return CU_FALSE;
family_id = device_handle->info.family_id;
chip_id = device_handle->info.chip_external_rev;
chip_rev = device_handle->info.chip_rev;
+ if (amdgpu_device_deinitialize(device_handle))
+ return CU_FALSE;
+
/* disable gfx engine basic test cases for some asics have no CPG */
if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
if (amdgpu_set_test_active("Basic Tests",
--
2.25.1
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[PATCH 0/7] libdrm tests for hot-unplug feature
Adding some tests to acompany the recently added hot-unplug feature. For now the test suite is disabled until the feature propagates from drm-misc-next to drm-next. Andrey Grodzovsky (7): tests/amdgpu: Fix valgrind warning xf86drm: Add function to retrieve char device path test/amdgpu: Add helper functions for hot unplug test/amdgpu/hotunplug: Add test suite for GPU unplug test/amdgpu/hotunplug: Add basic test tests/amdgpu/hotunplug: Add unplug with cs test. tests/amdgpu/hotunplug: Add hotunplug with exported bo test tests/amdgpu/amdgpu_test.c | 42 +++- tests/amdgpu/amdgpu_test.h | 26 +++ tests/amdgpu/basic_tests.c | 5 +- tests/amdgpu/hotunplug_tests.c | 357 + tests/amdgpu/meson.build | 1 + xf86drm.c | 23 +++ xf86drm.h | 1 + 7 files changed, 450 insertions(+), 5 deletions(-) create mode 100644 tests/amdgpu/hotunplug_tests.c -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 6/7] tests/amdgpu/hotunplug: Add unplug with cs test.
Same as simple test but while doing cs
Signed-off-by: Andrey Grodzovsky
---
tests/amdgpu/hotunplug_tests.c | 128 -
1 file changed, 126 insertions(+), 2 deletions(-)
diff --git a/tests/amdgpu/hotunplug_tests.c b/tests/amdgpu/hotunplug_tests.c
index c2bc1cf2..6e133a07 100644
--- a/tests/amdgpu/hotunplug_tests.c
+++ b/tests/amdgpu/hotunplug_tests.c
@@ -38,11 +38,13 @@
#include "xf86drm.h"
#include
+#define GFX_COMPUTE_NOP 0x1000
static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
static char *sysfs_remove = NULL;
+static bool do_cs;
CU_BOOL suite_hotunplug_tests_enable(void)
{
@@ -110,7 +112,7 @@ static int amdgpu_hotunplug_setup_test()
int r;
char *tmp_str;
- if (amdgpu_open_device_on_test_index(open_render_node) <= 0) {
+ if (amdgpu_open_device_on_test_index(open_render_node) < 0) {
printf("\n\n Failed to reopen device file!\n");
return CUE_SINIT_FAILED;
@@ -165,17 +167,128 @@ static inline int amdgpu_hotunplug_rescan()
return amdgpu_hotunplug_trigger("/sys/bus/pci/rescan");
}
+static int amdgpu_cs_sync(amdgpu_context_handle context,
+ unsigned int ip_type,
+ int ring,
+ unsigned int seqno)
+{
+ struct amdgpu_cs_fence fence = {
+ .context = context,
+ .ip_type = ip_type,
+ .ring = ring,
+ .fence = seqno,
+ };
+ uint32_t expired;
+
+ return amdgpu_cs_query_fence_status(,
+ AMDGPU_TIMEOUT_INFINITE,
+ 0, );
+}
-static void amdgpu_hotunplug_simple(void)
+static void *amdgpu_nop_cs()
+{
+ amdgpu_bo_handle ib_result_handle;
+ void *ib_result_cpu;
+ uint64_t ib_result_mc_address;
+ uint32_t *ptr;
+ int i, r;
+ amdgpu_bo_list_handle bo_list;
+ amdgpu_va_handle va_handle;
+ amdgpu_context_handle context;
+ struct amdgpu_cs_request ibs_request;
+ struct amdgpu_cs_ib_info ib_info;
+
+ r = amdgpu_cs_ctx_create(device_handle, );
+ CU_ASSERT_EQUAL(r, 0);
+
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
+ _result_handle, _result_cpu,
+ _result_mc_address, _handle);
+ CU_ASSERT_EQUAL(r, 0);
+
+ ptr = ib_result_cpu;
+ for (i = 0; i < 16; ++i)
+ ptr[i] = GFX_COMPUTE_NOP;
+
+ r = amdgpu_bo_list_create(device_handle, 1, _result_handle, NULL,
_list);
+ CU_ASSERT_EQUAL(r, 0);
+
+ memset(_info, 0, sizeof(struct amdgpu_cs_ib_info));
+ ib_info.ib_mc_address = ib_result_mc_address;
+ ib_info.size = 16;
+
+ memset(_request, 0, sizeof(struct amdgpu_cs_request));
+ ibs_request.ip_type = AMDGPU_HW_IP_GFX;
+ ibs_request.ring = 0;
+ ibs_request.number_of_ibs = 1;
+ ibs_request.ibs = _info;
+ ibs_request.resources = bo_list;
+
+ while (do_cs)
+ amdgpu_cs_submit(context, 0, _request, 1);
+
+ r = amdgpu_cs_sync(context, AMDGPU_HW_IP_GFX, 0, ibs_request.seq_no);
+ CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
+
+ amdgpu_bo_list_destroy(bo_list);
+ amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+ib_result_mc_address, 4096);
+
+ amdgpu_cs_ctx_free(context);
+
+ return (void *)0;
+}
+
+static pthread_t* amdgpu_create_cs_thread()
+{
+ int r;
+ pthread_t *thread = malloc(sizeof(*thread));
+ if (!thread)
+ return NULL;
+
+ do_cs = true;
+
+ r = pthread_create(thread, NULL, amdgpu_nop_cs, NULL);
+ CU_ASSERT_EQUAL(r, 0);
+
+ /* Give thread enough time to start*/
+ usleep(10);
+ return thread;
+}
+
+static void amdgpu_destroy_cs_thread(pthread_t *thread)
+{
+ void *status;
+
+ do_cs = false;
+
+ pthread_join(*thread, );
+ CU_ASSERT_EQUAL(status, 0);
+
+ free(thread);
+}
+
+
+static void amdgpu_hotunplug_test(bool with_cs)
{
int r;
+ pthread_t *thread = NULL;
r = amdgpu_hotunplug_setup_test();
CU_ASSERT_EQUAL(r , 0);
+ if (with_cs) {
+ thread = amdgpu_create_cs_thread();
+ CU_ASSERT_NOT_EQUAL(thread, NULL);
+ }
+
r = amdgpu_hotunplug_remove();
CU_ASSERT_EQUAL(r > 0, 1);
+ if (with_cs)
+ amdgpu_destroy_cs_thread(thread);
+
r = amdgpu_hotunplug_teardown_test();
CU_ASSERT_EQUAL(r , 0);
@@ -183,8 +296,19 @@ static void amdgpu_hotunplug_simple(void)
CU_ASSERT_EQUAL(r > 0, 1);
}
+static void amdgpu_hotunplug_simple(void)
+{
+ amdgpu_hotunplug_test(false);
+}
+
+static void
[PATCH 2/4] drm/amdkfd: Don't create crat memory sub-table if node has no memory
In some configuration, there is CPU-only (no memory) numa node. Don't
create crat memory sub-table for such node.
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 56e6dff..420a312 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1583,7 +1583,9 @@ static int kfd_fill_cu_for_cpu(int numa_node_id, int
*avail_size,
* @avail_size: Available size in the memory
* @sub_type_hdr: Memory into which compute info will be filled in
*
- * Return 0 if successful else return -ve value
+ * Return 0 if successful
+ * Return -ENOMEM if not enough space in caller allocated crat table
+ * Return -1 if this numa node has no memory
*/
static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size,
int proximity_domain,
@@ -1615,6 +1617,9 @@ static int kfd_fill_mem_info_for_cpu(int numa_node_id,
int *avail_size,
mem_in_bytes +=
zone_managed_pages(>node_zones[zone_type]);
mem_in_bytes <<= PAGE_SHIFT;
+ if (mem_in_bytes == 0)
+ return -1;
+
sub_type_hdr->length_low = lower_32_bits(mem_in_bytes);
sub_type_hdr->length_high = upper_32_bits(mem_in_bytes);
sub_type_hdr->proximity_domain = proximity_domain;
@@ -1742,15 +1747,19 @@ static int kfd_create_vcrat_image_cpu(void
*pcrat_image, size_t *size)
ret = kfd_fill_mem_info_for_cpu(numa_node_id, _size,
crat_table->num_domains,
(struct crat_subtype_memory *)sub_type_hdr);
- if (ret < 0) {
+ if (ret == -ENOMEM) {
pr_err("fill mem for cpu failed\n");
return ret;
}
- crat_table->length += sub_type_hdr->length;
- crat_table->total_entries++;
- sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
- sub_type_hdr->length);
+ /* ret == -1: this node has no memory */
+ if (ret == 0) {
+ crat_table->length += sub_type_hdr->length;
+ crat_table->total_entries++;
+
+ sub_type_hdr = (typeof(sub_type_hdr))((char
*)sub_type_hdr +
+ sub_type_hdr->length);
+ }
if (kfd_numa_node_to_apic_id(numa_node_id) != -1) {
/* Fill in Subtype: IO Link */
--
2.7.4
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Re: [PATCH v2] drm/amdkfd: optimize memory mapping latency
Am 2021-06-01 um 2:50 p.m. schrieb Eric Huang:
> 1. conditionally flush TLBs after map.
> 2. add heavy weight TLBs flushing after unmap.
>
> Signed-off-by: Eric Huang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 2 +-
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 21 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 27 +++
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++---
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 7 ++---
> 8 files changed, 41 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 2560977760b3..8f2d6711e12f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -280,7 +280,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
> struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
> uint64_t *size);
> int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
> - struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
> + struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool
> *flush_tlb);
> int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
> struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
> int amdgpu_amdkfd_gpuvm_sync_memory(
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 1fcfa172911a..14c8e23c68b9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1117,7 +1117,8 @@ static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
>
> static int update_gpuvm_pte(struct kgd_mem *mem,
> struct kfd_mem_attachment *entry,
> - struct amdgpu_sync *sync)
> + struct amdgpu_sync *sync,
> + bool *flush_tlb)
> {
> struct amdgpu_bo_va *bo_va = entry->bo_va;
> struct amdgpu_device *adev = entry->adev;
> @@ -1127,6 +1128,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
> if (ret)
> return ret;
>
> + bo_va->table_freed = false;
> /* Update the page tables */
> ret = amdgpu_vm_bo_update(adev, bo_va, false);
> if (ret) {
> @@ -1134,13 +1136,17 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
> return ret;
> }
>
> + if (flush_tlb)
> + *flush_tlb = *flush_tlb || bo_va->table_freed;
> +
> return amdgpu_sync_fence(sync, bo_va->last_pt_update);
> }
>
> static int map_bo_to_gpuvm(struct kgd_mem *mem,
> struct kfd_mem_attachment *entry,
> struct amdgpu_sync *sync,
> -bool no_update_pte)
> +bool no_update_pte,
> +bool *flush_tlb)
> {
> int ret;
>
> @@ -1157,7 +1163,7 @@ static int map_bo_to_gpuvm(struct kgd_mem *mem,
> if (no_update_pte)
> return 0;
>
> - ret = update_gpuvm_pte(mem, entry, sync);
> + ret = update_gpuvm_pte(mem, entry, sync, flush_tlb);
> if (ret) {
> pr_err("update_gpuvm_pte() failed\n");
> goto update_gpuvm_pte_failed;
> @@ -1687,7 +1693,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
> }
>
> int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
> - struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
> + struct kgd_dev *kgd, struct kgd_mem *mem,
> + void *drm_priv, bool *flush_tlb)
> {
> struct amdgpu_device *adev = get_amdgpu_device(kgd);
> struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
> @@ -1775,7 +1782,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
>entry->va, entry->va + bo_size, entry);
>
> ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
> - is_invalid_userptr);
> + is_invalid_userptr, flush_tlb);
> if (ret) {
> pr_err("Failed to map bo to gpuvm\n");
> goto out_unreserve;
> @@ -2469,7 +2476,7 @@ static int validate_invalid_user_pages(struct
> amdkfd_process_info *process_info)
> continue;
>
> kfd_mem_dmaunmap_attachment(mem, attachment);
> - ret = update_gpuvm_pte(mem, attachment, );
> + ret = update_gpuvm_pte(mem, attachment, , NULL);
> if (ret) {
> pr_err("%s: update PTE failed\n", __func__);
> /* make sure this gets validated again */
> @@ -2675,7 +2682,7 @@ int
[PATCH 4/4] drm/amdkfd: Patch memory parameters for all CPU nodes
There can be more than one CPU nodes. Patch memory width
and clock info for all CPU nodes, instead of only the first
one.
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 9be66ba..e982829 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1073,10 +1073,10 @@ int kfd_topology_init(void)
if (cpu_only_node) {
/* Add additional information to CPU only node created above */
down_write(_lock);
- kdev = list_first_entry(_device_list,
- struct kfd_topology_device, list);
+ list_for_each_entry(kdev, _device_list, list) {
+ kfd_add_non_crat_information(kdev);
+ }
up_write(_lock);
- kfd_add_non_crat_information(kdev);
}
err:
--
2.7.4
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[PATCH 3/4] drm/amdkfd: Use simd_count to determine whether it is a GPU node
Previously we used cpu_cores_count==0 to determine whether a node
is a GPU node. This is not correct any more since we introduced
memory only numa node. For memory only numa node, cpu_cores_count
is also 0 but it is not a GPU node.
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index dd7772c..87226d5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -835,7 +835,7 @@ static int kfd_parse_subtype_mem(struct crat_subtype_memory
*mem,
list_for_each_entry(dev, device_list, list) {
if (mem->proximity_domain == dev->proximity_domain) {
/* We're on GPU node */
- if (dev->node_props.cpu_cores_count == 0) {
+ if (dev->node_props.simd_count != 0) {
/* APU */
if (mem->visibility_type == 0)
heap_type =
--
2.7.4
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[PATCH 1/4] drm/amdkfd: Create node in kfd sysfs for memory only numa node
Previously kfd driver assumes all CPU numa nodes are associated
with system memory and there is no memory only numa node. This
is not true anymore for ALDEBARAN A+A set up. This patch creates
memory only node in kfd sysfs.
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 73 ---
1 file changed, 42 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 3251fe2..56e6dff 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -827,8 +827,11 @@ static int kfd_parse_subtype_mem(struct
crat_subtype_memory *mem,
uint32_t flags = 0;
uint32_t width;
- pr_debug("Found memory entry in CRAT table with proximity_domain=%d\n",
- mem->proximity_domain);
+ size_in_bytes =
+ ((uint64_t)mem->length_high << 32) +
+ mem->length_low;
+ pr_debug("Found memory entry in CRAT table with proximity_domain=%d,
size %lld\n",
+ mem->proximity_domain, size_in_bytes);
list_for_each_entry(dev, device_list, list) {
if (mem->proximity_domain == dev->proximity_domain) {
/* We're on GPU node */
@@ -848,9 +851,6 @@ static int kfd_parse_subtype_mem(struct crat_subtype_memory
*mem,
if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE)
flags |= HSA_MEM_FLAGS_NON_VOLATILE;
- size_in_bytes =
- ((uint64_t)mem->length_high << 32) +
- mem->length_low;
width = mem->width;
/* Multiple banks of the same type are aggregated into
@@ -1718,51 +1718,62 @@ static int kfd_create_vcrat_image_cpu(void
*pcrat_image, size_t *size)
sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
for_each_online_node(numa_node_id) {
+ pr_debug("numa node id %d\n", numa_node_id);
if (kfd_numa_node_to_apic_id(numa_node_id) == -1)
- continue;
-
- /* Fill in Subtype: Compute Unit */
- ret = kfd_fill_cu_for_cpu(numa_node_id, _size,
- crat_table->num_domains,
- (struct crat_subtype_computeunit *)sub_type_hdr);
- if (ret < 0)
- return ret;
- crat_table->length += sub_type_hdr->length;
- crat_table->total_entries++;
+ pr_debug("Numa node %d is a memory only numa node\n",
numa_node_id);
+
+ if (kfd_numa_node_to_apic_id(numa_node_id) != -1) {
+ /* Fill in Subtype: Compute Unit */
+ ret = kfd_fill_cu_for_cpu(numa_node_id, _size,
+ crat_table->num_domains,
+ (struct crat_subtype_computeunit
*)sub_type_hdr);
+ if (ret < 0) {
+ pr_err("fill cu for cpu failed\n");
+ return ret;
+ }
+ crat_table->length += sub_type_hdr->length;
+ crat_table->total_entries++;
- sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
- sub_type_hdr->length);
+ sub_type_hdr = (typeof(sub_type_hdr))((char
*)sub_type_hdr +
+ sub_type_hdr->length);
+ }
/* Fill in Subtype: Memory */
ret = kfd_fill_mem_info_for_cpu(numa_node_id, _size,
crat_table->num_domains,
(struct crat_subtype_memory *)sub_type_hdr);
- if (ret < 0)
+ if (ret < 0) {
+ pr_err("fill mem for cpu failed\n");
return ret;
+ }
crat_table->length += sub_type_hdr->length;
crat_table->total_entries++;
sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
sub_type_hdr->length);
- /* Fill in Subtype: IO Link */
+ if (kfd_numa_node_to_apic_id(numa_node_id) != -1) {
+ /* Fill in Subtype: IO Link */
#ifdef CONFIG_X86_64
- ret = kfd_fill_iolink_info_for_cpu(numa_node_id, _size,
- ,
- (struct crat_subtype_iolink *)sub_type_hdr);
- if (ret < 0)
- return ret;
+ ret = kfd_fill_iolink_info_for_cpu(numa_node_id,
_size,
+ ,
+ (struct crat_subtype_iolink
*)sub_type_hdr);
+ if (ret < 0) {
+
[PATCH 2/4] drm/amdkfd: Don't create crat memory sub-table if node has no memory
In some configuration, there is CPU-only (no memory) numa node. Don't
create crat memory sub-table for such node.
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 56e6dff..dd7772c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1583,7 +1583,8 @@ static int kfd_fill_cu_for_cpu(int numa_node_id, int
*avail_size,
* @avail_size: Available size in the memory
* @sub_type_hdr: Memory into which compute info will be filled in
*
- * Return 0 if successful else return -ve value
+ * Return memory size in bytes if successful else return -ve value
+ * Returning 0 means this numa node has no memory
*/
static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size,
int proximity_domain,
@@ -1619,7 +1620,7 @@ static int kfd_fill_mem_info_for_cpu(int numa_node_id,
int *avail_size,
sub_type_hdr->length_high = upper_32_bits(mem_in_bytes);
sub_type_hdr->proximity_domain = proximity_domain;
- return 0;
+ return mem_in_bytes;
}
#ifdef CONFIG_X86_64
@@ -1746,11 +1747,15 @@ static int kfd_create_vcrat_image_cpu(void
*pcrat_image, size_t *size)
pr_err("fill mem for cpu failed\n");
return ret;
}
- crat_table->length += sub_type_hdr->length;
- crat_table->total_entries++;
- sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
- sub_type_hdr->length);
+ /* ret == 0: this node has no memory */
+ if (ret > 0) {
+ crat_table->length += sub_type_hdr->length;
+ crat_table->total_entries++;
+
+ sub_type_hdr = (typeof(sub_type_hdr))((char
*)sub_type_hdr +
+ sub_type_hdr->length);
+ }
if (kfd_numa_node_to_apic_id(numa_node_id) != -1) {
/* Fill in Subtype: IO Link */
--
2.7.4
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[PATCH v2] drm/amdkfd: optimize memory mapping latency
1. conditionally flush TLBs after map.
2. add heavy weight TLBs flushing after unmap.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 2 +-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 21 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 27 +++
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 7 ++---
8 files changed, 41 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 2560977760b3..8f2d6711e12f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -280,7 +280,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
uint64_t *size);
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
- struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
+ struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool
*flush_tlb);
int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
int amdgpu_amdkfd_gpuvm_sync_memory(
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 1fcfa172911a..14c8e23c68b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1117,7 +1117,8 @@ static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
static int update_gpuvm_pte(struct kgd_mem *mem,
struct kfd_mem_attachment *entry,
- struct amdgpu_sync *sync)
+ struct amdgpu_sync *sync,
+ bool *flush_tlb)
{
struct amdgpu_bo_va *bo_va = entry->bo_va;
struct amdgpu_device *adev = entry->adev;
@@ -1127,6 +1128,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
if (ret)
return ret;
+ bo_va->table_freed = false;
/* Update the page tables */
ret = amdgpu_vm_bo_update(adev, bo_va, false);
if (ret) {
@@ -1134,13 +1136,17 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
return ret;
}
+ if (flush_tlb)
+ *flush_tlb = *flush_tlb || bo_va->table_freed;
+
return amdgpu_sync_fence(sync, bo_va->last_pt_update);
}
static int map_bo_to_gpuvm(struct kgd_mem *mem,
struct kfd_mem_attachment *entry,
struct amdgpu_sync *sync,
- bool no_update_pte)
+ bool no_update_pte,
+ bool *flush_tlb)
{
int ret;
@@ -1157,7 +1163,7 @@ static int map_bo_to_gpuvm(struct kgd_mem *mem,
if (no_update_pte)
return 0;
- ret = update_gpuvm_pte(mem, entry, sync);
+ ret = update_gpuvm_pte(mem, entry, sync, flush_tlb);
if (ret) {
pr_err("update_gpuvm_pte() failed\n");
goto update_gpuvm_pte_failed;
@@ -1687,7 +1693,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
}
int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
- struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
+ struct kgd_dev *kgd, struct kgd_mem *mem,
+ void *drm_priv, bool *flush_tlb)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
@@ -1775,7 +1782,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
entry->va, entry->va + bo_size, entry);
ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
- is_invalid_userptr);
+ is_invalid_userptr, flush_tlb);
if (ret) {
pr_err("Failed to map bo to gpuvm\n");
goto out_unreserve;
@@ -2469,7 +2476,7 @@ static int validate_invalid_user_pages(struct
amdkfd_process_info *process_info)
continue;
kfd_mem_dmaunmap_attachment(mem, attachment);
- ret = update_gpuvm_pte(mem, attachment, );
+ ret = update_gpuvm_pte(mem, attachment, , NULL);
if (ret) {
pr_err("%s: update PTE failed\n", __func__);
/* make sure this gets validated again */
@@ -2675,7 +2682,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info,
struct dma_fence **ef)
continue;
kfd_mem_dmaunmap_attachment(mem, attachment);
-
[PATCH v3 7/8] drm/amd/pm: Add renoir throttler translation
Perform dependent to independent throttle status translation
for renoir. Makes use of lookup table renoir_throttler_map.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 41 ---
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 1c399c4ab4dc..4071a116af75 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -128,6 +128,22 @@ static struct cmn2asic_mapping
renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] =
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,
WORKLOAD_PPLIB_CUSTOM_BIT),
};
+static const uint8_t renoir_throttler_map[] = {
+ [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
+ [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
+ [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
+ [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
+ [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
+ [THROTTLER_STATUS_BIT_THM_GFX] =
(SMU_THROTTLER_TEMP_VR_GFX_BIT),
+ [THROTTLER_STATUS_BIT_THM_SOC] =
(SMU_THROTTLER_TEMP_VR_SOC_BIT),
+ [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
+ [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
+ [THROTTLER_STATUS_BIT_PROCHOT_CPU] =
(SMU_THROTTLER_PROCHOT_CPU_BIT),
+ [THROTTLER_STATUS_BIT_PROCHOT_GFX] =
(SMU_THROTTLER_PROCHOT_GFX_BIT),
+ [THROTTLER_STATUS_BIT_EDC_CPU] = (SMU_THROTTLER_EDC_CPU_BIT),
+ [THROTTLER_STATUS_BIT_EDC_GFX] = (SMU_THROTTLER_EDC_GFX_BIT),
+};
+
static int renoir_init_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = >smu_table;
@@ -153,7 +169,7 @@ static int renoir_init_smc_tables(struct smu_context *smu)
if (!smu_table->watermarks_table)
goto err2_out;
- smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
+ smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
smu_table->gpu_metrics_table =
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table)
goto err3_out;
@@ -170,6 +186,19 @@ static int renoir_init_smc_tables(struct smu_context *smu)
return -ENOMEM;
}
+static uint64_t renoir_get_indep_throttler_status(
+ const unsigned long dep_status)
+{
+ uint64_t indep_status = 0;
+ uint8_t dep_bit = 0;
+
+ for_each_set_bit(dep_bit, _status, 32)
+ indep_status |= smu_u64_throttler_bit(dep_status,
+ renoir_throttler_map[dep_bit], dep_bit);
+
+ return indep_status;
+}
+
/*
* This interface just for getting uclk ultimate freq and should't introduce
* other likewise function result in overmuch callback.
@@ -1264,8 +1293,8 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context
*smu,
void **table)
{
struct smu_table_context *smu_table = >smu_table;
- struct gpu_metrics_v2_1 *gpu_metrics =
- (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+ struct gpu_metrics_v2_2 *gpu_metrics =
+ (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
SmuMetrics_t metrics;
int ret = 0;
@@ -1273,7 +1302,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context
*smu,
if (ret)
return ret;
- smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+ smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
gpu_metrics->temperature_gfx = metrics.GfxTemperature;
gpu_metrics->temperature_soc = metrics.SocTemperature;
@@ -1311,6 +1340,8 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context
*smu,
gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+ gpu_metrics->indep_throttle_status =
+ renoir_get_indep_throttler_status(metrics.ThrottlerStatus);
gpu_metrics->fan_pwm = metrics.FanPwm;
@@ -1318,7 +1349,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context
*smu,
*table = (void *)gpu_metrics;
- return sizeof(struct gpu_metrics_v2_1);
+ return sizeof(struct gpu_metrics_v2_2);
}
static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
--
2.17.1
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[PATCH v3 5/8] drm/amd/pm: Add sienna cichlid throttler translation
Perform dependent to independent throttle status translation
for sienna cichlid. Makes use of lookup table
sienna_cichlid_throttler_map.
Signed-off-by: Graham Sider
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 46 +--
1 file changed, 41 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 75acdb80c499..c26983a860ff 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -239,6 +239,27 @@ static struct cmn2asic_mapping
sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,
WORKLOAD_PPLIB_CUSTOM_BIT),
};
+static const uint8_t sienna_cichlid_throttler_map[] = {
+ [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
+ [THROTTLER_TEMP_HOTSPOT_BIT]= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+ [THROTTLER_TEMP_MEM_BIT]= (SMU_THROTTLER_TEMP_MEM_BIT),
+ [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+ [THROTTLER_TEMP_VR_MEM0_BIT]= (SMU_THROTTLER_TEMP_VR_MEM_BIT),
+ [THROTTLER_TEMP_VR_MEM1_BIT]= (SMU_THROTTLER_TEMP_VR_MEM_BIT),
+ [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+ [THROTTLER_TEMP_LIQUID0_BIT]= (SMU_THROTTLER_TEMP_LIQUID_BIT),
+ [THROTTLER_TEMP_LIQUID1_BIT]= (SMU_THROTTLER_TEMP_LIQUID_BIT),
+ [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
+ [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
+ [THROTTLER_PPT0_BIT]= (SMU_THROTTLER_PPT0_BIT),
+ [THROTTLER_PPT1_BIT]= (SMU_THROTTLER_PPT1_BIT),
+ [THROTTLER_PPT2_BIT]= (SMU_THROTTLER_PPT2_BIT),
+ [THROTTLER_PPT3_BIT]= (SMU_THROTTLER_PPT3_BIT),
+ [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
+ [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
+ [THROTTLER_APCC_BIT]= (SMU_THROTTLER_APCC_BIT),
+};
+
static int
sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
uint32_t *feature_mask, uint32_t num)
@@ -434,7 +455,7 @@ static int sienna_cichlid_tables_init(struct smu_context
*smu)
goto err0_out;
smu_table->metrics_time = 0;
- smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+ smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
smu_table->gpu_metrics_table =
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table)
goto err1_out;
@@ -453,6 +474,19 @@ static int sienna_cichlid_tables_init(struct smu_context
*smu)
return -ENOMEM;
}
+static uint64_t sienna_cichlid_get_indep_throttler_status(
+ const unsigned long dep_status)
+{
+ uint64_t indep_status = 0;
+ uint8_t dep_bit = 0;
+
+ for_each_set_bit(dep_bit, _status, 32)
+ indep_status |= smu_u64_throttler_bit(dep_status,
+ sienna_cichlid_throttler_map[dep_bit], dep_bit);
+
+ return indep_status;
+}
+
static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
MetricsMember_t member,
uint32_t *value)
@@ -3617,8 +3651,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct
smu_context *smu,
void **table)
{
struct smu_table_context *smu_table = >smu_table;
- struct gpu_metrics_v1_1 *gpu_metrics =
- (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+ struct gpu_metrics_v1_3 *gpu_metrics =
+ (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
SmuMetricsExternal_t metrics_external;
SmuMetrics_t *metrics =
&(metrics_external.SmuMetrics);
@@ -3632,7 +3666,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct
smu_context *smu,
if (ret)
return ret;
- smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+ smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
gpu_metrics->temperature_edge = metrics->TemperatureEdge;
gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot;
@@ -3667,6 +3701,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct
smu_context *smu,
gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
gpu_metrics->throttle_status = metrics->ThrottlerStatus;
+ gpu_metrics->indep_throttle_status =
+
sienna_cichlid_get_indep_throttler_status(metrics->ThrottlerStatus);
gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
@@ -3689,7 +3725,7 @@ static ssize_t
[PATCH v3 4/8] drm/amd/pm: Add navi1x throttler translation
Perform dependent to independent throttle status translation
for navi1x. Makes use of lookup table navi1x_throttler_map.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 +++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 78fe13183e8b..bf376b1be08d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -238,6 +238,28 @@ static struct cmn2asic_mapping
navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] =
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,
WORKLOAD_PPLIB_CUSTOM_BIT),
};
+static const uint8_t navi1x_throttler_map[] = {
+ [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
+ [THROTTLER_TEMP_HOTSPOT_BIT]= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+ [THROTTLER_TEMP_MEM_BIT]= (SMU_THROTTLER_TEMP_MEM_BIT),
+ [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+ [THROTTLER_TEMP_VR_MEM0_BIT]= (SMU_THROTTLER_TEMP_VR_MEM_BIT),
+ [THROTTLER_TEMP_VR_MEM1_BIT]= (SMU_THROTTLER_TEMP_VR_MEM_BIT),
+ [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+ [THROTTLER_TEMP_LIQUID0_BIT]= (SMU_THROTTLER_TEMP_LIQUID_BIT),
+ [THROTTLER_TEMP_LIQUID1_BIT]= (SMU_THROTTLER_TEMP_LIQUID_BIT),
+ [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
+ [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
+ [THROTTLER_PPT0_BIT]= (SMU_THROTTLER_PPT0_BIT),
+ [THROTTLER_PPT1_BIT]= (SMU_THROTTLER_PPT1_BIT),
+ [THROTTLER_PPT2_BIT]= (SMU_THROTTLER_PPT2_BIT),
+ [THROTTLER_PPT3_BIT]= (SMU_THROTTLER_PPT3_BIT),
+ [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
+ [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
+ [THROTTLER_APCC_BIT]= (SMU_THROTTLER_APCC_BIT),
+};
+
+
static bool is_asic_secure(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
@@ -524,6 +546,19 @@ static int navi10_tables_init(struct smu_context *smu)
return -ENOMEM;
}
+static uint64_t navi1x_get_indep_throttler_status(
+ const unsigned long dep_status)
+{
+ uint64_t indep_status = 0;
+ uint8_t dep_bit = 0;
+
+ for_each_set_bit(dep_bit, _status, 32)
+ indep_status |= smu_u64_throttler_bit(dep_status,
+ navi1x_throttler_map[dep_bit], dep_bit);
+
+ return indep_status;
+}
+
static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu,
MetricsMember_t member,
uint32_t *value)
@@ -2673,6 +2708,8 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct
smu_context *smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+ gpu_metrics->indep_throttle_status =
+
navi1x_get_indep_throttler_status(metrics.ThrottlerStatus);
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
@@ -2750,6 +2787,8 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context
*smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+ gpu_metrics->indep_throttle_status =
+
navi1x_get_indep_throttler_status(metrics.ThrottlerStatus);
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
@@ -2826,6 +2865,8 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct
smu_context *smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+ gpu_metrics->indep_throttle_status =
+
navi1x_get_indep_throttler_status(metrics.ThrottlerStatus);
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
@@ -2908,6 +2949,8 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context
*smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+ gpu_metrics->indep_throttle_status =
+
navi1x_get_indep_throttler_status(metrics.ThrottlerStatus);
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 6/8] drm/amd/pm: Add vangogh throttler translation
Perform dependent to independent throttle status translation
for vangogh. Makes use of lookup table vangogh_throttler_map.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 49 +++
1 file changed, 40 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 77f532a49e37..ab3c2df87c98 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -190,6 +190,20 @@ static struct cmn2asic_mapping
vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT]
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,
WORKLOAD_PPLIB_CUSTOM_BIT),
};
+static const uint8_t vangogh_throttler_map[] = {
+ [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
+ [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
+ [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
+ [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
+ [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
+ [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+ [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+ [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
+ [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
+ [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT),
+ [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
+};
+
static int vangogh_tables_init(struct smu_context *smu)
{
struct smu_table_context *smu_table = >smu_table;
@@ -226,7 +240,7 @@ static int vangogh_tables_init(struct smu_context *smu)
goto err0_out;
smu_table->metrics_time = 0;
- smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
+ smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
smu_table->gpu_metrics_table =
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table)
goto err1_out;
@@ -251,6 +265,19 @@ static int vangogh_tables_init(struct smu_context *smu)
return -ENOMEM;
}
+static uint64_t vangogh_get_indep_throttler_status(
+ const unsigned long dep_status)
+{
+ uint64_t indep_status = 0;
+ uint8_t dep_bit = 0;
+
+ for_each_set_bit(dep_bit, _status, 32)
+ indep_status |= smu_u64_throttler_bit(dep_status,
+ vangogh_throttler_map[dep_bit], dep_bit);
+
+ return indep_status;
+}
+
static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
MetricsMember_t member,
uint32_t *value)
@@ -1632,8 +1659,8 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct
smu_context *smu,
void **table)
{
struct smu_table_context *smu_table = >smu_table;
- struct gpu_metrics_v2_1 *gpu_metrics =
- (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+ struct gpu_metrics_v2_2 *gpu_metrics =
+ (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
SmuMetrics_legacy_t metrics;
int ret = 0;
@@ -1641,7 +1668,7 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct
smu_context *smu,
if (ret)
return ret;
- smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+ smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
gpu_metrics->temperature_gfx = metrics.GfxTemperature;
gpu_metrics->temperature_soc = metrics.SocTemperature;
@@ -1674,20 +1701,22 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct
smu_context *smu,
gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+ gpu_metrics->indep_throttle_status =
+
vangogh_get_indep_throttler_status(metrics.ThrottlerStatus);
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
*table = (void *)gpu_metrics;
- return sizeof(struct gpu_metrics_v2_1);
+ return sizeof(struct gpu_metrics_v2_2);
}
static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
void **table)
{
struct smu_table_context *smu_table = >smu_table;
- struct gpu_metrics_v2_1 *gpu_metrics =
- (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+ struct gpu_metrics_v2_2 *gpu_metrics =
+ (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
SmuMetrics_t metrics;
int ret = 0;
@@ -1695,7 +1724,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context
*smu,
if (ret)
return ret;
- smu_cmn_init_soft_gpu_metrics(gpu_metrics,
[PATCH v3 8/8] drm/amd/pm: Add aldebaran throttler translation
Perform dependent to independent throttle status translation
for aldebaran. Makes use of lookup table aldebaran_throttler_map.
Signed-off-by: Graham Sider
---
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 39 ---
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 7a1abb3d6a7a..abb8f3bcf1dc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -191,6 +191,20 @@ static const struct cmn2asic_mapping
aldebaran_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(I2C_COMMANDS),
};
+static const uint8_t aldebaran_throttler_map[] = {
+ [THROTTLER_PPT0_BIT]= (SMU_THROTTLER_PPT0_BIT),
+ [THROTTLER_PPT1_BIT]= (SMU_THROTTLER_PPT1_BIT),
+ [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
+ [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
+ [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT),
+ [THROTTLER_TEMP_GPU_BIT]= (SMU_THROTTLER_TEMP_GPU_BIT),
+ [THROTTLER_TEMP_MEM_BIT]= (SMU_THROTTLER_TEMP_MEM_BIT),
+ [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+ [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+ [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM_BIT),
+ [THROTTLER_APCC_BIT]= (SMU_THROTTLER_APCC_BIT),
+};
+
static int aldebaran_tables_init(struct smu_context *smu)
{
struct smu_table_context *smu_table = >smu_table;
@@ -213,7 +227,7 @@ static int aldebaran_tables_init(struct smu_context *smu)
return -ENOMEM;
smu_table->metrics_time = 0;
- smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_2);
+ smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
smu_table->gpu_metrics_table =
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table) {
kfree(smu_table->metrics_table);
@@ -517,6 +531,19 @@ static int aldebaran_freqs_in_same_level(int32_t
frequency1,
return (abs(frequency1 - frequency2) <= EPSILON);
}
+static uint64_t aldebaran_get_indep_throttler_status(
+ const unsigned long dep_status)
+{
+ uint64_t indep_status = 0;
+ uint8_t dep_bit = 0;
+
+ for_each_set_bit(dep_bit, _status, 32)
+ indep_status |= smu_u64_throttler_bit(dep_status,
+ aldebaran_throttler_map[dep_bit], dep_bit);
+
+ return indep_status;
+}
+
static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
MetricsMember_t member,
uint32_t *value)
@@ -1713,8 +1740,8 @@ static ssize_t aldebaran_get_gpu_metrics(struct
smu_context *smu,
void **table)
{
struct smu_table_context *smu_table = >smu_table;
- struct gpu_metrics_v1_2 *gpu_metrics =
- (struct gpu_metrics_v1_2 *)smu_table->gpu_metrics_table;
+ struct gpu_metrics_v1_3 *gpu_metrics =
+ (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
SmuMetrics_t metrics;
int i, ret = 0;
@@ -1724,7 +1751,7 @@ static ssize_t aldebaran_get_gpu_metrics(struct
smu_context *smu,
if (ret)
return ret;
- smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 2);
+ smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
gpu_metrics->temperature_edge = metrics.TemperatureEdge;
gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -1755,6 +1782,8 @@ static ssize_t aldebaran_get_gpu_metrics(struct
smu_context *smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+ gpu_metrics->indep_throttle_status =
+
aldebaran_get_indep_throttler_status(metrics.ThrottlerStatus);
gpu_metrics->current_fan_speed = 0;
@@ -1776,7 +1805,7 @@ static ssize_t aldebaran_get_gpu_metrics(struct
smu_context *smu,
*table = (void *)gpu_metrics;
- return sizeof(struct gpu_metrics_v1_2);
+ return sizeof(struct gpu_metrics_v1_3);
}
static int aldebaran_mode2_reset(struct smu_context *smu)
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 3/8] drm/amd/pm: Add arcturus throttler translation
Perform dependent to independent throttle status translation
for arcturus. Makes use of lookup table arcturus_throttler_map.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 45 ---
1 file changed, 40 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 1735a96dd307..c0bfd5634fca 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -211,6 +211,26 @@ static const struct cmn2asic_mapping
arcturus_workload_map[PP_SMC_POWER_PROFILE_
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,
WORKLOAD_PPLIB_CUSTOM_BIT),
};
+static const uint8_t arcturus_throttler_map[] = {
+ [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
+ [THROTTLER_TEMP_HOTSPOT_BIT]= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+ [THROTTLER_TEMP_MEM_BIT]= (SMU_THROTTLER_TEMP_MEM_BIT),
+ [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+ [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM_BIT),
+ [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+ [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
+ [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
+ [THROTTLER_PPT0_BIT]= (SMU_THROTTLER_PPT0_BIT),
+ [THROTTLER_PPT1_BIT]= (SMU_THROTTLER_PPT1_BIT),
+ [THROTTLER_PPT2_BIT]= (SMU_THROTTLER_PPT2_BIT),
+ [THROTTLER_PPT3_BIT]= (SMU_THROTTLER_PPT3_BIT),
+ [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
+ [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
+ [THROTTLER_APCC_BIT]= (SMU_THROTTLER_APCC_BIT),
+ [THROTTLER_VRHOT0_BIT] = (SMU_THROTTLER_VRHOT0_BIT),
+ [THROTTLER_VRHOT1_BIT] = (SMU_THROTTLER_VRHOT1_BIT),
+};
+
static int arcturus_tables_init(struct smu_context *smu)
{
struct smu_table_context *smu_table = >smu_table;
@@ -237,7 +257,7 @@ static int arcturus_tables_init(struct smu_context *smu)
return -ENOMEM;
smu_table->metrics_time = 0;
- smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+ smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
smu_table->gpu_metrics_table =
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table) {
kfree(smu_table->metrics_table);
@@ -540,6 +560,19 @@ static int arcturus_freqs_in_same_level(int32_t frequency1,
return (abs(frequency1 - frequency2) <= EPSILON);
}
+static uint64_t arcturus_get_indep_throttler_status(
+ const unsigned long dep_status)
+{
+ uint64_t indep_status = 0;
+ uint8_t dep_bit = 0;
+
+ for_each_set_bit(dep_bit, _status, 32)
+ indep_status |= smu_u64_throttler_bit(dep_status,
+ arcturus_throttler_map[dep_bit], dep_bit);
+
+ return indep_status;
+}
+
static int arcturus_get_smu_metrics_data(struct smu_context *smu,
MetricsMember_t member,
uint32_t *value)
@@ -2275,8 +2308,8 @@ static ssize_t arcturus_get_gpu_metrics(struct
smu_context *smu,
void **table)
{
struct smu_table_context *smu_table = >smu_table;
- struct gpu_metrics_v1_1 *gpu_metrics =
- (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+ struct gpu_metrics_v1_3 *gpu_metrics =
+ (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
SmuMetrics_t metrics;
int ret = 0;
@@ -2286,7 +2319,7 @@ static ssize_t arcturus_get_gpu_metrics(struct
smu_context *smu,
if (ret)
return ret;
- smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+ smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
gpu_metrics->temperature_edge = metrics.TemperatureEdge;
gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -2315,6 +2348,8 @@ static ssize_t arcturus_get_gpu_metrics(struct
smu_context *smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+ gpu_metrics->indep_throttle_status =
+
arcturus_get_indep_throttler_status(metrics.ThrottlerStatus);
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
@@ -2327,7 +2362,7 @@ static ssize_t arcturus_get_gpu_metrics(struct
smu_context *smu,
*table = (void *)gpu_metrics;
- return sizeof(struct gpu_metrics_v1_1);
+ return sizeof(struct gpu_metrics_v1_3);
}
static const struct pptable_funcs arcturus_ppt_funcs = {
--
2.17.1
[PATCH v3 1/8] drm/amd/pm: Add u64 throttler status field to gpu_metrics
This patch set adds support for a new ASIC independent u64 throttler
status field (indep_throttle_status). Piggybacks off the
gpu_metrics_v1_3 bump and similarly bumps gpu_metrics_v2 version (to
v2_2) to add field. Adding this new field allows us to allocate 16
bits to each type of throttler information for more leeway in adding
additional throttler bits in the future.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 58 ++-
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 3 +
2 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index b1cd52a9d684..a6436c331f46 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -577,7 +577,7 @@ struct gpu_metrics_v1_3 {
uint16_tcurrent_vclk1;
uint16_tcurrent_dclk1;
- /* Throttle status */
+ /* Throttle status (ASIC dependent) */
uint32_tthrottle_status;
/* Fans */
@@ -603,6 +603,9 @@ struct gpu_metrics_v1_3 {
uint16_tvoltage_mem;
uint16_tpadding1;
+
+ /* Throttle status (ASIC independent) */
+ uint64_tindep_throttle_status;
};
/*
@@ -709,4 +712,57 @@ struct gpu_metrics_v2_1 {
uint16_tpadding[3];
};
+struct gpu_metrics_v2_2 {
+ struct metrics_table_header common_header;
+
+ /* Temperature */
+ uint16_ttemperature_gfx; // gfx temperature on
APUs
+ uint16_ttemperature_soc; // soc temperature on
APUs
+ uint16_ttemperature_core[8]; // CPU core
temperature on APUs
+ uint16_ttemperature_l3[2];
+
+ /* Utilization */
+ uint16_taverage_gfx_activity;
+ uint16_taverage_mm_activity; // UVD or VCN
+
+ /* Driver attached timestamp (in ns) */
+ uint64_tsystem_clock_counter;
+
+ /* Power/Energy */
+ uint16_taverage_socket_power; // dGPU + APU
power on A + A platform
+ uint16_taverage_cpu_power;
+ uint16_taverage_soc_power;
+ uint16_taverage_gfx_power;
+ uint16_taverage_core_power[8]; // CPU core
power on APUs
+
+ /* Average clocks */
+ uint16_taverage_gfxclk_frequency;
+ uint16_taverage_socclk_frequency;
+ uint16_taverage_uclk_frequency;
+ uint16_taverage_fclk_frequency;
+ uint16_taverage_vclk_frequency;
+ uint16_taverage_dclk_frequency;
+
+ /* Current clocks */
+ uint16_tcurrent_gfxclk;
+ uint16_tcurrent_socclk;
+ uint16_tcurrent_uclk;
+ uint16_tcurrent_fclk;
+ uint16_tcurrent_vclk;
+ uint16_tcurrent_dclk;
+ uint16_tcurrent_coreclk[8]; // CPU core clocks
+ uint16_tcurrent_l3clk[2];
+
+ /* Throttle status (ASIC dependent) */
+ uint32_tthrottle_status;
+
+ /* Fans */
+ uint16_tfan_pwm;
+
+ uint16_tpadding[3];
+
+ /* Throttle status (ASIC independent) */
+ uint64_tindep_throttle_status;
+};
+
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 0ceb7329838c..01645537d9ab 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -773,6 +773,9 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t
frev, uint8_t crev)
case METRICS_VERSION(2, 1):
structure_size = sizeof(struct gpu_metrics_v2_1);
break;
+ case METRICS_VERSION(2, 2):
+ structure_size = sizeof(struct gpu_metrics_v2_2);
+ break;
default:
return;
}
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 2/8] drm/amd/pm: Add ASIC independent throttle bits
Add new defines for thermal throttle status bits which are ASIC
independent. This bit field will be visible to userspace via
gpu_metrics alongside the previous ASIC dependent bit fields. Separated
into four 16-bit types: power throttlers, current throttlers,
temperature, other.
Define macro smu_u64_throttler_bit to handle u32 -> u64,
dependent -> independent throttle bit translations.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 42 +
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 523f9d2982e9..86aa699f6c0c 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -35,6 +35,48 @@
#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
+// Power Throttlers
+#define SMU_THROTTLER_PPT0_BIT 0
+#define SMU_THROTTLER_PPT1_BIT 1
+#define SMU_THROTTLER_PPT2_BIT 2
+#define SMU_THROTTLER_PPT3_BIT 3
+#define SMU_THROTTLER_SPL_BIT 4
+#define SMU_THROTTLER_FPPT_BIT 5
+#define SMU_THROTTLER_SPPT_BIT 6
+#define SMU_THROTTLER_SPPT_APU_BIT 7
+
+// Current Throttlers
+#define SMU_THROTTLER_TDC_GFX_BIT 16
+#define SMU_THROTTLER_TDC_SOC_BIT 17
+#define SMU_THROTTLER_TDC_MEM_BIT 18
+#define SMU_THROTTLER_TDC_VDD_BIT 19
+#define SMU_THROTTLER_TDC_CVIP_BIT 20
+#define SMU_THROTTLER_EDC_CPU_BIT 21
+#define SMU_THROTTLER_EDC_GFX_BIT 22
+#define SMU_THROTTLER_APCC_BIT 23
+
+// Temperature
+#define SMU_THROTTLER_TEMP_GPU_BIT 32
+#define SMU_THROTTLER_TEMP_CORE_BIT33
+#define SMU_THROTTLER_TEMP_MEM_BIT 34
+#define SMU_THROTTLER_TEMP_EDGE_BIT35
+#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36
+#define SMU_THROTTLER_TEMP_VR_GFX_BIT 37
+#define SMU_THROTTLER_TEMP_VR_SOC_BIT 38
+#define SMU_THROTTLER_TEMP_VR_MEM_BIT 39
+#define SMU_THROTTLER_TEMP_LIQUID_BIT 40
+#define SMU_THROTTLER_VRHOT0_BIT 41
+#define SMU_THROTTLER_VRHOT1_BIT 42
+#define SMU_THROTTLER_PROCHOT_CPU_BIT 43
+#define SMU_THROTTLER_PROCHOT_GFX_BIT 44
+
+// Other
+#define SMU_THROTTLER_PPM_BIT 48
+#define SMU_THROTTLER_FIT_BIT 49
+
+#define smu_u64_throttler_bit(dep, INDEP_BIT, DEP_BIT) \
+ ((1ULL & (dep >> DEP_BIT)) << INDEP_BIT)
+
struct smu_hw_power_state {
unsigned int magic;
};
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: attr to control SS2.0 bias level (v2)
add sysfs attr to read/write smartshift bias level.
document smartshift_bias sysfs attr.
V2: add attr to amdgpu_device_attrs and use attr_update (Lijo)
Signed-off-by: Sathishkumar S
Reviewed-by: Lijo Lazar
---
Documentation/gpu/amdgpu.rst| 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 80 +
4 files changed, 92 insertions(+)
diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 6cce26b5621e..364680cdad2e 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -316,3 +316,9 @@ smartshift_dgpu_power
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
:doc: smartshift_dgpu_power
+
+smartshift_bias
+---
+
+.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
+ :doc: smartshift_bias
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ea49d0df7998..8a2df1bbe823 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -211,6 +211,7 @@ extern int amdgpu_discovery;
extern int amdgpu_mes;
extern int amdgpu_noretry;
extern int amdgpu_force_asic_type;
+extern int amdgpu_smartshift_bias;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
extern bool debug_evictions;
@@ -268,6 +269,10 @@ extern int amdgpu_num_kcq;
#define CIK_CURSOR_WIDTH 128
#define CIK_CURSOR_HEIGHT 128
+/* smasrt shift bias level limits */
+#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
+#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
+
struct amdgpu_device;
struct amdgpu_ib;
struct amdgpu_cs_parser;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index cce7e8e31883..5c13bca2944d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -171,6 +171,7 @@ int amdgpu_tmz = -1; /* auto */
uint amdgpu_freesync_vid_mode;
int amdgpu_reset_method = -1; /* auto */
int amdgpu_num_kcq = -1;
+int amdgpu_smartshift_bias;
static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 22cc27935c34..12bdbddc19ef 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1903,6 +1903,67 @@ static ssize_t amdgpu_get_smartshift_dgpu_power(struct
device *dev, struct devic
return r;
}
+/**
+ * DOC: smartshift_bias
+ *
+ * The amdgpu driver provides a sysfs API for reporting the
+ * smartshift(SS2.0) bias level. The value ranges from -100 to 100
+ * and the default is 0. -100 sets maximum preference to APU
+ * and 100 sets max perference to dGPU.
+ */
+
+static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int r = 0;
+
+ r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
+
+ return r;
+}
+
+static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+ int r = 0;
+ int bias = 0;
+
+ if (amdgpu_in_reset(adev))
+ return -EPERM;
+ if (adev->in_suspend && !adev->in_runpm)
+ return -EPERM;
+
+ r = pm_runtime_get_sync(ddev->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(ddev->dev);
+ return r;
+ }
+
+ r = kstrtoint(buf, 10, );
+ if (r)
+ goto out;
+
+ if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
+ bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
+ else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
+ bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
+
+ amdgpu_smartshift_bias = bias;
+ r = count;
+
+ /* TODO: upadte bias level with SMU message */
+
+out:
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return r;
+}
+
+
static int ss_power_attr_update(struct amdgpu_device *adev, struct
amdgpu_device_attr *attr,
uint32_t mask, enum amdgpu_device_attr_states
*states)
{
@@ -1923,6 +1984,23 @@ static int ss_power_attr_update(struct amdgpu_device
*adev, struct amdgpu_device
return 0;
}
+static int ss_bias_attr_update(struct amdgpu_device *adev, struct
amdgpu_device_attr *attr,
+ uint32_t mask, enum amdgpu_device_attr_states
*states)
+{
+ uint32_t ss_power, size;
+
+ if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
+ *states = ATTR_STATE_UNSUPPORTED;
+ else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
+
Re: display regression on Carrizo
[AMD Official Use Only] Hi Mario, Yes, this diff fixes the display on my Carrizo: [root@carrizo linux]# git diff diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index cd864cc83539..ca7739c9f6cb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1044,7 +1044,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc * precision on at least DCN display engines. */ - pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; + pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; if (pipe_ctx->plane_res.xfm != NULL) Tom From: Mario Kleiner Sent: Tuesday, June 1, 2021 09:17 To: StDenis, Tom Cc: amd-gfx list; Deucher, Alexander Subject: Re: display regression on Carrizo On Mon, May 31, 2021 at 4:14 PM StDenis, Tom wrote: > > [AMD Official Use Only] > > Hi Mario, > Hi Tom, > The following commit causes a display regression on my Carrizo when booting > linux into a console (e.g. no WM). When the driver inits the display goes > green and is unusable. The commit prior to this one on amd-staging-drm-next > results in a clean init. > That's sad. What happens if you only revert the change to drivers/gpu/drm/amd/display/dc/core/dc_resource.c in this commit,ie. change the assignment in resource_build_scaling_params() back to: pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; As my testing on Polaris / DCE11.2 showed, for some reason the change in linebuffer pixeldepth was not required for my Polaris11 to get 12bpc output, only for my Raven Ridge / DCN-1. Maybe I could make a followup patch to make it conditional on asic? Either only increase lb depth on DCN-1+, leave it off for DCE, or just exclude DCE-11.0 from the change, as Carrizo is DCE-11? I seem to remember there were some other DCE-11 specific restrictions wrt. 64bpp fp16 and the scaler. Maybe something similar happens here? -mario > commit b1114ddd63be03825182d6162ff25fa3492cd6f5 > Author: Mario Kleiner > Date: Fri Mar 19 22:03:15 2021 +0100 > > drm/amd/display: Increase linebuffer pixel depth to 36bpp. > > Testing with the photometer shows that at least Raven Ridge DCN-1.0 > does not achieve more than 10 bpc effective output precision with a > 16 bpc unorm surface of type SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616, > unless linebuffer depth is increased from LB_PIXEL_DEPTH_30BPP to > LB_PIXEL_DEPTH_36BPP. Otherwise precision gets truncated somewhere > to 10 bpc effective depth. > > Strangely this increase was not needed on Polaris11 DCE-11.2 during > testing to get 12 bpc effective precision. It also is not needed for > fp16 framebuffers. > > Tested on DCN-1.0 and DCE-11.2. > > Signed-off-by: Mario Kleiner > Signed-off-by: Alex Deucher > > drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +-- > drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 6 -- > drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c | 3 ++- > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 3 ++- > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 3 ++- > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +- > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 3 ++- > 8 files changed, 19 insertions(+), 10 deletions(-) > > Tom ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/pm: sysfs attrs to read ss powershare (v6)
add sysfs attrs to read smartshift APU and DGPU power share.
document the sysfs device attributes.
V2: change variable/macro name for stapm power limit (Lijo)
V3: files to be exposed as sysfs device attributes (Alex)
V4: check ret value of sysfs create and remove only if created.
V5: add ss attrs in amdgpu_device_attrs and use attr_update (Lijo)
V6: all checks for ss support to be in if else if statements. (Lijo)
Signed-off-by: Sathishkumar S
Reviewed-by: Lijo Lazar
---
Documentation/gpu/amdgpu.rst | 15 +++
.../gpu/drm/amd/include/kgd_pp_interface.h| 2 +
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 110 ++
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 2 +
4 files changed, 129 insertions(+)
diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 2062a6023678..6cce26b5621e 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -300,4 +300,19 @@ pcie_replay_count
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
:doc: pcie_replay_count
++GPU SmartShift Information
+
+
+GPU SmartShift information via sysfs
+smartshift_apu_power
+
+
+.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
+ :doc: smartshift_apu_power
+
+smartshift_dgpu_power
+-
+
+.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
+ :doc: smartshift_dgpu_power
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index b1cd52a9d684..7bc7492f37b9 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -124,6 +124,8 @@ enum amd_pp_sensors {
AMDGPU_PP_SENSOR_VCE_POWER,
AMDGPU_PP_SENSOR_UVD_POWER,
AMDGPU_PP_SENSOR_GPU_POWER,
+ AMDGPU_PP_SENSOR_SS_APU_SHARE,
+ AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index f48132bc089d..bf9da642622c 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1817,6 +1817,112 @@ static ssize_t amdgpu_get_gpu_metrics(struct device
*dev,
return size;
}
+/**
+ * DOC: smartshift_apu_power
+ *
+ * The amdgpu driver provides a sysfs API for reporting APU power
+ * share if it supports smartshift. The value is expressed as
+ * the proportion of stapm limit where stapm limit is the total APU
+ * power limit. The result is in percentage. If APU power is 130% of
+ * STAPM, then APU is using 30% of the dGPU's headroom.
+ */
+
+static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct
device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+ uint32_t ss_power, size;
+ int r = 0;
+
+ if (amdgpu_in_reset(adev))
+ return -EPERM;
+ if (adev->in_suspend && !adev->in_runpm)
+ return -EPERM;
+
+ r = pm_runtime_get_sync(ddev->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(ddev->dev);
+ return r;
+ }
+
+ r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
+ (void *)_power, );
+ if (r)
+ goto out;
+
+ r = sysfs_emit(buf, "%u%%\n", ss_power);
+
+out:
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+ return r;
+}
+
+/**
+ * DOC: smartshift_dgpu_power
+ *
+ * The amdgpu driver provides a sysfs API for reporting the dGPU power
+ * share if the device is in HG and supports smartshift. The value
+ * is expressed as the proportion of stapm limit where stapm limit
+ * is the total APU power limit. The value is in percentage. If dGPU
+ * power is 20% higher than STAPM power(120%), it's using 20% of the
+ * APU's power headroom.
+ */
+
+static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct
device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+ uint32_t ss_power, size;
+ int r = 0;
+
+ if (amdgpu_in_reset(adev))
+ return -EPERM;
+ if (adev->in_suspend && !adev->in_runpm)
+ return -EPERM;
+
+ r = pm_runtime_get_sync(ddev->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(ddev->dev);
+ return r;
+ }
+
+ r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
+ (void *)_power, );
+
+ if (r)
+ goto out;
+
+ r = sysfs_emit(buf, "%u%%\n", ss_power);
[PATCH] drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime
On SRIOV, driver should only access register through RLC in runtime Signed-off-by: shaoyunl Change-Id: Iecaa52436a2985a18ede9c86cb00cc197a717bd6 --- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index c781808e4dc3..f6cf70e69cce 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -28,12 +28,12 @@ #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \ - ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \ + ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \ adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \ WREG32(reg, value)) #define __RREG32_SOC15_RLC__(reg, flag, hwip) \ - ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \ + ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \ adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \ RREG32(reg)) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdkfd: optimize memory mapping latency
Am 2021-06-01 um 12:05 p.m. schrieb Felix Kuehling:
> Am 2021-05-29 um 6:51 p.m. schrieb Eric Huang:
>> 1. conditionally flush TLBs after map.
>> 2. add heavy weight TLBs flushing after unmap.
>>
>> Signed-off-by: Eric Huang
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 +
>> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 ++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 1 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 2 +-
>> drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 24 +++
>> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++---
>> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
>> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++--
>> 8 files changed, 25 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>> index 2560977760b3..997258c24ef2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>> @@ -85,6 +85,7 @@ struct kgd_mem {
>>
>> bool aql_queue;
>> bool is_imported;
>> +bool table_freed;
>> };
>>
>> /* KFD Memory Eviction */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> index 385c33675227..8ac0d849fd3f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> @@ -1132,6 +1132,8 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
>> return ret;
>> }
>>
>> +mem->table_freed = bo_va->table_freed;
>> +
> I think this should be
>
> mem->table_freed = mem->table_freed || bo_va->table_freed;
>
> That way, on a multi-GPU system, mem->table_freed gets set to true if
> any GPU freed a page table. Then somewhere, this needs to be reset to false.
>
> However, that means, if one GPU frees a page table, all GPUs need to
> flush, which may be unnecessary. A better alternative would be to do the
> TLB flushing right here, only for the affected GPU, instead of returning
> an aggregated "table_freed" all the way back to
> kfd_ioctl_map_memory_to_gpu, which flushes all GPUs.
On second thought, in this function you don't know the PASID to flush,
and you don't know whether to flush a PASID (with HWS) or a VMID
(without HWS). Also, we don't wait here for the mapping to complete, so
this is not the right place to flush.
So you probably do need to return this all the way to
kfd_ioctl_map_memory_to_gpu after all. And the flush has to be after the
amdgpu_amdkfd_gpuvm_sync_memory. So flushing only the affected GPUs is
getting more difficult. If the flush is rare enough, it doesn't matter.
So I'm OK with your proposed solution of flushing all GPUs in
kfd_ioctl_map_memory_to_gpu. Just make sure you OR together the
table_freed flags from all the GPUs, and reset it to false before you
start mapping. Also, you probably don't need to store this permanently
in the kgd_mem structure. Just add an output parameter to
amdgpu_amdkfd_gpuvm_map_memory_to_gpu.
Regards,
Felix
>
> Finally, bo_va->table_freed is only used once, after the
> amdgpu_vm_bo_update call returns. So there is no good reason to store
> this permanently in the bo_va structure. It would be better to just add
> an output parameter to amdgpu_vm_bo_update.
>
> Regards,
> Felix
>
>
>> return amdgpu_sync_fence(sync, bo_va->last_pt_update);
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>> index 36e7f088d4ee..0e0f27f779cd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>> @@ -87,6 +87,7 @@ struct amdgpu_bo_va {
>> boolcleared;
>>
>> boolis_xgmi;
>> +booltable_freed;
>> };
>>
>> struct amdgpu_bo {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 95b94c95adac..ff3eb8395017 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -1885,7 +1885,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
>> struct amdgpu_bo_va *bo_va,
>> resv, mapping->start,
>> mapping->last, update_flags,
>> mapping->offset, mem,
>> -pages_addr, last_update, NULL,
>> +pages_addr, last_update,
>> _va->table_freed,
>> vram_base_offset);
>> if (r)
>> return r;
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
>> index 960913a35ee4..c45ccd1d03c0 100644
>> ---
Re: [PATCH 2/2] drm/amdkfd: optimize memory mapping latency
Am 2021-05-29 um 6:51 p.m. schrieb Eric Huang:
> 1. conditionally flush TLBs after map.
> 2. add heavy weight TLBs flushing after unmap.
>
> Signed-off-by: Eric Huang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 +
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 24 +++
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++---
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++--
> 8 files changed, 25 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 2560977760b3..997258c24ef2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -85,6 +85,7 @@ struct kgd_mem {
>
> bool aql_queue;
> bool is_imported;
> + bool table_freed;
> };
>
> /* KFD Memory Eviction */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 385c33675227..8ac0d849fd3f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1132,6 +1132,8 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
> return ret;
> }
>
> + mem->table_freed = bo_va->table_freed;
> +
I think this should be
mem->table_freed = mem->table_freed || bo_va->table_freed;
That way, on a multi-GPU system, mem->table_freed gets set to true if
any GPU freed a page table. Then somewhere, this needs to be reset to false.
However, that means, if one GPU frees a page table, all GPUs need to
flush, which may be unnecessary. A better alternative would be to do the
TLB flushing right here, only for the affected GPU, instead of returning
an aggregated "table_freed" all the way back to
kfd_ioctl_map_memory_to_gpu, which flushes all GPUs.
Finally, bo_va->table_freed is only used once, after the
amdgpu_vm_bo_update call returns. So there is no good reason to store
this permanently in the bo_va structure. It would be better to just add
an output parameter to amdgpu_vm_bo_update.
Regards,
Felix
> return amdgpu_sync_fence(sync, bo_va->last_pt_update);
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> index 36e7f088d4ee..0e0f27f779cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> @@ -87,6 +87,7 @@ struct amdgpu_bo_va {
> boolcleared;
>
> boolis_xgmi;
> + booltable_freed;
> };
>
> struct amdgpu_bo {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 95b94c95adac..ff3eb8395017 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -1885,7 +1885,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
> struct amdgpu_bo_va *bo_va,
> resv, mapping->start,
> mapping->last, update_flags,
> mapping->offset, mem,
> - pages_addr, last_update, NULL,
> + pages_addr, last_update,
> _va->table_freed,
> vram_base_offset);
> if (r)
> return r;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> index 960913a35ee4..c45ccd1d03c0 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> @@ -1658,16 +1658,18 @@ static int kfd_ioctl_map_memory_to_gpu(struct file
> *filep,
> }
>
> /* Flush TLBs after waiting for the page table updates to complete */
> - for (i = 0; i < args->n_devices; i++) {
> - peer = kfd_device_by_id(devices_arr[i]);
> - if (WARN_ON_ONCE(!peer))
> - continue;
> - peer_pdd = kfd_get_process_device_data(peer, p);
> - if (WARN_ON_ONCE(!peer_pdd))
> - continue;
> - if (!amdgpu_read_lock(peer->ddev, true)) {
> - kfd_flush_tlb(peer_pdd);
> - amdgpu_read_unlock(peer->ddev);
> + if (((struct kgd_mem *)mem)->table_freed) {
> + for (i = 0; i < args->n_devices; i++) {
> + peer = kfd_device_by_id(devices_arr[i]);
> + if (WARN_ON_ONCE(!peer))
> + continue;
> + peer_pdd =
Re: [PATCH v2 2/2] drm/amdgpu: Don't flush HDP on A+A
On 2021-06-01 3:05 a.m., Christian König wrote:
Am 01.06.21 um 02:06 schrieb Eric Huang:
With XGMI connection flushing HDP on PCIe is unnecessary,
it is also to optimize memory allocation latency.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 3 +++
4 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
index 7ec99d591584..1ca23f2f51d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
@@ -44,6 +44,7 @@ struct amdgpu_hdp {
struct ras_common_if *ras_if;
const struct amdgpu_hdp_funcs *funcs;
const struct amdgpu_hdp_ras_funcs *ras_funcs;
+ bool no_flush;
};
int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index aaa2574ce9bc..f31eae2931f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -226,7 +226,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring,
unsigned num_ibs,
if (!(adev->flags & AMD_IS_APU))
#endif
{
- if (ring->funcs->emit_hdp_flush)
+ if (ring->funcs->emit_hdp_flush &&
+ !adev->hdp.no_flush)
This still emits the flush through MMIO.
As matter of fact, it doesn't, because amdgpu_asic_flush_hdp will check
the flag again in hdp_v4_0.c. I even think the check here is unnecessary
for previous asic, because asic other than Aldeberan A+A has to flush
tlbs according to hardware specific.
What you need to do is to initialize the hdp.no_flush field for all
asics and architectures and then use that here in the if above this one.
I don't understand why it should be for all asics. Currently only
Aldeberan A+A need no TLB flush, we don't have to consider other asics.
And hdp.no_flush is a common flag for all asics, Is there an issue in
other asics for this flag on tlb flush?
amdgpu_ring_emit_hdp_flush(ring);
else
amdgpu_asic_flush_hdp(adev, ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 2749621d5f63..6e1eab615914 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1223,6 +1223,7 @@ static int gmc_v9_0_early_init(void *handle)
adev->gmc.xgmi.supported = true;
adev->gmc.xgmi.connected_to_cpu =
adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
+ adev->hdp.no_flush = adev->gmc.xgmi.connected_to_cpu;
}
gmc_v9_0_set_gmc_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index 74b90cc2bf48..e1b2face8656 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -40,6 +40,9 @@
static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
struct amdgpu_ring *ring)
{
+ if (adev->hdp.no_flush)
+ return;
+
Just to be clear once more, this approach is a NAK.
Checks like this should not be in the hardware specific function.
As I mention above, TLB flush should be specific for Asic for my opinion.
Regards,
Eric
Regards,
Christian.
if (!ring || !ring->funcs->emit_wreg)
WREG32_NO_KIQ((adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
else
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[PATCH] drm/amdgpu: bump driver version
For 16bpc display support. Signed-off-by: Alex Deucher Cc: Mario Kleiner --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index c21710d72afc..f576426e24fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -95,9 +95,10 @@ * - 3.39.0 - DMABUF implicit sync does a full pipeline sync * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ * - 3.41.0 - Add video codec query + * - 3.42.0 - Add 16bpc fixed point display support */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 41 +#define KMS_DRIVER_MINOR 42 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit; -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: 5.13-rc3 Renoir (ChipID = 0x1636): error GPU reset, fences timed out, failed to initialize parser -125
On Mon, May 31, 2021 at 4:17 AM Julian Wollrath wrote:
>
> Hello,
>
> on 5.13-rc3 with a 4650U (Renoir, ChipID = 0x1636) I am able to
> reliably get the GPU to reset under X11/Xorg with the amdgpu driver
> (current from git) and having persistent problems afterwards. I
> achieve this in the following way (using ROOT (root.cern.ch) to draw a
> histogram):
>
> $ root
> # TH1 *t = new TH1I("test", "test", 2, -.5, 1.5)
> # t->Fill(1)
> # t->Draw()
>
>
> this opens a window showing the histogram and results in
>
> kernel: [ 370.709485] [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR*
> Waiting for fences timed out!
> kernel: [ 375.820701] [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR*
> Waiting for fences timed out!
> kernel: [ 375.830689] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx
> timeout, signaled seq=3783, emitted seq=3785
> kernel: [ 375.831015] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process
> information: process Xorg pid 1028 thread Xorg
> :cs0 pid 1029
> kernel: [ 375.831174] amdgpu :03:00.0: amdgpu: GPU reset begin!
> kernel: [ 375.924610] [drm] free PSP TMR buffer
> kernel: [ 375.951409] amdgpu :03:00.0: amdgpu: MODE2 reset
> kernel: [ 375.951531] amdgpu :03:00.0: amdgpu: GPU reset succeeded,
> trying to resume
> kernel: [ 375.951712] [drm] PCIE GART of 1024M enabled.
> kernel: [ 375.951715] [drm] PTB located at 0x00F40090
> kernel: [ 375.951957] [drm] PSP is resuming...
> kernel: [ 375.971811] [drm] reserve 0x40 from 0xf41f80 for PSP TMR
> kernel: [ 376.277979] amdgpu :03:00.0: amdgpu: RAS: optional ras ta
> ucode is not available
> kernel: [ 376.288823] amdgpu :03:00.0: amdgpu: RAP: optional rap ta
> ucode is not available
> kernel: [ 376.288830] amdgpu :03:00.0: amdgpu: SECUREDISPLAY:
> securedisplay ta ucode is not available
> kernel: [ 376.288836] amdgpu :03:00.0: amdgpu: SMU is resuming...
> kernel: [ 376.290539] amdgpu :03:00.0: amdgpu: SMU is resumed
> successfully!
> kernel: [ 376.648574] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to
> initialize parser -125!
> kernel: [ 376.649562] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to
> initialize parser -125!
> kernel: [ 376.721210] [drm] kiq ring mec 2 pipe 1 q 0
> kernel: [ 376.722457] [drm] DMUB hardware initialized: version=0x01020008
> kernel: [ 376.936133] [drm] VCN decode and encode initialized
> successfully(under DPG Mode).
> kernel: [ 376.936628] [drm] JPEG decode initialized successfully.
> kernel: [ 376.936635] amdgpu :03:00.0: amdgpu: ring gfx uses VM inv eng
> 0 on hub 0
> kernel: [ 376.936639] amdgpu :03:00.0: amdgpu: ring comp_1.0.0 uses VM
> inv eng 1 on hub 0
> kernel: [ 376.936641] amdgpu :03:00.0: amdgpu: ring comp_1.1.0 uses VM
> inv eng 4 on hub 0
> kernel: [ 376.936643] amdgpu :03:00.0: amdgpu: ring comp_1.2.0 uses VM
> inv eng 5 on hub 0
> kernel: [ 376.936645] amdgpu :03:00.0: amdgpu: ring comp_1.3.0 uses VM
> inv eng 6 on hub 0
> kernel: [ 376.936646] amdgpu :03:00.0: amdgpu: ring comp_1.0.1 uses VM
> inv eng 7 on hub 0
> kernel: [ 376.936648] amdgpu :03:00.0: amdgpu: ring comp_1.1.1 uses VM
> inv eng 8 on hub 0
> kernel: [ 376.936649] amdgpu :03:00.0: amdgpu: ring comp_1.2.1 uses VM
> inv eng 9 on hub 0
> kernel: [ 376.936650] amdgpu :03:00.0: amdgpu: ring comp_1.3.1 uses VM
> inv eng 10 on hub 0
> kernel: [ 376.936652] amdgpu :03:00.0: amdgpu: ring kiq_2.1.0 uses VM
> inv eng 11 on hub 0
> kernel: [ 376.936654] amdgpu :03:00.0: amdgpu: ring sdma0 uses VM inv
> eng 0 on hub 1
> kernel: [ 376.936656] amdgpu :03:00.0: amdgpu: ring vcn_dec uses VM inv
> eng 1 on hub 1
> kernel: [ 376.936657] amdgpu :03:00.0: amdgpu: ring vcn_enc0 uses VM inv
> eng 4 on hub 1
> kernel: [ 376.936659] amdgpu :03:00.0: amdgpu: ring vcn_enc1 uses VM inv
> eng 5 on hub 1
> kernel: [ 376.936660] amdgpu :03:00.0: amdgpu: ring jpeg_dec uses VM inv
> eng 6 on hub 1
> kernel: [ 376.945068] amdgpu :03:00.0: amdgpu: recover vram bo from
> shadow start
> kernel: [ 376.945075] amdgpu :03:00.0: amdgpu: recover vram bo from
> shadow done
> kernel: [ 376.945081] [drm] Skip scheduling IBs!
> kernel: [ 376.945084] [drm] Skip scheduling IBs!
> kernel: [ 376.945119] amdgpu :03:00.0: amdgpu: GPU reset(2) succeeded!
The GPU reset was successful. You'll need to restart your GUI
environment. Unfortunately no current desktop environments on Linux
properly handle lost contexts.
Alex
> kernel: [ 376.945161] [drm] Skip scheduling IBs!
> kernel: [ 376.945169] [drm] Skip scheduling IBs!
> kernel: [ 376.945172] [drm] Skip scheduling IBs!
> kernel: [ 376.945235] [drm] Skip scheduling IBs!
> kernel: [ 376.945243] [drm] Skip scheduling IBs!
> kernel: [ 376.945246] [drm] Skip scheduling IBs!
> kernel: [ 376.945248] [drm] Skip scheduling IBs!
> kernel: [ 376.945251] [drm] Skip scheduling IBs!
> kernel: [ 376.945253] [drm] Skip scheduling IBs!
>
[PATCH -next] drm/amdgpu: Remove unneeded semicolon
Remove unneeded semicolon. Signed-off-by: Zheng Yongjun --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index 65b1dca4b02e..148f6c3343ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -227,7 +227,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) break; default: break; - }; + } } /* Reinit NBIF block */ -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/1] drm/amd/display: fix coding style
Am 01.06.21 um 12:13 schrieb Nirmoy Das:
Fixes: 60d198ca66ecf778 ("drm/amd/display: WARN_ON cleanups")
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
Hi Alex,
Can you please squash this with the "Fixes" patch?
We could keep that separated as well, no big deal.
Christian.
Thanks,
Nirmoy
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 09bbec4dab7c..56abc27b78f7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -315,9 +315,8 @@ get_crtc_by_otg_inst(struct amdgpu_device *adev,
struct drm_crtc *crtc;
struct amdgpu_crtc *amdgpu_crtc;
- if (WARN_ON(otg_inst == -1)) {
+ if (WARN_ON(otg_inst == -1))
return adev->mode_info.crtcs[0];
- }
list_for_each_entry(crtc, >mode_config.crtc_list, head) {
amdgpu_crtc = to_amdgpu_crtc(crtc);
--
2.31.1
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[PATCH 1/1] drm/amd/display: fix coding style
Fixes: 60d198ca66ecf778 ("drm/amd/display: WARN_ON cleanups")
Signed-off-by: Nirmoy Das
---
Hi Alex,
Can you please squash this with the "Fixes" patch?
Thanks,
Nirmoy
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 09bbec4dab7c..56abc27b78f7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -315,9 +315,8 @@ get_crtc_by_otg_inst(struct amdgpu_device *adev,
struct drm_crtc *crtc;
struct amdgpu_crtc *amdgpu_crtc;
- if (WARN_ON(otg_inst == -1)) {
+ if (WARN_ON(otg_inst == -1))
return adev->mode_info.crtcs[0];
- }
list_for_each_entry(crtc, >mode_config.crtc_list, head) {
amdgpu_crtc = to_amdgpu_crtc(crtc);
--
2.31.1
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Re: [PATCH] drm/amdgpu: bump driver version
On Tue, Jun 1, 2021 at 4:00 PM Alex Deucher wrote: > > For 16bpc display support. > > Signed-off-by: Alex Deucher > Cc: Mario Kleiner > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > index c21710d72afc..f576426e24fc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -95,9 +95,10 @@ > * - 3.39.0 - DMABUF implicit sync does a full pipeline sync > * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ > * - 3.41.0 - Add video codec query > + * - 3.42.0 - Add 16bpc fixed point display support > */ > #define KMS_DRIVER_MAJOR 3 > -#define KMS_DRIVER_MINOR 41 > +#define KMS_DRIVER_MINOR 42 > #define KMS_DRIVER_PATCHLEVEL 0 > > int amdgpu_vram_limit; > -- > 2.31.1 > Reviewed-by: Mario Kleiner Thanks Alex. -mario ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: display regression on Carrizo
On Mon, May 31, 2021 at 4:14 PM StDenis, Tom wrote: > > [AMD Official Use Only] > > Hi Mario, > Hi Tom, > The following commit causes a display regression on my Carrizo when booting > linux into a console (e.g. no WM). When the driver inits the display goes > green and is unusable. The commit prior to this one on amd-staging-drm-next > results in a clean init. > That's sad. What happens if you only revert the change to drivers/gpu/drm/amd/display/dc/core/dc_resource.c in this commit,ie. change the assignment in resource_build_scaling_params() back to: pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; As my testing on Polaris / DCE11.2 showed, for some reason the change in linebuffer pixeldepth was not required for my Polaris11 to get 12bpc output, only for my Raven Ridge / DCN-1. Maybe I could make a followup patch to make it conditional on asic? Either only increase lb depth on DCN-1+, leave it off for DCE, or just exclude DCE-11.0 from the change, as Carrizo is DCE-11? I seem to remember there were some other DCE-11 specific restrictions wrt. 64bpp fp16 and the scaler. Maybe something similar happens here? -mario > commit b1114ddd63be03825182d6162ff25fa3492cd6f5 > Author: Mario Kleiner > Date: Fri Mar 19 22:03:15 2021 +0100 > > drm/amd/display: Increase linebuffer pixel depth to 36bpp. > > Testing with the photometer shows that at least Raven Ridge DCN-1.0 > does not achieve more than 10 bpc effective output precision with a > 16 bpc unorm surface of type SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616, > unless linebuffer depth is increased from LB_PIXEL_DEPTH_30BPP to > LB_PIXEL_DEPTH_36BPP. Otherwise precision gets truncated somewhere > to 10 bpc effective depth. > > Strangely this increase was not needed on Polaris11 DCE-11.2 during > testing to get 12 bpc effective precision. It also is not needed for > fp16 framebuffers. > > Tested on DCN-1.0 and DCE-11.2. > > Signed-off-by: Mario Kleiner > Signed-off-by: Alex Deucher > > drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +-- > drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 6 -- > drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c | 3 ++- > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 3 ++- > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 3 ++- > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +- > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 3 ++- > 8 files changed, 19 insertions(+), 10 deletions(-) > > Tom ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH -next] drm/amd/display: fix warning: ‘update_dsc_caps’ and ‘apply_dsc_policy_for_stream’ defined but not used
Fixes gcc '-Wunused-function' warning:
‘update_dsc_caps’ and ‘apply_dsc_policy_for_stream’ are only used
if 'CONFIG_DRM_AMD_DC_DCN' is defined,
however, it's defined even if 'CONFIG_DRM_AMD_DC_DCN' is not defined.
Thus gcc will report following warning
if 'CONFIG_DRM_AMD_DC_DCN' is not defined:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5572:13: warning:
‘apply_dsc_policy_for_stream’ defined but not used [-Wunused-function]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5556:13: warning:
‘update_dsc_caps’ defined but not used [-Wunused-function]
Thus move the definition of ‘update_dsc_caps’ and
‘apply_dsc_policy_for_stream’ inside define macro to fix it.
Signed-off-by: Baokun Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f0adfda32213..e0af394103aa 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5553,6 +5553,7 @@ static void dm_enable_per_frame_crtc_master_sync(struct
dc_state *context)
}
}
+#if defined(CONFIG_DRM_AMD_DC_DCN)
static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
struct dc_sink *sink,
struct dc_stream_state *stream,
struct
dsc_dec_dpcd_caps *dsc_caps)
@@ -5560,12 +5561,10 @@ static void update_dsc_caps(struct amdgpu_dm_connector
*aconnector,
stream->timing.flags.DSC = 0;
if (aconnector->dc_link && sink->sink_signal ==
SIGNAL_TYPE_DISPLAY_PORT) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
dsc_caps);
-#endif
}
}
@@ -5578,7 +5577,6 @@ static void apply_dsc_policy_for_stream(struct
amdgpu_dm_connector *aconnector,
link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
dc_link_get_link_cap(aconnector->dc_link));
-#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Set DSC policy according to dsc_clock_en */
dc_dsc_policy_set_enable_dsc_when_not_needed(
aconnector->dsc_settings.dsc_force_enable ==
DSC_CLK_FORCE_ENABLE);
@@ -5609,8 +5607,8 @@ static void apply_dsc_policy_for_stream(struct
amdgpu_dm_connector *aconnector,
if (stream->timing.flags.DSC &&
aconnector->dsc_settings.dsc_bits_per_pixel)
stream->timing.dsc_cfg.bits_per_pixel =
aconnector->dsc_settings.dsc_bits_per_pixel;
-#endif
}
+#endif
static struct drm_display_mode *
get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
--
2.31.1
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RE: [PATCH] drm/amdgpu: enable smart shift on dGPU (v5)
[AMD Official Use Only]
Acked-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> Sathishkumar S
> Sent: Sunday, May 30, 2021 5:19 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Sundararaju,
> Sathishkumar ; Sharma, Shashank
>
> Subject: [PATCH] drm/amdgpu: enable smart shift on dGPU (v5)
>
> enable smart shift on dGPU if it is part of HG system and the platform
> supports ATCS method to handle power shift.
>
> V2: avoid psc updates in baco enter and exit (Lijo)
> fix alignment (Shashank)
> V3: rebased on unified ATCS handling. (Alex)
> V4: check for return value and warn on failed update (Shashank)
> return 0 if device does not support smart shift. (Lizo)
> V5: rebased on ATPX/ATCS structures global (Alex)
>
> Signed-off-by: Sathishkumar S
> Reviewed-by: Lijo Lazar
> Reviewed-by: Shashank Sharma
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 18
> drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 49
> ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 6 +++
> 4 files changed, 97 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 0ea2ed3a55f1..827533a543c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -130,6 +130,13 @@ struct amdgpu_mgpu_info
> boolpending_reset;
> };
>
> +enum amdgpu_ss {
> + AMDGPU_SS_DRV_LOAD,
> + AMDGPU_SS_DEV_D0,
> + AMDGPU_SS_DEV_D3,
> + AMDGPU_SS_DRV_UNLOAD
> +};
> +
> struct amdgpu_watchdog_timer
> {
> bool timeout_fatal_disable;
> @@ -1267,6 +1274,7 @@ int amdgpu_device_mode1_reset(struct
> amdgpu_device *adev); bool amdgpu_device_supports_atpx(struct
> drm_device *dev); bool amdgpu_device_supports_px(struct drm_device
> *dev); bool amdgpu_device_supports_boco(struct drm_device *dev);
> +bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
> bool amdgpu_device_supports_baco(struct drm_device *dev); bool
> amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
> struct amdgpu_device *peer_adev); @@ -
> 1339,6 +1347,13 @@ struct amdgpu_afmt_acr { struct amdgpu_afmt_acr
> amdgpu_afmt_acr(uint32_t clock);
>
> /* amdgpu_acpi.c */
> +
> +/* ATCS Device/Driver State */
> +#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
> +#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
> +#define AMDGPU_ATCS_PSC_DRV_STATE_OPR0
> +#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR1
> +
> #if defined(CONFIG_ACPI)
> int amdgpu_acpi_init(struct amdgpu_device *adev); void
> amdgpu_acpi_fini(struct amdgpu_device *adev); @@ -1348,6 +1363,7 @@
> int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
> u8 perf_req, bool advertise);
> int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
> u8 dev_state, bool drv_state);
> +int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum
> +amdgpu_ss ss_state);
> int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
>
> void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps
> *caps); @@ -1361,6 +1377,8 @@ static inline void amdgpu_acpi_detect(void)
> { } static inline bool amdgpu_acpi_is_power_shift_control_supported(void)
> { return false; } static inline int amdgpu_acpi_power_shift_control(struct
> amdgpu_device *adev,
> u8 dev_state, bool drv_state)
> { return 0; }
> +static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
> + enum amdgpu_ss ss_state)
> { return 0; }
> #endif
>
> int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index b631316bfe5b..84a1b4bc9bb4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -754,6 +754,55 @@ int amdgpu_acpi_power_shift_control(struct
> amdgpu_device *adev,
> return 0;
> }
>
> +/**
> + * amdgpu_acpi_smart_shift_update - update dGPU device state to SBIOS
> + *
> + * @dev: drm_device pointer
> + * @ss_state: current smart shift event
> + *
> + * returns 0 on success,
> + * otherwise return error number.
> + */
> +int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum
> +amdgpu_ss ss_state) {
> + struct amdgpu_device *adev = drm_to_adev(dev);
> + int r;
> +
> + if (!amdgpu_device_supports_smart_shift(dev))
> + return 0;
> +
> + switch (ss_state) {
> + /* SBIOS trigger "stop", "enable" and "start" at D0, Driver Operational.
> + * SBIOS trigger "stop" at D3, Driver Not Operational.
> + * SBIOS trigger "stop" and "disable" at D0, Driver NOT operational.
>
RE: [PATCH 6/6] amdgpu/pm: add kernel documentation for smu_get_power_limit
[AMD Official Use Only]
Series is reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> Darren Powell
> Sent: Saturday, May 29, 2021 7:06 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Powell, Darren
> Subject: [PATCH 6/6] amdgpu/pm: add kernel documentation for
> smu_get_power_limit
>
> added doc tag "amdgpu_pp_power" with description
> added tags for enums pp_power_limit_level, pp_power_sample_window
> added tag for function smu_get_power_limit
>
> Test:
> * Temporary insertion into Documentation/gpu/amdgpu.rst
> START
> Power Limit
> ---
> .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h
>:doc: amdgpu_pp_power
>
> .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h
>:identifiers: pp_power_limit_level
>
> .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h
>:identifiers: pp_power_sample_window
>
> .. kernel-doc:: drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>:identifiers: smu_get_power_limit
> -END-
>
> Signed-off-by: Darren Powell
> ---
> .../gpu/drm/amd/include/kgd_pp_interface.h| 30
> ++-
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 +++
> 2 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 369a72f03e92..46d2fc434e24 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -192,6 +192,26 @@ enum pp_df_cstate {
> DF_CSTATE_ALLOW,
> };
>
> +/**
> + * DOC: amdgpu_pp_power
> + *
> + * APU power is managed to system-level requirements through the PPT
> + * (package power tracking) feature. PPT is intended to limit power to the
> + * requirements of the power source and could be dynamically updated to
> + * maximize APU performance within the system power budget.
> + *
> + * Two windows of power measurement can be requested, where
> supported, with
> + * :c:type:`enum pp_power_sample_window
> `.
> + */
> +
> +/**
> + * enum pp_power_limit_level - Used to query the power limits
> + *
> + * @PP_PWR_LIMIT_MIN: Minimum Power Limit
> + * @PP_PWR_LIMIT_CURRENT: Current Power Limit
> + * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
> + * @PP_PWR_LIMIT_MAX: Maximum Power Limit
> + */
> enum pp_power_limit_level
> {
> PP_PWR_LIMIT_MIN = -1,
> @@ -200,7 +220,15 @@ enum pp_power_limit_level
> PP_PWR_LIMIT_MAX,
> };
>
> - enum pp_power_sample_window
> +/**
> + * enum pp_power_sample_window - Used to specify the window size of
> the requested power
> + *
> + * @PP_PWR_WINDOW_DEFAULT: manages the configurable, thermally
> significant
> + * moving average of APU power (default ~5000 ms).
> + * @PP_PWR_WINDOW_FAST: manages the ~10 ms moving average of
> APU power,
> + * where supported.
> + */
> +enum pp_power_sample_window
> {
> PP_PWR_WINDOW_DEFAULT,
> PP_PWR_WINDOW_FAST,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 5671abd58bcf..b7a9037a2dbc 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2166,6 +2166,16 @@ static int smu_set_fan_speed_rpm(void *handle,
> uint32_t speed)
> return ret;
> }
>
> +/**
> + * smu_get_power_limit - Request one of the SMU Power Limits
> + *
> + * @handle: pointer to smu context
> + * @limit: requested limit is written back to this variable
> + * @pp_limit_level: _power_limit_level which power limit to return
> + * @sample_window: _power_sample_window measurement window
> + * Return: 0 on success, <0 on error
> + *
> + */
> int smu_get_power_limit(void *handle,
> uint32_t *limit,
> enum pp_power_limit_level pp_limit_level,
> --
> 2.25.1
>
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RE: [PATCH] drm/amdgpu: optimize code about format string in gfx_v10_0_init_microcode()
[Public]
Reviewed-by: Lijo Lazar
-Original Message-
From: amd-gfx On Behalf Of Kevin Wang
Sent: Monday, May 31, 2021 2:34 PM
To: amd-gfx@lists.freedesktop.org
Cc: Yin, Tianci (Rico) ; Wang, Kevin(Yang)
Subject: [PATCH] drm/amdgpu: optimize code about format string in
gfx_v10_0_init_microcode()
the memset() and snprintf() is not necessary.
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 80729ea8416a..11a64ca8a5ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3935,7 +3935,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device
*adev) {
const char *chip_name;
char fw_name[40];
- char wks[10];
+ char *wks = "";
int err;
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL; @@ -3948,7 +3948,6
@@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n");
- memset(wks, 0, sizeof(wks));
switch (adev->asic_type) {
case CHIP_NAVI10:
chip_name = "navi10";
@@ -3957,7 +3956,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device
*adev)
chip_name = "navi14";
if (!(adev->pdev->device == 0x7340 &&
adev->pdev->revision != 0x00))
- snprintf(wks, sizeof(wks), "_wks");
+ wks = "_wks";
break;
case CHIP_NAVI12:
chip_name = "navi12";
--
2.17.1
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RE: [PATCH] drm/amd/display: Fix uninitialized field when expanding macro MI_DCE12_MASK_SH_LIST
[AMD Public Use]
CC "Jones Lee" as the author of original patch.
Below patch is:
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Shi, Leslie
Sent: Tuesday, June 1, 2021 11:18 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Chen, Guchun
Subject: [PATCH] drm/amd/display: Fix uninitialized field when expanding macro
MI_DCE12_MASK_SH_LIST
This is caused by 63213103 "drm/amd/display/dc/dce/dce_mem_input: Remove
duplicate initialisation of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT, MASK}"
Signed-off-by: Leslie Shi
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 08a4c8d029d9..f98400efdd9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -297,6 +297,7 @@ struct dce_mem_input_registers {
MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
#define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\
+ SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\
--
2.25.1
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RE: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signature
[Public]
May be just call it power_limit or power_cap similar to hwmon. The various
limits correspond to hwmon power[1-*]_cap and levels correspond to min/ max etc.
Thanks,
Lijo
From: Powell, Darren
Sent: Tuesday, June 1, 2021 4:50 AM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function
signature
[Public]
>< > The limits are not limited to sample window. There are limits like APU
>only limit, platform limit and totally obscure ones like PPT0/PPT1 etc.
>It's better that the new enum takes care of those as well in case there is a
>need to make them available through sysfs.
I think you mean something more like this?
+ enum pp_power_constraints
+{
+ PP_PWR_CONSTRAINT_DEFAULT,
+ PP_PWR_CONSTRAINT_FASTWINDOW,
+};
+
From: Lazar, Lijo mailto:lijo.la...@amd.com>>
Sent: Monday, May 31, 2021 2:04 AM
To: Powell, Darren mailto:darren.pow...@amd.com>>;
amd-gfx@lists.freedesktop.org
mailto:amd-gfx@lists.freedesktop.org>>
Subject: RE: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function
signature
[Public]
-Original Message-
From: Powell, Darren mailto:darren.pow...@amd.com>>
Sent: Saturday, May 29, 2021 4:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Powell, Darren mailto:darren.pow...@amd.com>>
Subject: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signature
add two new powerplay enums (limit_level, sample_window) add enums to
smu_get_power_limit signature remove input bitfield stuffing of output
variable limit update calls to smu_get_power_limit
* Test
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f
10` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
lspci -nn | grep "VGA\|Display" ; \
echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \
echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \
echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default
Signed-off-by: Darren Powell
mailto:darren.pow...@amd.com>>
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 14
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 18 +-
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 3 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 +--
4 files changed, 57 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index b1cd52a9d684..ddbf802ea8ad 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -192,6 +192,20 @@ enum pp_df_cstate {
DF_CSTATE_ALLOW,
};
+enum pp_power_limit_level
+{
+ PP_PWR_LIMIT_MIN = -1,
+ PP_PWR_LIMIT_CURRENT,
+ PP_PWR_LIMIT_DEFAULT,
+ PP_PWR_LIMIT_MAX,
+};
+
+ enum pp_power_sample_window
+{
+ PP_PWR_WINDOW_DEFAULT,
+ PP_PWR_WINDOW_FAST,
+};
+
< > The limits are not limited to sample window. There are limits like APU only
limit, platform limit and totally obscure ones like PPT0/PPT1 etc.
It's better that the new enum takes care of those as well in case there is a
need to make them available through sysfs.
Thanks,
Lijo
#define PP_GROUP_MASK0xF000
#define PP_GROUP_SHIFT 28
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 13da377888d2..f7b45803431d 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2717,8 +2717,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct
device *dev, {
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- int limit_type = to_sensor_dev_attr(attr)->index;
- uint32_t limit = limit_type << 24;
+ enum pp_power_sample_window sample_window =
to_sensor_dev_attr(attr)->index;
+ uint32_t limit;
uint32_t max_limit = 0;
ssize_t size;
int r;
@@ -2735,7 +2735,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct
device *dev,
}
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(>smu, , SMU_PPT_LIMIT_MAX);
+ smu_get_power_limit(>smu, , PP_PWR_LIMIT_MAX,
+sample_window);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 100);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle,
@@ -2757,8 +2757,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device
*dev, {
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- int limit_type = to_sensor_dev_attr(attr)->index;
- uint32_t limit = limit_type << 24;
+
[PATCH] drm/amd/display: Remove the redundant initialization of local variable
Local variable 'i' and 'j' will be initialized in the for loop, so
remove the redundant initialization.
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Signed-off-by: Shaokun Zhang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 4713f09bcbf1..e4f2a2d3a819 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -304,7 +304,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
struct dc_stream_state *stream,
struct dc_crtc_timing_adjust *adjust)
{
- int i = 0;
+ int i;
bool ret = false;
stream->adjust.v_total_max = adjust->v_total_max;
@@ -332,7 +332,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
{
/* TODO: Support multiple streams */
const struct dc_stream_state *stream = streams[0];
- int i = 0;
+ int i;
bool ret = false;
struct crtc_position position;
@@ -539,7 +539,7 @@ void dc_stream_set_dyn_expansion(struct dc *dc, struct
dc_stream_state *stream,
enum dc_dynamic_expansion option)
{
/* OPP FMT dyn expansion updates*/
- int i = 0;
+ int i;
struct pipe_ctx *pipe_ctx;
for (i = 0; i < MAX_PIPES; i++) {
@@ -597,7 +597,7 @@ void dc_stream_set_dither_option(struct dc_stream_state
*stream,
bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state
*stream)
{
- int i = 0;
+ int i;
bool ret = false;
struct pipe_ctx *pipes;
@@ -614,7 +614,7 @@ bool dc_stream_set_gamut_remap(struct dc *dc, const struct
dc_stream_state *stre
bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state
*stream)
{
- int i = 0;
+ int i;
bool ret = false;
struct pipe_ctx *pipes;
@@ -640,8 +640,7 @@ void dc_stream_set_static_screen_params(struct dc *dc,
int num_streams,
const struct dc_static_screen_params *params)
{
- int i = 0;
- int j = 0;
+ int i, j;
struct pipe_ctx *pipes_affected[MAX_PIPES];
int num_pipes_affected = 0;
@@ -896,7 +895,7 @@ static void disable_all_writeback_pipes_for_stream(
static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state
*context,
struct dc_stream_state *stream, bool
lock)
{
- int i = 0;
+ int i;
/* Checks if interdependent update function pointer is NULL or not,
takes care of DCE110 case */
if (dc->hwss.interdependent_update_lock)
@@ -1156,7 +1155,7 @@ static void enable_timing_multisync(
struct dc *dc,
struct dc_state *ctx)
{
- int i = 0, multisync_count = 0;
+ int i, multisync_count = 0;
int pipe_count = dc->res_pool->pipe_count;
struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
--
2.7.4
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Re: AMDGPU error: "[drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR* Waiting for fences timed out!"
Hi, I'm using the Ryzen 3200G and its iGPU, on a kernel with that patch applied[0] and the latest linux-firmware (20210511.7685cf4-1) I'm still getting this hang. [0] https://git.archlinux.org/linux.git/log/?h=v5.12.8-arch1 hang5 Description: Binary data ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
回复: [PATCH] drm/amdgpu: fix sdma firmware version error in sriov
[AMD Official Use Only]
Reviewed-by: Stanley.Yang
Regards,
Stanley
> -邮件原件-
> 发件人: Wang, Kevin(Yang)
> 发送时间: Monday, May 31, 2021 5:33 PM
> 收件人: amd-gfx@lists.freedesktop.org
> 抄送: frank@amd.ccom; Yang, Stanley ; Wang,
> Kevin(Yang)
> 主题: [PATCH] drm/amdgpu: fix sdma firmware version error in sriov
>
> Re-adjust the function return order to avoid empty sdma version in the sriov
> environment. (read amdgpu_firmware_info)
>
> Signed-off-by: Kevin Wang
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index deb907f96090..98059bce692f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -147,9 +147,6 @@ static int sdma_v5_2_init_microcode(struct
> amdgpu_device *adev)
> struct amdgpu_firmware_info *info = NULL;
> const struct common_firmware_header *header = NULL;
>
> - if (amdgpu_sriov_vf(adev) && (adev->asic_type ==
> CHIP_SIENNA_CICHLID))
> - return 0;
> -
> DRM_DEBUG("\n");
>
> switch (adev->asic_type) {
> @@ -187,6 +184,9 @@ static int sdma_v5_2_init_microcode(struct
> amdgpu_device *adev)
> (void *)>sdma.instance[0],
> sizeof(struct amdgpu_sdma_instance));
>
> + if (amdgpu_sriov_vf(adev) && (adev->asic_type ==
> CHIP_SIENNA_CICHLID))
> + return 0;
> +
> DRM_DEBUG("psp_load == '%s'\n",
> adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ?
> "true" : "false");
>
> --
> 2.17.1
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[PATCH] drm/amd/display: Fix uninitialized field when expanding macro MI_DCE12_MASK_SH_LIST
This is caused by 63213103 "drm/amd/display/dc/dce/dce_mem_input: Remove
duplicate initialisation of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT, MASK}"
Signed-off-by: Leslie Shi
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 08a4c8d029d9..f98400efdd9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -297,6 +297,7 @@ struct dce_mem_input_registers {
MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
#define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\
+ SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\
--
2.25.1
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Re: [PATCH v2 2/2] drm/amdgpu: Don't flush HDP on A+A
Am 01.06.21 um 02:06 schrieb Eric Huang:
With XGMI connection flushing HDP on PCIe is unnecessary,
it is also to optimize memory allocation latency.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 3 +++
4 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
index 7ec99d591584..1ca23f2f51d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
@@ -44,6 +44,7 @@ struct amdgpu_hdp {
struct ras_common_if*ras_if;
const struct amdgpu_hdp_funcs *funcs;
const struct amdgpu_hdp_ras_funcs *ras_funcs;
+ boolno_flush;
};
int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index aaa2574ce9bc..f31eae2931f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -226,7 +226,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
if (!(adev->flags & AMD_IS_APU))
#endif
{
- if (ring->funcs->emit_hdp_flush)
+ if (ring->funcs->emit_hdp_flush &&
+ !adev->hdp.no_flush)
This still emits the flush through MMIO.
What you need to do is to initialize the hdp.no_flush field for all
asics and architectures and then use that here in the if above this one.
amdgpu_ring_emit_hdp_flush(ring);
else
amdgpu_asic_flush_hdp(adev, ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 2749621d5f63..6e1eab615914 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1223,6 +1223,7 @@ static int gmc_v9_0_early_init(void *handle)
adev->gmc.xgmi.supported = true;
adev->gmc.xgmi.connected_to_cpu =
adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
+ adev->hdp.no_flush = adev->gmc.xgmi.connected_to_cpu;
}
gmc_v9_0_set_gmc_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index 74b90cc2bf48..e1b2face8656 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -40,6 +40,9 @@
static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
struct amdgpu_ring *ring)
{
+ if (adev->hdp.no_flush)
+ return;
+
Just to be clear once more, this approach is a NAK.
Checks like this should not be in the hardware specific function.
Regards,
Christian.
if (!ring || !ring->funcs->emit_wreg)
WREG32_NO_KIQ((adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
else
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Re: [PATCH v2 1/2] drm/amdgpu: Fix a bug on flag table_freed
Am 01.06.21 um 02:06 schrieb Eric Huang:
table_freed will be always true when mapping a memory with size
bigger than 2MB. The problem is page table's entries are always
existed, but existing mapping depends on page talbe's bo, so
using a check of page table's bo existed will resolve the issue.
Signed-off-by: Eric Huang
Reviewed-by: Christian König for this one.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 539c117906cc..2c20bba7dc1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1582,9 +1582,12 @@ static int amdgpu_vm_update_ptes(struct
amdgpu_vm_update_params *params,
* completely covered by the range and so potentially
still in use.
*/
while (cursor.pfn < frag_start) {
- amdgpu_vm_free_pts(adev, params->vm, );
+ /* Make sure previous mapping is freed */
+ if (cursor.entry->base.bo) {
+ params->table_freed = true;
+ amdgpu_vm_free_pts(adev, params->vm,
);
+ }
amdgpu_vm_pt_next(adev, );
- params->table_freed = true;
}
} else if (frag >= shift) {
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