[PATCH 1/1] drm/amdkfd: Disable SVM per GPU, not per process
When some GPUs don't support SVM, don't disabe it for the entire process.
That would be inconsistent with the information the process got from the
topology, which indicates SVM support per GPU.
Instead disable SVM support only for the unsupported GPUs. This is done
by checking any per-device attributes against the bitmap of supported
GPUs. Also use the supported GPU bitmap to initialize access bitmaps for
new SVM address ranges.
Don't handle recoverable page faults from unsupported GPUs. (I don't
think there will be unsupported GPUs that can generate recoverable page
faults. But better safe than sorry.)
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 --
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 4 --
drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 -
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 55
drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 7 +++
drivers/gpu/drm/amd/amdkfd/kfd_topology.c| 6 +--
7 files changed, 44 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 5788a4656fa1..67541c30327a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1797,9 +1797,6 @@ static int kfd_ioctl_svm(struct file *filep, struct
kfd_process *p, void *data)
struct kfd_ioctl_svm_args *args = data;
int r = 0;
- if (p->svm_disabled)
- return -EPERM;
-
pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n",
args->start_addr, args->size, args->op, args->nattr);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 91c50739b756..a9b329f0f862 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -405,10 +405,6 @@ int kfd_init_apertures(struct kfd_process *process)
case CHIP_POLARIS12:
case CHIP_VEGAM:
kfd_init_apertures_vi(pdd, id);
- /* VI GPUs cannot support SVM with only
-* 40 bits of virtual address space.
-*/
- process->svm_disabled = true;
break;
case CHIP_VEGA10:
case CHIP_VEGA12:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 329684ee5d6e..6dc22fa1e555 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -743,6 +743,7 @@ struct svm_range_list {
spinlock_t deferred_list_lock;
atomic_tevicted_ranges;
struct delayed_work restore_work;
+ DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);
};
/* Process data */
@@ -826,7 +827,6 @@ struct kfd_process {
/* shared virtual memory registered by this process */
struct svm_range_list svms;
- bool svm_disabled;
bool xnack_enabled;
};
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index f1f40bba5c60..09b98a83f670 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1260,7 +1260,6 @@ static struct kfd_process *create_process(const struct
task_struct *thread)
process->mm = thread->mm;
process->lead_thread = thread->group_leader;
process->n_pdds = 0;
- process->svm_disabled = false;
INIT_DELAYED_WORK(>eviction_work, evict_process_worker);
INIT_DELAYED_WORK(>restore_work, restore_process_worker);
process->last_restore_timestamp = get_jiffies_64();
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 0f18bd0dc64e..420ca667be32 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -281,7 +281,8 @@ svm_range *svm_range_new(struct svm_range_list *svms,
uint64_t start,
p = container_of(svms, struct kfd_process, svms);
if (p->xnack_enabled)
- bitmap_fill(prange->bitmap_access, MAX_GPU_INSTANCE);
+ bitmap_copy(prange->bitmap_access, svms->bitmap_supported,
+ MAX_GPU_INSTANCE);
svm_range_set_default_attributes(>preferred_loc,
>prefetch_loc,
@@ -580,33 +581,25 @@ svm_range_check_attr(struct kfd_process *p,
int gpuidx;
for (i = 0; i < nattr; i++) {
+ gpuidx = MAX_GPU_INSTANCE;
+
switch (attrs[i].type) {
case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC:
if (attrs[i].value != KFD_IOCTL_SVM_LOCATION_SYSMEM &&
-
Re: [PATCH 33/40] drm/amd/pm: Fix a bug in i2c_xfer
On 2021-06-10 5:12 p.m., Alex Deucher wrote: > On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote: >> "req" is now a pointer , i.e. it is no longer >> allocated on the stack, thus taking its reference >> and passing that is a bug. >> >> This commit fixes this bug. >> >> Cc: Alex Deucher >> Signed-off-by: Luben Tuikov > Can we just squash this into the original patch where this was broken? > Reviewed-by: Alex Deucher Yeah, I'll do this--it'll be better this way. Regards, Luben > >> --- >> drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +- >> drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- >> drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- >> 3 files changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c >> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c >> index 0db79a5236e1f1..7d9a2946806f58 100644 >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c >> @@ -1957,7 +1957,7 @@ static int arcturus_i2c_xfer(struct i2c_adapter >> *i2c_adap, >> } >> } >> mutex_lock(>smu.mutex); >> - r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, >> , true); >> + r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, req, >> true); >> mutex_unlock(>smu.mutex); >> if (r) >> goto fail; >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c >> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c >> index 2acf54967c6ab1..0568cbfb023459 100644 >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c >> @@ -2752,7 +2752,7 @@ static int navi10_i2c_xfer(struct i2c_adapter >> *i2c_adap, >> } >> } >> mutex_lock(>smu.mutex); >> - r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, >> , true); >> + r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, req, >> true); >> mutex_unlock(>smu.mutex); >> if (r) >> goto fail; >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c >> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c >> index 44ca3b3f83f4d9..091b3339faadb9 100644 >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c >> @@ -3440,7 +3440,7 @@ static int sienna_cichlid_i2c_xfer(struct i2c_adapter >> *i2c_adap, >> } >> } >> mutex_lock(>smu.mutex); >> - r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, >> , true); >> + r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, req, >> true); >> mutex_unlock(>smu.mutex); >> if (r) >> goto fail; >> -- >> 2.32.0 >> >> ___ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Cluben.tuikov%40amd.com%7Ca961cab9226c41c5fde408d92c54721c%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637589563470538602%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=LQxzFaoGKixKHL8HD2YzWDxv1FYO7oXhW4y0UMpzslY%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Verify Gamma & Degamma LUT sizes in amdgpu_dm_atomic_check
On 2021-06-07 10:53 a.m., Mark Yacoub wrote:
> On Fri, Jun 4, 2021 at 4:17 PM Harry Wentland wrote:
>>
>>
>>
>> On 2021-06-04 1:01 p.m., Mark Yacoub wrote:
>>> From: Mark Yacoub
>>>
>>> For each CRTC state, check the size of Gamma and Degamma LUTs so
>>> unexpected and larger sizes wouldn't slip through.
>>>
>>> TEST: IGT:kms_color::pipe-invalid-gamma-lut-sizes
>>>
>>> Signed-off-by: Mark Yacoub
>>> Change-Id: I9d513a38e8ac2af1b4bf802e1feb1a4d726fba4c
>>> ---
>>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++
>>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
>>> .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 40 ---
>>> 3 files changed, 38 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> index 38d497d30dba8..f6cd522b42a80 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> @@ -9402,6 +9402,9 @@ static int amdgpu_dm_atomic_check(struct drm_device
>>> *dev,
>>> dm_old_crtc_state->dsc_force_changed == false)
>>> continue;
>>>
>>> + if ((ret = amdgpu_dm_verify_lut_sizes(new_crtc_state)))
>>> + goto fail;
>>> +
>>> if (!new_crtc_state->enable)
>>> continue;
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
>>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
>>> index 8bfe901cf2374..1b77cd2612691 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
>>> @@ -541,6 +541,7 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device
>>> *dev);
>>> #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
>>>
>>> void amdgpu_dm_init_color_mod(void);
>>> +int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
>>> int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
>>> int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
>>> struct dc_plane_state *dc_plane_state);
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>>> index 157fe4efbb599..da6f9fcc0b415 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>>> @@ -284,6 +284,37 @@ static int __set_input_tf(struct dc_transfer_func
>>> *func,
>>> return res ? 0 : -ENOMEM;
>>> }
>>>
>>> +/**
>>> + * Verifies that the Degamma and Gamma LUTs attached to the |crtc_state|
>>> are of
>>> + * the expected size.
>>> + * Returns 0 on success.
>>> + */
>>> +int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
>>> +{
>>> + const struct drm_color_lut *lut = NULL;
>>> + uint32_t size = 0;
>>> +
>>> + lut = __extract_blob_lut(crtc_state->degamma_lut, );
>>> + if (lut && size != MAX_COLOR_LUT_ENTRIES) {
>>
>> Isn't the point of the LUT size that it can be variable? Did you observe any
>> problems with LUTs that are not of size 4096?
> Is it supposed to be variable?
> I'm basing my knowledge of LUTs on this IGT Test:
> https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/blob/master/tests/kms_color_helper.c#L281>>
> It does check for invalid sizes and for the exact size, giving me the
> impression that it's not too flexible.
> Is variability of size an AMD specific behavior or should it be a DRM
> behavior?
>>
>> Legacy X-based userspace will give us 256 size LUTs. We can't break support
>> for
>> that. See MAX_COLOR_LEGACY_LUT_ENTRIES.
> In the new function `amdgpu_dm_verify_lut_sizes`, I maintained parity
> with the old behavior. In `amdgpu_dm_update_crtc_color_mgmt`, the
> degamma size is only checked against `MAX_COLOR_LUT_ENTRIES` while
> regamma_size size is checked against both MAX_COLOR_LUT_ENTRIES and
> MAX_COLOR_LEGACY_LUT_ENTRIES:
> https://gitlab.freedesktop.org/agd5f/linux/-/blob/amd-staging-drm-next/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c#L321>>
> Also, in the definition of MAX_COLOR_LEGACY_LUT_ENTRIES, it mentions
> "Legacy gamm[sic] LUT" not degamma:
> https://gitlab.freedesktop.org/agd5f/linux/-/blame/amd-staging-drm-next/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h#L616>>
> As well as the commit when it was introduced, it seems to be handling
> gammas rather than degamma LUTs:
> https://gitlab.freedesktop.org/agd5f/linux/-/commit/086247a4b2fba49800b27807f22bb894cd8363fb>>
> Let me know if this would be a bug in the old behavior and I can fix
> it, or if i'm missing something.
Ah, yes, you're right, of course. Thanks for walking me through it. :)
Reviewed-by: Harry Wentland
Harry
>>
>> Harry
>>
>>> + DRM_DEBUG_DRIVER(
>>> + "Invalid Degamma LUT size. Should be %u but got
>>> %u.\n",
>>> +
Re: [PATCH] drm/amdkfd: Add memory sync before TLB flush on unmap
On 2021-06-10 3:00 p.m., Eric Huang wrote:
It is to fix a failure for SDMA updating PTEs.
Signed-off-by: Eric Huang
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 26 +---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 98f1d2b586c5..17d0a318b708 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1766,14 +1766,33 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file
*filep,
amdgpu_read_unlock(peer->ddev);
goto unmap_memory_from_gpu_failed;
}
- kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
amdgpu_read_unlock(peer->ddev);
args->n_success = i+1;
}
- kfree(devices_arr);
-
mutex_unlock(>mutex);
+ err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem, true);
+ if (err) {
+ pr_debug("Sync memory failed, wait interrupted by user
signal\n");
+ goto sync_memory_failed;
+ }
+
+ /* Flush TLBs after waiting for the page table updates to complete */
+ for (i = 0; i < args->n_devices; i++) {
+ peer = kfd_device_by_id(devices_arr[i]);
+ if (WARN_ON_ONCE(!peer))
+ continue;
+ peer_pdd = kfd_get_process_device_data(peer, p);
+ if (WARN_ON_ONCE(!peer_pdd))
+ continue;
+ if (!amdgpu_read_lock(peer->ddev, true)) {
+ kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
+ amdgpu_read_unlock(peer->ddev);
+ }
+ }
+
+ kfree(devices_arr);
+
return 0;
bind_process_to_device_failed:
@@ -1781,6 +1800,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file
*filep,
unmap_memory_from_gpu_failed:
mutex_unlock(>mutex);
copy_from_user_failed:
+sync_memory_failed:
kfree(devices_arr);
return err;
}
___
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[PATCH] drm/amdkfd: Add memory sync before TLB flush on unmap
It is to fix a failure for SDMA updating PTEs.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 26 +---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 98f1d2b586c5..17d0a318b708 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1766,14 +1766,33 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file
*filep,
amdgpu_read_unlock(peer->ddev);
goto unmap_memory_from_gpu_failed;
}
- kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
amdgpu_read_unlock(peer->ddev);
args->n_success = i+1;
}
- kfree(devices_arr);
-
mutex_unlock(>mutex);
+ err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem,
true);
+ if (err) {
+ pr_debug("Sync memory failed, wait interrupted by user
signal\n");
+ goto sync_memory_failed;
+ }
+
+ /* Flush TLBs after waiting for the page table updates to complete */
+ for (i = 0; i < args->n_devices; i++) {
+ peer = kfd_device_by_id(devices_arr[i]);
+ if (WARN_ON_ONCE(!peer))
+ continue;
+ peer_pdd = kfd_get_process_device_data(peer, p);
+ if (WARN_ON_ONCE(!peer_pdd))
+ continue;
+ if (!amdgpu_read_lock(peer->ddev, true)) {
+ kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
+ amdgpu_read_unlock(peer->ddev);
+ }
+ }
+
+ kfree(devices_arr);
+
return 0;
bind_process_to_device_failed:
@@ -1781,6 +1800,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file
*filep,
unmap_memory_from_gpu_failed:
mutex_unlock(>mutex);
copy_from_user_failed:
+sync_memory_failed:
kfree(devices_arr);
return err;
}
--
2.25.1
___
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Re: [PATCH 40/40] drm/amdgpu: Use a single loop
On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
>
> In smu_v11_0_i2c_transmit() use a single loop to
> transmit bytes, instead of two nested loops.
>
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 72 ++
> 1 file changed, 34 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> index 7f48ee020bc03e..751ea2517c4380 100644
> --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> @@ -243,49 +243,45 @@ static uint32_t smu_v11_0_i2c_transmit(struct
> i2c_adapter *control,
> /* Clear status bits */
> smu_v11_0_i2c_clear_status(control);
>
> -
> timeout_counter = jiffies + msecs_to_jiffies(20);
>
> while (numbytes > 0) {
> reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
> - if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
> - do {
> - reg = REG_SET_FIELD(reg,
> CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]);
> -
> - /* Final message, final byte, must
> -* generate a STOP, to release the
> -* bus, i.e. don't hold SCL low.
> -*/
> - if (numbytes == 1 && i2c_flag & I2C_M_STOP)
> - reg = REG_SET_FIELD(reg,
> -
> CKSVII2C_IC_DATA_CMD,
> - STOP, 1);
> -
> - if (bytes_sent == 0 && i2c_flag &
> I2C_X_RESTART)
> - reg = REG_SET_FIELD(reg,
> -
> CKSVII2C_IC_DATA_CMD,
> - RESTART, 1);
> -
> - /* Write */
> - reg = REG_SET_FIELD(reg,
> CKSVII2C_IC_DATA_CMD, CMD, 0);
> - WREG32_SOC15(SMUIO, 0,
> mmCKSVII2C_IC_DATA_CMD, reg);
> -
> - /* Record that the bytes were transmitted */
> - bytes_sent++;
> - numbytes--;
> -
> - reg = RREG32_SOC15(SMUIO, 0,
> mmCKSVII2C_IC_STATUS);
> -
> - } while (numbytes && REG_GET_FIELD(reg,
> CKSVII2C_IC_STATUS, TFNF));
> - }
> + if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
> + /*
> +* We waited for too long for the transmission
> +* FIFO to become not-full. Exit the loop
> +* with error.
> +*/
> + if (time_after(jiffies, timeout_counter)) {
> + ret |= I2C_SW_TIMEOUT;
> + goto Err;
> + }
> + } else {
> + reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT,
> + data[bytes_sent]);
>
> - /*
> -* We waited too long for the transmission FIFO to become
> not-full.
> -* Exit the loop with error.
> -*/
> - if (time_after(jiffies, timeout_counter)) {
> - ret |= I2C_SW_TIMEOUT;
> - goto Err;
> + /* Final message, final byte, must generate a
> +* STOP to release the bus, i.e. don't hold
> +* SCL low.
> +*/
> + if (numbytes == 1 && i2c_flag & I2C_M_STOP)
> + reg = REG_SET_FIELD(reg,
> + CKSVII2C_IC_DATA_CMD,
> + STOP, 1);
> +
> + if (bytes_sent == 0 && i2c_flag & I2C_X_RESTART)
> + reg = REG_SET_FIELD(reg,
> + CKSVII2C_IC_DATA_CMD,
> + RESTART, 1);
> +
> + /* Write */
> + reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD,
> 0);
> + WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
> +
> + /* Record that the bytes were transmitted */
> + bytes_sent++;
> + numbytes--;
> }
> }
>
> --
> 2.32.0
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
>
[PATCH 1/1] drm/amdgpu: remove amdgpu_vm_pt
Page table entries are now in embedded in VM BO, so
we do not need struct amdgpu_vm_pt. This patch replaces
struct amdgpu_vm_pt with struct amdgpu_vm_bo_base.
Signed-off-by: Nirmoy Das
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 26 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 12 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 164 --
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 9 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +-
12 files changed, 105 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index fb6bcc386de1..f96598279593 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -356,7 +356,7 @@ static int amdgpu_amdkfd_validate_vm_bo(void *_unused,
struct amdgpu_bo *bo)
*/
static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
{
- struct amdgpu_bo *pd = vm->root.base.bo;
+ struct amdgpu_bo *pd = vm->root.bo;
struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
int ret;
@@ -372,7 +372,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
return ret;
}
- vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
+ vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
if (vm->use_cpu_for_update) {
ret = amdgpu_bo_kmap(pd, NULL);
@@ -387,7 +387,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
{
- struct amdgpu_bo *pd = vm->root.base.bo;
+ struct amdgpu_bo *pd = vm->root.bo;
struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
int ret;
@@ -1153,7 +1153,7 @@ static int process_sync_pds_resv(struct
amdkfd_process_info *process_info,
list_for_each_entry(peer_vm, _info->vm_list_head,
vm_list_node) {
- struct amdgpu_bo *pd = peer_vm->root.base.bo;
+ struct amdgpu_bo *pd = peer_vm->root.bo;
ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
AMDGPU_SYNC_NE_OWNER,
@@ -1220,7 +1220,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void
**process_info,
vm->process_info = *process_info;
/* Validate page directory and attach eviction fence */
- ret = amdgpu_bo_reserve(vm->root.base.bo, true);
+ ret = amdgpu_bo_reserve(vm->root.bo, true);
if (ret)
goto reserve_pd_fail;
ret = vm_validate_pt_pd_bos(vm);
@@ -1228,16 +1228,16 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void
**process_info,
pr_err("validate_pt_pd_bos() failed\n");
goto validate_pd_fail;
}
- ret = amdgpu_bo_sync_wait(vm->root.base.bo,
+ ret = amdgpu_bo_sync_wait(vm->root.bo,
AMDGPU_FENCE_OWNER_KFD, false);
if (ret)
goto wait_pd_fail;
- ret = dma_resv_reserve_shared(vm->root.base.bo->tbo.base.resv, 1);
+ ret = dma_resv_reserve_shared(vm->root.bo->tbo.base.resv, 1);
if (ret)
goto reserve_shared_fail;
- amdgpu_bo_fence(vm->root.base.bo,
+ amdgpu_bo_fence(vm->root.bo,
>process_info->eviction_fence->base, true);
- amdgpu_bo_unreserve(vm->root.base.bo);
+ amdgpu_bo_unreserve(vm->root.bo);
/* Update process info */
mutex_lock(>process_info->lock);
@@ -1251,7 +1251,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void
**process_info,
reserve_shared_fail:
wait_pd_fail:
validate_pd_fail:
- amdgpu_bo_unreserve(vm->root.base.bo);
+ amdgpu_bo_unreserve(vm->root.bo);
reserve_pd_fail:
vm->process_info = NULL;
if (info) {
@@ -1306,7 +1306,7 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device
*adev,
struct amdgpu_vm *vm)
{
struct amdkfd_process_info *process_info = vm->process_info;
- struct amdgpu_bo *pd = vm->root.base.bo;
+ struct amdgpu_bo *pd = vm->root.bo;
if (!process_info)
return;
@@ -1362,7 +1362,7 @@ void amdgpu_amdkfd_gpuvm_release_process_vm(struct
kgd_dev *kgd, void *drm_priv)
uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
{
struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
- struct amdgpu_bo *pd = avm->root.base.bo;
+ struct amdgpu_bo *pd = avm->root.bo;
Re: [PATCH 39/40] drm/amdgpu: Fix koops when accessing RAS EEPROM
On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
>
> Debugfs RAS EEPROM files are available when
> the ASIC supports RAS, and when the debugfs is
> enabled, an also when "ras_enable" module
> parameter is set to 0. However in this case,
> we get a kernel oops when accessing some of
> the "ras_..." controls in debugfs. The reason
> for this is that struct amdgpu_ras::adev is
> unset. This commit sets it, thus enabling access
> to those facilities. Note that this facilitates
> EEPROM access and not necessarily RAS features or
> functionality.
>
> Cc: Alexander Deucher
> Cc: John Clements
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 16
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index d791a360a92366..772d87701ad4a8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -1947,11 +1947,20 @@ int amdgpu_ras_recovery_init(struct amdgpu_device
> *adev)
> bool exc_err_limit = false;
> int ret;
>
> - if (adev->ras_enabled && con)
> - data = >eh_data;
> - else
> + if (!con)
> + return 0;
> +
> + /* Allow access to RAS EEPROM via debugfs, when the ASIC
> +* supports RAS and debugfs is enabled, but when
> +* adev->ras_enabled is unset, i.e. when "ras_enable"
> +* module parameter is set to 0.
> +*/
> + con->adev = adev;
> +
> + if (!adev->ras_enabled)
> return 0;
>
> + data = >eh_data;
> *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
> if (!*data) {
> ret = -ENOMEM;
> @@ -1961,7 +1970,6 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
> mutex_init(>recovery_lock);
> INIT_WORK(>recovery_work, amdgpu_ras_do_recovery);
> atomic_set(>in_recovery, 0);
> - con->adev = adev;
>
> max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
> amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
> --
> 2.32.0
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 36/40] drm/amdgpu: Use explicit cardinality for clarity
On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
>
> RAS_MAX_RECORD_NUM may mean the maximum record
> number, as in the maximum house number on your
> street, or it may mean the maximum number of
> records, as in the count of records, which is also
> a number. To make this distinction whether the
> number is ordinal (index) or cardinal (count),
> rename this macro to RAS_MAX_RECORD_COUNT.
>
> This makes it easy to understand what it refers
> to, especially when we compute quantities such as,
> how many records do we have left in the table,
> especially when there are so many other numbers,
> quantities and numerical macros around.
>
> Also rename the long,
> amdgpu_ras_eeprom_get_record_max_length() to the
> more succinct and clear,
> amdgpu_ras_eeprom_max_record_count().
>
> When computing the threshold, which also deals
> with counts, i.e. "how many", use cardinal
> "max_eeprom_records_count", than the quantitative
> "max_eeprom_records_len".
>
> Simplify the logic here and there, as well.
>
> Cc: Guchun Chen
> Cc: John Clements
> Cc: Hawking Zhang
> Cc: Alexander Deucher
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 50 ---
> .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 8 +--
> .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h| 2 +-
> 4 files changed, 30 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 3de1accb060e37..0203f654576bcc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -853,11 +853,10 @@ MODULE_PARM_DESC(reset_method, "GPU reset method (-1 =
> auto (default), 0 = legac
> module_param_named(reset_method, amdgpu_reset_method, int, 0444);
>
> /**
> - * DOC: bad_page_threshold (int)
> - * Bad page threshold is to specify the threshold value of faulty pages
> - * detected by RAS ECC, that may result in GPU entering bad status if total
> - * faulty pages by ECC exceed threshold value and leave it for user's further
> - * check.
> + * DOC: bad_page_threshold (int) Bad page threshold is specifies the
> + * threshold value of faulty pages detected by RAS ECC, which may
> + * result in the GPU entering bad status when the number of total
> + * faulty pages by ECC exceeds the threshold value.
> */
> MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default
> value), 0 = disable bad page retirement)");
> module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index 66c96c65e7eeb9..95ab400b641af0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -71,8 +71,8 @@ const char *ras_block_string[] = {
> /* inject address is 52 bits */
> #defineRAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
>
> -/* typical ECC bad page rate(1 bad page per 100MB VRAM) */
> -#define RAS_BAD_PAGE_RATE (100 * 1024 * 1024ULL)
> +/* typical ECC bad page rate is 1 bad page per 100MB VRAM */
> +#define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL)
>
> enum amdgpu_ras_retire_page_reservation {
> AMDGPU_RAS_RETIRE_PAGE_RESERVED,
> @@ -1841,27 +1841,24 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device
> *adev)
> static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
> {
> struct amdgpu_ras_eeprom_control *control =
> - >psp.ras.ras->eeprom_control;
> - struct eeprom_table_record *bps = NULL;
> - int ret = 0;
> + >psp.ras.ras->eeprom_control;
> + struct eeprom_table_record *bps;
> + int ret;
>
> /* no bad page record, skip eeprom access */
> - if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
> - return ret;
> + if (control->num_recs == 0 || amdgpu_bad_page_threshold == 0)
> + return 0;
>
> bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
> if (!bps)
> return -ENOMEM;
>
> - if (amdgpu_ras_eeprom_read(control, bps, control->num_recs)) {
> + ret = amdgpu_ras_eeprom_read(control, bps, control->num_recs);
> + if (ret)
> dev_err(adev->dev, "Failed to load EEPROM table records!");
> - ret = -EIO;
> - goto out;
> - }
> -
> - ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
> + else
> + ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
>
> -out:
> kfree(bps);
> return ret;
> }
> @@ -1901,11 +1898,9 @@ static bool amdgpu_ras_check_bad_page(struct
> amdgpu_device *adev,
> }
>
> static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
> -
Re: [PATCH 34/40] drm/amdgpu: Fix amdgpu_ras_eeprom_init()
On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
>
> No need to account for the 2 bytes of EEPROM
> address--this is now well abstracted away by
> the fixes the the lower layers.
>
> Cc: Andrey Grodzovsky
> Cc: Alexander Deucher
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index dc48c556398039..7d0f9e1e62dc4f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -306,7 +306,7 @@ int amdgpu_ras_eeprom_init(struct
> amdgpu_ras_eeprom_control *control,
> return ret;
> }
>
> - __decode_table_header_from_buff(hdr, [2]);
> + __decode_table_header_from_buff(hdr, buff);
>
> if (hdr->header == RAS_TABLE_HDR_VAL) {
> control->num_recs = (hdr->tbl_size - RAS_TABLE_HEADER_SIZE) /
> --
> 2.32.0
>
> ___
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Re: [PATCH 33/40] drm/amd/pm: Fix a bug in i2c_xfer
On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote: > > "req" is now a pointer , i.e. it is no longer > allocated on the stack, thus taking its reference > and passing that is a bug. > > This commit fixes this bug. > > Cc: Alex Deucher > Signed-off-by: Luben Tuikov Can we just squash this into the original patch where this was broken? Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +- > drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- > drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > index 0db79a5236e1f1..7d9a2946806f58 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > @@ -1957,7 +1957,7 @@ static int arcturus_i2c_xfer(struct i2c_adapter > *i2c_adap, > } > } > mutex_lock(>smu.mutex); > - r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, , > true); > + r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, req, > true); > mutex_unlock(>smu.mutex); > if (r) > goto fail; > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > index 2acf54967c6ab1..0568cbfb023459 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > @@ -2752,7 +2752,7 @@ static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap, > } > } > mutex_lock(>smu.mutex); > - r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, , > true); > + r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, req, > true); > mutex_unlock(>smu.mutex); > if (r) > goto fail; > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > index 44ca3b3f83f4d9..091b3339faadb9 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > @@ -3440,7 +3440,7 @@ static int sienna_cichlid_i2c_xfer(struct i2c_adapter > *i2c_adap, > } > } > mutex_lock(>smu.mutex); > - r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, , > true); > + r = smu_cmn_update_table(>smu, SMU_TABLE_I2C_COMMANDS, 0, req, > true); > mutex_unlock(>smu.mutex); > if (r) > goto fail; > -- > 2.32.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 32/40] drm/amdgpu: Return result fix in RAS
On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
>
> The low level EEPROM write method, doesn't return
> 1, but the number of bytes written. Thus do not
> compare to 1, instead, compare to greater than 0
> for success.
>
> Other cleanup: if the lower layers returned
> -errno, then return that, as opposed to
> overwriting the error code with one-fits-all
> -EINVAL. For instance, some return -EAGAIN.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c| 3 +--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 22 +++
> .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 2 +-
> drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c| 3 +--
> 4 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> index a5a87affedabf1..a4815af111ed12 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> @@ -105,8 +105,7 @@ static int __amdgpu_eeprom_xfer(struct i2c_adapter
> *i2c_adap, u32 eeprom_addr,
> int r;
> u16 len;
>
> - r = 0;
> - for ( ; buf_size > 0;
> + for (r = 0; buf_size > 0;
> buf_size -= len, eeprom_addr += len, eeprom_buf += len) {
> /* Set the EEPROM address we want to write to/read from.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index e3ad081eddd40b..66c96c65e7eeb9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -355,8 +355,9 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file
> *f,
> * to see which blocks support RAS on a particular asic.
> *
> */
> -static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char
> __user *buf,
> - size_t size, loff_t *pos)
> +static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
> +const char __user *buf,
> +size_t size, loff_t *pos)
> {
> struct amdgpu_device *adev = (struct amdgpu_device
> *)file_inode(f)->i_private;
> struct ras_debug_if data;
> @@ -370,7 +371,7 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file
> *f, const char __user *
>
> ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, );
> if (ret)
> - return -EINVAL;
> + return ret;
>
> if (data.op == 3) {
> ret = amdgpu_reserve_page_direct(adev, data.inject.address);
> @@ -439,21 +440,24 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct
> file *f, const char __user *
> * will reset EEPROM table to 0 entries.
> *
> */
> -static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char
> __user *buf,
> - size_t size, loff_t *pos)
> +static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
> + const char __user *buf,
> + size_t size, loff_t *pos)
> {
> struct amdgpu_device *adev =
> (struct amdgpu_device *)file_inode(f)->i_private;
> int ret;
>
> ret = amdgpu_ras_eeprom_reset_table(
> - &(amdgpu_ras_get_context(adev)->eeprom_control));
> + &(amdgpu_ras_get_context(adev)->eeprom_control));
>
> - if (ret == 1) {
> + if (ret > 0) {
> + /* Something was written to EEPROM.
> +*/
> amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
> return size;
> } else {
> - return -EIO;
> + return ret;
> }
> }
>
> @@ -1991,7 +1995,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
> kfree(*data);
> con->eh_data = NULL;
> out:
> - dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
> + dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
>
> /*
> * Except error threshold exceeding case, other failure cases in this
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index 17cea35275e46c..dc48c556398039 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -335,7 +335,7 @@ int amdgpu_ras_eeprom_init(struct
> amdgpu_ras_eeprom_control *control,
> ret = amdgpu_ras_eeprom_reset_table(control);
> }
>
> - return ret == 1 ? 0 : -EIO;
> + return ret > 0 ? 0 : -EIO;
> }
>
> static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control
> *control,
>
Re: [PATCH 31/40] drm/amdgpu: Fix width of I2C address
On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
>
> The I2C address is kept as a 16-bit quantity in
> the kernel. The I2C_TAR::I2C_TAR field is 10-bit
> wide.
>
> Fix the width of the I2C address for Vega20 from 8
> bits to 16 bits to accommodate the full spectrum
> of I2C address space.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 19 +++
> 1 file changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> index e403ba556e5590..65035256756679 100644
> --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> @@ -111,12 +111,15 @@ static void smu_v11_0_i2c_set_clock(struct i2c_adapter
> *control)
> WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20);
> }
>
> -static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, uint8_t
> address)
> +static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, u16
> address)
> {
> struct amdgpu_device *adev = to_amdgpu_device(control);
>
> - /* We take 7-bit addresses raw */
> - WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, (address & 0xFF));
> + /* The IC_TAR::IC_TAR field is 10-bits wide.
> +* It takes a 7-bit or 10-bit addresses as an address,
> +* i.e. no read/write bit--no wire format, just the address.
> +*/
> + WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, address & 0x3FF);
> }
>
> static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)
> @@ -215,8 +218,8 @@ static uint32_t smu_v11_0_i2c_poll_rx_status(struct
> i2c_adapter *control)
> * Returns 0 on success or error.
> */
> static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control,
> - uint8_t address, uint8_t *data,
> - uint32_t numbytes, uint32_t i2c_flag)
> + u16 address, u8 *data,
> + u32 numbytes, u32 i2c_flag)
> {
> struct amdgpu_device *adev = to_amdgpu_device(control);
> uint32_t bytes_sent, reg, ret = 0;
> @@ -225,7 +228,7 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter
> *control,
> bytes_sent = 0;
>
> DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
> -(uint16_t)address, numbytes);
> +address, numbytes);
>
> if (drm_debug_enabled(DRM_UT_DRIVER)) {
> print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
> @@ -318,8 +321,8 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter
> *control,
> * Returns 0 on success or error.
> */
> static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control,
> -uint8_t address, uint8_t *data,
> -uint32_t numbytes, uint8_t i2c_flag)
> + u16 address, u8 *data,
> + u32 numbytes, u32 i2c_flag)
> {
> struct amdgpu_device *adev = to_amdgpu_device(control);
> uint32_t bytes_received, ret = I2C_OK;
> --
> 2.32.0
>
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Re: [PATCH 30/40] drm/amd/pm: Simplify managed I2C transfer functions
On Tue, Jun 8, 2021 at 5:41 PM Luben Tuikov wrote:
>
> Now that we have an I2C quirk table for
> SMU-managed I2C controllers, the I2C core does the
> checks for us, so we don't need to do them, and so
> simplify the managed I2C transfer functions.
>
> Also, for Arcturus and Navi10, fix setting the
> command type from "cmd->CmdConfig" to "cmd->Cmd".
> The latter is what appears to be taking in
> the enumeration I2C_CMD_... as an integer,
> not a bit-flag.
>
> For Sienna, the "Cmd" field seems to have been
> eliminated, and command type and flags all live in
> the "CmdConfig" field--this is left untouched.
>
> Fix: Detect and add changing of direction
> bit-flag, as this is necessary for the SMU to
> detect the direction change in the 1-d array of
> data it gets.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 78 ---
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 78 ---
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 76 --
> 3 files changed, 95 insertions(+), 137 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index de8d7513042966..0db79a5236e1f1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -1907,31 +1907,14 @@ static int arcturus_dpm_set_vcn_enable(struct
> smu_context *smu, bool enable)
> }
>
> static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
> -struct i2c_msg *msgs, int num)
> +struct i2c_msg *msg, int num_msgs)
> {
> struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
> struct smu_table_context *smu_table = >smu.smu_table;
> struct smu_table *table = _table->driver_table;
> SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
> - short available_bytes = MAX_SW_I2C_COMMANDS;
> - int i, j, r, c, num_done = 0;
> - u8 slave;
> -
> - /* only support a single slave addr per transaction */
> - slave = msgs[0].addr;
> - for (i = 0; i < num; i++) {
> - if (slave != msgs[i].addr)
> - return -EINVAL;
> -
> - available_bytes -= msgs[i].len;
> - if (available_bytes >= 0) {
> - num_done++;
> - } else {
> - /* This message and all the follwing won't be
> processed */
> - available_bytes += msgs[i].len;
> - break;
> - }
> - }
> + int i, j, r, c;
> + u16 dir;
>
> req = kzalloc(sizeof(*req), GFP_KERNEL);
> if (!req)
> @@ -1939,33 +1922,38 @@ static int arcturus_i2c_xfer(struct i2c_adapter
> *i2c_adap,
>
> req->I2CcontrollerPort = 1;
> req->I2CSpeed = I2C_SPEED_FAST_400K;
> - req->SlaveAddress = slave << 1; /* 8 bit addresses */
> - req->NumCmds = MAX_SW_I2C_COMMANDS - available_bytes;;
> -
> - c = 0;
> - for (i = 0; i < num_done; i++) {
> - struct i2c_msg *msg = [i];
> + req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
> + dir = msg[0].flags & I2C_M_RD;
>
> - for (j = 0; j < msg->len; j++) {
> - SwI2cCmd_t *cmd = >SwI2cCmds[c++];
> + for (c = i = 0; i < num_msgs; i++) {
> + for (j = 0; j < msg[i].len; j++, c++) {
> + SwI2cCmd_t *cmd = >SwI2cCmds[c];
>
> if (!(msg[i].flags & I2C_M_RD)) {
> /* write */
> - cmd->CmdConfig |= I2C_CMD_WRITE;
> - cmd->RegisterAddr = msg->buf[j];
> + cmd->Cmd = I2C_CMD_WRITE;
> + cmd->RegisterAddr = msg[i].buf[j];
> + }
> +
> + if ((dir ^ msg[i].flags) & I2C_M_RD) {
> + /* The direction changes.
> +*/
> + dir = msg[i].flags & I2C_M_RD;
> + cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
> }
>
> + req->NumCmds++;
> +
> /*
> * Insert STOP if we are at the last byte of either
> last
> * message for the transaction or the client
> explicitly
> * requires a STOP at this particular message.
> */
> - if ((j == msg->len -1 ) &&
> - ((i == num_done - 1) || (msg[i].flags &
> I2C_M_STOP)))
> + if
Re: [PATCH 29/40] drm/amd/pm: Extend the I2C quirk table
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> Extend the I2C quirk table for SMU access
> controlled I2C adapters. Let the kernel I2C layer
> check that the messages all have the same address,
> and that their combined size doesn't exceed the
> maximum size of a SMU software I2C request.
>
> Suggested-by: Jean Delvare
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 5 -
> drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 5 -
> drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 5 -
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 974740ac72fded..de8d7513042966 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -2006,8 +2006,11 @@ static const struct i2c_algorithm arcturus_i2c_algo = {
>
>
> static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = {
> - .max_read_len = MAX_SW_I2C_COMMANDS,
> + .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR,
> + .max_read_len = MAX_SW_I2C_COMMANDS,
> .max_write_len = MAX_SW_I2C_COMMANDS,
> + .max_comb_1st_msg_len = 2,
> + .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
> };
>
> static int arcturus_i2c_control_init(struct smu_context *smu, struct
> i2c_adapter *control)
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 8ab06fa87edb04..1b8cd3746d0ebc 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -2800,8 +2800,11 @@ static const struct i2c_algorithm navi10_i2c_algo = {
> };
>
> static const struct i2c_adapter_quirks navi10_i2c_control_quirks = {
> - .max_read_len = MAX_SW_I2C_COMMANDS,
> + .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR,
> + .max_read_len = MAX_SW_I2C_COMMANDS,
> .max_write_len = MAX_SW_I2C_COMMANDS,
> + .max_comb_1st_msg_len = 2,
> + .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
> };
>
> static int navi10_i2c_control_init(struct smu_context *smu, struct
> i2c_adapter *control)
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 91614ae186f7f5..b38127f8009d3d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -3488,8 +3488,11 @@ static const struct i2c_algorithm
> sienna_cichlid_i2c_algo = {
> };
>
> static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
> - .max_read_len = MAX_SW_I2C_COMMANDS,
> + .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR,
> + .max_read_len = MAX_SW_I2C_COMMANDS,
> .max_write_len = MAX_SW_I2C_COMMANDS,
> + .max_comb_1st_msg_len = 2,
> + .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
> };
>
> static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct
> i2c_adapter *control)
> --
> 2.32.0
>
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Re: [PATCH 28/40] drm/amdgpu: EEPROM: add explicit read and write
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> Add explicit amdgpu_eeprom_read() and
> amdgpu_eeprom_write() for clarity.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h | 16
> drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 5 ++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 10 +-
> 3 files changed, 23 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h
> index 417472be2712e6..966b434f0de2b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h
> @@ -29,4 +29,20 @@
> int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,
>u8 *eeprom_buf, u16 bytes, bool read);
>
> +static inline int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,
> +u32 eeprom_addr, u8 *eeprom_buf,
> +u16 bytes)
> +{
> + return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
> + true);
> +}
> +
> +static inline int amdgpu_eeprom_write(struct i2c_adapter *i2c_adap,
> + u32 eeprom_addr, u8 *eeprom_buf,
> + u16 bytes)
> +{
> + return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
> + false);
> +}
> +
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> index 69b9559f840ac3..7709caeb233d67 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> @@ -66,7 +66,7 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device
> *adev, uint32_t addrptr,
> {
> int ret, size;
>
> - ret = amdgpu_eeprom_xfer(>pm.smu_i2c, addrptr, buff, 1, true);
> + ret = amdgpu_eeprom_read(>pm.smu_i2c, addrptr, buff, 1);
> if (ret < 1) {
> DRM_WARN("FRU: Failed to get size field");
> return ret;
> @@ -77,8 +77,7 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device
> *adev, uint32_t addrptr,
> */
> size = buff[0] - I2C_PRODUCT_INFO_OFFSET;
>
> - ret = amdgpu_eeprom_xfer(>pm.smu_i2c, addrptr + 1, buff, size,
> -true);
> + ret = amdgpu_eeprom_read(>pm.smu_i2c, addrptr + 1, buff, size);
> if (ret < 1) {
> DRM_WARN("FRU: Failed to get data field");
> return ret;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index 550a31953d2da1..17cea35275e46c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -151,9 +151,9 @@ static int __update_table_header(struct
> amdgpu_ras_eeprom_control *control,
>
> /* i2c may be unstable in gpu reset */
> down_read(>reset_sem);
> - ret = amdgpu_eeprom_xfer(>pm.smu_i2c,
> -control->i2c_address + RAS_HDR_START,
> -buff, RAS_TABLE_HEADER_SIZE, false);
> + ret = amdgpu_eeprom_write(>pm.smu_i2c,
> + control->i2c_address + RAS_HDR_START,
> + buff, RAS_TABLE_HEADER_SIZE);
> up_read(>reset_sem);
>
> if (ret < 1)
> @@ -298,9 +298,9 @@ int amdgpu_ras_eeprom_init(struct
> amdgpu_ras_eeprom_control *control,
> mutex_init(>tbl_mutex);
>
> /* Read/Create table header from EEPROM address 0 */
> - ret = amdgpu_eeprom_xfer(>pm.smu_i2c,
> + ret = amdgpu_eeprom_read(>pm.smu_i2c,
> control->i2c_address + RAS_HDR_START,
> -buff, RAS_TABLE_HEADER_SIZE, true);
> +buff, RAS_TABLE_HEADER_SIZE);
> if (ret < 1) {
> DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret);
> return ret;
> --
> 2.32.0
>
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Re: [PATCH 27/40] drm/amdgpu: RAS xfer to read/write
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> Wrap amdgpu_ras_eeprom_xfer(..., bool write),
> into amdgpu_ras_eeprom_read() and
> amdgpu_ras_eeprom_write(), as that makes reading
> and understanding the code clearer.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 ---
> .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 24 +++
> .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h| 8 ---
> 3 files changed, 28 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index beaa1fee7f71f3..e3ad081eddd40b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -1817,10 +1817,9 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device
> *adev)
> save_count = data->count - control->num_recs;
> /* only new entries are saved */
> if (save_count > 0) {
> - if (amdgpu_ras_eeprom_xfer(control,
> - >bps[control->num_recs],
> - save_count,
> - true)) {
> + if (amdgpu_ras_eeprom_write(control,
> + >bps[control->num_recs],
> + save_count)) {
> dev_err(adev->dev, "Failed to save EEPROM table
> data!");
> return -EIO;
> }
> @@ -1850,7 +1849,7 @@ static int amdgpu_ras_load_bad_pages(struct
> amdgpu_device *adev)
> if (!bps)
> return -ENOMEM;
>
> - if (amdgpu_ras_eeprom_xfer(control, bps, control->num_recs, false)) {
> + if (amdgpu_ras_eeprom_read(control, bps, control->num_recs)) {
> dev_err(adev->dev, "Failed to load EEPROM table records!");
> ret = -EIO;
> goto out;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index 9e3fbc44b4bc4a..550a31953d2da1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -432,9 +432,9 @@ bool amdgpu_ras_eeprom_check_err_threshold(struct
> amdgpu_device *adev)
> return false;
> }
>
> -int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
> - struct eeprom_table_record *records,
> - const u32 num, bool write)
> +static int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
> + struct eeprom_table_record *records,
> + const u32 num, bool write)
> {
> int i, ret = 0;
> unsigned char *buffs, *buff;
> @@ -554,6 +554,20 @@ int amdgpu_ras_eeprom_xfer(struct
> amdgpu_ras_eeprom_control *control,
> return ret == num ? 0 : -EIO;
> }
>
> +int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
> + struct eeprom_table_record *records,
> + const u32 num)
> +{
> + return amdgpu_ras_eeprom_xfer(control, records, num, false);
> +}
> +
> +int amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
> + struct eeprom_table_record *records,
> + const u32 num)
> +{
> + return amdgpu_ras_eeprom_xfer(control, records, num, true);
> +}
> +
> inline uint32_t amdgpu_ras_eeprom_get_record_max_length(void)
> {
> return RAS_MAX_RECORD_NUM;
> @@ -574,13 +588,13 @@ void amdgpu_ras_eeprom_test(struct
> amdgpu_ras_eeprom_control *control)
> recs[i].retired_page = i;
> }
>
> - if (!amdgpu_ras_eeprom_xfer(control, recs, 1, true)) {
> + if (!amdgpu_ras_eeprom_write(control, recs, 1)) {
>
> memset(recs, 0, sizeof(*recs) * 1);
>
> control->next_addr = RAS_RECORD_START;
>
> - if (!amdgpu_ras_eeprom_xfer(control, recs, 1, false)) {
> + if (!amdgpu_ras_eeprom_read(control, recs)) {
> for (i = 0; i < 1; i++)
> DRM_INFO("rec.address :0x%llx,
> rec.retired_page :%llu",
> recs[i].address,
> recs[i].retired_page);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
> index 6a1bd527bce57a..fa9c509a8e2f2b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
> @@ -82,9 +82,11 @@ int amdgpu_ras_eeprom_reset_table(struct
> amdgpu_ras_eeprom_control *control);
>
> bool amdgpu_ras_eeprom_check_err_threshold(struct
Re: [PATCH 26/40] drm/amdgpu: Rename misspelled function
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> Instead of fixing the spelling in
> amdgpu_ras_eeprom_process_recods(),
> rename it to,
> amdgpu_ras_eeprom_xfer(),
> to look similar to other I2C and protocol
> transfer (read/write) functions.
>
> Also to keep the column span to within reason by
> using a shorter name.
>
> Change the "num" function parameter from "int" to
> "const u32" since it is the number of items
> (records) to xfer, i.e. their count, which cannot
> be a negative number.
>
> Also swap the order of parameters, keeping the
> pointer to records and their number next to each
> other, while the direction now becomes the last
> parameter.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 11 +--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 7 +++
> 3 files changed, 13 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index ec936cde272602..beaa1fee7f71f3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -1817,10 +1817,10 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device
> *adev)
> save_count = data->count - control->num_recs;
> /* only new entries are saved */
> if (save_count > 0) {
> - if (amdgpu_ras_eeprom_process_recods(control,
> -
> >bps[control->num_recs],
> - true,
> - save_count)) {
> + if (amdgpu_ras_eeprom_xfer(control,
> + >bps[control->num_recs],
> + save_count,
> + true)) {
> dev_err(adev->dev, "Failed to save EEPROM table
> data!");
> return -EIO;
> }
> @@ -1850,8 +1850,7 @@ static int amdgpu_ras_load_bad_pages(struct
> amdgpu_device *adev)
> if (!bps)
> return -ENOMEM;
>
> - if (amdgpu_ras_eeprom_process_recods(control, bps, false,
> - control->num_recs)) {
> + if (amdgpu_ras_eeprom_xfer(control, bps, control->num_recs, false)) {
> dev_err(adev->dev, "Failed to load EEPROM table records!");
> ret = -EIO;
> goto out;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index d3678706bb736d..9e3fbc44b4bc4a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -432,9 +432,9 @@ bool amdgpu_ras_eeprom_check_err_threshold(struct
> amdgpu_device *adev)
> return false;
> }
>
> -int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control
> *control,
> -struct eeprom_table_record *records,
> -bool write, int num)
> +int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
> + struct eeprom_table_record *records,
> + const u32 num, bool write)
> {
> int i, ret = 0;
> unsigned char *buffs, *buff;
> @@ -574,13 +574,13 @@ void amdgpu_ras_eeprom_test(struct
> amdgpu_ras_eeprom_control *control)
> recs[i].retired_page = i;
> }
>
> - if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) {
> + if (!amdgpu_ras_eeprom_xfer(control, recs, 1, true)) {
>
> memset(recs, 0, sizeof(*recs) * 1);
>
> control->next_addr = RAS_RECORD_START;
>
> - if (!amdgpu_ras_eeprom_process_recods(control, recs, false,
> 1)) {
> + if (!amdgpu_ras_eeprom_xfer(control, recs, 1, false)) {
> for (i = 0; i < 1; i++)
> DRM_INFO("rec.address :0x%llx,
> rec.retired_page :%llu",
> recs[i].address,
> recs[i].retired_page);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
> index 4c4c3d840a35c5..6a1bd527bce57a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
> @@ -82,10 +82,9 @@ int amdgpu_ras_eeprom_reset_table(struct
> amdgpu_ras_eeprom_control *control);
>
> bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev);
>
> -int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control
> *control,
> - struct
Re: [PATCH 25/40] drm/amdgpu: RAS: EEPROM --> RAS
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> In amdgpu_ras_eeprom.c--the interface from RAS to
> EEPROM, rename macros from EEPROM to RAS, to
> indicate that the quantities and objects are RAS
> specific, not EEPROM. We can decrease the RAS
> table, or put it in different offset of EEPROM as
> needed in the future.
>
> Remove EEPROM_ADDRESS_SIZE macro definition, equal
> to 2, from the file and calculations, as that
> quantity is computed and added on the stack,
> in the lower layer, amdgpu_eeprom_xfer().
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 103 +-
> 1 file changed, 50 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index 3ef38b90fc3a83..d3678706bb736d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -37,26 +37,25 @@
> /*
> * The 2 macros bellow represent the actual size in bytes that
> * those entities occupy in the EEPROM memory.
> - * EEPROM_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record)
> which
> + * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
> * uses uint64 to store 6b fields such as retired_page.
> */
> -#define EEPROM_TABLE_HEADER_SIZE 20
> -#define EEPROM_TABLE_RECORD_SIZE 24
> -
> -#define EEPROM_ADDRESS_SIZE 0x2
> +#define RAS_TABLE_HEADER_SIZE 20
> +#define RAS_TABLE_RECORD_SIZE 24
>
> /* Table hdr is 'AMDR' */
> -#define EEPROM_TABLE_HDR_VAL 0x414d4452
> -#define EEPROM_TABLE_VER 0x0001
> +#define RAS_TABLE_HDR_VAL 0x414d4452
> +#define RAS_TABLE_VER 0x0001
>
> /* Bad GPU tag ‘BADG’ */
> -#define EEPROM_TABLE_HDR_BAD 0x42414447
> +#define RAS_TABLE_HDR_BAD 0x42414447
>
> -/* Assume 2-Mbit size */
> -#define EEPROM_SIZE_BYTES (256 * 1024)
> -#define EEPROM_HDR_START0
> -#define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE)
> -#define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES -
> EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE)
> +/* Assume 2-Mbit size EEPROM and take up the whole space. */
> +#define RAS_TBL_SIZE_BYTES (256 * 1024)
> +#define RAS_HDR_START 0
> +#define RAS_RECORD_START(RAS_HDR_START + RAS_TABLE_HEADER_SIZE)
> +#define RAS_MAX_RECORD_NUM ((RAS_TBL_SIZE_BYTES -
> RAS_TABLE_HEADER_SIZE) \
> +/ RAS_TABLE_RECORD_SIZE)
>
> #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras,
> eeprom_control))->adev
>
> @@ -153,8 +152,8 @@ static int __update_table_header(struct
> amdgpu_ras_eeprom_control *control,
> /* i2c may be unstable in gpu reset */
> down_read(>reset_sem);
> ret = amdgpu_eeprom_xfer(>pm.smu_i2c,
> -control->i2c_address + EEPROM_HDR_START,
> -buff, EEPROM_TABLE_HEADER_SIZE, false);
> +control->i2c_address + RAS_HDR_START,
> +buff, RAS_TABLE_HEADER_SIZE, false);
> up_read(>reset_sem);
>
> if (ret < 1)
> @@ -236,11 +235,11 @@ static int amdgpu_ras_eeprom_correct_header_tag(
> struct amdgpu_ras_eeprom_control *control,
> uint32_t header)
> {
> - unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE];
> + unsigned char buff[RAS_TABLE_HEADER_SIZE];
> struct amdgpu_ras_eeprom_table_header *hdr = >tbl_hdr;
> int ret = 0;
>
> - memset(buff, 0, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE);
> + memset(buff, 0, RAS_TABLE_HEADER_SIZE);
>
> mutex_lock(>tbl_mutex);
> hdr->header = header;
> @@ -252,20 +251,20 @@ static int amdgpu_ras_eeprom_correct_header_tag(
>
> int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
> {
> - unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] =
> { 0 };
> + unsigned char buff[RAS_TABLE_HEADER_SIZE] = { 0 };
> struct amdgpu_ras_eeprom_table_header *hdr = >tbl_hdr;
> int ret = 0;
>
> mutex_lock(>tbl_mutex);
>
> - hdr->header = EEPROM_TABLE_HDR_VAL;
> - hdr->version = EEPROM_TABLE_VER;
> - hdr->first_rec_offset = EEPROM_RECORD_START;
> - hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
> + hdr->header = RAS_TABLE_HDR_VAL;
> + hdr->version = RAS_TABLE_VER;
> + hdr->first_rec_offset = RAS_RECORD_START;
> + hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
>
> control->tbl_byte_sum = 0;
> __update_tbl_checksum(control, NULL, 0, 0);
> - control->next_addr = EEPROM_RECORD_START;
> + control->next_addr = RAS_RECORD_START;
Re: [PATCH 24/40] drm/amdgpu: I2C class is HWMON
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote: > > Set the auto-discoverable class of I2C bus to > HWMON. Remove SPD. > > Cc: Jean Delvare > Cc: Alexander Deucher > Cc: Andrey Grodzovsky > Cc: Lijo Lazar > Cc: Stanley Yang > Cc: Hawking Zhang > Signed-off-by: Luben Tuikov Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 2 +- > drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +- > drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- > drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- > 4 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c > b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c > index b8d6d308fb06a0..e403ba556e5590 100644 > --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c > +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c > @@ -667,7 +667,7 @@ int smu_v11_0_i2c_control_init(struct i2c_adapter > *control) > > mutex_init(>pm.smu_i2c_mutex); > control->owner = THIS_MODULE; > - control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON; > + control->class = I2C_CLASS_HWMON; > control->dev.parent = >pdev->dev; > control->algo = _v11_0_i2c_algo; > snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > index c2d6d7c8129593..974740ac72fded 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > @@ -2016,7 +2016,7 @@ static int arcturus_i2c_control_init(struct smu_context > *smu, struct i2c_adapter > int res; > > control->owner = THIS_MODULE; > - control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON; > + control->class = I2C_CLASS_HWMON; > control->dev.parent = >pdev->dev; > control->algo = _i2c_algo; > control->quirks = _i2c_control_quirks; > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > index 56000463f64e45..8ab06fa87edb04 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > @@ -2810,7 +2810,7 @@ static int navi10_i2c_control_init(struct smu_context > *smu, struct i2c_adapter * > int res; > > control->owner = THIS_MODULE; > - control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON; > + control->class = I2C_CLASS_HWMON; > control->dev.parent = >pdev->dev; > control->algo = _i2c_algo; > snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > index 86804f3b0a951b..91614ae186f7f5 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > @@ -3498,7 +3498,7 @@ static int sienna_cichlid_i2c_control_init(struct > smu_context *smu, struct i2c_a > int res; > > control->owner = THIS_MODULE; > - control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON; > + control->class = I2C_CLASS_HWMON; > control->dev.parent = >pdev->dev; > control->algo = _cichlid_i2c_algo; > snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); > -- > 2.32.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 23/40] drm/amdgpu: Fix wrap-around bugs in RAS
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> Fix the size of the EEPROM from 256000 bytes
> to 262144 bytes (256 KiB).
>
> Fix a couple or wrap around bugs. If a valid
> value/address is 0 <= addr < size, the inverse of
> this inequality (barring negative values which
> make no sense here) is addr >= size. Fix this in
> the RAS code.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 20 +--
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index f316fb11b16d9e..3ef38b90fc3a83 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -52,12 +52,11 @@
> /* Bad GPU tag ‘BADG’ */
> #define EEPROM_TABLE_HDR_BAD 0x42414447
>
> -/* Assume 2 Mbit size */
> -#define EEPROM_SIZE_BYTES 256000
> -#define EEPROM_PAGE__SIZE_BYTES 256
> -#define EEPROM_HDR_START 0
> -#define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE)
> -#define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES -
> EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE)
> +/* Assume 2-Mbit size */
> +#define EEPROM_SIZE_BYTES (256 * 1024)
> +#define EEPROM_HDR_START0
> +#define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE)
> +#define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES -
> EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE)
>
> #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras,
> eeprom_control))->adev
>
> @@ -402,9 +401,8 @@ static uint32_t __correct_eeprom_dest_address(uint32_t
> curr_address)
> uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE;
>
> /* When all EEPROM memory used jump back to 0 address */
> - if (next_address > EEPROM_SIZE_BYTES) {
> - DRM_INFO("Reached end of EEPROM memory, jumping to 0 "
> -"and overriding old record");
> + if (next_address >= EEPROM_SIZE_BYTES) {
> + DRM_INFO("Reached end of EEPROM memory, wrap around to 0.");
> return EEPROM_RECORD_START;
> }
>
> @@ -476,7 +474,9 @@ int amdgpu_ras_eeprom_process_recods(struct
> amdgpu_ras_eeprom_control *control,
> }
>
> /* In case of overflow just start from beginning to not lose newest
> records */
> - if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num >
> EEPROM_SIZE_BYTES))
> + if (write &&
> + (control->next_addr +
> +EEPROM_TABLE_RECORD_SIZE * num >= EEPROM_SIZE_BYTES))
> control->next_addr = EEPROM_RECORD_START;
>
> /*
> --
> 2.32.0
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 22/40] drm/amdgpu: RAS and FRU now use 19-bit I2C address
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> Convert RAS and FRU code to use the 19-bit I2C
> memory address and remove all "slave_addr", as
> this is now absolved into the 19-bit address.
>
> Cc: Jean Delvare
> Cc: John Clements
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 19 ++---
> .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 82 +++
> .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h| 2 +-
> 3 files changed, 39 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> index 2b854bc6ae34bb..69b9559f840ac3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> @@ -29,8 +29,8 @@
> #include "amdgpu_fru_eeprom.h"
> #include "amdgpu_eeprom.h"
>
> -#define I2C_PRODUCT_INFO_ADDR 0x56
> -#define I2C_PRODUCT_INFO_OFFSET0xC0
> +#define FRU_EEPROM_MADDR0x6
> +#define I2C_PRODUCT_INFO_OFFSET 0xC0
>
> static bool is_fru_eeprom_supported(struct amdgpu_device *adev)
> {
> @@ -62,12 +62,11 @@ static bool is_fru_eeprom_supported(struct amdgpu_device
> *adev)
> }
>
> static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t
> addrptr,
> - unsigned char *buff)
> + unsigned char *buff)
> {
> int ret, size;
>
> - ret = amdgpu_eeprom_xfer(>pm.smu_i2c, I2C_PRODUCT_INFO_ADDR,
> -addrptr, buff, 1, true);
> + ret = amdgpu_eeprom_xfer(>pm.smu_i2c, addrptr, buff, 1, true);
> if (ret < 1) {
> DRM_WARN("FRU: Failed to get size field");
> return ret;
> @@ -78,8 +77,8 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device
> *adev, uint32_t addrptr,
> */
> size = buff[0] - I2C_PRODUCT_INFO_OFFSET;
>
> - ret = amdgpu_eeprom_xfer(>pm.smu_i2c, I2C_PRODUCT_INFO_ADDR,
> -addrptr + 1, buff, size, true);
> + ret = amdgpu_eeprom_xfer(>pm.smu_i2c, addrptr + 1, buff, size,
> +true);
> if (ret < 1) {
> DRM_WARN("FRU: Failed to get data field");
> return ret;
> @@ -91,8 +90,8 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device
> *adev, uint32_t addrptr,
> int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
> {
> unsigned char buff[34];
> - int addrptr, size;
> - int len;
> + u32 addrptr;
> + int size, len;
>
> if (!is_fru_eeprom_supported(adev))
> return 0;
> @@ -115,7 +114,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device
> *adev)
> * Bytes 8-a are all 1-byte and refer to the size of the entire
> struct,
> * and the language field, so just start from 0xb, manufacturer size
> */
> - addrptr = 0xb;
> + addrptr = FRU_EEPROM_MADDR + 0xb;
> size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
> if (size < 1) {
> DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", size);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index 2b981e96ce5b9e..f316fb11b16d9e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -28,11 +28,11 @@
> #include "atom.h"
> #include "amdgpu_eeprom.h"
>
> -#define EEPROM_I2C_TARGET_ADDR_VEGA20 0x50
> -#define EEPROM_I2C_TARGET_ADDR_ARCTURUS0x54
> -#define EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342 0x50
> -#define EEPROM_I2C_TARGET_ADDR_SIENNA_CICHLID 0x50
> -#define EEPROM_I2C_TARGET_ADDR_ALDEBARAN0x50
> +#define EEPROM_I2C_MADDR_VEGA20 0x0
> +#define EEPROM_I2C_MADDR_ARCTURUS 0x4
> +#define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0
> +#define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0
> +#define EEPROM_I2C_MADDR_ALDEBARAN 0x0
>
> /*
> * The 2 macros bellow represent the actual size in bytes that
> @@ -58,7 +58,6 @@
> #define EEPROM_HDR_START 0
> #define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE)
> #define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES -
> EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE)
> -#define EEPROM_ADDR_MSB_MASK GENMASK(17, 8)
>
> #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras,
> eeprom_control))->adev
>
> @@ -74,43 +73,43 @@ static bool __is_ras_eeprom_supported(struct
> amdgpu_device *adev)
> }
>
> static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
> - uint16_t *i2c_addr)
> + struct amdgpu_ras_eeprom_control
> *control)
> {
> struct
Re: [PATCH 21/40] drm/amdgpu: I2C EEPROM full memory addressing
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote: > > * "eeprom_addr" is now 32-bit wide. > * Remove "slave_addr" from the I2C EEPROM driver > interface. The I2C EEPROM Device Type Identifier > is fixed at 1010b, and the rest of the bits > of the Device Address Byte/Device Select Code, > are memory address bits, where the first three > of those bits are the hardware selection bits. > All this is now a 19-bit address and passed > as "eeprom_addr". This abstracts the I2C bus > for EEPROM devices for this I2C EEPROM driver. > Now clients only pass the 19-bit EEPROM memory > address, to the I2C EEPROM driver, as the 32-bit > "eeprom_addr", from which they want to read from > or write to. > > Cc: Jean Delvare > Cc: Alexander Deucher > Cc: Andrey Grodzovsky > Cc: Lijo Lazar > Cc: Stanley Yang > Cc: Hawking Zhang > Signed-off-by: Luben Tuikov Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c | 88 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h | 4 +- > 2 files changed, 72 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c > index 94aeda1c7f8ca0..a5a87affedabf1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c > @@ -24,7 +24,7 @@ > #include "amdgpu_eeprom.h" > #include "amdgpu.h" > > -/* AT24CM02 has a 256-byte write page size. > +/* AT24CM02 and M24M02-R have a 256-byte write page size. > */ > #define EEPROM_PAGE_BITS 8 > #define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS) > @@ -32,20 +32,72 @@ > > #define EEPROM_OFFSET_SIZE 2 > > -static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, > - u16 slave_addr, u16 eeprom_addr, > +/* EEPROM memory addresses are 19-bits long, which can > + * be partitioned into 3, 8, 8 bits, for a total of 19. > + * The upper 3 bits are sent as part of the 7-bit > + * "Device Type Identifier"--an I2C concept, which for EEPROM devices > + * is hard-coded as 1010b, indicating that it is an EEPROM > + * device--this is the wire format, followed by the upper > + * 3 bits of the 19-bit address, followed by the direction, > + * followed by two bytes holding the rest of the 16-bits of > + * the EEPROM memory address. The format on the wire for EEPROM > + * devices is: 1010XYZD, A15:A8, A7:A0, > + * Where D is the direction and sequenced out by the hardware. > + * Bits XYZ are memory address bits 18, 17 and 16. > + * These bits are compared to how pins 1-3 of the part are connected, > + * depending on the size of the part, more on that later. > + * > + * Note that of this wire format, a client is in control > + * of, and needs to specify only XYZ, A15:A8, A7:0, bits, > + * which is exactly the EEPROM memory address, or offset, > + * in order to address up to 8 EEPROM devices on the I2C bus. > + * > + * For instance, a 2-Mbit I2C EEPROM part, addresses all its bytes, > + * using an 18-bit address, bit 17 to 0 and thus would use all but one bit of > + * the 19 bits previously mentioned. The designer would then not connect > + * pins 1 and 2, and pin 3 usually named "A_2" or "E2", would be connected to > + * either Vcc or GND. This would allow for up to two 2-Mbit parts on > + * the same bus, where one would be addressable with bit 18 as 1, and > + * the other with bit 18 of the address as 0. > + * > + * For a 2-Mbit part, bit 18 is usually known as the "Chip Enable" or > + * "Hardware Address Bit". This bit is compared to the load on pin 3 > + * of the device, described above, and if there is a match, then this > + * device responds to the command. This way, you can connect two > + * 2-Mbit EEPROM devices on the same bus, but see one contiguous > + * memory from 0 to 7h, where address 0 to 3 is in the device > + * whose pin 3 is connected to GND, and address 4 to 7h is in > + * the 2nd device, whose pin 3 is connected to Vcc. > + * > + * This addressing you encode in the 32-bit "eeprom_addr" below, > + * namely the 19-bits "XYZ,A15:A0", as a single 19-bit address. For > + * instance, eeprom_addr = 0x6DA01, is 110_1101_1010__0001, where > + * XYZ=110b, and A15:A0=DA01h. The XYZ bits become part of the device > + * address, and the rest of the address bits are sent as the memory > + * address bytes. > + * > + * That is, for an I2C EEPROM driver everything is controlled by > + * the "eeprom_addr". > + * > + * P.S. If you need to write, lock and read the Identification Page, > + * (M24M02-DR device only, which we do not use), change the "7" to > + * "0xF" in the macro below, and let the client set bit 20 to 1 in > + * "eeprom_addr", and set A10 to 0 to write into it, and A10 and A1 to > + * 1 to lock it permanently. > + */ > +#define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 7)) > + > +static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 > eeprom_addr, >
Re: [PATCH 19/40] drm/amdgpu: Fixes to the AMDGPU EEPROM driver
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> * When reading from the EEPROM device, there is no
> device limitation on the number of bytes
> read--they're simply sequenced out. Thus, read
> the whole data requested in one go.
>
> * When writing to the EEPROM device, there is a
> 256-byte page limit to write to before having to
> generate a STOP on the bus, as well as the
> address written to mustn't cross over the page
> boundary (it actually rolls over). Maximize the
> data written to per bus acquisition.
>
> * Return the number of bytes read/written, or -errno.
>
> * Add kernel doc.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c | 96 +++---
> 1 file changed, 68 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> index d02ea083a6c69b..7fdb5bd2fc8bc8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> @@ -24,59 +24,99 @@
> #include "amdgpu_eeprom.h"
> #include "amdgpu.h"
>
> -#define EEPROM_OFFSET_LENGTH 2
> +/* AT24CM02 has a 256-byte write page size.
> + */
> +#define EEPROM_PAGE_BITS 8
> +#define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS)
> +#define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1)
> +
> +#define EEPROM_OFFSET_SIZE 2
>
> +/**
> + * amdgpu_eeprom_xfer -- Read/write from/to an I2C EEPROM device
> + * @i2c_adap: pointer to the I2C adapter to use
> + * @slave_addr: I2C address of the slave device
> + * @eeprom_addr: EEPROM address from which to read/write
> + * @eeprom_buf: pointer to data buffer to read into/write from
> + * @buf_size: the size of @eeprom_buf
> + * @read: True if reading from the EEPROM, false if writing
> + *
> + * Returns the number of bytes read/written; -errno on error.
> + */
> int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap,
>u16 slave_addr, u16 eeprom_addr,
> - u8 *eeprom_buf, u16 bytes, bool read)
> + u8 *eeprom_buf, u16 buf_size, bool read)
> {
> - u8 eeprom_offset_buf[2];
> - u16 bytes_transferred;
> + u8 eeprom_offset_buf[EEPROM_OFFSET_SIZE];
> struct i2c_msg msgs[] = {
> {
> .addr = slave_addr,
> .flags = 0,
> - .len = EEPROM_OFFSET_LENGTH,
> + .len = EEPROM_OFFSET_SIZE,
> .buf = eeprom_offset_buf,
> },
> {
> .addr = slave_addr,
> .flags = read ? I2C_M_RD : 0,
> - .len = bytes,
> - .buf = eeprom_buf,
> },
> };
> + const u8 *p = eeprom_buf;
> int r;
> + u16 len;
> +
> + r = 0;
> + for (len = 0; buf_size > 0;
> +buf_size -= len, eeprom_addr += len, eeprom_buf += len) {
> + /* Set the EEPROM address we want to write to/read from.
> +*/
> + msgs[0].buf[0] = (eeprom_addr >> 8) & 0xff;
> + msgs[0].buf[1] = eeprom_addr & 0xff;
>
> - msgs[0].buf[0] = ((eeprom_addr >> 8) & 0xff);
> - msgs[0].buf[1] = (eeprom_addr & 0xff);
> + if (!read) {
> + /* Write the maximum amount of data, without
> +* crossing the device's page boundary, as per
> +* its spec. Partial page writes are allowed,
> +* starting at any location within the page,
> +* so long as the page boundary isn't crossed
> +* over (actually the page pointer rolls
> +* over).
> +*
> +* As per the AT24CM02 EEPROM spec, after
> +* writing into a page, the I2C driver MUST
> +* terminate the transfer, i.e. in
> +* "i2c_transfer()" below, with a STOP
> +* condition, so that the self-timed write
> +* cycle begins. This is implied for the
> +* "i2c_transfer()" abstraction.
> +*/
> + len = min(EEPROM_PAGE_SIZE - (eeprom_addr &
> + EEPROM_PAGE_MASK),
> + (u32)buf_size);
> + } else {
> + /* Reading from the EEPROM has no limitation
> +* on the number of bytes read from the EEPROM
> +* device--they are simply sequenced out.
> +*/
> + len = buf_size;
Re: [PATCH 18/40] drm/amdgpu: Fix Vega20 I2C to be agnostic (v2)
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> Teach Vega20 I2C to be agnostic. Allow addressing
> different devices while the master holds the bus.
> Set STOP as per the controller's specification.
>
> v2: Qualify generating ReSTART before the 1st byte
> of the message, when set by the caller, as
> those functions are separated, as caught by
> Andrey G.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 105 +
> 2 files changed, 69 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> index fe0e9b0c4d5a38..d02ea083a6c69b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
> @@ -41,10 +41,10 @@ int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap,
> },
> {
> .addr = slave_addr,
> - .flags = read ? I2C_M_RD: 0,
> + .flags = read ? I2C_M_RD : 0,
> .len = bytes,
> .buf = eeprom_buf,
> - }
> + },
> };
> int r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> index 5a90d9351b22eb..b8d6d308fb06a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> @@ -41,9 +41,7 @@
> #define I2C_SW_TIMEOUT8
> #define I2C_ABORT 0x10
>
> -/* I2C transaction flags */
> -#define I2C_NO_STOP1
> -#define I2C_RESTART2
> +#define I2C_X_RESTART BIT(31)
>
> #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device,
> pm.smu_i2c))
>
> @@ -205,9 +203,6 @@ static uint32_t smu_v11_0_i2c_poll_rx_status(struct
> i2c_adapter *control)
> return ret;
> }
>
> -
> -
> -
> /**
> * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave
> device.
> *
> @@ -252,21 +247,22 @@ static uint32_t smu_v11_0_i2c_transmit(struct
> i2c_adapter *control,
> reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
> if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
> do {
> - reg = 0;
> - /*
> -* Prepare transaction, no need to set
> RESTART. I2C engine will send
> -* START as soon as it sees data in TXFIFO
> -*/
> - if (bytes_sent == 0)
> - reg = REG_SET_FIELD(reg,
> CKSVII2C_IC_DATA_CMD, RESTART,
> - (i2c_flag &
> I2C_RESTART) ? 1 : 0);
> reg = REG_SET_FIELD(reg,
> CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]);
>
> - /* determine if we need to send STOP bit or
> not */
> - if (numbytes == 1)
> - /* Final transaction, so send stop
> unless I2C_NO_STOP */
> - reg = REG_SET_FIELD(reg,
> CKSVII2C_IC_DATA_CMD, STOP,
> - (i2c_flag &
> I2C_NO_STOP) ? 0 : 1);
> + /* Final message, final byte, must
> +* generate a STOP, to release the
> +* bus, i.e. don't hold SCL low.
> +*/
> + if (numbytes == 1 && i2c_flag & I2C_M_STOP)
> + reg = REG_SET_FIELD(reg,
> +
> CKSVII2C_IC_DATA_CMD,
> + STOP, 1);
> +
> + if (bytes_sent == 0 && i2c_flag &
> I2C_X_RESTART)
> + reg = REG_SET_FIELD(reg,
> +
> CKSVII2C_IC_DATA_CMD,
> + RESTART, 1);
> +
> /* Write */
> reg = REG_SET_FIELD(reg,
> CKSVII2C_IC_DATA_CMD, CMD, 0);
> WREG32_SOC15(SMUIO, 0,
> mmCKSVII2C_IC_DATA_CMD, reg);
> @@ -341,23 +337,21 @@ static uint32_t smu_v11_0_i2c_receive(struct
> i2c_adapter *control,
>
> smu_v11_0_i2c_clear_status(control);
>
> -
> /* Prepare transaction */
> -
> - /* Each time we disable I2C, so this is not a
[PATCH 18/24] drm/amd/display: Rename constant
From: Wesley Chalmers
[WHY]
7 is the minimum number of retries TX must attempt on an AUX DEFER, not
the maximum.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 83d97dfe328f..9d5e09b188c2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -615,7 +615,7 @@ int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
}
#define AUX_MAX_RETRIES 7
-#define AUX_MAX_DEFER_RETRIES 7
+#define AUX_MIN_DEFER_RETRIES 7
#define AUX_MAX_I2C_DEFER_RETRIES 7
#define AUX_MAX_INVALID_REPLY_RETRIES 2
#define AUX_MAX_TIMEOUT_RETRIES 3
@@ -664,7 +664,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
retry_on_defer = true;
fallthrough;
case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
- if (++aux_defer_retries >=
AUX_MAX_DEFER_RETRIES) {
+ if (++aux_defer_retries >=
AUX_MIN_DEFER_RETRIES) {
goto fail;
} else {
if ((*payload->reply ==
AUX_TRANSACTION_REPLY_AUX_DEFER) ||
@@ -701,7 +701,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
// Check whether a DEFER had occurred before the
timeout.
// If so, treat timeout as a DEFER.
if (retry_on_defer) {
- if (++aux_defer_retries >=
AUX_MAX_DEFER_RETRIES)
+ if (++aux_defer_retries >=
AUX_MIN_DEFER_RETRIES)
goto fail;
else if (payload->defer_delay > 0)
msleep(payload->defer_delay);
--
2.25.1
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[PATCH 22/24] drm/amd/display: Add interface to get Calibrated Avg Level from FIFO
From: Wesley Chalmers
[WHY]
Hardware has handed down a new sequence requiring the value of this
register be read from clk_mgr.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Anson Jacob
---
.../display/dc/dcn10/dcn10_stream_encoder.h | 24 +++
.../display/dc/dcn20/dcn20_stream_encoder.c | 12 ++
.../display/dc/dcn20/dcn20_stream_encoder.h | 3 +++
.../dc/dcn30/dcn30_dio_stream_encoder.c | 2 ++
.../dc/dcn30/dcn30_dio_stream_encoder.h | 12 ++
.../amd/display/dc/inc/hw/stream_encoder.h| 3 +++
.../include/asic_reg/dcn/dcn_3_0_1_sh_mask.h | 2 ++
.../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h | 2 ++
8 files changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 76b334644f9e..0d86df97878c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -52,6 +52,7 @@
SRI(AFMT_60958_1, DIG, id), \
SRI(AFMT_60958_2, DIG, id), \
SRI(DIG_FE_CNTL, DIG, id), \
+ SRI(DIG_FIFO_STATUS, DIG, id), \
SRI(HDMI_CONTROL, DIG, id), \
SRI(HDMI_DB_CONTROL, DIG, id), \
SRI(HDMI_GC, DIG, id), \
@@ -124,6 +125,7 @@ struct dcn10_stream_enc_registers {
uint32_t AFMT_60958_2;
uint32_t DIG_FE_CNTL;
uint32_t DIG_FE_CNTL2;
+ uint32_t DIG_FIFO_STATUS;
uint32_t DP_MSE_RATE_CNTL;
uint32_t DP_MSE_RATE_UPDATE;
uint32_t DP_PIXEL_FORMAT;
@@ -266,6 +268,17 @@ struct dcn10_stream_enc_registers {
SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\
+ SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR,
mask_sh),\
@@ -488,6 +501,17 @@ struct dcn10_stream_enc_registers {
type DP_VID_N_MUL;\
type DP_VID_M_DOUBLE_VALUE_EN;\
type DIG_SOURCE_SELECT;\
+ type DIG_FIFO_LEVEL_ERROR;\
+ type DIG_FIFO_USE_OVERWRITE_LEVEL;\
+ type DIG_FIFO_OVERWRITE_LEVEL;\
+ type DIG_FIFO_ERROR_ACK;\
+ type DIG_FIFO_CAL_AVERAGE_LEVEL;\
+ type DIG_FIFO_MAXIMUM_LEVEL;\
+ type DIG_FIFO_MINIMUM_LEVEL;\
+ type DIG_FIFO_READ_CLOCK_SRC;\
+ type DIG_FIFO_CALIBRATED;\
+ type DIG_FIFO_FORCE_RECAL_AVERAGE;\
+ type DIG_FIFO_FORCE_RECOMP_MINMAX;\
type DIG_CLOCK_PATTERN
#define SE_REG_FIELD_LIST_DCN2_0(type) \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 4075ae111530..e6307397e0d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -552,6 +552,17 @@ void enc2_stream_encoder_dp_set_stream_attribute(
DP_SST_SDP_SPLITTING, enable_sdp_splitting);
}
+uint32_t enc2_get_fifo_cal_average_level(
+ struct stream_encoder *enc)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ uint32_t fifo_level;
+
+ REG_GET(DIG_FIFO_STATUS,
+ DIG_FIFO_CAL_AVERAGE_LEVEL, _level);
+ return fifo_level;
+}
+
static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
.dp_set_odm_combine =
enc2_dp_set_odm_combine,
@@ -598,6 +609,7 @@ static const struct stream_encoder_funcs
dcn20_str_enc_funcs = {
.dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet,
.set_dynamic_metadata = enc2_set_dynamic_metadata,
.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+ .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,
};
void dcn20_stream_encoder_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
[PATCH 14/24] drm/amd/display: Set LTTPR Transparent Mode after read link cap
From: Wesley Chalmers
[WHY]
SCR for DP 2.0 Spec states that a DPTX shall put LTTPRs into Transparent
mode after reading LTTPR Capability registers on HPD.
The wording of the SCR is somewhat ambiguous as to whether
Transparent mode must be set explicity, or is implicitly set on LTTPR
capability read. Explicitly setting Transparent mode after LTTPR
capability read should cover all
cases.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 38fabaff51ea..586f05a6cd77 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3705,9 +3705,10 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
link->dpcd_caps.lttpr_caps.max_lane_count <= 4
&&
link->dpcd_caps.lttpr_caps.revision.raw >=
0x14);
- if (is_lttpr_present)
+ if (is_lttpr_present) {
CONN_DATA_DETECT(link, lttpr_dpcd_data,
sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
- else
+ configure_lttpr_mode_transparent(link);
+ } else
link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
}
return is_lttpr_present;
--
2.25.1
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[PATCH 16/24] drm/amd/display: Improve logic for is_lttpr_present
From: Wesley Chalmers [WHY] DP specifies that an LTTPR device is only present if PHY_REPEATER_CNT is 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, or 0x01. All other values should be considered no LTTPRs present. [HOW] Function dp_convert_to_count already does this check. Use it to determine if PHY_REPEATER_CNT is a valid LTTPR count. Signed-off-by: Wesley Chalmers Reviewed-by: Jun Lei Acked-by: Anson Jacob --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index c68b49a14f88..7e52bb3047bc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -3699,8 +3699,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */ - is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 && - link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff && + is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 && link->dpcd_caps.lttpr_caps.max_lane_count > 0 && link->dpcd_caps.lttpr_caps.max_lane_count <= 4 && link->dpcd_caps.lttpr_caps.revision.raw >= 0x14); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/24] drm/amd/display: tune backlight ramping profiles
From: Josip Pavic
[Why & How]
Tune backlight ramping profiles for each Vari-Bright level to suit
customer preferences
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Anson Jacob
---
.../amd/display/modules/power/power_helpers.c | 20 +--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 5e7331be1c0d..2b00f334e93d 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -87,19 +87,19 @@ struct abm_parameters {
};
static const struct abm_parameters abm_settings_config0[abm_defines_max_level]
= {
-// min_red max_red bright_pos dark_pos bright_gain contrast dev
min_knee max_knee blStart blRed
- {0xff, 0xbf,0x20, 0x00, 0xff,0x99, 0xb3, 0x40,
0xe0, 0x, 0x},
- {0xde, 0x85,0x20, 0x00, 0xff,0x90, 0xa8, 0x40,
0xdf, 0x, 0x},
- {0xb0, 0x50,0x20, 0x00, 0xc0,0x88, 0x78, 0x70,
0xa0, 0x, 0x},
- {0x82, 0x40,0x20, 0x00, 0x00,0xff, 0xb3, 0x70,
0x70, 0x, 0x},
+// min_red max_red bright_pos dark_pos bright_gain contrast dev
min_knee max_knee blRedblStart
+ {0xff, 0xbf,0x20, 0x00, 0xff,0x99, 0xb3,
0x40, 0xe0, 0xf777, 0x},
+ {0xde, 0x85,0x20, 0x00, 0xe0,0x90, 0xa8,
0x40, 0xc8, 0xf777, 0x},
+ {0xb0, 0x50,0x20, 0x00, 0xc0,0x88, 0x78,
0x70, 0xa0, 0x, 0x},
+ {0x82, 0x40,0x20, 0x00, 0x00,0xb8, 0xb3,
0x70, 0x70, 0xe333, 0xb333},
};
static const struct abm_parameters abm_settings_config1[abm_defines_max_level]
= {
-// min_red max_red bright_pos dark_pos bright_gain contrast dev
min_knee max_knee blStart blRed
- {0xf0, 0xd9,0x20, 0x00, 0x00,0xff, 0xb3, 0x70,
0x70, 0x, 0x},
- {0xcd, 0xa5,0x20, 0x00, 0x00,0xff, 0xb3, 0x70,
0x70, 0x, 0x},
- {0x99, 0x65,0x20, 0x00, 0x00,0xff, 0xb3, 0x70,
0x70, 0x, 0x},
- {0x82, 0x4d,0x20, 0x00, 0x00,0xff, 0xb3, 0x70,
0x70, 0x, 0x},
+// min_red max_red bright_pos dark_pos bright_gain contrast dev
min_knee max_knee blRed blStart
+ {0xf0, 0xd9,0x20, 0x00, 0x00,0xff, 0xb3,
0x70, 0x70, 0x, 0x},
+ {0xcd, 0xa5,0x20, 0x00, 0x00,0xff, 0xb3,
0x70, 0x70, 0x, 0x},
+ {0x99, 0x65,0x20, 0x00, 0x00,0xff, 0xb3,
0x70, 0x70, 0x, 0x},
+ {0x82, 0x4d,0x20, 0x00, 0x00,0xff, 0xb3,
0x70, 0x70, 0x, 0x},
};
static const struct abm_parameters * const abm_settings[] = {
--
2.25.1
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[PATCH 23/24] drm/amd/display: Cover edge-case when changing DISPCLK WDIVIDER
From: Wesley Chalmers
[WHY]
When changing the DISPCLK_WDIVIDER value from 126 to 127, the change in
clock rate is too great for the FIFOs to handle. This can cause visible
corruption during clock change.
HW has handed down this register sequence to fix the issue.
[HOW]
The sequence, from HW:
a. 127 -> 126
Read DIG_FIFO_CAL_AVERAGE_LEVEL
FIFO level N = DIG_FIFO_CAL_AVERAGE_LEVEL / 4
Set DCCG_FIFO_ERRDET_OVR_EN = 1
Write 1 to OTGx_DROP_PIXEL for (N-4) times
Set DCCG_FIFO_ERRDET_OVR_EN = 0
Write DENTIST_DISPCLK_RDIVIDER = 126
Because of frequency stepping, sequence a can be executed to change the
divider from 127 to any other divider value.
b. 126 -> 127
Read DIG_FIFO_CAL_AVERAGE_LEVEL
FIFO level N = DIG_FIFO_CAL_AVERAGE_LEVEL / 4
Set DCCG_FIFO_ERRDET_OVR_EN = 1
Write 1 to OTGx_ADD_PIXEL for (12-N) times
Set DCCG_FIFO_ERRDET_OVR_EN = 0
Write DENTIST_DISPCLK_RDIVIDER = 127
Because of frequency stepping, divider must first be set from any other
divider value to 126 before executing sequence b.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Anson Jacob
---
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 68 ++-
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h | 3 +-
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 4 +-
3 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 59d17195bc22..9d1db74de36d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -123,7 +123,7 @@ void dcn20_update_clocks_update_dpp_dto(struct
clk_mgr_internal *clk_mgr,
}
}
-void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
+void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr,
struct dc_state *context)
{
int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
* clk_mgr->base.dentist_vco_freq_khz /
clk_mgr->base.clks.dppclk_khz;
@@ -132,6 +132,68 @@ void dcn20_update_clocks_update_dentist(struct
clk_mgr_internal *clk_mgr)
uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
+ uint32_t current_dispclk_wdivider;
+ uint32_t i;
+
+ REG_GET(DENTIST_DISPCLK_CNTL,
+ DENTIST_DISPCLK_WDIVIDER, _dispclk_wdivider);
+
+ /* When changing divider to or from 127, some extra programming is
required to prevent corruption */
+ if (current_dispclk_wdivider == 127 && dispclk_wdivider != 127) {
+ for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count;
i++) {
+ struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[i];
+ uint32_t fifo_level;
+ struct dccg *dccg =
clk_mgr->base.ctx->dc->res_pool->dccg;
+ struct stream_encoder *stream_enc =
pipe_ctx->stream_res.stream_enc;
+ int32_t N;
+ int32_t j;
+
+ if (!pipe_ctx->stream)
+ continue;
+ /* Virtual encoders don't have this function */
+ if (!stream_enc->funcs->get_fifo_cal_average_level)
+ continue;
+ fifo_level =
stream_enc->funcs->get_fifo_cal_average_level(
+ stream_enc);
+ N = fifo_level / 4;
+ dccg->funcs->set_fifo_errdet_ovr_en(
+ dccg,
+ true);
+ for (j = 0; j < N - 4; j++)
+ dccg->funcs->otg_drop_pixel(
+ dccg,
+ pipe_ctx->stream_res.tg->inst);
+ dccg->funcs->set_fifo_errdet_ovr_en(
+ dccg,
+ false);
+ }
+ } else if (dispclk_wdivider == 127 && current_dispclk_wdivider != 127) {
+ REG_UPDATE(DENTIST_DISPCLK_CNTL,
+ DENTIST_DISPCLK_WDIVIDER, 126);
+ REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50,
100);
+ for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count;
i++) {
+ struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[i];
+ struct dccg *dccg =
clk_mgr->base.ctx->dc->res_pool->dccg;
+ struct stream_encoder *stream_enc =
pipe_ctx->stream_res.stream_enc;
+ uint32_t fifo_level;
+ int32_t N;
+ int32_t j;
+
+ if (!pipe_ctx->stream)
+
[PATCH 21/24] drm/amd/display: Partition DPCD address space and break up transactions
From: Wesley Chalmers
[WHY]
SCR for DP 2.0 spec says that multiple LTTPRs must not be accessed in a
single AUX transaction.
There may be other places in future where breaking up AUX accesses is
necessary.
[HOW]
Partition the entire DPCD address space into blocks. When an incoming AUX
request spans multiple blocks, break up the request into multiple requests.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
.../drm/amd/display/dc/core/dc_link_dpcd.c| 87 ++-
include/drm/drm_dp_helper.h | 17
2 files changed, 102 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
index 8957565f87bc..27ec1e6e9c43 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
@@ -43,6 +43,60 @@ static enum dc_status internal_link_write_dpcd(
return DC_OK;
}
+/*
+ * Partition the entire DPCD address space
+ * XXX: This partitioning must cover the entire DPCD address space,
+ * and must contain no gaps or overlapping address ranges.
+ */
+static const struct dpcd_address_range mandatory_dpcd_partitions[] = {
+ { 0, DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1) - 1},
+ { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1),
DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },
+ { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2),
DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3) - 1 },
+ { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3),
DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4) - 1 },
+ { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4),
DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5) - 1 },
+ { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5),
DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6) - 1 },
+ { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6),
DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7) - 1 },
+ { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7),
DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8) - 1 },
+ { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8),
DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },
+ /*
+* The FEC registers are contiguous
+*/
+ { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1),
DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },
+ { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2),
DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },
+ { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3),
DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3) - 1 },
+ { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4),
DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4) - 1 },
+ { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5),
DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5) - 1 },
+ { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6),
DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6) - 1 },
+ { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7),
DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7) - 1 },
+ { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR8), DP_LTTPR_MAX_ADD },
+ /* all remaining DPCD addresses */
+ { DP_LTTPR_MAX_ADD + 1, DP_DPCD_MAX_ADD } };
+
+static inline bool do_addresses_intersect_with_range(
+ const struct dpcd_address_range *range,
+ const uint32_t start_address,
+ const uint32_t end_address)
+{
+ return start_address <= range->end && end_address >= range->start;
+}
+
+static uint32_t dpcd_get_next_partition_size(const uint32_t address, const
uint32_t size)
+{
+ const uint32_t end_address = END_ADDRESS(address, size);
+ uint32_t partition_iterator = 0;
+
+ /*
+* find current partition
+* this loop spins forever if partition map above is not surjective
+*/
+ while
(!do_addresses_intersect_with_range(_dpcd_partitions[partition_iterator],
+ address, end_address))
+ partition_iterator++;
+ if (end_address < mandatory_dpcd_partitions[partition_iterator].end)
+ return size;
+ return ADDRESS_RANGE_SIZE(address,
mandatory_dpcd_partitions[partition_iterator].end);
+}
+
/*
* Ranges of DPCD addresses that must be read in a single transaction
* XXX: Do not allow any two address ranges in this array to overlap
@@ -115,12 +169,28 @@ enum dc_status core_link_read_dpcd(
uint32_t size)
{
uint32_t extended_address;
+ uint32_t partitioned_address;
uint8_t *extended_data;
uint32_t extended_size;
+ /* size of the remaining partitioned address space */
+ uint32_t size_left_to_read;
enum dc_status status;
+ /* size of the next partition to be read from */
+ uint32_t partition_size;
+ uint32_t data_index = 0;
dpcd_extend_address_range(address, data, size, _address,
_data, _size);
- status =
[PATCH 19/24] drm/amd/display: 7 retries + 50 ms timeout on AUX DEFER
From: Wesley Chalmers
[WHY]
DP 2.0 SCR specifies that TX devices must retry at least 7 times when
receiving an AUX DEFER reply from RX. In addition, the specification
states that the TX shall not retry indefinitely, and gives a suggestive
timeout interval of 50ms.
[HOW]
Keep retrying until both 7 or more retries have been made, and the 50ms
interval has passed.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 9d5e09b188c2..49cb4e6d6411 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -616,6 +616,7 @@ int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
#define AUX_MAX_RETRIES 7
#define AUX_MIN_DEFER_RETRIES 7
+#define AUX_MAX_DEFER_TIMEOUT_MS 50
#define AUX_MAX_I2C_DEFER_RETRIES 7
#define AUX_MAX_INVALID_REPLY_RETRIES 2
#define AUX_MAX_TIMEOUT_RETRIES 3
@@ -628,6 +629,10 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
bool payload_reply = true;
enum aux_return_code_type operation_result;
bool retry_on_defer = false;
+ struct ddc *ddc_pin = ddc->ddc_pin;
+ struct dce_aux *aux_engine =
ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+ struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
+ uint32_t defer_time_in_ms = 0;
int aux_ack_retries = 0,
aux_defer_retries = 0,
@@ -660,19 +665,26 @@ bool dce_aux_transfer_with_retries(struct ddc_service
*ddc,
break;
case AUX_TRANSACTION_REPLY_AUX_DEFER:
+ /* polling_timeout_period is in us */
+ defer_time_in_ms +=
aux110->polling_timeout_period / 1000;
+ /* fall through */
case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
retry_on_defer = true;
fallthrough;
case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
- if (++aux_defer_retries >=
AUX_MIN_DEFER_RETRIES) {
+ if (++aux_defer_retries >= AUX_MIN_DEFER_RETRIES
+ && defer_time_in_ms >=
AUX_MAX_DEFER_TIMEOUT_MS) {
goto fail;
} else {
if ((*payload->reply ==
AUX_TRANSACTION_REPLY_AUX_DEFER) ||
(*payload->reply ==
AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
- if (payload->defer_delay > 1)
+ if (payload->defer_delay > 1) {
msleep(payload->defer_delay);
- else if (payload->defer_delay
<= 1)
+ defer_time_in_ms +=
payload->defer_delay;
+ } else if (payload->defer_delay
<= 1) {
udelay(payload->defer_delay * 1000);
+ defer_time_in_ms +=
payload->defer_delay;
+ }
}
}
break;
--
2.25.1
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[PATCH 17/24] drm/amd/display: Enforce DPCD Address ranges
From: Wesley Chalmers
[WHY]
Some DPCD addresses, notably LTTPR Capability registers, are expected to
be read all together in a single DPCD transaction. Rather than force callers to
read registers they don't need, we want to quietly extend the addresses
read, and only return back the values the caller asked for.
This does not affect DPCD writes.
[HOW]
Create an additional layer above AUX to perform 'checked' DPCD
transactions.
Iterate through an array of DPCD address ranges that are marked as being
contiguous. If a requested read falls within one of those ranges, extend
the read to include the entire range.
After DPCD has been queried, copy the requested bytes into the caller's
data buffer, and deallocate all resources used.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/Makefile | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +
.../drm/amd/display/dc/core/dc_link_dpcd.c| 135 ++
.../drm/amd/display/dc/core/dc_link_hwss.c| 31 +---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 +
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 1 +
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 1 +
.../gpu/drm/amd/display/dc/hdcp/hdcp_msg.c| 1 +
.../gpu/drm/amd/display/dc/inc/link_dpcd.h| 18 +++
.../gpu/drm/amd/display/dc/inc/link_hwss.h| 14 --
11 files changed, 162 insertions(+), 45 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
b/drivers/gpu/drm/amd/display/dc/Makefile
index 95aca9b0ef7f..34fc36e77595 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -60,7 +60,7 @@ include $(AMD_DC)
DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o
dc_sink.o \
dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
-dc_link_enc_cfg.o
+dc_link_enc_cfg.o dc_link_dpcd.o
ifdef CONFIG_DRM_AMD_DC_DCN
DISPLAY_CORE += dc_vm_helper.o
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 05c963a5b789..9058e45add92 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -49,6 +49,7 @@
#include "dmub/dmub_srv.h"
#include "inc/hw/panel_cntl.h"
#include "inc/link_enc_cfg.h"
+#include "inc/link_dpcd.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 7e52bb3047bc..1b28b4a40f62 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -25,6 +25,8 @@ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
link->ctx->logger
#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+#include "link_dpcd.h"
+
/* maximum pre emphasis level allowed for each voltage swing level*/
static const enum dc_pre_emphasis
voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
new file mode 100644
index ..8957565f87bc
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
@@ -0,0 +1,135 @@
+#include
+#include
+#include
+#include
+#include "drm/drm_dp_helper.h"
+#include
+#include "dm_helpers.h"
+
+#define END_ADDRESS(start, size) (start + size - 1)
+#define ADDRESS_RANGE_SIZE(start, end) (end - start + 1)
+struct dpcd_address_range {
+ uint32_t start;
+ uint32_t end;
+};
+
+static enum dc_status internal_link_read_dpcd(
+ struct dc_link *link,
+ uint32_t address,
+ uint8_t *data,
+ uint32_t size)
+{
+ if (!link->aux_access_disabled &&
+ !dm_helpers_dp_read_dpcd(link->ctx,
+ link, address, data, size)) {
+ return DC_ERROR_UNEXPECTED;
+ }
+
+ return DC_OK;
+}
+
+static enum dc_status internal_link_write_dpcd(
+ struct dc_link *link,
+ uint32_t address,
+ const uint8_t *data,
+ uint32_t size)
+{
+ if (!link->aux_access_disabled &&
+ !dm_helpers_dp_write_dpcd(link->ctx,
+ link, address, data, size)) {
+ return DC_ERROR_UNEXPECTED;
+ }
+
+ return DC_OK;
+}
+
+/*
+ * Ranges of DPCD addresses that must be read in a single transaction
+ * XXX: Do not allow any two address ranges in this array to overlap
+ */
+static const struct dpcd_address_range mandatory_dpcd_blocks[] = {
+ { DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT }};
+
+/*
+ * extend addresses to read all mandatory blocks
[PATCH 24/24] drm/amd/display: Extend AUX timeout for DP initial reads
From: Wesley Chalmers
[WHY]
DP LL Compliance tests require that the first DPCD transactions after a
hotplug have a timeout interval of 3.2 ms. In cases where LTTPR is
disabled, this means that the first reads from DP_SET_POWER and DP_DPCD_REV
must have an extended
timeout.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 1b28b4a40f62..5ecbe525b676 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3750,9 +3750,6 @@ static bool retrieve_link_cap(struct dc_link *link)
LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
is_lttpr_present = dp_retrieve_lttpr_cap(link);
- if (!is_lttpr_present)
- dc_link_aux_try_to_configure_timeout(link->ddc,
LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
-
status = core_link_read_dpcd(link, DP_SET_POWER,
_power_state, sizeof(dpcd_power_state));
@@ -3781,12 +3778,14 @@ static bool retrieve_link_cap(struct dc_link *link)
break;
}
-
if (status != DC_OK) {
dm_error("%s: Read receiver caps dpcd data failed.\n",
__func__);
return false;
}
+ if (!is_lttpr_present)
+ dc_link_aux_try_to_configure_timeout(link->ddc,
LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
+
{
union training_aux_rd_interval aux_rd_interval;
--
2.25.1
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[PATCH 11/24] drm/amd/display: Read LTTPR caps first on hotplug
From: Wesley Chalmers
[WHY]
A new SCR for the DP2.0 spec requires that LTTPR caps be the first thing
read from DPCD upon hotplug.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 65 ++-
1 file changed, 33 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 7024589791fe..0e2741cd5f26 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3660,38 +3660,6 @@ static bool retrieve_link_cap(struct dc_link *link)
dc_link_aux_try_to_configure_timeout(link->ddc,
LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
- status = core_link_read_dpcd(link, DP_SET_POWER,
- _power_state, sizeof(dpcd_power_state));
-
- /* Delay 1 ms if AUX CH is in power down state. Based on spec
-* section 2.3.1.2, if AUX CH may be powered down due to
-* write to DPCD 600h = 2. Sink AUX CH is monitoring differential
-* signal and may need up to 1 ms before being able to reply.
-*/
- if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
- udelay(1000);
-
- dpcd_set_source_specific_data(link);
- /* Sink may need to configure internals based on vendor, so allow some
-* time before proceeding with possibly vendor specific transactions
-*/
- msleep(post_oui_delay);
-
- for (i = 0; i < read_dpcd_retry_cnt; i++) {
- status = core_link_read_dpcd(
- link,
- DP_DPCD_REV,
- dpcd_data,
- sizeof(dpcd_data));
- if (status == DC_OK)
- break;
- }
-
- if (status != DC_OK) {
- dm_error("%s: Read dpcd data failed.\n", __func__);
- return false;
- }
-
/* Query BIOS to determine if LTTPR functionality is forced on by
system */
if (bios->funcs->get_lttpr_caps) {
enum bp_result bp_query_result;
@@ -3778,6 +3746,39 @@ static bool retrieve_link_cap(struct dc_link *link)
dc_link_aux_try_to_configure_timeout(link->ddc,
LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
+ status = core_link_read_dpcd(link, DP_SET_POWER,
+ _power_state, sizeof(dpcd_power_state));
+
+ /* Delay 1 ms if AUX CH is in power down state. Based on spec
+* section 2.3.1.2, if AUX CH may be powered down due to
+* write to DPCD 600h = 2. Sink AUX CH is monitoring differential
+* signal and may need up to 1 ms before being able to reply.
+*/
+ if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
+ udelay(1000);
+
+ dpcd_set_source_specific_data(link);
+ /* Sink may need to configure internals based on vendor, so allow some
+* time before proceeding with possibly vendor specific transactions
+*/
+ msleep(post_oui_delay);
+
+ for (i = 0; i < read_dpcd_retry_cnt; i++) {
+ status = core_link_read_dpcd(
+ link,
+ DP_DPCD_REV,
+ dpcd_data,
+ sizeof(dpcd_data));
+ if (status == DC_OK)
+ break;
+ }
+
+
+ if (status != DC_OK) {
+ dm_error("%s: Read receiver caps dpcd data failed.\n",
__func__);
+ return false;
+ }
+
{
union training_aux_rd_interval aux_rd_interval;
--
2.25.1
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[PATCH 03/24] drm/amd/display: add config option for eDP hotplug detection
From: Yi-Ling Chen
[Why]
Some custom platforms use eDP hotplug events to notify panel
capability changes that should be reported
[How]
Add a DC config option that unblocks eDP hotplug events
Signed-off-by: Yi-Ling Chen
Reviewed-by: Aric Cyr
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 10 ++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 0f91280883a6..33e83c033284 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -904,9 +904,10 @@ static bool dc_link_detect_helper(struct dc_link *link,
if (dc_is_virtual_signal(link->connector_signal))
return false;
- if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
-link->connector_signal == SIGNAL_TYPE_EDP) &&
- link->local_sink) {
+ if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
+ link->connector_signal == SIGNAL_TYPE_EDP) &&
+ (!link->dc->config.allow_edp_hotplug_detection)) &&
+ link->local_sink) {
// need to re-write OUI and brightness in resume case
if (link->connector_signal == SIGNAL_TYPE_EDP) {
dpcd_set_source_specific_data(link);
@@ -1501,7 +1502,8 @@ static bool dc_link_construct(struct dc_link *link,
link->connector_signal = SIGNAL_TYPE_EDP;
if (link->hpd_gpio) {
- link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
+ if (!link->dc->config.allow_edp_hotplug_detection)
+ link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
link->irq_source_hpd_rx =
dal_irq_get_rx_source(link->hpd_gpio);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index a70697898025..6470eee8e212 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -303,6 +303,7 @@ struct dc_config {
bool multi_mon_pp_mclk_switch;
bool disable_dmcu;
bool enable_4to1MPC;
+ bool allow_edp_hotplug_detection;
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool clamp_min_dcfclk;
#endif
--
2.25.1
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[PATCH 10/24] drm/amd/display: move psr dm interface to separate files
From: Roman Li
[Why]
Improve the maintain/read abilities of dm code.
[How]
Create amdgpu_dm_psr.c/h files.
Move psr function from amdgpu_dm.c
Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauskas
Acked-by: Anson Jacob
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile| 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 137 +--
.../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 166 ++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h | 37
4 files changed, 205 insertions(+), 137 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
index 9a3b7bf8ab0b..91fb72c96545 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
@@ -28,7 +28,7 @@
AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o amdgpu_dm_color.o
ifneq ($(CONFIG_DRM_AMD_DC),)
-AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o
+AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o
amdgpu_dm_psr.o
endif
ifdef CONFIG_DRM_AMD_DC_HDCP
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c0a3119982b0..03b4ac4bf9ba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -58,6 +58,7 @@
#if defined(CONFIG_DEBUG_FS)
#include "amdgpu_dm_debugfs.h"
#endif
+#include "amdgpu_dm_psr.h"
#include "ivsrcid/ivsrcid_vislands30.h"
@@ -213,12 +214,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
static void handle_cursor_update(struct drm_plane *plane,
struct drm_plane_state *old_plane_state);
-static void amdgpu_dm_set_psr_caps(struct dc_link *link);
-static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
-static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
-static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
-static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
-
static const struct drm_format_info *
amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
@@ -10826,136 +10821,6 @@ void amdgpu_dm_update_freesync_caps(struct
drm_connector *connector,
freesync_capable);
}
-static void amdgpu_dm_set_psr_caps(struct dc_link *link)
-{
- uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
-
- if (!(link->connector_signal & SIGNAL_TYPE_EDP))
- return;
- if (link->type == dc_connection_none)
- return;
- if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
- dpcd_data, sizeof(dpcd_data))) {
- link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];
-
- if (dpcd_data[0] == 0) {
- link->psr_settings.psr_version =
DC_PSR_VERSION_UNSUPPORTED;
- link->psr_settings.psr_feature_enabled = false;
- } else {
- link->psr_settings.psr_version = DC_PSR_VERSION_1;
- link->psr_settings.psr_feature_enabled = true;
- }
-
- DRM_INFO("PSR support:%d\n",
link->psr_settings.psr_feature_enabled);
- }
-}
-
-/*
- * amdgpu_dm_link_setup_psr() - configure psr link
- * @stream: stream state
- *
- * Return: true if success
- */
-static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
-{
- struct dc_link *link = NULL;
- struct psr_config psr_config = {0};
- struct psr_context psr_context = {0};
- bool ret = false;
-
- if (stream == NULL)
- return false;
-
- link = stream->link;
-
- psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
-
- if (psr_config.psr_version > 0) {
- psr_config.psr_exit_link_training_required = 0x1;
- psr_config.psr_frame_capture_indication_req = 0;
- psr_config.psr_rfb_setup_time = 0x37;
- psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
- psr_config.allow_smu_optimizations = 0x0;
-
- ret = dc_link_setup_psr(link, stream, _config,
_context);
-
- }
- DRM_DEBUG_DRIVER("PSR link: %d\n",
link->psr_settings.psr_feature_enabled);
-
- return ret;
-}
-
-/*
- * amdgpu_dm_psr_enable() - enable psr f/w
- * @stream: stream state
- *
- * Return: true if success
- */
-bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
-{
- struct dc_link *link = stream->link;
- unsigned int vsync_rate_hz = 0;
- struct dc_static_screen_params params = {0};
- /* Calculate number of static frames before generating interrupt to
-* enter PSR.
-
[PATCH 12/24] drm/amd/display: Move LTTPR cap read into its own function
From: Wesley Chalmers
[WHY]
We want LTTPR capabilities to be readable from more places than just
retrieve_link_cap
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 75 ++-
1 file changed, 41 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0e2741cd5f26..38fabaff51ea 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3619,47 +3619,16 @@ static bool dpcd_read_sink_ext_caps(struct dc_link
*link)
return true;
}
-static bool retrieve_link_cap(struct dc_link *link)
+bool dp_retrieve_lttpr_cap(struct dc_link *link)
{
- /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also
DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
-* which means size 16 will be good for both of those DPCD register
block reads
-*/
- uint8_t dpcd_data[16];
uint8_t lttpr_dpcd_data[6];
-
- /*Only need to read 1 byte starting from
DP_DPRX_FEATURE_ENUMERATION_LIST.
-*/
- uint8_t dpcd_dprx_data = '\0';
- uint8_t dpcd_power_state = '\0';
-
- struct dp_device_vendor_id sink_id;
- union down_stream_port_count down_strm_port_count;
- union edp_configuration_cap edp_config_cap;
- union dp_downstream_port_present ds_port = { 0 };
- enum dc_status status = DC_ERROR_UNEXPECTED;
- uint32_t read_dpcd_retry_cnt = 3;
- int i;
- struct dp_sink_hw_fw_revision dp_hw_fw_revision;
- bool is_lttpr_present = false;
- const uint32_t post_oui_delay = 30; // 30ms
bool vbios_lttpr_enable = false;
bool vbios_lttpr_interop = false;
struct dc_bios *bios = link->dc->ctx->dc_bios;
+ enum dc_status status = DC_ERROR_UNEXPECTED;
+ bool is_lttpr_present = false;
- memset(dpcd_data, '\0', sizeof(dpcd_data));
memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
- memset(_strm_port_count,
- '\0', sizeof(union down_stream_port_count));
- memset(_config_cap, '\0',
- sizeof(union edp_configuration_cap));
-
- /* if extended timeout is supported in hardware,
-* default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
-* CTS 4.2.1.1 regression introduced by CTS specs requirement update.
-*/
- dc_link_aux_try_to_configure_timeout(link->ddc,
- LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
-
/* Query BIOS to determine if LTTPR functionality is forced on by
system */
if (bios->funcs->get_lttpr_caps) {
enum bp_result bp_query_result;
@@ -3741,7 +3710,45 @@ static bool retrieve_link_cap(struct dc_link *link)
else
link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
}
+ return is_lttpr_present;
+}
+
+static bool retrieve_link_cap(struct dc_link *link)
+{
+ /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also
DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
+* which means size 16 will be good for both of those DPCD register
block reads
+*/
+ uint8_t dpcd_data[16];
+ /*Only need to read 1 byte starting from
DP_DPRX_FEATURE_ENUMERATION_LIST.
+*/
+ uint8_t dpcd_dprx_data = '\0';
+ uint8_t dpcd_power_state = '\0';
+
+ struct dp_device_vendor_id sink_id;
+ union down_stream_port_count down_strm_port_count;
+ union edp_configuration_cap edp_config_cap;
+ union dp_downstream_port_present ds_port = { 0 };
+ enum dc_status status = DC_ERROR_UNEXPECTED;
+ uint32_t read_dpcd_retry_cnt = 3;
+ int i;
+ struct dp_sink_hw_fw_revision dp_hw_fw_revision;
+ const uint32_t post_oui_delay = 30; // 30ms
+ bool is_lttpr_present = false;
+
+ memset(dpcd_data, '\0', sizeof(dpcd_data));
+ memset(_strm_port_count,
+ '\0', sizeof(union down_stream_port_count));
+ memset(_config_cap, '\0',
+ sizeof(union edp_configuration_cap));
+
+ /* if extended timeout is supported in hardware,
+* default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
+* CTS 4.2.1.1 regression introduced by CTS specs requirement update.
+*/
+ dc_link_aux_try_to_configure_timeout(link->ddc,
+ LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
+ is_lttpr_present = dp_retrieve_lttpr_cap(link);
if (!is_lttpr_present)
dc_link_aux_try_to_configure_timeout(link->ddc,
LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
--
2.25.1
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[PATCH 01/24] drm/amd/display: Remove unnecessary blank lines
From: Dmytro Laktyushkin cleanup Signed-off-by: Dmytro Laktyushkin Reviewed-by: Aric Cyr Acked-by: Anson Jacob --- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index 345d2d409a6e..0ea9b18662e3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -159,7 +159,6 @@ dml_get_pipe_attr_func(refcyc_per_meta_chunk_vblank_l_in_us, mode_lib->vba.TimeP dml_get_pipe_attr_func(refcyc_per_meta_chunk_vblank_c_in_us, mode_lib->vba.TimePerChromaMetaChunkVBlank); dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_l_in_us, mode_lib->vba.TimePerMetaChunkFlip); dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_c_in_us, mode_lib->vba.TimePerChromaMetaChunkFlip); - dml_get_pipe_attr_func(vstartup, mode_lib->vba.VStartup); dml_get_pipe_attr_func(vupdate_offset, mode_lib->vba.VUpdateOffsetPix); dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix); @@ -419,7 +418,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) visited[j] = true; mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes; - mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 1; mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] = (enum scan_direction_class) (src->source_scan); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 02/24] drm/amd/display: add DMUB registers to crash dump diagnostic data.
From: Ashley Thomas
[WHY]
Ability to triage DMCUB is improved with availability of certain
dmub registers not currently captured in crash dump diagnostic data.
[HOW]
Add dmub registers to diagnostic data collection.
Thanks Nicholas Kazlauskas for awesome input on this!
Signed-off-by: Ashley Thomas
Reviewed-by: Nicholas Kazlauskas
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 100 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 4 +
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 29 +
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 65 +++-
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 14 ++-
.../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 5 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn30.c | 5 +-
.../drm/amd/display/dmub/src/dmub_dcn301.c| 5 +-
.../drm/amd/display/dmub/src/dmub_dcn302.c| 5 +-
.../drm/amd/display/dmub/src/dmub_dcn303.c| 5 +-
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 10 ++
11 files changed, 238 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 48ca23e1e599..36b6fbcc0441 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -86,6 +86,7 @@ void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv,
error:
DC_ERROR("Error queuing DMUB command: status=%d\n", status);
+ dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
}
void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv)
@@ -95,8 +96,10 @@ void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv)
enum dmub_status status;
status = dmub_srv_cmd_execute(dmub);
- if (status != DMUB_STATUS_OK)
+ if (status != DMUB_STATUS_OK) {
DC_ERROR("Error starting DMUB execution: status=%d\n", status);
+ dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
+ }
}
void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
@@ -106,8 +109,10 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
enum dmub_status status;
status = dmub_srv_wait_for_idle(dmub, 10);
- if (status != DMUB_STATUS_OK)
+ if (status != DMUB_STATUS_OK) {
DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
+ dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
+ }
}
void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
@@ -214,3 +219,94 @@ void dc_dmub_trace_event_control(struct dc *dc, bool
enable)
{
dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
}
+
+bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct
dmub_diagnostic_data *diag_data)
+{
+ if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data)
+ return false;
+ return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
+}
+
+void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
+{
+ struct dmub_diagnostic_data diag_data = {0};
+
+ if (!dc_dmub_srv || !dc_dmub_srv->dmub) {
+ DC_LOG_ERROR("%s: invalid parameters.", __func__);
+ return;
+ }
+
+ if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, _data)) {
+ DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.",
__func__);
+ return;
+ }
+
+ DC_LOG_DEBUG(
+ "DMCUB STATE\n"
+ "dmcub_version : %08x\n"
+ "scratch [0] : %08x\n"
+ "scratch [1] : %08x\n"
+ "scratch [2] : %08x\n"
+ "scratch [3] : %08x\n"
+ "scratch [4] : %08x\n"
+ "scratch [5] : %08x\n"
+ "scratch [6] : %08x\n"
+ "scratch [7] : %08x\n"
+ "scratch [8] : %08x\n"
+ "scratch [9] : %08x\n"
+ "scratch [10] : %08x\n"
+ "scratch [11] : %08x\n"
+ "scratch [12] : %08x\n"
+ "scratch [13] : %08x\n"
+ "scratch [14] : %08x\n"
+ "scratch [15] : %08x\n"
+ "pc : %08x\n"
+ "unk_fault_addr : %08x\n"
+ "inst_fault_addr: %08x\n"
+ "data_fault_addr: %08x\n"
+ "inbox1_rptr: %08x\n"
+ "inbox1_wptr: %08x\n"
+ "inbox1_size: %08x\n"
+ "inbox0_rptr: %08x\n"
+ "inbox0_wptr: %08x\n"
+ "inbox0_size: %08x\n"
+ "is_enabled : %d\n"
+ "is_soft_reset : %d\n"
+ "is_secure_reset: %d\n"
+
[PATCH 08/24] drm/amd/display: [FW Promotion] Release 0.0.70
From: Anthony Koo Signed-off-by: Anthony Koo Reviewed-by: Anthony Koo Acked-by: Anson Jacob --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index ff1f4ec1531e..18d2f51eb50d 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -47,10 +47,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0xefd666c1 +#define DMUB_FW_VERSION_GIT_HASH 0x5cac099d3 #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 69 +#define DMUB_FW_VERSION_REVISION 70 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/24] drm/amd/display: Updated variable name.
From: David Galiffi
[Why]
Fixed spelling error.
[How]
Changed "currnet_setting" to "current_setting".
Signed-off-by: David Galiffi
Reviewed-by: Wesley Chalmers
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 919c94de2a20..7024589791fe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1806,7 +1806,7 @@ bool perform_link_training_with_retries(
enum dp_panel_mode panel_mode;
struct link_encoder *link_enc;
enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
- struct dc_link_settings currnet_setting = *link_setting;
+ struct dc_link_settings current_setting = *link_setting;
/* Dynamically assigned link encoders associated with stream rather than
* link.
@@ -1832,7 +1832,7 @@ bool perform_link_training_with_retries(
link,
signal,
pipe_ctx->clock_source->id,
- _setting);
+ _setting);
if (stream->sink_patches.dppowerup_delay > 0) {
int delay_dp_power_up_in_ms =
stream->sink_patches.dppowerup_delay;
@@ -1847,12 +1847,12 @@ bool perform_link_training_with_retries(
panel_mode != DP_PANEL_MODE_DEFAULT);
if (link->aux_access_disabled) {
- dc_link_dp_perform_link_training_skip_aux(link,
_setting);
+ dc_link_dp_perform_link_training_skip_aux(link,
_setting);
return true;
} else {
status = dc_link_dp_perform_link_training(
link,
-
_setting,
+
_setting,
skip_video_pattern);
if (status == LINK_TRAINING_SUCCESS)
return true;
@@ -1872,12 +1872,12 @@ bool perform_link_training_with_retries(
if (status == LINK_TRAINING_ABORT)
break;
else if (do_fallback) {
- decide_fallback_link_setting(*link_setting,
_setting, status);
+ decide_fallback_link_setting(*link_setting,
_setting, status);
/* Fail link training if reduced link bandwidth no
longer meets
* stream requirements.
*/
if (dc_bandwidth_in_kbps_from_timing(>timing) <
- dc_link_bandwidth_kbps(link,
_setting))
+ dc_link_bandwidth_kbps(link,
_setting))
break;
}
--
2.25.1
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[PATCH 13/24] drm/amd/display: Read LTTPR caps first on bootup
From: Wesley Chalmers
[WHY]
SCR for DP 2.0 requires that LTTPR caps be read first on hotplug.
For the sake of consistency, this should also be the case on bootup.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 3 +++
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 1 +
3 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 3b175af97388..711ba953a99b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -54,6 +54,7 @@
#include "dce/dmub_hw_lock_mgr.h"
#include "dc_trace.h"
#include "dce/dmub_outbox.h"
+#include "inc/dc_link_dp.h"
#define DC_LOGGER_INIT(logger)
@@ -1403,6 +1404,9 @@ void dcn10_init_hw(struct dc *dc)
if (dc->links[i]->connector_signal !=
SIGNAL_TYPE_DISPLAY_PORT)
continue;
+ /* DP 2.0 requires that LTTPR Caps be read first */
+ dp_retrieve_lttpr_cap(dc->links[i]);
+
/*
* If any of the displays are lit up turn them off.
* The reason is that some MST hubs cannot be turned off
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index ef5d0b778a72..6c88c5f236a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -48,6 +48,7 @@
#include "dc_dmub_srv.h"
#include "link_hwss.h"
#include "dpcd_defs.h"
+#include "inc/dc_link_dp.h"
@@ -529,6 +530,8 @@ void dcn30_init_hw(struct dc *dc)
for (i = 0; i < dc->link_count; i++) {
if (dc->links[i]->connector_signal !=
SIGNAL_TYPE_DISPLAY_PORT)
continue;
+ /* DP 2.0 states that LTTPR regs must be read first */
+ dp_retrieve_lttpr_cap(dc->links[i]);
/* if any of the displays are lit up turn them off */
status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index dd38dd63697f..e2b58ec9912d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -190,4 +190,5 @@ enum dc_status dpcd_configure_lttpr_mode(
struct link_training_settings *lt_settings);
enum dp_link_encoding dp_get_link_encoding_format(const struct
dc_link_settings *link_settings);
+bool dp_retrieve_lttpr_cap(struct dc_link *link);
#endif /* __DC_LINK_DP_H__ */
--
2.25.1
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[PATCH 20/24] drm/amd/display: Do not count I2C DEFERs with AUX DEFERs
From: Wesley Chalmers
[WHY]
DP 2.0 SCR specifies that
"A DPTX shall distinguish I2C_DEFER|AUX_ACK from AUX_DEFER. AUX retries
due to
I2C_DEFER are not counted as part of minimum 7 retires (sic) upon
AUX_DEFER’s"
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 49cb4e6d6411..28631714f697 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -667,12 +667,13 @@ bool dce_aux_transfer_with_retries(struct ddc_service
*ddc,
case AUX_TRANSACTION_REPLY_AUX_DEFER:
/* polling_timeout_period is in us */
defer_time_in_ms +=
aux110->polling_timeout_period / 1000;
+ ++aux_defer_retries;
/* fall through */
case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
retry_on_defer = true;
fallthrough;
case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
- if (++aux_defer_retries >= AUX_MIN_DEFER_RETRIES
+ if (aux_defer_retries >= AUX_MIN_DEFER_RETRIES
&& defer_time_in_ms >=
AUX_MAX_DEFER_TIMEOUT_MS) {
goto fail;
} else {
--
2.25.1
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[PATCH 15/24] drm/amd/display: Always write repeater mode regardless of LTTPR
From: Wesley Chalmers
[WHY]
SCR for DP2.0 requires that LT be performed with PHY_REPEATER_MODE
programmed to 0x55 (Transparent) whenever PHY_REPEATER_CNT is any value
other than 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, or 0x01.
[HOW]
Write Non-Transparent (0xAA) to PHY_REPEATER_MODE when LTTPRs detected and
Non-Transparent is
requested.
Write Transparent in all other cases.
Signed-off-by: Wesley Chalmers
Reviewed-by: Jun Lei
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 586f05a6cd77..c68b49a14f88 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1618,11 +1618,10 @@ enum dc_status dpcd_configure_lttpr_mode(struct dc_link
*link, struct link_train
{
enum dc_status status = DC_OK;
- if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
- status = configure_lttpr_mode_transparent(link);
-
- else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
+ if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
status = configure_lttpr_mode_non_transparent(link,
lt_settings);
+ else
+ status = configure_lttpr_mode_transparent(link);
return status;
}
--
2.25.1
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[PATCH 05/24] drm/amd/display: dp mst detection code refactor
From: Wenjing Liu
[why]
Move mst start top mgr in dc_link_detect layer.
Remove unused same_dpcd variable.
Move PEAK_FACTOR_X1000 and LINK_TRAINING_MAX_VERIFY_RETRY
to the proper header for defining dc link internal constant.
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 156 +++---
.../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 10 +-
2 files changed, 70 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 33e83c033284..05c963a5b789 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -59,20 +59,6 @@
#define RETIMER_REDRIVER_INFO(...) \
DC_LOG_RETIMER_REDRIVER( \
__VA_ARGS__)
-/***
- * Private structures
-
**/
-
-enum {
- PEAK_FACTOR_X1000 = 1006,
- /*
-* Some receivers fail to train on first try and are good
-* on subsequent tries. 2 retries should be plenty. If we
-* don't have a successful training then we don't expect to
-* ever get one.
-*/
- LINK_TRAINING_MAX_VERIFY_RETRY = 2
-};
/***
* Private functions
@@ -718,11 +704,9 @@ static void read_current_link_settings_on_detect(struct
dc_link *link)
static bool detect_dp(struct dc_link *link,
struct display_sink_capability *sink_caps,
- bool *converter_disable_audio,
- struct audio_support *audio_support,
enum dc_detect_reason reason)
{
- bool boot = false;
+ struct audio_support *audio_support =
>dc->res_pool->audio_support;
sink_caps->signal = link_detect_sink(link, reason);
sink_caps->transaction_type =
@@ -745,60 +729,12 @@ static bool detect_dp(struct dc_link *link,
* of this function). */
query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST,
link);
#endif
- /*
-* This call will initiate MST topology discovery. Which
-* will detect MST ports and add new DRM connector DRM
-* framework. Then read EDID via remote i2c over aux. In
-* the end, will notify DRM detect result and save EDID
-* into DRM framework.
-*
-* .detect is called by .fill_modes.
-* .fill_modes is called by user mode ioctl
-* DRM_IOCTL_MODE_GETCONNECTOR.
-*
-* .get_modes is called by .fill_modes.
-*
-* call .get_modes, AMDGPU DM implementation will create
-* new dc_sink and add to dc_link. For long HPD plug
-* in/out, MST has its own handle.
-*
-* Therefore, just after dc_create, link->sink is not
-* created for MST until user mode app calls
-* DRM_IOCTL_MODE_GETCONNECTOR.
-*
-* Need check ->sink usages in case ->sink = NULL
-* TODO: s3 resume check
-*/
- if (reason == DETECT_REASON_BOOT)
- boot = true;
-
- dm_helpers_dp_update_branch_info(link->ctx, link);
-
- if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
-link, boot)) {
- /* MST not supported */
- link->type = dc_connection_single;
- sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
- }
}
if (link->type != dc_connection_mst_branch &&
- is_dp_branch_device(link)) {
+ is_dp_branch_device(link))
/* DP SST branch */
link->type = dc_connection_sst_branch;
- if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
- /*
-* SST branch unplug processing for short irq
-*/
- link_disconnect_sink(link);
- return true;
- }
-
- if (is_dp_active_dongle(link) &&
- (link->dpcd_caps.dongle_type !=
-
[PATCH 09/24] drm/amd/display: 3.2.140
From: Aric Cyr This version brings along following fixed: - LTTPR improvements - Backlight improvements - eDP hotplug detection Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Anson Jacob --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 6470eee8e212..9d924e8496f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.139" +#define DC_VER "3.2.140" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/24] DC Patches June 10, 2021
This DC patchset brings improvements in multiple areas. In summary, we have: * LTTPR improvements * Backlight improvements * eDP hotplug detection *** BLURB HERE *** Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.70 Aric Cyr (1): drm/amd/display: 3.2.140 Ashley Thomas (1): drm/amd/display: add DMUB registers to crash dump diagnostic data. David Galiffi (1): drm/amd/display: Updated variable name. Dmytro Laktyushkin (1): drm/amd/display: Remove unnecessary blank lines Josip Pavic (1): drm/amd/display: tune backlight ramping profiles Po-Ting Chen (1): drm/amd/display: Change swizzle visual confirm reference pipe Roman Li (1): drm/amd/display: move psr dm interface to separate files Wenjing Liu (1): drm/amd/display: dp mst detection code refactor Wesley Chalmers (14): drm/amd/display: Read LTTPR caps first on hotplug drm/amd/display: Move LTTPR cap read into its own function drm/amd/display: Read LTTPR caps first on bootup drm/amd/display: Set LTTPR Transparent Mode after read link cap drm/amd/display: Always write repeater mode regardless of LTTPR drm/amd/display: Improve logic for is_lttpr_present drm/amd/display: Enforce DPCD Address ranges drm/amd/display: Rename constant drm/amd/display: 7 retries + 50 ms timeout on AUX DEFER drm/amd/display: Do not count I2C DEFERs with AUX DEFERs drm/amd/display: Partition DPCD address space and break up transactions drm/amd/display: Add interface to get Calibrated Avg Level from FIFO drm/amd/display: Cover edge-case when changing DISPCLK WDIVIDER drm/amd/display: Extend AUX timeout for DP initial reads Yi-Ling Chen (1): drm/amd/display: add config option for eDP hotplug detection .../gpu/drm/amd/display/amdgpu_dm/Makefile| 2 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 137 +-- .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 166 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h | 37 +++ drivers/gpu/drm/amd/display/dc/Makefile | 2 +- .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 68 +- .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h | 3 +- .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 4 +- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 10 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 167 ++ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 170 +++--- .../drm/amd/display/dc/core/dc_link_dpcd.c| 218 ++ .../drm/amd/display/dc/core/dc_link_hwss.c| 31 +-- drivers/gpu/drm/amd/display/dc/dc.h | 3 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 100 +++- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 4 + drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 23 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 + .../display/dc/dcn10/dcn10_stream_encoder.h | 24 ++ .../display/dc/dcn20/dcn20_stream_encoder.c | 12 + .../display/dc/dcn20/dcn20_stream_encoder.h | 3 + .../dc/dcn30/dcn30_dio_stream_encoder.c | 2 + .../dc/dcn30/dcn30_dio_stream_encoder.h | 12 + .../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 4 + .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 1 + .../drm/amd/display/dc/dml/display_mode_vba.c | 2 - .../gpu/drm/amd/display/dc/hdcp/hdcp_msg.c| 1 + .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 11 +- .../amd/display/dc/inc/hw/stream_encoder.h| 3 + .../gpu/drm/amd/display/dc/inc/link_dpcd.h| 18 ++ .../gpu/drm/amd/display/dc/inc/link_hwss.h| 14 -- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 29 +++ .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 65 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 14 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 5 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn30.c | 5 +- .../drm/amd/display/dmub/src/dmub_dcn301.c| 5 +- .../drm/amd/display/dmub/src/dmub_dcn302.c| 5 +- .../drm/amd/display/dmub/src/dmub_dcn303.c| 5 +- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 10 + .../amd/display/modules/power/power_helpers.c | 20 +- .../include/asic_reg/dcn/dcn_3_0_1_sh_mask.h | 2 + .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h | 2 + include/drm/drm_dp_helper.h | 17 ++ 45 files changed, 1042 insertions(+), 403 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h create mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c create mode 100644 drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 17/40] drm/amdgpu/pm: ADD I2C quirk adapter table
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> From: Andrey Grodzovsky
>
> To be used by kernel clients of the adapter.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Andrey Grodzovsky
> Suggested-by: Lazar Lijo
> Signed-off-by: Luben Tuikov
> Reviewed-by: Luben Tuikov
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 7 +++
> drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 6 ++
> drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 6 ++
> 3 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 409299a608e1b3..c2d6d7c8129593 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -2004,6 +2004,12 @@ static const struct i2c_algorithm arcturus_i2c_algo = {
> .functionality = arcturus_i2c_func,
> };
>
> +
> +static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = {
> + .max_read_len = MAX_SW_I2C_COMMANDS,
> + .max_write_len = MAX_SW_I2C_COMMANDS,
> +};
> +
> static int arcturus_i2c_control_init(struct smu_context *smu, struct
> i2c_adapter *control)
> {
> struct amdgpu_device *adev = to_amdgpu_device(control);
> @@ -2013,6 +2019,7 @@ static int arcturus_i2c_control_init(struct smu_context
> *smu, struct i2c_adapter
> control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON;
> control->dev.parent = >pdev->dev;
> control->algo = _i2c_algo;
> + control->quirks = _i2c_control_quirks;
> snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
>
> res = i2c_add_adapter(control);
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 4010b891f25678..56000463f64e45 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -2799,6 +2799,11 @@ static const struct i2c_algorithm navi10_i2c_algo = {
> .functionality = navi10_i2c_func,
> };
>
> +static const struct i2c_adapter_quirks navi10_i2c_control_quirks = {
> + .max_read_len = MAX_SW_I2C_COMMANDS,
> + .max_write_len = MAX_SW_I2C_COMMANDS,
> +};
> +
> static int navi10_i2c_control_init(struct smu_context *smu, struct
> i2c_adapter *control)
> {
> struct amdgpu_device *adev = to_amdgpu_device(control);
> @@ -2809,6 +2814,7 @@ static int navi10_i2c_control_init(struct smu_context
> *smu, struct i2c_adapter *
> control->dev.parent = >pdev->dev;
> control->algo = _i2c_algo;
> snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
> + control->quirks = _i2c_control_quirks;
>
> res = i2c_add_adapter(control);
> if (res)
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index d5b750d84112fa..86804f3b0a951b 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -3487,6 +3487,11 @@ static const struct i2c_algorithm
> sienna_cichlid_i2c_algo = {
> .functionality = sienna_cichlid_i2c_func,
> };
>
> +static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
> + .max_read_len = MAX_SW_I2C_COMMANDS,
> + .max_write_len = MAX_SW_I2C_COMMANDS,
> +};
> +
> static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct
> i2c_adapter *control)
> {
> struct amdgpu_device *adev = to_amdgpu_device(control);
> @@ -3497,6 +3502,7 @@ static int sienna_cichlid_i2c_control_init(struct
> smu_context *smu, struct i2c_a
> control->dev.parent = >pdev->dev;
> control->algo = _cichlid_i2c_algo;
> snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
> + control->quirks = _cichlid_i2c_control_quirks;
>
> res = i2c_add_adapter(control);
> if (res)
> --
> 2.32.0
>
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Re: [PATCH 16/40] drm/amd/pm: SMU I2C: Return number of messages processed
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> From: Andrey Grodzovsky
>
> Fix from number of processed bytes to number of
> processed I2C messages.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Andrey Grodzovsky
> Signed-off-by: Luben Tuikov
> Reviewed-by: Luben Tuikov
Reviewed-by: Alex Deucher
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 43 +++
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 +++
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 43 +++
> 3 files changed, 75 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 235e83e9f0feb7..409299a608e1b3 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -1913,9 +1913,8 @@ static int arcturus_i2c_xfer(struct i2c_adapter
> *i2c_adap,
> struct smu_table_context *smu_table = >smu.smu_table;
> struct smu_table *table = _table->driver_table;
> SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
> - u16 bytes_to_transfer, remaining_bytes, msg_bytes;
> - u16 available_bytes = MAX_SW_I2C_COMMANDS;
> - int i, j, r, c;
> + short available_bytes = MAX_SW_I2C_COMMANDS;
> + int i, j, r, c, num_done = 0;
> u8 slave;
>
> /* only support a single slave addr per transaction */
> @@ -1923,8 +1922,15 @@ static int arcturus_i2c_xfer(struct i2c_adapter
> *i2c_adap,
> for (i = 0; i < num; i++) {
> if (slave != msgs[i].addr)
> return -EINVAL;
> - bytes_to_transfer += min(msgs[i].len, available_bytes);
> - available_bytes -= bytes_to_transfer;
> +
> + available_bytes -= msgs[i].len;
> + if (available_bytes >= 0) {
> + num_done++;
> + } else {
> + /* This message and all the follwing won't be
> processed */
> + available_bytes += msgs[i].len;
> + break;
> + }
> }
>
> req = kzalloc(sizeof(*req), GFP_KERNEL);
> @@ -1934,24 +1940,28 @@ static int arcturus_i2c_xfer(struct i2c_adapter
> *i2c_adap,
> req->I2CcontrollerPort = 1;
> req->I2CSpeed = I2C_SPEED_FAST_400K;
> req->SlaveAddress = slave << 1; /* 8 bit addresses */
> - req->NumCmds = bytes_to_transfer;
> + req->NumCmds = MAX_SW_I2C_COMMANDS - available_bytes;;
>
> - remaining_bytes = bytes_to_transfer;
> c = 0;
> - for (i = 0; i < num; i++) {
> + for (i = 0; i < num_done; i++) {
> struct i2c_msg *msg = [i];
>
> - msg_bytes = min(msg->len, remaining_bytes);
> - for (j = 0; j < msg_bytes; j++) {
> + for (j = 0; j < msg->len; j++) {
> SwI2cCmd_t *cmd = >SwI2cCmds[c++];
>
> - remaining_bytes--;
> if (!(msg[i].flags & I2C_M_RD)) {
> /* write */
> cmd->CmdConfig |= I2C_CMD_WRITE;
> cmd->RegisterAddr = msg->buf[j];
> }
> - if (!remaining_bytes)
> +
> + /*
> +* Insert STOP if we are at the last byte of either
> last
> +* message for the transaction or the client
> explicitly
> +* requires a STOP at this particular message.
> +*/
> + if ((j == msg->len -1 ) &&
> + ((i == num_done - 1) || (msg[i].flags &
> I2C_M_STOP)))
> cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
>
> if ((j == 0) && !(msg[i].flags & I2C_M_NOSTART))
> @@ -1964,21 +1974,18 @@ static int arcturus_i2c_xfer(struct i2c_adapter
> *i2c_adap,
> if (r)
> goto fail;
>
> - remaining_bytes = bytes_to_transfer;
> c = 0;
> - for (i = 0; i < num; i++) {
> + for (i = 0; i < num_done; i++) {
> struct i2c_msg *msg = [i];
>
> - msg_bytes = min(msg->len, remaining_bytes);
> - for (j = 0; j < msg_bytes; j++) {
> + for (j = 0; j < msg->len; j++) {
> SwI2cCmd_t *cmd = >SwI2cCmds[c++];
>
> - remaining_bytes--;
> if (msg[i].flags & I2C_M_RD)
> msg->buf[j] = cmd->Data;
> }
> }
> - r = bytes_to_transfer;
> + r = num_done;
>
> fail:
> kfree(req);
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>
Re: [PATCH 15/40] drm/amdgpu: Send STOP for the last byte of msg only
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote: > > From: Andrey Grodzovsky > > Let's just ignore the I2C_M_STOP hint from upper > layer for SMU I2C code as there is no clean > mapping between single per I2C message STOP flag > at the kernel I2C layer and the SMU, per each byte > STOP flag. We will just by default set it at the > end of the SMU I2C message. > > Cc: Jean Delvare > Cc: Alexander Deucher > Cc: Andrey Grodzovsky > Cc: Lijo Lazar > Cc: Stanley Yang > Cc: Hawking Zhang > Signed-off-by: Andrey Grodzovsky > Suggested-by: Lazar Lijo > Signed-off-by: Luben Tuikov > Reviewed-by: Luben Tuikov Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 ++-- > drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 ++-- > drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 ++-- > 3 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > index 72b02025b07e06..235e83e9f0feb7 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > @@ -1951,9 +1951,9 @@ static int arcturus_i2c_xfer(struct i2c_adapter > *i2c_adap, > cmd->CmdConfig |= I2C_CMD_WRITE; > cmd->RegisterAddr = msg->buf[j]; > } > - if ((msg[i].flags & I2C_M_STOP) || > - (!remaining_bytes)) > + if (!remaining_bytes) > cmd->CmdConfig |= CMDCONFIG_STOP_MASK; > + > if ((j == 0) && !(msg[i].flags & I2C_M_NOSTART)) > cmd->CmdConfig |= CMDCONFIG_RESTART_BIT; > } > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > index 289d09a5d711b9..b94c5a1d3eb756 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > @@ -2746,9 +2746,9 @@ static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap, > cmd->CmdConfig |= I2C_CMD_WRITE; > cmd->RegisterAddr = msg->buf[j]; > } > - if ((msg[i].flags & I2C_M_STOP) || > - (!remaining_bytes)) > + if (!remaining_bytes) > cmd->CmdConfig |= CMDCONFIG_STOP_MASK; > + > if ((j == 0) && !(msg[i].flags & I2C_M_NOSTART)) > cmd->CmdConfig |= CMDCONFIG_RESTART_BIT; > } > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > index e8e57462ce9d64..2fa667a86c1a54 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > @@ -3434,9 +3434,9 @@ static int sienna_cichlid_i2c_xfer(struct i2c_adapter > *i2c_adap, > cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; > cmd->ReadWriteData = msg->buf[j]; > } > - if ((msg[i].flags & I2C_M_STOP) || > - (!remaining_bytes)) > + if (!remaining_bytes) > cmd->CmdConfig |= CMDCONFIG_STOP_MASK; > + > if ((j == 0) && !(msg[i].flags & I2C_M_NOSTART)) > cmd->CmdConfig |= CMDCONFIG_RESTART_BIT; > } > -- > 2.32.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 14/40] drm/amdgpu: Drop i > 0 restriction for issuing RESTART
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote: > > From: Andrey Grodzovsky Needs a commit message. With that fixed: Acked-by: Alex Deucher > > Cc: Jean Delvare > Cc: Alexander Deucher > Cc: Andrey Grodzovsky > Cc: Lijo Lazar > Cc: Stanley Yang > Cc: Hawking Zhang > Signed-off-by: Andrey Grodzovsky > Signed-off-by: Luben Tuikov > Reviewed-by: Luben Tuikov > --- > drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +- > drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- > drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > index 73e261260b76e6..72b02025b07e06 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c > @@ -1954,7 +1954,7 @@ static int arcturus_i2c_xfer(struct i2c_adapter > *i2c_adap, > if ((msg[i].flags & I2C_M_STOP) || > (!remaining_bytes)) > cmd->CmdConfig |= CMDCONFIG_STOP_MASK; > - if ((i > 0) && (j == 0) && !(msg[i].flags & > I2C_M_NOSTART)) > + if ((j == 0) && !(msg[i].flags & I2C_M_NOSTART)) > cmd->CmdConfig |= CMDCONFIG_RESTART_BIT; > } > } > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > index 5dc48e557c2bad..289d09a5d711b9 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c > @@ -2749,7 +2749,7 @@ static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap, > if ((msg[i].flags & I2C_M_STOP) || > (!remaining_bytes)) > cmd->CmdConfig |= CMDCONFIG_STOP_MASK; > - if ((i > 0) && (j == 0) && !(msg[i].flags & > I2C_M_NOSTART)) > + if ((j == 0) && !(msg[i].flags & I2C_M_NOSTART)) > cmd->CmdConfig |= CMDCONFIG_RESTART_BIT; > } > } > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > index fdbc54622dbfbf..e8e57462ce9d64 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > @@ -3437,7 +3437,7 @@ static int sienna_cichlid_i2c_xfer(struct i2c_adapter > *i2c_adap, > if ((msg[i].flags & I2C_M_STOP) || > (!remaining_bytes)) > cmd->CmdConfig |= CMDCONFIG_STOP_MASK; > - if ((i > 0) && (j == 0) && !(msg[i].flags & > I2C_M_NOSTART)) > + if ((j == 0) && !(msg[i].flags & I2C_M_NOSTART)) > cmd->CmdConfig |= CMDCONFIG_RESTART_BIT; > } > } > -- > 2.32.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 13/40] dmr/amdgpu: Add RESTART handling also to smu_v11_0_i2c (VG20)
On Tue, Jun 8, 2021 at 5:40 PM Luben Tuikov wrote:
>
> From: Andrey Grodzovsky
>
> Also generilize the code to accept and translate to
> HW bits any I2C relvent flags both for read and write.
>
> Cc: Jean Delvare
> Cc: Alexander Deucher
> Cc: Andrey Grodzovsky
> Cc: Lijo Lazar
> Cc: Stanley Yang
> Cc: Hawking Zhang
> Signed-off-by: Andrey Grodzovsky
> Signed-off-by: Luben Tuikov
> Reviewed-by: Luben Tuikov
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 22 --
> 1 file changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> index 3193d566f4f87e..5a90d9351b22eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
> @@ -530,13 +530,11 @@ static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter
> *control)
> /* I2C GLUE /
>
> static uint32_t smu_v11_0_i2c_read_data(struct i2c_adapter *control,
> - struct i2c_msg *msg)
> + struct i2c_msg *msg, uint32_t
> i2c_flag)
> {
> - uint32_t ret = 0;
> + uint32_t ret;
>
> - /* Now read data starting with that address */
> - ret = smu_v11_0_i2c_receive(control, msg->addr, msg->buf, msg->len,
> - I2C_RESTART);
> + ret = smu_v11_0_i2c_receive(control, msg->addr, msg->buf, msg->len,
> i2c_flag);
>
> if (ret != I2C_OK)
> DRM_ERROR("ReadData() - I2C error occurred :%x", ret);
> @@ -545,12 +543,11 @@ static uint32_t smu_v11_0_i2c_read_data(struct
> i2c_adapter *control,
> }
>
> static uint32_t smu_v11_0_i2c_write_data(struct i2c_adapter *control,
> - struct i2c_msg *msg)
> + struct i2c_msg *msg, uint32_t
> i2c_flag)
> {
> uint32_t ret;
>
> - /* Send I2C_NO_STOP unless requested to stop. */
> - ret = smu_v11_0_i2c_transmit(control, msg->addr, msg->buf, msg->len,
> ((msg->flags & I2C_M_STOP) ? 0 : I2C_NO_STOP));
> + ret = smu_v11_0_i2c_transmit(control, msg->addr, msg->buf, msg->len,
> i2c_flag);
>
> if (ret != I2C_OK)
> DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret);
> @@ -601,12 +598,17 @@ static int smu_v11_0_i2c_xfer(struct i2c_adapter
> *i2c_adap,
> smu_v11_0_i2c_init(i2c_adap);
>
> for (i = 0; i < num; i++) {
> + uint32_t i2c_flag = ((msgs[i].flags & I2C_M_NOSTART) ? 0 :
> I2C_RESTART) ||
> + (((msgs[i].flags & I2C_M_STOP) ? 0 :
> I2C_NO_STOP));
> +
> if (msgs[i].flags & I2C_M_RD)
> ret = smu_v11_0_i2c_read_data(i2c_adap,
> - msgs + i);
> + msgs + i,
> + i2c_flag);
> else
> ret = smu_v11_0_i2c_write_data(i2c_adap,
> - msgs + i);
> + msgs + i,
> + i2c_flag);
>
> if (ret != I2C_OK) {
> num = -EIO;
> --
> 2.32.0
>
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[PATCH] drm/amd/display: Add Freesync video documentation
Recently, we added support for an experimental feature named Freesync
video; for more details on that, refer to:
commit a372f4abecb1 ("drm/amd/display: Skip modeset for front porch change")
commit 952bc47fb2ca ("drm/amd/display: Add freesync video modes based on
preferred modes")
commit d03ee581eee6 ("drm/amd/display: Add module parameter for freesync video
mode")
Nevertheless, we did not document it in detail in our driver. This
commit introduces a kernel-doc and expands the module parameter
description.
Cc: Aurabindo Pillai
Cc: Sean Paul
Cc: Harry Wentland
Signed-off-by: Rodrigo Siqueira
---
Documentation/gpu/amdgpu-dc.rst | 6
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 17 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 +++
3 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/Documentation/gpu/amdgpu-dc.rst b/Documentation/gpu/amdgpu-dc.rst
index cc89b0fc11df..f7ff7e1309de 100644
--- a/Documentation/gpu/amdgpu-dc.rst
+++ b/Documentation/gpu/amdgpu-dc.rst
@@ -66,3 +66,9 @@ Display Core
**WIP**
+
+FreeSync Video
+--
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+ :doc: FreeSync Video
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3de1accb060e..561c7ead4a5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -836,8 +836,21 @@ module_param_named(tmz, amdgpu_tmz, int, 0444);
/**
* DOC: freesync_video (uint)
- * Enabled the optimization to adjust front porch timing to achieve seamless
mode change experience
- * when setting a freesync supported mode for which full modeset is not needed.
+ * Enable the optimization to adjust front porch timing to achieve seamless
+ * mode change experience when setting a freesync supported mode for which full
+ * modeset is not needed.
+ *
+ * The Display core will add a set of modes derived from the base FreeSync
+ * video mode into the corresponding connector's mode list based on commonly
+ * used refresh rates and VRR range of the connected display, when users enable
+ * this feature. From the userspace perspective, they can see a seamless mode
+ * change experience when the change between different refresh rates under the
+ * same resolution. Additionally, userspace applications such as Video playback
+ * can read this modeset list and change the refresh rate based on the video
+ * frame rate.
+ *
+ * Note: This is an experimental feature.
+ *
* The default value: 0 (off).
*/
MODULE_PARM_DESC(
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 54dfa245b656..710ee3954062 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5718,6 +5718,36 @@ static void apply_dsc_policy_for_stream(struct
amdgpu_dm_connector *aconnector,
}
#endif
+/**
+ * DOC: FreeSync Video
+ *
+ * When a userspace application wants to play a video, the content follows a
+ * standard format definition that usually specifies the FPS for that format.
+ * The below list illustrates some video format and the expected FPS,
+ * respectively:
+ *
+ * - TV/NTSC (23.976 FPS)
+ * - Cinema (24 FPS)
+ * - TV/PAL (25 FPS)
+ * - TV/NTSC (29.97 FPS)
+ * - TV/NTSC (30 FPS)
+ * - Cinema HFR (48 FPS)
+ * - TV/PAL (50 FPS)
+ * - Commonly used (60 FPS)
+ * - Multiples of 24 (48,72,96 FPS)
+ *
+ * The list of standards video format is not huge and can be added to the
+ * connector modeset list beforehand. With that, userspace can leverage
+ * FreeSync to extends the front porch in order to attain the target refresh
+ * rate. Such a switch will happen seamlessly, without screen blanking or
+ * reprogramming of the output in any other way. If the userspace requests a
+ * modesetting change compatible with FreeSync modes that only differ in the
+ * refresh rate, DC will skip the full update and avoid blink during the
+ * transition. For example, the video player can change the modesetting from
+ * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
+ * causing any display blink. This same concept can be applied to a mode
+ * setting change.
+ */
static struct drm_display_mode *
get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
bool use_probed_modes)
--
2.25.1
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Re: Change how amdgpu stores fences in dma_resv objects
Am 10.06.21 um 18:34 schrieb Michel Dänzer: On 2021-06-10 11:17 a.m., Christian König wrote: Since we can't find a consensus on hot to move forward with the dma_resv object I concentrated on changing the approach for amdgpu first. This new approach changes how the driver stores the command submission fence in the dma_resv object in DMA-buf exported BOs. For exported BOs we now store the CS fence in a dma_fence_chain container and assign that one to the exclusive fences slot. During synchronization this dma_fence_chain container is unpacked again and the containing fences handled individually. This has a little bit more overhead than the old approach, but it allows for waiting for the exclusive slot for writes again. Nice! This seems to work as expected with https://gitlab.gnome.org/GNOME/mutter/-/merge_requests/1880: Some buffers now don't poll readable at first, until the GPU is done processing them. Well I'm still pretty sure that any polling on the CPU should be avoided, but yes it is nice to have that working now in general. Unfortunately, as expected, without a high priority context for the compositor which can preempt client drawing, this isn't enough to prevent slow clients from slowing down the compositor as well. But it should already help for fullscreen apps where the compositor can directly scan out the client buffers at least. I have seen patches for this flying by internally, but not sure about the status. Christian. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Change how amdgpu stores fences in dma_resv objects
On 2021-06-10 11:17 a.m., Christian König wrote: > Since we can't find a consensus on hot to move forward with the dma_resv > object I concentrated on changing the approach for amdgpu first. > > This new approach changes how the driver stores the command submission fence > in the dma_resv object in DMA-buf exported BOs. > > For exported BOs we now store the CS fence in a dma_fence_chain container and > assign that one to the exclusive fences slot. > > During synchronization this dma_fence_chain container is unpacked again and > the containing fences handled individually. > > This has a little bit more overhead than the old approach, but it allows for > waiting for the exclusive slot for writes again. Nice! This seems to work as expected with https://gitlab.gnome.org/GNOME/mutter/-/merge_requests/1880: Some buffers now don't poll readable at first, until the GPU is done processing them. Unfortunately, as expected, without a high priority context for the compositor which can preempt client drawing, this isn't enough to prevent slow clients from slowing down the compositor as well. But it should already help for fullscreen apps where the compositor can directly scan out the client buffers at least. -- Earthling Michel Dänzer | https://redhat.com Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 06/24] drm/amd/display: Change swizzle visual confirm reference pipe
From: Po-Ting Chen
[Why]
To change the swizzle visual confirm reference pipe from top pipe to
bottom pipe due to bottom pipe information would be more important
for multiple overlay case.
Signed-off-by: Po-Ting Chen
Reviewed-by: Anthony Koo
Acked-by: Anson Jacob
---
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 15f987a63025..9039fb134db5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -409,13 +409,13 @@ void get_surface_tile_visual_confirm_color(
struct tg_color *color)
{
uint32_t color_value = MAX_TG_COLOR_VALUE;
- /* Determine the overscan color based on the top-most (desktop) plane's
context */
- struct pipe_ctx *top_pipe_ctx = pipe_ctx;
+ /* Determine the overscan color based on the bottom-most plane's
context */
+ struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;
- while (top_pipe_ctx->top_pipe != NULL)
- top_pipe_ctx = top_pipe_ctx->top_pipe;
+ while (bottom_pipe_ctx->bottom_pipe != NULL)
+ bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
- switch (top_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
+ switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
case DC_SW_LINEAR:
/* LINEAR Surface - set border color to red */
color->color_r_cr = color_value;
--
2.25.1
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Re: [PATCH 4/4] drm/i915/display: Add handling for new "active bpc" property
On Tue, Jun 08, 2021 at 07:19:31PM +0200, Werner Sembach wrote:
>
> Am 07.06.21 um 22:33 schrieb Werner Sembach:
> > Am 07.06.21 um 08:47 schrieb Werner Sembach:
> >>
> >> Am 04.06.21 um 19:30 schrieb Ville Syrjälä:
> >>> On Fri, Jun 04, 2021 at 07:17:23PM +0200, Werner Sembach wrote:
> This commits implements the "active bpc" drm property for the Intel
> GPU driver.
>
> Signed-off-by: Werner Sembach
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 13 +
> drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++-
> 4 files changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 64e9107d70f7..f7898d9d7438 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10164,6 +10164,8 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> struct intel_crtc *crtc;
> + struct drm_connector *connector;
> + struct drm_connector_state *new_conn_state;
> u64 put_domains[I915_MAX_PIPES] = {};
> intel_wakeref_t wakeref = 0;
> int i;
> @@ -10324,6 +10326,17 @@ static void
> intel_atomic_commit_tail(struct intel_atomic_state *state)
> }
> intel_runtime_pm_put(_priv->runtime_pm, state->wakeref);
> + /* Extract information from crtc to communicate it to
> userspace as connector properties */
> + for_each_new_connector_in_state(>base, connector,
> new_conn_state, i) {
> + struct drm_crtc *crtc = new_conn_state->crtc;
> + if (crtc) {
> + new_crtc_state =
> to_intel_crtc_state(drm_atomic_get_new_crtc_state(>base,
> crtc));
> >>> intel_atomic_get_new_crtc_state()
> >> Thanks, will use that.
> >>>
> + new_conn_state->active_bpc = new_crtc_state->pipe_bpp / 3;
> + }
> + else
> + new_conn_state->active_bpc = 0;
> + }
> >>> This also seems too late. I think the whole thing should be
> >>> done somewhere around the normal swap_state() stuff.
> >> Ok, will look into it.
> > So I tried to put it in intel_atomic_commit() after
> > drm_atomic_helper_swap_state() and before
> > INIT_WORK(>base.commit_work, intel_atomic_commit_work) (which
> > creates a worker for intel_atomic_commit_tail), but somewhere in
> > between, the connector_state seems to change: The bpc written with the
> > for_each_new_connector_in_state() loop, gets discarded.
>
> This was not the problem. Setting the drm property immutable made it
> (also?) immutable from the driver context, which I didn't test separately.
>
> Removed the immutable again and moved the loop.
Immutable props are special. See __drm_object_property_get_value().
--
Ville Syrjälä
Intel
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Re: [PATCH v2 4/7] drm/i915/display: Add handling for new "active bpc" property
On Thu, Jun 10, 2021 at 02:50:36PM +0200, Maxime Ripard wrote:
> Hi
>
> On Tue, Jun 08, 2021 at 07:43:17PM +0200, Werner Sembach wrote:
> > This commits implements the "active bpc" drm property for the Intel GPU
> > driver.
> >
> > Signed-off-by: Werner Sembach
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 14 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++-
> > drivers/gpu/drm/i915/display/intel_hdmi.c| 4 +++-
> > 4 files changed, 26 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 64e9107d70f7..50c11b8770a7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -10388,6 +10388,9 @@ static int intel_atomic_commit(struct drm_device
> > *dev,
> > {
> > struct intel_atomic_state *state = to_intel_atomic_state(_state);
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct drm_connector *connector;
> > + struct drm_connector_state *new_conn_state;
> > + int i;
> > int ret = 0;
> >
> > state->wakeref = intel_runtime_pm_get(_priv->runtime_pm);
> > @@ -10456,6 +10459,17 @@ static int intel_atomic_commit(struct drm_device
> > *dev,
> > intel_shared_dpll_swap_state(state);
> > intel_atomic_track_fbs(state);
> >
> > + /* Extract information from crtc to communicate it to userspace as
> > connector properties */
> > + for_each_new_connector_in_state(>base, connector,
> > new_conn_state, i) {
> > + struct intel_crtc *crtc = to_intel_crtc(new_conn_state->crtc);
> > + if (crtc) {
> > + struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > + new_conn_state->active_bpc = new_crtc_state->pipe_bpp /
> > 3;
> > + }
> > + else
> > + new_conn_state->active_bpc = 0;
> > + }
> > +
>
> This seems fairly intrusive, but also commit / commit_tail might not be
> the best place to put this, we want to support it at the connector
> level.
>
> Indeed, this will cause some issue if your HDMI output is a bridge for
> example, where the commit will be in an entirely different driver that
> has no dependency on the HDMI controller one.
>
> I think it would be best to do that assignment in atomic_check. That
> way, if the userspace does a commit with DRM_MODE_ATOMIC_TEST_ONLY it
> would know what the output state would have been like.
DRM_MODE_ATOMIC_TEST_ONLY isn't allowed to change anything.
--
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Intel
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Re: [PATCH v2 4/7] drm/i915/display: Add handling for new "active bpc" property
Hi
On Tue, Jun 08, 2021 at 07:43:17PM +0200, Werner Sembach wrote:
> This commits implements the "active bpc" drm property for the Intel GPU
> driver.
>
> Signed-off-by: Werner Sembach
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 14 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++-
> drivers/gpu/drm/i915/display/intel_hdmi.c| 4 +++-
> 4 files changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 64e9107d70f7..50c11b8770a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10388,6 +10388,9 @@ static int intel_atomic_commit(struct drm_device *dev,
> {
> struct intel_atomic_state *state = to_intel_atomic_state(_state);
> struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_connector *connector;
> + struct drm_connector_state *new_conn_state;
> + int i;
> int ret = 0;
>
> state->wakeref = intel_runtime_pm_get(_priv->runtime_pm);
> @@ -10456,6 +10459,17 @@ static int intel_atomic_commit(struct drm_device
> *dev,
> intel_shared_dpll_swap_state(state);
> intel_atomic_track_fbs(state);
>
> + /* Extract information from crtc to communicate it to userspace as
> connector properties */
> + for_each_new_connector_in_state(>base, connector,
> new_conn_state, i) {
> + struct intel_crtc *crtc = to_intel_crtc(new_conn_state->crtc);
> + if (crtc) {
> + struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + new_conn_state->active_bpc = new_crtc_state->pipe_bpp /
> 3;
> + }
> + else
> + new_conn_state->active_bpc = 0;
> + }
> +
This seems fairly intrusive, but also commit / commit_tail might not be
the best place to put this, we want to support it at the connector
level.
Indeed, this will cause some issue if your HDMI output is a bridge for
example, where the commit will be in an entirely different driver that
has no dependency on the HDMI controller one.
I think it would be best to do that assignment in atomic_check. That
way, if the userspace does a commit with DRM_MODE_ATOMIC_TEST_ONLY it
would know what the output state would have been like.
Also, all of your patches don't follow the kernel coding style. Make
sure you fix the issues reported by checkpatch --strict
Maxime
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[PATCH -next] drm/amdgpu: Use DIV_ROUND_UP_ULL instead of DIV_ROUND_UP
When compiling the kernel for MIPS with CONFIG_DRM_AMDGPU = y, errors are
encountered as follows:
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.o: In function `amdgpu_vram_mgr_new':
amdgpu_vram_mgr.c:(.text+0x740): undefined reference to `__udivdi3'
Making a 64 bit division by a/b (a is uint64_t) is not supported by default
in linux kernel space. Instead, using do_div is OK for this situation. For
this problem, using DIV_ROUND_UP_ULL instead of DIV_ROUND_UP is better.
Fixes: 6a7f76e70fac ("drm/amdgpu: add VRAM manager v2")
Reported-by: Hulk Robot
Signed-off-by: He Ying
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 9a6df02477ce..436ec246a7da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -407,7 +407,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
#endif
pages_per_node = max_t(uint32_t, pages_per_node,
tbo->page_alignment);
- num_nodes = DIV_ROUND_UP(PFN_UP(mem_bytes), pages_per_node);
+ num_nodes = DIV_ROUND_UP_ULL(PFN_UP(mem_bytes), pages_per_node);
}
node = kvmalloc(struct_size(node, mm_nodes, num_nodes),
--
2.17.1
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Re: [PATCH -next] drm/amdgpu: Use DIV_ROUND_UP_ULL instead of DIV_ROUND_UP
Hello,
在 2021/6/10 16:20, Christian König 写道:
Am 10.06.21 um 10:20 schrieb He Ying:
When compiling the kernel for MIPS with CONFIG_DRM_AMDGPU = y, errors
are
encountered as follows:
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.o: In function
`amdgpu_vram_mgr_new':
amdgpu_vram_mgr.c:(.text+0x740): undefined reference to `__udivdi3'
Making a 64 bit division by a/b (a is uint64_t) is not supported by
default
in linux kernel space. Instead, using do_div is OK for this
situation. For
this problem, using DIV_ROUND_UP_ULL instead of DIV_ROUND_UP is better.
Already fixed by this patch in drm-next:
commit 691cf8cd7a531dbfcc29d09a23c509a86fd9b24f
Author: Dave Airlie
Date: Thu Jun 10 12:59:00 2021 +1000
drm/amdgpu: use correct rounding macro for 64-bit
This fixes 32-bit arm build due to lack of 64-bit divides.
OK. Sigh.
Before sending my patch, I searched patches in https://lore.kernel.org/lkml/
but I didn't find this patch. How can I find whether my patch is duplicated
before sending it? Any suggestions?
Thanks.
Regards,
Christian.
Fixes: 6a7f76e70fac ("drm/amdgpu: add VRAM manager v2")
Reported-by: Hulk Robot
Signed-off-by: He Ying
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 9a6df02477ce..436ec246a7da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -407,7 +407,7 @@ static int amdgpu_vram_mgr_new(struct
ttm_resource_manager *man,
#endif
pages_per_node = max_t(uint32_t, pages_per_node,
tbo->page_alignment);
- num_nodes = DIV_ROUND_UP(PFN_UP(mem_bytes), pages_per_node);
+ num_nodes = DIV_ROUND_UP_ULL(PFN_UP(mem_bytes),
pages_per_node);
}
node = kvmalloc(struct_size(node, mm_nodes, num_nodes),
.
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Re: [PATCH -next] drm/amdgpu: Use DIV_ROUND_UP_ULL instead of DIV_ROUND_UP
Am 10.06.21 um 10:20 schrieb He Ying:
When compiling the kernel for MIPS with CONFIG_DRM_AMDGPU = y, errors are
encountered as follows:
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.o: In function `amdgpu_vram_mgr_new':
amdgpu_vram_mgr.c:(.text+0x740): undefined reference to `__udivdi3'
Making a 64 bit division by a/b (a is uint64_t) is not supported by default
in linux kernel space. Instead, using do_div is OK for this situation. For
this problem, using DIV_ROUND_UP_ULL instead of DIV_ROUND_UP is better.
Already fixed by this patch in drm-next:
commit 691cf8cd7a531dbfcc29d09a23c509a86fd9b24f
Author: Dave Airlie
Date: Thu Jun 10 12:59:00 2021 +1000
drm/amdgpu: use correct rounding macro for 64-bit
This fixes 32-bit arm build due to lack of 64-bit divides.
Regards,
Christian.
Fixes: 6a7f76e70fac ("drm/amdgpu: add VRAM manager v2")
Reported-by: Hulk Robot
Signed-off-by: He Ying
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 9a6df02477ce..436ec246a7da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -407,7 +407,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
#endif
pages_per_node = max_t(uint32_t, pages_per_node,
tbo->page_alignment);
- num_nodes = DIV_ROUND_UP(PFN_UP(mem_bytes), pages_per_node);
+ num_nodes = DIV_ROUND_UP_ULL(PFN_UP(mem_bytes), pages_per_node);
}
node = kvmalloc(struct_size(node, mm_nodes, num_nodes),
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amdgpu warning/crash on kernel 5.12.9
Hello, I receive warning/crash on kernel 5.12.9 on amdgpu. I paste the error below, did you ppl need detailed information described Documentation/admin-guide/reporting-bugs.rst or this is enought ? <6>[6.591737] [drm] fb depth is 24 <6>[6.591738] [drm]pitch is 10240 <6>[6.591780] fbcon: amdgpudrmfb (fb0) is primary device <4>[6.831292] [drm] REG_WAIT timeout 1us * 10 tries - mpc2_assert_idle_mpcc line:480 <4>[6.831315] [ cut here ] <4>[6.831315] WARNING: CPU: 0 PID: 732 at drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:959 dcn30_set_hubp_blank+0x214/0x220 [amdgpu] <4>[6.831444] Modules linked in: joydev btusb btrtl btbcm hid_generic btintel bluetooth usbhid uas iwlmvm ecdh_generic ecc hid usb_storage usblp mac80211 snd_hda_codec_realtek intel_rapl_msr snd_hda_codec_generic intel_rapl_common iwlwifi amdgpu(+) ledtrig_audio snd_hda_codec_hdmi iommu_v2 gpu_sched drm_ttm_helper edac_mce_amd snd_hda_intel ttm snd_intel_dspcfg drm_kms_helper snd_intel_sdw_acpi snd_hda_codec kvm_amd snd_hda_core evdev wmi_bmof drm snd_hwdep kvm agpgart igb irqbypass snd_pcm fb_sys_fops crct10dif_pclmul crc32_pclmul xhci_pci cfg80211 syscopyarea dca snd_timer ghash_clmulni_intel sysfillrect xhci_pci_renesas i2c_piix4 snd i2c_algo_bit sysimgblt rapl soundcore ccp rfkill k10temp i2c_core xhci_hcd tpm_crb tpm_tis tpm_tis_core wmi button acpi_cpufreq loop <4>[6.831463] CPU: 0 PID: 732 Comm: udevd Not tainted 5.12.9 #1 <4>[6.831465] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./X570 Phantom Gaming 4, BIOS P4.00 04/15/2021 <4>[6.831465] RIP: 0010:dcn30_set_hubp_blank+0x214/0x220 [amdgpu] <4>[6.831587] Code: 31 f6 48 8b 07 48 8b 40 50 e8 18 b4 77 f6 48 8b 9b d0 02 00 00 48 85 db 75 df eb 8c 0f 0b e9 46 ff ff ff 0f 0b e9 be fe ff ff <0f> 0b e9 42 fe ff ff 0f 1f 44 00 00 0f 1f 44 00 00 41 57 41 56 45 <4>[6.831588] RSP: 0018:a90780cc7338 EFLAGS: 00010246 <4>[6.831590] RAX: RBX: 0001 RCX: 0003 <4>[6.831590] RDX: RSI: RDI: 9bdfd2ea <4>[6.831591] RBP: 9bdfd3d801e8 R08: a90780cc7324 R09: a90780cc7280 <4>[6.831591] R10: 0002 R11: 343a656e696c2063 R12: 9bdfd3d801e8 <4>[6.831592] R13: 9bdfd07f R14: R15: 9bdfd3d801e8 <4>[6.831593] FS: 7fa55e27f140() GS:9be6dea0() knlGS: <4>[6.831594] CS: 0010 DS: ES: CR0: 80050033 <4>[6.831594] CR2: 7fa55d9d6eb3 CR3: 0001097bc000 CR4: 00350ef0 <4>[6.831595] Call Trace: <4>[6.831597] dcn10_wait_for_mpcc_disconnect+0x116/0x190 [amdgpu] <4>[6.831727] dcn20_plane_atomic_disable+0x3e/0x150 [amdgpu] <4>[6.831858] dcn20_disable_plane+0x24/0x40 [amdgpu] <4>[6.831985] dcn10_init_pipes+0x307/0x3f0 [amdgpu] <4>[6.832112] dce110_enable_accelerated_mode+0x9c/0x260 [amdgpu] <4>[6.832237] dc_commit_state+0x97f/0xa80 [amdgpu] <4>[6.832359] amdgpu_dm_atomic_commit_tail+0x576/0x25e0 [amdgpu] <4>[6.832489] ? dcn30_validate_bandwidth+0x11f/0x270 [amdgpu] <4>[6.832621] ? kfree+0xba/0x3f0 <4>[6.832623] ? dcn30_validate_bandwidth+0x11f/0x270 [amdgpu] <4>[6.832743] ? fill_dc_plane_info_and_addr+0x3b0/0x3b0 [amdgpu] <4>[6.832870] ? dm_plane_helper_prepare_fb+0x1db/0x240 [amdgpu] <4>[6.832995] ? drm_atomic_helper_setup_commit+0x74b/0x810 [drm_kms_helper] <4>[6.833005] commit_tail+0x94/0x130 [drm_kms_helper] <4>[6.833014] drm_atomic_helper_commit+0x113/0x140 [drm_kms_helper] <4>[6.833023] drm_client_modeset_commit_atomic+0x1e4/0x220 [drm] <4>[6.833043] drm_client_modeset_commit_locked+0x56/0x150 [drm] <4>[6.833059] drm_client_modeset_commit+0x24/0x40 [drm] <4>[6.833075] drm_fb_helper_set_par+0xa5/0xd0 [drm_kms_helper] <4>[6.833084] fbcon_init+0x264/0x4f0 <4>[6.833086] visual_init+0xce/0x130 <4>[6.833089] do_bind_con_driver.isra.0+0x1db/0x2e0 <4>[6.833091] do_take_over_console+0x116/0x180 <4>[6.833092] do_fbcon_takeover+0x5c/0xc0 <4>[6.833094] register_framebuffer+0x1e4/0x300 <4>[6.833096] __drm_fb_helper_initial_config_and_unlock+0x321/0x4a0 [drm_kms_helper] <4>[6.833105] amdgpu_fbdev_init+0xb9/0xf0 [amdgpu] <4>[6.833207] amdgpu_device_init.cold+0x1626/0x1ad6 [amdgpu] <4>[6.85] ? is_acpi_device_node+0x21/0x30 <4>[6.87] amdgpu_driver_load_kms+0x64/0x230 [amdgpu] <4>[6.833437] amdgpu_pci_probe+0x11f/0x1b0 [amdgpu] <4>[6.833533] local_pci_probe+0x42/0x80 <4>[6.833536] ? __cond_resched+0x16/0x40 <4>[6.833537] pci_device_probe+0xfa/0x1b0 <4>[6.833539] really_probe+0xed/0x430 <4>[6.833541] driver_probe_device+0x4f/0xb0 <4>[6.833542] device_driver_attach+0xa1/0xb0 <4>[6.833543] __driver_attach+0x74/0x110 <4>[6.833545] ? device_driver_attach+0xb0/0xb0
RE: [PATCH] drm/amdgpu: reset psp ring wptr during ring_create
[AMD Official Use Only]
Reviewed-by: Horace Chen
-Original Message-
From: amd-gfx On Behalf Of YuBiao Wang
Sent: Wednesday, June 9, 2021 11:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, YuBiao ; Grodzovsky, Andrey
; Xiao, Jack ; Xu, Feifei
; Chen, Horace ; Wang, Kevin(Yang)
; Xiaojie Yuan ; Tuikov, Luben
; Deucher, Alexander ; Quan,
Evan ; Koenig, Christian ; Liu,
Monk ; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: reset psp ring wptr during ring_create
[Why]
psp ring wptr is not initialized properly in ring_create, which would lead to
psp failure after several gpu reset.
[How]
Set ring_wptr to zero in psp_ring_create.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 0fd1ed918627..3e6218799a0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -468,6 +468,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev)) {
+ ring->ring_wptr = 0;
ret = psp_v11_0_ring_stop(psp, ring_type);
if (ret) {
DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); diff
--git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 908664a5774b..be05d9cbd41e 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -231,6 +231,7 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
psp_v3_1_reroute_ih(psp);
if (amdgpu_sriov_vf(adev)) {
+ ring->ring_wptr = 0;
ret = psp_v3_1_ring_stop(psp, ring_type);
if (ret) {
DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
--
2.25.1
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RE: [PATCH] drm/amdgpu: PWRBRK sequence changes for Aldebaran
[AMD Official Use Only] Reviewed-by: Lijo Lazar -Original Message- From: Ashish Pawar Sent: Thursday, June 10, 2021 12:18 AM To: amd-gfx@lists.freedesktop.org Cc: Lazar, Lijo ; Quan, Evan ; Pawar, Ashish Subject: [PATCH] drm/amdgpu: PWRBRK sequence changes for Aldebaran Modify power brake enablement sequence on Aldebaran Signed-off-by: Ashish Pawar --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c index c0352dcc89be..1769c4cba2ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c @@ -782,11 +782,6 @@ void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1); WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp); - WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); - tmp = 0; - tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1); - WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp); - WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); tmp = 0; tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/7] dma-buf: add dma_fence_chain_alloc/free
Add a common allocation helper. Cleaning up the mix of kzalloc/kmalloc
and some unused code in the selftest.
Signed-off-by: Christian König
---
drivers/dma-buf/st-dma-fence-chain.c | 16 --
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 4 ++--
drivers/gpu/drm/drm_syncobj.c | 6 ++---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 6 ++---
drivers/gpu/drm/msm/msm_gem_submit.c | 6 ++---
include/linux/dma-fence-chain.h | 22 +++
6 files changed, 35 insertions(+), 25 deletions(-)
diff --git a/drivers/dma-buf/st-dma-fence-chain.c
b/drivers/dma-buf/st-dma-fence-chain.c
index 9525f7f56119..8ce1ea59d31b 100644
--- a/drivers/dma-buf/st-dma-fence-chain.c
+++ b/drivers/dma-buf/st-dma-fence-chain.c
@@ -58,28 +58,20 @@ static struct dma_fence *mock_fence(void)
return >base;
}
-static inline struct mock_chain {
- struct dma_fence_chain base;
-} *to_mock_chain(struct dma_fence *f) {
- return container_of(f, struct mock_chain, base.base);
-}
-
static struct dma_fence *mock_chain(struct dma_fence *prev,
struct dma_fence *fence,
u64 seqno)
{
- struct mock_chain *f;
+ struct dma_fence_chain *f;
- f = kmalloc(sizeof(*f), GFP_KERNEL);
+ f = dma_fence_chain_alloc();
if (!f)
return NULL;
- dma_fence_chain_init(>base,
-dma_fence_get(prev),
-dma_fence_get(fence),
+ dma_fence_chain_init(f, dma_fence_get(prev), dma_fence_get(fence),
seqno);
- return >base.base;
+ return >base;
}
static int sanitycheck(void *arg)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 90136f9dedd6..325e82621467 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1124,7 +1124,7 @@ static int
amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p
dep->chain = NULL;
if (syncobj_deps[i].point) {
- dep->chain = kmalloc(sizeof(*dep->chain), GFP_KERNEL);
+ dep->chain = dma_fence_chain_alloc();
if (!dep->chain)
return -ENOMEM;
}
@@ -1132,7 +1132,7 @@ static int
amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p
dep->syncobj = drm_syncobj_find(p->filp,
syncobj_deps[i].handle);
if (!dep->syncobj) {
- kfree(dep->chain);
+ dma_fence_chain_free(dep->chain);
return -EINVAL;
}
dep->point = syncobj_deps[i].point;
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index fdd2ec87cdd1..1c5b9ef6da37 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -861,7 +861,7 @@ static int drm_syncobj_transfer_to_timeline(struct drm_file
*file_private,
);
if (ret)
goto err;
- chain = kzalloc(sizeof(struct dma_fence_chain), GFP_KERNEL);
+ chain = dma_fence_chain_alloc();
if (!chain) {
ret = -ENOMEM;
goto err1;
@@ -1402,10 +1402,10 @@ drm_syncobj_timeline_signal_ioctl(struct drm_device
*dev, void *data,
goto err_points;
}
for (i = 0; i < args->count_handles; i++) {
- chains[i] = kzalloc(sizeof(struct dma_fence_chain), GFP_KERNEL);
+ chains[i] = dma_fence_chain_alloc();
if (!chains[i]) {
for (j = 0; j < i; j++)
- kfree(chains[j]);
+ dma_fence_chain_free(chains[j]);
ret = -ENOMEM;
goto err_chains;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 66789111a24b..a22cb86730b3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2983,7 +2983,7 @@ __free_fence_array(struct eb_fence *fences, unsigned int
n)
while (n--) {
drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
dma_fence_put(fences[n].dma_fence);
- kfree(fences[n].chain_fence);
+ dma_fence_chain_free(fences[n].chain_fence);
}
kvfree(fences);
}
@@ -3097,9 +3097,7 @@ add_timeline_fence_array(struct i915_execbuffer *eb,
return -EINVAL;
}
- f->chain_fence =
- kmalloc(sizeof(*f->chain_fence),
-
[PATCH 6/7] drm/amdgpu: unwrap fence chains in the explicit sync fence
Unwrap a the explicit fence if it is a dma_fence_chain and
sync to the first fence not matching the owner rules.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 118 +--
1 file changed, 68 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 1b2ceccaf5b0..862eb3c1c4c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -28,6 +28,8 @@
*Christian König
*/
+#include
+
#include "amdgpu.h"
#include "amdgpu_trace.h"
#include "amdgpu_amdkfd.h"
@@ -186,6 +188,55 @@ int amdgpu_sync_vm_fence(struct amdgpu_sync *sync, struct
dma_fence *fence)
return amdgpu_sync_fence(sync, fence);
}
+/* Determine based on the owner and mode if we should sync to a fence or not */
+static bool amdgpu_sync_test_fence(struct amdgpu_device *adev,
+ enum amdgpu_sync_mode mode,
+ void *owner, struct dma_fence *f)
+{
+ void *fence_owner = amdgpu_sync_get_owner(f);
+
+ /* Always sync to moves, no matter what */
+ if (fence_owner == AMDGPU_FENCE_OWNER_UNDEFINED)
+ return true;
+
+ /* We only want to trigger KFD eviction fences on
+* evict or move jobs. Skip KFD fences otherwise.
+*/
+ if (fence_owner == AMDGPU_FENCE_OWNER_KFD &&
+ owner != AMDGPU_FENCE_OWNER_UNDEFINED)
+ return false;
+
+ /* Never sync to VM updates either. */
+ if (fence_owner == AMDGPU_FENCE_OWNER_VM &&
+ owner != AMDGPU_FENCE_OWNER_UNDEFINED)
+ return false;
+
+ /* Ignore fences depending on the sync mode */
+ switch (mode) {
+ case AMDGPU_SYNC_ALWAYS:
+ return true;
+
+ case AMDGPU_SYNC_NE_OWNER:
+ if (amdgpu_sync_same_dev(adev, f) &&
+ fence_owner == owner)
+ return false;
+ break;
+
+ case AMDGPU_SYNC_EQ_OWNER:
+ if (amdgpu_sync_same_dev(adev, f) &&
+ fence_owner != owner)
+ return false;
+ break;
+
+ case AMDGPU_SYNC_EXPLICIT:
+ return false;
+ }
+
+ WARN(debug_evictions && fence_owner == AMDGPU_FENCE_OWNER_KFD,
+"Adding eviction fence to sync obj");
+ return true;
+}
+
/**
* amdgpu_sync_resv - sync to a reservation object
*
@@ -211,67 +262,34 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct
amdgpu_sync *sync,
/* always sync to the exclusive fence */
f = dma_resv_excl_fence(resv);
- r = amdgpu_sync_fence(sync, f);
+ dma_fence_chain_for_each(f, f) {
+ struct dma_fence_chain *chain = to_dma_fence_chain(f);
+
+ if (amdgpu_sync_test_fence(adev, mode, owner, chain ?
+ chain->fence : f)) {
+ r = amdgpu_sync_fence(sync, f);
+ dma_fence_put(f);
+ if (r)
+ return r;
+ break;
+ }
+ }
flist = dma_resv_shared_list(resv);
- if (!flist || r)
- return r;
+ if (!flist)
+ return 0;
for (i = 0; i < flist->shared_count; ++i) {
- void *fence_owner;
-
f = rcu_dereference_protected(flist->shared[i],
dma_resv_held(resv));
- fence_owner = amdgpu_sync_get_owner(f);
-
- /* Always sync to moves, no matter what */
- if (fence_owner == AMDGPU_FENCE_OWNER_UNDEFINED) {
+ if (amdgpu_sync_test_fence(adev, mode, owner, f)) {
r = amdgpu_sync_fence(sync, f);
if (r)
- break;
- }
-
- /* We only want to trigger KFD eviction fences on
-* evict or move jobs. Skip KFD fences otherwise.
-*/
- if (fence_owner == AMDGPU_FENCE_OWNER_KFD &&
- owner != AMDGPU_FENCE_OWNER_UNDEFINED)
- continue;
-
- /* Never sync to VM updates either. */
- if (fence_owner == AMDGPU_FENCE_OWNER_VM &&
- owner != AMDGPU_FENCE_OWNER_UNDEFINED)
- continue;
-
- /* Ignore fences depending on the sync mode */
- switch (mode) {
- case AMDGPU_SYNC_ALWAYS:
- break;
-
- case AMDGPU_SYNC_NE_OWNER:
- if (amdgpu_sync_same_dev(adev, f) &&
- fence_owner == owner)
- continue;
- break;
-
- case AMDGPU_SYNC_EQ_OWNER:
- if
[PATCH 7/7] drm/amdgpu: rework dma_resv handling
Drop the workaround and instead implement a better solution.
Basically we are now chaining all submissions using a dma_fence_chain
container and adding them as exclusive fence to the dma_resv object.
This way other drivers can still sync to the single exclusive fence
while amdgpu only sync to fences from different processes.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 54 +
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 65 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 -
6 files changed, 47 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
index a130e766cbdb..c905a4cfc173 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
@@ -34,6 +34,7 @@ struct amdgpu_fpriv;
struct amdgpu_bo_list_entry {
struct ttm_validate_buffer tv;
struct amdgpu_bo_va *bo_va;
+ struct dma_fence_chain *chain;
uint32_tpriority;
struct page **user_pages;
booluser_invalidated;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 325e82621467..f6f3029f958d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -587,6 +587,20 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
goto out;
}
+ amdgpu_bo_list_for_each_entry(e, p->bo_list) {
+ struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
+
+ e->bo_va = amdgpu_vm_bo_find(vm, bo);
+
+ if (bo->tbo.base.dma_buf && !amdgpu_bo_explicit_sync(bo)) {
+ e->chain = dma_fence_chain_alloc();
+ if (!e->chain) {
+ r = -ENOMEM;
+ goto error_validate;
+ }
+ }
+ }
+
amdgpu_cs_get_threshold_for_moves(p->adev, >bytes_moved_threshold,
>bytes_moved_vis_threshold);
p->bytes_moved = 0;
@@ -614,15 +628,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
gws = p->bo_list->gws_obj;
oa = p->bo_list->oa_obj;
- amdgpu_bo_list_for_each_entry(e, p->bo_list) {
- struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
-
- /* Make sure we use the exclusive slot for shared BOs */
- if (bo->prime_shared_count)
- e->tv.num_shared = 0;
- e->bo_va = amdgpu_vm_bo_find(vm, bo);
- }
-
if (gds) {
p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
@@ -644,8 +649,13 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
}
error_validate:
- if (r)
+ if (r) {
+ amdgpu_bo_list_for_each_entry(e, p->bo_list) {
+ dma_fence_chain_free(e->chain);
+ e->chain = NULL;
+ }
ttm_eu_backoff_reservation(>ticket, >validated);
+ }
out:
return r;
}
@@ -685,9 +695,17 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser
*parser, int error,
{
unsigned i;
- if (error && backoff)
+ if (error && backoff) {
+ struct amdgpu_bo_list_entry *e;
+
+ amdgpu_bo_list_for_each_entry(e, parser->bo_list) {
+ dma_fence_chain_free(e->chain);
+ e->chain = NULL;
+ }
+
ttm_eu_backoff_reservation(>ticket,
>validated);
+ }
for (i = 0; i < parser->num_post_deps; i++) {
drm_syncobj_put(parser->post_deps[i].syncobj);
@@ -1260,6 +1278,20 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
amdgpu_vm_move_to_lru_tail(p->adev, >vm);
+ amdgpu_bo_list_for_each_entry(e, p->bo_list) {
+ struct dma_resv *resv = e->tv.bo->base.resv;
+ struct dma_fence_chain *chain = e->chain;
+
+ if (!chain)
+ continue;
+
+ dma_fence_chain_init(chain, dma_resv_excl_fence(resv),
+dma_fence_get(p->fence), 1);
+
+ rcu_assign_pointer(resv->fence_excl, >base);
+ e->chain = NULL;
+ }
+
ttm_eu_fence_buffer_objects(>ticket, >validated, p->fence);
mutex_unlock(>adev->notifier_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
[PATCH 3/7] dma-buf: add dma_fence_chain_alloc/free self tests
Exercise the newly added functions.
Signed-off-by: Christian König
---
drivers/dma-buf/st-dma-fence-chain.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/dma-buf/st-dma-fence-chain.c
b/drivers/dma-buf/st-dma-fence-chain.c
index 8ce1ea59d31b..855c129c6093 100644
--- a/drivers/dma-buf/st-dma-fence-chain.c
+++ b/drivers/dma-buf/st-dma-fence-chain.c
@@ -95,6 +95,53 @@ static int sanitycheck(void *arg)
return err;
}
+static int __alloc_free(void *arg)
+{
+ atomic_t *counter = arg;
+ int i, j;
+
+ for (i = 0; i < 1024; ++i) {
+ struct dma_fence_chain *chains[64];
+
+ for (j = 0; j < ARRAY_SIZE(chains); ++j)
+ chains[j] = dma_fence_chain_alloc();
+
+ for (j = 0; j < ARRAY_SIZE(chains); ++j)
+ dma_fence_chain_free(chains[j]);
+
+ atomic_add(ARRAY_SIZE(chains), counter);
+ }
+ return 0;
+}
+
+static int alloc_free(void *arg)
+{
+ struct task_struct *threads[8];
+ atomic_t counter = ATOMIC_INIT(0);
+ int i, err = 0;
+
+ for (i = 0; i < ARRAY_SIZE(threads); i++) {
+ threads[i] = kthread_run(__alloc_free, , "dmabuf/%d",
+i);
+ if (IS_ERR(threads[i])) {
+ err = PTR_ERR(threads[i]);
+ break;
+ }
+ }
+
+ while (i--) {
+ int ret;
+
+ ret = kthread_stop(threads[i]);
+ if (ret && !err)
+ err = ret;
+ }
+
+ pr_info("Completed %u cycles\n", atomic_read());
+
+ return err;
+}
+
struct fence_chains {
unsigned int chain_length;
struct dma_fence **fences;
@@ -677,6 +724,7 @@ int dma_fence_chain(void)
{
static const struct subtest tests[] = {
SUBTEST(sanitycheck),
+ SUBTEST(alloc_free),
SUBTEST(find_seqno),
SUBTEST(find_signaled),
SUBTEST(find_out_of_order),
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 5/7] drm/syncobj: drop the manual garbage collection
Not needed any more since dma_fence_chain objects take care of this now. Signed-off-by: Christian König --- drivers/gpu/drm/drm_syncobj.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c index 1c5b9ef6da37..e6d144775a87 100644 --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@ -304,9 +304,6 @@ void drm_syncobj_add_point(struct drm_syncobj *syncobj, list_for_each_entry_safe(cur, tmp, >cb_list, node) syncobj_wait_syncobj_func(syncobj, cur); spin_unlock(>lock); - - /* Walk the chain once to trigger garbage collection */ - dma_fence_chain_for_each(fence, prev); dma_fence_put(prev); } EXPORT_SYMBOL(drm_syncobj_add_point); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/7] dma-buf: add dma_fence_chain_garbage_collect
Add some rather sophisticated lockless garbage collection
for dma_fence_chain objects.
For this keep all initialized dma_fence_chain nodes an a
queue and trigger garbage collection before a new one is
allocated.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-fence-chain.c | 160 +-
include/linux/dma-fence-chain.h | 5 +
2 files changed, 142 insertions(+), 23 deletions(-)
diff --git a/drivers/dma-buf/dma-fence-chain.c
b/drivers/dma-buf/dma-fence-chain.c
index 1b4cb3e5cec9..c2f0b69eabb7 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -9,8 +9,53 @@
#include
+static struct dma_fence_chain __rcu *fifo_front;
+static struct dma_fence_chain __rcu **fifo_back = _front;
+
static bool dma_fence_chain_enable_signaling(struct dma_fence *fence);
+/**
+ * dma_fence_chain_enqueue - enqeue a chain node for garbage collection
+ * @chain: the chain node to enqueue
+ *
+ * Add the chain node to the end of the gc fifo.
+ */
+static void dma_fence_chain_enqueue(struct dma_fence_chain *chain)
+{
+ struct dma_fence_chain __rcu **tmp;
+
+ RCU_INIT_POINTER(chain->next, NULL);
+ tmp = xchg((struct dma_fence_chain __force ***)_back,
+ >next);
+
+ /* This is intentionally unordered since we only need the fifo for gc */
+ rcu_assign_pointer(*tmp, chain);
+}
+
+/**
+ * dma_fence_chain_dequeue - deqeueue a chain node for garbage collection
+ *
+ * Remove the first chain node from the gc fifo while making sure that always
+ * keep at least one node on the fifo for lockless fifo implementation.
+ * Returns the dequeued chain node or NULL.
+ */
+static struct dma_fence_chain *dma_fence_chain_dequeue(void)
+{
+ struct dma_fence_chain *chain, *tmp;
+
+ rcu_read_lock();
+ chain = rcu_dereference(fifo_front);
+ /* Never dequeue the last chain node for lockless fifo */
+ if (unlikely(!chain || !rcu_access_pointer(chain->next))) {
+ rcu_read_unlock();
+ return NULL;
+ }
+ tmp = cmpxchg((struct dma_fence_chain __force **)_front,
+ chain, rcu_access_pointer(chain->next));
+ rcu_read_unlock();
+ return tmp == chain ? chain : NULL;
+}
+
/**
* dma_fence_chain_get_prev - use RCU to get a reference to the previous fence
* @chain: chain node to get the previous node from
@@ -28,6 +73,43 @@ static struct dma_fence *dma_fence_chain_get_prev(struct
dma_fence_chain *chain)
return prev;
}
+/**
+ * dma_fence_chain_try_replace - try to replace the prev node
+ * @chain: Chain node we try to replace prev.
+ * @prev: the old prev node
+ *
+ * Try to replace the previous chain node when it or its containing fence is
+ * signaled. Returns true if we tried, false if we need to wait.
+ */
+static bool dma_fence_chain_try_replace(struct dma_fence_chain *chain,
+ struct dma_fence *prev)
+{
+ struct dma_fence *replacement, *tmp;
+ struct dma_fence_chain *prev_chain;
+
+ prev_chain = to_dma_fence_chain(prev);
+ if (prev_chain) {
+ if (!dma_fence_is_signaled(prev_chain->fence))
+ return false;
+
+ replacement = dma_fence_chain_get_prev(prev_chain);
+ } else {
+ if (!dma_fence_is_signaled(prev))
+ return false;
+
+ replacement = NULL;
+ }
+
+ tmp = cmpxchg((struct dma_fence __force **)>prev, prev,
+ replacement);
+ if (tmp == prev)
+ dma_fence_put(tmp);
+ else
+ dma_fence_put(replacement);
+
+ return true;
+}
+
/**
* dma_fence_chain_walk - chain walking function
* @fence: current chain node
@@ -38,8 +120,8 @@ static struct dma_fence *dma_fence_chain_get_prev(struct
dma_fence_chain *chain)
*/
struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence)
{
- struct dma_fence_chain *chain, *prev_chain;
- struct dma_fence *prev, *replacement, *tmp;
+ struct dma_fence_chain *chain;
+ struct dma_fence *prev;
chain = to_dma_fence_chain(fence);
if (!chain) {
@@ -48,26 +130,8 @@ struct dma_fence *dma_fence_chain_walk(struct dma_fence
*fence)
}
while ((prev = dma_fence_chain_get_prev(chain))) {
-
- prev_chain = to_dma_fence_chain(prev);
- if (prev_chain) {
- if (!dma_fence_is_signaled(prev_chain->fence))
- break;
-
- replacement = dma_fence_chain_get_prev(prev_chain);
- } else {
- if (!dma_fence_is_signaled(prev))
- break;
-
- replacement = NULL;
- }
-
- tmp = cmpxchg((struct dma_fence __force **)>prev,
- prev, replacement);
- if (tmp == prev)
-
[PATCH 1/7] dma-buf: some dma_fence_chain improvements
The callback and the irq work are never used at the same
time. Putting them into an union saves us 24 bytes and
makes the structure only 120 bytes in size.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-fence-chain.c | 2 +-
include/linux/dma-fence-chain.h | 8 +---
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/dma-buf/dma-fence-chain.c
b/drivers/dma-buf/dma-fence-chain.c
index 7d129e68ac70..1b4cb3e5cec9 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -137,6 +137,7 @@ static void dma_fence_chain_cb(struct dma_fence *f, struct
dma_fence_cb *cb)
struct dma_fence_chain *chain;
chain = container_of(cb, typeof(*chain), cb);
+ init_irq_work(>work, dma_fence_chain_irq_work);
irq_work_queue(>work);
dma_fence_put(f);
}
@@ -239,7 +240,6 @@ void dma_fence_chain_init(struct dma_fence_chain *chain,
rcu_assign_pointer(chain->prev, prev);
chain->fence = fence;
chain->prev_seqno = 0;
- init_irq_work(>work, dma_fence_chain_irq_work);
/* Try to reuse the context of the previous chain node. */
if (prev_chain && __dma_fence_is_later(seqno, prev->seqno, prev->ops)) {
diff --git a/include/linux/dma-fence-chain.h b/include/linux/dma-fence-chain.h
index 10462a029da2..9d6a062be640 100644
--- a/include/linux/dma-fence-chain.h
+++ b/include/linux/dma-fence-chain.h
@@ -25,12 +25,14 @@
*/
struct dma_fence_chain {
struct dma_fence base;
- spinlock_t lock;
struct dma_fence __rcu *prev;
u64 prev_seqno;
struct dma_fence *fence;
- struct dma_fence_cb cb;
- struct irq_work work;
+ union {
+ struct dma_fence_cb cb;
+ struct irq_work work;
+ };
+ spinlock_t lock;
};
extern const struct dma_fence_ops dma_fence_chain_ops;
--
2.25.1
___
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Change how amdgpu stores fences in dma_resv objects
Since we can't find a consensus on hot to move forward with the dma_resv object I concentrated on changing the approach for amdgpu first. This new approach changes how the driver stores the command submission fence in the dma_resv object in DMA-buf exported BOs. For exported BOs we now store the CS fence in a dma_fence_chain container and assign that one to the exclusive fences slot. During synchronization this dma_fence_chain container is unpacked again and the containing fences handled individually. This has a little bit more overhead than the old approach, but it allows for waiting for the exclusive slot for writes again. Regards, Christian. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2 1/7] drm/sysfs: introduce drm_sysfs_connector_hotplug_event
On Wed, 09 Jun 2021 21:23:27 +
Simon Ser wrote:
> This function sends a hotplug uevent with a CONNECTOR property.
>
> Signed-off-by: Simon Ser
> ---
> drivers/gpu/drm/drm_sysfs.c | 25 +
> include/drm/drm_sysfs.h | 1 +
> 2 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
> index 968a9560b4aa..8423e44c3035 100644
> --- a/drivers/gpu/drm/drm_sysfs.c
> +++ b/drivers/gpu/drm/drm_sysfs.c
> @@ -343,6 +343,31 @@ void drm_sysfs_hotplug_event(struct drm_device *dev)
> }
> EXPORT_SYMBOL(drm_sysfs_hotplug_event);
>
> +/**
> + * drm_sysfs_connector_hotplug_event - generate a DRM uevent for any
> connector
> + * change
> + * @connector: connector which has changed
> + *
> + * Send a uevent for the DRM connector specified by @connector. This will
> send
> + * a uevent with the properties HOTPLUG=1 and CONNECTOR.
> + */
> +void drm_sysfs_connector_hotplug_event(struct drm_connector *connector)
> +{
> + struct drm_device *dev = connector->dev;
> + char hotplug_str[] = "HOTPLUG=1", conn_id[21];
> + char *envp[] = { hotplug_str, conn_id, NULL };
> +
> + snprintf(conn_id, sizeof(conn_id),
> + "CONNECTOR=%u", connector->base.id);
> +
> + drm_dbg_kms(connector->dev,
> + "[CONNECTOR:%d:%s] generating connector hotplug event\n",
> + connector->base.id, connector->name);
> +
> + kobject_uevent_env(>primary->kdev->kobj, KOBJ_CHANGE, envp);
> +}
> +EXPORT_SYMBOL(drm_sysfs_connector_hotplug_event);
Hi,
I believe this change would be safe for Weston while Weston would not
take advantage of the optimisation without patching it. The idea seems
fine to me, and patching Weston to take advantage of this would be fine
too.
I can't say anything about the kernel internal details on how to
implement this, and I don't recall if the per-connector epoch counter
was supposed to the exposed to userspace, offering a different way to
do the same.
Thanks,
pq
> +
> /**
> * drm_sysfs_connector_status_event - generate a DRM uevent for connector
> * property status change
> diff --git a/include/drm/drm_sysfs.h b/include/drm/drm_sysfs.h
> index d454ef617b2c..6273cac44e47 100644
> --- a/include/drm/drm_sysfs.h
> +++ b/include/drm/drm_sysfs.h
> @@ -11,6 +11,7 @@ int drm_class_device_register(struct device *dev);
> void drm_class_device_unregister(struct device *dev);
>
> void drm_sysfs_hotplug_event(struct drm_device *dev);
> +void drm_sysfs_connector_hotplug_event(struct drm_connector *connector);
> void drm_sysfs_connector_status_event(struct drm_connector *connector,
> struct drm_property *property);
> #endif
pgpbf2fDViE7X.pgp
Description: OpenPGP digital signature
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Re: [PATCH v2 5/7] drm/uAPI: Add "active color format" drm property as feedback for userspace
On Tue, 8 Jun 2021 19:43:18 +0200
Werner Sembach wrote:
> Add a new general drm property "active color format" which can be used by
> graphic drivers to report the used color format back to userspace.
>
> There was no way to check which color format got actually used on a given
> monitor. To surely predict this, one must know the exact capabilities of the
> monitor, the GPU, and the connection used and what the default behaviour of
> the
> used driver is (e.g. amdgpu prefers YCbCr 4:4:4 while i915 prefers RGB). This
> property helps eliminating the guessing on this point.
>
> In the future, automatic color calibration for screens might also depend on
> this
> information being available.
>
> Signed-off-by: Werner Sembach
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 2 ++
> drivers/gpu/drm/drm_connector.c | 46 +++
> include/drm/drm_connector.h | 13 +
> 3 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 7ae4e40936b5..bb78da2405f9 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -875,6 +875,8 @@ drm_atomic_connector_get_property(struct drm_connector
> *connector,
> *val = state->max_requested_bpc;
> } else if (property == connector->active_bpc_property) {
> *val = state->active_bpc;
> + } else if (property == connector->active_color_format_property) {
> + *val = state->active_color_format;
> } else if (connector->funcs->atomic_get_property) {
> return connector->funcs->atomic_get_property(connector,
> state, property, val);
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index c0c3c09bfed0..f4f35c4117b6 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -887,6 +887,14 @@ static const struct drm_prop_enum_list
> drm_dp_subconnector_enum_list[] = {
> { DRM_MODE_SUBCONNECTOR_Native, "Native"}, /* DP */
> };
>
> +static const struct drm_prop_enum_list drm_color_format_enum_list[] = {
> + { 0, "none" },
> + { DRM_COLOR_FORMAT_RGB444, "rgb" },
> + { DRM_COLOR_FORMAT_YCRCB444, "ycbcr444" },
> + { DRM_COLOR_FORMAT_YCRCB422, "ycbcr422" },
> + { DRM_COLOR_FORMAT_YCRCB420, "ycbcr420" },
> +};
> +
> DRM_ENUM_NAME_FN(drm_get_dp_subconnector_name,
>drm_dp_subconnector_enum_list)
>
> @@ -1202,6 +1210,14 @@ static const struct drm_prop_enum_list
> dp_colorspaces[] = {
> * display engine and connected monitor, and the "max bpc" property.
> * Drivers shall use drm_connector_attach_active_bpc_property() to install
> * this property.
> +
> + * active color format:
> + * This read-only property tells userspace the color format actually used
> + * by the hardware display engine on "the cable" on a connector. The chosen
> + * value depends on hardware capabilities, both display engine and
> + * connected monitor. Drivers shall use
> + * drm_connector_attach_active_color_format_property() to install this
> + * property.
Hi,
I think also the enum values should be documented in the UAPI docs. Or
listed at the very least. Otherwise userspace developers "do not know"
what strings to decode.
Thanks,
pq
> *
> * Connectors also have one standardized atomic property:
> *
> @@ -2191,6 +2207,36 @@ int drm_connector_attach_active_bpc_property(struct
> drm_connector *connector,
> }
> EXPORT_SYMBOL(drm_connector_attach_active_bpc_property);
>
> +/**
> + * drm_connector_attach_active_color_format_property - attach "active color
> format" property
> + * @connector: connector to attach active color format property on.
> + *
> + * This is used to check the applied color format on a connector.
> + *
> + * Returns:
> + * Zero on success, negative errno on failure.
> + */
> +int drm_connector_attach_active_color_format_property(struct drm_connector
> *connector)
> +{
> + struct drm_device *dev = connector->dev;
> + struct drm_property *prop;
> +
> + prop = connector->active_color_format_property;
> + if (!prop) {
> + prop = drm_property_create_enum(dev, 0, "active color format",
> drm_color_format_enum_list, ARRAY_SIZE(drm_color_format_enum_list));
> + if (!prop)
> + return -ENOMEM;
> +
> + connector->active_color_format_property = prop;
> + }
> +
> + drm_object_attach_property(>base, prop, 0);
> + connector->state->active_color_format = 0;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_connector_attach_active_color_format_property);
> +
> /**
> * drm_connector_set_vrr_capable_property - sets the variable refresh rate
> * capable property for a connector
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index c58cba2b6afe..167cd36129ae 100644
> --- a/include/drm/drm_connector.h
>
[pull] amdgpu, radeon drm-fixes-5.13
Hi Dave, Daniel, Fixes for 5.13. The following changes since commit 614124bea77e452aa6df7a8714e8bc820b489922: Linux 5.13-rc5 (2021-06-06 15:47:27 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-5.13-2021-06-09 for you to fetch changes up to ab8363d3875a83f4901eb1cc00ce8afd24de6c85: radeon: use memcpy_to/fromio for UVD fw upload (2021-06-08 14:05:11 -0400) amd-drm-fixes-5.13-2021-06-09: amdgpu: - Use kvzmalloc in amdgu_bo_create - Use drm_dbg_kms for reporting failure to get a GEM FB - Fix some register offsets for Sienna Cichlid - Fix fall-through warning radeon: - memcpy_to/from_io fixes Changfeng (1): drm/amdgpu: switch kzalloc to kvzalloc in amdgpu_bo_create Chen Li (1): radeon: use memcpy_to/fromio for UVD fw upload Gustavo A. R. Silva (1): drm/amd/pm: Fix fall-through warning for Clang Michel Dänzer (1): drm/amdgpu: Use drm_dbg_kms for reporting failure to get a GEM FB Rohit Khaire (1): drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid drivers/gpu/drm/amd/amdgpu/amdgpu_display.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +- .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 1 + drivers/gpu/drm/radeon/radeon_uvd.c| 4 ++-- 5 files changed, 28 insertions(+), 11 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2 2/7] drm/uAPI: Add "active bpc" as feedback channel for "max bpc" drm property
On Tue, 8 Jun 2021 19:43:15 +0200
Werner Sembach wrote:
> Add a new general drm property "active bpc" which can be used by graphic
> drivers
> to report the applied bit depth per pixel back to userspace.
>
> While "max bpc" can be used to change the color depth, there was no way to
> check
> which one actually got used. While in theory the driver chooses the
> best/highest
> color depth within the max bpc setting a user might not be fully aware what
> his
> hardware is or isn't capable off. This is meant as a quick way to double check
> the setup.
>
> In the future, automatic color calibration for screens might also depend on
> this
> information being available.
>
> Signed-off-by: Werner Sembach
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 2 ++
> drivers/gpu/drm/drm_connector.c | 41 +++
> include/drm/drm_connector.h | 15 +++
> 3 files changed, 58 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 268bb69c2e2f..7ae4e40936b5 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -873,6 +873,8 @@ drm_atomic_connector_get_property(struct drm_connector
> *connector,
> *val = 0;
> } else if (property == connector->max_bpc_property) {
> *val = state->max_requested_bpc;
> + } else if (property == connector->active_bpc_property) {
> + *val = state->active_bpc;
> } else if (connector->funcs->atomic_get_property) {
> return connector->funcs->atomic_get_property(connector,
> state, property, val);
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 7631f76e7f34..c0c3c09bfed0 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -1195,6 +1195,14 @@ static const struct drm_prop_enum_list
> dp_colorspaces[] = {
> * drm_connector_attach_max_bpc_property() to create and attach the
> * property to the connector during initialization.
> *
> + * active bpc:
> + * This read-only range property tells userspace the pixel color bit depth
> + * actually used by the hardware display engine on "the cable" on a
> + * connector. The chosen value depends on hardware capabilities, both
> + * display engine and connected monitor, and the "max bpc" property.
> + * Drivers shall use drm_connector_attach_active_bpc_property() to install
> + * this property.
> + *
This description is now clear to me, but I wonder, is it also how
others understand it wrt. dithering?
Dithering done on monitor is irrelevant, because we are talking about
"on the cable" pixels. But since we are talking about "on the cable"
pixels, also dithering done by the display engine must not factor in.
Should the dithering done by display engine result in higher "active
bpc" number than what is actually transmitted on the cable?
I cannot guess what userspace would want exactly. I think the
strict "on the cable" interpretation is a safe bet, because it then
gives a lower limit on observed bpc. Dithering settings should be
exposed with other KMS properties, so userspace can factor those in.
But to be absolutely sure, we'd have to ask some color management
experts.
Cc'ing Mario in case he has an opinion.
Since "active bpc" is related to "max bpc", the both should follow the
same definition. Do they do that now?
Maybe a clarifying note about interaction with dithering would still be
good to have here.
I recall reading some comments from you about having problems with
making this immutable. Is it properly immutable now?
That is, drm_info reports the property as "(immutable)".
https://github.com/ascent12/drm_info
If we are not sure if DSC could result in lower observed bpc than
"active bpc", then DSC state would need to be exposed as a KMS property
too, with a note that it invalidates what "active bpc" shows. Or maybe
"active bpc" should be "unknown" in that case?
Thanks,
pq
> * Connectors also have one standardized atomic property:
> *
> * CRTC_ID:
> @@ -2150,6 +2158,39 @@ int drm_connector_attach_max_bpc_property(struct
> drm_connector *connector,
> }
> EXPORT_SYMBOL(drm_connector_attach_max_bpc_property);
>
> +/**
> + * drm_connector_attach_active_bpc_property - attach "active bpc" property
> + * @connector: connector to attach active bpc property on.
> + * @min: The minimum bit depth supported by the connector.
> + * @max: The maximum bit depth supported by the connector.
> + *
> + * This is used to check the applied bit depth on a connector.
> + *
> + * Returns:
> + * Zero on success, negative errno on failure.
> + */
> +int drm_connector_attach_active_bpc_property(struct drm_connector *connector,
> + int min, int max)
> +{
> + struct drm_device *dev = connector->dev;
> + struct drm_property *prop;
> +
> + prop = connector->active_bpc_property;
[pull] amdgpu, amdkfd, radeon drm-next-5.14
Hi Dave, Daniel, More new stuff for 5.14. The following changes since commit 5745d647d5563d3e9d32013ad4e5c629acff04d7: Merge tag 'amd-drm-next-5.14-2021-06-02' of https://gitlab.freedesktop.org/agd5f/linux into drm-next (2021-06-04 06:13:57 +1000) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-5.14-2021-06-09 for you to fetch changes up to 2c1b1ac7084edf477309d27c02d9da7f79b33cec: drm/amdgpu/vcn: drop gfxoff control for VCN2+ (2021-06-09 22:15:02 -0400) amd-drm-next-5.14-2021-06-09: amdgpu: - SR-IOV fixes - Smartshift updates - GPUVM TLB flush updates - 16bpc fixed point display fix for DCE11 - BACO cleanups and core refactoring - Aldebaran updates - Initial Yellow Carp support - RAS fixes - PM API cleanup - DC visual confirm updates - DC DP MST fixes - DC DML fixes - Misc code cleanups and bug fixes amdkfd: - Initial Yellow Carp support radeon: - memcpy_to/from_io fixes UAPI: - Add Yellow Carp chip family id Used internally in the kernel driver and by mesa Aaron Liu (42): drm/amdgpu: add yellow carp asic header files (v3) drm/amdgpu: add yellow carp asic_type enum drm/amdgpu: add uapi to define yellow carp series drm/amdgpu: add yellow carp support for gpu_info and ip block setting drm/amdgpu: add nv common ip block support for yellow carp drm/amdgpu: add yellow carp support for ih block drm/amdgpu: add gmc v10 supports for yellow carp drm/amdgpu: support fw load type for yellow carp drm/amdgpu: add gfx support for yellow carp drm/amdgpu: add sdma support for yellow carp drm/amdgpu: set ip blocks for yellow carp drm/amdkfd: add yellow carp KFD support drm/amdgpu: support nbio_7_2_1 for yellow carp drm/admgpu/pm: add smu v13 driver interface header for yellow carp (v3) drm/amdgpu/pm: add smu v13.0.1 firmware header for yellow carp (V4) drm/amdgpu/pm: add smu v13.0.1 smc header for yellow carp (v2) drm/amd/pm: add smu13 ip support for moment(V3) drm/amd/pm: add yellow_carp_ppt implementation(V3) drm/amd/pm: partially enable swsmu for yellow carp(V2) drm/amdgpu: add smu ip block for yellow carp(V3) drm/amdgpu: add gfx golden settings for yellow carp (v3) drm/amdgpu: reserved buffer is not needed with ip discovery enabled drm/amdgpu: add psp_v13 support for yellow carp drm/amdgpu: enable psp_v13 for yellow carp drm/amdgpu/pm: set_pp_feature is unsupport for yellow carp drm/amdgpu/pm: add set_driver_table_location implementation for yellow carp drm/amdgpu: add GFX Clock Gating support for yellow carp drm/amdgpu: add MMHUB Clock Gating support for yellow carp drm/amdgpu: add GFX Power Gating support for yellow carp drm/amdgpu/pm: enable smu_hw_init for yellow carp drm/amdgpu/pm: add gfx_off_control for yellow carp drm/amdgpu/pm: enable gfx_off in yellow carp smu post init drm/amdgpu: add SDMA Clock Gating support for yellow carp drm/amdgpu: add HDP Clock Gating support for yellow carp drm/amdgpu: add ATHUB Clock Gating support for yellow carp drm/amdgpu: add IH Clock Gating support for yellow carp drm/amdgpu: enable VCN PG and CG for yellow carp drm/amdgpu/pm: support smu_post_init for yellow carp drm/amdgpu: add RLC_PG_DELAY_3 for yellow carp drm/amdgpu: add timestamp counter query support for yellow carp drm/amd/pm: add PrepareMp1ForUnload support for yellow carp drm/amdgpu: add mode2 reset support for yellow carp Alex Deucher (5): drm/amdgpu: add yellow_carp_reg_base_init function for yellow carp (v2) drm/amdgpu: add mmhub client support for yellow carp drm/amdgpu/dc: fix DCN3.1 Makefile for PPC64 drm/amdgpu/dc: fix DCN3.1 FP handling drm/amdgpu/vcn: drop gfxoff control for VCN2+ Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.68 Aric Cyr (4): drm/amd/display: Change default policy for MPO with multidisplay drm/amd/display: 3.2.138 drm/amd/display: Fix crash during MPO + ODM combine mode recalculation drm/amd/display: 3.2.139 Bernard Zhao (1): drm/amd/display: remove no need variable Changfeng (1): drm/amdgpu: switch kzalloc to kvzalloc in amdgpu_bo_create Chen Li (2): radeon: fix coding issues reported from sparse radeon: use memcpy_to/fromio for UVD fw upload Christian König (1): drm/amdgpu: fix VM handling for GART allocations Christophe JAILLET (1): drm/amdgpu: Fix a a typo in a comment Colin Ian King (3): drm/amdgpu: remove redundant assignment of variable k drm/amd/display: remove variable active_disp drm/amd/display: Fix two spelling mistakes, clean wide lines Darren Powell (6): amdgpu/pm: reorder
Re: [PATCH] drm/amdgpu: use adev_to_drm macro for consistency (v2)
Am 10.06.21 um 04:47 schrieb Guchun Chen: Use adev_to_drm() to get to the drm_device pointer. Signed-off-by: Guchun Chen Reviewed-by: Luben Tuikov Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 016815b7a773..fb6bcc386de1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -639,7 +639,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, } } - gobj = amdgpu_gem_prime_import(>ddev, mem->dmabuf); + gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf); if (IS_ERR(gobj)) return PTR_ERR(gobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index ec936cde2726..bfbcb9ff2453 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2122,7 +2122,7 @@ static void amdgpu_ras_counte_dw(struct work_struct *work) struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, ras_counte_delay_work.work); struct amdgpu_device *adev = con->adev; - struct drm_device *dev = >ddev; + struct drm_device *dev = adev_to_drm(adev->ddev); unsigned long ce_count, ue_count; int res; ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: use adev_to_drm macro for consistency (v2)
Am 2021-06-09 um 10:47 p.m. schrieb Guchun Chen: > Use adev_to_drm() to get to the drm_device pointer. > > Signed-off-by: Guchun Chen > Reviewed-by: Luben Tuikov > Reviewed-by: Alex Deucher Reviewed-by: Felix Kuehling > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > index 016815b7a773..fb6bcc386de1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > @@ -639,7 +639,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct > kgd_mem *mem, > } > } > > - gobj = amdgpu_gem_prime_import(>ddev, mem->dmabuf); > + gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf); > if (IS_ERR(gobj)) > return PTR_ERR(gobj); > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index ec936cde2726..bfbcb9ff2453 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -2122,7 +2122,7 @@ static void amdgpu_ras_counte_dw(struct work_struct > *work) > struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, > ras_counte_delay_work.work); > struct amdgpu_device *adev = con->adev; > - struct drm_device *dev = >ddev; > + struct drm_device *dev = adev_to_drm(adev->ddev); > unsigned long ce_count, ue_count; > int res; > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: use adev_to_drm macro for consistency (v2)
Use adev_to_drm() to get to the drm_device pointer. Signed-off-by: Guchun Chen Reviewed-by: Luben Tuikov Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 016815b7a773..fb6bcc386de1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -639,7 +639,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, } } - gobj = amdgpu_gem_prime_import(>ddev, mem->dmabuf); + gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf); if (IS_ERR(gobj)) return PTR_ERR(gobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index ec936cde2726..bfbcb9ff2453 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2122,7 +2122,7 @@ static void amdgpu_ras_counte_dw(struct work_struct *work) struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, ras_counte_delay_work.work); struct amdgpu_device *adev = con->adev; - struct drm_device *dev = >ddev; + struct drm_device *dev = adev_to_drm(adev->ddev); unsigned long ce_count, ue_count; int res; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: use adev_to_drm to get drm_device
[Public] Thanks for your kind feedback, Luben, Felix and Alex. I will send a v2 set with your comments addressed and RB added. Regards, Guchun -Original Message- From: Tuikov, Luben Sent: Thursday, June 10, 2021 1:06 AM To: Alex Deucher ; Chen, Guchun Cc: amd-gfx list ; Kuehling, Felix Subject: Re: [PATCH] drm/amdgpu: use adev_to_drm to get drm_device That's exactly what I said, but can see that 1/2 of the responses went to amd-gfx, and the other half to brahma ML. Regards, Luben On 2021-06-09 11:38 a.m., Alex Deucher wrote: > On Wed, Jun 9, 2021 at 5:23 AM Guchun Chen wrote: >> Fixes: >> 9faf262c32d3 drm/amdgpu: Add DMA mapping of GTT BOs >> 090f3a60d7e8 drm/amdgpu: Use delayed work to collect RAS error >> counters >> > drop the fixes lines and say something like use the adev_to_drm() > macro for consistency. With that, > Reviewed-by: Alex Deucher > >> Signed-off-by: Guchun Chen >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- >> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- >> 2 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c >> index 016815b7a773..fb6bcc386de1 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c >> @@ -639,7 +639,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct >> kgd_mem *mem, >> } >> } >> >> - gobj = amdgpu_gem_prime_import(>ddev, mem->dmabuf); >> + gobj = amdgpu_gem_prime_import(adev_to_drm(adev), >> + mem->dmabuf); >> if (IS_ERR(gobj)) >> return PTR_ERR(gobj); >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c >> index ec936cde2726..bfbcb9ff2453 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c >> @@ -2122,7 +2122,7 @@ static void amdgpu_ras_counte_dw(struct work_struct >> *work) >> struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, >> ras_counte_delay_work.work); >> struct amdgpu_device *adev = con->adev; >> - struct drm_device *dev = >ddev; >> + struct drm_device *dev = adev_to_drm(adev->ddev); >> unsigned long ce_count, ue_count; >> int res; >> >> -- >> 2.17.1 >> >> ___ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis >> ts.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7C >> luben.tuikov%40amd.com%7C04e4afbe1642484eb15008d92b5ca67d%7C3dd8961fe >> 4884e608e11a82d994e183d%7C0%7C0%7C637588499214061155%7CUnknown%7CTWFp >> bGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6M >> n0%3D%7C1000sdata=DvbjnGu0Lafx%2FgCIejsFJgMyngl9bKIvIdLjTngQrCM% >> 3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
