Re: [PATCH] drm/amdgpu/pm: Don't show pp_power_profile_mode for YC and later APUs
[Public] Instead of ASIC check better to do the check based on ppt_func->get_power_profile_mode. If function is NULL/not implemented, drop the attribute. Thanks, Lijo
Re: amdgpu "Fatal error during GPU init"; Ryzen 5600G integrated GPU + kernel 5.14.13
I got this comment from ASRockRack support re: the 'purple' screen: " Did you also get that background color in the BIOS menu? If not, it appears that this is the color may have something to do with video driver and it seems to be common with open source operating system. I came across these two forums with similar experience, there are some solution mentioned that might help you fix the driver issue. https://forums.linuxmint.com/viewtopic.php?t=202548 https://askubuntu.com/questions/1219150/ubuntu-19-10-stuck-at-purple-screen-during-boot-using-kvm " Doesn't seem like either of those two are a specific fit. But the point is that ASRockRack is suggesting it's the driver/config.
RE: [PATCH v2] drm/amd/display: Look at firmware version to determine using dmub on dcn21
[Public]
> -Original Message-
> From: Alex Deucher
> Sent: Friday, October 29, 2021 4:34 PM
> To: Limonciello, Mario
> Cc: amd-gfx list ; Li, Roman
>
> Subject: Re: [PATCH v2] drm/amd/display: Look at firmware version to
> determine using dmub on dcn21
>
> On Fri, Oct 29, 2021 at 4:33 PM Mario Limonciello
> wrote:
> >
> > commit b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all
> > dcn21
> > asics") switched over to using dmub on Renoir to fix Gitlab 1735, but
> > this implied a new dependency on newer firmware which might not be met
> > on older kernel versions.
> >
> > Since sw_init runs before hw_init, there is an opportunity to
> > determine whether or not the firmware version is new to adjust the behavior.
> >
> > Cc: roman...@amd.com
> > BugLink:
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitl
> > ab.freedesktop.org%2Fdrm%2Famd%2F-
> %2Fissues%2F1772data=04%7C01%7C
> >
> Roman.Li%40amd.com%7C4e27c983112e4ffdd36008d99b1b860a%7C3dd8961f
> e4884e
> >
> 608e11a82d994e183d%7C0%7C0%7C637711364793611804%7CUnknown%7CT
> WFpbGZsb3
> >
> d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7
> >
> C1000sdata=cFwunb4aAJbFkCe6lIFMY4oWfbkCVWAGshe8lB0rg0U%3D&
> amp;res
> > erved=0
> > BugLink:
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitl
> > ab.freedesktop.org%2Fdrm%2Famd%2F-
> %2Fissues%2F1735data=04%7C01%7C
> >
> Roman.Li%40amd.com%7C4e27c983112e4ffdd36008d99b1b860a%7C3dd8961f
> e4884e
> >
> 608e11a82d994e183d%7C0%7C0%7C637711364793611804%7CUnknown%7CT
> WFpbGZsb3
> >
> d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7
> >
> C1000sdata=%2F9sfVD5PN2tsl0bXkctPzkrHpJKQoZDex8xCDt1bVPg%3D&
> amp;r
> > eserved=0
> > Fixes: b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all
> > dcn21 asics")
> > Signed-off-by: Mario Limonciello
>
> Acked-by: Alex Deucher
>
> > ---
> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 6dd6262f2769..e7ff8ad4c5a7 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -1410,7 +1410,10 @@ static int amdgpu_dm_init(struct amdgpu_device
> *adev)
> > switch (adev->ip_versions[DCE_HWIP][0]) {
> > case IP_VERSION(2, 1, 0):
> > init_data.flags.gpu_vm_support = true;
> > + if
> > + (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> > init_data.flags.disable_dmcu = true;
> > + else
> > + init_data.flags.disable_dmcu =
> > + adev->dm.dmcub_fw_version > 0x0100;
Since this is the only fw version that needs dmcu, it's safer to use equal
condition here.
> > break;
> > case IP_VERSION(1, 0, 0):
> > case IP_VERSION(1, 0, 1):
> > --
> > 2.25.1
> >
Re: amdgpu "Fatal error during GPU init"; Ryzen 5600G integrated GPU + kernel 5.14.13
in case it's useful grep -i amd /var/log/Xorg.0.log | grep -v Modeline [ 324.709] (II) Applying OutputClass "AMDgpu" to /dev/dri/card0 [ 324.709]loading driver: amdgpu [ 324.818] (==) Matched amdgpu as autoconfigured driver 0 [ 324.818] (II) LoadModule: "amdgpu" [ 324.825] (II) Loading /usr/lib64/xorg/modules/drivers/amdgpu_drv.so [ 324.877] (II) Module amdgpu: vendor="X.Org Foundation" [ 324.992] (II) AMDGPU: Driver for AMD Radeon: All GPUs supported by the amdgpu kernel driver [ 325.108] (II) Loading sub module "ramdac" [ 325.108] (II) LoadModule: "ramdac" [ 325.108] (II) Module "ramdac" already built-in [ 325.110] (II) AMDGPU(0): Creating default Display subsection in Screen section [ 325.110] (==) AMDGPU(0): Depth 24, (--) framebuffer bpp 32 [ 325.110] (II) AMDGPU(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) [ 325.110] (==) AMDGPU(0): Default visual is TrueColor [ 325.110] (==) AMDGPU(0): RGB weight 888 [ 325.110] (II) AMDGPU(0): Using 8 bits per RGB (8 bit DAC) [ 325.110] (--) AMDGPU(0): Chipset: "Unknown AMD Radeon GPU" (ChipID = 0x1638) [ 327.957] (II) AMDGPU(0): glamor X acceleration enabled on AMD RENOIR (DRM 3.42.0, 5.14.14-200.fc34.x86_64, LLVM 12.0.1) [ 327.957] (II) AMDGPU(0): glamor detected, initialising EGL layer. [ 327.957] (==) AMDGPU(0): TearFree property default: auto [ 327.957] (==) AMDGPU(0): VariableRefresh: disabled [ 327.957] (II) AMDGPU(0): KMS Pageflipping: enabled [ 327.957] (II) AMDGPU(0): Output HDMI-A-0 has no monitor section [ 327.958] (II) AMDGPU(0): Output HDMI-A-1 has no monitor section [ 327.958] (II) AMDGPU(0): Output DisplayPort-0 has no monitor section [ 327.963] (II) AMDGPU(0): EDID for output HDMI-A-0 [ 327.963] (II) AMDGPU(0): EDID for output HDMI-A-1 [ 327.963] (II) AMDGPU(0): Manufacturer: VSC Model: cc32 Serial#: 16843025 [ 327.963] (II) AMDGPU(0): Year: 2018 Week: 47 [ 327.963] (II) AMDGPU(0): EDID Version: 1.3 [ 327.963] (II) AMDGPU(0): Digital Display Input [ 327.963] (II) AMDGPU(0): Max Image Size [cm]: horiz.: 60 vert.: 34 [ 327.963] (II) AMDGPU(0): Gamma: 2.20 [ 327.963] (II) AMDGPU(0): DPMS capabilities: Off [ 327.963] (II) AMDGPU(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 [ 327.963] (II) AMDGPU(0): Default color space is primary color space [ 327.963] (II) AMDGPU(0): First detailed timing is preferred mode [ 327.963] (II) AMDGPU(0): redX: 0.661 redY: 0.332 greenX: 0.304 greenY: 0.613 [ 327.963] (II) AMDGPU(0): blueX: 0.149 blueY: 0.060 whiteX: 0.313 whiteY: 0.329 [ 327.963] (II) AMDGPU(0): Supported established timings: [ 327.963] (II) AMDGPU(0): 720x400@70Hz [ 327.963] (II) AMDGPU(0): 640x480@60Hz [ 327.963] (II) AMDGPU(0): 640x480@67Hz [ 327.963] (II) AMDGPU(0): 640x480@72Hz [ 327.963] (II) AMDGPU(0): 640x480@75Hz [ 327.963] (II) AMDGPU(0): 800x600@56Hz [ 327.963] (II) AMDGPU(0): 800x600@60Hz [ 327.963] (II) AMDGPU(0): 800x600@72Hz [ 327.963] (II) AMDGPU(0): 800x600@75Hz [ 327.964] (II) AMDGPU(0): 832x624@75Hz [ 327.964] (II) AMDGPU(0): 1024x768@60Hz [ 327.964] (II) AMDGPU(0): 1024x768@70Hz [ 327.964] (II) AMDGPU(0): 1024x768@75Hz [ 327.964] (II) AMDGPU(0): 1280x1024@75Hz [ 327.964] (II) AMDGPU(0): 1152x864@75Hz [ 327.964] (II) AMDGPU(0): Manufacturer's mask: 0 [ 327.964] (II) AMDGPU(0): Supported standard timings: [ 327.964] (II) AMDGPU(0): #0: hsize: 2048 vsize 1152 refresh: 60 vid: 49377 [ 327.964] (II) AMDGPU(0): #1: hsize: 1920 vsize 1200 refresh: 60 vid: 209 [ 327.964] (II) AMDGPU(0): #2: hsize: 1920 vsize 1080 refresh: 60 vid: 49361 [ 327.964] (II) AMDGPU(0): #3: hsize: 1680 vsize 1050 refresh: 60 vid: 179 [ 327.964] (II) AMDGPU(0): #4: hsize: 1600 vsize 900 refresh: 60 vid: 49321 [ 327.964] (II) AMDGPU(0): #5: hsize: 1280 vsize 1024 refresh: 60 vid: 32897 [ 327.964] (II) AMDGPU(0): #6: hsize: 1280
Re: amdgpu "Fatal error during GPU init"; Ryzen 5600G integrated GPU + kernel 5.14.13
I would start with an sbios update is possible. I swapped out the ASRockRack X470D4U mobo for a new, next-gen X570D4U. Keeping the same 2X16GB UDIMMs, and trying 2 different Ryzen 5600G CPUs, I now see the following ... With an NVIDIA PCIe card as primary adapter, it posts & functions, as before; no issues or problems. Selecting the on-die AMDGPU, via the board's HDMI connector, now also posts & boots; No more OOPS. Booting, now on uname -rm 5.14.14-200.fc34.x86_64 x86_64 dmesg @ boot is: dmesg | grep -i amdgpu [1.623977] [drm] amdgpu kernel modesetting enabled. [1.627731] amdgpu: Virtual CRAT table created for CPU [1.627738] amdgpu: Topology: Add CPU node [1.627782] fb0: switching to amdgpudrmfb from EFI VGA [1.627910] amdgpu :30:00.0: vgaarb: deactivate vga console [1.627972] amdgpu :30:00.0: amdgpu: Trusted Memory Zone (TMZ) feature enabled [1.634655] amdgpu :30:00.0: amdgpu: Fetched VBIOS from ROM BAR [1.634656] amdgpu: ATOM BIOS: 113-CEZANNE-018 [1.635463] amdgpu :30:00.0: amdgpu: VRAM: 512M 0x00F4 - 0x00F41FFF (512M used) [1.635465] amdgpu :30:00.0: amdgpu: GART: 1024M 0x - 0x3FFF [1.635466] amdgpu :30:00.0: amdgpu: AGP: 267419648M 0x00F8 - 0x [1.635504] [drm] amdgpu: 512M of VRAM memory ready [1.635505] [drm] amdgpu: 3072M of GTT memory ready. [1.639127] amdgpu :30:00.0: amdgpu: PSP runtime database doesn't exist [1.667936] amdgpu :30:00.0: amdgpu: Will use PSP to load VCN firmware [2.469604] amdgpu :30:00.0: amdgpu: RAS: optional ras ta ucode is not available [2.477996] amdgpu :30:00.0: amdgpu: RAP: optional rap ta ucode is not available [2.477999] amdgpu :30:00.0: amdgpu: SECUREDISPLAY: securedisplay ta ucode is not available [2.478948] amdgpu :30:00.0: amdgpu: SMU is initialized successfully! [2.530805] kfd kfd: amdgpu: Allocated 3969056 bytes on gart [2.758719] amdgpu: HMM registered 512MB device memory [2.758741] amdgpu: SRAT table not found [2.758741] amdgpu: Virtual CRAT table created for GPU [2.758942] amdgpu: Topology: Add dGPU node [0x1638:0x1002] [2.758944] kfd kfd: amdgpu: added device 1002:1638 [2.758958] amdgpu :30:00.0: amdgpu: SE 1, SH per SE 2, CU per SH 18, active_cu_number 27 [2.949242] fbcon: amdgpu (fb0) is primary device [3.052240] amdgpu :30:00.0: [drm] fb0: amdgpu frame buffer device [3.061026] amdgpu :30:00.0: amdgpu: ring gfx uses VM inv eng 0 on hub 0 [3.061030] amdgpu :30:00.0: amdgpu: ring comp_1.0.0 uses VM inv eng 1 on hub 0 [3.061031] amdgpu :30:00.0: amdgpu: ring comp_1.1.0 uses VM inv eng 4 on hub 0 [3.061032] amdgpu :30:00.0: amdgpu: ring comp_1.2.0 uses VM inv eng 5 on hub 0 [3.061032] amdgpu :30:00.0: amdgpu: ring comp_1.3.0 uses VM inv eng 6 on hub 0 [3.061033] amdgpu :30:00.0: amdgpu: ring comp_1.0.1 uses VM inv eng 7 on hub 0 [3.061034] amdgpu :30:00.0: amdgpu: ring comp_1.1.1 uses VM inv eng 8 on hub 0 [3.061034] amdgpu :30:00.0: amdgpu: ring comp_1.2.1 uses VM inv eng 9 on hub 0 [3.061035] amdgpu :30:00.0: amdgpu: ring comp_1.3.1 uses VM inv eng 10 on hub 0 [3.061036] amdgpu :30:00.0: amdgpu: ring kiq_2.1.0 uses VM inv eng 11 on hub 0 [3.061037] amdgpu :30:00.0: amdgpu: ring sdma0 uses VM inv eng 0 on hub 1 [3.061038] amdgpu :30:00.0: amdgpu: ring vcn_dec uses VM inv eng 1 on hub 1 [3.061039] amdgpu :30:00.0: amdgpu: ring vcn_enc0 uses VM inv eng 4 on hub 1 [3.061039] amdgpu :30:00.0: amdgpu: ring vcn_enc1 uses VM inv eng 5 on hub 1 [3.061040] amdgpu :30:00.0: amdgpu: ring jpeg_dec uses VM inv eng 6 on hub 1 [3.209226] [drm] Initialized amdgpu 3.42.0 20150101 for :30:00.0 on minor 0 [ 13.749477] snd_hda_intel :30:00.1: bound :30:00.0 (ops amdgpu_dm_audio_component_bind_ops [amdgpu]) However, now, the output color registration is wrong. After grub selection, boot shell background is pink/magenta everywhere. Screenshot here: https://imgur.com/q2JJ4n6 If I continue from shell to launch a desktop
[PATCH] drm/amdgpu/pm: Don't show pp_power_profile_mode for YC and later APUs
This command corresponding to this attribute was deprecated in the PMFW
for YC so don't show a non-functional attribute.
Since future APUs may be brought up using IP version checking also
disable it for future APU's. If any do support the command then they
can be treated as exceptions.
Suggested-by: Alex Deucher
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 49fe4155c374..c7326f0ec517 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2094,6 +2094,9 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
if (!(asic_type == CHIP_VANGOGH || asic_type ==
CHIP_SIENNA_CICHLID))
*states = ATTR_STATE_UNSUPPORTED;
+ } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
+ if ((adev->flags & AMD_IS_APU) && asic_type >= CHIP_YELLOW_CARP)
+ *states = ATTR_STATE_UNSUPPORTED;
}
switch (asic_type) {
--
2.25.1
Re: [PATCH v2] drm/amdgpu/pm: drop pp_power_profile_mode support for yellow carp
On 10/29/2021 15:57, Alex Deucher wrote:
On Fri, Oct 29, 2021 at 11:34 AM Mario Limonciello
wrote:
This was added by commit bd8dcea93a7d ("drm/amd/pm: add callbacks to
read/write sysfs file pp_power_profile_mode") but the feature was
deprecated from PMFW. Remove it from the driver.
Signed-off-by: Mario Limonciello
Probably want something like the following too:
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index c255b4b8e685..c1b8ed9f7ba8 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2092,6 +2092,9 @@ static int default_attr_update(struct
amdgpu_device *adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
if (!(asic_type == CHIP_VANGOGH || asic_type ==
CHIP_SIENNA_CICHLID))
*states = ATTR_STATE_UNSUPPORTED;
+ } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
+ if (asic_type == CHIP_YELLOW_CARP)
+ *states = ATTR_STATE_UNSUPPORTED;
}
switch (asic_type) {
So we don't expose the sysfs knob on the YC, but that can be a follow
up patch if you want.
I guess for now something like that makes sense. I'll send a follow up.
Acked-by: Alex Deucher
---
Changes from v1->v2:
* Drop changes to RN and VGH as the deprecation is only in YC.
* Leave PPSMC_MSG_ActiveProcessNotify message but mark deprecated
* Rename PPSMC_MSG_SPARE0 to align to the name used by PMFW (PPSMC_MSG_SPARE)
.../gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h| 4 +-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 87 ---
2 files changed, 2 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
index 1d3447991d0c..fc9198846e70 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
@@ -51,7 +51,7 @@
#define PPSMC_MSG_PowerUpVcn0x07 ///< Power up VCN; VCN
is power gated by default
#define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless display
#define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for
GFXCLK, argument is frequency in MHz
-#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Set active work load
type
+#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Deprecated (Not to
be used)
#define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down
GFX, i.e. enter GFXOFF
#define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for
GFX driver unload
#define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of
DRAM address for Driver table transfer
@@ -63,7 +63,7 @@
#define PPSMC_MSG_SetHardMinSocclkByFreq0x13 ///< Set hard min for
SOC CLK
#define PPSMC_MSG_SetSoftMinFclk0x14 ///< Set hard min for
FCLK
#define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for
VCN clocks (VCLK and DCLK)
-#define PPSMC_MSG_SPARE00x16 ///< Spared
+#define PPSMC_MSG_SPARE 0x16 ///< Spare
#define PPSMC_MSG_GetGfxclkFrequency0x17 ///< Get GFX clock
frequency
#define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
#define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of
allowing GFXOFF entry
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index a403657151ba..8215bbf5ed7c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -64,7 +64,6 @@ static struct cmn2asic_msg_mapping
yellow_carp_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn,
1),
MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn,
1),
MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
1),
- MSG_MAP(ActiveProcessNotify,PPSMC_MSG_ActiveProcessNotify,
1),
MSG_MAP(PrepareMp1ForUnload,PPSMC_MSG_PrepareMp1ForUnload,
1),
MSG_MAP(SetDriverDramAddrHigh,
PPSMC_MSG_SetDriverDramAddrHigh,1),
MSG_MAP(SetDriverDramAddrLow,
PPSMC_MSG_SetDriverDramAddrLow, 1),
@@ -135,14 +134,6 @@ static struct cmn2asic_mapping
yellow_carp_table_map[SMU_TABLE_COUNT] = {
TAB_MAP_VALID(CUSTOM_DPM),
TAB_MAP_VALID(DPMCLOCKS),
};
-
-static struct cmn2asic_mapping
yellow_carp_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
- WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,
WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
- WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,
WORKLOAD_PPLIB_VIDEO_BIT),
- WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,
Re: [PATCH v2] drm/amdgpu/pm: drop pp_power_profile_mode support for yellow carp
On Fri, Oct 29, 2021 at 11:34 AM Mario Limonciello
wrote:
>
> This was added by commit bd8dcea93a7d ("drm/amd/pm: add callbacks to
> read/write sysfs file pp_power_profile_mode") but the feature was
> deprecated from PMFW. Remove it from the driver.
>
> Signed-off-by: Mario Limonciello
Probably want something like the following too:
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index c255b4b8e685..c1b8ed9f7ba8 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2092,6 +2092,9 @@ static int default_attr_update(struct
amdgpu_device *adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
if (!(asic_type == CHIP_VANGOGH || asic_type ==
CHIP_SIENNA_CICHLID))
*states = ATTR_STATE_UNSUPPORTED;
+ } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
+ if (asic_type == CHIP_YELLOW_CARP)
+ *states = ATTR_STATE_UNSUPPORTED;
}
switch (asic_type) {
So we don't expose the sysfs knob on the YC, but that can be a follow
up patch if you want.
Acked-by: Alex Deucher
> ---
> Changes from v1->v2:
> * Drop changes to RN and VGH as the deprecation is only in YC.
> * Leave PPSMC_MSG_ActiveProcessNotify message but mark deprecated
> * Rename PPSMC_MSG_SPARE0 to align to the name used by PMFW (PPSMC_MSG_SPARE)
>
> .../gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h| 4 +-
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 87 ---
> 2 files changed, 2 insertions(+), 89 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> index 1d3447991d0c..fc9198846e70 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
> @@ -51,7 +51,7 @@
> #define PPSMC_MSG_PowerUpVcn0x07 ///< Power up VCN; VCN
> is power gated by default
> #define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless
> display
> #define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for
> GFXCLK, argument is frequency in MHz
> -#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Set active work
> load type
> +#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Deprecated (Not to
> be used)
> #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down
> GFX, i.e. enter GFXOFF
> #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for
> GFX driver unload
> #define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits
> of DRAM address for Driver table transfer
> @@ -63,7 +63,7 @@
> #define PPSMC_MSG_SetHardMinSocclkByFreq0x13 ///< Set hard min for
> SOC CLK
> #define PPSMC_MSG_SetSoftMinFclk0x14 ///< Set hard min for
> FCLK
> #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for
> VCN clocks (VCLK and DCLK)
> -#define PPSMC_MSG_SPARE00x16 ///< Spared
> +#define PPSMC_MSG_SPARE 0x16 ///< Spare
> #define PPSMC_MSG_GetGfxclkFrequency0x17 ///< Get GFX clock
> frequency
> #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
> #define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of
> allowing GFXOFF entry
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index a403657151ba..8215bbf5ed7c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -64,7 +64,6 @@ static struct cmn2asic_msg_mapping
> yellow_carp_message_map[SMU_MSG_MAX_COUNT] =
> MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn,
> 1),
> MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn,
> 1),
> MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
> 1),
> - MSG_MAP(ActiveProcessNotify,
> PPSMC_MSG_ActiveProcessNotify, 1),
> MSG_MAP(PrepareMp1ForUnload,
> PPSMC_MSG_PrepareMp1ForUnload, 1),
> MSG_MAP(SetDriverDramAddrHigh,
> PPSMC_MSG_SetDriverDramAddrHigh,1),
> MSG_MAP(SetDriverDramAddrLow,
> PPSMC_MSG_SetDriverDramAddrLow, 1),
> @@ -135,14 +134,6 @@ static struct cmn2asic_mapping
> yellow_carp_table_map[SMU_TABLE_COUNT] = {
> TAB_MAP_VALID(CUSTOM_DPM),
> TAB_MAP_VALID(DPMCLOCKS),
> };
> -
> -static struct cmn2asic_mapping
> yellow_carp_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,
> WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,
> WORKLOAD_PPLIB_VIDEO_BIT),
> -
Re: [PATCH v2] drm/amd/display: Look at firmware version to determine using dmub on dcn21
On Fri, Oct 29, 2021 at 4:33 PM Mario Limonciello
wrote:
>
> commit b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
> asics") switched over to using dmub on Renoir to fix Gitlab 1735, but this
> implied a new dependency on newer firmware which might not be met on older
> kernel versions.
>
> Since sw_init runs before hw_init, there is an opportunity to determine
> whether or not the firmware version is new to adjust the behavior.
>
> Cc: roman...@amd.com
> BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1772
> BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1735
> Fixes: b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
> asics")
> Signed-off-by: Mario Limonciello
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 6dd6262f2769..e7ff8ad4c5a7 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1410,7 +1410,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> switch (adev->ip_versions[DCE_HWIP][0]) {
> case IP_VERSION(2, 1, 0):
> init_data.flags.gpu_vm_support = true;
> + if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> init_data.flags.disable_dmcu = true;
> + else
> + init_data.flags.disable_dmcu =
> adev->dm.dmcub_fw_version > 0x0100;
> break;
> case IP_VERSION(1, 0, 0):
> case IP_VERSION(1, 0, 1):
> --
> 2.25.1
>
[PATCH v2] drm/amd/display: Look at firmware version to determine using dmub on dcn21
commit b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
asics") switched over to using dmub on Renoir to fix Gitlab 1735, but this
implied a new dependency on newer firmware which might not be met on older
kernel versions.
Since sw_init runs before hw_init, there is an opportunity to determine
whether or not the firmware version is new to adjust the behavior.
Cc: roman...@amd.com
BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1772
BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1735
Fixes: b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
asics")
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6dd6262f2769..e7ff8ad4c5a7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1410,7 +1410,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 1, 0):
init_data.flags.gpu_vm_support = true;
+ if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
init_data.flags.disable_dmcu = true;
+ else
+ init_data.flags.disable_dmcu =
adev->dm.dmcub_fw_version > 0x0100;
break;
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
--
2.25.1
RE: [PATCH] drm/amd/display: Look at firmware version to determine using dmub on dcn21
[Public]
> -Original Message-
> From: Alex Deucher
> Sent: Friday, October 29, 2021 15:24
> To: Limonciello, Mario
> Cc: amd-gfx list ; Li, Roman
>
> Subject: Re: [PATCH] drm/amd/display: Look at firmware version to determine
> using dmub on dcn21
>
> On Fri, Oct 29, 2021 at 4:19 PM Alex Deucher wrote:
> >
> > On Fri, Oct 29, 2021 at 4:12 PM Mario Limonciello
> > wrote:
> > >
> > > commit b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
> > > asics") switched over to using dmub on Renoir to fix Gitlab 1735, but this
> > > implied a new dependency on newer firmware which might not be met on
> older
> > > kernel versions.
> > >
> > > Since sw_init runs before hw_init, there is an opportunity to determine
> > > whether or not the firmware version is new to adjust the behavior.
> > >
> > > Cc: roman...@amd.com
> > > BugLink:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.fr
> eedesktop.org%2Fdrm%2Famd%2F-
> %2Fissues%2F1772data=04%7C01%7Cmario.limonciello%40amd.com%7
> C03c84193638144254d6f08d99b1a147c%7C3dd8961fe4884e608e11a82d994e1
> 83d%7C0%7C0%7C637711358602513049%7CUnknown%7CTWFpbGZsb3d8eyJ
> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C
> 1000sdata=frHB0cKKTUHWxj0t8kFBBYTlGapT2dpqUOddJyuPeZ0%3D
> p;reserved=0
> > > BugLink:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.fr
> eedesktop.org%2Fdrm%2Famd%2F-
> %2Fissues%2F1735data=04%7C01%7Cmario.limonciello%40amd.com%7
> C03c84193638144254d6f08d99b1a147c%7C3dd8961fe4884e608e11a82d994e1
> 83d%7C0%7C0%7C637711358602522996%7CUnknown%7CTWFpbGZsb3d8eyJ
> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C
> 1000sdata=dOqYHWrdTNrJdqdTL1OFJHJVY8ntiLG%2BJzWSqGLSn5w%3D
> reserved=0
> > > Fixes: b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
> asics")
> > > Signed-off-by: Mario Limonciello
> >
> > Acked-by: Alex Deucher
>
> Actually if there are version differences between renoir and green
> sardine, maybe we need to bring back the old logic. E.g.,
> if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> init_data.flags.disable_dmcu = true;
> else
> init_data.flags.disable_dmcu = adev->dm.dmcub_fw_version > 0x0100;
>
Good point - I'll respin for that.
> Alex
>
> >
> > > ---
> > > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > index 6dd6262f2769..85b3de97f870 100644
> > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > @@ -1410,7 +1410,7 @@ static int amdgpu_dm_init(struct amdgpu_device
> *adev)
> > > switch (adev->ip_versions[DCE_HWIP][0]) {
> > > case IP_VERSION(2, 1, 0):
> > > init_data.flags.gpu_vm_support = true;
> > > - init_data.flags.disable_dmcu = true;
> > > + init_data.flags.disable_dmcu =
> > > adev->dm.dmcub_fw_version >
> 0x0100;
> > > break;
> > > case IP_VERSION(1, 0, 0):
> > > case IP_VERSION(1, 0, 1):
> > > --
> > > 2.25.1
> > >
Re: [PATCH] drm/amd/display: Look at firmware version to determine using dmub on dcn21
On Fri, Oct 29, 2021 at 4:19 PM Alex Deucher wrote:
>
> On Fri, Oct 29, 2021 at 4:12 PM Mario Limonciello
> wrote:
> >
> > commit b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
> > asics") switched over to using dmub on Renoir to fix Gitlab 1735, but this
> > implied a new dependency on newer firmware which might not be met on older
> > kernel versions.
> >
> > Since sw_init runs before hw_init, there is an opportunity to determine
> > whether or not the firmware version is new to adjust the behavior.
> >
> > Cc: roman...@amd.com
> > BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1772
> > BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1735
> > Fixes: b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
> > asics")
> > Signed-off-by: Mario Limonciello
>
> Acked-by: Alex Deucher
Actually if there are version differences between renoir and green
sardine, maybe we need to bring back the old logic. E.g.,
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
init_data.flags.disable_dmcu = true;
else
init_data.flags.disable_dmcu = adev->dm.dmcub_fw_version > 0x0100;
Alex
>
> > ---
> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 6dd6262f2769..85b3de97f870 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -1410,7 +1410,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> > switch (adev->ip_versions[DCE_HWIP][0]) {
> > case IP_VERSION(2, 1, 0):
> > init_data.flags.gpu_vm_support = true;
> > - init_data.flags.disable_dmcu = true;
> > + init_data.flags.disable_dmcu =
> > adev->dm.dmcub_fw_version > 0x0100;
> > break;
> > case IP_VERSION(1, 0, 0):
> > case IP_VERSION(1, 0, 1):
> > --
> > 2.25.1
> >
Re: [PATCH] drm/amd/display: Look at firmware version to determine using dmub on dcn21
On Fri, Oct 29, 2021 at 4:12 PM Mario Limonciello
wrote:
>
> commit b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
> asics") switched over to using dmub on Renoir to fix Gitlab 1735, but this
> implied a new dependency on newer firmware which might not be met on older
> kernel versions.
>
> Since sw_init runs before hw_init, there is an opportunity to determine
> whether or not the firmware version is new to adjust the behavior.
>
> Cc: roman...@amd.com
> BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1772
> BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1735
> Fixes: b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
> asics")
> Signed-off-by: Mario Limonciello
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 6dd6262f2769..85b3de97f870 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1410,7 +1410,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
> switch (adev->ip_versions[DCE_HWIP][0]) {
> case IP_VERSION(2, 1, 0):
> init_data.flags.gpu_vm_support = true;
> - init_data.flags.disable_dmcu = true;
> + init_data.flags.disable_dmcu =
> adev->dm.dmcub_fw_version > 0x0100;
> break;
> case IP_VERSION(1, 0, 0):
> case IP_VERSION(1, 0, 1):
> --
> 2.25.1
>
[PATCH] drm/amd/display: Look at firmware version to determine using dmub on dcn21
commit b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
asics") switched over to using dmub on Renoir to fix Gitlab 1735, but this
implied a new dependency on newer firmware which might not be met on older
kernel versions.
Since sw_init runs before hw_init, there is an opportunity to determine
whether or not the firmware version is new to adjust the behavior.
Cc: roman...@amd.com
BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1772
BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1735
Fixes: b1c61212d8dc ("drm/amd/display: Fully switch to dmub for all dcn21
asics")
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6dd6262f2769..85b3de97f870 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1410,7 +1410,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 1, 0):
init_data.flags.gpu_vm_support = true;
- init_data.flags.disable_dmcu = true;
+ init_data.flags.disable_dmcu =
adev->dm.dmcub_fw_version > 0x0100;
break;
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
--
2.25.1
[pull] amdgpu, amdkfd drm-next-5.16
Hi Dave, Daniel, Fixes for 5.16. The following changes since commit 31fa8cbce4664946a1688898410fee41ad05364d: drm: Add R10 and R12 FourCC (2021-10-28 17:20:45 +1000) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-5.16-2021-10-29 for you to fetch changes up to 403475be6d8b122c3e6b8a47e075926d7299e5ef: drm/amdgpu/gmc6: fix DMA mask from 44 to 40 bits (2021-10-28 14:27:00 -0400) amd-drm-next-5.16-2021-10-29: amdgpu: - RAS fixes - Fix a potential memory leak in device tear down - Add a stutter mode quirk - Misc display fixes - Further display FP refactoring - Display USB4 fixes - Display DP2.0 fixes - DCN 3.1 fixes - Display 8 ch audio fix - Fix DMA mask regression for SI parts - Aldebaran fixes amdkfd: - userptr fix - BO lifetime fix - Misc code cleanup UAPI: - Minor header cleanup (no functional change) Ahmad Othman (2): drm/amd/display: Add support for USB4 on C20 PHY for DCN3.1 drm/amd/display: fix a crash on USB4 over C20 PHY Alex Deucher (6): drm/amdgpu/display: add quirk handling for stutter mode drm/amdgpu/pm: look up current_level for asics without pm callback drm/amdgpu/UAPI: rearrange header to better align related items drm/amdgpu/discovery: add UVD/VCN IP instance info for soc15 parts drm/amdgpu/discovery: add SDMA IP instance info for soc15 parts drm/amdgpu/gmc6: fix DMA mask from 44 to 40 bits Anson Jacob (2): drm/amd/display: dcn20_resource_construct reduce scope of FPU enabled drm/amd/display: Remove unused macros Anthony Koo (2): drm/amd/display: [FW Promotion] Release 0.0.89 drm/amd/display: [FW Promotion] Release 0.0.90 Aric Cyr (4): drm/amd/display: Handle I2C-over-AUX write channel status update drm/amd/display: 3.2.158 drm/amd/display: Fix 3DLUT skipped programming drm/amd/display: 3.2.159 Candice Li (1): drm/amdgpu: Update TA version output in driver Dmytro Laktyushkin (3): drm/amd/display: clean up dcn31 revision check drm/amd/display: restyle dcn31 resource header inline with other asics drm/amd/display: allow windowed mpo + odm George Shen (2): drm/amd/display: Implement fixed DP drive settings drm/amd/display: Add comment for preferred_training_settings Guo, Bing (2): drm/amd/display: Get ceiling for v_total calc drm/amd/display: set Layout properly for 8ch audio at timing validation Hansen (1): drm/amd/display: Set phy_mux_sel bit in dmub scratch register Jimmy Kizito (1): drm/amd/display: Add workaround flag for EDID read on certain docks Jude Shih (2): drm/amd/display: Fix USB4 hot plug crash issue drm/amd/display: Enable dpia in dmub only for DCN31 B0 Kent Russell (2): drm/amdgpu: Warn when bad pages approaches 90% threshold drm/amdgpu: Add kernel parameter support for ignoring bad page threshold Lang Yu (4): drm/amdkfd: Separate pinned BOs destruction from general routine drm/amdgpu: fix a potential memory leak in amdgpu_device_fini_sw() drm/amdkfd: Add an optional argument into update queue operation(v2) drm/amdkfd: Remove cu mask from struct queue_properties(v2) Lewis Huang (1): drm/amd/display: Align bw context with hw config when system resume Martin Leung (1): drm/amd/display: Manually adjust strobe for DCN303 Meenakshikumar Somasundaram (3): drm/amd/display: FEC configuration for dpia links drm/amd/display: FEC configuration for dpia links in MST mode drm/amd/display: MST support for DPIA Michael Strauss (3): drm/amd/display: Set i2c memory to light sleep during hw init drm/amd/display: Defer GAMCOR and DSCL power down sequence to vupdate drm/amd/display: Fallback to clocks which meet requested voltage on DCN31 Nicholas Kazlauskas (1): drm/amd/display: Fix deadlock when falling back to v2 from v3 Patrik Jakobsson (1): drm/amdgpu: Fix even more out of bound writes from debugfs Philip Yang (1): drm/amdkfd: restore userptr ignore bad address error Qingqing Zhuo (2): drm/amd/display: move FPU associated DSC code to DML folder drm/amd/display: move FPU associated DCN301 code to DML folder Robin Chen (1): drm/amd/display: dc_link_set_psr_allow_active refactoring Tao Zhou (2): drm/amdgpu: skip GPRs init for some CU settings on ALDEBARAN drm/amdgpu: remove GPRs init for ALDEBARAN in gpu reset (v3) Wenjing Liu (5): drm/amd/display: adopt DP2.0 LT SCR revision 8 drm/amd/display: implement decide lane settings drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings drm/amd/display: add two lane settings training options drm/amd/display: fix link training regression for 1 or 2 lane drivers/gpu/drm/amd/amdgpu/amdgpu.h
Re: [PATCH v2 2/2] drm/amdkfd: fix resume error when iommu disabled in Picasso
will it merge into linux 5.15 release?
2021-10-13 14:16 GMT+08:00, Yifan Zhang :
> When IOMMU disabled in sbios and kfd in iommuv2 path,
> IOMMU resume failure blocks system resume. Don't allow kfd to
> use iommu v2 when iommu is disabled.
>
> Reported-by: youling
> Tested-by: youling
> Signed-off-by: Yifan Zhang
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index 08eedbc6699d..99d2b9c875ea 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -1021,6 +1021,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
> kfd_double_confirm_iommu_support(kfd);
>
> if (kfd_iommu_device_init(kfd)) {
> + kfd->use_iommu_v2 = false;
> dev_err(kfd_device, "Error initializing iommuv2\n");
> goto device_iommu_error;
> }
> --
> 2.25.1
>
>
[PATCH v2] drm/amdgpu/pm: drop pp_power_profile_mode support for yellow carp
This was added by commit bd8dcea93a7d ("drm/amd/pm: add callbacks to
read/write sysfs file pp_power_profile_mode") but the feature was
deprecated from PMFW. Remove it from the driver.
Signed-off-by: Mario Limonciello
---
Changes from v1->v2:
* Drop changes to RN and VGH as the deprecation is only in YC.
* Leave PPSMC_MSG_ActiveProcessNotify message but mark deprecated
* Rename PPSMC_MSG_SPARE0 to align to the name used by PMFW (PPSMC_MSG_SPARE)
.../gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h| 4 +-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 87 ---
2 files changed, 2 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
index 1d3447991d0c..fc9198846e70 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
@@ -51,7 +51,7 @@
#define PPSMC_MSG_PowerUpVcn0x07 ///< Power up VCN; VCN is
power gated by default
#define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless display
#define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for
GFXCLK, argument is frequency in MHz
-#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Set active work load
type
+#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Deprecated (Not to
be used)
#define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down
GFX, i.e. enter GFXOFF
#define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX
driver unload
#define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of
DRAM address for Driver table transfer
@@ -63,7 +63,7 @@
#define PPSMC_MSG_SetHardMinSocclkByFreq0x13 ///< Set hard min for SOC
CLK
#define PPSMC_MSG_SetSoftMinFclk0x14 ///< Set hard min for FCLK
#define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN
clocks (VCLK and DCLK)
-#define PPSMC_MSG_SPARE00x16 ///< Spared
+#define PPSMC_MSG_SPARE 0x16 ///< Spare
#define PPSMC_MSG_GetGfxclkFrequency0x17 ///< Get GFX clock
frequency
#define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
#define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of
allowing GFXOFF entry
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index a403657151ba..8215bbf5ed7c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -64,7 +64,6 @@ static struct cmn2asic_msg_mapping
yellow_carp_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn,
1),
MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn,
1),
MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
1),
- MSG_MAP(ActiveProcessNotify,PPSMC_MSG_ActiveProcessNotify,
1),
MSG_MAP(PrepareMp1ForUnload,PPSMC_MSG_PrepareMp1ForUnload,
1),
MSG_MAP(SetDriverDramAddrHigh,
PPSMC_MSG_SetDriverDramAddrHigh,1),
MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,
1),
@@ -135,14 +134,6 @@ static struct cmn2asic_mapping
yellow_carp_table_map[SMU_TABLE_COUNT] = {
TAB_MAP_VALID(CUSTOM_DPM),
TAB_MAP_VALID(DPMCLOCKS),
};
-
-static struct cmn2asic_mapping
yellow_carp_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
- WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,
WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
- WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,
WORKLOAD_PPLIB_VIDEO_BIT),
- WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,
WORKLOAD_PPLIB_VR_BIT),
- WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,
WORKLOAD_PPLIB_COMPUTE_BIT),
- WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,
WORKLOAD_PPLIB_CUSTOM_BIT),
-};
static int yellow_carp_init_smc_tables(struct smu_context *smu)
{
@@ -543,81 +534,6 @@ static int yellow_carp_set_watermarks_table(struct
smu_context *smu,
return 0;
}
-static int yellow_carp_get_power_profile_mode(struct smu_context *smu,
- char *buf)
-{
- static const char *profile_name[] = {
- "BOOTUP_DEFAULT",
- "3D_FULL_SCREEN",
- "POWER_SAVING",
- "VIDEO",
- "VR",
- "COMPUTE",
- "CUSTOM"};
- uint32_t i, size = 0;
- int16_t workload_type = 0;
-
- if (!buf)
- return -EINVAL;
-
-
[PATCH 10/14] drm/amd/display: Add MPC meory shutdown support
From: Jake Wang
[Why & How]
The MPC memory clocks should be powered down when not in use.
Acked-by: Aurabindo Pillai
Signed-off-by: Jake Wang
Reviewed-by: Eric Yang
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 7 +-
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 69 +++
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 1 +
3 files changed, 44 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index a82319f4d081..95149734378b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -1381,13 +1381,11 @@ int mpcc3_release_rmu(struct mpc *mpc, int mpcc_id)
}
-static void mpc3_mpc_init(struct mpc *mpc)
+static void mpc3_set_mpc_mem_lp_mode(struct mpc *mpc)
{
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
int mpcc_id;
- mpc1_mpc_init(mpc);
-
if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
if (mpc30->mpc_mask->MPC_RMU0_MEM_LOW_PWR_MODE &&
mpc30->mpc_mask->MPC_RMU1_MEM_LOW_PWR_MODE) {
REG_UPDATE(MPC_RMU_MEM_PWR_CTRL,
MPC_RMU0_MEM_LOW_PWR_MODE, 3);
@@ -1405,7 +1403,7 @@ const struct mpc_funcs dcn30_mpc_funcs = {
.read_mpcc_state = mpc1_read_mpcc_state,
.insert_plane = mpc1_insert_plane,
.remove_mpcc = mpc1_remove_mpcc,
- .mpc_init = mpc3_mpc_init,
+ .mpc_init = mpc1_mpc_init,
.mpc_init_single_inst = mpc1_mpc_init_single_inst,
.update_blending = mpc2_update_blending,
.cursor_lock = mpc1_cursor_lock,
@@ -1432,6 +1430,7 @@ const struct mpc_funcs dcn30_mpc_funcs = {
.power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
.get_mpc_out_mux = mpc1_get_mpc_out_mux,
.set_bg_color = mpc1_set_bg_color,
+ .set_mpc_mem_lp_mode = mpc3_set_mpc_mem_lp_mode,
};
void dcn30_mpc_construct(struct dcn30_mpc *mpc30,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 1b089893460a..5dd1ce9ddb53 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -66,6 +66,45 @@
#define FN(reg_name, field_name) \
hws->shifts->field_name, hws->masks->field_name
+static void enable_memory_low_power(struct dc *dc)
+{
+ struct dce_hwseq *hws = dc->hwseq;
+ int i;
+
+ if (dc->debug.enable_mem_low_power.bits.dmcu) {
+ // Force ERAM to shutdown if DMCU is not enabled
+ if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
+ REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE,
3);
+ }
+ }
+
+ // Set default OPTC memory power states
+ if (dc->debug.enable_mem_low_power.bits.optc) {
+ // Shutdown when unassigned and light sleep in VBLANK
+ REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3,
ODM_MEM_VBLANK_PWR_MODE, 1);
+ }
+
+ if (dc->debug.enable_mem_low_power.bits.vga) {
+ // Power down VGA memory
+ REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
+ }
+
+ if (dc->debug.enable_mem_low_power.bits.mpc)
+
dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
+
+
+ if (dc->debug.enable_mem_low_power.bits.vpg &&
dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {
+ // Power down VPGs
+ for (i = 0; i < dc->res_pool->stream_enc_count; i++)
+
dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)
+
dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);
+#endif
+ }
+
+}
+
void dcn31_init_hw(struct dc *dc)
{
struct abm **abms = dc->res_pool->multiple_abms;
@@ -108,35 +147,7 @@ void dcn31_init_hw(struct dc *dc)
if (res_pool->dccg->funcs->dccg_init)
res_pool->dccg->funcs->dccg_init(res_pool->dccg);
- if (dc->debug.enable_mem_low_power.bits.dmcu) {
- // Force ERAM to shutdown if DMCU is not enabled
- if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
- REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE,
3);
- }
- }
-
- // Set default OPTC memory power states
- if (dc->debug.enable_mem_low_power.bits.optc) {
- // Shutdown when unassigned and light sleep in VBLANK
- REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3,
ODM_MEM_VBLANK_PWR_MODE, 1);
- }
-
- if (dc->debug.enable_mem_low_power.bits.vga) {
- // Power down VGA memory
-
[PATCH 14/14] drm/amd/display: 3.2.160
From: Aric Cyr Acked-by: Aurabindo Pillai Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e9bac161fd25..3aac3f4a2852 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.159" +#define DC_VER "3.2.160" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.30.2
[PATCH 13/14] drm/amd/display: [FW Promotion] Release 0.0.91
From: Anthony Koo Acked-by: Aurabindo Pillai Signed-off-by: Anthony Koo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 6a79818337a1..1c4cac4a4894 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -47,10 +47,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x9525efb5 +#define DMUB_FW_VERSION_GIT_HASH 0x1d82d23e #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 90 +#define DMUB_FW_VERSION_REVISION 91 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.30.2
[PATCH 12/14] drm/amd/display: add condition check for dmub notification
[Why & How] In order to have dc_enable_dmub_notifications() more precise, add one more condition to check if dc->debug.dpia_debug.bits.disable_dpia is false. Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Wayne Lin Signed-off-by: Aurabindo Pillai Reviewed-by: Nicholas Kazlauskas --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 11a00e4d9e81..398de46fb7e4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3608,7 +3608,8 @@ bool dc_enable_dmub_notifications(struct dc *dc) #if defined(CONFIG_DRM_AMD_DC_DCN) /* YELLOW_CARP B0 USB4 DPIA needs dmub notifications for interrupts */ if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && - dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) + dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 && + !dc->debug.dpia_debug.bits.disable_dpia) return true; #endif /* dmub aux needs dmub notifications to be enabled */ -- 2.30.2
[PATCH 09/14] drm/amd/display: Added HPO HW control shutdown support
From: Jake Wang
[Why]
HPO is only used for DP2.0. HPO HW control should be
disable when not being used to save power.
[How]
Shutdown HPO HW control during init hw.
Shutdown HPO HW control during stream disable.
Enable HPO HW control during stream enable if DP2.0.
Acked-by: Aurabindo Pillai
Signed-off-by: Jake Wang
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 4 +++-
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 6 ++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 +++
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 9 +
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c| 1 +
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c| 6 --
.../gpu/drm/amd/display/dc/inc/hw_sequencer_private.h| 1 +
9 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index a5339796902a..e9bac161fd25 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -675,6 +675,7 @@ struct dc_debug_options {
#endif
union mem_low_power_enable_options enable_mem_low_power;
union root_clock_optimization_options root_clock_optimization;
+ bool hpo_optimization;
bool force_vblank_alignment;
/* Enable dmub aux for legacy ddc */
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 989f5b6907e2..a3fee929cd12 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -671,6 +671,7 @@ struct dce_hwseq_registers {
uint32_t MC_VM_FB_LOCATION_BASE;
uint32_t MC_VM_FB_LOCATION_TOP;
uint32_t MC_VM_FB_OFFSET;
+ uint32_t HPO_TOP_HW_CONTROL;
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -1152,7 +1153,8 @@ struct dce_hwseq_registers {
type DOMAIN_PGFSM_PWR_STATUS;\
type HPO_HDMISTREAMCLK_G_GATE_DIS;\
type DISABLE_HOSTVM_FORCE_ALLOW_PSTATE;\
- type I2C_LIGHT_SLEEP_FORCE;
+ type I2C_LIGHT_SLEEP_FORCE;\
+ type HPO_IO_EN;
struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index af3e68d3e747..24e47df526f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1244,6 +1244,12 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
#endif
if (dc_is_dp_signal(pipe_ctx->stream->signal))
dp_source_sequence_trace(link,
DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE);
+
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ if (dc->hwseq->funcs.setup_hpo_hw_control &&
is_dp_128b_132b_signal(pipe_ctx))
+ dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, false);
+#endif
+
}
void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index cfee456c6c9a..4f88376a118f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2397,6 +2397,9 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
* BY this, it is logic clean to separate stream and link
*/
if (is_dp_128b_132b_signal(pipe_ctx)) {
+ if
(pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control)
+
pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control(
+ pipe_ctx->stream->ctx->dc->hwseq, true);
setup_dp_hpo_stream(pipe_ctx, true);
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->enable_stream(
pipe_ctx->stream_res.hpo_dp_stream_enc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index d24ad7754d71..1b089893460a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -264,6 +264,9 @@ void dcn31_init_hw(struct dc *dc)
if (dc->debug.enable_mem_low_power.bits.i2c)
REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
+ if (hws->funcs.setup_hpo_hw_control)
+ hws->funcs.setup_hpo_hw_control(hws, false);
+
if (!dc->debug.disable_clock_gate) {
/* enable all DCN clock gating */
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
@@ -597,3 +600,9 @@ void dcn31_reset_hw_ctx_wrap(
/* New dc_state in the process of being applied to hardware. */
[PATCH 11/14] drm/amd/display: Added new DMUB boot option for power optimization
From: Jake Wang
[Why]
During Z10, root clock gating and memory low power registers needs to
to be restored if optimization is enabled in driver.
[How]
Added new DMUB boot option for root clock gating and memory low power.
Acked-by: Aurabindo Pillai
Signed-off-by: Jake Wang
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 717c0e572d2f..cd204eef073b 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -238,6 +238,7 @@ struct dmub_srv_hw_params {
bool load_inst_const;
bool skip_panel_power_sequence;
bool disable_z10;
+ bool power_optimization;
bool dpia_supported;
bool disable_dpia;
};
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
index 10ebf20eaa41..fa0569174aec 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
@@ -340,6 +340,7 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv
*dmub, const struct dmu
boot_options.bits.z10_disable = params->disable_z10;
boot_options.bits.dpia_supported = params->dpia_supported;
boot_options.bits.enable_dpia = params->disable_dpia ? 0 : 1;
+ boot_options.bits.power_optimization = params->power_optimization;
boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic ==
DMUB_ASIC_DCN31B) ? 1 : 0;
--
2.30.2
[PATCH 07/14] drm/amd/display: Clear encoder assignments when state cleared.
From: Jimmy Kizito
[Why]
State can be cleared without removing individual streams (by
calling dc_remove_stream_from_ctx()). This can leave the
encoder assignment module in an incoherent state and cause
future assignments to be incorrect.
[How]
Clear encoder assignments when committing 0 streams or
re-initializing hardware.
Acked-by: Aurabindo Pillai
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
---
.../drm/amd/display/dc/core/dc_link_enc_cfg.c | 22 +++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index 72b0f8594b4a..25e48a8cbb78 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -236,6 +236,23 @@ static struct link_encoder *get_link_enc_used_by_link(
return link_enc;
}
+/* Clear all link encoder assignments. */
+static void clear_enc_assignments(struct dc_state *state)
+{
+ int i;
+ enum engine_id eng_id;
+ struct dc_stream_state *stream;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+ state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].valid =
false;
+ eng_id =
state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].eng_id;
+ stream =
state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i].stream;
+ if (eng_id != ENGINE_ID_UNKNOWN)
+ state->res_ctx.link_enc_cfg_ctx.link_enc_avail[eng_id -
ENGINE_ID_DIGA] = eng_id;
+ if (stream)
+ stream->link_enc = NULL;
+ }
+}
void link_enc_cfg_init(
struct dc *dc,
@@ -250,6 +267,8 @@ void link_enc_cfg_init(
state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i] =
ENGINE_ID_UNKNOWN;
}
+ clear_enc_assignments(state);
+
state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
}
@@ -265,6 +284,9 @@ void link_enc_cfg_link_encs_assign(
ASSERT(state->stream_count == stream_count);
+ if (stream_count == 0)
+ clear_enc_assignments(state);
+
/* Release DIG link encoder resources before running assignment
algorithm. */
for (i = 0; i < stream_count; i++)
dc->res_pool->funcs->link_enc_unassign(state, streams[i]);
--
2.30.2
[PATCH 08/14] drm/amd/display: fix register write sequence for LINK_SQUARE_PATTERN
From: Wenjing Liu
[why]
write LINK_SQUARE_PATTERN_num + 1 for square pulse pattern.
Specs requirement to write this register prior to write LINK_QUAL_LANEX_SET.
Acked-by: Aurabindo Pillai
Signed-off-by: Wenjing Liu
Reviewed-by: George Shen
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index cc25ba0ec7db..cb7bf9148904 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5329,6 +5329,14 @@ bool dc_link_dp_set_test_pattern(
return false;
if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ if (test_pattern == DP_TEST_PATTERN_SQUARE_PULSE)
+ core_link_write_dpcd(link,
+ DP_LINK_SQUARE_PATTERN,
+ p_custom_pattern,
+ 1);
+
+#endif
/* tell receiver that we are sending qualification
* pattern DP 1.2 or later - DP receiver's link quality
* pattern is set using DPCD LINK_QUAL_LANEx_SET
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index bc87ea0adf94..e68e9a86a4d9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -898,6 +898,9 @@ struct dpcd_usb4_dp_tunneling_info {
#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0A3
#endif
+#ifndef DP_LINK_SQUARE_PATTERN
+#define DP_LINK_SQUARE_PATTERN 0x10F
+#endif
#ifndef DP_DSC_CONFIGURATION
#define DP_DSC_CONFIGURATION 0x161
#endif
--
2.30.2
[PATCH 06/14] drm/amd/display: Force disable planes on any pipe split change
From: Roman Li
[Why]
In scenario when 1 display connected with pipe split (2 pipes in use)
and 3 new displays simultaneously hotplugged via MST hub (4 pipes in use),
mpcc may get reprogram to other vtg, remaining busy.
In this case waiting for mpcc idle timeouts with error like this:
[drm] REG_WAIT timeout 1us * 10 tries - mpc2_assert_idle_mpcc
RIP: 0010:mpc2_assert_mpcc_idle_before_connect
Call Trace:
dcn20_update_mpcc
dcn20_program_front_end_for_ctx
dc_commit_state
amdgpu_dm_atomic_commit_tail
...
[How]
Add pipe split change condition to disable dangling plane.
Acked-by: Aurabindo Pillai
Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 12e5470fa567..11a00e4d9e81 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1085,6 +1085,8 @@ static void disable_dangling_plane(struct dc *dc, struct
dc_state *context)
struct dc_stream_state *old_stream =
dc->current_state->res_ctx.pipe_ctx[i].stream;
bool should_disable = true;
+ bool pipe_split_change =
+ context->res_ctx.pipe_ctx[i].top_pipe !=
dc->current_state->res_ctx.pipe_ctx[i].top_pipe;
for (j = 0; j < context->stream_count; j++) {
if (old_stream == context->streams[j]) {
@@ -1092,6 +1094,9 @@ static void disable_dangling_plane(struct dc *dc, struct
dc_state *context)
break;
}
}
+ if (!should_disable && pipe_split_change)
+ should_disable = true;
+
if (should_disable && old_stream) {
dc_rem_all_planes_for_stream(dc, old_stream,
dangling_context);
disable_all_writeback_pipes_for_stream(dc, old_stream,
dangling_context);
--
2.30.2
[PATCH 04/14] drm/amd/display: avoid link loss short pulse stuck the system
From: Yu-ting Shen
[Why]
MST monitor sends link loss short pulse continuous but sink is
occupy by HDMI input to lead link training fail.
[How]
disable link once retraining fail.
Acked-by: Aurabindo Pillai
Signed-off-by: Yu-ting Shen
Reviewed-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 2796bdd17de1..f14f71dd1aa9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4279,6 +4279,8 @@ void core_link_enable_stream(
*/
if (status != DC_FAIL_DP_LINK_TRAINING ||
pipe_ctx->stream->signal ==
SIGNAL_TYPE_DISPLAY_PORT_MST) {
+ if (false ==
stream->link->link_status.link_active)
+ disable_link(stream->link,
pipe_ctx->stream->signal);
BREAK_TO_DEBUGGER();
return;
}
--
2.30.2
[PATCH 05/14] drm/amd/display: Fix bpc calculation for specific encodings
From: Bing Guo
[Why]
1. YCbCr 4:2:2 8bpc/10bpc modes are blocked for HDMI by policy
2. A YCbCr 4:2:0 calculation error blocked some 4:2:0 timing modes
[How]
YCbCr 4:2:2 8bpc/10bpc modes are allowed for HDMI
Fix YCbCr 4:2:0 calculation error
Acked-by: Aurabindo Pillai
Signed-off-by: Bing Guo
Reviewed-by: Chris Park
---
.../amd/display/dc/dml/dcn30/display_mode_vba_30.c | 13 +++--
.../amd/display/dc/dml/dcn31/display_mode_vba_31.c | 14 +-
2 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index e3d9f1decdfc..f47d82da115c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3576,16 +3576,9 @@ static double TruncToValidBPP(
MinDSCBPP = 8;
MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
} else {
- if (Output == dm_hdmi) {
- NonDSCBPP0 = 24;
- NonDSCBPP1 = 24;
- NonDSCBPP2 = 24;
- }
- else {
- NonDSCBPP0 = 16;
- NonDSCBPP1 = 20;
- NonDSCBPP2 = 24;
- }
+ NonDSCBPP0 = 16;
+ NonDSCBPP1 = 20;
+ NonDSCBPP2 = 24;
if (Format == dm_n422) {
MinDSCBPP = 7;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index d58925cff420..7e937bdcea00 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -3892,15 +3892,11 @@ static double TruncToValidBPP(
MinDSCBPP = 8;
MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
} else {
- if (Output == dm_hdmi) {
- NonDSCBPP0 = 24;
- NonDSCBPP1 = 24;
- NonDSCBPP2 = 24;
- } else {
- NonDSCBPP0 = 16;
- NonDSCBPP1 = 20;
- NonDSCBPP2 = 24;
- }
+
+ NonDSCBPP0 = 16;
+ NonDSCBPP1 = 20;
+ NonDSCBPP2 = 24;
+
if (Format == dm_n422) {
MinDSCBPP = 7;
MaxDSCBPP = 2 * DSCInputBitPerComponent - 1.0 / 16.0;
--
2.30.2
[PATCH 03/14] drm/amd/display: Fix dummy p-state hang on monitors with extreme timing
From: Felipe Clark
[WHY]
It was found that the system would hang on a dummy pstate when playing
4k60 videos on a 1080p 390Hz monitor.
[HOW]
Properly select the dummy_pstate_latency_ms when firmware assisted
memory clock switching is enabled instead of assuming that the highest
latency would work for every monitor timing.
Acked-by: Aurabindo Pillai
Signed-off-by: Felipe Clark
Reviewed-by: Jun Lei
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index e50c695e3c96..79a66e0c4303 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2128,10 +2128,10 @@ static noinline void dcn30_calculate_wm_and_dlg_fp(
int pipe_cnt,
int vlevel)
{
+ int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
int i, pipe_idx;
- double dcfclk =
context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
- bool pstate_en =
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
!=
- dm_dram_clock_change_unsupported;
+ double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];
+ bool pstate_en =
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] !=
dm_dram_clock_change_unsupported;
if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
@@ -2207,6 +2207,7 @@ static noinline void dcn30_calculate_wm_and_dlg_fp(
context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
context->bw_ctx.dml.soc.sr_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
}
+
context->bw_ctx.bw.dcn.watermarks.c.urgent_ns =
get_wm_urgent(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
--
2.30.2
[PATCH 02/14] drm/amd/display: Fix dcn10_log_hubp_states printf format string
From: Anson Jacob
Fix spacing issue for the format string.
Addresses-Coverity-ID: 1446765: ("Invalid printf format string")
Acked-by: Aurabindo Pillai
Signed-off-by: Anson Jacob
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index a25732d07222..0b788d794fb3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -231,7 +231,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void
*log_ctx)
if (!s->blank_en)
DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh
%8xh %8xh %8xh %8xh %8xh %8xh %8xh"
- "% 8xh %8xh %8xh %8xh %8xh %8xh %8xh
%8xh %8xh %8xh %8xh %8xh %8xh %8xh"
+ " %8xh %8xh %8xh %8xh %8xh %8xh %8xh
%8xh %8xh %8xh %8xh %8xh %8xh %8xh"
" %8xh %8xh %8xh %8xh %8xh %8xh %8xh
%8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
pool->hubps[i]->inst,
dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end,
dlg_regs->min_dst_y_next_start,
dlg_regs->refcyc_per_htotal,
dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
--
2.30.2
[PATCH 01/14] drm/amd/display: dsc engine not disabled after unplug dsc mst hub
From: Hersen Wu
[WHY]
If timing and bpp of displays on mst hub are not changed,
pbn, slot_num for displays should not be changed. Linux
user mode may initiate atomic_check with different display
configuration after set mode finished. This will call to
amdgpu_dm to re-compute payload, slot_num of displays and
saved to dm_connect_state. stream->timing.flags.dsc, pbn,
slot_num are updated to values which may be different from
that were used for set mode. when dsc hub with 3 4k@60hz dp
connected, 3 dsc engines are enabled. timing.flags.dsc = 1.
timing.flags.dsc are changed to 0 due to atomic check. when
dsc hub is unplugged, amdgpu driver check timing.flags.dsc
for last mode set and find out flags.dsc = 0, then does not
disable dsc.
[HOW]
check status of displays on dsc mst hubs. re-compute pbn,
slot_num, timing.flags.dsc only if there is mode, connect
or enable/disable change.
Acked-by: Aurabindo Pillai
Signed-off-by: Hersen Wu
Reviewed-by: Mikita Lipski
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 31 ++--
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 150 ++
2 files changed, 138 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6dd6262f2769..b48f3cb5ddeb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7241,8 +7241,8 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct
drm_atomic_state *state,
struct drm_connector_state *new_con_state;
struct amdgpu_dm_connector *aconnector;
struct dm_connector_state *dm_conn_state;
- int i, j, clock;
- int vcpi, pbn_div, pbn = 0;
+ int i, j;
+ int vcpi, pbn_div, pbn, slot_num = 0;
for_each_new_connector_in_state(state, connector, new_con_state, i) {
@@ -7270,17 +7270,7 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct
drm_atomic_state *state,
if (!stream)
continue;
- if (stream->timing.flags.DSC != 1) {
- drm_dp_mst_atomic_enable_dsc(state,
-aconnector->port,
-dm_conn_state->pbn,
-0,
-false);
- continue;
- }
-
pbn_div = dm_mst_get_pbn_divider(stream->link);
- clock = stream->timing.pix_clk_100hz / 10;
/* pbn is calculated by compute_mst_dsc_configs_for_state*/
for (j = 0; j < dc_state->stream_count; j++) {
if (vars[j].aconnector == aconnector) {
@@ -7289,6 +7279,23 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct
drm_atomic_state *state,
}
}
+ if (j == dc_state->stream_count)
+ continue;
+
+ slot_num = DIV_ROUND_UP(pbn, pbn_div);
+
+ if (stream->timing.flags.DSC != 1) {
+ dm_conn_state->pbn = pbn;
+ dm_conn_state->vcpi_slots = slot_num;
+
+ drm_dp_mst_atomic_enable_dsc(state,
+aconnector->port,
+dm_conn_state->pbn,
+0,
+false);
+ continue;
+ }
+
vcpi = drm_dp_mst_atomic_enable_dsc(state,
aconnector->port,
pbn, pbn_div,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 874a49b605c7..32a5ce09a62a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -534,13 +534,14 @@ static int kbps_to_peak_pbn(int kbps)
static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params
*params,
struct dsc_mst_fairness_vars *vars,
- int count)
+ int count,
+ int k)
{
int i;
for (i = 0; i < count; i++) {
memset([i].timing->dsc_cfg, 0,
sizeof(params[i].timing->dsc_cfg));
- if (vars[i].dsc_enabled && dc_dsc_compute_config(
+ if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
params[i].sink->ctx->dc->res_pool->dscs[0],
[i].sink->dsc_caps.dsc_dec_caps,
params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
@@ -553,7 +554,7 @@ static void
[PATCH 00/14] DC patches for Nov 1, 2021
This DC patchset brings improvements in multiple areas. In summary, we highlight: * DC release version 3.2.160 * DMUB fw version 0.0.91 and bug fixes * DSC related fixes * Minor power optimization improvements * Bug fixes and improvements in display pipeline --- Anson Jacob (1): drm/amd/display: Fix dcn10_log_hubp_states printf format string Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.91 Aric Cyr (1): drm/amd/display: 3.2.160 Aurabindo Pillai (1): drm/amd/display: add condition check for dmub notification Bing Guo (1): drm/amd/display: Fix bpc calculation for specific encodings Felipe Clark (1): drm/amd/display: Fix dummy p-state hang on monitors with extreme timing Hersen Wu (1): drm/amd/display: dsc engine not disabled after unplug dsc mst hub Jake Wang (3): drm/amd/display: Added HPO HW control shutdown support drm/amd/display: Add MPC meory shutdown support drm/amd/display: Added new DMUB boot option for power optimization Jimmy Kizito (1): drm/amd/display: Clear encoder assignments when state cleared. Roman Li (1): drm/amd/display: Force disable planes on any pipe split change Wenjing Liu (1): drm/amd/display: fix register write sequence for LINK_SQUARE_PATTERN Yu-ting Shen (1): drm/amd/display: avoid link loss short pulse stuck the system .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 31 ++-- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 150 ++ drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 + .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 + .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 22 +++ drivers/gpu/drm/amd/display/dc/dc.h | 3 +- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 + .../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 4 +- .../display/dc/dce110/dce110_hw_sequencer.c | 6 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 3 + .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 7 +- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 7 +- .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 78 + .../drm/amd/display/dc/dcn31/dcn31_hwseq.h| 1 + .../gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 1 + .../drm/amd/display/dc/dcn31/dcn31_resource.c | 6 +- .../dc/dml/dcn30/display_mode_vba_30.c| 13 +- .../dc/dml/dcn31/display_mode_vba_31.c| 14 +- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 1 + .../amd/display/dc/inc/hw_sequencer_private.h | 1 + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 + 25 files changed, 271 insertions(+), 106 deletions(-) -- 2.30.2
Re: [PATCH 1/1] drm/amdgpu: remove unnecessary checks
ping!
On 10/22/2021 1:03 PM, Nirmoy Das wrote:
amdgpu_ttm_backend_bind() only needed for TTM_PL_TT
and AMDGPU_PL_PREEMPT.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index d784f8d3a834..eb872fc4ad92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -914,11 +914,6 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
ttm->num_pages, bo_mem, ttm);
}
- if (bo_mem->mem_type == AMDGPU_PL_GDS ||
- bo_mem->mem_type == AMDGPU_PL_GWS ||
- bo_mem->mem_type == AMDGPU_PL_OA)
- return -EINVAL;
-
if (bo_mem->mem_type != TTM_PL_TT ||
!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
gtt->offset = AMDGPU_BO_INVALID_OFFSET;
[PATCH 1/1] drm/amdgpu: return early on error while setting bar0 memtype
We set WC memtype for aper_base but don't check return value
of arch_io_reserve_memtype_wc(). Be more defensive and return
early on error.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 073ba2af0b9c..6b25982a9077 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1032,9 +1032,14 @@ int amdgpu_bo_init(struct amdgpu_device *adev)
/* On A+A platform, VRAM can be mapped as WB */
if (!adev->gmc.xgmi.connected_to_cpu) {
/* reserve PAT memory space to WC for VRAM */
- arch_io_reserve_memtype_wc(adev->gmc.aper_base,
+ int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base,
adev->gmc.aper_size);
+ if (r) {
+ DRM_ERROR("Unable to set WC memtype for the aperture
base\n");
+ return r;
+ }
+
/* Add an MTRR for the VRAM */
adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
adev->gmc.aper_size);
--
2.33.1
Re: [PATCH] mm/migrate.c: Remove MIGRATE_PFN_LOCKED
On Friday, 29 October 2021 2:33:31 AM AEDT Felix Kuehling wrote:
> Am 2021-10-27 um 9:42 p.m. schrieb Alistair Popple:
> > On Wednesday, 27 October 2021 3:09:57 AM AEDT Felix Kuehling wrote:
> >> Am 2021-10-25 um 12:16 a.m. schrieb Alistair Popple:
> >>> MIGRATE_PFN_LOCKED is used to indicate to migrate_vma_prepare() that a
> >>> source page was already locked during migrate_vma_collect(). If it
> >>> wasn't then the a second attempt is made to lock the page. However if
> >>> the first attempt failed it's unlikely a second attempt will succeed,
> >>> and the retry adds complexity. So clean this up by removing the retry
> >>> and MIGRATE_PFN_LOCKED flag.
> >>>
> >>> Destination pages are also meant to have the MIGRATE_PFN_LOCKED flag
> >>> set, but nothing actually checks that.
> >>>
> >>> Signed-off-by: Alistair Popple
> >> It makes sense to me. Do you have any empirical data on how much more
> >> likely migrations are going to fail with this change due to contested
> >> page locks?
> > Thanks Felix. I do not have any empirical data on this but I've mostly seen
> > migrations fail due to the reference count check failing rather than
> > failure to
> > lock the page. Even then it's mostly been due to thrashing on the same
> > page, so
> > I would be surprised if this change made any noticeable difference.
>
> We have seen more page locking contention on NUMA systems that disappear
> when we disable NUMA balancing. Probably NUMA balancing migrations
> result in the page lock being more contended, which can cause HMM
> migration of some pages to fail.
Yeah, we've found NUMA balancing in general is pretty unhelpful for HMM based
migrations and mappings so have been looking into ways of disabling it for HMM
ranges.
> Also, for migrations to system memory, multiple threads page faulting
> concurrently can cause contention. I was just helping debug such an
> issue. Having migrations to system memory be only partially successful
> is problematic. We'll probably have to implement some retry logic in the
> driver to handle this.
Sounds similar to the problem I was referring to, except in my case I was
seeing contention on the page reference checks due to lots of threads hitting
__migration_entry_wait() at just the wrong time. I am working on a fix for that
that avoids taking the reference at all, however I think retry logic will still
be needed and suspect a driver is probably the best place to implement that.
> Regards,
> Felix
>
>
> >
> >> Either way, the patch is
> >>
> >> Acked-by: Felix Kuehling
> >>
> >>
> >>> ---
> >>> Documentation/vm/hmm.rst | 2 +-
> >>> arch/powerpc/kvm/book3s_hv_uvmem.c | 4 +-
> >>> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 -
> >>> drivers/gpu/drm/nouveau/nouveau_dmem.c | 4 +-
> >>> include/linux/migrate.h | 1 -
> >>> lib/test_hmm.c | 5 +-
> >>> mm/migrate.c | 145 +--
> >>> 7 files changed, 35 insertions(+), 128 deletions(-)
> >>>
> >>> diff --git a/Documentation/vm/hmm.rst b/Documentation/vm/hmm.rst
> >>> index a14c2938e7af..f2a59ed82ed3 100644
> >>> --- a/Documentation/vm/hmm.rst
> >>> +++ b/Documentation/vm/hmm.rst
> >>> @@ -360,7 +360,7 @@ between device driver specific code and shared common
> >>> code:
> >>> system memory page, locks the page with ``lock_page()``, and fills in
> >>> the
> >>> ``dst`` array entry with::
> >>>
> >>> - dst[i] = migrate_pfn(page_to_pfn(dpage)) | MIGRATE_PFN_LOCKED;
> >>> + dst[i] = migrate_pfn(page_to_pfn(dpage));
> >>>
> >>> Now that the driver knows that this page is being migrated, it can
> >>> invalidate device private MMU mappings and copy device private memory
> >>> diff --git a/arch/powerpc/kvm/book3s_hv_uvmem.c
> >>> b/arch/powerpc/kvm/book3s_hv_uvmem.c
> >>> index a7061ee3b157..28c436df9935 100644
> >>> --- a/arch/powerpc/kvm/book3s_hv_uvmem.c
> >>> +++ b/arch/powerpc/kvm/book3s_hv_uvmem.c
> >>> @@ -560,7 +560,7 @@ static int __kvmppc_svm_page_out(struct
> >>> vm_area_struct *vma,
> >>> gpa, 0, page_shift);
> >>>
> >>> if (ret == U_SUCCESS)
> >>> - *mig.dst = migrate_pfn(pfn) | MIGRATE_PFN_LOCKED;
> >>> + *mig.dst = migrate_pfn(pfn);
> >>> else {
> >>> unlock_page(dpage);
> >>> __free_page(dpage);
> >>> @@ -774,7 +774,7 @@ static int kvmppc_svm_page_in(struct vm_area_struct
> >>> *vma,
> >>> }
> >>> }
> >>>
> >>> - *mig.dst = migrate_pfn(page_to_pfn(dpage)) | MIGRATE_PFN_LOCKED;
> >>> + *mig.dst = migrate_pfn(page_to_pfn(dpage));
> >>> migrate_vma_pages();
> >>> out_finalize:
> >>> migrate_vma_finalize();
> >>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> >>> b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> >>> index 4a16e3c257b9..41d9417f182b 100644
> >>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> >>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> >>> @@
RE: [PATCH] drm/amdgpu: use correct register mask to extract field
[AMD Official Use Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin)
Sent: Friday, October 29, 2021 15:17
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Min, Frank ;
Lazar, Lijo ; Oak Zeng ; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: use correct register mask to extract field
From: Oak Zeng
Aldebaran has different register mask definitions for regiter
MC_VM_XGMI_LFB_CNTL. Use the correct masks to interpret fields of this register.
Signed-off-by: Oak Zeng
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
index 497b86c376c6..90f0aefbdb39 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
@@ -54,15 +54,17 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
seg_size = REG_GET_FIELD(
RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE),
MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
+ max_region =
+ REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE,
+PF_MAX_REGION);
} else {
xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
seg_size = REG_GET_FIELD(
RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
+ max_region =
+ REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
PF_MAX_REGION);
}
- max_region =
- REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
PF_MAX_REGION);
switch (adev->asic_type) {
@@ -89,9 +91,15 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
return -EINVAL;
- adev->gmc.xgmi.physical_node_id =
- REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
- PF_LFB_REGION);
+ if (adev->asic_type == CHIP_ALDEBARAN) {
+ adev->gmc.xgmi.physical_node_id =
+ REG_GET_FIELD(xgmi_lfb_cntl,
MC_VM_XGMI_LFB_CNTL_ALDE,
+ PF_LFB_REGION);
+ } else {
+ adev->gmc.xgmi.physical_node_id =
+ REG_GET_FIELD(xgmi_lfb_cntl,
MC_VM_XGMI_LFB_CNTL,
+ PF_LFB_REGION);
+ }
if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
return -EINVAL;
--
2.25.1
[PATCH] drm/amdgpu: use correct register mask to extract field
From: Oak Zeng
Aldebaran has different register mask definitions for
regiter MC_VM_XGMI_LFB_CNTL. Use the correct masks
to interpret fields of this register.
Signed-off-by: Oak Zeng
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
index 497b86c376c6..90f0aefbdb39 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
@@ -54,15 +54,17 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
seg_size = REG_GET_FIELD(
RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE),
MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
+ max_region =
+ REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE,
PF_MAX_REGION);
} else {
xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
seg_size = REG_GET_FIELD(
RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
+ max_region =
+ REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
PF_MAX_REGION);
}
- max_region =
- REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
PF_MAX_REGION);
switch (adev->asic_type) {
@@ -89,9 +91,15 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
return -EINVAL;
- adev->gmc.xgmi.physical_node_id =
- REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
- PF_LFB_REGION);
+ if (adev->asic_type == CHIP_ALDEBARAN) {
+ adev->gmc.xgmi.physical_node_id =
+ REG_GET_FIELD(xgmi_lfb_cntl,
MC_VM_XGMI_LFB_CNTL_ALDE,
+ PF_LFB_REGION);
+ } else {
+ adev->gmc.xgmi.physical_node_id =
+ REG_GET_FIELD(xgmi_lfb_cntl,
MC_VM_XGMI_LFB_CNTL,
+ PF_LFB_REGION);
+ }
if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
return -EINVAL;
--
2.25.1
Re: Lockdep spalt on killing a processes
Am 28.10.21 um 19:26 schrieb Andrey Grodzovsky: On 2021-10-27 3:58 p.m., Andrey Grodzovsky wrote: On 2021-10-27 10:50 a.m., Christian König wrote: Am 27.10.21 um 16:47 schrieb Andrey Grodzovsky: On 2021-10-27 10:34 a.m., Christian König wrote: Am 27.10.21 um 16:27 schrieb Andrey Grodzovsky: [SNIP] Let me please know if I am still missing some point of yours. Well, I mean we need to be able to handle this for all drivers. For sure, but as i said above in my opinion we need to change only for those drivers that don't use the _locked version. And that absolutely won't work. See the dma_fence is a contract between drivers, so you need the same calling convention between all drivers. Either we always call the callback with the lock held or we always call it without the lock, but sometimes like that and sometimes otherwise won't work. Christian. I am not sure I fully understand what problems this will cause but anyway, then we are back to irq_work. We cannot embed irq_work as union within dma_fenc's cb_list because it's already reused as timestamp and as rcu head after the fence is signaled. So I will do it within drm_scheduler with single irq_work per drm_sched_entity as we discussed before. That won't work either. We free up the entity after the cleanup function. That's the reason we use the callback on the job in the first place. Yep, missed it. We could overlead the cb structure in the job though. I guess, since no one else is using this member it after the cb executed. Andrey Attached a patch. Give it a try please, I tested it on my side and tried to generate the right conditions to trigger this code path by repeatedly submitting commands while issuing GPU reset to stop the scheduler and then killing command submissions process in the middle. But for some reason looks like the job_queue was always empty already at the time of entity kill. It was trivial to trigger with the stress utility I've hacked together: amdgpu_stress -b v 1g -b g 1g -c 1 2 1g 1k Then while it is copying just cntrl+c to kill it. The patch itself is: Tested-by: Christian König Reviewed-by: Christian König Thanks, Christian. Andrey Christian. Andrey Andrey
