Re: [PATCH v6] drm/amdgpu: handle IH ring1 overflow
Am 25.11.21 um 02:56 schrieb Felix Kuehling: Am 2021-11-24 um 5:58 p.m. schrieb Philip Yang: [SNIP] #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih)) #define amdgpu_ih_decode_iv(adev, iv) \ (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv)) +#define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \ + (WARN_ON_ONCE(!(adev)->irq.ih_funcs->decode_iv_ts) ? 0 : \ + (adev)->irq.ih_funcs->decode_iv_ts((ih), (rptr), (offset))) #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih)) int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, @@ -89,10 +99,12 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv, unsigned int num_dw); -int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev, - struct amdgpu_ih_ring *ih); +int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev, + struct amdgpu_ih_ring *ih); int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, struct amdgpu_iv_entry *entry); +uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr, + signed int offset); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 3ec5ff5a6dbe..b129898db433 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -119,6 +119,11 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, return 1; } + /* Stale retry fault if timestamp goes backward */ + if (entry->ih == &adev->irq.ih1 && + amdgpu_ih_ts_after(entry->timestamp, entry->ih->processed_timestamp)) + return 1; + This check should go before amdgpu_gmc_filter_faults. Otherwise amdgpu_gmc_filter_faults may later drop a real fault because it added a stale fault in its hash table. I was already wondering if we shouldn't move all of this completely into amdgpu_gmc_filter_faults(). I mean essentially we are filtering faults here once more, just based on a different criteria. Regards, Christian.
Re: [PATCH v5] drm/amdgpu: handle IH ring1 overflow
Am 24.11.21 um 23:52 schrieb philip yang: On 2021-11-24 10:33 a.m., Christian König wrote: Am 24.11.21 um 16:23 schrieb philip yang: [SNIP] +/** + * amdgpu_ih_process1 - interrupt handler work for IH ring1 + * + * @adev: amdgpu_device pointer + * @ih: ih ring to process + * + * Interrupt handler of IH ring1, walk the IH ring1. + * Returns irq process return code. + */ +int amdgpu_ih_process1(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) I don't think we need this new function any more. The check if the timestamp goes backwards can now be done inside the page fault handler. Do you mean to merge this into the original ring0 interrupt handler? Then we need add parameter (ih->overflow_enabled) and process two different cases in ring0 interrupt handler, I think that is not good to maintain later so I want to separate them. What I mean is you don't need any different handling any more if we use the timestamp anyway. Just keep the last processed timestamp in the page fault code and ignore faults when it starts to go backwards. If IVs should be dropped or processed as much as possible is depending on quite a bunch of things and should probably not be handled in the IH code in general. Use ih->processed_timestamp updated in decode_iv, for both checkpoint process and page fault handler to drop stale fault. interrupt handler don't need change. Well that's what I wanted to say: I would rather change the interrupt handler for page faults than the general interrupt processing. That we should drop older faults is page fault handling specific and should not affect other handlers. Regards, Christian. Thanks, Philip Regards, Christian.
Re: [PATCH v5] drm/amdgpu: handle IH ring1 overflow
Am 24.11.21 um 21:20 schrieb Felix Kuehling: Am 2021-11-24 um 10:23 a.m. schrieb philip yang: #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih)) #define amdgpu_ih_decode_iv(adev, iv) \ (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv)) +#define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \ + (WARN_ON_ONCE(!(adev)->irq.ih_funcs->decode_iv_ts) ? 0 : \ Please drop that WARN_ON_ONCE here. Agree, will drop it. I suggested this. We're assuming that this function will never be called on hardware that doesn't support time stamps, and that all hardware with time stamps will implement the decode_iv_ts function. But it's good to get a log message if that assumption is ever broken, rather than just silently getting wrong results. Well exactly that's the point, you won't get wrong results but a NULL pointer exception instead. So we already have a backtrace in the logs. Regards, Christian. Regards, Felix Regards, Philip
[PATCH v3] drm/amdgpu: reset asic after system-wide suspend aborted (v3)
Do ASIC reset at the moment Sx suspend aborted behind of amdgpu suspend
to keep AMDGPU in a clean reset state and that can avoid re-initialize
device improperly error. Currently,we just always do asic reset in the
amdgpu resume until sort out the PM abort case.
v2: Remove incomplete PM abort flag and add GPU hive case check for
GPU reset.
v3: Some dGPU reset method not support at the early resume time and
temprorary skip the dGPU case.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7d4115d..f6e1a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3983,6 +3983,14 @@ int amdgpu_device_resume(struct drm_device *dev, bool
fbcon)
if (adev->in_s0ix)
amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
+ /*TODO: In order to not let all-always asic reset affect resume latency
+* need sort out the case which really need asic reset in the resume
process.
+* As to the known issue on the system suspend abort behind the AMDGPU
suspend,
+* may can sort this case by checking struct suspend_stats which need
exported
+* firstly.
+*/
+ if (adev->flags & AMD_IS_APU)
+ amdgpu_asic_reset(adev);
/* post card */
if (amdgpu_device_need_post(adev)) {
r = amdgpu_device_asic_init(adev);
--
2.7.4
RE: [PATCH v2] drm/amdgpu: reset asic after system-wide suspend aborted (v2)
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Wednesday, November 24, 2021 9:30 PM
> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
>
> Subject: Re: [PATCH v2] drm/amdgpu: reset asic after system-wide suspend
> aborted (v2)
>
>
>
> On 11/24/2021 6:13 PM, Prike Liang wrote:
> > Do ASIC reset at the moment Sx suspend aborted behind of amdgpu
> > suspend to keep AMDGPU in a clean reset state and that can avoid
> > re-initialize device improperly error. Currently,we just always do
> > asic reset in the amdgpu resume until sort out the PM abort case.
> >
> > v2: Remove incomplete PM abort flag and add GPU hive case check for
> > GPU reset.
> >
> > Signed-off-by: Prike Liang
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 7d4115d..3fcd90d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -3983,6 +3983,14 @@ int amdgpu_device_resume(struct drm_device
> *dev, bool fbcon)
> > if (adev->in_s0ix)
> > amdgpu_gfx_state_change_set(adev,
> sGpuChangeState_D0Entry);
> >
> > + /*TODO: In order to not let all-always asic reset affect resume
> latency
> > +* need sort out the case which really need asic reset in the resume
> process.
> > +* As to the known issue on the system suspend abort behind the
> AMDGPU suspend,
> > +* may can sort this case by checking struct suspend_stats which
> need exported
> > +* firstly.
> > +*/
> > + if (adev->gmc.xgmi.num_physical_nodes <= 1)
> > + amdgpu_asic_reset(adev);
>
> Newer dGPUs depend on PMFW to do reset and that is not loaded at this
> point. For some, there is a mini FW available which could technically handle a
> reset and some of the older ones depend on PSP. Strongly suggest to check
> all such cases before doing a reset here.
>
> Or, the safest at this point could be to do the reset only for APUs.
>
> Thanks,
> Lijo
>
Thanks for the input, that may need a lot of effort to sort out reset method
from many dGPUs.
So in this time let's only handle APUs firstly.
> > /* post card */
> > if (amdgpu_device_need_post(adev)) {
> > r = amdgpu_device_asic_init(adev);
> >
RE: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID
[Public] I guess you need to add this IP version in nv_query_video_codecs as well. With above clarified/fixed, this patch is: Reviewed-by: Guchun Chen Regards, Guchun -Original Message- From: Jane Jian Sent: Thursday, November 25, 2021 11:15 AM To: Deucher, Alexander ; Chen, Guchun ; Chen, JingWen Cc: amd-gfx@lists.freedesktop.org; Jian, Jane Subject: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID [WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58 --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 503995c7ff6c..f6fae79203ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -918,6 +918,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(3, 0, 64): case IP_VERSION(3, 1, 1): case IP_VERSION(3, 0, 2): + case IP_VERSION(3, 0, 192): amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); if (!amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 4f7c70845785..585961c2f5f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -135,6 +135,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) break; case IP_VERSION(3, 0, 0): case IP_VERSION(3, 0, 64): + case IP_VERSION(3, 0, 192): if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) fw_name = FIRMWARE_SIENNA_CICHLID; else -- 2.17.1
[PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID
[WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58 --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 503995c7ff6c..f6fae79203ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -918,6 +918,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(3, 0, 64): case IP_VERSION(3, 1, 1): case IP_VERSION(3, 0, 2): + case IP_VERSION(3, 0, 192): amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); if (!amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 4f7c70845785..585961c2f5f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -135,6 +135,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) break; case IP_VERSION(3, 0, 0): case IP_VERSION(3, 0, 64): + case IP_VERSION(3, 0, 192): if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) fw_name = FIRMWARE_SIENNA_CICHLID; else -- 2.17.1
RE: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID
[Public] A typo. It's better to move 'case IP_VERSION(3, 0, 192)' after IP_VERSION(3, 0, 2)? case IP_VERSION(3, 1, 1): case IP_VERSION(3, 0, 2): + case IP_VERSION(3, 0, 192): amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); if (!amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); break; Regards, Guchun -Original Message- From: amd-gfx On Behalf Of Chen, Guchun Sent: Thursday, November 25, 2021 10:19 AM To: Alex Deucher ; Jian, Jane Cc: Deucher, Alexander ; Chen, JingWen ; amd-gfx list Subject: RE: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID [Public] It's better to move 'case IP_VERSION(3, 0, 192)' after IP_VERSION(3, 0, 192)? case IP_VERSION(3, 1, 1): case IP_VERSION(3, 0, 2): + case IP_VERSION(3, 0, 192): amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); if (!amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); break; Regards, Guchun -Original Message- From: Alex Deucher Sent: Wednesday, November 24, 2021 10:23 PM To: Jian, Jane Cc: Deucher, Alexander ; Chen, Guchun ; Chen, JingWen ; amd-gfx list Subject: Re: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID On Wed, Nov 24, 2021 at 9:20 AM Jane Jian wrote: > > [WHY] > for sriov odd# vf will modify vcn0 engine ip revision(due to > multimedia bandwidth feature), which will be mismatched with original > vcn0 revision > > [HOW] > add new version check for vcn0 disabled revision(3, 0, 192), typically > modified under sriov mode > > Signed-off-by: Jane Jian Reviewed-by: Alex Deucher > Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58 > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > index 503995c7ff6c..3f9b7b0bab3c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > @@ -923,6 +923,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct > amdgpu_device *adev) > amdgpu_device_ip_block_add(adev, > &jpeg_v3_0_ip_block); > break; > case IP_VERSION(3, 0, 33): > + case IP_VERSION(3, 0, 192): > amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); > break; > default: > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > index 4f7c70845785..585961c2f5f2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > @@ -135,6 +135,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) > break; > case IP_VERSION(3, 0, 0): > case IP_VERSION(3, 0, 64): > + case IP_VERSION(3, 0, 192): > if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) > fw_name = FIRMWARE_SIENNA_CICHLID; > else > -- > 2.17.1 >
[PATCH 2/2] amdgpu/pm: Modify implmentations of get_power_profile_mode to use amdgpu_pp_profile_name
After modifying navi10 in previous commit, extend the changes so all
implementations of
pp_hwmgr_func->get_power_profile_mode and
pptable_funcs->get_power_profile_mode use
amdgpu_pp_profile_name
== Test ==
LOGFILE=pp_profile_strings.test.log
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print
$9}'`
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
lspci -nn | grep "VGA\|Display" > $LOGFILE
FILES="pp_power_profile_mode "
for f in $FILES
do
echo === $f === >> $LOGFILE
cat $HWMON_DIR/device/$f >> $LOGFILE
done
cat $LOGFILE
Signed-off-by: Darren Powell
---
.../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 9 +
.../gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c| 14 +++---
.../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 12 +++-
.../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 10 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 10 +-
.../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 10 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 10 +-
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c| 10 +-
8 files changed, 12 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 258c573acc97..a3fb56cbc48e 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1441,13 +1441,6 @@ static int smu10_get_power_profile_mode(struct pp_hwmgr
*hwmgr, char *buf)
{70, 90, 0, 0,},
{30, 60, 0, 6,},
};
- static const char *profile_name[6] = {
- "BOOTUP_DEFAULT",
- "3D_FULL_SCREEN",
- "POWER_SAVING",
- "VIDEO",
- "VR",
- "COMPUTE"};
static const char *title[6] = {"NUM",
"MODE_NAME",
"BUSY_SET_POINT",
@@ -1465,7 +1458,7 @@ static int smu10_get_power_profile_mode(struct pp_hwmgr
*hwmgr, char *buf)
for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d
%14d\n",
- i, profile_name[i], (i == hwmgr->power_profile_mode) ?
"*" : " ",
+ i, amdgpu_pp_profile_name[i], (i ==
hwmgr->power_profile_mode) ? "*" : " ",
profile_mode_setting[i][0], profile_mode_setting[i][1],
profile_mode_setting[i][2], profile_mode_setting[i][3]);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index aceebf584225..3f8f2b89ff80 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -5500,14 +5500,6 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr
*hwmgr, char *buf)
uint32_t i, size = 0;
uint32_t len;
- static const char *profile_name[7] = {"BOOTUP_DEFAULT",
- "3D_FULL_SCREEN",
- "POWER_SAVING",
- "VIDEO",
- "VR",
- "COMPUTE",
- "CUSTOM"};
-
static const char *title[8] = {"NUM",
"MODE_NAME",
"SCLK_UP_HYST",
@@ -5531,7 +5523,7 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr
*hwmgr, char *buf)
for (i = 0; i < len; i++) {
if (i == hwmgr->power_profile_mode) {
size += sysfs_emit_at(buf, size, "%3d %14s %s: %8d %16d
%16d %16d %16d %16d\n",
- i, profile_name[i], "*",
+ i, amdgpu_pp_profile_name[i], "*",
data->current_profile_setting.sclk_up_hyst,
data->current_profile_setting.sclk_down_hyst,
data->current_profile_setting.sclk_activity,
@@ -5542,12 +5534,12 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr
*hwmgr, char *buf)
}
if (smu7_profiling[i].bupdate_sclk)
size += sysfs_emit_at(buf, size, "%3d %16s: %8d %16d
%16d ",
- i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
+ i, amdgpu_pp_profile_name[i],
smu7_profiling[i].sclk_up_hyst,
smu7_profiling[i].sclk_down_hyst,
smu7_profiling[i].sclk_activity);
[PATCH 1/2] amdgpu/pm: Create shared array of power profile name strings
== Description ==
All the power profile modes use the same strings (or a subset of)
Creating a public array of the strings will allow sharing rather than
duplicating for each chip
First patch only implements change for navi10, followup with other chips
== Changes ==
Create a declaration of the public array in kgd_pp_interface.h
Define the public array in amdgpu_pm.c
Modify the implementaiton of navi10_get_power_profile_mode to use new array
== Test ==
LOGFILE=pp_profile_strings.test.log
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print
$9}'`
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
lspci -nn | grep "VGA\|Display" > $LOGFILE
FILES="pp_power_profile_mode "
for f in $FILES
do
echo === $f === >> $LOGFILE
cat $HWMON_DIR/device/$f >> $LOGFILE
done
cat $LOGFILE
Signed-off-by: Darren Powell
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 4
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 10 ++
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 10 +-
3 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index bac15c466733..5c0867ebcfce 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -153,6 +153,10 @@ enum PP_SMC_POWER_PROFILE {
PP_SMC_POWER_PROFILE_COUNT,
};
+extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
+
+
+
enum {
PP_GROUP_UNKNOWN = 0,
PP_GROUP_GFX = 1,
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 41472ed99253..b47d4140859a 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -82,6 +82,16 @@ static const struct hwmon_temp_label {
{PP_TEMP_MEM, "mem"},
};
+const char * const amdgpu_pp_profile_name[] = {
+ "BOOTUP_DEFAULT",
+ "3D_FULL_SCREEN",
+ "POWER_SAVING",
+ "VIDEO",
+ "VR",
+ "COMPUTE",
+ "CUSTOM"
+};
+
/**
* DOC: power_dpm_state
*
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 71161f6b78fe..020f596baed2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1710,14 +1710,6 @@ static int navi10_get_power_profile_mode(struct
smu_context *smu, char *buf)
DpmActivityMonitorCoeffInt_t activity_monitor;
uint32_t i, size = 0;
int16_t workload_type = 0;
- static const char *profile_name[] = {
- "BOOTUP_DEFAULT",
- "3D_FULL_SCREEN",
- "POWER_SAVING",
- "VIDEO",
- "VR",
- "COMPUTE",
- "CUSTOM"};
static const char *title[] = {
"PROFILE_INDEX(NAME)",
"CLOCK_TYPE(NAME)",
@@ -1756,7 +1748,7 @@ static int navi10_get_power_profile_mode(struct
smu_context *smu, char *buf)
}
size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
- i, profile_name[i], (i == smu->power_profile_mode) ?
"*" : " ");
+ i, amdgpu_pp_profile_name[i], (i ==
smu->power_profile_mode) ? "*" : " ");
size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d
%7d %7d %7d %7d %7d\n",
" ",
--
2.33.1
[PATCH 0/2] Create shared array of power profile name strings
== Description ==
All the power profile modes use the same strings (or a subset of)
Creating a public array of the strings will allow sharing rather than
duplicating for each chip
First patch only implements change for navi10
Second patch extends the changes to all other implementations of
pp_hwmgr_func->get_power_profile_mode (smu10, smu7, vega10, vega20)
and pptable_funcs->get_power_profile_mode (arcturus, sienna_cichlid, vangogh,
renoir)
=== Test System ===
* DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2)
+ ISO(Ubuntu 20.04.3 LTS)
+ Kernel(5.13.0-geabeb4f20a07-fdoagd5f)
=== Patch Summary ===
linux: (g...@gitlab.freedesktop.org:agd5f) origin/amd-staging-drm-next @
1e7a606dca04
+ 482319edaabb amdgpu/pm: Create shared array of power profile name strings
+ 1e7a606dca04 amdgpu/pm: Modify implmentations of get_power_profile_mode
to use amdgpu_pp_profile_name
=== Test ===
LOGFILE=pp_profile_strings.test.log
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print
$9}'`
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
lspci -nn | grep "VGA\|Display" > $LOGFILE
FILES="pp_power_profile_mode "
for f in $FILES
do
echo === $f === >> $LOGFILE
cat $HWMON_DIR/device/$f >> $LOGFILE
done
cat $LOGFILE
Darren Powell (2):
amdgpu/pm: Create shared array of power profile name strings
amdgpu/pm: Modify implmentations of get_power_profile_mode to use
amdgpu_pp_profile_name
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 4
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 10 ++
.../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 9 +
.../gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c| 14 +++---
.../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 12 +++-
.../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 10 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 10 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c| 10 +-
.../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 10 +-
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 10 +-
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c| 10 +-
11 files changed, 27 insertions(+), 82 deletions(-)
base-commit: eabeb4f20a0786188fba07a2dd1b0a614c4e15f6
--
2.33.1
RE: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID
[Public] It's better to move 'case IP_VERSION(3, 0, 192)' after IP_VERSION(3, 0, 192)? case IP_VERSION(3, 1, 1): case IP_VERSION(3, 0, 2): + case IP_VERSION(3, 0, 192): amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); if (!amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); break; Regards, Guchun -Original Message- From: Alex Deucher Sent: Wednesday, November 24, 2021 10:23 PM To: Jian, Jane Cc: Deucher, Alexander ; Chen, Guchun ; Chen, JingWen ; amd-gfx list Subject: Re: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID On Wed, Nov 24, 2021 at 9:20 AM Jane Jian wrote: > > [WHY] > for sriov odd# vf will modify vcn0 engine ip revision(due to > multimedia bandwidth feature), which will be mismatched with original > vcn0 revision > > [HOW] > add new version check for vcn0 disabled revision(3, 0, 192), typically > modified under sriov mode > > Signed-off-by: Jane Jian Reviewed-by: Alex Deucher > Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58 > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > index 503995c7ff6c..3f9b7b0bab3c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > @@ -923,6 +923,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct > amdgpu_device *adev) > amdgpu_device_ip_block_add(adev, > &jpeg_v3_0_ip_block); > break; > case IP_VERSION(3, 0, 33): > + case IP_VERSION(3, 0, 192): > amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); > break; > default: > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > index 4f7c70845785..585961c2f5f2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > @@ -135,6 +135,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) > break; > case IP_VERSION(3, 0, 0): > case IP_VERSION(3, 0, 64): > + case IP_VERSION(3, 0, 192): > if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) > fw_name = FIRMWARE_SIENNA_CICHLID; > else > -- > 2.17.1 >
Re: [PATCH v1 7/9] lib: add support for device coherent type in test_hmm
Am 2021-11-15 um 2:30 p.m. schrieb Alex Sierra:
> Device Coherent type uses device memory that is coherently accesible by
> the CPU. This could be shown as SP (special purpose) memory range
> at the BIOS-e820 memory enumeration. If no SP memory is supported in
> system, this could be faked by setting CONFIG_EFI_FAKE_MEMMAP.
>
> Currently, test_hmm only supports two different SP ranges of at least
> 256MB size. This could be specified in the kernel parameter variable
> efi_fake_mem. Ex. Two SP ranges of 1GB starting at 0x1 &
> 0x14000 physical address. Ex.
> efi_fake_mem=1G@0x1:0x4,1G@0x14000:0x4
>
> Signed-off-by: Alex Sierra
> ---
> lib/test_hmm.c | 191 +---
> lib/test_hmm_uapi.h | 15 ++--
> 2 files changed, 153 insertions(+), 53 deletions(-)
>
> diff --git a/lib/test_hmm.c b/lib/test_hmm.c
> index 45334df28d7b..9e2cc0cd4412 100644
> --- a/lib/test_hmm.c
> +++ b/lib/test_hmm.c
> @@ -471,6 +471,7 @@ static int dmirror_allocate_chunk(struct dmirror_device
> *mdevice,
> unsigned long pfn_first;
> unsigned long pfn_last;
> void *ptr;
> + int ret = -ENOMEM;
>
> devmem = kzalloc(sizeof(*devmem), GFP_KERNEL);
> if (!devmem)
> @@ -553,7 +554,7 @@ static int dmirror_allocate_chunk(struct dmirror_device
> *mdevice,
> }
> spin_unlock(&mdevice->lock);
>
> - return true;
> + return 0;
You're changing the meaning of the return value, but you're not updating
the callers. I think at least dmirror_devmem_alloc_page will be broken
by this change.
>
> err_release:
> mutex_unlock(&mdevice->devmem_lock);
> @@ -562,7 +563,7 @@ static int dmirror_allocate_chunk(struct dmirror_device
> *mdevice,
> err_devmem:
> kfree(devmem);
>
> - return false;
> + return ret;
> }
>
> static struct page *dmirror_devmem_alloc_page(struct dmirror_device *mdevice)
> @@ -571,8 +572,10 @@ static struct page *dmirror_devmem_alloc_page(struct
> dmirror_device *mdevice)
> struct page *rpage;
>
> /*
> - * This is a fake device so we alloc real system memory to store
> - * our device memory.
> + * For ZONE_DEVICE private type, this is a fake device so we alloc real
> + * system memory to store our device memory.
> + * For ZONE_DEVICE coherent type we use the actual dpage to store the
> data
> + * and ignore rpage.
>*/
> rpage = alloc_page(GFP_HIGHUSER);
> if (!rpage)
> @@ -623,12 +626,17 @@ static void dmirror_migrate_alloc_and_copy(struct
> migrate_vma *args,
>* unallocated pte_none() or read-only zero page.
>*/
> spage = migrate_pfn_to_page(*src);
> + if (spage && is_zone_device_page(spage))
> + pr_err("page already in device spage pfn: 0x%lx\n",
> + page_to_pfn(spage));
> + WARN_ON(spage && is_zone_device_page(spage));
You can write WARN_ON inside the if-condition:
if (WARN_ON(spage && is_zone_device_page(spage))
...
But I don't see why you need both pr_err and WARN_ON. You can add a
custom message by using WARN instead of WARN_ON:
WARN(spage && is_zone_device_page(spage),
"page already in device spage pfn: 0x%lx\n",
page_to_pfn(spage));
>
> dpage = dmirror_devmem_alloc_page(mdevice);
> if (!dpage)
> continue;
>
> - rpage = dpage->zone_device_data;
> + rpage = is_device_private_page(dpage) ? dpage->zone_device_data
> :
> + dpage;
> if (spage)
> copy_highpage(rpage, spage);
> else
> @@ -640,8 +648,11 @@ static void dmirror_migrate_alloc_and_copy(struct
> migrate_vma *args,
>* the simulated device memory and that page holds the pointer
>* to the mirror.
>*/
> + rpage = dpage->zone_device_data;
> rpage->zone_device_data = dmirror;
>
> + pr_debug("migrating from sys to dev pfn src: 0x%lx pfn dst:
> 0x%lx\n",
> + page_to_pfn(spage), page_to_pfn(dpage));
> *dst = migrate_pfn(page_to_pfn(dpage)) |
> MIGRATE_PFN_LOCKED;
> if ((*src & MIGRATE_PFN_WRITE) ||
> @@ -721,10 +732,13 @@ static int dmirror_migrate_finalize_and_map(struct
> migrate_vma *args,
> continue;
>
> /*
> - * Store the page that holds the data so the page table
> - * doesn't have to deal with ZONE_DEVICE private pages.
> + * For ZONE_DEVICE private pages we store the page that
> + * holds the data so the page table doesn't have to deal it.
> + * For ZONE_DEVICE coherent pages we store the actual page,
> since
> + * the CPU
Re: [PATCH v6] drm/amdgpu: handle IH ring1 overflow
Am 2021-11-24 um 5:58 p.m. schrieb Philip Yang:
> IH ring1 is used to process GPU retry fault, overflow is enabled to
> drain retry fault because we want receive other interrupts while
> handling retry fault to recover range. There is no overflow flag set
> when wptr pass rptr. Use timestamp of rptr and wptr to handle overflow
> and drain retry fault.
>
> Add amdgpu_ih_function interface decode_iv_ts for different chips to get
> timestamp from IV entry with different iv size and timestamp offset.
> amdgpu_ih_decode_iv_ts_helper is used for vega10, vega20, navi10.
>
> Drain retry fault is done if processed_timestamp is equal to or larger
> than checkpoint timestamp. Page fault handler skips retry fault entry if
> entry timestamp goes backward.
>
> Signed-off-by: Philip Yang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 58 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 16 ++-
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 +++
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +++
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 1 +
> drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +-
> 8 files changed, 56 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> index 0c7963dfacad..3e043acaab82 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> @@ -164,52 +164,32 @@ void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih,
> const uint32_t *iv,
> }
> }
>
> -/* Waiter helper that checks current rptr matches or passes checkpoint wptr
> */
> -static bool amdgpu_ih_has_checkpoint_processed(struct amdgpu_device *adev,
> - struct amdgpu_ih_ring *ih,
> - uint32_t checkpoint_wptr,
> - uint32_t *prev_rptr)
> -{
> - uint32_t cur_rptr = ih->rptr | (*prev_rptr & ~ih->ptr_mask);
> -
> - /* rptr has wrapped. */
> - if (cur_rptr < *prev_rptr)
> - cur_rptr += ih->ptr_mask + 1;
> - *prev_rptr = cur_rptr;
> -
> - /* check ring is empty to workaround missing wptr overflow flag */
> - return cur_rptr >= checkpoint_wptr ||
> -(cur_rptr & ih->ptr_mask) == amdgpu_ih_get_wptr(adev, ih);
> -}
> -
> /**
> - * amdgpu_ih_wait_on_checkpoint_process - wait to process IVs up to
> checkpoint
> + * amdgpu_ih_wait_on_checkpoint_process_ts - wait to process IVs up to
> checkpoint
> *
> * @adev: amdgpu_device pointer
> * @ih: ih ring to process
> *
> * Used to ensure ring has processed IVs up to the checkpoint write pointer.
> */
> -int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev,
> +int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
> struct amdgpu_ih_ring *ih)
> {
> - uint32_t checkpoint_wptr, rptr;
> + uint32_t checkpoint_wptr;
> + uint64_t checkpoint_ts;
> + long timeout = HZ;
>
> if (!ih->enabled || adev->shutdown)
> return -ENODEV;
>
> checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);
> - /* Order wptr with rptr. */
> + /* Order wptr with ring data. */
> rmb();
> - rptr = READ_ONCE(ih->rptr);
> -
> - /* wptr has wrapped. */
> - if (rptr > checkpoint_wptr)
> - checkpoint_wptr += ih->ptr_mask + 1;
> + checkpoint_ts = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1);
>
> - return wait_event_interruptible(ih->wait_process,
> - amdgpu_ih_has_checkpoint_processed(adev, ih,
> - checkpoint_wptr, &rptr));
> + return wait_event_interruptible_timeout(ih->wait_process,
> + !amdgpu_ih_ts_after(ih->processed_timestamp, checkpoint_ts),
> + timeout);
> }
>
> /**
> @@ -298,4 +278,22 @@ void amdgpu_ih_decode_iv_helper(struct amdgpu_device
> *adev,
>
> /* wptr/rptr are in bytes! */
> ih->rptr += 32;
> + if (ih == &adev->irq.ih1 &&
> + amdgpu_ih_ts_after(ih->processed_timestamp, entry->timestamp))
> + ih->processed_timestamp = entry->timestamp;
I'd call this "latest_decoded_timestamp". At this point it hasn't been
processed yet.
Also, I think it would be safe and cheap enough to do this on all IH
rings, in case someone finds it useful for something else, e.g. using
amdgpu_ih_wait_on_checkpoint_process_ts on IH ring 0.
> +}
> +
> +uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
> +signed int offset)
> +{
> + uint32_t iv_size = 32;
> + uint32_t dw1, dw2;
> + uint32_t index;
> +
> + rptr += iv_size * offset;
> + index = (rptr & ih->ptr_mask) >> 2;
> +
> + dw1 = le32_to_cpu(ih->ring[index + 1]);
> + dw2 = le32_to_cpu(ih->ring[in
[PATCH v6] drm/amdgpu: handle IH ring1 overflow
IH ring1 is used to process GPU retry fault, overflow is enabled to
drain retry fault because we want receive other interrupts while
handling retry fault to recover range. There is no overflow flag set
when wptr pass rptr. Use timestamp of rptr and wptr to handle overflow
and drain retry fault.
Add amdgpu_ih_function interface decode_iv_ts for different chips to get
timestamp from IV entry with different iv size and timestamp offset.
amdgpu_ih_decode_iv_ts_helper is used for vega10, vega20, navi10.
Drain retry fault is done if processed_timestamp is equal to or larger
than checkpoint timestamp. Page fault handler skips retry fault entry if
entry timestamp goes backward.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 58 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 16 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 +++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +++
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +-
8 files changed, 56 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 0c7963dfacad..3e043acaab82 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -164,52 +164,32 @@ void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih,
const uint32_t *iv,
}
}
-/* Waiter helper that checks current rptr matches or passes checkpoint wptr */
-static bool amdgpu_ih_has_checkpoint_processed(struct amdgpu_device *adev,
- struct amdgpu_ih_ring *ih,
- uint32_t checkpoint_wptr,
- uint32_t *prev_rptr)
-{
- uint32_t cur_rptr = ih->rptr | (*prev_rptr & ~ih->ptr_mask);
-
- /* rptr has wrapped. */
- if (cur_rptr < *prev_rptr)
- cur_rptr += ih->ptr_mask + 1;
- *prev_rptr = cur_rptr;
-
- /* check ring is empty to workaround missing wptr overflow flag */
- return cur_rptr >= checkpoint_wptr ||
- (cur_rptr & ih->ptr_mask) == amdgpu_ih_get_wptr(adev, ih);
-}
-
/**
- * amdgpu_ih_wait_on_checkpoint_process - wait to process IVs up to checkpoint
+ * amdgpu_ih_wait_on_checkpoint_process_ts - wait to process IVs up to
checkpoint
*
* @adev: amdgpu_device pointer
* @ih: ih ring to process
*
* Used to ensure ring has processed IVs up to the checkpoint write pointer.
*/
-int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev,
+int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
struct amdgpu_ih_ring *ih)
{
- uint32_t checkpoint_wptr, rptr;
+ uint32_t checkpoint_wptr;
+ uint64_t checkpoint_ts;
+ long timeout = HZ;
if (!ih->enabled || adev->shutdown)
return -ENODEV;
checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);
- /* Order wptr with rptr. */
+ /* Order wptr with ring data. */
rmb();
- rptr = READ_ONCE(ih->rptr);
-
- /* wptr has wrapped. */
- if (rptr > checkpoint_wptr)
- checkpoint_wptr += ih->ptr_mask + 1;
+ checkpoint_ts = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1);
- return wait_event_interruptible(ih->wait_process,
- amdgpu_ih_has_checkpoint_processed(adev, ih,
- checkpoint_wptr, &rptr));
+ return wait_event_interruptible_timeout(ih->wait_process,
+ !amdgpu_ih_ts_after(ih->processed_timestamp, checkpoint_ts),
+ timeout);
}
/**
@@ -298,4 +278,22 @@ void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
/* wptr/rptr are in bytes! */
ih->rptr += 32;
+ if (ih == &adev->irq.ih1 &&
+ amdgpu_ih_ts_after(ih->processed_timestamp, entry->timestamp))
+ ih->processed_timestamp = entry->timestamp;
+}
+
+uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
+ signed int offset)
+{
+ uint32_t iv_size = 32;
+ uint32_t dw1, dw2;
+ uint32_t index;
+
+ rptr += iv_size * offset;
+ index = (rptr & ih->ptr_mask) >> 2;
+
+ dw1 = le32_to_cpu(ih->ring[index + 1]);
+ dw2 = le32_to_cpu(ih->ring[index + 2]);
+ return dw1 | ((u64)(dw2 & 0x) << 32);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 0649b59830a5..dd1c2eded6b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -68,20 +68,30 @@ struct amdgpu_ih_ring {
/* For waiting on IH processing at checkpoint. */
wait_queue_head_t wait_process;
+ uint64_tprocessed_ti
Re: [PATCH v5] drm/amdgpu: handle IH ring1 overflow
On 2021-11-24 10:33 a.m., Christian König wrote: Am 24.11.21 um 16:23 schrieb philip yang: [SNIP] +/** + * amdgpu_ih_process1 - interrupt handler work for IH ring1 + * + * @adev: amdgpu_device pointer + * @ih: ih ring to process + * + * Interrupt handler of IH ring1, walk the IH ring1. + * Returns irq process return code. + */ +int amdgpu_ih_process1(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) I don't think we need this new function any more. The check if the timestamp goes backwards can now be done inside the page fault handler. Do you mean to merge this into the original ring0 interrupt handler? Then we need add parameter (ih->overflow_enabled) and process two different cases in ring0 interrupt handler, I think that is not good to maintain later so I want to separate them. What I mean is you don't need any different handling any more if we use the timestamp anyway. Just keep the last processed timestamp in the page fault code and ignore faults when it starts to go backwards. If IVs should be dropped or processed as much as possible is depending on quite a bunch of things and should probably not be handled in the IH code in general. Use ih->processed_timestamp updated in decode_iv, for both checkpoint process and page fault handler to drop stale fault. interrupt handler don't need change. Thanks, Philip Regards, Christian.
Re: [PATCH v1] drm/amd/display: Add DP-HDMI PCON SST Support
On 2021-11-24 12:28 p.m., Fangzhi Zuo wrote:
1. Parse DSC caps from PCON DPCD
2. Determine policy if decoding DSC at PCON
3. Enable/disable DSC at PCON
Signed-off-by: Fangzhi Zuo
Reviewed-by: Nicholas Kazlauskas
Regards,
Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 +++
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 13 +-
2 files changed, 44 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9a1ac657faa2..9dbf6bf3f1c3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6047,10 +6047,12 @@ static void update_dsc_caps(struct amdgpu_dm_connector
*aconnector,
if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
sink->sink_signal == SIGNAL_TYPE_EDP)) {
- dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
-
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
-
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
- dsc_caps);
+ if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
+ sink->link->dpcd_caps.dongle_type ==
DISPLAY_DONGLE_DP_HDMI_CONVERTER)
+ dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
+
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
+
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
+ dsc_caps);
}
}
@@ -6120,6 +6122,8 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
uint32_t link_bandwidth_kbps;
uint32_t max_dsc_target_bpp_limit_override = 0;
struct dc *dc = sink->ctx->dc;
+ uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps;
+ uint32_t dsc_max_supported_bw_in_kbps;
link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
dc_link_get_link_cap(aconnector->dc_link));
@@ -6138,16 +6142,37 @@ static void apply_dsc_policy_for_stream(struct
amdgpu_dm_connector *aconnector,
apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps,
max_dsc_target_bpp_limit_override);
} else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
-
- if
(dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
+ if
(dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
dsc_caps,
aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
max_dsc_target_bpp_limit_override,
link_bandwidth_kbps,
&stream->timing,
&stream->timing.dsc_cfg)) {
- stream->timing.flags.DSC = 1;
- DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n",
__func__, drm_connector->name);
+ stream->timing.flags.DSC = 1;
+ DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST
RX\n",
+__func__,
drm_connector->name);
+ }
+ } else if (sink->link->dpcd_caps.dongle_type ==
DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
+ timing_bw_in_kbps =
dc_bandwidth_in_kbps_from_timing(&stream->timing);
+ max_supported_bw_in_kbps = link_bandwidth_kbps;
+ dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
+
+ if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
+ max_supported_bw_in_kbps > 0 &&
+ dsc_max_supported_bw_in_kbps > 0)
+ if
(dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ dsc_caps,
+
aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
+
max_dsc_target_bpp_limit_override,
+ dsc_max_supported_bw_in_kbps,
+ &stream->timing,
+ &stream->timing.dsc_cfg)) {
+ stream->timi
Re: [PATCH] drm/amd/display: fix 64 bit divide
On 11/24/21 8:36 AM, Alex Deucher wrote:
Use do_div.
Fixes: c34f1652a18c4b ("drm/amd/display: fixed an error related to 4:2:0/4:2:2
DSC")
Reported-by: kernel test robot
Reported-by: Randy Dunlap
Cc: Bing Guo
Signed-off-by: Alex Deucher
Acked-by: Randy Dunlap # build-tested
Thanks.
---
drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
index 381561ee0026..7e306aa3e2b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
@@ -100,6 +100,7 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config
*pps, struct dsc_par
int ret;
struct rc_params rc;
struct drm_dsc_config dsc_cfg;
+ unsigned long long tmp;
calc_rc_params(&rc, pps);
dsc_params->pps = *pps;
@@ -111,9 +112,9 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config
*pps, struct dsc_par
dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 :
64;
ret = drm_dsc_compute_rc_parameters(&dsc_cfg);
- dsc_params->bytes_per_pixel =
- (uint32_t)(((unsigned long
long)dsc_cfg.slice_chunk_size * 0x1000 + (dsc_cfg.slice_width - 1))
- /
(uint32_t)dsc_cfg.slice_width); //ROUND-UP
+ tmp = (unsigned long long)dsc_cfg.slice_chunk_size * 0x1000 +
(dsc_cfg.slice_width - 1);
+ do_div(tmp, (uint32_t)dsc_cfg.slice_width); //ROUND-UP
+ dsc_params->bytes_per_pixel = (uint32_t)tmp;
copy_pps_fields(&dsc_params->pps, &dsc_cfg);
dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits;
--
~Randy
[pull] amdgpu, amdkfd drm-fixes-5.16
Hi Dave, Daniel, Fixes for 5.16. The following changes since commit 136057256686de39cc3a07c2e39ef6bc43003ff6: Linux 5.16-rc2 (2021-11-21 13:47:39 -0800) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-5.16-2021-11-24 for you to fetch changes up to 692cd92e66ee10597676530573a495dc1d3bec6a: drm/amd/display: update bios scratch when setting backlight (2021-11-24 15:14:36 -0500) amd-drm-fixes-5.16-2021-11-24: amdgpu: - SRIOV fixes - dma-buf double free fix - Display fixes for GPU resets - Fix DSC powergating regression - GPU TSC fixes - Interrupt handler overflow fixes - Endian fix in IP discovery table handling - Aldebaran ASPM fix - Fix overclocking regression on older asics - Backlight/ACPI fix amdkfd: - SVM fixes - VMA removal race fix Alex Deucher (4): drm/amdgpu/gfx10: add wraparound gpu counter check for APUs as well drm/amdgpu/gfx9: switch to golden tsc registers for renoir+ drm/amdgpu/pm: fix powerplay OD interface drm/amd/display: update bios scratch when setting backlight Felix Kuehling (1): drm/amdgpu: Fix MMIO HDP flush on SRIOV Lijo Lazar (1): drm/amdgpu: Skip ASPM programming on aldebaran Nicholas Kazlauskas (3): drm/amd/display: Fix DPIA outbox timeout after GPU reset drm/amd/display: Set plane update flags for all planes in reset drm/amd/display: Reset link encoder assignments for GPU reset Philip Yang (6): drm/amdgpu: IH process reset count when restart drm/amdkfd: process exit and retry fault race drm/amdkfd: handle VMA remove race drm/amdkfd: simplify drain retry fault drm/amdgpu: enable Navi 48-bit IH timestamp counter drm/amdgpu: enable Navi retry fault wptr overflow Yang Wang (1): drm/amdgpu: fix byteorder error in amdgpu discovery Yi-Ling Chen (1): drm/amd/display: Fixed DSC would not PG after removing DSC stream shaoyunl (1): drm/amdgpu: move kfd post_reset out of reset_sriov function xinhui pan (1): drm/amdgpu: Fix double free of dmabuf drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 -- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 12 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 12 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 ++- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 46 +++-- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 34 +++ drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 4 + drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 4 + drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 4 + drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 7 +- drivers/gpu/drm/amd/amdgpu/nv.c| 8 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 111 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 2 +- .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 20 ++-- .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c| 24 ++--- .../gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c| 6 +- .../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 28 +++--- .../gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 10 +- .../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 58 ++- 28 files changed, 279 insertions(+), 186 deletions(-)
Re: [PATCH v5] drm/amdgpu: handle IH ring1 overflow
Am 2021-11-24 um 10:23 a.m. schrieb philip yang: >>> #define amdgpu_ih_get_wptr(adev, ih) >>> (adev)->irq.ih_funcs->get_wptr((adev), (ih)) >>> #define amdgpu_ih_decode_iv(adev, iv) \ >>> (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv)) >>> +#define amdgpu_ih_decode_iv_ts(adev, ih, rptr, offset) \ >>> + (WARN_ON_ONCE(!(adev)->irq.ih_funcs->decode_iv_ts) ? 0 : \ >> >> Please drop that WARN_ON_ONCE here. >> > Agree, will drop it. > I suggested this. We're assuming that this function will never be called on hardware that doesn't support time stamps, and that all hardware with time stamps will implement the decode_iv_ts function. But it's good to get a log message if that assumption is ever broken, rather than just silently getting wrong results. Regards, Felix > Regards, > > Philip >
kernel 5.15.x: AMD RX 6700 XT - Fails to resume after screen blank
Hi all, TL;DR - git bisection points to https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.4&id=61d861cf478576d85d6032f864360a34b26084b1 as causing an issue when changing power state after idle. Since 5.15.0 I have had intermittent issues with my GPU failing to resume after entering power saving. I have errors like these: Nov 18 09:52:19 katana kernel: [ 4921.669813] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:21 katana kernel: [ 4923.667803] snd_hda_intel :0d:00.1: refused to change power state from D0 to D3hot Nov 18 09:52:26 katana kernel: [ 4928.622234] amdgpu :0d:00.0: amdgpu: Failed to export SMU metrics table! Nov 18 09:52:31 katana kernel: [ 4933.371814] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:31 katana kernel: [ 4933.650854] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:32 katana kernel: [ 4933.921708] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:32 katana kernel: [ 4933.940249] amdgpu :0d:00.0: amdgpu: SMU: I'm not done with your previous command! Nov 18 09:52:32 katana kernel: [ 4933.940254] amdgpu :0d:00.0: amdgpu: Failed to export SMU metrics table! Nov 18 09:52:32 katana kernel: [ 4934.192236] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:32 katana kernel: [ 4934.463213] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:33 katana kernel: [ 4934.736895] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:33 katana kernel: [ 4935.007928] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:33 katana kernel: [ 4935.279063] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:33 katana kernel: [ 4935.550243] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:34 katana kernel: [ 4935.824034] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:34 katana kernel: [ 4936.095158] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:34 katana kernel: [ 4936.366210] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:34 katana kernel: [ 4936.629193] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:35 katana kernel: [ 4936.886333] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:35 katana kernel: [ 4937.140815] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:35 katana kernel: [ 4937.395341] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:35 katana kernel: [ 4937.649885] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:36 katana kernel: [ 4937.906944] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 Nov 18 09:52:36 katana kernel: [ 4938.162866] [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 this eventually leads to processes crashing, and the system locking up during shutdown. A git bisection has isolated the following patch as the cause. commit 8f0284f190e6a0aa09015090568c03f18288231a (refs/bisect/bad) Merge: 5bea1c8ce673 61d861cf4785 Author: Dave Airlie Date: Mon Aug 30 09:06:01 2021 +1000 Merge tag 'amd-drm-next-5.15-2021-08-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.15-2021-08-27: amdgpu: - PLL fix for SI - Misc code cleanups - RAS fixes - PSP cleanups - Polaris UVD/VCE suspend fixes - aldebaran fixes - DCN3.x mclk fixes amdkfd: - CWSR fixes for arcturus and aldebaran - SVM fixes Signed-off-by: Dave Airlie From: Alex Deucher Link: https://patchwork.freedesktop.org/patch/msgid/20210827192336.4649-1-alexander.deuc...@amd.com commit 61d861cf478576d85d6032f864360a34b26084b1 (HEAD) Author: Nicholas Kazlauskas Date: Wed May 13 11:58:50 2020 -0400 drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to bounding box [Why] This is a global parameter, not a per pipe parameter and it's useful for experimenting with the prefetch schedule to be adjustable from the SOC bb. [How] Add a parameter to the SOC bb, default is the existing policy for all DCN. Fill it in when filling SOC bb parameters. Revert the policy to use MinDCFClk at the same time since that's not going to give us P-State in most cases on the spreadsheet. Bug: https://gitlab.freedesktop.
Re: [PATCH] drm/amd/display: Fix warning comparing pointer to 0
On 2021-11-24 5:20 a.m., Jiapeng Chong wrote: Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c:96:14-15: WARNING comparing pointer to 0. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index 122ba29..ec636d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -93,7 +93,7 @@ static void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, TABLE_CASE(420, 12, min); } - if (table == 0) + if (!table) return; index = (bpp - table[0].bpp) * 2; Reviewed-by: Rodrigo Siqueira Applied to amd-staging-drm-next Thanks
Re: [PATCH] drm/amd/display: update bios scratch when setting backlight
On 2021-11-24 13:55, Alex Deucher wrote:
> On Wed, Nov 24, 2021 at 1:52 PM Harry Wentland wrote:
>>
>> On 2021-11-24 11:36, Alex Deucher wrote:
>>> Update the bios scratch register when updating the backlight
>>> level. Some platforms apparently read this scratch register
>>> and do additional operations in their hotkey handlers.
>>>
>>> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1518
>>> Signed-off-by: Alex Deucher
>>
>> Maybe dce_driver_set_backlight should handle this but doing this
>> in amdgpu also works. I don't know if I have a preference either
>> way.
>
> Might be helpful for other OSes unless they handle the bios scratch
> registers some other way. Also does dce_driver_set_backlight() handle
> OLED and aux controlled backlights?
>
No, that has its own codepath and other OSes tend to always use the ABM
path which uses DMCU/DMUB for programming backlight. I'm not sure if they
let FW handle that or deal with it in the DM for the OS. Hence your approach
is possibly more sensible in amdgpu.
Harry
> Alex
>
>>
>> Reviewed-by: Harry Wentland
>>
>> Harry
>>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 12
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 2 ++
>>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
>>> 3 files changed, 18 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
>>> index 96b7bb13a2dd..12a6b1c99c93 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
>>> @@ -1569,6 +1569,18 @@ void amdgpu_atombios_scratch_regs_engine_hung(struct
>>> amdgpu_device *adev,
>>> WREG32(adev->bios_scratch_reg_offset + 3, tmp);
>>> }
>>>
>>> +void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device
>>> *adev,
>>> + u32 backlight_level)
>>> +{
>>> + u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);
>>> +
>>> + tmp &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
>>> + tmp |= (backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
>>> + ATOM_S2_CURRENT_BL_LEVEL_MASK;
>>> +
>>> + WREG32(adev->bios_scratch_reg_offset + 2, tmp);
>>> +}
>>> +
>>> bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
>>> {
>>> u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
>>> index 8cc0222dba19..27e74b1fc260 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
>>> @@ -185,6 +185,8 @@ bool
>>> amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev);
>>> void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool
>>> lock);
>>> void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
>>> bool hung);
>>> +void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device
>>> *adev,
>>> + u32 backlight_level);
>>> bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
>>>
>>> void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> index 40a4269770fa..05e4a0952a2b 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> @@ -51,6 +51,7 @@
>>> #include
>>> #endif
>>> #include "amdgpu_pm.h"
>>> +#include "amdgpu_atombios.h"
>>>
>>> #include "amd_shared.h"
>>> #include "amdgpu_dm_irq.h"
>>> @@ -3918,6 +3919,9 @@ static int amdgpu_dm_backlight_set_level(struct
>>> amdgpu_display_manager *dm,
>>> caps = dm->backlight_caps[bl_idx];
>>>
>>> dm->brightness[bl_idx] = user_brightness;
>>> + /* update scratch register */
>>> + if (bl_idx == 0)
>>> + amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev,
>>> dm->brightness[bl_idx]);
>>> brightness = convert_brightness_from_user(&caps,
>>> dm->brightness[bl_idx]);
>>> link = (struct dc_link *)dm->backlight_link[bl_idx];
>>>
>>>
>>
Re: [PATCH] drm/amd/display: update bios scratch when setting backlight
On Wed, Nov 24, 2021 at 1:52 PM Harry Wentland wrote:
>
> On 2021-11-24 11:36, Alex Deucher wrote:
> > Update the bios scratch register when updating the backlight
> > level. Some platforms apparently read this scratch register
> > and do additional operations in their hotkey handlers.
> >
> > Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1518
> > Signed-off-by: Alex Deucher
>
> Maybe dce_driver_set_backlight should handle this but doing this
> in amdgpu also works. I don't know if I have a preference either
> way.
Might be helpful for other OSes unless they handle the bios scratch
registers some other way. Also does dce_driver_set_backlight() handle
OLED and aux controlled backlights?
Alex
>
> Reviewed-by: Harry Wentland
>
> Harry
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 12
> > drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 2 ++
> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
> > 3 files changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> > index 96b7bb13a2dd..12a6b1c99c93 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> > @@ -1569,6 +1569,18 @@ void amdgpu_atombios_scratch_regs_engine_hung(struct
> > amdgpu_device *adev,
> > WREG32(adev->bios_scratch_reg_offset + 3, tmp);
> > }
> >
> > +void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device
> > *adev,
> > + u32 backlight_level)
> > +{
> > + u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);
> > +
> > + tmp &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
> > + tmp |= (backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
> > + ATOM_S2_CURRENT_BL_LEVEL_MASK;
> > +
> > + WREG32(adev->bios_scratch_reg_offset + 2, tmp);
> > +}
> > +
> > bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
> > {
> > u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
> > index 8cc0222dba19..27e74b1fc260 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
> > @@ -185,6 +185,8 @@ bool
> > amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev);
> > void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool
> > lock);
> > void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
> > bool hung);
> > +void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device
> > *adev,
> > + u32 backlight_level);
> > bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
> >
> > void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 40a4269770fa..05e4a0952a2b 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -51,6 +51,7 @@
> > #include
> > #endif
> > #include "amdgpu_pm.h"
> > +#include "amdgpu_atombios.h"
> >
> > #include "amd_shared.h"
> > #include "amdgpu_dm_irq.h"
> > @@ -3918,6 +3919,9 @@ static int amdgpu_dm_backlight_set_level(struct
> > amdgpu_display_manager *dm,
> > caps = dm->backlight_caps[bl_idx];
> >
> > dm->brightness[bl_idx] = user_brightness;
> > + /* update scratch register */
> > + if (bl_idx == 0)
> > + amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev,
> > dm->brightness[bl_idx]);
> > brightness = convert_brightness_from_user(&caps,
> > dm->brightness[bl_idx]);
> > link = (struct dc_link *)dm->backlight_link[bl_idx];
> >
> >
>
Re: [PATCH] drm/amd/display: update bios scratch when setting backlight
On 2021-11-24 11:36, Alex Deucher wrote:
> Update the bios scratch register when updating the backlight
> level. Some platforms apparently read this scratch register
> and do additional operations in their hotkey handlers.
>
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1518
> Signed-off-by: Alex Deucher
Maybe dce_driver_set_backlight should handle this but doing this
in amdgpu also works. I don't know if I have a preference either
way.
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 12
> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 2 ++
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
> 3 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> index 96b7bb13a2dd..12a6b1c99c93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> @@ -1569,6 +1569,18 @@ void amdgpu_atombios_scratch_regs_engine_hung(struct
> amdgpu_device *adev,
> WREG32(adev->bios_scratch_reg_offset + 3, tmp);
> }
>
> +void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device
> *adev,
> + u32 backlight_level)
> +{
> + u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);
> +
> + tmp &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
> + tmp |= (backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
> + ATOM_S2_CURRENT_BL_LEVEL_MASK;
> +
> + WREG32(adev->bios_scratch_reg_offset + 2, tmp);
> +}
> +
> bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
> {
> u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
> index 8cc0222dba19..27e74b1fc260 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
> @@ -185,6 +185,8 @@ bool amdgpu_atombios_has_gpu_virtualization_table(struct
> amdgpu_device *adev);
> void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool
> lock);
> void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
> bool hung);
> +void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device
> *adev,
> + u32 backlight_level);
> bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
>
> void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 40a4269770fa..05e4a0952a2b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -51,6 +51,7 @@
> #include
> #endif
> #include "amdgpu_pm.h"
> +#include "amdgpu_atombios.h"
>
> #include "amd_shared.h"
> #include "amdgpu_dm_irq.h"
> @@ -3918,6 +3919,9 @@ static int amdgpu_dm_backlight_set_level(struct
> amdgpu_display_manager *dm,
> caps = dm->backlight_caps[bl_idx];
>
> dm->brightness[bl_idx] = user_brightness;
> + /* update scratch register */
> + if (bl_idx == 0)
> + amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev,
> dm->brightness[bl_idx]);
> brightness = convert_brightness_from_user(&caps,
> dm->brightness[bl_idx]);
> link = (struct dc_link *)dm->backlight_link[bl_idx];
>
>
RE: [PATCH] drm/amd/display: fix 64 bit divide
[AMD Official Use Only]
Reviewed-by: Bing Guo <
-Original Message-
From: Deucher, Alexander
Sent: Wednesday, November 24, 2021 11:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; kernel test robot
; Randy Dunlap ; Guo, Bing
Subject: [PATCH] drm/amd/display: fix 64 bit divide
Use do_div.
Fixes: c34f1652a18c4b ("drm/amd/display: fixed an error related to 4:2:0/4:2:2
DSC")
Reported-by: kernel test robot
Reported-by: Randy Dunlap
Cc: Bing Guo
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
index 381561ee0026..7e306aa3e2b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
@@ -100,6 +100,7 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config
*pps, struct dsc_par
int ret;
struct rc_params rc;
struct drm_dsc_config dsc_cfg;
+ unsigned long long tmp;
calc_rc_params(&rc, pps);
dsc_params->pps = *pps;
@@ -111,9 +112,9 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config
*pps, struct dsc_par
dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 :
64;
ret = drm_dsc_compute_rc_parameters(&dsc_cfg);
- dsc_params->bytes_per_pixel =
- (uint32_t)(((unsigned long
long)dsc_cfg.slice_chunk_size * 0x1000 + (dsc_cfg.slice_width - 1))
- /
(uint32_t)dsc_cfg.slice_width); //ROUND-UP
+ tmp = (unsigned long long)dsc_cfg.slice_chunk_size * 0x1000 +
(dsc_cfg.slice_width - 1);
+ do_div(tmp, (uint32_t)dsc_cfg.slice_width); //ROUND-UP
+ dsc_params->bytes_per_pixel = (uint32_t)tmp;
copy_pps_fields(&dsc_params->pps, &dsc_cfg);
dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits;
--
2.31.1
[PATCH v1] drm/amd/display: Add DP-HDMI PCON SST Support
1. Parse DSC caps from PCON DPCD
2. Determine policy if decoding DSC at PCON
3. Enable/disable DSC at PCON
Signed-off-by: Fangzhi Zuo
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 +++
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 13 +-
2 files changed, 44 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9a1ac657faa2..9dbf6bf3f1c3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6047,10 +6047,12 @@ static void update_dsc_caps(struct amdgpu_dm_connector
*aconnector,
if (aconnector->dc_link && (sink->sink_signal ==
SIGNAL_TYPE_DISPLAY_PORT ||
sink->sink_signal == SIGNAL_TYPE_EDP)) {
- dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
-
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
-
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
- dsc_caps);
+ if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
+ sink->link->dpcd_caps.dongle_type ==
DISPLAY_DONGLE_DP_HDMI_CONVERTER)
+ dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
+
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
+
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
+ dsc_caps);
}
}
@@ -6120,6 +6122,8 @@ static void apply_dsc_policy_for_stream(struct
amdgpu_dm_connector *aconnector,
uint32_t link_bandwidth_kbps;
uint32_t max_dsc_target_bpp_limit_override = 0;
struct dc *dc = sink->ctx->dc;
+ uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps;
+ uint32_t dsc_max_supported_bw_in_kbps;
link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
dc_link_get_link_cap(aconnector->dc_link));
@@ -6138,16 +6142,37 @@ static void apply_dsc_policy_for_stream(struct
amdgpu_dm_connector *aconnector,
apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps,
max_dsc_target_bpp_limit_override);
} else if (aconnector->dc_link && sink->sink_signal ==
SIGNAL_TYPE_DISPLAY_PORT) {
-
- if
(dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
+ if
(dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
dsc_caps,
aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
max_dsc_target_bpp_limit_override,
link_bandwidth_kbps,
&stream->timing,
&stream->timing.dsc_cfg)) {
- stream->timing.flags.DSC = 1;
- DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST
RX\n", __func__, drm_connector->name);
+ stream->timing.flags.DSC = 1;
+ DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from
SST RX\n",
+__func__,
drm_connector->name);
+ }
+ } else if (sink->link->dpcd_caps.dongle_type ==
DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
+ timing_bw_in_kbps =
dc_bandwidth_in_kbps_from_timing(&stream->timing);
+ max_supported_bw_in_kbps = link_bandwidth_kbps;
+ dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
+
+ if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
+ max_supported_bw_in_kbps > 0 &&
+ dsc_max_supported_bw_in_kbps > 0)
+ if
(dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ dsc_caps,
+
aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
+
max_dsc_target_bpp_limit_override,
+ dsc_max_supported_bw_in_kbps,
+ &stream->timing,
+ &stream->timing.dsc_cfg)) {
+ stream->timing.flags.DSC = 1;
+ DRM_DEBUG_DRIVER("%s: [%s] DSC is
selected from DP
[PATCH] drm/amd/display: fix 64 bit divide
Use do_div.
Fixes: c34f1652a18c4b ("drm/amd/display: fixed an error related to 4:2:0/4:2:2
DSC")
Reported-by: kernel test robot
Reported-by: Randy Dunlap
Cc: Bing Guo
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
index 381561ee0026..7e306aa3e2b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
@@ -100,6 +100,7 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config
*pps, struct dsc_par
int ret;
struct rc_params rc;
struct drm_dsc_config dsc_cfg;
+ unsigned long long tmp;
calc_rc_params(&rc, pps);
dsc_params->pps = *pps;
@@ -111,9 +112,9 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config
*pps, struct dsc_par
dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 :
64;
ret = drm_dsc_compute_rc_parameters(&dsc_cfg);
- dsc_params->bytes_per_pixel =
- (uint32_t)(((unsigned long
long)dsc_cfg.slice_chunk_size * 0x1000 + (dsc_cfg.slice_width - 1))
- /
(uint32_t)dsc_cfg.slice_width); //ROUND-UP
+ tmp = (unsigned long long)dsc_cfg.slice_chunk_size * 0x1000 +
(dsc_cfg.slice_width - 1);
+ do_div(tmp, (uint32_t)dsc_cfg.slice_width); //ROUND-UP
+ dsc_params->bytes_per_pixel = (uint32_t)tmp;
copy_pps_fields(&dsc_params->pps, &dsc_cfg);
dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits;
--
2.31.1
[PATCH] drm/amd/display: update bios scratch when setting backlight
Update the bios scratch register when updating the backlight
level. Some platforms apparently read this scratch register
and do additional operations in their hotkey handlers.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1518
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 12
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 2 ++
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
3 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 96b7bb13a2dd..12a6b1c99c93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1569,6 +1569,18 @@ void amdgpu_atombios_scratch_regs_engine_hung(struct
amdgpu_device *adev,
WREG32(adev->bios_scratch_reg_offset + 3, tmp);
}
+void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device
*adev,
+ u32 backlight_level)
+{
+ u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);
+
+ tmp &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
+ tmp |= (backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
+ ATOM_S2_CURRENT_BL_LEVEL_MASK;
+
+ WREG32(adev->bios_scratch_reg_offset + 2, tmp);
+}
+
bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
{
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
index 8cc0222dba19..27e74b1fc260 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
@@ -185,6 +185,8 @@ bool amdgpu_atombios_has_gpu_virtualization_table(struct
amdgpu_device *adev);
void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
bool hung);
+void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device
*adev,
+ u32 backlight_level);
bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 40a4269770fa..05e4a0952a2b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -51,6 +51,7 @@
#include
#endif
#include "amdgpu_pm.h"
+#include "amdgpu_atombios.h"
#include "amd_shared.h"
#include "amdgpu_dm_irq.h"
@@ -3918,6 +3919,9 @@ static int amdgpu_dm_backlight_set_level(struct
amdgpu_display_manager *dm,
caps = dm->backlight_caps[bl_idx];
dm->brightness[bl_idx] = user_brightness;
+ /* update scratch register */
+ if (bl_idx == 0)
+ amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev,
dm->brightness[bl_idx]);
brightness = convert_brightness_from_user(&caps,
dm->brightness[bl_idx]);
link = (struct dc_link *)dm->backlight_link[bl_idx];
--
2.31.1
Re: linux-next: Tree for Nov 24 (drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.o)
On 11/23/21 9:16 PM, Stephen Rothwell wrote: Hi all, Changes since 20211123: on i386: ld: drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.o: in function `dscc_compute_dsc_parameters': rc_calc_dpi.c:(.text+0x31f): undefined reference to `__udivdi3' -- ~Randy
Re: [PATCH v5] drm/amdgpu: handle IH ring1 overflow
Am 24.11.21 um 16:23 schrieb philip yang: [SNIP] +/** + * amdgpu_ih_process1 - interrupt handler work for IH ring1 + * + * @adev: amdgpu_device pointer + * @ih: ih ring to process + * + * Interrupt handler of IH ring1, walk the IH ring1. + * Returns irq process return code. + */ +int amdgpu_ih_process1(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) I don't think we need this new function any more. The check if the timestamp goes backwards can now be done inside the page fault handler. Do you mean to merge this into the original ring0 interrupt handler? Then we need add parameter (ih->overflow_enabled) and process two different cases in ring0 interrupt handler, I think that is not good to maintain later so I want to separate them. What I mean is you don't need any different handling any more if we use the timestamp anyway. Just keep the last processed timestamp in the page fault code and ignore faults when it starts to go backwards. If IVs should be dropped or processed as much as possible is depending on quite a bunch of things and should probably not be handled in the IH code in general. Regards, Christian.
Re: [PATCH v5] drm/amdgpu: handle IH ring1 overflow
On 2021-11-24 4:37 a.m., Christian
König wrote:
Am
23.11.21 um 20:22 schrieb Philip Yang:
IH ring1 is used to process GPU retry
fault, overflow is enabled to
drain retry fault because we want receive other interrupts while
handling retry fault to recover range. There is no overflow flag
set
when wptr pass rptr. Use timestamp of rptr and wptr to handle
overflow
and drain retry fault.
Add helper function amdgpu_ih_decode_iv_ts to get 48bit
timestamp from
IV entry. drain retry fault is done if processed_timestamp is
equal to or larger than checkpoint timestamp.
Add function amdgpu_ih_process1 to process IH ring1 until
timestamp of
rptr is larger then timestamp of next entry.
Helper amdgpu_ih_ts_after to compare time stamps with 48bit wrap
around.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 107
++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 13 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +-
7 files changed, 99 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 0c7963dfacad..30b4e0e01444 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -164,52 +164,45 @@ void amdgpu_ih_ring_write(struct
amdgpu_ih_ring *ih, const uint32_t *iv,
}
}
+/* return true if time stamp t2 is after t1 with 48bit wrap
around */
+static inline bool amdgpu_ih_ts_after(uint64_t t1, uint64_t t2)
+{
+ return ((int64_t)(t2 << 16) - (int64_t)(t1 <<
16)) > 0LL;
+}
+
/* Waiter helper that checks current rptr matches or passes
checkpoint wptr */
-static bool amdgpu_ih_has_checkpoint_processed(struct
amdgpu_device *adev,
+static bool amdgpu_ih_has_checkpoint_processed_ts(struct
amdgpu_device *adev,
struct amdgpu_ih_ring *ih,
- uint32_t checkpoint_wptr,
- uint32_t *prev_rptr)
+ uint64_t checkpoint_ts)
{
- uint32_t cur_rptr = ih->rptr | (*prev_rptr &
~ih->ptr_mask);
-
- /* rptr has wrapped. */
- if (cur_rptr < *prev_rptr)
- cur_rptr += ih->ptr_mask + 1;
- *prev_rptr = cur_rptr;
-
- /* check ring is empty to workaround missing wptr overflow
flag */
- return cur_rptr >= checkpoint_wptr ||
- (cur_rptr & ih->ptr_mask) ==
amdgpu_ih_get_wptr(adev, ih);
+ return !amdgpu_ih_ts_after(ih->processed_timestamp,
checkpoint_ts);
I don't see much of a reason to keep this function, it only
consists of a call to amdgpu_ih_ts_after() and is used only once.
Will remove this function.
}
/**
- * amdgpu_ih_wait_on_checkpoint_process - wait to process IVs
up to checkpoint
+ * amdgpu_ih_wait_on_checkpoint_process_ts - wait to process
IVs up to checkpoint
*
* @adev: amdgpu_device pointer
* @ih: ih ring to process
*
* Used to ensure ring has processed IVs up to the checkpoint
write pointer.
*/
-int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device
*adev,
+int amdgpu_ih_wait_on_checkpoint_process_ts(struct
amdgpu_device *adev,
struct amdgpu_ih_ring *ih)
{
- uint32_t checkpoint_wptr, rptr;
+ uint32_t checkpoint_wptr;
+ uint64_t checkpoint_ts;
if (!ih->enabled || adev->shutdown)
[bug report] drm/amd/display: check top_pipe_to_program pointer
Hello Yang Li,
This is a semi-automatic email about new static checker warnings.
The patch a689e8d1f800: "drm/amd/display: check top_pipe_to_program
pointer" from Nov 15, 2021, leads to the following Smatch complaint:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3064
commit_planes_for_stream()
error: we previously assumed 'top_pipe_to_program' could be null (see line
2887)
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c
2822 static void commit_planes_for_stream(struct dc *dc,
2823 struct dc_surface_update *srf_updates,
2824 int surface_count,
2825 struct dc_stream_state *stream,
2826 struct dc_stream_update *stream_update,
2827 enum surface_update_type update_type,
2828 struct dc_state *context)
2829 {
2830 int i, j;
2831 struct pipe_ctx *top_pipe_to_program = NULL;
Set to NULL here
2832 bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
2833
2834 #if defined(CONFIG_DRM_AMD_DC_DCN)
2835 dc_z10_restore(dc);
2836 #endif
2837
2838 if (get_seamless_boot_stream_count(context) > 0 &&
surface_count > 0) {
2839 /* Optimize seamless boot flag keeps clocks and
watermarks high until
2840 * first flip. After first flip, optimization is
required to lower
2841 * bandwidth. Important to note that it is expected
UEFI will
2842 * only light up a single display on POST, therefore we
only expect
2843 * one stream with seamless boot flag set.
2844 */
2845 if (stream->apply_seamless_boot_optimization) {
2846 stream->apply_seamless_boot_optimization =
false;
2847
2848 if (get_seamless_boot_stream_count(context) ==
0)
2849 dc->optimized_required = true;
2850 }
2851 }
2852
2853 if (update_type == UPDATE_TYPE_FULL) {
2854 #if defined(CONFIG_DRM_AMD_DC_DCN)
2855 dc_allow_idle_optimizations(dc, false);
2856
2857 #endif
2858 if (get_seamless_boot_stream_count(context) == 0)
2859 dc->hwss.prepare_bandwidth(dc, context);
2860
2861 context_clock_trace(dc, context);
2862 }
2863
2864 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2865 struct pipe_ctx *pipe_ctx =
&context->res_ctx.pipe_ctx[j];
2866
2867 if (!pipe_ctx->top_pipe &&
2868 !pipe_ctx->prev_odm_pipe &&
2869 pipe_ctx->stream &&
2870 pipe_ctx->stream == stream) {
2871 top_pipe_to_program = pipe_ctx;
^^
Set to non-NULL here.
2872 }
2873 }
2874
2875 #ifdef CONFIG_DRM_AMD_DC_DCN
2876 if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
2877 struct pipe_ctx *mpcc_pipe;
2878 struct pipe_ctx *odm_pipe;
2879
2880 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe;
mpcc_pipe = mpcc_pipe->bottom_pipe)
2881 for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe =
odm_pipe->next_odm_pipe)
2882 odm_pipe->ttu_regs.min_ttu_vblank =
MAX_TTU;
2883 }
2884 #endif
2885
2886 if ((update_type != UPDATE_TYPE_FAST) &&
stream->update_flags.bits.dsc_changed)
2887 if (top_pipe_to_program &&
^^^
The patch adds a new NULL check to make clang happy.
2888
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2889 if (should_use_dmub_lock(stream->link)) {
2890 union dmub_hw_lock_flags hw_locks = { 0
};
2891 struct dmub_hw_lock_inst_flags
inst_flags = { 0 };
2892
2893 hw_locks.bits.lock_dig = 1;
2894 inst_flags.dig_inst =
top_pipe_to_program->stream_res.tg->inst;
2895
2896 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2897 true,
2898 &hw_locks,
2899 &inst_flags);
2900 } else
2901
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2902
top_pipe_to_program->stream_res.t
Re: [PATCH 3/3] drm/amdgpu: check atomic flag to differeniate with legacy path
[AMD Official Use Only]
Series is:
Reviewed-by: Alex Deucher
From: Cui, Flora
Sent: Tuesday, November 23, 2021 9:43 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org
; Deucher, Alexander
Cc: Cui, Flora ; Alex Deucher
Subject: [PATCH 3/3] drm/amdgpu: check atomic flag to differeniate with legacy
path
since vkms support atomic KMS interface
Signed-off-by: Flora Cui
Reviewed-by: Guchun Chen
Acked-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7d4115d52523..8e9e50aa4a95 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3830,7 +3830,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
/* disable all interrupts */
amdgpu_irq_disable_all(adev);
if (adev->mode_info.mode_config_initialized){
- if (!amdgpu_device_has_dc_support(adev))
+ if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
drm_helper_force_disable_all(adev_to_drm(adev));
else
drm_atomic_helper_shutdown(adev_to_drm(adev));
@@ -5124,7 +5124,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
drm_sched_start(&ring->sched,
!tmp_adev->asic_reset_res);
}
- if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
+ if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) &&
!job_signaled) {
drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
}
--
2.25.1
Re: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID
On Wed, Nov 24, 2021 at 9:20 AM Jane Jian wrote: > > [WHY] > for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia > bandwidth feature), > which will be mismatched with original vcn0 revision > > [HOW] > add new version check for vcn0 disabled revision(3, 0, 192), typically > modified under > sriov mode > > Signed-off-by: Jane Jian Reviewed-by: Alex Deucher > Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58 > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > index 503995c7ff6c..3f9b7b0bab3c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > @@ -923,6 +923,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct > amdgpu_device *adev) > amdgpu_device_ip_block_add(adev, > &jpeg_v3_0_ip_block); > break; > case IP_VERSION(3, 0, 33): > + case IP_VERSION(3, 0, 192): > amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); > break; > default: > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > index 4f7c70845785..585961c2f5f2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > @@ -135,6 +135,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) > break; > case IP_VERSION(3, 0, 0): > case IP_VERSION(3, 0, 64): > + case IP_VERSION(3, 0, 192): > if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) > fw_name = FIRMWARE_SIENNA_CICHLID; > else > -- > 2.17.1 >
[PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID
[WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58 --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 503995c7ff6c..3f9b7b0bab3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -923,6 +923,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); break; case IP_VERSION(3, 0, 33): + case IP_VERSION(3, 0, 192): amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 4f7c70845785..585961c2f5f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -135,6 +135,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) break; case IP_VERSION(3, 0, 0): case IP_VERSION(3, 0, 64): + case IP_VERSION(3, 0, 192): if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) fw_name = FIRMWARE_SIENNA_CICHLID; else -- 2.17.1
Re: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID
On Wed, Nov 24, 2021 at 4:54 AM Jane Jian wrote: > > [WHY] > for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia > bandwidth feature), > which will be mismatched with original vcn0 revision > > [HOW] > add new version check for vcn0 disabled revision > > Signed-off-by: Jane Jian > Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58 > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +++ > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > index 503995c7ff6c..1dabbcbc3970 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c > @@ -925,6 +925,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct > amdgpu_device *adev) > case IP_VERSION(3, 0, 33): > amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); > break; > + case IP_VERSION(3, 0, 192): You can probably just add this case to the above 3.0.33 case. > + amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); > + break; > default: > dev_err(adev->dev, > "Failed to add vcn/jpeg ip > block(UVD_HWIP:0x%x)\n", > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > index 4f7c70845785..27125e5e3092 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > @@ -143,6 +143,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) > (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) > adev->vcn.indirect_sram = true; > break; > + case IP_VERSION(3, 0, 192): > + if (amdgpu_sriov_vf(adev)) I think you can skip the sr-iov check here. > + fw_name = FIRMWARE_SIENNA_CICHLID; > + break; > case IP_VERSION(3, 0, 2): > fw_name = FIRMWARE_VANGOGH; > break; > -- > 2.17.1 >
[PATCH] drm/amd/display: Fix warning comparing pointer to 0
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c:96:14-15: WARNING comparing pointer to 0. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index 122ba29..ec636d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -93,7 +93,7 @@ static void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, TABLE_CASE(420, 12, min); } - if (table == 0) + if (!table) return; index = (bpp - table[0].bpp) * 2; -- 1.8.3.1
[PATCH] drm/amd/display: fix application of sizeof to pointer
From: Lv Ruyi
Both of split and merge are pointers, not arrays.
Reported-by: Zeal Robot
Signed-off-by: Lv Ruyi
---
drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
index ece34b0b8a46..91810aaee5a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
@@ -1223,8 +1223,8 @@ static void dml_full_validate_bw_helper(struct dc *dc,
*pipe_cnt = dml_populate_dml_pipes_from_context(dc, context,
pipes, false);
*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes,
*pipe_cnt);
if (*vlevel < context->bw_ctx.dml.soc.num_states) {
- memset(split, 0, sizeof(split));
- memset(merge, 0, sizeof(merge));
+ memset(split, 0, MAX_PIPES * sizeof(*split));
+ memset(merge, 0, MAX_PIPES * sizeof(*merge));
*vlevel = dml_validate_apply_pipe_split_flags(dc,
context, *vlevel, split, merge);
}
--
2.25.1
Re: [PATCH v2] drm/amdgpu: reset asic after system-wide suspend aborted (v2)
On 11/24/2021 6:13 PM, Prike Liang wrote:
Do ASIC reset at the moment Sx suspend aborted behind of amdgpu suspend
to keep AMDGPU in a clean reset state and that can avoid re-initialize
device improperly error. Currently,we just always do asic reset in the
amdgpu resume until sort out the PM abort case.
v2: Remove incomplete PM abort flag and add GPU hive case check for
GPU reset.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7d4115d..3fcd90d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3983,6 +3983,14 @@ int amdgpu_device_resume(struct drm_device *dev, bool
fbcon)
if (adev->in_s0ix)
amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
+ /*TODO: In order to not let all-always asic reset affect resume latency
+* need sort out the case which really need asic reset in the resume
process.
+* As to the known issue on the system suspend abort behind the AMDGPU
suspend,
+* may can sort this case by checking struct suspend_stats which need
exported
+* firstly.
+*/
+ if (adev->gmc.xgmi.num_physical_nodes <= 1)
+ amdgpu_asic_reset(adev);
Newer dGPUs depend on PMFW to do reset and that is not loaded at this
point. For some, there is a mini FW available which could technically
handle a reset and some of the older ones depend on PSP. Strongly
suggest to check all such cases before doing a reset here.
Or, the safest at this point could be to do the reset only for APUs.
Thanks,
Lijo
/* post card */
if (amdgpu_device_need_post(adev)) {
r = amdgpu_device_asic_init(adev);
[PATCH v2] drm/amdgpu: reset asic after system-wide suspend aborted (v2)
Do ASIC reset at the moment Sx suspend aborted behind of amdgpu suspend
to keep AMDGPU in a clean reset state and that can avoid re-initialize
device improperly error. Currently,we just always do asic reset in the
amdgpu resume until sort out the PM abort case.
v2: Remove incomplete PM abort flag and add GPU hive case check for
GPU reset.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7d4115d..3fcd90d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3983,6 +3983,14 @@ int amdgpu_device_resume(struct drm_device *dev, bool
fbcon)
if (adev->in_s0ix)
amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
+ /*TODO: In order to not let all-always asic reset affect resume latency
+* need sort out the case which really need asic reset in the resume
process.
+* As to the known issue on the system suspend abort behind the AMDGPU
suspend,
+* may can sort this case by checking struct suspend_stats which need
exported
+* firstly.
+*/
+ if (adev->gmc.xgmi.num_physical_nodes <= 1)
+ amdgpu_asic_reset(adev);
/* post card */
if (amdgpu_device_need_post(adev)) {
r = amdgpu_device_asic_init(adev);
--
2.7.4
RE: [PATCH] drm/amdgpu: Skip ASPM programming on aldebaran
[AMD Official Use Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, November 24, 2021 19:35
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Pawar, Ashish
; Deucher, Alexander
Subject: [PATCH] drm/amdgpu: Skip ASPM programming on aldebaran
There is no need for additional programming, keep the default settings.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index e96516d3fd45..dc5e93756fea 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -694,6 +694,9 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device
*adev) {
uint32_t def, data;
+ if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(7, 4, 4))
+ return;
+
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
--
2.25.1
[PATCH] drm/amdgpu: Skip ASPM programming on aldebaran
There is no need for additional programming, keep the default settings.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index e96516d3fd45..dc5e93756fea 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -694,6 +694,9 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device
*adev)
{
uint32_t def, data;
+ if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(7, 4, 4))
+ return;
+
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
--
2.25.1
Re: [PATCH v3 2/6] drm: improve drm_buddy_alloc function
On 23/11/2021 22:39, Arunpravin wrote:
On 18/11/21 12:09 am, Matthew Auld wrote:
On 16/11/2021 20:18, Arunpravin wrote:
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which allocates
the requested power-of-two block comply with range limitations
- Moved order computation and memory alignment logic from
i915 driver to drm buddy
v2:
merged below changes to keep the build unbroken
- drm_buddy_alloc_range() becomes obsolete and may be removed
- enable ttm range allocation (fpfn / lpfn) support in i915 driver
- apply enhanced drm_buddy_alloc() function to i915 driver
v3(Matthew Auld):
- Fix alignment issues and remove unnecessary list_empty check
- add more validation checks for input arguments
- make alloc_range() block allocations as bottom-up
- optimize order computation logic
- replace uint64_t with u64, which is preferred in the kernel
Signed-off-by: Arunpravin
---
drivers/gpu/drm/drm_buddy.c | 259 ++
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 69 ++---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 2 +
include/drm/drm_buddy.h | 22 +-
4 files changed, 203 insertions(+), 149 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 39eb1d224bec..c9b18a29f8d1 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -274,63 +274,6 @@ void drm_buddy_free_list(struct drm_buddy_mm *mm, struct
list_head *objects)
}
EXPORT_SYMBOL(drm_buddy_free_list);
-/**
- * drm_buddy_alloc - allocate power-of-two blocks
- *
- * @mm: DRM buddy manager to allocate from
- * @order: size of the allocation
- *
- * The order value here translates to:
- *
- * 0 = 2^0 * mm->chunk_size
- * 1 = 2^1 * mm->chunk_size
- * 2 = 2^2 * mm->chunk_size
- *
- * Returns:
- * allocated ptr to the &drm_buddy_block on success
- */
-struct drm_buddy_block *
-drm_buddy_alloc(struct drm_buddy_mm *mm, unsigned int order)
-{
- struct drm_buddy_block *block = NULL;
- unsigned int i;
- int err;
-
- for (i = order; i <= mm->max_order; ++i) {
- block = list_first_entry_or_null(&mm->free_list[i],
-struct drm_buddy_block,
-link);
- if (block)
- break;
- }
-
- if (!block)
- return ERR_PTR(-ENOSPC);
-
- BUG_ON(!drm_buddy_block_is_free(block));
-
- while (i != order) {
- err = split_block(mm, block);
- if (unlikely(err))
- goto out_free;
-
- /* Go low */
- block = block->left;
- i--;
- }
-
- mark_allocated(block);
- mm->avail -= drm_buddy_block_size(mm, block);
- kmemleak_update_trace(block);
- return block;
-
-out_free:
- if (i != order)
- __drm_buddy_free(mm, block);
- return ERR_PTR(err);
-}
-EXPORT_SYMBOL(drm_buddy_alloc);
-
static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2)
{
return s1 <= e2 && e1 >= s2;
@@ -341,52 +284,22 @@ static inline bool contains(u64 s1, u64 e1, u64 s2, u64
e2)
return s1 <= s2 && e1 >= e2;
}
-/**
- * drm_buddy_alloc_range - allocate range
- *
- * @mm: DRM buddy manager to allocate from
- * @blocks: output list head to add allocated blocks
- * @start: start of the allowed range for this block
- * @size: size of the allocation
- *
- * Intended for pre-allocating portions of the address space, for example to
- * reserve a block for the initial framebuffer or similar, hence the
expectation
- * here is that drm_buddy_alloc() is still the main vehicle for
- * allocations, so if that's not the case then the drm_mm range allocator is
- * probably a much better fit, and so you should probably go use that instead.
- *
- * Note that it's safe to chain together multiple alloc_ranges
- * with the same blocks list
- *
- * Returns:
- * 0 on success, error code on failure.
- */
-int drm_buddy_alloc_range(struct drm_buddy_mm *mm,
- struct list_head *blocks,
- u64 start, u64 size)
+static struct drm_buddy_block *
+alloc_range(struct drm_buddy_mm *mm,
+ u64 start, u64 end,
+ unsigned int order)
{
struct drm_buddy_block *block;
struct drm_buddy_block *buddy;
- LIST_HEAD(allocated);
LIST_HEAD(dfs);
- u64 end;
int err;
int i;
- if (size < mm->chunk_size)
- return -EINVAL;
-
- if (!IS_ALIGNED(size | start, mm->chunk_size))
- return -EINVAL;
-
- if (range_overflows(start, size, mm->size))
- return -EINVAL;
+ end = end - 1;
for (i = 0; i < mm->n_roots; ++i)
list_
[PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID
[WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision Signed-off-by: Jane Jian Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58 --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 503995c7ff6c..1dabbcbc3970 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -925,6 +925,9 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(3, 0, 33): amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); break; + case IP_VERSION(3, 0, 192): + amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); + break; default: dev_err(adev->dev, "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 4f7c70845785..27125e5e3092 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -143,6 +143,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; + case IP_VERSION(3, 0, 192): + if (amdgpu_sriov_vf(adev)) + fw_name = FIRMWARE_SIENNA_CICHLID; + break; case IP_VERSION(3, 0, 2): fw_name = FIRMWARE_VANGOGH; break; -- 2.17.1
Re: [PATCH v5] drm/amdgpu: handle IH ring1 overflow
Am 23.11.21 um 20:22 schrieb Philip Yang:
IH ring1 is used to process GPU retry fault, overflow is enabled to
drain retry fault because we want receive other interrupts while
handling retry fault to recover range. There is no overflow flag set
when wptr pass rptr. Use timestamp of rptr and wptr to handle overflow
and drain retry fault.
Add helper function amdgpu_ih_decode_iv_ts to get 48bit timestamp from
IV entry. drain retry fault is done if processed_timestamp is
equal to or larger than checkpoint timestamp.
Add function amdgpu_ih_process1 to process IH ring1 until timestamp of
rptr is larger then timestamp of next entry.
Helper amdgpu_ih_ts_after to compare time stamps with 48bit wrap around.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 107 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 13 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_svm.c| 2 +-
7 files changed, 99 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 0c7963dfacad..30b4e0e01444 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -164,52 +164,45 @@ void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih,
const uint32_t *iv,
}
}
+/* return true if time stamp t2 is after t1 with 48bit wrap around */
+static inline bool amdgpu_ih_ts_after(uint64_t t1, uint64_t t2)
+{
+ return ((int64_t)(t2 << 16) - (int64_t)(t1 << 16)) > 0LL;
+}
+
/* Waiter helper that checks current rptr matches or passes checkpoint wptr */
-static bool amdgpu_ih_has_checkpoint_processed(struct amdgpu_device *adev,
+static bool amdgpu_ih_has_checkpoint_processed_ts(struct amdgpu_device *adev,
struct amdgpu_ih_ring *ih,
- uint32_t checkpoint_wptr,
- uint32_t *prev_rptr)
+ uint64_t checkpoint_ts)
{
- uint32_t cur_rptr = ih->rptr | (*prev_rptr & ~ih->ptr_mask);
-
- /* rptr has wrapped. */
- if (cur_rptr < *prev_rptr)
- cur_rptr += ih->ptr_mask + 1;
- *prev_rptr = cur_rptr;
-
- /* check ring is empty to workaround missing wptr overflow flag */
- return cur_rptr >= checkpoint_wptr ||
- (cur_rptr & ih->ptr_mask) == amdgpu_ih_get_wptr(adev, ih);
+ return !amdgpu_ih_ts_after(ih->processed_timestamp, checkpoint_ts);
I don't see much of a reason to keep this function, it only consists of
a call to amdgpu_ih_ts_after() and is used only once.
}
/**
- * amdgpu_ih_wait_on_checkpoint_process - wait to process IVs up to checkpoint
+ * amdgpu_ih_wait_on_checkpoint_process_ts - wait to process IVs up to
checkpoint
*
* @adev: amdgpu_device pointer
* @ih: ih ring to process
*
* Used to ensure ring has processed IVs up to the checkpoint write pointer.
*/
-int amdgpu_ih_wait_on_checkpoint_process(struct amdgpu_device *adev,
+int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
struct amdgpu_ih_ring *ih)
{
- uint32_t checkpoint_wptr, rptr;
+ uint32_t checkpoint_wptr;
+ uint64_t checkpoint_ts;
if (!ih->enabled || adev->shutdown)
return -ENODEV;
checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);
- /* Order wptr with rptr. */
+ /* Order wptr with ring data. */
rmb();
- rptr = READ_ONCE(ih->rptr);
-
- /* wptr has wrapped. */
- if (rptr > checkpoint_wptr)
- checkpoint_wptr += ih->ptr_mask + 1;
+ checkpoint_ts = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1);
return wait_event_interruptible(ih->wait_process,
- amdgpu_ih_has_checkpoint_processed(adev, ih,
- checkpoint_wptr, &rptr));
+ amdgpu_ih_has_checkpoint_processed_ts(adev, ih,
+ checkpoint_ts));
}
/**
@@ -254,6 +247,56 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct
amdgpu_ih_ring *ih)
return IRQ_HANDLED;
}
+/**
+ * amdgpu_ih_process1 - interrupt handler work for IH ring1
+ *
+ * @adev: amdgpu_device pointer
+ * @ih: ih ring to process
+ *
+ * Interrupt handler of IH ring1, walk the IH ring1.
+ * Returns irq process return code.
+ */
+int amdgpu_ih_process1(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
I don't think we need this new function any more.
The check if the timestamp goes backwards can now be done inside the
page fault handler.
+{
+ uint64_t ts, ts_next;
+ unsigned int count;
+ u32 wptr;
+
+
