[PATCH V3 7/7] drm/amd/pm: revise the implementation of smu_cmn_disable_all_features_with_exception

[Evan Quan]

As there is no internal cache for enabled ppfeatures now. Thus the 2nd
parameter will be not needed any more.

Signed-off-by: Evan Quan 
Change-Id: I0c1811f216c55d6ddfabdc9e099dc214c21bdf2e
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++---
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 -
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 7 ---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h| 1 -
 drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   | 2 +-
 5 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 59be1c822b2c..1c9c11a92d42 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1360,9 +1360,7 @@ static int smu_disable_dpms(struct smu_context *smu)
case IP_VERSION(11, 5, 0):
case IP_VERSION(11, 0, 12):
case IP_VERSION(11, 0, 13):
-   return smu_disable_all_features_with_exception(smu,
-  true,
-  
SMU_FEATURE_COUNT);
+   return 0;
default:
break;
}
@@ -1378,9 +1376,7 @@ static int smu_disable_dpms(struct smu_context *smu)
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 5):
case IP_VERSION(11, 0, 9):
-   return smu_disable_all_features_with_exception(smu,
-  true,
-  
SMU_FEATURE_BACO_BIT);
+   return 0;
default:
break;
}
@@ -1392,7 +1388,6 @@ static int smu_disable_dpms(struct smu_context *smu)
 */
if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
ret = smu_disable_all_features_with_exception(smu,
- false,
  
SMU_FEATURE_BACO_BIT);
if (ret)
dev_err(adev->dev, "Failed to disable smu features 
except BACO.\n");
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 721b4080d3e6..55b24988455d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -990,7 +990,6 @@ struct pptable_funcs {
 *   exception to those in 
 */
int (*disable_all_features_with_exception)(struct smu_context *smu,
-  bool no_hw_disablement,
   enum smu_feature_mask mask);
 
/**
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index acb9f0ca191b..2a6b752a6996 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -767,9 +767,6 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
  *   @mask
  *
  * @smu:   smu_context pointer
- * @no_hw_disablement: whether real dpm disablement should be performed
- * true: update the cache(about dpm enablement state) only
- * false: real dpm disablement plus cache update
  * @mask:  the dpm feature which should not be disabled
  * SMU_FEATURE_COUNT: no exception, all dpm features
  * to disable
@@ -778,7 +775,6 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
  * 0 on success or a negative error code on failure.
  */
 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
-   bool no_hw_disablement,
enum smu_feature_mask mask)
 {
uint64_t features_to_disable = U64_MAX;
@@ -794,9 +790,6 @@ int smu_cmn_disable_all_features_with_exception(struct 
smu_context *smu,
features_to_disable &= ~(1ULL << skipped_feature_id);
}
 
-   if (no_hw_disablement)
-   return 0;
-
return smu_cmn_feature_update_enable_state(smu,
   features_to_disable,
   0);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index bfe3430829c7..a4c593ed8b03 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -79,7 +79,6 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
uint64_t new_mask);
 
 

[PATCH V3 6/7] drm/amd/pm: avoid consecutive retrieving for enabled ppfeatures

[Evan Quan]

As the enabled ppfeatures are just retrieved ahead. We can use
that directly instead of retrieving again and again.

Signed-off-by: Evan Quan 
Change-Id: I08827437fcbbc52084418c8ca6a90cfa503306a9
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 3d263b27b6c2..acb9f0ca191b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -680,6 +680,7 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
int8_t sort_feature[SMU_FEATURE_COUNT];
size_t size = 0;
int ret = 0, i;
+   int feature_id;
 
ret = smu_cmn_get_enabled_mask(smu,
   _mask);
@@ -708,11 +709,18 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context 
*smu,
if (sort_feature[i] < 0)
continue;
 
+   /* convert to asic spcific feature ID */
+   feature_id = smu_cmn_to_asic_specific_index(smu,
+   
CMN2ASIC_MAPPING_FEATURE,
+   sort_feature[i]);
+   if (feature_id < 0)
+   continue;
+
size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n",
count++,
smu_get_feature_name(smu, sort_feature[i]),
i,
-   !!smu_cmn_feature_is_enabled(smu, 
sort_feature[i]) ?
+   !!test_bit(feature_id, (unsigned long 
*)_mask) ?
"enabled" : "disabled");
}
 
-- 
2.29.0

[PATCH V3 5/7] drm/amd/pm: drop the cache for enabled ppfeatures

[Evan Quan]

The following scenarios make the driver cache for enabled ppfeatures
outdated and invalid:
  - Other tools interact with PMFW to change the enabled ppfeatures.
  - PMFW may enable/disable some features behind driver's back. E.g.
for sienna_cichild, on gfxoff entering, PMFW will disable gfx
related DPM features. All those are performed without driver's
notice.
Also considering driver does not actually interact with PMFW such
frequently, the benefit brought by such cache is very limited.

Signed-off-by: Evan Quan 
Change-Id: I20ed58ab216e930c7a5d223be1eb99146889f2b3
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  1 -
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 -
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 23 +-
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 16 +--
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 23 +-
 .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  | 16 +--
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 46 +--
 7 files changed, 17 insertions(+), 109 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 803068cb5079..59be1c822b2c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -950,7 +950,6 @@ static int smu_sw_init(void *handle)
smu->pool_size = adev->pm.smu_prv_buffer_size;
smu->smu_feature.feature_num = SMU_FEATURE_MAX;
bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
-   bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 
mutex_init(>message_lock);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 8cd1c3bb595a..721b4080d3e6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -390,7 +390,6 @@ struct smu_feature
uint32_t feature_num;
DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
-   DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
 };
 
 struct smu_clocks {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index d36b64371492..d71155a66f97 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -798,27 +798,8 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 int smu_v11_0_system_features_control(struct smu_context *smu,
 bool en)
 {
-   struct smu_feature *feature = >smu_feature;
-   uint64_t feature_mask;
-   int ret = 0;
-
-   ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
-SMU_MSG_DisableAllSmuFeatures), NULL);
-   if (ret)
-   return ret;
-
-   bitmap_zero(feature->enabled, feature->feature_num);
-
-   if (en) {
-   ret = smu_cmn_get_enabled_mask(smu, _mask);
-   if (ret)
-   return ret;
-
-   bitmap_copy(feature->enabled, (unsigned long *)_mask,
-   feature->feature_num);
-   }
-
-   return ret;
+   return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
+ SMU_MSG_DisableAllSmuFeatures), NULL);
 }
 
 int smu_v11_0_notify_display_change(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 478151e72889..96a5b31f708d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -1947,27 +1947,13 @@ static int vangogh_get_dpm_clock_table(struct 
smu_context *smu, struct dpm_clock
 static int vangogh_system_features_control(struct smu_context *smu, bool en)
 {
struct amdgpu_device *adev = smu->adev;
-   struct smu_feature *feature = >smu_feature;
-   uint64_t feature_mask;
int ret = 0;
 
if (adev->pm.fw_version >= 0x43f1700 && !en)
ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_RlcPowerNotify,
  RLC_STATUS_OFF, NULL);
 
-   bitmap_zero(feature->enabled, feature->feature_num);
-
-   if (!en)
-   return ret;
-
-   ret = smu_cmn_get_enabled_mask(smu, _mask);
-   if (ret)
-   return ret;
-
-   bitmap_copy(feature->enabled, (unsigned long *)_mask,
-   feature->feature_num);
-
-   return 0;
+   return ret;
 }
 
 static int vangogh_post_smu_init(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 92b5c1108a2e..f0ab1dc3ca59 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ 

[PATCH V3 3/7] drm/amd/pm: update the data type for retrieving enabled ppfeatures

[Evan Quan]

Use uint64_t instead of an array of uint32_t. This can avoid
some non-necessary intermediate uint32_t -> uint64_t conversions.

Signed-off-by: Evan Quan 
Reviewed-by: Alex Deucher 
Change-Id: I4e217357203a23440f058d7e25f55eaebd15c5ef
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  2 +-
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  5 ++--
 .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c |  5 +---
 .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c   |  6 +---
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  5 +---
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  5 +---
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c|  4 +--
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 10 ++-
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c|  7 ++---
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  4 +--
 .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  |  9 ++
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 29 +++
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h|  3 +-
 drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   |  2 +-
 14 files changed, 32 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 9861d70a5dad..ae48cc5aa567 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2310,7 +2310,7 @@ static int smu_read_sensor(void *handle,
*size = 4;
break;
case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
-   ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
+   ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
*size = 8;
break;
case AMDGPU_PP_SENSOR_UVD_POWER:
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 4c585241ef66..8cd1c3bb595a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -975,10 +975,9 @@ struct pptable_funcs {
/**
 * @get_enabled_mask: Get a mask of features that are currently enabled
 *on the SMU.
-* _mask: Array representing enabled feature mask.
-* : Elements in _mask.
+* _mask: Enabled feature mask.
 */
-   int (*get_enabled_mask)(struct smu_context *smu, uint32_t 
*feature_mask, uint32_t num);
+   int (*get_enabled_mask)(struct smu_context *smu, uint64_t 
*feature_mask);
 
/**
 * @feature_is_enabled: Test if a feature is enabled.
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index ee296441c5bc..63f2b50cd486 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -2022,15 +2022,12 @@ static void arcturus_dump_pptable(struct smu_context 
*smu)
 static bool arcturus_is_dpm_running(struct smu_context *smu)
 {
int ret = 0;
-   uint32_t feature_mask[2];
uint64_t feature_enabled;
 
-   ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
+   ret = smu_cmn_get_enabled_mask(smu, _enabled);
if (ret)
return false;
 
-   feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
-
return !!(feature_enabled & SMC_DPM_FEATURE);
 }
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index cc080a0075ee..2b38a9154dd4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -350,20 +350,16 @@ static bool cyan_skillfish_is_dpm_running(struct 
smu_context *smu)
 {
struct amdgpu_device *adev = smu->adev;
int ret = 0;
-   uint32_t feature_mask[2];
uint64_t feature_enabled;
 
/* we need to re-init after suspend so return false */
if (adev->in_suspend)
return false;
 
-   ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
+   ret = smu_cmn_get_enabled_mask(smu, _enabled);
if (ret)
return false;
 
-   feature_enabled = (uint64_t)feature_mask[0] |
-   ((uint64_t)feature_mask[1] << 32);
-
/*
 * cyan_skillfish specific, query default sclk inseted of hard code.
 */
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 4a86520d01c3..84cbde3f913d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1639,15 +1639,12 @@ static int navi10_display_config_changed(struct 
smu_context *smu)
 static bool navi10_is_dpm_running(struct smu_context *smu)
 {
int ret = 0;
-   uint32_t feature_mask[2];
uint64_t feature_enabled;
 
-   ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);

[PATCH V3 4/7] drm/amd/pm: correct the usage for 'supported' member of smu_feature structure

[Evan Quan]

The supported features should be retrieved just after EnableAllDpmFeatures 
message
complete. And the check(whether some dpm feature is supported) is only needed 
when we
decide to enable or disable it.

Signed-off-by: Evan Quan 
Change-Id: I07c9a5ac5290cd0d88a40ce1768d393156419b5a
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 11 +++
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  8 
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 10 +-
 drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c|  3 ---
 drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  |  5 +
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  3 ---
 drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  |  3 ---
 7 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index ae48cc5aa567..803068cb5079 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1057,8 +1057,10 @@ static int smu_get_thermal_temperature_range(struct 
smu_context *smu)
 
 static int smu_smc_hw_setup(struct smu_context *smu)
 {
+   struct smu_feature *feature = >smu_feature;
struct amdgpu_device *adev = smu->adev;
uint32_t pcie_gen = 0, pcie_width = 0;
+   uint64_t features_supported;
int ret = 0;
 
if (adev->in_suspend && smu_is_dpm_running(smu)) {
@@ -1138,6 +1140,15 @@ static int smu_smc_hw_setup(struct smu_context *smu)
return ret;
}
 
+   ret = smu_feature_get_enabled_mask(smu, _supported);
+   if (ret) {
+   dev_err(adev->dev, "Failed to retrieve supported dpm 
features!\n");
+   return ret;
+   }
+   bitmap_copy(feature->supported,
+   (unsigned long *)_supported,
+   feature->feature_num);
+
if (!smu_is_dpm_running(smu))
dev_info(adev->dev, "dpm has been disabled\n");
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 84cbde3f913d..f55ead5f9aba 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1624,8 +1624,8 @@ static int navi10_display_config_changed(struct 
smu_context *smu)
int ret = 0;
 
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
-   smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
-   smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+   smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+   smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_NumOfDisplays,
  
smu->display_config->num_display,
  NULL);
@@ -1860,13 +1860,13 @@ static int navi10_notify_smc_display_config(struct 
smu_context *smu)
min_clocks.dcef_clock_in_sr = 
smu->display_config->min_dcef_deep_sleep_set_clk;
min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
 
-   if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+   if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
clock_req.clock_type = amd_pp_dcef_clock;
clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
 
ret = smu_v11_0_display_clock_voltage_request(smu, _req);
if (!ret) {
-   if (smu_cmn_feature_is_supported(smu, 
SMU_FEATURE_DS_DCEFCLK_BIT)) {
+   if (smu_cmn_feature_is_enabled(smu, 
SMU_FEATURE_DS_DCEFCLK_BIT)) {
ret = smu_cmn_send_smc_msg_with_param(smu,
  
SMU_MSG_SetMinDeepSleepDcefclk,
  
min_clocks.dcef_clock_in_sr/100,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index b6759f8b5167..804e1c98238d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1280,8 +1280,8 @@ static int sienna_cichlid_display_config_changed(struct 
smu_context *smu)
int ret = 0;
 
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
-   smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
-   smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+   smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+   smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 #if 0
ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_NumOfDisplays,
   

[PATCH V3 2/7] drm/amd/pm: unify the interface for retrieving enabled ppfeatures

[Evan Quan]

Instead of having two which do the same thing.

Signed-off-by: Evan Quan 
Change-Id: I6302c9b5abdb999c4b7c83a0d1852181208b1c1f
--
v1->v2:
  - use SMU IP version check rather than an asic type check(Alex)
---
 .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c   |  2 +-
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  |  6 +-
 .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  |  6 +-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 95 ---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h|  4 -
 5 files changed, 46 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 2f57333e6071..cc080a0075ee 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -357,7 +357,7 @@ static bool cyan_skillfish_is_dpm_running(struct 
smu_context *smu)
if (adev->in_suspend)
return false;
 
-   ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+   ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
if (ret)
return false;
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 721027917f81..b4a3c9b8b54e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -507,7 +507,7 @@ static bool vangogh_is_dpm_running(struct smu_context *smu)
if (adev->in_suspend)
return false;
 
-   ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+   ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
 
if (ret)
return false;
@@ -1965,7 +1965,7 @@ static int vangogh_system_features_control(struct 
smu_context *smu, bool en)
if (!en)
return ret;
 
-   ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+   ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
if (ret)
return ret;
 
@@ -2182,7 +2182,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
.dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
.is_dpm_running = vangogh_is_dpm_running,
.read_sensor = vangogh_read_sensor,
-   .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
+   .get_enabled_mask = smu_cmn_get_enabled_mask,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_watermarks_table = vangogh_set_watermarks_table,
.set_driver_table_location = smu_v11_0_set_driver_table_location,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index bd24a2632214..f425827e2361 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -209,7 +209,7 @@ static int yellow_carp_system_features_control(struct 
smu_context *smu, bool en)
if (!en)
return ret;
 
-   ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+   ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
if (ret)
return ret;
 
@@ -258,7 +258,7 @@ static bool yellow_carp_is_dpm_running(struct smu_context 
*smu)
uint32_t feature_mask[2];
uint64_t feature_enabled;
 
-   ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+   ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
 
if (ret)
return false;
@@ -1174,7 +1174,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = 
{
.is_dpm_running = yellow_carp_is_dpm_running,
.set_watermarks_table = yellow_carp_set_watermarks_table,
.get_gpu_metrics = yellow_carp_get_gpu_metrics,
-   .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
+   .get_enabled_mask = smu_cmn_get_enabled_mask,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_driver_table_location = smu_v13_0_set_driver_table_location,
.gfx_off_control = smu_v13_0_gfx_off_control,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index c3c679bf9d9f..c2e6c8b603da 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -545,67 +545,59 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
 uint32_t *feature_mask,
 uint32_t num)
 {
-   uint32_t feature_mask_high = 0, feature_mask_low = 0;
struct smu_feature *feature = >smu_feature;
+   struct amdgpu_device *adev = smu->adev;
+   uint32_t *feature_mask_high;
+   uint32_t *feature_mask_low;
int ret = 0;
 
if (!feature_mask || num < 2)
return -EINVAL;
 
-   if (bitmap_empty(feature->enabled, feature->feature_num)) {
-   ret = smu_cmn_send_smc_msg(smu, 

[PATCH V3 1/7] drm/amd/pm: correct the way for retrieving enabled ppfeatures on Renoir

[Evan Quan]

As other dGPU asics, Renoir should use smu_cmn_get_enabled_mask() for
that job.

Signed-off-by: Evan Quan 
Acked-by: Alex Deucher 
Change-Id: I9e845ba84dd45d0826506de44ef4760fa851a516
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index fcead7c6ca7e..c3c679bf9d9f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -710,7 +710,8 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
size_t size = 0;
int ret = 0, i;
 
-   if (!smu->is_apu) {
+   if (!smu->is_apu ||
+   (smu->adev->asic_type == CHIP_RENOIR)) {
ret = smu_cmn_get_enabled_mask(smu,
feature_mask,
2);
-- 
2.29.0

[PATCH v2] drm/amdgpu: add safeguards for querying GMC CG state

[Lang Yu]

We observed a GPU hang when querying GMC CG state(i.e.,
cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
skillfish doesn't support any CG features.

Only allow ASICs which support GMC CG features accessing
related registers. As some ASICs support GMC CG but cg_flags
are not set. Use GC IP version instead of cg_flags to
determine whether GMC CG is supported or not.

v2:
 - Use a function to encapsulate more functionality.(Christian)
 - Use IP verion to determine whether CG is supported or not.(Lijo)

Signed-off-by: Lang Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 10 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  |  3 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  3 +++
 5 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index d426de48d299..be1f03b02af6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -876,3 +876,13 @@ int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
 
return 0;
 }
+
+bool amdgpu_gmc_cg_enabled(struct amdgpu_device *adev)
+{
+   switch (adev->ip_versions[GC_HWIP][0]) {
+   case IP_VERSION(10, 1, 3):
+   return false;
+   default:
+   return true;
+   }
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 93505bb0a36c..b916e73c7de1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -338,4 +338,5 @@ uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, 
uint64_t mc_addr);
 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo 
*bo);
 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
+bool amdgpu_gmc_cg_enabled(struct amdgpu_device *adev);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 73ab0eebe4e2..4e46f618d6c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1156,6 +1156,9 @@ static void gmc_v10_0_get_clockgating_state(void *handle, 
u32 *flags)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+   if (!amdgpu_gmc_cg_enabled(adev))
+   return;
+
adev->mmhub.funcs->get_clockgating(adev, flags);
 
if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index ca9841d5669f..ff9dff2a6cf1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1695,6 +1695,9 @@ static void gmc_v8_0_get_clockgating_state(void *handle, 
u32 *flags)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int data;
 
+   if (!amdgpu_gmc_cg_enabled(adev))
+   return;
+
if (amdgpu_sriov_vf(adev))
*flags = 0;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 4595027a8c63..faf017609dfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1952,6 +1952,9 @@ static void gmc_v9_0_get_clockgating_state(void *handle, 
u32 *flags)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+   if (!amdgpu_gmc_cg_enabled(adev))
+   return;
+
adev->mmhub.funcs->get_clockgating(adev, flags);
 
athub_v1_0_get_clockgating(adev, flags);
-- 
2.25.1

[PATCH] drm/amdgpu: Fix uninitialized variable use warning

[Lijo Lazar]

Fix uninitialized variable use
warning: variable 'reg_access_ctrl' is uninitialized when used here 
[-Wuninitialized]
 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * 
reg_access_ctrl->scratch_reg0;

Fixes: 51263163eb3f("drm/amdgpu: add helper for rlcg indirect reg
access")

Reported-by: kernel test robot 
Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 80c25176c993..c13765218919 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -875,6 +875,7 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device 
*adev, u32 offset, u32 v
return 0;
}
 
+   reg_access_ctrl = >gfx.rlc.reg_access_ctrl;
scratch_reg0 = (void __iomem *)adev->rmmio + 4 * 
reg_access_ctrl->scratch_reg0;
scratch_reg1 = (void __iomem *)adev->rmmio + 4 * 
reg_access_ctrl->scratch_reg1;
scratch_reg2 = (void __iomem *)adev->rmmio + 4 * 
reg_access_ctrl->scratch_reg2;
-- 
2.25.1

[RFC PATCH v6 3/3] drm: remove allow_fb_modifiers

[Tomohito Esaki]

The allow_fb_modifiers flag is unnecessary since it has been replaced
with fb_modifiers_not_supported flag.

v3:
 - change the order as follows:
   1. add fb_modifiers_not_supported flag
   2. add default modifiers
   3. remove allow_fb_modifiers flag

v5:
 - keep a sanity check in plane init func

Signed-off-by: Tomohito Esaki 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Laurent Pinchart 
---
 drivers/gpu/drm/selftests/test-drm_framebuffer.c |  1 -
 include/drm/drm_mode_config.h| 16 
 2 files changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/selftests/test-drm_framebuffer.c 
b/drivers/gpu/drm/selftests/test-drm_framebuffer.c
index 61b44d3a6a61..f6d66285c5fc 100644
--- a/drivers/gpu/drm/selftests/test-drm_framebuffer.c
+++ b/drivers/gpu/drm/selftests/test-drm_framebuffer.c
@@ -323,7 +323,6 @@ static struct drm_device mock_drm_device = {
.max_width = MAX_WIDTH,
.min_height = MIN_HEIGHT,
.max_height = MAX_HEIGHT,
-   .allow_fb_modifiers = true,
.funcs = _config_funcs,
},
 };
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index 4a93dac91cf9..6b5e01295348 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -917,22 +917,6 @@ struct drm_mode_config {
 */
bool async_page_flip;
 
-   /**
-* @allow_fb_modifiers:
-*
-* Whether the driver supports fb modifiers in the ADDFB2.1 ioctl call.
-* Note that drivers should not set this directly, it is automatically
-* set in drm_universal_plane_init().
-*
-* IMPORTANT:
-*
-* If this is set the driver must fill out the full implicit modifier
-* information in their _mode_config_funcs.fb_create hook for legacy
-* userspace which does not set modifiers. Otherwise the GETFB2 ioctl is
-* broken for modifier aware userspace.
-*/
-   bool allow_fb_modifiers;
-
/**
 * @fb_modifiers_not_supported:
 *
-- 
2.25.1

[RFC PATCH v6 2/3] drm: add support modifiers for drivers whose planes only support linear layout

[Tomohito Esaki]

The LINEAR modifier is advertised as default if a driver doesn't specify
modifiers.

v2:
 - rebase to the latest master branch (5.16.0+)
+ "drm/plane: Make format_mod_supported truly optional" patch [1]
   [1] https://patchwork.freedesktop.org/patch/467940/?series=98255=3

v3:
 - change the order as follows:
   1. add fb_modifiers_not_supported flag
   2. add default modifiers
   3. remove allow_fb_modifiers flag

v5:
 - change default_modifiers array from non-static to static
 - remove terminator in default_modifiers array
 - use ARRAY_SIZE to get the format_modifier_count
 - update sanity check in plane init func to use the
   fb_modifiers_not_supported
 - modify kernel docs

Signed-off-by: Tomohito Esaki 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Laurent Pinchart 
---
 drivers/gpu/drm/drm_plane.c | 23 +--
 include/drm/drm_plane.h |  3 +++
 2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index deeec60a3315..bf0daa8d9bbd 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -237,6 +237,9 @@ static int __drm_universal_plane_init(struct drm_device 
*dev,
  const char *name, va_list ap)
 {
struct drm_mode_config *config = >mode_config;
+   static const uint64_t default_modifiers[] = {
+   DRM_FORMAT_MOD_LINEAR,
+   };
unsigned int format_modifier_count = 0;
int ret;
 
@@ -277,16 +280,16 @@ static int __drm_universal_plane_init(struct drm_device 
*dev,
 
while (*temp_modifiers++ != DRM_FORMAT_MOD_INVALID)
format_modifier_count++;
+   } else {
+   if (!dev->mode_config.fb_modifiers_not_supported) {
+   format_modifiers = default_modifiers;
+   format_modifier_count = ARRAY_SIZE(default_modifiers);
+   }
}
 
/* autoset the cap and check for consistency across all planes */
-   if (format_modifier_count) {
-   drm_WARN_ON(dev, !config->allow_fb_modifiers &&
-   !list_empty(>plane_list));
-   config->allow_fb_modifiers = true;
-   } else {
-   drm_WARN_ON(dev, config->allow_fb_modifiers);
-   }
+   drm_WARN_ON(dev, config->fb_modifiers_not_supported &&
+   format_modifier_count);
 
plane->modifier_count = format_modifier_count;
plane->modifiers = kmalloc_array(format_modifier_count,
@@ -341,7 +344,7 @@ static int __drm_universal_plane_init(struct drm_device 
*dev,
drm_object_attach_property(>base, config->prop_src_h, 0);
}
 
-   if (config->allow_fb_modifiers)
+   if (format_modifier_count)
create_in_format_blob(dev, plane);
 
return 0;
@@ -368,8 +371,8 @@ static int __drm_universal_plane_init(struct drm_device 
*dev,
  * drm_universal_plane_init() to let the DRM managed resource infrastructure
  * take care of cleanup and deallocation.
  *
- * Drivers supporting modifiers must set @format_modifiers on all their planes,
- * even those that only support DRM_FORMAT_MOD_LINEAR.
+ * Drivers that only support the DRM_FORMAT_MOD_LINEAR modifier support may set
+ * @format_modifiers to NULL. The plane will advertise the linear modifier.
  *
  * Returns:
  * Zero on success, error code on failure.
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 0c1102dc4d88..a0390b6ad3b4 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -803,6 +803,9 @@ void *__drmm_universal_plane_alloc(struct drm_device *dev,
  *
  * The @drm_plane_funcs.destroy hook must be NULL.
  *
+ * Drivers that only support the DRM_FORMAT_MOD_LINEAR modifier support may set
+ * @format_modifiers to NULL. The plane will advertise the linear modifier.
+ *
  * Returns:
  * Pointer to new plane, or ERR_PTR on failure.
  */
-- 
2.25.1

[RFC PATCH v6 1/3] drm: introduce fb_modifiers_not_supported flag in mode_config

[Tomohito Esaki]

If only linear modifier is advertised, since there are many drivers that
only linear supported, the DRM core should handle this rather than
open-coding in every driver. However, there are legacy drivers such as
radeon that do not support modifiers but infer the actual layout of the
underlying buffer. Therefore, a new flag fb_modifiers_not_supported is
introduced for these legacy drivers, and allow_fb_modifiers is replaced
with this new flag.

v3:
 - change the order as follows:
   1. add fb_modifiers_not_supported flag
   2. add default modifiers
   3. remove allow_fb_modifiers flag
 - add a conditional disable in amdgpu_dm_plane_init()

v4:
 - modify kernel docs

v5:
 - modify kernel docs

Signed-off-by: Tomohito Esaki 
Acked-by: Harry Wentland 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Laurent Pinchart 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  6 +++---
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|  2 ++
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  2 ++
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |  1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  2 ++
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +++
 drivers/gpu/drm/drm_framebuffer.c |  6 +++---
 drivers/gpu/drm/drm_ioctl.c   |  2 +-
 drivers/gpu/drm/nouveau/nouveau_display.c |  6 --
 drivers/gpu/drm/radeon/radeon_display.c   |  2 ++
 include/drm/drm_mode_config.h | 10 ++
 11 files changed, 33 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 82011e75ed85..edbb30d47b8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -954,7 +954,7 @@ static int amdgpu_display_verify_sizes(struct 
amdgpu_framebuffer *rfb)
int ret;
unsigned int i, block_width, block_height, block_size_log2;
 
-   if (!rfb->base.dev->mode_config.allow_fb_modifiers)
+   if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
return 0;
 
for (i = 0; i < format_info->num_planes; ++i) {
@@ -1141,7 +1141,7 @@ int amdgpu_display_framebuffer_init(struct drm_device 
*dev,
if (ret)
return ret;
 
-   if (!dev->mode_config.allow_fb_modifiers) {
+   if (dev->mode_config.fb_modifiers_not_supported) {
drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
  "GFX9+ requires FB check based on format 
modifier\n");
ret = check_tiling_flags_gfx6(rfb);
@@ -1149,7 +1149,7 @@ int amdgpu_display_framebuffer_init(struct drm_device 
*dev,
return ret;
}
 
-   if (dev->mode_config.allow_fb_modifiers &&
+   if (!dev->mode_config.fb_modifiers_not_supported &&
!(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
ret = convert_tiling_flags_to_modifier(rfb);
if (ret) {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index d1570a462a51..fb61c0814115 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2798,6 +2798,8 @@ static int dce_v10_0_sw_init(void *handle)
adev_to_drm(adev)->mode_config.preferred_depth = 24;
adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 
+   adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
+
adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
 
r = amdgpu_display_modeset_create_props(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 18a7b3bd633b..17942a11366d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2916,6 +2916,8 @@ static int dce_v11_0_sw_init(void *handle)
adev_to_drm(adev)->mode_config.preferred_depth = 24;
adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 
+   adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
+
adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
 
r = amdgpu_display_modeset_create_props(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index c7803dc2b2d5..2ec99ec8e1a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2674,6 +2674,7 @@ static int dce_v6_0_sw_init(void *handle)
adev_to_drm(adev)->mode_config.max_height = 16384;
adev_to_drm(adev)->mode_config.preferred_depth = 24;
adev_to_drm(adev)->mode_config.prefer_shadow = 1;
+   adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
 
r = amdgpu_display_modeset_create_props(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

[RFC PATCH v6 0/3] Add support modifiers for drivers whose planes only support linear layout

[Tomohito Esaki]

Some drivers whose planes only support linear layout fb do not support format
modifiers.
These drivers should support modifiers, however the DRM core should handle this
rather than open-coding in every driver.

In this patch series, these drivers expose format modifiers based on the
following suggestion[1].

On Thu, Nov 18, 2021 at 01:02:11PM +, Daniel Stone wrote:
> I think the best way forward here is:
>   - add a new mode_config.cannot_support_modifiers flag, and enable
> this in radeon (plus any other drivers in the same boat)
>   - change drm_universal_plane_init() to advertise the LINEAR modifier
> when NULL is passed as the modifier list (including installing a
> default .format_mod_supported hook)
>   - remove the mode_config.allow_fb_modifiers hook and always
> advertise modifier support, unless
> mode_config.cannot_support_modifiers is set


[1] 
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20190509054518.10781-1-e...@igel.co.jp/#24602575

v6:
* add Reviewed-by and Acked-by
* add a changelog per-patch

v5: https://www.spinics.net/lists/dri-devel/msg330860.html
* rebase to the latest master branch (5.17-rc1+)
+ "drm/plane: Make format_mod_supported truly optional" patch [2]
  [2] https://patchwork.freedesktop.org/patch/467940/?series=98255=3

* change default_modifiers array from non-static to static
* remove terminator in default_modifiers array
* use ARRAY_SIZE to get the format_modifier_count
* keep a sanity check in plane init func
* modify several kerneldocs

v4: https://www.spinics.net/lists/dri-devel/msg329508.html
* modify documentation for fb_modifiers_not_supported flag in kerneldoc

v3: https://www.spinics.net/lists/dri-devel/msg329102.html
* change the order as follows:
   1. add fb_modifiers_not_supported flag
   2. add default modifiers
   3. remove allow_fb_modifiers flag
* add a conditional disable in amdgpu_dm_plane_init()

v2: https://www.spinics.net/lists/dri-devel/msg328939.html
* rebase to the latest master branch (5.16.0+)
  + "drm/plane: Make format_mod_supported truly optional" patch [2]

v1: https://www.spinics.net/lists/dri-devel/msg327352.html
* The initial patch set

Tomohito Esaki (3):
  drm: introduce fb_modifiers_not_supported flag in mode_config
  drm: add support modifiers for drivers whose planes only support
linear layout
  drm: remove allow_fb_modifiers

 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  6 ++---
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|  2 ++
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  2 ++
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |  1 +
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  2 ++
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +++
 drivers/gpu/drm/drm_framebuffer.c |  6 ++---
 drivers/gpu/drm/drm_ioctl.c   |  2 +-
 drivers/gpu/drm/drm_plane.c   | 23 +++
 drivers/gpu/drm/nouveau/nouveau_display.c |  6 +++--
 drivers/gpu/drm/radeon/radeon_display.c   |  2 ++
 .../gpu/drm/selftests/test-drm_framebuffer.c  |  1 -
 include/drm/drm_mode_config.h | 18 +--
 include/drm/drm_plane.h   |  3 +++
 14 files changed, 45 insertions(+), 32 deletions(-)

-- 
2.25.1

[PATCH v2 1/28] drm/amdgpu: fix that issue that the number of the crtc of the 3250c is not correct

[RyanLin]

v2:
  - remove unnecessary comments and Id

[Why]
External displays take priority over internal display when there are fewer 
display controllers than displays.

[How]
The root cause is because of that number of the crtc is not correct.
The number of the crtc on the 3250c is 3, but on the 3500c is 4.
>From the source code, we can see that number of the crtc has been fixed at 4.
Needs to set the num_crtc to 3 for 3250c platform.

Signed-off-by: RyanLin 

---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 40c91b448f7d..455a2c45e8cd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2738,9 +2738,15 @@ static int dm_early_init(void *handle)
break;
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
-   adev->mode_info.num_crtc = 4;
-   adev->mode_info.num_hpd = 4;
-   adev->mode_info.num_dig = 4;
+   if (adev->rev_id >= 8) {
+   adev->mode_info.num_crtc = 3;
+   adev->mode_info.num_hpd = 3;
+   adev->mode_info.num_dig = 3;
+   } else {
+   adev->mode_info.num_crtc = 4;
+   adev->mode_info.num_hpd = 4;
+   adev->mode_info.num_dig = 4;
+   }
break;
 #endif
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
-- 
2.25.1

RE: [PATCH] drm/amdgpu: add umc_convert_error_address to simplify code

[Zhou1, Tao]

[AMD Official Use Only]

Ping...

> -Original Message-
> From: Zhou1, Tao 
> Sent: Wednesday, January 26, 2022 7:05 PM
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Yang, Stanley ; Chai,
> Thomas ; Clements, John ;
> Lazar, Lijo 
> Cc: Zhou1, Tao 
> Subject: [PATCH] drm/amdgpu: add umc_convert_error_address to simplify
> code
> 
> Make code reusable and more simple.
> 
> Signed-off-by: Tao Zhou 
> ---
>  drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 94 +--
> drivers/gpu/drm/amd/amdgpu/umc_v8_7.c | 82 +--
>  2 files changed, 61 insertions(+), 115 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> index 47452b61b615..4abcdda42ac6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
> @@ -114,21 +114,13 @@ static void
> umc_v6_7_ecc_info_query_ras_error_count(struct amdgpu_device *adev,
>   }
>  }
> 
> -static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device
> *adev,
> -  struct ras_err_data *err_data,
> -  uint32_t ch_inst,
> -  uint32_t umc_inst)
> +static void umc_v6_7_convert_error_address(struct amdgpu_device *adev,
> + struct ras_err_data *err_data, uint32_t
> ch_inst,
> + uint32_t umc_inst, uint64_t err_addr,
> + uint64_t mc_umc_status)
>  {
> - uint64_t mc_umc_status, err_addr, soc_pa, retired_page, column;
>   uint32_t channel_index;
> - uint32_t eccinfo_table_idx;
> - struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
> -
> - eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
> - channel_index =
> - adev->umc.channel_idx_tbl[umc_inst * adev-
> >umc.channel_inst_num + ch_inst];
> -
> - mc_umc_status = ras-
> >umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
> + uint64_t soc_pa, retired_page, column;
> 
>   if (mc_umc_status == 0)
>   return;
> @@ -136,12 +128,13 @@ static void
> umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
>   if (!err_data->err_addr)
>   return;
> 
> + channel_index =
> + adev->umc.channel_idx_tbl[umc_inst * adev-
> >umc.channel_inst_num +
> +ch_inst];
> +
>   /* calculate error address if ue/ce error is detected */
>   if (REG_GET_FIELD(mc_umc_status,
> MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
>   (REG_GET_FIELD(mc_umc_status,
> MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
>   REG_GET_FIELD(mc_umc_status,
> MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
> -
> - err_addr = ras-
> >umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
>   err_addr = REG_GET_FIELD(err_addr,
> MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
> 
>   /* translate umc channel address to soc pa, 3 parts are included
> */ @@ -173,6 +166,23 @@ static void
> umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
>   }
>  }
> 
> +static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device
> *adev,
> +  struct ras_err_data *err_data,
> +  uint32_t ch_inst,
> +  uint32_t umc_inst)
> +{
> + uint64_t mc_umc_status, err_addr;
> + uint32_t eccinfo_table_idx;
> + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
> +
> + eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
> + mc_umc_status = ras-
> >umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
> + err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
> +
> + umc_v6_7_convert_error_address(adev, err_data, ch_inst, umc_inst,
> + err_addr, mc_umc_status);
> +}
> +
>  static void umc_v6_7_ecc_info_query_ras_error_address(struct amdgpu_device
> *adev,
>void *ras_error_status)
>  {
> @@ -348,9 +358,7 @@ static void umc_v6_7_query_error_address(struct
> amdgpu_device *adev,
>uint32_t umc_inst)
>  {
>   uint32_t mc_umc_status_addr;
> - uint32_t channel_index;
> - uint64_t mc_umc_status, mc_umc_addrt0;
> - uint64_t err_addr, soc_pa, retired_page, column;
> + uint64_t mc_umc_status, mc_umc_addrt0, err_addr;
> 
>   mc_umc_status_addr =
>   SOC15_REG_OFFSET(UMC, 0,
> regMCA_UMC_UMC0_MCUMC_STATUST0); @@ -358,54 +366,10 @@ static
> void umc_v6_7_query_error_address(struct amdgpu_device *adev,
>   SOC15_REG_OFFSET(UMC, 0,
> regMCA_UMC_UMC0_MCUMC_ADDRT0);
> 
>   mc_umc_status = RREG64_PCIE((mc_umc_status_addr +
> umc_reg_offset) * 4);
> + err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
> 
> - if (mc_umc_status == 0)
> - return;
> -
> - 

RE: [PATCH] drm/amd/display: Keep eDP Vdd on when eDP stream is already

[Liu, Zhan]

[Public]

After giving it a second thought, I will apply a similar patch on internal 
branch first, then get it promoted to external branch. This patch is abandoned.

Thanks,
Zhan

> -Original Message-
> From: Liu, Zhan
> Sent: 2022/January/27, Thursday 9:51 PM
> To: amd-gfx@lists.freedesktop.org; Liu, Charlene 
> Cc: Pierre-Loup Griffais ; Cornij, Nikola
> ; Kotarac, Pavle ; Gutierrez,
> Agustin 
> Subject: [PATCH] drm/amd/display: Keep eDP Vdd on when eDP stream is already
>
> [Why]
> Even if can_apply_edp_fast_boot is set to 1 at boot, this flag will be 
> cleared to 0
> at S3 resume. However, we still need to keep Vdd on at S3 resume. Turning eDP
> Vdd off at resume will result in black screen at S3 resume.
>
> [How]
> Don't turn eDP Vdd off when there is an existing eDP stream. This can assure 
> eDP
> display come back after S3.
>
> Signed-off-by: Zhan Liu 
> ---
>  .../display/dc/dce110/dce110_hw_sequencer.c   | 23 +--
>  1 file changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> index 72dd41e7a7d6..1aa6f2737534 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> @@ -1796,9 +1796,28 @@ void dce110_enable_accelerated_mode(struct dc *dc,
> struct dc_state *context)
>   break;
>   }
>   }
> - // We are trying to enable eDP, don't power down VDD
> - if (can_apply_edp_fast_boot)
> +
> + /*
> +  * TO-DO: So far the code logic below only addresses single eDP
> case.
> +  * For dual eDP case, there are a few things that need to be
> +  * implemented first:
> +  *
> +  * 1. Change the fastboot logic above, so eDP link[0 or 1]'s
> +  * stream[0 or 1] will all be checked.
> +  *
> +  * 2. Change keep_edp_vdd_on to an array, and maintain
> keep_edp_vdd_on
> +  * for each eDP.
> +  *
> +  * Once above 2 things are completed, we can then change the
> logic below
> +  * correspondingly, so dual eDP case will be fully covered.
> +  */
> +
> + // We are trying to enable eDP, don't power down VDD if there is
> an existing eDP stream
> + if ((edp_stream_num = 1 && edp_streams[0]) ||
> +can_apply_edp_fast_boot) {
>   keep_edp_vdd_on = true;
> + DC_LOG_EVENT_LINK_TRAINING("At least 1 eDP stream is
> already enabled, will keep eDP Vdd on\n");
> + } else
> + DC_LOG_EVENT_LINK_TRAINING("No eDP stream enabled,
> will turn eDP Vdd
> +off\n");
>   }
>
>   // Check seamless boot support
> --
> 2.25.1

[PATCH] drm/amd/display: Keep eDP Vdd on when eDP stream is already

[Liu, Zhan]

[Public]

[Why]
Even if can_apply_edp_fast_boot is set to 1 at boot, this flag will
be cleared to 0 at S3 resume. However, we still need to keep Vdd on
at S3 resume. Turning eDP Vdd off at resume will result in black
screen at S3 resume.

[How]
Don't turn eDP Vdd off when there is an existing eDP stream. This can
assure eDP display come back after S3.

Signed-off-by: Zhan Liu 
---
 .../display/dc/dce110/dce110_hw_sequencer.c   | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 72dd41e7a7d6..1aa6f2737534 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1796,9 +1796,28 @@ void dce110_enable_accelerated_mode(struct dc *dc, 
struct dc_state *context)
break;
}
}
-   // We are trying to enable eDP, don't power down VDD
-   if (can_apply_edp_fast_boot)
+
+   /*
+* TO-DO: So far the code logic below only addresses single eDP 
case.
+* For dual eDP case, there are a few things that need to be
+* implemented first:
+*
+* 1. Change the fastboot logic above, so eDP link[0 or 1]'s
+* stream[0 or 1] will all be checked.
+*
+* 2. Change keep_edp_vdd_on to an array, and maintain 
keep_edp_vdd_on
+* for each eDP.
+*
+* Once above 2 things are completed, we can then change the 
logic below
+* correspondingly, so dual eDP case will be fully covered.
+*/
+
+   // We are trying to enable eDP, don't power down VDD if there 
is an existing eDP stream
+   if ((edp_stream_num = 1 && edp_streams[0]) || 
can_apply_edp_fast_boot) {
keep_edp_vdd_on = true;
+   DC_LOG_EVENT_LINK_TRAINING("At least 1 eDP stream is 
already enabled, will keep eDP Vdd on\n");
+   } else
+   DC_LOG_EVENT_LINK_TRAINING("No eDP stream enabled, will 
turn eDP Vdd off\n");
}

// Check seamless boot support
--
2.25.1

Re: [PATCH] drm/amdgpu: Fix an error message in rmmod

[Yin, Tianci (Rico)]

[AMD Official Use Only]

The error message is from HIQ dequeue procedure,  not from HCQ, so no doorbell 
writing.

Jan 25 16:10:58 lnx-ci-node kernel: [18161.477067] Call Trace:
Jan 25 16:10:58 lnx-ci-node kernel: [18161.477072]  dump_stack+0x7d/0x9c
Jan 25 16:10:58 lnx-ci-node kernel: [18161.477651]  
hqd_destroy_v10_3+0x58/0x254 [amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.48]  destroy_mqd+0x1e/0x30 
[amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.477884]  
kernel_queue_uninit+0xcf/0x100 [amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.477985]  pm_uninit+0x1a/0x30 
[amdgpu] #kernel_queue_uninit(pm->priv_queue, hanging); this priv_queue == HIQ
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478127]  stop_cpsch+0x98/0x100 
[amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478242]  
kgd2kfd_suspend.part.0+0x32/0x50 [amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478338]  kgd2kfd_suspend+0x1b/0x20 
[amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478433]  
amdgpu_amdkfd_suspend+0x1e/0x30 [amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478529]  
amdgpu_device_fini_hw+0x182/0x335 [amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478655]  
amdgpu_driver_unload_kms+0x5c/0x80 [amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478732]  amdgpu_pci_remove+0x27/0x40 
[amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478806]  pci_device_remove+0x3e/0xb0
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478809]  
device_release_driver_internal+0x103/0x1d0
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478813]  driver_detach+0x4c/0x90
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478814]  bus_remove_driver+0x5c/0xd0
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478815]  driver_unregister+0x31/0x50
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478817]  
pci_unregister_driver+0x40/0x90
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478818]  amdgpu_exit+0x15/0x2d1 
[amdgpu]
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478942]  
__x64_sys_delete_module+0x147/0x260
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478944]  ? 
exit_to_user_mode_prepare+0x41/0x1d0
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478946]  ? ksys_write+0x67/0xe0
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478948]  do_syscall_64+0x40/0xb0
Jan 25 16:10:58 lnx-ci-node kernel: [18161.478951]  
entry_SYSCALL_64_after_hwframe+0x44/0xae

Regards,
Rico

From: Kuehling, Felix 
Sent: Thursday, January 27, 2022 23:28
To: Yin, Tianci (Rico) ; Wang, Yang(Kevin) 
; amd-gfx@lists.freedesktop.org 

Cc: Grodzovsky, Andrey ; Chen, Guchun 

Subject: Re: [PATCH] drm/amdgpu: Fix an error message in rmmod

The hang you're seeing is the result of a command submission of an
UNMAP_QUEUES and QUERY_STATUS command to the HIQ. This is done using a
doorbell. KFD writes commands to the HIQ and rings a doorbell to wake up
the HWS (see kq_submit_packet in kfd_kernel_queue.c). Why does this
doorbell not trigger gfxoff exit during rmmod?


Regards,
   Felix



Am 2022-01-26 um 22:38 schrieb Yin, Tianci (Rico):
>
> [AMD Official Use Only]
>
>
> The rmmod ops has prerequisite multi-user target and blacklist amdgpu,
> which is IGT requirement so that IGT can make itself DRM master to
> test KMS.
> igt-gpu-tools/build/tests/amdgpu/amd_module_load --run-subtest reload
>
> From my understanding, the KFD process belongs to the regular way of
> gfxoff exit, which doorbell writing triggers gfxoff exit. For example,
> KFD maps HCQ thru cmd on HIQ or KIQ ring, or UMD commits jobs on HCQ,
> these both trigger doorbell writing(pls refer to
> gfx_v10_0_ring_set_wptr_compute()).
>
> As to the IGT reload test, the dequeue request is not thru a cmd on a
> ring, it directly writes CP registers, so GFX core remains in gfxoff.
>
> Thanks,
> Rico
>
> 
> *From:* Kuehling, Felix 
> *Sent:* Wednesday, January 26, 2022 23:08
> *To:* Yin, Tianci (Rico) ; Wang, Yang(Kevin)
> ; amd-gfx@lists.freedesktop.org
> 
> *Cc:* Grodzovsky, Andrey ; Chen, Guchun
> 
> *Subject:* Re: [PATCH] drm/amdgpu: Fix an error message in rmmod
> My question is, why is this problem only seen during module unload? Why
> aren't we seeing HWS hangs due to GFX_OFF all the time in normal
> operations? For example when the GPU is idle and a new KFD process is
> started, creating a new runlist. Are we just getting lucky because the
> process first has to allocate some memory, which maybe makes some HW
> access (flushing TLBs etc.) that wakes up the GPU?
>
>
> Regards,
>Felix
>
>
>
> Am 2022-01-26 um 01:43 schrieb Yin, Tianci (Rico):
> >
> > [AMD Official Use Only]
> >
> >
> > Thanks Kevin and Felix!
> >
> > In gfxoff state, the dequeue request(by cp register writing) can't
> > make gfxoff exit, actually the cp is powered off and the cp register
> > writing is invalid, doorbell registers writing(regluar way) or
> > directly request smu to disable gfx powergate(by invoking
> > amdgpu_gfx_off_ctrl) can trigger gfxoff exit.
> >
> > I have also 

Re: [PATCH v2 6/8] drm/amdkfd: Add user queue eviction restore SMI event

[Felix Kuehling]

Am 2022-01-20 um 18:13 schrieb Philip Yang:

Output user queue eviction and restore event. User queue eviction may be
triggered by migration, MMU notifier, TTM eviction or device suspend.

User queue restore may be rescheduled if eviction happens again while
restore.

Signed-off-by: Philip Yang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|  7 +++-
  .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 11 --
  drivers/gpu/drm/amd/amdkfd/kfd_device.c   |  4 +-
  drivers/gpu/drm/amd/amdkfd/kfd_priv.h |  2 +-
  drivers/gpu/drm/amd/amdkfd/kfd_process.c  | 37 +--
  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c   | 34 +
  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h   |  4 ++
  drivers/gpu/drm/amd/amdkfd/kfd_svm.c  | 16 ++--
  8 files changed, 101 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index ac841ae8f5cc..bd3301e2c682 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -309,6 +309,7 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device 
*adev,
   */
  void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo);
  void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
+void kfd_process_smi_event_restore_rescheduled(struct mm_struct *mm);
  #else
  static inline
  void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
@@ -325,9 +326,13 @@ static inline
  void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
  {
  }
+
+static inline void kfd_process_smi_event_restore_rescheduled(struct mm_struct 
*mm)
+{
+}
  #endif
  /* KGD2KFD callbacks */
-int kgd2kfd_quiesce_mm(struct mm_struct *mm);
+int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);
  int kgd2kfd_resume_mm(struct mm_struct *mm);
  int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
struct dma_fence *fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 5df387c4d7fb..c44e8dc0d869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -2066,7 +2066,7 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
evicted_bos = atomic_inc_return(_info->evicted_bos);
if (evicted_bos == 1) {
/* First eviction, stop the queues */
-   r = kgd2kfd_quiesce_mm(mm);
+   r = kgd2kfd_quiesce_mm(mm, USERPTR_EVICTION);
if (r)
pr_err("Failed to quiesce KFD\n");
schedule_delayed_work(_info->restore_userptr_work,
@@ -2340,13 +2340,16 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct 
work_struct *work)
  
  unlock_out:

mutex_unlock(_info->lock);
-   mmput(mm);
-   put_task_struct(usertask);
  
  	/* If validation failed, reschedule another attempt */

-   if (evicted_bos)
+   if (evicted_bos) {
schedule_delayed_work(_info->restore_userptr_work,
msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
+
+   kfd_process_smi_event_restore_rescheduled(mm);
+   }
+   mmput(mm);
+   put_task_struct(usertask);
  }
  
  /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 5a47f437b455..ffaa80447d9c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -783,7 +783,7 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void 
*ih_ring_entry)
spin_unlock_irqrestore(>interrupt_lock, flags);
  }
  
-int kgd2kfd_quiesce_mm(struct mm_struct *mm)

+int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
  {
struct kfd_process *p;
int r;
@@ -797,7 +797,7 @@ int kgd2kfd_quiesce_mm(struct mm_struct *mm)
return -ESRCH;
  
  	WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);

-   r = kfd_process_evict_queues(p);
+   r = kfd_process_evict_queues(p, trigger);
  
  	kfd_unref_process(p);

return r;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index ea68f3b3a4e9..39519084df78 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -906,7 +906,7 @@ static inline struct kfd_process_device 
*kfd_process_device_from_gpuidx(
  }
  
  void kfd_unref_process(struct kfd_process *p);

-int kfd_process_evict_queues(struct kfd_process *p);
+int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger);
  int kfd_process_restore_queues(struct kfd_process *p);
  void kfd_suspend_all_processes(void);
  int kfd_resume_all_processes(void);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 

Re: [PATCH v2 5/8] drm/amdkfd: add migration SMI event

[Felix Kuehling]

Am 2022-01-20 um 18:13 schrieb Philip Yang:

After migration is finished, output timestamp when migration starts,
duration of migration, svm range address and size, GPU id of
migration source and destination and svm range attributes,

Migration trigger could be prefetch, CPU or GPU page fault and TTM
eviction.

Signed-off-by: Philip Yang 
---
  drivers/gpu/drm/amd/amdkfd/kfd_migrate.c| 67 ++---
  drivers/gpu/drm/amd/amdkfd/kfd_migrate.h|  5 +-
  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 29 +
  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h |  5 ++
  drivers/gpu/drm/amd/amdkfd/kfd_svm.c| 16 +++--
  5 files changed, 91 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 88db82b3d443..06fb888f87aa 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -32,6 +32,7 @@
  #include "kfd_priv.h"
  #include "kfd_svm.h"
  #include "kfd_migrate.h"
+#include "kfd_smi_events.h"
  
  #ifdef dev_fmt

  #undef dev_fmt
@@ -402,10 +403,11 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, 
struct svm_range *prange,
  static long
  svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
struct vm_area_struct *vma, uint64_t start,
-   uint64_t end)
+   uint64_t end, uint32_t trigger)
  {
uint64_t npages = (end - start) >> PAGE_SHIFT;
-   struct kfd_process_device *pdd;
+   struct kfd_process_device *pdd = NULL;
+   uint64_t timestamp = ktime_get_boottime_ns();
struct dma_fence *mfence = NULL;
struct migrate_vma migrate;
unsigned long cpages = 0;
@@ -431,6 +433,10 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct 
svm_range *prange,
migrate.dst = migrate.src + npages;
scratch = (dma_addr_t *)(migrate.dst + npages);
  
+	pdd = svm_range_get_pdd_by_adev(prange, adev);

+   if (!pdd)
+   goto out_free;
+
r = migrate_vma_setup();
if (r) {
dev_err(adev->dev, "vma setup fail %d range [0x%lx 0x%lx]\n", r,
@@ -459,6 +465,11 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct 
svm_range *prange,
svm_migrate_copy_done(adev, mfence);
migrate_vma_finalize();
  
+	kfd_smi_event_migration(adev->kfd.dev, pdd->process->pasid,


The pasid is only used by kfd_smi_event_migration to determine the PID. 
But you already know the PID here:


container_of(prange->svms, struct kfd_process, svms)->lead_thread->pid;



+   start >> PAGE_SHIFT, end >> PAGE_SHIFT,
+   0, adev->kfd.dev->id, prange->prefetch_loc,
+   prange->preferred_loc, trigger, timestamp);
+
svm_range_dma_unmap(adev->dev, scratch, 0, npages);
svm_range_free_dma_mappings(prange);
  
@@ -466,10 +477,7 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct svm_range *prange,

kvfree(buf);
  out:
if (!r && cpages) {
-   pdd = svm_range_get_pdd_by_adev(prange, adev);
-   if (pdd)
-   WRITE_ONCE(pdd->page_in, pdd->page_in + cpages);
-
+   WRITE_ONCE(pdd->page_in, pdd->page_in + cpages);
return cpages;
}
return r;
@@ -480,6 +488,7 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct 
svm_range *prange,
   * @prange: range structure
   * @best_loc: the device to migrate to
   * @mm: the process mm structure
+ * @trigger: reason of migration
   *
   * Context: Process context, caller hold mmap read lock, svms lock, prange 
lock
   *
@@ -488,7 +497,7 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, struct 
svm_range *prange,
   */
  static int
  svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,
-   struct mm_struct *mm)
+   struct mm_struct *mm, uint32_t trigger)
  {
unsigned long addr, start, end;
struct vm_area_struct *vma;
@@ -525,7 +534,7 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t 
best_loc,
break;
  
  		next = min(vma->vm_end, end);

-   r = svm_migrate_vma_to_vram(adev, prange, vma, addr, next);
+   r = svm_migrate_vma_to_vram(adev, prange, vma, addr, next, 
trigger);
if (r < 0) {
pr_debug("failed %ld to migrate\n", r);
break;
@@ -641,12 +650,14 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, 
struct svm_range *prange,
  
  static long

  svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
-  struct vm_area_struct *vma, uint64_t start, uint64_t end)
+  struct vm_area_struct *vma, uint64_t start, uint64_t end,
+  uint32_t trigger)
  {
uint64_t npages = 

Re: [PATCH v4 00/10] Add MEMORY_DEVICE_COHERENT for coherent device memory mapping

[Sierra Guiza, Alejandro (Alex)]

Andrew,
We're somehow new on this procedure. Are you referring to rebase this 
patch series to
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 
<5.17-rc1 tag>?


Regards,
Alex Sierra

Alex Deucher,
Just a quick heads up. This patch series contains changes to the amdgpu 
driver which we're

planning to merge through Andrew's tree, If that's ok with you.

Regards,
Alex Sierra

On 1/27/2022 4:32 PM, Andrew Morton wrote:

On Wed, 26 Jan 2022 21:09:39 -0600 Alex Sierra  wrote:


This patch series introduces MEMORY_DEVICE_COHERENT, a type of memory
owned by a device that can be mapped into CPU page tables like
MEMORY_DEVICE_GENERIC and can also be migrated like
MEMORY_DEVICE_PRIVATE.

Some more reviewer input appears to be desirable here.

I was going to tentatively add it to -mm and -next, but problems.
5.17-rc1's mm/migrate.c:migrate_vma_check_page() is rather different
from the tree you patched.  Please redo, refresh and resend?

Re: [PATCH v2 4/8] drm/amdkfd: Add GPU recoverable fault SMI event

[Felix Kuehling]

Am 2022-01-20 um 18:13 schrieb Philip Yang:

Output timestamp when GPU recoverable fault starts, ends and duration to
recover the fault, if migration happened or only GPU page table is
updated, fault address, read or write fault.

Signed-off-by: Philip Yang 
---
  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 48 +
  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h |  7 ++-
  drivers/gpu/drm/amd/amdkfd/kfd_svm.c| 17 ++--
  3 files changed, 67 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
index 68c93701c5f7..080eba0d3be0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
@@ -266,6 +266,54 @@ void kfd_smi_event_update_vmfault(struct kfd_dev *dev, 
uint16_t pasid)
add_event_to_kfifo(0, dev, KFD_SMI_EVENT_VMFAULT, fifo_in, len);
  }
  
+static bool kfd_smi_event_duration(struct kfd_dev *dev, uint64_t ts,

+  uint64_t *duration)
+{
+   if (list_empty(>smi_clients))
+   return false;


I'm not sure what this check has to do with the duration calculation. I 
think this should be checked in the caller.


But I'd actually prefer not to include the duration in the message 
because it's redundant. If you have both the start and end event in the 
log, the duration can be easily calculated from the time stamps by 
whatever tool is used to analyze or visualize the log. We do need a way 
to match the start event to the end event. I think the PID and address 
should be good enough for that.




+
+   *duration = ktime_get_boottime_ns() - ts;
+   return true;
+}
+
+void kfd_smi_event_page_fault_start(struct kfd_dev *dev, pid_t pid,
+   unsigned long address, bool write_fault,
+   uint64_t ts)
+{
+   char fifo_in[64];
+   int len;
+
+   if (list_empty(>smi_clients))
+   return;
+
+   len = snprintf(fifo_in, sizeof(fifo_in), "%x %lld -%d @%lx(%x) %c\n",
+  KFD_SMI_EVENT_PAGE_FAULT_START, ts, pid, address,
+  dev->id, write_fault ? 'W' : 'R');
+
+   add_event_to_kfifo(pid, dev, KFD_SMI_EVENT_PAGE_FAULT_START, fifo_in,
+  len);
+}
+
+void kfd_smi_event_page_fault_end(struct kfd_dev *dev, pid_t pid,
+ unsigned long address, bool migration,
+ uint64_t ts)
+{
+   char fifo_in[64];
+   uint64_t duration;
+   int len;
+
+   if (!kfd_smi_event_duration(dev, ts, ))
+   return;
+
+   len = snprintf(fifo_in, sizeof(fifo_in),
+  "%x %lld(%lld) -%d @%lx(%x) %c\n",
+  KFD_SMI_EVENT_PAGE_FAULT_END, ktime_get_boottime_ns(),
+  duration, pid, address, dev->id, migration ? 'M' : 'm');
+
+   add_event_to_kfifo(pid, dev, KFD_SMI_EVENT_PAGE_FAULT_END, fifo_in,
+  len);
+}
+
  int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd)
  {
struct kfd_smi_client *client;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
index bffd0c32b060..7f70db914d2c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
@@ -28,5 +28,10 @@ void kfd_smi_event_update_vmfault(struct kfd_dev *dev, 
uint16_t pasid);
  void kfd_smi_event_update_thermal_throttling(struct kfd_dev *dev,
 uint64_t throttle_bitmask);
  void kfd_smi_event_update_gpu_reset(struct kfd_dev *dev, bool post_reset);
-
+void kfd_smi_event_page_fault_start(struct kfd_dev *dev, pid_t pid,
+   unsigned long address, bool write_fault,
+   uint64_t ts);
+void kfd_smi_event_page_fault_end(struct kfd_dev *dev, pid_t pid,
+ unsigned long address, bool migration,
+ uint64_t ts);
  #endif
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 2d2cae05dbea..08b21f9759ea 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -32,6 +32,7 @@
  #include "kfd_priv.h"
  #include "kfd_svm.h"
  #include "kfd_migrate.h"
+#include "kfd_smi_events.h"
  
  #ifdef dev_fmt

  #undef dev_fmt
@@ -1596,7 +1597,7 @@ static int svm_range_validate_and_map(struct mm_struct 
*mm,
svm_range_unreserve_bos();
  
  	if (!r)

-   prange->validate_timestamp = ktime_to_us(ktime_get());
+   prange->validate_timestamp = ktime_get_boottime_ns();
  
  	return r;

  }
@@ -2665,11 +2666,12 @@ svm_range_restore_pages(struct amdgpu_device *adev, 
unsigned int pasid,
struct svm_range_list *svms;
struct svm_range *prange;
struct kfd_process *p;
-   uint64_t 

Re: [PATCH v2 3/8] drm/amdkfd: Enable per process SMI event

[Felix Kuehling]

Am 2022-01-20 um 18:13 schrieb Philip Yang:

Process receive event from same process by default. Add a flag to be
able to receive event from all processes, this requires super user
permission.

Event with pid 0 send to all processes, to keep the default behavior of
existing SMI events.

Signed-off-by: Philip Yang 


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 29 -
  1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
index 18ed1b72f0f7..68c93701c5f7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
@@ -37,6 +37,8 @@ struct kfd_smi_client {
uint64_t events;
struct kfd_dev *dev;
spinlock_t lock;
+   pid_t pid;
+   bool suser;
  };
  
  #define MAX_KFIFO_SIZE	1024

@@ -150,16 +152,27 @@ static int kfd_smi_ev_release(struct inode *inode, struct 
file *filep)
return 0;
  }
  
-static void add_event_to_kfifo(struct kfd_dev *dev, unsigned int smi_event,

- char *event_msg, int len)
+static bool kfd_smi_ev_enabled(pid_t pid, struct kfd_smi_client *client,
+  unsigned int event)
+{
+   uint64_t all = KFD_SMI_EVENT_MASK_FROM_INDEX(KFD_SMI_EVENT_ALL_PROCESS);
+   uint64_t events = READ_ONCE(client->events);
+
+   if (pid && client->pid != pid && !(client->suser && (events & all)))
+   return false;
+
+   return events & KFD_SMI_EVENT_MASK_FROM_INDEX(event);
+}
+
+static void add_event_to_kfifo(pid_t pid, struct kfd_dev *dev,
+  unsigned int smi_event, char *event_msg, int len)
  {
struct kfd_smi_client *client;
  
  	rcu_read_lock();
  
  	list_for_each_entry_rcu(client, >smi_clients, list) {

-   if (!(READ_ONCE(client->events) &
-   KFD_SMI_EVENT_MASK_FROM_INDEX(smi_event)))
+   if (!kfd_smi_ev_enabled(pid, client, smi_event))
continue;
spin_lock(>lock);
if (kfifo_avail(>fifo) >= len) {
@@ -202,7 +215,7 @@ void kfd_smi_event_update_gpu_reset(struct kfd_dev *dev, 
bool post_reset)
len = snprintf(fifo_in, sizeof(fifo_in), "%x %x\n", event,
dev->reset_seq_num);
  
-	add_event_to_kfifo(dev, event, fifo_in, len);

+   add_event_to_kfifo(0, dev, event, fifo_in, len);
  }
  
  void kfd_smi_event_update_thermal_throttling(struct kfd_dev *dev,

@@ -225,7 +238,7 @@ void kfd_smi_event_update_thermal_throttling(struct kfd_dev 
*dev,
   KFD_SMI_EVENT_THERMAL_THROTTLE, throttle_bitmask,
   amdgpu_dpm_get_thermal_throttling_counter(dev->adev));
  
-	add_event_to_kfifo(dev, KFD_SMI_EVENT_THERMAL_THROTTLE,	fifo_in, len);

+   add_event_to_kfifo(0, dev, KFD_SMI_EVENT_THERMAL_THROTTLE, fifo_in, 
len);
  }
  
  void kfd_smi_event_update_vmfault(struct kfd_dev *dev, uint16_t pasid)

@@ -250,7 +263,7 @@ void kfd_smi_event_update_vmfault(struct kfd_dev *dev, 
uint16_t pasid)
len = snprintf(fifo_in, sizeof(fifo_in), "%x %x:%s\n", 
KFD_SMI_EVENT_VMFAULT,
task_info.pid, task_info.task_name);
  
-	add_event_to_kfifo(dev, KFD_SMI_EVENT_VMFAULT, fifo_in, len);

+   add_event_to_kfifo(0, dev, KFD_SMI_EVENT_VMFAULT, fifo_in, len);
  }
  
  int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd)

@@ -282,6 +295,8 @@ int kfd_smi_event_open(struct kfd_dev *dev, uint32_t *fd)
spin_lock_init(>lock);
client->events = 0;
client->dev = dev;
+   client->pid = current->pid;
+   client->suser = capable(CAP_SYS_ADMIN);
  
  	spin_lock(>smi_lock);

list_add_rcu(>list, >smi_clients);

Re: [PATCH v4 00/10] Add MEMORY_DEVICE_COHERENT for coherent device memory mapping

[Andrew Morton]

On Wed, 26 Jan 2022 21:09:39 -0600 Alex Sierra  wrote:

> This patch series introduces MEMORY_DEVICE_COHERENT, a type of memory
> owned by a device that can be mapped into CPU page tables like
> MEMORY_DEVICE_GENERIC and can also be migrated like
> MEMORY_DEVICE_PRIVATE.

Some more reviewer input appears to be desirable here.

I was going to tentatively add it to -mm and -next, but problems. 
5.17-rc1's mm/migrate.c:migrate_vma_check_page() is rather different
from the tree you patched.  Please redo, refresh and resend?

Re: [PATCH] drm/amdgpu: Wrong order for config and counter_id parameters

[Alex Deucher]

Applied.  Thanks!

Alex

On Wed, Jan 26, 2022 at 4:48 AM  wrote:
>
> From: huangqu 
>
> Wrong order for config and counter_id parameters was passed, when calling 
> df_v3_6_pmc_set_deferred and df_v3_6_pmc_is_deferred functions.
>
> Signed-off-by: huangqu 
> ---
>  drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c 
> b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> index 43c5e3ec9..f4dfca013 100644
> --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> @@ -458,7 +458,7 @@ static int df_v3_6_pmc_add_cntr(struct amdgpu_device 
> *adev,
>
>  #define DEFERRED_ARM_MASK  (1 << 31)
>  static int df_v3_6_pmc_set_deferred(struct amdgpu_device *adev,
> -   int counter_idx, uint64_t config,
> +   uint64_t config, int counter_idx,
> bool is_deferred)
>  {
>
> @@ -476,8 +476,8 @@ static int df_v3_6_pmc_set_deferred(struct amdgpu_device 
> *adev,
>  }
>
>  static bool df_v3_6_pmc_is_deferred(struct amdgpu_device *adev,
> -   int counter_idx,
> -   uint64_t config)
> +   uint64_t config,
> +   int counter_idx)
>  {
> return  (df_v3_6_pmc_has_counter(adev, config, counter_idx) &&
> (adev->df_perfmon_config_assign_mask[counter_idx]
> --
> 2.31.1
>

Re: [PATCH] drm/amd/amdgpu: fix spelling mistake "disbale" -> "disable"

[Alex Deucher]

Applied.  Thanks!

Alex

On Thu, Jan 27, 2022 at 3:45 AM tangmeng  wrote:
>
> There is a spelling mistake. Fix it.
>
> Signed-off-by: tangmeng 
> ---
>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 
> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index aef9d059ae52..a642c04cf17d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -544,7 +544,7 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device 
> *adev,
>  {
> int r;
>
> -   /* trigger gpu-reset by hypervisor only if TDR disbaled */
> +   /* trigger gpu-reset by hypervisor only if TDR disabled */
> if (!amdgpu_gpu_recovery) {
> /* see what event we get */
> r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
> --
> 2.20.1
>
>
>

RE: [PATCH v6 4/4] drm/amd: Only run s3 or s0ix if system is configured properly

[Limonciello, Mario]

[Public]

Thanks for the review.  I'm only going to merge 2-4 initially though.
The reporter on 1 has some questionable results, and I have a follow up patch 
for them to try.
If that combined with 1 looks good I'll bring that patch for review.

From: Deucher, Alexander 
Sent: Thursday, January 27, 2022 08:50
To: Limonciello, Mario ; 
amd-gfx@lists.freedesktop.org
Cc: Liang, Prike 
Subject: Re: [PATCH v6 4/4] drm/amd: Only run s3 or s0ix if system is 
configured properly


[Public]

Series is:
Reviewed-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Mario Limonciello 
mailto:mario.limoncie...@amd.com>>
Sent: Wednesday, January 26, 2022 5:58 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Liang, Prike mailto:prike.li...@amd.com>>; 
Limonciello, Mario mailto:mario.limoncie...@amd.com>>
Subject: [PATCH v6 4/4] drm/amd: Only run s3 or s0ix if system is configured 
properly

This will cause misconfigured systems to not run the GPU suspend
routines.

* In APUs that are properly configured system will go into s2idle.
* In APUs that are intended to be S3 but user selects
  s2idle the GPU will stay fully powered for the suspend.
* In APUs that are intended to be s2idle and system misconfigured
  the GPU will stay fully powered for the suspend.
* In systems that are intended to be s2idle, but AMD dGPU is also
  present, the dGPU will go through S3

Signed-off-by: Mario Limonciello 
mailto:mario.limoncie...@amd.com>>
---
v5->v6:
 * Move code into prepare vfunc and use DPM_FLAG_SMART_SUSPEND to skip
   suspend code in incorrectly configured systems.
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 922accdd4246..3e581f35f19d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2289,6 +2289,7 @@ static void amdgpu_drv_delayed_reset_work_handler(struct 
work_struct *work)
 static int amdgpu_pmops_prepare(struct device *dev)
 {
 struct drm_device *drm_dev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = drm_to_adev(drm_dev);

 /* Return a positive number here so
  * DPM_FLAG_SMART_SUSPEND works properly
@@ -2296,6 +2297,13 @@ static int amdgpu_pmops_prepare(struct device *dev)
 if (amdgpu_device_supports_boco(drm_dev))
 return pm_runtime_suspended(dev);

+   /* if we will not support s3 or s2i for the device
+*  then skip suspend
+*/
+   if (!amdgpu_acpi_is_s0ix_active(adev) &&
+   !amdgpu_acpi_is_s3_active(adev))
+   return 1;
+
 return 0;
 }

--
2.25.1

Re: [PATCH 1/2] drm/amd: Expose the FRU SMU I2C bus

[Alex Deucher]

On Thu, Jan 27, 2022 at 1:54 PM Luben Tuikov  wrote:
>
> Expose the FRU SMU I2C bus.

Maybe rework the commit message a bit.  Something like:
Expose both SMU i2c buses.  Some boards use the same bus for both the
RAS and FRU EEPROMs others use different buses.  This enables the
additional i2c bus and sets the right buses to use for RAS and FRU.

With that fixed, the series is:
Reviewed-by: Alex Deucher 

>
> Cc: Roy Sun 
> Co-developed-by: Alex Deucher 
> Signed-off-by: Luben Tuikov 
> ---
>  .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c|  6 +-
>  .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 14 ++--
>  drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c| 80 ---
>  drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h|  6 +-
>  drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   | 14 +++-
>  .../amd/pm/powerplay/smumgr/vega20_smumgr.c   |  4 +-
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  4 +-
>  drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  4 +-
>  .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 69 +++-
>  .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 68 +++-
>  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 71 +++-
>  .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 44 +++---
>  drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   |  4 +-
>  13 files changed, 273 insertions(+), 115 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> index 60e7e637eaa33d..40180648be3811 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> @@ -75,7 +75,7 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device 
> *adev, uint32_t addrptr,
>  {
> int ret, size;
>
> -   ret = amdgpu_eeprom_read(>pm.smu_i2c, addrptr, buff, 1);
> +   ret = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, addrptr, buff, 
> 1);
> if (ret < 1) {
> DRM_WARN("FRU: Failed to get size field");
> return ret;
> @@ -86,7 +86,7 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device 
> *adev, uint32_t addrptr,
>  */
> size = buff[0] - I2C_PRODUCT_INFO_OFFSET;
>
> -   ret = amdgpu_eeprom_read(>pm.smu_i2c, addrptr + 1, buff, size);
> +   ret = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, addrptr + 1, 
> buff, size);
> if (ret < 1) {
> DRM_WARN("FRU: Failed to get data field");
> return ret;
> @@ -109,7 +109,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device 
> *adev)
> offset = 0;
>
> /* If algo exists, it means that the i2c_adapter's initialized */
> -   if (!adev->pm.smu_i2c.algo) {
> +   if (!adev->pm.fru_eeprom_i2c_bus || 
> !adev->pm.fru_eeprom_i2c_bus->algo) {
> DRM_WARN("Cannot access FRU, EEPROM accessor not 
> initialized");
> return -ENODEV;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index 05117eda105b55..c09d047272b207 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -194,7 +194,7 @@ static int __write_table_header(struct 
> amdgpu_ras_eeprom_control *control)
>
> /* i2c may be unstable in gpu reset */
> down_read(>reset_sem);
> -   res = amdgpu_eeprom_write(>pm.smu_i2c,
> +   res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
>   control->i2c_address +
>   control->ras_header_offset,
>   buf, RAS_TABLE_HEADER_SIZE);
> @@ -389,7 +389,7 @@ static int __amdgpu_ras_eeprom_write(struct 
> amdgpu_ras_eeprom_control *control,
> /* i2c may be unstable in gpu reset */
> down_read(>reset_sem);
> buf_size = num * RAS_TABLE_RECORD_SIZE;
> -   res = amdgpu_eeprom_write(>pm.smu_i2c,
> +   res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
>   control->i2c_address +
>   RAS_INDEX_TO_OFFSET(control, fri),
>   buf, buf_size);
> @@ -548,7 +548,7 @@ amdgpu_ras_eeprom_update_header(struct 
> amdgpu_ras_eeprom_control *control)
> }
>
> down_read(>reset_sem);
> -   res = amdgpu_eeprom_read(>pm.smu_i2c,
> +   res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
>  control->i2c_address +
>  control->ras_record_offset,
>  buf, buf_size);
> @@ -644,7 +644,7 @@ static int __amdgpu_ras_eeprom_read(struct 
> amdgpu_ras_eeprom_control *control,
> /* i2c may be unstable in gpu reset */
> down_read(>reset_sem);
> buf_size = num * RAS_TABLE_RECORD_SIZE;
> -   res = amdgpu_eeprom_read(>pm.smu_i2c,
> +   res = 

[PATCH 2/2] drm/amd: Enable FRU EEPROM for Sienna Cichlid

[Luben Tuikov]

Enable the FRU EEPROM I2C bus for Sienna Cichlid
server boards, for which it is enabled by checking
the VBIOS version.

Cc: Roy Sun 
Cc: Alex Deucher 
Signed-off-by: Luben Tuikov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 40180648be3811..ce5d5ee336a990 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -46,7 +46,7 @@ static bool is_fru_eeprom_supported(struct amdgpu_device 
*adev)
if (amdgpu_sriov_vf(adev))
return false;
 
-   /* VBIOS is of the format ###-DXXXYY-##. For SKU identification,
+   /* VBIOS is of the format ###-DXXX-##. For SKU identification,
 * we can use just the "DXXX" portion. If there were more models, we
 * could convert the 3 characters to a hex integer and use a switch
 * for ease/speed/readability. For now, 2 string comparisons are
@@ -65,6 +65,12 @@ static bool is_fru_eeprom_supported(struct amdgpu_device 
*adev)
case CHIP_ALDEBARAN:
/* All Aldebaran SKUs have the FRU */
return true;
+   case CHIP_SIENNA_CICHLID:
+   if (strnstr(atom_ctx->vbios_version, "D603",
+   sizeof(atom_ctx->vbios_version)))
+   return true;
+   else
+   return false;
default:
return false;
}
-- 
2.34.0

[PATCH 1/2] drm/amd: Expose the FRU SMU I2C bus

[Luben Tuikov]

Expose the FRU SMU I2C bus.

Cc: Roy Sun 
Co-developed-by: Alex Deucher 
Signed-off-by: Luben Tuikov 
---
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c|  6 +-
 .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 14 ++--
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c| 80 ---
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h|  6 +-
 drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   | 14 +++-
 .../amd/pm/powerplay/smumgr/vega20_smumgr.c   |  4 +-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  4 +-
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  4 +-
 .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 69 +++-
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 68 +++-
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 71 +++-
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 44 +++---
 drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   |  4 +-
 13 files changed, 273 insertions(+), 115 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 60e7e637eaa33d..40180648be3811 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -75,7 +75,7 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, 
uint32_t addrptr,
 {
int ret, size;
 
-   ret = amdgpu_eeprom_read(>pm.smu_i2c, addrptr, buff, 1);
+   ret = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, addrptr, buff, 1);
if (ret < 1) {
DRM_WARN("FRU: Failed to get size field");
return ret;
@@ -86,7 +86,7 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, 
uint32_t addrptr,
 */
size = buff[0] - I2C_PRODUCT_INFO_OFFSET;
 
-   ret = amdgpu_eeprom_read(>pm.smu_i2c, addrptr + 1, buff, size);
+   ret = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, addrptr + 1, 
buff, size);
if (ret < 1) {
DRM_WARN("FRU: Failed to get data field");
return ret;
@@ -109,7 +109,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
offset = 0;
 
/* If algo exists, it means that the i2c_adapter's initialized */
-   if (!adev->pm.smu_i2c.algo) {
+   if (!adev->pm.fru_eeprom_i2c_bus || !adev->pm.fru_eeprom_i2c_bus->algo) 
{
DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
return -ENODEV;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 05117eda105b55..c09d047272b207 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -194,7 +194,7 @@ static int __write_table_header(struct 
amdgpu_ras_eeprom_control *control)
 
/* i2c may be unstable in gpu reset */
down_read(>reset_sem);
-   res = amdgpu_eeprom_write(>pm.smu_i2c,
+   res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
  control->i2c_address +
  control->ras_header_offset,
  buf, RAS_TABLE_HEADER_SIZE);
@@ -389,7 +389,7 @@ static int __amdgpu_ras_eeprom_write(struct 
amdgpu_ras_eeprom_control *control,
/* i2c may be unstable in gpu reset */
down_read(>reset_sem);
buf_size = num * RAS_TABLE_RECORD_SIZE;
-   res = amdgpu_eeprom_write(>pm.smu_i2c,
+   res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
  control->i2c_address +
  RAS_INDEX_TO_OFFSET(control, fri),
  buf, buf_size);
@@ -548,7 +548,7 @@ amdgpu_ras_eeprom_update_header(struct 
amdgpu_ras_eeprom_control *control)
}
 
down_read(>reset_sem);
-   res = amdgpu_eeprom_read(>pm.smu_i2c,
+   res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
 control->i2c_address +
 control->ras_record_offset,
 buf, buf_size);
@@ -644,7 +644,7 @@ static int __amdgpu_ras_eeprom_read(struct 
amdgpu_ras_eeprom_control *control,
/* i2c may be unstable in gpu reset */
down_read(>reset_sem);
buf_size = num * RAS_TABLE_RECORD_SIZE;
-   res = amdgpu_eeprom_read(>pm.smu_i2c,
+   res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
 control->i2c_address +
 RAS_INDEX_TO_OFFSET(control, fri),
 buf, buf_size);
@@ -1009,7 +1009,7 @@ static int __verify_ras_table_checksum(struct 
amdgpu_ras_eeprom_control *control
return -ENOMEM;
}
 
-   res = amdgpu_eeprom_read(>pm.smu_i2c,
+   res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
 control->i2c_address +
 control->ras_header_offset,
 

Re: [PATCH RESEND] drm/amd/display: Force link_rate as LINK_RATE_RBR2 for 2018 15" Apple Retina panels

[Alex Deucher]

On Wed, Jan 26, 2022 at 8:56 AM Aditya Garg  wrote:
>
> From: Aun-Ali Zaidi 
>
> The eDP link rate reported by the DP_MAX_LINK_RATE dpcd register (0xa) is
> contradictory to the highest rate supported reported by
> EDID (0xc = LINK_RATE_RBR2). The effects of this compounded with commit
> '4a8ca46bae8a ("drm/amd/display: Default max bpc to 16 for eDP")' results
> in no display modes being found and a dark panel.
>
> For now, simply force the maximum supported link rate for the eDP attached
> 2018 15" Apple Retina panels.
>
> Additionally, we must also check the firmware revision since the device ID
> reported by the DPCD is identical to that of the more capable 16,1,
> incorrectly quirking it. We also use said firmware check to quirk the
> refreshed 15,1 models with Vega graphics as they use a slightly newer
> firmware version.
>
> Tested-by: Aun-Ali Zaidi 
> Signed-off-by: Aun-Ali Zaidi 
> Signed-off-by: Aditya Garg 
> ---
>  .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 19 +++
>  1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 05e216524..17939ad17 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -5597,6 +5597,25 @@ static bool retrieve_link_cap(struct dc_link *link)
> dp_hw_fw_revision.ieee_fw_rev,
> sizeof(dp_hw_fw_revision.ieee_fw_rev));
>
> +   /* Quirk for Apple MBP 2018 15" Retina panels: wrong DP_MAX_LINK_RATE 
> */
> +   {
> +   uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 };
> +   uint8_t fwrev_mbp_2018[] = { 7, 4 };
> +   uint8_t fwrev_mbp_2018_vega[] = { 8, 4 };
> +
> +   // We also check for the firmware revision as 16,1 models 
> have an
> +   // identical device id and are incorrectly quirked otherwise.

C style comments please.  I'll let one of the display guys comment on
the rest of the patch.  Seems reasonable, we have a similar quirk for
the Apple MBP 2017 15" Retina panel later in this function.  Could you
move this next to the other quirk?

Alex


> +   if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
> +   !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018,
> +sizeof(str_mbp_2018)) &&
> +   (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018,
> +sizeof(fwrev_mbp_2018)) ||
> +   !memcmp(link->dpcd_caps.sink_fw_revision, 
> fwrev_mbp_2018_vega,
> +sizeof(fwrev_mbp_2018_vega {
> +   link->reported_link_cap.link_rate = LINK_RATE_RBR2;
> +   }
> +   }
> +
> memset(>dpcd_caps.dsc_caps, '\0',
> sizeof(link->dpcd_caps.dsc_caps));
> memset(>dpcd_caps.fec_cap, '\0', 
> sizeof(link->dpcd_caps.fec_cap));
> --
> 2.25.1
>
>

Re: [PATCH] drm/amdgpu/swsmu/i2c: return an error if the SMU is not running

[Luben Tuikov]

Reviewed-by: Luben Tuikov 

Regards,
Luben

On 1/27/22 12:23, Alex Deucher wrote:
> Return an error if someone tries to use the i2c bus when the
> SMU is not running.  Otherwise we can end up sending commands
> to the SMU which will either get ignored or could cause other
> issues depending on what state the GPU and SMU are in.
>
> Cc: luben.tui...@amd.com
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c   | 3 +++
>  drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 +++
>  drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 3 +++
>  drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c  | 3 +++
>  4 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 2c78d04d5611..bc20d0da4393 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -2070,6 +2070,9 @@ static int arcturus_i2c_xfer(struct i2c_adapter 
> *i2c_adap,
>   int i, j, r, c;
>   u16 dir;
>  
> + if (!adev->pm.dpm_enabled)
> + return -EBUSY;
> +
>   req = kzalloc(sizeof(*req), GFP_KERNEL);
>   if (!req)
>   return -ENOMEM;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 84834c24a7e9..47a75f9c453e 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -2754,6 +2754,9 @@ static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
>   int i, j, r, c;
>   u16 dir;
>  
> + if (!adev->pm.dpm_enabled)
> + return -EBUSY;
> +
>   req = kzalloc(sizeof(*req), GFP_KERNEL);
>   if (!req)
>   return -ENOMEM;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 651fe748e423..bca622ca9af4 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -3449,6 +3449,9 @@ static int sienna_cichlid_i2c_xfer(struct i2c_adapter 
> *i2c_adap,
>   int i, j, r, c;
>   u16 dir;
>  
> + if (!adev->pm.dpm_enabled)
> + return -EBUSY;
> +
>   req = kzalloc(sizeof(*req), GFP_KERNEL);
>   if (!req)
>   return -ENOMEM;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> index 8c02adbf446a..08415de45e16 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> @@ -1473,6 +1473,9 @@ static int aldebaran_i2c_xfer(struct i2c_adapter 
> *i2c_adap,
>   int i, j, r, c;
>   u16 dir;
>  
> + if (!adev->pm.dpm_enabled)
> + return -EBUSY;
> +
>   req = kzalloc(sizeof(*req), GFP_KERNEL);
>   if (!req)
>   return -ENOMEM;

Regards,
-- 
Luben

[PATCH] drm/amdgpu: fix undefined preprocessor identifier 'CONFIG_ARM64'

[Alex Deucher]

Check if the identifer is defined.

Cc: victor.z...@amd.com
Reported-by: kernel test robot 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 40803aab136f..645093610aa0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -294,9 +294,9 @@ struct amdgpu_video_codec_info;
 
 static inline bool is_virtual_machine(void)
 {
-#ifdef CONFIG_X86
+#if defined(CONFIG_X86)
return boot_cpu_has(X86_FEATURE_HYPERVISOR);
-#elif CONFIG_ARM64
+#elif defined(CONFIG_ARM64)
return !is_kernel_in_hyp_mode();
 #else
return false;
-- 
2.34.1

[PATCH] drm/amdgpu/swsmu/i2c: return an error if the SMU is not running

[Alex Deucher]

Return an error if someone tries to use the i2c bus when the
SMU is not running.  Otherwise we can end up sending commands
to the SMU which will either get ignored or could cause other
issues depending on what state the GPU and SMU are in.

Cc: luben.tui...@amd.com
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c   | 3 +++
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 3 +++
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 3 +++
 drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c  | 3 +++
 4 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 2c78d04d5611..bc20d0da4393 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -2070,6 +2070,9 @@ static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
int i, j, r, c;
u16 dir;
 
+   if (!adev->pm.dpm_enabled)
+   return -EBUSY;
+
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 84834c24a7e9..47a75f9c453e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2754,6 +2754,9 @@ static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
int i, j, r, c;
u16 dir;
 
+   if (!adev->pm.dpm_enabled)
+   return -EBUSY;
+
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 651fe748e423..bca622ca9af4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -3449,6 +3449,9 @@ static int sienna_cichlid_i2c_xfer(struct i2c_adapter 
*i2c_adap,
int i, j, r, c;
u16 dir;
 
+   if (!adev->pm.dpm_enabled)
+   return -EBUSY;
+
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 8c02adbf446a..08415de45e16 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1473,6 +1473,9 @@ static int aldebaran_i2c_xfer(struct i2c_adapter 
*i2c_adap,
int i, j, r, c;
u16 dir;
 
+   if (!adev->pm.dpm_enabled)
+   return -EBUSY;
+
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
-- 
2.34.1

Re: [PATCH] drm/amdgpu: Fix an error message in rmmod

[Felix Kuehling]

The hang you're seeing is the result of a command submission of an 
UNMAP_QUEUES and QUERY_STATUS command to the HIQ. This is done using a 
doorbell. KFD writes commands to the HIQ and rings a doorbell to wake up 
the HWS (see kq_submit_packet in kfd_kernel_queue.c). Why does this 
doorbell not trigger gfxoff exit during rmmod?



Regards,
  Felix



Am 2022-01-26 um 22:38 schrieb Yin, Tianci (Rico):


[AMD Official Use Only]


The rmmod ops has prerequisite multi-user target and blacklist amdgpu,
which is IGT requirement so that IGT can make itself DRM master to 
test KMS.

igt-gpu-tools/build/tests/amdgpu/amd_module_load --run-subtest reload

From my understanding, the KFD process belongs to the regular way of 
gfxoff exit, which doorbell writing triggers gfxoff exit. For example, 
KFD maps HCQ thru cmd on HIQ or KIQ ring, or UMD commits jobs on HCQ, 
these both trigger doorbell writing(pls refer to 
gfx_v10_0_ring_set_wptr_compute()).


As to the IGT reload test, the dequeue request is not thru a cmd on a 
ring, it directly writes CP registers, so GFX core remains in gfxoff.


Thanks,
Rico


*From:* Kuehling, Felix 
*Sent:* Wednesday, January 26, 2022 23:08
*To:* Yin, Tianci (Rico) ; Wang, Yang(Kevin) 
; amd-gfx@lists.freedesktop.org 

*Cc:* Grodzovsky, Andrey ; Chen, Guchun 


*Subject:* Re: [PATCH] drm/amdgpu: Fix an error message in rmmod
My question is, why is this problem only seen during module unload? Why
aren't we seeing HWS hangs due to GFX_OFF all the time in normal
operations? For example when the GPU is idle and a new KFD process is
started, creating a new runlist. Are we just getting lucky because the
process first has to allocate some memory, which maybe makes some HW
access (flushing TLBs etc.) that wakes up the GPU?


Regards,
   Felix



Am 2022-01-26 um 01:43 schrieb Yin, Tianci (Rico):
>
> [AMD Official Use Only]
>
>
> Thanks Kevin and Felix!
>
> In gfxoff state, the dequeue request(by cp register writing) can't
> make gfxoff exit, actually the cp is powered off and the cp register
> writing is invalid, doorbell registers writing(regluar way) or
> directly request smu to disable gfx powergate(by invoking
> amdgpu_gfx_off_ctrl) can trigger gfxoff exit.
>
> I have also tryed
> 
amdgpu_dpm_switch_power_profile(adev,PP_SMC_POWER_PROFILE_COMPUTE,false),

> but it has no effect.
>
> [10386.162273] amdgpu: cp queue pipe 4 queue 0 preemption failed
> [10671.225065] amdgpu: mmCP_HQD_ACTIVE : 0x
> [10386.162290] amdgpu: mmCP_HQD_HQ_STATUS0 : 0x
> [10386.162297] amdgpu: mmCP_STAT : 0x
> [10386.162303] amdgpu: mmCP_BUSY_STAT : 0x
> [10386.162308] amdgpu: mmRLC_STAT : 0x
> [10386.162314] amdgpu: mmGRBM_STATUS : 0x
> [10386.162320] amdgpu: mmGRBM_STATUS2: 0x
>
> Thanks again!
> Rico
> 
> *From:* Kuehling, Felix 
> *Sent:* Tuesday, January 25, 2022 23:31
> *To:* Wang, Yang(Kevin) ; Yin, Tianci (Rico)
> ; amd-gfx@lists.freedesktop.org
> 
> *Cc:* Grodzovsky, Andrey ; Chen, Guchun
> 
> *Subject:* Re: [PATCH] drm/amdgpu: Fix an error message in rmmod
> I have no objection to the change. It restores the sequence that was
> used before e9669fb78262. But I don't understand why GFX_OFF is causing
> a preemption error during module unload, but not when KFD is in normal
> use. Maybe it's because of the compute power profile that's normally set
> by amdgpu_amdkfd_set_compute_idle before we interact with the HWS.
>
>
> Either way, the patch is
>
> Acked-by: Felix Kuehling 
>
>
>
> Am 2022-01-25 um 05:48 schrieb Wang, Yang(Kevin):
> >
> > [AMD Official Use Only]
> >
> >
> > [AMD Official Use Only]
> >
> >
> > the issue is introduced in following patch, so add following
> > information is better.
> > /fixes: (e9669fb78262) drm/amdgpu: Add early fini callback/
> > /
> > /
> > Reviewed-by: Yang Wang 
> > /
> > /
> > Best Regards,
> > Kevin
> >
> > 


> > *From:* amd-gfx  on behalf of
> > Tianci Yin 
> > *Sent:* Tuesday, January 25, 2022 6:03 PM
> > *To:* amd-gfx@lists.freedesktop.org 
> > *Cc:* Grodzovsky, Andrey ; Yin, Tianci
> > (Rico) ; Chen, Guchun 
> > *Subject:* [PATCH] drm/amdgpu: Fix an error message in rmmod
> > From: "Tianci.Yin" 
> >
> > [why]
> > In rmmod procedure, kfd sends cp a dequeue request, but the
> > request does not get response, then an error message "cp
> > queue pipe 4 queue 0 preemption failed" printed.
> >
> > [how]
> > Performing kfd suspending after disabling gfxoff can fix it.
> >
> > Change-Id: I0453f28820542d4a5ab26e38fb5b87ed76ce6930
> > Signed-off-by: Tianci.Yin 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 

Re: [PATCH v6 4/4] drm/amd: Only run s3 or s0ix if system is configured properly

[Deucher, Alexander]

[Public]

Series is:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Mario 
Limonciello 
Sent: Wednesday, January 26, 2022 5:58 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Liang, Prike ; Limonciello, Mario 

Subject: [PATCH v6 4/4] drm/amd: Only run s3 or s0ix if system is configured 
properly

This will cause misconfigured systems to not run the GPU suspend
routines.

* In APUs that are properly configured system will go into s2idle.
* In APUs that are intended to be S3 but user selects
  s2idle the GPU will stay fully powered for the suspend.
* In APUs that are intended to be s2idle and system misconfigured
  the GPU will stay fully powered for the suspend.
* In systems that are intended to be s2idle, but AMD dGPU is also
  present, the dGPU will go through S3

Signed-off-by: Mario Limonciello 
---
v5->v6:
 * Move code into prepare vfunc and use DPM_FLAG_SMART_SUSPEND to skip
   suspend code in incorrectly configured systems.
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 922accdd4246..3e581f35f19d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2289,6 +2289,7 @@ static void amdgpu_drv_delayed_reset_work_handler(struct 
work_struct *work)
 static int amdgpu_pmops_prepare(struct device *dev)
 {
 struct drm_device *drm_dev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = drm_to_adev(drm_dev);

 /* Return a positive number here so
  * DPM_FLAG_SMART_SUSPEND works properly
@@ -2296,6 +2297,13 @@ static int amdgpu_pmops_prepare(struct device *dev)
 if (amdgpu_device_supports_boco(drm_dev))
 return pm_runtime_suspended(dev);

+   /* if we will not support s3 or s2i for the device
+*  then skip suspend
+*/
+   if (!amdgpu_acpi_is_s0ix_active(adev) &&
+   !amdgpu_acpi_is_s3_active(adev))
+   return 1;
+
 return 0;
 }

--
2.25.1

RE: [PATCH RESEND] drm/amdgpu: Remove the vega10 from ras support list

[Chen, Guchun]

[AMD Official Use Only]

Hi Jun,

In RAS code, we have this special handling for Vega10. Can you elaborate it 
please? Any problem you have observed?

Regards,
Guchun

-Original Message-
From: Ma, Jun  
Sent: Thursday, January 27, 2022 7:47 PM
To: amd-gfx@lists.freedesktop.org; brahma_sw_dev 
Cc: Zhang, Hawking ; Zhou1, Tao ; Ma, 
Jun 
Subject: [PATCH RESEND] drm/amdgpu: Remove the vega10 from ras support list

Remove vega10 from the ras support check function.
Base on this change, the ras initial function is optimized.

Signed-off-by: majun 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 38 +
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 37e9b7e82993..aa1de974e07e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2129,8 +2129,7 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device 
*adev)
 
 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)  {
-   return adev->asic_type == CHIP_VEGA10 ||
-   adev->asic_type == CHIP_VEGA20 ||
+   return adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_ARCTURUS ||
adev->asic_type == CHIP_ALDEBARAN ||
adev->asic_type == CHIP_SIENNA_CICHLID; @@ -2164,13 +2163,13 @@ 
static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
  * we have to initialize ras as normal. but need check if operation is
  * allowed or not in each function.
  */
-static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
+static bool amdgpu_ras_check_supported(struct amdgpu_device *adev)
 {
adev->ras_hw_enabled = adev->ras_enabled = 0;
 
if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
!amdgpu_ras_asic_supported(adev))
-   return;
+   return false;
 
if (!adev->gmc.xgmi.connected_to_cpu) {
if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { @@ -2203,6 
+2202,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
 
adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
adev->ras_hw_enabled & amdgpu_ras_mask;
+
+   return true;
 }
 
 static void amdgpu_ras_counte_dw(struct work_struct *work) @@ -2236,6 +2237,9 
@@ int amdgpu_ras_init(struct amdgpu_device *adev)
int r;
bool df_poison, umc_poison;
 
+   if (!amdgpu_ras_check_supported(adev))
+   return -EINVAL;
+
if (con)
return 0;
 
@@ -2250,28 +2254,24 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
INIT_DELAYED_WORK(>ras_counte_delay_work, amdgpu_ras_counte_dw);
atomic_set(>ras_ce_count, 0);
atomic_set(>ras_ue_count, 0);
-
con->objs = (struct ras_manager *)(con + 1);
+   con->features = 0;
 
amdgpu_ras_set_context(adev, con);
 
-   amdgpu_ras_check_supported(adev);
-
-   if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
-   /* set gfx block ras context feature for VEGA20 Gaming
-* send ras disable cmd to ras ta during ras late init.
-*/
-   if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
+   if (!adev->ras_enabled) {
+   /* set gfx block ras context feature for VEGA20 Gaming
+* send ras disable cmd to ras ta during ras late init.
+*/
+   if (adev->asic_type == CHIP_VEGA20) {
con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
-
return 0;
+   } else {
+   r = 0;
+   goto release_con;
}
-
-   r = 0;
-   goto release_con;
}
 
-   con->features = 0;
INIT_LIST_HEAD(>head);
/* Might need get this flag from vbios. */
con->flags = RAS_DEFAULT_FLAGS;
@@ -2545,7 +2545,9 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
 
 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)  {
-   amdgpu_ras_check_supported(adev);
+   if (!amdgpu_ras_check_supported(adev))
+   return;
+
if (!adev->ras_hw_enabled)
return;
 
--
2.25.1

Re: FIx for UMR arm build

[StDenis, Tom]

[AMD Official Use Only]

Pushed out, with your Rb.




From: Alex Deucher 
Sent: Thursday, January 27, 2022 09:11
To: Newton, Jeremy
Cc: amd-gfx@lists.freedesktop.org; StDenis, Tom
Subject: Re: FIx for UMR arm build

Reviewed-by: Alex Deucher 

On Thu, Jan 27, 2022 at 8:39 AM Newton, Jeremy  wrote:
>
> [AMD Official Use Only]
>
>
> Sorry I think I forgot to attach the patch 
> 
> From: Newton, Jeremy
> Sent: January 27, 2022 8:39 AM
> To: amd-gfx@lists.freedesktop.org 
> Cc: StDenis, Tom 
> Subject: FIx for UMR arm build
>
> I know we only technically only care about x86, but this just fixes a syntax 
> issue if you build on arm.

Re: [PATCH] drm/amdgpu: fix that issue that the number of the crtc of the 3250c is not correct

[Alex Deucher]

Please use C style comments /* */.  WIth that fixed:
Reviewed-by: Alex Deucher 


On Thu, Jan 27, 2022 at 3:12 AM RyanLin  wrote:
>
> [Why]
> External displays take priority over internal display when there are fewer
> display controllers than displays.
>
> [How]
> The root cause is because of that number of the crtc is not correct.
> The number of the crtc on the 3250c is 3, but on the 3500c is 4.
> On the source code, we can see that number of the crtc has been fixed at 4.
> Needs to set the num_crtc to 3 for 3250c platform.
>
> Signed-off-by: RyanLin 
> Change-Id: I837df7101cc4849d2c3021fd529b4061edab4bb1
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 40c91b448f7d..dbeef7b57a9b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2738,9 +2738,15 @@ static int dm_early_init(void *handle)
> break;
>  #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> case CHIP_RAVEN:
> -   adev->mode_info.num_crtc = 4;
> -   adev->mode_info.num_hpd = 4;
> -   adev->mode_info.num_dig = 4;
> +   if (adev->rev_id >= 8) { //chip_name = "raven2";
> +   adev->mode_info.num_crtc = 3;
> +   adev->mode_info.num_hpd = 3;
> +   adev->mode_info.num_dig = 3;
> +   } else {
> +   adev->mode_info.num_crtc = 4;
> +   adev->mode_info.num_hpd = 4;
> +   adev->mode_info.num_dig = 4;
> +   }
> break;
>  #endif
>  #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> --
> 2.25.1
>

[PATCH v11 5/5] drm/amdgpu: add drm buddy support to amdgpu

[Arunpravin]

- Remove drm_mm references and replace with drm buddy functionalities
- Add res cursor support for drm buddy

v2(Matthew Auld):
  - replace spinlock with mutex as we call kmem_cache_zalloc
(..., GFP_KERNEL) in drm_buddy_alloc() function

  - lock drm_buddy_block_trim() function as it calls
mark_free/mark_split are all globally visible

v3(Matthew Auld):
  - remove trim method error handling as we address the failure case
at drm_buddy_block_trim() function

v4:
  - fix warnings reported by kernel test robot 

v5:
  - fix merge conflict issue

v6:
  - fix warnings reported by kernel test robot 

Signed-off-by: Arunpravin 
---
 drivers/gpu/drm/Kconfig   |   1 +
 .../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h|  97 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |   7 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c  | 259 ++
 4 files changed, 231 insertions(+), 133 deletions(-)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index dfdd3ec5f793..eb5a57ae3c5c 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -279,6 +279,7 @@ config DRM_AMDGPU
select HWMON
select BACKLIGHT_CLASS_DEVICE
select INTERVAL_TREE
+   select DRM_BUDDY
help
  Choose this option if you have a recent AMD Radeon graphics card.
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index acfa207cf970..da12b4ff2e45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -30,12 +30,15 @@
 #include 
 #include 
 
+#include "amdgpu_vram_mgr.h"
+
 /* state back for walking over vram_mgr and gtt_mgr allocations */
 struct amdgpu_res_cursor {
uint64_tstart;
uint64_tsize;
uint64_tremaining;
-   struct drm_mm_node  *node;
+   void*node;
+   uint32_tmem_type;
 };
 
 /**
@@ -52,27 +55,63 @@ static inline void amdgpu_res_first(struct ttm_resource 
*res,
uint64_t start, uint64_t size,
struct amdgpu_res_cursor *cur)
 {
+   struct drm_buddy_block *block;
+   struct list_head *head, *next;
struct drm_mm_node *node;
 
-   if (!res || res->mem_type == TTM_PL_SYSTEM) {
-   cur->start = start;
-   cur->size = size;
-   cur->remaining = size;
-   cur->node = NULL;
-   WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT);
-   return;
-   }
+   if (!res)
+   goto err_out;
 
BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
 
-   node = to_ttm_range_mgr_node(res)->mm_nodes;
-   while (start >= node->size << PAGE_SHIFT)
-   start -= node++->size << PAGE_SHIFT;
+   cur->mem_type = res->mem_type;
+
+   switch (cur->mem_type) {
+   case TTM_PL_VRAM:
+   head = _amdgpu_vram_mgr_node(res)->blocks;
+
+   block = list_first_entry_or_null(head,
+struct drm_buddy_block,
+link);
+   if (!block)
+   goto err_out;
+
+   while (start >= amdgpu_node_size(block)) {
+   start -= amdgpu_node_size(block);
+
+   next = block->link.next;
+   if (next != head)
+   block = list_entry(next, struct 
drm_buddy_block, link);
+   }
+
+   cur->start = amdgpu_node_start(block) + start;
+   cur->size = min(amdgpu_node_size(block) - start, size);
+   cur->remaining = size;
+   cur->node = block;
+   break;
+   case TTM_PL_TT:
+   node = to_ttm_range_mgr_node(res)->mm_nodes;
+   while (start >= node->size << PAGE_SHIFT)
+   start -= node++->size << PAGE_SHIFT;
+
+   cur->start = (node->start << PAGE_SHIFT) + start;
+   cur->size = min((node->size << PAGE_SHIFT) - start, size);
+   cur->remaining = size;
+   cur->node = node;
+   break;
+   default:
+   goto err_out;
+   }
 
-   cur->start = (node->start << PAGE_SHIFT) + start;
-   cur->size = min((node->size << PAGE_SHIFT) - start, size);
+   return;
+
+err_out:
+   cur->start = start;
+   cur->size = size;
cur->remaining = size;
-   cur->node = node;
+   cur->node = NULL;
+   WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT);
+   return;
 }
 
 /**
@@ -85,7 +124,9 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
  */
 static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t 
size)
 {
-   struct drm_mm_node *node = 

[PATCH v11 4/5] drm/amdgpu: move vram inline functions into a header

[Arunpravin]

Move shared vram inline functions and structs
into a header file

Signed-off-by: Arunpravin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 51 
 1 file changed, 51 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
new file mode 100644
index ..59983464cce5
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __AMDGPU_VRAM_MGR_H__
+#define __AMDGPU_VRAM_MGR_H__
+
+#include 
+
+struct amdgpu_vram_mgr_node {
+   struct ttm_resource base;
+   struct list_head blocks;
+   unsigned long flags;
+};
+
+static inline u64 amdgpu_node_start(struct drm_buddy_block *block)
+{
+   return drm_buddy_block_offset(block);
+}
+
+static inline u64 amdgpu_node_size(struct drm_buddy_block *block)
+{
+   return PAGE_SIZE << drm_buddy_block_order(block);
+}
+
+static inline struct amdgpu_vram_mgr_node *
+to_amdgpu_vram_mgr_node(struct ttm_resource *res)
+{
+   return container_of(res, struct amdgpu_vram_mgr_node, base);
+}
+
+#endif
-- 
2.25.1

[PATCH v11 3/5] drm: implement a method to free unused pages

[Arunpravin]

On contiguous allocation, we round up the size
to the *next* power of 2, implement a function
to free the unused pages after the newly allocate block.

v2(Matthew Auld):
  - replace function name 'drm_buddy_free_unused_pages' with
drm_buddy_block_trim
  - replace input argument name 'actual_size' with 'new_size'
  - add more validation checks for input arguments
  - add overlaps check to avoid needless searching and splitting
  - merged the below patch to see the feature in action
 - add free unused pages support to i915 driver
  - lock drm_buddy_block_trim() function as it calls mark_free/mark_split
are all globally visible

v3(Matthew Auld):
  - remove trim method error handling as we address the failure case
at drm_buddy_block_trim() function

v4:
  - in case of trim, at __alloc_range() split_block failure path
marks the block as free and removes it from the original list,
potentially also freeing it, to overcome this problem, we turn
the drm_buddy_block_trim() input node into a temporary node to
prevent recursively freeing itself, but still retain the
un-splitting/freeing of the other nodes(Matthew Auld)

  - modify the drm_buddy_block_trim() function return type

v5(Matthew Auld):
  - revert drm_buddy_block_trim() function return type changes in v4
  - modify drm_buddy_block_trim() passing argument n_pages to original_size
as n_pages has already been rounded up to the next power-of-two and
passing n_pages results noop

v6:
  - fix warnings reported by kernel test robot 

v7:
  - modify drm_buddy_block_trim() function doc description
  - at drm_buddy_block_trim() handle non-allocated block as
a serious programmer error
  - fix a typo

Signed-off-by: Arunpravin 
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/drm_buddy.c   | 69 +++
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 10 +++
 include/drm/drm_buddy.h   |  4 ++
 3 files changed, 83 insertions(+)

diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 30cad939a112..4845ef784b5e 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -542,6 +542,75 @@ static int __drm_buddy_alloc_range(struct drm_buddy *mm,
return __alloc_range(mm, , start, size, blocks);
 }
 
+/**
+ * drm_buddy_block_trim - free unused pages
+ *
+ * @mm: DRM buddy manager
+ * @new_size: original size requested
+ * @blocks: Input and output list of allocated blocks.
+ * MUST contain single block as input to be trimmed.
+ * On success will contain the newly allocated blocks
+ * making up the @new_size. Blocks always appear in
+ * ascending order
+ *
+ * For contiguous allocation, we round up the size to the nearest
+ * power of two value, drivers consume *actual* size, so remaining
+ * portions are unused and can be optionally freed with this function
+ *
+ * Returns:
+ * 0 on success, error code on failure.
+ */
+int drm_buddy_block_trim(struct drm_buddy *mm,
+u64 new_size,
+struct list_head *blocks)
+{
+   struct drm_buddy_block *parent;
+   struct drm_buddy_block *block;
+   LIST_HEAD(dfs);
+   u64 new_start;
+   int err;
+
+   if (!list_is_singular(blocks))
+   return -EINVAL;
+
+   block = list_first_entry(blocks,
+struct drm_buddy_block,
+link);
+
+   if (WARN_ON(!drm_buddy_block_is_allocated(block)))
+   return -EINVAL;
+
+   if (new_size > drm_buddy_block_size(mm, block))
+   return -EINVAL;
+
+   if (!new_size || !IS_ALIGNED(new_size, mm->chunk_size))
+   return -EINVAL;
+
+   if (new_size == drm_buddy_block_size(mm, block))
+   return 0;
+
+   list_del(>link);
+   mark_free(mm, block);
+   mm->avail += drm_buddy_block_size(mm, block);
+
+   /* Prevent recursively freeing this node */
+   parent = block->parent;
+   block->parent = NULL;
+
+   new_start = drm_buddy_block_offset(block);
+   list_add(>tmp_link, );
+   err =  __alloc_range(mm, , new_start, new_size, blocks);
+   if (err) {
+   mark_allocated(block);
+   mm->avail -= drm_buddy_block_size(mm, block);
+   list_add(>link, blocks);
+   }
+
+   block->parent = parent;
+   return err;
+}
+EXPORT_SYMBOL(drm_buddy_block_trim);
+
 /**
  * drm_buddy_alloc_blocks - allocate power-of-two blocks
  *
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c 
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index 7f553cceb6c0..76d5211c25eb 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -97,6 +97,16 @@ static int i915_ttm_buddy_man_alloc(struct 
ttm_resource_manager *man,
if (unlikely(err))
goto err_free_blocks;
 
+   if (place->flags & TTM_PL_FLAG_CONTIGUOUS) {
+   u64 

[PATCH v11 2/5] drm: implement top-down allocation method

[Arunpravin]

Implemented a function which walk through the order list,
compares the offset and returns the maximum offset block,
this method is unpredictable in obtaining the high range
address blocks which depends on allocation and deallocation.
for instance, if driver requests address at a low specific
range, allocator traverses from the root block and splits
the larger blocks until it reaches the specific block and
in the process of splitting, lower orders in the freelist
are occupied with low range address blocks and for the
subsequent TOPDOWN memory request we may return the low
range blocks.To overcome this issue, we may go with the
below approach.

The other approach, sorting each order list entries in
ascending order and compares the last entry of each
order list in the freelist and return the max block.
This creates sorting overhead on every drm_buddy_free()
request and split up of larger blocks for a single page
request.

v2:
  - Fix alignment issues(Matthew Auld)
  - Remove unnecessary list_empty check(Matthew Auld)
  - merged the below patch to see the feature in action
 - add top-down alloc support to i915 driver

Signed-off-by: Arunpravin 
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/drm_buddy.c   | 36 ---
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c |  3 ++
 include/drm/drm_buddy.h   |  1 +
 3 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index cfc160a1ef1a..30cad939a112 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -369,6 +369,26 @@ alloc_range_bias(struct drm_buddy *mm,
return ERR_PTR(err);
 }
 
+static struct drm_buddy_block *
+get_maxblock(struct list_head *head)
+{
+   struct drm_buddy_block *max_block = NULL, *node;
+
+   max_block = list_first_entry_or_null(head,
+struct drm_buddy_block,
+link);
+   if (!max_block)
+   return NULL;
+
+   list_for_each_entry(node, head, link) {
+   if (drm_buddy_block_offset(node) >
+   drm_buddy_block_offset(max_block))
+   max_block = node;
+   }
+
+   return max_block;
+}
+
 static struct drm_buddy_block *
 alloc_from_freelist(struct drm_buddy *mm,
unsigned int order,
@@ -379,11 +399,17 @@ alloc_from_freelist(struct drm_buddy *mm,
int err;
 
for (i = order; i <= mm->max_order; ++i) {
-   block = list_first_entry_or_null(>free_list[i],
-struct drm_buddy_block,
-link);
-   if (block)
-   break;
+   if (flags & DRM_BUDDY_TOPDOWN_ALLOCATION) {
+   block = get_maxblock(>free_list[i]);
+   if (block)
+   break;
+   } else {
+   block = list_first_entry_or_null(>free_list[i],
+struct drm_buddy_block,
+link);
+   if (block)
+   break;
+   }
}
 
if (!block)
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c 
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index a328a38fab07..7f553cceb6c0 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -53,6 +53,9 @@ static int i915_ttm_buddy_man_alloc(struct 
ttm_resource_manager *man,
INIT_LIST_HEAD(_res->blocks);
bman_res->mm = mm;
 
+   if (place->flags & TTM_PL_FLAG_TOPDOWN)
+   bman_res->flags |= DRM_BUDDY_TOPDOWN_ALLOCATION;
+
if (place->fpfn || lpfn != man->size)
bman_res->flags |= DRM_BUDDY_RANGE_ALLOCATION;
 
diff --git a/include/drm/drm_buddy.h b/include/drm/drm_buddy.h
index 54f25a372f27..f0378fb48d06 100644
--- a/include/drm/drm_buddy.h
+++ b/include/drm/drm_buddy.h
@@ -23,6 +23,7 @@
 })
 
 #define DRM_BUDDY_RANGE_ALLOCATION (1 << 0)
+#define DRM_BUDDY_TOPDOWN_ALLOCATION (1 << 1)
 
 struct drm_buddy_block {
 #define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
-- 
2.25.1

[PATCH v11 1/5] drm: improve drm_buddy_alloc function

[Arunpravin]

- Make drm_buddy_alloc a single function to handle
  range allocation and non-range allocation demands

- Implemented a new function alloc_range() which allocates
  the requested power-of-two block comply with range limitations

- Moved order computation and memory alignment logic from
  i915 driver to drm buddy

v2:
  merged below changes to keep the build unbroken
   - drm_buddy_alloc_range() becomes obsolete and may be removed
   - enable ttm range allocation (fpfn / lpfn) support in i915 driver
   - apply enhanced drm_buddy_alloc() function to i915 driver

v3(Matthew Auld):
  - Fix alignment issues and remove unnecessary list_empty check
  - add more validation checks for input arguments
  - make alloc_range() block allocations as bottom-up
  - optimize order computation logic
  - replace uint64_t with u64, which is preferred in the kernel

v4(Matthew Auld):
  - keep drm_buddy_alloc_range() function implementation for generic
actual range allocations
  - keep alloc_range() implementation for end bias allocations

v5(Matthew Auld):
  - modify drm_buddy_alloc() passing argument place->lpfn to lpfn
as place->lpfn will currently always be zero for i915

v6(Matthew Auld):
  - fixup potential uaf - If we are unlucky and can't allocate
enough memory when splitting blocks, where we temporarily
end up with the given block and its buddy on the respective
free list, then we need to ensure we delete both blocks,
and no just the buddy, before potentially freeing them

  - fix warnings reported by kernel test robot 

v7(Matthew Auld):
  - revert fixup potential uaf
  - keep __alloc_range() add node to the list logic same as
drm_buddy_alloc_blocks() by having a temporary list variable
  - at drm_buddy_alloc_blocks() keep i915 range_overflows macro
and add a new check for end variable

v8:
  - fix warnings reported by kernel test robot 

Signed-off-by: Arunpravin 
---
 drivers/gpu/drm/drm_buddy.c   | 315 +-
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c |  67 ++--
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.h |   2 +
 include/drm/drm_buddy.h   |  13 +-
 4 files changed, 280 insertions(+), 117 deletions(-)

diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index d60878bc9c20..cfc160a1ef1a 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -282,23 +282,97 @@ void drm_buddy_free_list(struct drm_buddy *mm, struct 
list_head *objects)
 }
 EXPORT_SYMBOL(drm_buddy_free_list);
 
-/**
- * drm_buddy_alloc_blocks - allocate power-of-two blocks
- *
- * @mm: DRM buddy manager to allocate from
- * @order: size of the allocation
- *
- * The order value here translates to:
- *
- * 0 = 2^0 * mm->chunk_size
- * 1 = 2^1 * mm->chunk_size
- * 2 = 2^2 * mm->chunk_size
- *
- * Returns:
- * allocated ptr to the _buddy_block on success
- */
-struct drm_buddy_block *
-drm_buddy_alloc_blocks(struct drm_buddy *mm, unsigned int order)
+static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2)
+{
+   return s1 <= e2 && e1 >= s2;
+}
+
+static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2)
+{
+   return s1 <= s2 && e1 >= e2;
+}
+
+static struct drm_buddy_block *
+alloc_range_bias(struct drm_buddy *mm,
+u64 start, u64 end,
+unsigned int order)
+{
+   struct drm_buddy_block *block;
+   struct drm_buddy_block *buddy;
+   LIST_HEAD(dfs);
+   int err;
+   int i;
+
+   end = end - 1;
+
+   for (i = 0; i < mm->n_roots; ++i)
+   list_add_tail(>roots[i]->tmp_link, );
+
+   do {
+   u64 block_start;
+   u64 block_end;
+
+   block = list_first_entry_or_null(,
+struct drm_buddy_block,
+tmp_link);
+   if (!block)
+   break;
+
+   list_del(>tmp_link);
+
+   if (drm_buddy_block_order(block) < order)
+   continue;
+
+   block_start = drm_buddy_block_offset(block);
+   block_end = block_start + drm_buddy_block_size(mm, block) - 1;
+
+   if (!overlaps(start, end, block_start, block_end))
+   continue;
+
+   if (drm_buddy_block_is_allocated(block))
+   continue;
+
+   if (contains(start, end, block_start, block_end) &&
+   order == drm_buddy_block_order(block)) {
+   /*
+* Find the free block within the range.
+*/
+   if (drm_buddy_block_is_free(block))
+   return block;
+
+   continue;
+   }
+
+   if (!drm_buddy_block_is_split(block)) {
+   err = split_block(mm, block);
+   if (unlikely(err))
+   goto 

Re: FIx for UMR arm build

[Alex Deucher]

Reviewed-by: Alex Deucher 

On Thu, Jan 27, 2022 at 8:39 AM Newton, Jeremy  wrote:
>
> [AMD Official Use Only]
>
>
> Sorry I think I forgot to attach the patch 
> 
> From: Newton, Jeremy
> Sent: January 27, 2022 8:39 AM
> To: amd-gfx@lists.freedesktop.org 
> Cc: StDenis, Tom 
> Subject: FIx for UMR arm build
>
> I know we only technically only care about x86, but this just fixes a syntax 
> issue if you build on arm.

Re: FIx for UMR arm build

[Newton, Jeremy]

[AMD Official Use Only]

Sorry I think I forgot to attach the patch 

From: Newton, Jeremy
Sent: January 27, 2022 8:39 AM
To: amd-gfx@lists.freedesktop.org 
Cc: StDenis, Tom 
Subject: FIx for UMR arm build

I know we only technically only care about x86, but this just fixes a syntax 
issue if you build on arm.
From d20c6d41ed47553ddbb6cf90a31649da4d40bd72 Mon Sep 17 00:00:00 2001
From: Jeremy Newton 
Date: Wed, 12 Jan 2022 10:43:07 -0500
Subject: [PATCH] umr/gui: fix ARM build

Simple syntax error in one of the arm cases for imgui

Signed-off-by: Jeremy Newton 
---
 src/app/gui/imgui/imgui_internal.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/app/gui/imgui/imgui_internal.h b/src/app/gui/imgui/imgui_internal.h
index 3180cc5..bf00e91 100644
--- a/src/app/gui/imgui/imgui_internal.h
+++ b/src/app/gui/imgui/imgui_internal.h
@@ -264,7 +264,7 @@ namespace ImStb
 #define IM_DEBUG_BREAK()__asm__ volatile("int $0x03")
 #elif defined(__GNUC__) && defined(__thumb__)
 #define IM_DEBUG_BREAK()__asm__ volatile(".inst 0xde01")
-#elif defined(__GNUC__) defined(__arm__) && !defined(__thumb__)
+#elif defined(__GNUC__) && defined(__arm__) && !defined(__thumb__)
 #define IM_DEBUG_BREAK()__asm__ volatile(".inst 0xe7f001f0");
 #else
 #define IM_DEBUG_BREAK()IM_ASSERT(0)// It is expected that you define IM_DEBUG_BREAK() into something that will break nicely in a debugger!
-- 
2.33.1

FIx for UMR arm build

[Newton, Jeremy]

[AMD Official Use Only]

I know we only technically only care about x86, but this just fixes a syntax 
issue if you build on arm.

[PATCH RESEND] drm/amdgpu: Remove the vega10 from ras support list

[majun]

Remove vega10 from the ras support check function.
Base on this change, the ras initial function is optimized.

Signed-off-by: majun 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 38 +
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 37e9b7e82993..aa1de974e07e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2129,8 +2129,7 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device 
*adev)
 
 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
 {
-   return adev->asic_type == CHIP_VEGA10 ||
-   adev->asic_type == CHIP_VEGA20 ||
+   return adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_ARCTURUS ||
adev->asic_type == CHIP_ALDEBARAN ||
adev->asic_type == CHIP_SIENNA_CICHLID;
@@ -2164,13 +2163,13 @@ static void amdgpu_ras_get_quirks(struct amdgpu_device 
*adev)
  * we have to initialize ras as normal. but need check if operation is
  * allowed or not in each function.
  */
-static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
+static bool amdgpu_ras_check_supported(struct amdgpu_device *adev)
 {
adev->ras_hw_enabled = adev->ras_enabled = 0;
 
if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
!amdgpu_ras_asic_supported(adev))
-   return;
+   return false;
 
if (!adev->gmc.xgmi.connected_to_cpu) {
if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
@@ -2203,6 +2202,8 @@ static void amdgpu_ras_check_supported(struct 
amdgpu_device *adev)
 
adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
adev->ras_hw_enabled & amdgpu_ras_mask;
+
+   return true;
 }
 
 static void amdgpu_ras_counte_dw(struct work_struct *work)
@@ -2236,6 +2237,9 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
int r;
bool df_poison, umc_poison;
 
+   if (!amdgpu_ras_check_supported(adev))
+   return -EINVAL;
+
if (con)
return 0;
 
@@ -2250,28 +2254,24 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
INIT_DELAYED_WORK(>ras_counte_delay_work, amdgpu_ras_counte_dw);
atomic_set(>ras_ce_count, 0);
atomic_set(>ras_ue_count, 0);
-
con->objs = (struct ras_manager *)(con + 1);
+   con->features = 0;
 
amdgpu_ras_set_context(adev, con);
 
-   amdgpu_ras_check_supported(adev);
-
-   if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
-   /* set gfx block ras context feature for VEGA20 Gaming
-* send ras disable cmd to ras ta during ras late init.
-*/
-   if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
+   if (!adev->ras_enabled) {
+   /* set gfx block ras context feature for VEGA20 Gaming
+* send ras disable cmd to ras ta during ras late init.
+*/
+   if (adev->asic_type == CHIP_VEGA20) {
con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
-
return 0;
+   } else {
+   r = 0;
+   goto release_con;
}
-
-   r = 0;
-   goto release_con;
}
 
-   con->features = 0;
INIT_LIST_HEAD(>head);
/* Might need get this flag from vbios. */
con->flags = RAS_DEFAULT_FLAGS;
@@ -2545,7 +2545,9 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
 
 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
 {
-   amdgpu_ras_check_supported(adev);
+   if (!amdgpu_ras_check_supported(adev))
+   return;
+
if (!adev->ras_hw_enabled)
return;
 
-- 
2.25.1

Re: [PATCH] drivers: Fix typo in comment

[????]

Thanks, I have splitit.



  
 
 


 --Reply to Message--
 On Thu, Jan 27, 2022 18:06 PM Daniel Vetterhttp://blog.ffwll.ch
OnThu,Jan27,2022at02:51:56PM+0800,tangmengwrote:
Replacedisbalewithdisableandreplaceunavaibalewithunavailable.

Signed-off-by:tangmeng

Re: [PATCH] drivers: Fix typo in comment

[Daniel Vetter]

On Thu, Jan 27, 2022 at 07:56:05AM +0100, Greg KH wrote:
> On Thu, Jan 27, 2022 at 02:51:56PM +0800, tangmeng wrote:
> > Replace disbale with disable and replace unavaibale with unavailable.
> > 
> > Signed-off-by: tangmeng 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
> >  drivers/gpu/drm/tilcdc/tilcdc_crtc.c  | 2 +-
> >  drivers/pcmcia/rsrc_nonstatic.c   | 2 +-
> >  drivers/usb/chipidea/udc.c| 2 +-
> >  4 files changed, 4 insertions(+), 4 deletions(-)
> 
> This needs to be broken up per-subsystem, thanks.

For drm please also split it per-driver, so one patch per file you change
here.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

Re: [RFC PATCH v5 0/3] Add support modifiers for drivers whose planes only support linear layout

[Daniel Vetter]

On Thu, Jan 27, 2022 at 12:25:36PM +0900, Tomohito Esaki wrote:
> Some drivers whose planes only support linear layout fb do not support format
> modifiers.
> These drivers should support modifiers, however the DRM core should handle 
> this
> rather than open-coding in every driver.
> 
> In this patch series, these drivers expose format modifiers based on the
> following suggestion[1].
> 
> On Thu, Nov 18, 2021 at 01:02:11PM +, Daniel Stone wrote:
> > I think the best way forward here is:
> >   - add a new mode_config.cannot_support_modifiers flag, and enable
> > this in radeon (plus any other drivers in the same boat)
> >   - change drm_universal_plane_init() to advertise the LINEAR modifier
> > when NULL is passed as the modifier list (including installing a
> > default .format_mod_supported hook)
> >   - remove the mode_config.allow_fb_modifiers hook and always
> > advertise modifier support, unless
> > mode_config.cannot_support_modifiers is set
> 
> 
> [1] 
> https://patchwork.kernel.org/project/linux-renesas-soc/patch/20190509054518.10781-1-e...@igel.co.jp/#24602575

Two procedural things:
- There's an r-b on all the patches from Andy from the last round, please
  include that.
- Please also include a changelog per-patch (at least going forward), that
  helps with judging where a patch series is.

But aside from this I think this looks ready.

Cheers, Daniel

> 
> v5:
> * rebase to the latest master branch (5.17-rc1+)
>   + "drm/plane: Make format_mod_supported truly optional" patch [2]
>   [2] https://patchwork.freedesktop.org/patch/467940/?series=98255=3
> 
> * change default_modifiers array from non-static to static
> * remove terminator in default_modifiers array
> * use ARRAY_SIZE to get the format_modifier_count
> * keep a sanity check in plane init func
> * modify several kerneldocs
> 
> v4: https://www.spinics.net/lists/dri-devel/msg329508.html
> * modify documentation for fb_modifiers_not_supported flag in kerneldoc
> 
> v3: https://www.spinics.net/lists/dri-devel/msg329102.html
> * change the order as follows:
>1. add fb_modifiers_not_supported flag
>2. add default modifiers
>3. remove allow_fb_modifiers flag
> * add a conditional disable in amdgpu_dm_plane_init()
> 
> v2: https://www.spinics.net/lists/dri-devel/msg328939.html
> * rebase to the latest master branch (5.16.0+)
>   + "drm/plane: Make format_mod_supported truly optional" patch [2]
> 
> v1: https://www.spinics.net/lists/dri-devel/msg327352.html
> * The initial patch set
> 
> Tomohito Esaki (3):
>   drm: introduce fb_modifiers_not_supported flag in mode_config
>   drm: add support modifiers for drivers whose planes only support
> linear layout
>   drm: remove allow_fb_modifiers
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  6 ++---
>  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|  2 ++
>  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  2 ++
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |  1 +
>  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  2 ++
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +++
>  drivers/gpu/drm/drm_framebuffer.c |  6 ++---
>  drivers/gpu/drm/drm_ioctl.c   |  2 +-
>  drivers/gpu/drm/drm_plane.c   | 23 +++
>  drivers/gpu/drm/nouveau/nouveau_display.c |  6 +++--
>  drivers/gpu/drm/radeon/radeon_display.c   |  2 ++
>  .../gpu/drm/selftests/test-drm_framebuffer.c  |  1 -
>  include/drm/drm_mode_config.h | 18 +--
>  include/drm/drm_plane.h   |  3 +++
>  14 files changed, 45 insertions(+), 32 deletions(-)
> 
> -- 
> 2.25.1
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

Re: [PATCH V2] drm/amdgpu: move GTT allocation from gmc_sw_init to gmc_hw_init(V2)

[Christian König]

Am 27.01.22 um 08:52 schrieb Aaron Liu:

The below patch causes system hang for harvested ASICs.
d015e9861e55 drm/amdgpu: improve debug VRAM access performance using sdma

The root cause is that GTT buffer should be allocated after GC SA harvest
programming completed.


That doesn't make much sense. We intentionally modified the code so that 
this is possible.


What is the rational that we need to program the HW before allocating 
system memory?


Regards,
Christian.



For harvested AISC, the GC SA harvest process(see utcl2_harvest) is
programmed in gmc_v10_0_hw_init function. This is a hardware programming.
Therefore should be located in hw init. Hence need to move GTT allocation
from gmc_v*_0_sw_init to gmc_v*_0_hw_init.

V2: expand to all gmc_v*_0_hw_init functions.

Signed-off-by: Aaron Liu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 21 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  3 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  8 
  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  |  4 +++-
  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 13 +
  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 13 +
  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 13 +
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 13 +
  8 files changed, 63 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index d426de48d299..ac75bde8ac61 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -876,3 +876,24 @@ int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
  
  	return 0;

  }
+
+int amdgpu_gmc_allocate_sdma_access_gtt(struct amdgpu_device *adev)
+{
+   int ret;
+
+   ret = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
+   AMDGPU_GEM_DOMAIN_GTT,
+   >mman.sdma_access_bo, NULL,
+   >mman.sdma_access_ptr);
+
+   if (ret)
+   DRM_WARN("Debug VRAM access will use slowpath MM access\n");
+
+   return ret;
+}
+
+void amdgpu_gmc_free_sdma_access_gtt(struct amdgpu_device *adev)
+{
+   amdgpu_bo_free_kernel(>mman.sdma_access_bo, NULL,
+   >mman.sdma_access_ptr);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 93505bb0a36c..b8ba16de5e1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -338,4 +338,7 @@ uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, 
uint64_t mc_addr);
  uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
  uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo 
*bo);
  int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
+int amdgpu_gmc_allocate_sdma_access_gtt(struct amdgpu_device *adev);
+void amdgpu_gmc_free_sdma_access_gtt(struct amdgpu_device *adev);
+
  #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 3d8a20956b74..7ce0478b2908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1823,12 +1823,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
return r;
}
  
-	if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,

-   AMDGPU_GEM_DOMAIN_GTT,
-   >mman.sdma_access_bo, NULL,
-   >mman.sdma_access_ptr))
-   DRM_WARN("Debug VRAM access will use slowpath MM access\n");
-
return 0;
  }
  
@@ -1850,8 +1844,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)

if (adev->mman.stolen_reserved_size)
amdgpu_bo_free_kernel(>mman.stolen_reserved_memory,
  NULL, NULL);
-   amdgpu_bo_free_kernel(>mman.sdma_access_bo, NULL,
-   >mman.sdma_access_ptr);
amdgpu_ttm_fw_reserve_vram_fini(adev);
  
  	if (drm_dev_enter(adev_to_drm(adev), )) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 73ab0eebe4e2..d923e4127c87 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1062,7 +1062,7 @@ static int gmc_v10_0_hw_init(void *handle)
if (adev->umc.funcs && adev->umc.funcs->init_registers)
adev->umc.funcs->init_registers(adev);
  
-	return 0;

+   return amdgpu_gmc_allocate_sdma_access_gtt(adev);
  }
  
  /**

@@ -1082,6 +1082,8 @@ static int gmc_v10_0_hw_fini(void *handle)
  {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  
+	amdgpu_gmc_free_sdma_access_gtt(adev);

+
gmc_v10_0_gart_disable(adev);
  
  	if (amdgpu_sriov_vf(adev)) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 

[PATCH] drivers: Fix typo in comment

[tangmeng]

Replace disbale with disable and replace unavaibale with unavailable.

Signed-off-by: tangmeng 
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c  | 2 +-
 drivers/pcmcia/rsrc_nonstatic.c   | 2 +-
 drivers/usb/chipidea/udc.c| 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index aef9d059ae52..a642c04cf17d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -544,7 +544,7 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device 
*adev,
 {
int r;
 
-   /* trigger gpu-reset by hypervisor only if TDR disbaled */
+   /* trigger gpu-reset by hypervisor only if TDR disabled */
if (!amdgpu_gpu_recovery) {
/* see what event we get */
r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 29890d704cb4..b986946b3b10 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -996,7 +996,7 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
if (stat & LCDC_FRAME_DONE) {
tilcdc_crtc->frame_done = true;
wake_up(_crtc->frame_done_wq);
-   /* rev 1 lcdc appears to hang if irq is not disbaled here */
+   /* rev 1 lcdc appears to hang if irq is not disabled here */
if (priv->rev == 1)
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 LCDC_V1_FRAME_DONE_INT_ENA);
diff --git a/drivers/pcmcia/rsrc_nonstatic.c b/drivers/pcmcia/rsrc_nonstatic.c
index 6b6c578b5f92..ad1141fddb4c 100644
--- a/drivers/pcmcia/rsrc_nonstatic.c
+++ b/drivers/pcmcia/rsrc_nonstatic.c
@@ -394,7 +394,7 @@ static int do_validate_mem(struct pcmcia_socket *s,
  * do_mem_probe() checks a memory region for use by the PCMCIA subsystem.
  * To do so, the area is split up into sensible parts, and then passed
  * into the @validate() function. Only if @validate() and @fallback() fail,
- * the area is marked as unavaibale for use by the PCMCIA subsystem. The
+ * the area is marked as unavailable for use by the PCMCIA subsystem. The
  * function returns the size of the usable memory area.
  */
 static int do_mem_probe(struct pcmcia_socket *s, u_long base, u_long num,
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index f9ca5010f65b..dc6c96e04bcf 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -2152,7 +2152,7 @@ static void udc_id_switch_for_host(struct ci_hdrc *ci)
 {
/*
 * host doesn't care B_SESSION_VALID event
-* so clear and disbale BSV irq
+* so clear and disable BSV irq
 */
if (ci->is_otg)
hw_write_otgsc(ci, OTGSC_BSVIE | OTGSC_BSVIS, OTGSC_BSVIS);
-- 
2.20.1

Re: [PATCH] drivers: Fix typo in comment

[Greg KH]

On Thu, Jan 27, 2022 at 02:51:56PM +0800, tangmeng wrote:
> Replace disbale with disable and replace unavaibale with unavailable.
> 
> Signed-off-by: tangmeng 
> ---
>  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
>  drivers/gpu/drm/tilcdc/tilcdc_crtc.c  | 2 +-
>  drivers/pcmcia/rsrc_nonstatic.c   | 2 +-
>  drivers/usb/chipidea/udc.c| 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)

This needs to be broken up per-subsystem, thanks.

greg k-h

[PATCH] drm/amd/amdgpu: fix spelling mistake "disbale" -> "disable"

[tangmeng]

There is a spelling mistake. Fix it.

Signed-off-by: tangmeng 
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index aef9d059ae52..a642c04cf17d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -544,7 +544,7 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device 
*adev,
 {
int r;
 
-   /* trigger gpu-reset by hypervisor only if TDR disbaled */
+   /* trigger gpu-reset by hypervisor only if TDR disabled */
if (!amdgpu_gpu_recovery) {
/* see what event we get */
r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
-- 
2.20.1


)

[PATCH] drm/amdgpu: fix that issue that the number of the crtc of the 3250c is not correct

[RyanLin]

[Why]
External displays take priority over internal display when there are fewer 
display controllers than displays.

[How]
The root cause is because of that number of the crtc is not correct.
The number of the crtc on the 3250c is 3, but on the 3500c is 4.
On the source code, we can see that number of the crtc has been fixed at 4.
Needs to set the num_crtc to 3 for 3250c platform.

Signed-off-by: RyanLin 
Change-Id: I837df7101cc4849d2c3021fd529b4061edab4bb1
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 40c91b448f7d..dbeef7b57a9b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2738,9 +2738,15 @@ static int dm_early_init(void *handle)
break;
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
-   adev->mode_info.num_crtc = 4;
-   adev->mode_info.num_hpd = 4;
-   adev->mode_info.num_dig = 4;
+   if (adev->rev_id >= 8) { //chip_name = "raven2";
+   adev->mode_info.num_crtc = 3;
+   adev->mode_info.num_hpd = 3;
+   adev->mode_info.num_dig = 3;
+   } else {
+   adev->mode_info.num_crtc = 4;
+   adev->mode_info.num_hpd = 4;
+   adev->mode_info.num_dig = 4;
+   }
break;
 #endif
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
-- 
2.25.1

RE: [PATCH] drm/amdgpu: add safeguards for accessing mmhub CG registers

[Yu, Lang]

[Public]

>  Should we set *flags = 0 before we return?

That will clear other bit masks. Actually, the caller initialize flags to 0, we 
can just return.
Or  just *flags &= ~( AMD_CG_SUPPORT_XXX) before we return.

Regards,
Lang

From: Deucher, Alexander 
Sent: Thursday, January 27, 2022 4:27 AM
To: Yu, Lang ; amd-gfx@lists.freedesktop.org
Cc: Lazar, Lijo ; Huang, Ray 
Subject: Re: [PATCH] drm/amdgpu: add safeguards for accessing mmhub CG registers


[Public]

Should we set *flags = 0 before we return?

Alex


From: Yu, Lang mailto:lang...@amd.com>>
Sent: Wednesday, January 26, 2022 2:53 AM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; Lazar, Lijo 
mailto:lijo.la...@amd.com>>; Huang, Ray 
mailto:ray.hu...@amd.com>>; Yu, Lang 
mailto:lang...@amd.com>>
Subject: [PATCH] drm/amdgpu: add safeguards for accessing mmhub CG registers

We observed a gpu hang when querying mmhub CG status(i.e.,
cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
skillfish doesn't support any CG features.

Only allow asics which support CG features accessing related
registers. Will add similar safeguards for other IPs in the
furture.

Signed-off-by: Lang Yu mailto:lang...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 3 +++
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 3 +++
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 3 +++
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 3 +++
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 3 +++
 5 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 4c9f0c0f3116..1869e2019461 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -550,6 +550,9 @@ static void mmhub_v1_0_get_clockgating(struct amdgpu_device 
*adev, u32 *flags)
 {
 int data, data1;

+   if (!(adev->cg_flags & (AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_MC_LS)))
+   return;
+
 if (amdgpu_sriov_vf(adev))
 *flags = 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
index 3b901f941627..f7b9843b36e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
@@ -546,6 +546,9 @@ static void mmhub_v1_7_get_clockgating(struct amdgpu_device 
*adev, u32 *flags)
 {
 int data, data1;

+   if (!(adev->cg_flags & (AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_MC_LS)))
+   return;
+
 if (amdgpu_sriov_vf(adev))
 *flags = 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 3718ff610ab2..3f5f326379b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -686,6 +686,9 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device 
*adev, u32 *flags)
 {
 int data, data1;

+   if (!(adev->cg_flags & (AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_MC_LS)))
+   return;
+
 if (amdgpu_sriov_vf(adev))
 *flags = 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index 9e16da28505a..b23dd9ddfb5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -580,6 +580,9 @@ static void mmhub_v2_3_get_clockgating(struct amdgpu_device 
*adev, u32 *flags)
 {
 int data, data1, data2, data3;

+   if (!(adev->cg_flags & (AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_MC_LS)))
+   return;
+
 if (amdgpu_sriov_vf(adev))
 *flags = 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index 619106f7d23d..a2d5c8424e2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -651,6 +651,9 @@ static void mmhub_v9_4_get_clockgating(struct amdgpu_device 
*adev, u32 *flags)
 {
 int data, data1;

+   if (!(adev->cg_flags & (AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_MC_LS)))
+   return;
+
 if (amdgpu_sriov_vf(adev))
 *flags = 0;

--
2.25.1

Re: [PATCH] drm/amd/amdgpu: Add ip_discovery_text sysfs entry (v2)

[Christian König]

Am 25.01.22 um 19:18 schrieb Tom St Denis:

Newer hardware has a discovery table in hardware that the kernel will
rely on instead of header files for things like IP offsets.  This
sysfs entry adds a simple to parse table of IP instances and segment
offsets.

Produces output that looks like:

$ cat ip_discovery_text
ATHUB{0} v2.0.0: 0c00 02408c00
CLKA{0} v11.0.0: 00016c00 02401800
CLKA{1} v11.0.0: 00016e00 02401c00
CLKA{2} v11.0.0: 00017000 02402000
CLKA{3} v11.0.0: 00017200 02402400
CLKA{4} v11.0.0: 0001b000 0242d800
CLKB{0} v11.0.0: 00017e00 0240bc00
DBGU_NBIO{0} v3.0.0: 01c0 02409000
DBGU0{0} v3.0.0: 0180 02409800
DBGU1{0} v3.0.0: 01a0 02409c00
DF{0} v3.0.0: 7000 0240b800
DFX{0} v4.1.0: 0580 02409400
DFX_DAP{0} v2.0.0: 05a0 00b8 0240c400
DMU{0} v2.0.2: 0012 00c0 34c0 9000 02403c00
FUSE{0} v11.0.0: 00017400 02401400
GC{0} v10.1.10: 1260 a000 02402c00


Mhm, I'm also leaning more into Alex direction that this should probably 
better represented as directory structure in sysfs.


We could expose the IP discovery table as binary, but parsing it first 
and then not building proper sysfs structures is pretty clearly against 
the documented rules.


Regards,
Christian.



(v2): Use a macro for buffer size and fix alignment in amdgpu.h

Signed-off-by: Tom St Denis 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 79 ++-
  2 files changed, 79 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3bc76759c143..43caeb4bdc07 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1019,6 +1019,7 @@ struct amdgpu_device {
struct amdgpu_ip_block  ip_blocks[AMDGPU_MAX_IP_NUM];
uint32_tharvest_ip_mask;
int num_ip_blocks;
+   char*ip_discovery_text;
struct mutexmn_lock;
DECLARE_HASHTABLE(mn_hash, 7);
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

index 07623634fdc2..d036977dab8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -267,6 +267,19 @@ static void amdgpu_discovery_harvest_config_quirk(struct 
amdgpu_device *adev)
}
  }
  
+static ssize_t ip_discovery_text_show(struct device *dev,

+   struct device_attribute *attr, char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = drm_to_adev(ddev);
+
+   return sysfs_emit(buf, "%s", adev->ip_discovery_text);
+}
+
+static DEVICE_ATTR(ip_discovery_text, S_IRUGO,
+   ip_discovery_text_show, NULL);
+
+
  static int amdgpu_discovery_init(struct amdgpu_device *adev)
  {
struct table_info *info;
@@ -351,6 +364,11 @@ static int amdgpu_discovery_init(struct amdgpu_device 
*adev)
goto out;
}
  
+	// init sysfs for ip_discovery

+   r = sysfs_create_file(>dev->kobj, 
_attr_ip_discovery_text.attr);
+   if (r)
+   dev_err(adev->dev, "Could not create amdgpu device attr\n");
+
return 0;
  
  out:

@@ -363,7 +381,11 @@ static int amdgpu_discovery_init(struct amdgpu_device 
*adev)
  void amdgpu_discovery_fini(struct amdgpu_device *adev)
  {
kfree(adev->mman.discovery_bin);
+   kfree(adev->ip_discovery_text);
+   sysfs_remove_file(>dev->kobj, _attr_ip_discovery_text.attr);
+
adev->mman.discovery_bin = NULL;
+   adev->ip_discovery_text = NULL;
  }
  
  static int amdgpu_discovery_validate_ip(const struct ip *ip)

@@ -382,6 +404,22 @@ static int amdgpu_discovery_validate_ip(const struct ip 
*ip)
return 0;
  }
  
+#define IP_DISCOVERY_BLOCK_SIZE 4096

+
+static int add_string(char **dst, unsigned *size, char *src)
+{
+   if (strlen(src) + strlen(*dst) >= *size) {
+   void *tmp = krealloc(*dst, *size + IP_DISCOVERY_BLOCK_SIZE, 
GFP_KERNEL);
+   if (!tmp) {
+   return -1;
+   }
+   *dst = tmp;
+   *size = *size + IP_DISCOVERY_BLOCK_SIZE;
+   }
+   strcat(*dst, src);
+   return 0;
+}
+
  int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
  {
struct binary_header *bhdr;
@@ -396,6 +434,8 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device 
*adev)
int hw_ip;
int i, j, k;
int r;
+   unsigned txt_size = IP_DISCOVERY_BLOCK_SIZE;
+   char *linebuf;
  
  	r = amdgpu_discovery_init(adev);

if (r) {
@@ -410,6 +450,15 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device 
*adev)
  
  	DRM_DEBUG("number of dies: %d\n", num_dies);
  
+	adev->ip_discovery_text = kzalloc(txt_size, GFP_KERNEL);

+   linebuf = kzalloc(IP_DISCOVERY_BLOCK_SIZE, GFP_KERNEL);
+