[PATCH] x86/configs: Update defconfig with peer-to-peer configs

[Ramesh Errabolu]

- Update defconfig for PCI_P2PDMA
- Update defconfig for DMABUF_MOVE_NOTIFY
- Update defconfig for HSA_AMD_P2P
---

Notes:
Following procedure was applied:
make rock-dbg_defconfig
make menuconfig
Enable PCI_P2PDMA
Enable DMABUF_MOVE_NOTIFY
Enable HSA_AMD_P2P
make savedefconfig
cp defconfig rock-dbg_defconfig
commit changes

 arch/x86/configs/rock-dbg_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/configs/rock-dbg_defconfig 
b/arch/x86/configs/rock-dbg_defconfig
index 406fdfaceb55..0ad80a8c8eab 100644
--- a/arch/x86/configs/rock-dbg_defconfig
+++ b/arch/x86/configs/rock-dbg_defconfig
@@ -303,6 +303,7 @@ CONFIG_PCIEAER=y
 CONFIG_PCI_REALLOC_ENABLE_AUTO=y
 CONFIG_PCI_STUB=y
 CONFIG_PCI_IOV=y
+CONFIG_PCI_P2PDMA=y
 CONFIG_HOTPLUG_PCI=y
 CONFIG_RAPIDIO=y
 CONFIG_RAPIDIO_DMA_ENGINE=y
@@ -417,6 +418,7 @@ CONFIG_DRM_AMDGPU=m
 CONFIG_DRM_AMDGPU_SI=y
 CONFIG_DRM_AMDGPU_CIK=y
 CONFIG_HSA_AMD=y
+CONFIG_HSA_AMD_P2P=y
 CONFIG_DRM_AST=m
 CONFIG_FB=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
@@ -453,6 +455,7 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
 CONFIG_DMADEVICES=y
+CONFIG_DMABUF_MOVE_NOTIFY=y
 # CONFIG_X86_PLATFORM_DEVICES is not set
 CONFIG_AMD_IOMMU=y
 CONFIG_INTEL_IOMMU=y
-- 
2.35.1

[PATCH 1/2] drm/amdgpu: add the IP discovery IP versions for HW INFO data

[Alex Deucher]

Use the former pad element to store the IP versions from the
IP discovery table.  This allows userspace to get the IP
version from the kernel to better align with hardware IP
versions.

Proposed mesa patch:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411/diffs?commit_id=c8a63590dfd0d64e6e6a634dcfed993f135dd075

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 24 
 include/uapi/drm/amdgpu_drm.h   |  3 ++-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 4b44a4bc2fb3..7e03f3719d11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -473,6 +473,30 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 
result->hw_ip_version_major = adev->ip_blocks[i].version->major;
result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
+
+   if (adev->asic_type >= CHIP_VEGA10) {
+   switch (type) {
+   case AMD_IP_BLOCK_TYPE_GFX:
+   result->ip_discovery_version = 
adev->ip_versions[GC_HWIP][0];
+   break;
+   case AMD_IP_BLOCK_TYPE_SDMA:
+   result->ip_discovery_version = 
adev->ip_versions[SDMA0_HWIP][0];
+   break;
+   case AMD_IP_BLOCK_TYPE_UVD:
+   case AMD_IP_BLOCK_TYPE_VCN:
+   case AMD_IP_BLOCK_TYPE_JPEG:
+   result->ip_discovery_version = 
adev->ip_versions[UVD_HWIP][0];
+   break;
+   case AMD_IP_BLOCK_TYPE_VCE:
+   result->ip_discovery_version = 
adev->ip_versions[VCE_HWIP][0];
+   break;
+   default:
+   result->ip_discovery_version = 0;
+   break;
+   }
+   } else {
+   result->ip_discovery_version = 0;
+   }
result->capabilities_flags = 0;
result->available_rings = (1 << num_rings) - 1;
result->ib_start_alignment = ib_start_alignment;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 18d3246d636e..3a2674b4a2d9 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -1093,7 +1093,8 @@ struct drm_amdgpu_info_hw_ip {
__u32  ib_size_alignment;
/** Bitmask of available rings. Bit 0 means ring 0, etc. */
__u32  available_rings;
-   __u32  _pad;
+   /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
+   __u32  ip_discovery_version;
 };
 
 struct drm_amdgpu_info_num_handles {
-- 
2.35.3

[PATCH 2/2] drm/amdgpu: bump driver version for IP discovery info in HW INFO

[Alex Deucher]

So userspace knows when it is available.

Proposed mesa patch:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411/diffs?commit_id=c8a63590dfd0d64e6e6a634dcfed993f135dd075

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d6a5d0f424da..c716cea0675a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -100,10 +100,11 @@
  * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B 
&& 128B
  * - 3.45.0 - Add context ioctl stable pstate interface
  * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
- * * 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
+ * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
+ * - 3.48.0 - Add IP discovery version info to HW INFO
  */
 #define KMS_DRIVER_MAJOR   3
-#define KMS_DRIVER_MINOR   47
+#define KMS_DRIVER_MINOR   48
 #define KMS_DRIVER_PATCHLEVEL  0
 
 int amdgpu_vram_limit;
-- 
2.35.3

[PATCH 2/9] drm/amd/display: Add DCN314 IRQ services

[Alex Deucher]

From: Roman Li 

IRQ services to support DCN 3.1.4 interrupts.

Signed-off-by: Roman Li 
Signed-off-by: Alex Deucher 
---
 .../dc/irq/dcn314/irq_service_dcn314.c| 434 ++
 .../dc/irq/dcn314/irq_service_dcn314.h|  35 ++
 2 files changed, 469 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.h

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c 
b/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
new file mode 100644
index ..bea6f157cbb7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
@@ -0,0 +1,434 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/logger_interface.h"
+#include "../dce110/irq_service_dce110.h"
+
+
+#include "dcn/dcn_3_1_4_offset.h"
+#include "dcn/dcn_3_1_4_sh_mask.h"
+
+#include "irq_service_dcn314.h"
+
+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
+
+#define DCN_BASE__INST0_SEG2   0x34C0
+
+enum dc_irq_source to_dal_irq_source_dcn314(
+   struct irq_service *irq_service,
+   uint32_t src_id,
+   uint32_t ext_id)
+{
+   switch (src_id) {
+   case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK1;
+   case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK2;
+   case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK3;
+   case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK4;
+   case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK5;
+   case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK6;
+   case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC1_VLINE0;
+   case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC2_VLINE0;
+   case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC3_VLINE0;
+   case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC4_VLINE0;
+   case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC5_VLINE0;
+   case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC6_VLINE0;
+   case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP1;
+   case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP2;
+   case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP3;
+   case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP4;
+   case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP5;
+   case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP6;
+   case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE1;
+   case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE2;
+   case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE3;
+   case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE4;
+   case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE5;
+   case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE6;
+   case 

[PATCH 9/9] drm/amd/display: Enable DCN314 in DM

[Alex Deucher]

From: Roman Li 

Add support for DCN 3.1.4 in Display Manager

Signed-off-by: Roman Li 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c|  1 +
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index eb5efb4aa2ba..15dac00317ad 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -116,6 +116,8 @@ MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
+#define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
@@ -1941,6 +1943,10 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? 
DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
break;
+   case IP_VERSION(3, 1, 4):
+   dmub_asic = DMUB_ASIC_DCN314;
+   fw_name_dmub = FIRMWARE_DCN_314_DMUB;
+   break;
case IP_VERSION(3, 1, 5):
dmub_asic = DMUB_ASIC_DCN315;
fw_name_dmub = FIRMWARE_DCN_315_DMUB;
@@ -4222,6 +4228,7 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
case IP_VERSION(3, 0, 0):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
+   case IP_VERSION(3, 1, 4):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
case IP_VERSION(3, 2, 0):
@@ -4242,6 +4249,7 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
+   case IP_VERSION(3, 1, 4):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
case IP_VERSION(3, 2, 0):
@@ -4358,6 +4366,7 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
+   case IP_VERSION(3, 1, 4):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
case IP_VERSION(3, 2, 0):
@@ -4546,6 +4555,7 @@ static int dm_early_init(void *handle)
case IP_VERSION(2, 1, 0):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
+   case IP_VERSION(3, 1, 4):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
case IP_VERSION(3, 2, 0):
@@ -5296,6 +5306,7 @@ get_plane_modifiers(struct amdgpu_device *adev, unsigned 
int plane_type, uint64_
add_gfx10_1_modifiers(adev, mods, , );
break;
case AMDGPU_FAMILY_GC_11_0_0:
+   case AMDGPU_FAMILY_GC_11_0_2:
add_gfx11_modifiers(adev, mods, , );
break;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 71e6d98410fc..d76c8dfaf3f0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -667,6 +667,7 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct 
amdgpu_device *adev, struct
 
hdcp_work[i].hdcp.config.psp.handle = >psp;
if (dc->ctx->dce_version == DCN_VERSION_3_1 ||
+   dc->ctx->dce_version == DCN_VERSION_3_14 ||
dc->ctx->dce_version == DCN_VERSION_3_15 ||
dc->ctx->dce_version == DCN_VERSION_3_16)
hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
-- 
2.35.3

[PATCH 7/9] drm/amd/display: Enable DCN314 in DC

[Alex Deucher]

From: Roman Li 

Add support for DCN 3.1.4 in Display Core

Signed-off-by: Roman Li 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
 .../display/dc/bios/command_table_helper2.c   |   1 +
 .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |   9 +
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |  22 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |   4 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |   1 +
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   8 +
 .../drm/amd/display/dc/dce/dce_clock_source.h |   5 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |  17 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h  | 219 ++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c |  16 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  35 +++
 .../display/dc/dcn31/dcn31_dio_link_encoder.h |  28 +++
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |   3 +
 .../gpu/drm/amd/display/dc/gpio/hw_factory.c  |   1 +
 .../drm/amd/display/dc/gpio/hw_translate.c|   1 +
 drivers/gpu/drm/amd/display/dc/irq/Makefile   |  10 +
 17 files changed, 366 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
b/drivers/gpu/drm/amd/display/dc/Makefile
index dfe82bcdd17d..b6bacf6b25e1 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -60,6 +60,7 @@ DC_LIBS += dcn301
 DC_LIBS += dcn302
 DC_LIBS += dcn303
 DC_LIBS += dcn31
+DC_LIBS += dcn314
 DC_LIBS += dcn315
 DC_LIBS += dcn316
 DC_LIBS += dcn32
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index f22593bcb862..8538f13e01bf 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -75,6 +75,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
case DCN_VERSION_3_02:
case DCN_VERSION_3_03:
case DCN_VERSION_3_1:
+   case DCN_VERSION_3_14:
case DCN_VERSION_3_15:
case DCN_VERSION_3_16:
case DCN_VERSION_3_2:
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 7b505e1e9308..053084121db2 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -154,6 +154,15 @@ AMD_DAL_CLK_MGR_DCN31 = $(addprefix 
$(AMDDALPATH)/dc/clk_mgr/dcn31/,$(CLK_MGR_DC
 
 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN31)
 
+###
+# DCN314
+###
+CLK_MGR_DCN314 = dcn314_smu.o dcn314_clk_mgr.o
+
+AMD_DAL_CLK_MGR_DCN314 = $(addprefix 
$(AMDDALPATH)/dc/clk_mgr/dcn314/,$(CLK_MGR_DCN314))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN314)
+
 ###
 # DCN315
 ###
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 6972f99e9a9a..4c76091fd1f2 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -43,11 +43,11 @@
 #include "dcn30/dcn30_clk_mgr.h"
 #include "dcn301/vg_clk_mgr.h"
 #include "dcn31/dcn31_clk_mgr.h"
+#include "dcn314/dcn314_clk_mgr.h"
 #include "dcn315/dcn315_clk_mgr.h"
 #include "dcn316/dcn316_clk_mgr.h"
 #include "dcn32/dcn32_clk_mgr.h"
 
-
 int clk_mgr_helper_get_active_display_cnt(
struct dc *dc,
struct dc_state *context)
@@ -287,6 +287,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, 
struct pp_smu_funcs *p
return _mgr->base.base;
}
break;
+
case FAMILY_YELLOW_CARP: {
struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), 
GFP_KERNEL);
 
@@ -335,6 +336,20 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, 
struct pp_smu_funcs *p
return _mgr->base;
break;
}
+
+   case AMDGPU_FAMILY_GC_11_0_2: {
+   struct clk_mgr_dcn314 *clk_mgr = kzalloc(sizeof(*clk_mgr), 
GFP_KERNEL);
+
+   if (clk_mgr == NULL) {
+   BREAK_TO_DEBUGGER();
+   return NULL;
+   }
+
+   dcn314_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+   return _mgr->base.base;
+   }
+   break;
+
 #endif
default:
ASSERT(0); /* Unknown Asic */
@@ -381,6 +396,11 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
case AMDGPU_FAMILY_GC_11_0_0:
dcn32_clk_mgr_destroy(clk_mgr);
break;
+
+   case AMDGPU_FAMILY_GC_11_0_2:
+   dcn314_clk_mgr_destroy(clk_mgr);
+   break;
+
default:
   

[PATCH 3/9] drm/amd/display: Add DCN314 clock manager

[Alex Deucher]

From: Roman Li 

Clock and SMU interfaces for DCN 3.1.4

Signed-off-by: Roman Li 
Signed-off-by: Alex Deucher 
---
 .../dc/clk_mgr/dcn314/dcn314_clk_mgr.c| 751 ++
 .../dc/clk_mgr/dcn314/dcn314_clk_mgr.h|  57 ++
 .../display/dc/clk_mgr/dcn314/dcn314_smu.c| 391 +
 .../display/dc/clk_mgr/dcn314/dcn314_smu.h|  79 ++
 4 files changed, 1278 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
new file mode 100644
index ..df6dd8465272
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -0,0 +1,751 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+
+#include "dcn314_clk_mgr.h"
+
+#include "dccg.h"
+#include "clk_mgr_internal.h"
+
+// For dce12_get_dp_ref_freq_khz
+#include "dce100/dce_clk_mgr.h"
+
+// For dcn20_update_clocks_update_dpp_dto
+#include "dcn20/dcn20_clk_mgr.h"
+
+
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dm_helpers.h"
+
+/* TODO: remove this include once we ported over remaining clk mgr functions*/
+#include "dcn30/dcn30_clk_mgr.h"
+#include "dcn31/dcn31_clk_mgr.h"
+
+#include "dc_dmub_srv.h"
+#include "dc_link_dp.h"
+#include "dcn314_smu.h"
+
+#define MAX_INSTANCE7
+#define MAX_SEGMENT 8
+
+struct IP_BASE_INSTANCE {
+   unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE {
+   struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 
0, 0, 0, 0 } },
+   { { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 
0, 0 } },
+   { { 0x00017000, 0x02402000, 0, 0, 0, 0, 
0, 0 } },
+   { { 0x00017200, 0x02402400, 0, 0, 0, 0, 
0, 0 } },
+   { { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 
0, 0 } },
+   { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 
0, 0 } },
+   { { 0x0001B400, 0x0242E000, 0, 0, 0, 0, 
0, 0 } } } };
+
+#define regCLK1_CLK_PLL_REQ0x0237
+#define regCLK1_CLK_PLL_REQ_BASE_IDX   0
+
+#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT0x0
+#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT   0xc
+#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT   0x10
+#define CLK1_CLK_PLL_REQ__FbMult_int_MASK  0x01FFL
+#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0xF000L
+#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xL
+
+#define REG(reg_name) \
+   (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## 
reg_name)
+
+#define TO_CLK_MGR_DCN314(clk_mgr)\
+   container_of(clk_mgr, struct clk_mgr_dcn314, base)
+
+static int dcn314_get_active_display_cnt_wa(
+   struct dc *dc,
+   struct dc_state *context)
+{
+   int i, display_count;
+   bool tmds_present = false;
+
+   display_count = 0;
+   for (i = 0; i < context->stream_count; i++) {
+   const struct dc_stream_state *stream = context->streams[i];
+
+   if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
+   stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
+   stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
+   tmds_present = true;
+   }

[PATCH 8/9] drm/amd/display: Add DMUB support for DCN314

[Alex Deucher]

From: Roman Li 

Initialize DMUB for DCN 3.1.4.
Use same funcs as DCN31.

Signed-off-by: Roman Li 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 4c6a624f04a7..4a122925c3ae 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -223,6 +223,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum 
dmub_asic asic)
 
case DMUB_ASIC_DCN31:
case DMUB_ASIC_DCN31B:
+   case DMUB_ASIC_DCN314:
case DMUB_ASIC_DCN315:
case DMUB_ASIC_DCN316:
if (asic == DMUB_ASIC_DCN315)
-- 
2.35.3

[PATCH 6/9] drm/amd/display: Add DCN314 version identifiers

[Alex Deucher]

From: Roman Li 

DCN 3.1.4 version and family ids

Signed-off-by: Roman Li 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   | 1 +
 drivers/gpu/drm/amd/display/include/dal_asic_id.h | 1 +
 drivers/gpu/drm/amd/display/include/dal_types.h   | 1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h 
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 04049dc5d9df..ced176d17bae 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -98,6 +98,7 @@ enum dmub_asic {
DMUB_ASIC_DCN303,
DMUB_ASIC_DCN31,
DMUB_ASIC_DCN31B,
+   DMUB_ASIC_DCN314,
DMUB_ASIC_DCN315,
DMUB_ASIC_DCN316,
DMUB_ASIC_DCN32,
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h 
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index a0dffe30b394..ab06c7fc7452 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -244,6 +244,7 @@ enum {
 #define ASICREV_IS_GC_10_3_7(eChipRev) ((eChipRev >= GC_10_3_7_A0) && 
(eChipRev < GC_10_3_7_UNKNOWN))
 
 #define AMDGPU_FAMILY_GC_11_0_0 145
+#define AMDGPU_FAMILY_GC_11_0_2 148
 #define GC_11_0_0_A0 0x1
 #define GC_11_0_2_A0 0x10
 #define GC_11_UNKNOWN 0xFF
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h 
b/drivers/gpu/drm/amd/display/include/dal_types.h
index 775c640fc820..d2427cf1155f 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -57,6 +57,7 @@ enum dce_version {
DCN_VERSION_3_02,
DCN_VERSION_3_03,
DCN_VERSION_3_1,
+   DCN_VERSION_3_14,
DCN_VERSION_3_15,
DCN_VERSION_3_16,
DCN_VERSION_3_2,
-- 
2.35.3

[PATCH 0/9] Add DCN 3.1.4 Support

[Alex Deucher]

This patch set adds support for DCN 3.1.4, a display block
on AMD GPUs.  Patch 1 adds new DCN registers and is too
big for the mailing list.

Roman Li (9):
  drm/amdgpu: Add reg headers for DCN314
  drm/amd/display: Add DCN314 IRQ services
  drm/amd/display: Add DCN314 clock manager
  drm/amd/display: Add DCN314 DC resources
  drm/amd/display: Add DCN314 DML calculation support
  drm/amd/display: Add DCN314 version identifiers
  drm/amd/display: Enable DCN314 in DC
  drm/amd/display: Add DMUB support for DCN314
  drm/amd/display: Enable DCN314 in DM

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |11 +
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 1 +
 drivers/gpu/drm/amd/display/dc/Makefile   | 1 +
 .../display/dc/bios/command_table_helper2.c   | 1 +
 .../gpu/drm/amd/display/dc/clk_mgr/Makefile   | 9 +
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |22 +-
 .../dc/clk_mgr/dcn314/dcn314_clk_mgr.c|   751 +
 .../dc/clk_mgr/dcn314/dcn314_clk_mgr.h|57 +
 .../display/dc/clk_mgr/dcn314/dcn314_smu.c|   391 +
 .../display/dc/clk_mgr/dcn314/dcn314_smu.h|79 +
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 4 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 +
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 8 +
 .../drm/amd/display/dc/dce/dce_clock_source.h | 5 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |17 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h  |   219 +
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c |16 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |35 +
 .../display/dc/dcn31/dcn31_dio_link_encoder.h |28 +
 .../drm/amd/display/dc/dcn31/dcn31_resource.c | 3 +
 .../gpu/drm/amd/display/dc/dcn314/Makefile|43 +
 .../drm/amd/display/dc/dcn314/dcn314_dccg.c   |   265 +
 .../drm/amd/display/dc/dcn314/dcn314_dccg.h   |   158 +
 .../dc/dcn314/dcn314_dio_stream_encoder.c |   448 +
 .../dc/dcn314/dcn314_dio_stream_encoder.h |   311 +
 .../drm/amd/display/dc/dcn314/dcn314_hwseq.c  |   341 +
 .../drm/amd/display/dc/dcn314/dcn314_hwseq.h  |40 +
 .../drm/amd/display/dc/dcn314/dcn314_init.c   |   158 +
 .../drm/amd/display/dc/dcn314/dcn314_init.h   |34 +
 .../drm/amd/display/dc/dcn314/dcn314_optc.c   |   240 +
 .../drm/amd/display/dc/dcn314/dcn314_optc.h   |   255 +
 .../amd/display/dc/dcn314/dcn314_resource.c   |  2357 +
 .../amd/display/dc/dcn314/dcn314_resource.h   |43 +
 .../dc/dml/dcn314/display_mode_vba_314.c  |  7420 ++
 .../dc/dml/dcn314/display_mode_vba_314.h  |44 +
 .../dc/dml/dcn314/display_rq_dlg_calc_314.c   |  1733 +
 .../dc/dml/dcn314/display_rq_dlg_calc_314.h   |70 +
 .../gpu/drm/amd/display/dc/gpio/hw_factory.c  | 1 +
 .../drm/amd/display/dc/gpio/hw_translate.c| 1 +
 drivers/gpu/drm/amd/display/dc/irq/Makefile   |10 +
 .../dc/irq/dcn314/irq_service_dcn314.c|   434 +
 .../dc/irq/dcn314/irq_service_dcn314.h|35 +
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   | 1 +
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 1 +
 .../gpu/drm/amd/display/include/dal_asic_id.h | 1 +
 .../gpu/drm/amd/display/include/dal_types.h   | 1 +
 .../include/asic_reg/dcn/dcn_3_1_4_offset.h   | 15245 
 .../include/asic_reg/dcn/dcn_3_1_4_sh_mask.h  | 61832 
 .../include/asic_reg/dpcs/dpcs_3_1_4_offset.h |  7215 ++
 .../asic_reg/dpcs/dpcs_3_1_4_sh_mask.h| 55194 ++
 50 files changed, 155575 insertions(+), 15 deletions(-)
 create mode 100644 
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h
 create mode 100644 
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.h
 create mode 100644 
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.h
 create mode 100644 

Re: [PATCH v8 02/15] mm: move page zone helpers into new header-specific file

[Felix Kuehling]

On 2022-07-08 07:28, David Hildenbrand wrote:

On 07.07.22 21:03, Alex Sierra wrote:

[WHY]
Have a cleaner way to expose all page zone helpers in one header

What exactly is a "page zone"? Do you mean a buddy zone as in
include/linux/mmzone.h ?

Zone as in ZONE_DEVICE. Maybe we could extend mmzone.h instead of 
creating page_zone.h? That should work as long as it's OK to include 
mmzone.h in memremap.h.


Regards,
  Felix

Re: [PATCH 1/1] drm/amdkfd: Process notifier release callback don't take mutex

[Felix Kuehling]

I think this could also be fixed by not taking the process_info lock in 
svm_range_restore_work and svm_range_set_attr. I'm not even sure why 
we're taking this lock in the SVM code. I think that was copied from the 
restore workers in amdgpu_amdkfd_gpuvm.c because there it's used to 
protect the BO lists. But I think in the case of SVM, the equivalent 
lists are protected by the svms->lock.


Regards,
  Felix


On 2022-07-07 17:23, Philip Yang wrote:

Move process queues cleanup to deferred work kfd_process_wq_release, to
avoid potential deadlock circular locking warning:

  WARNING: possible circular locking dependency detected
the existing dependency chain (in reverse order) is:
   -> #2
 ((work_completion)(>deferred_list_work)){+.+.}-{0:0}:
 __flush_work+0x343/0x4a0
 svm_range_list_lock_and_flush_work+0x39/0xc0
 svm_range_set_attr+0xe8/0x1080 [amdgpu]
 kfd_ioctl+0x19b/0x600 [amdgpu]
 __x64_sys_ioctl+0x81/0xb0
 do_syscall_64+0x34/0x80
 entry_SYSCALL_64_after_hwframe+0x44/0xae

   -> #1 (>lock#2){+.+.}-{3:3}:
 __mutex_lock+0xa4/0x940
 amdgpu_amdkfd_gpuvm_acquire_process_vm+0x2e3/0x590
 kfd_process_device_init_vm+0x61/0x200 [amdgpu]
 kfd_ioctl_acquire_vm+0x83/0xb0 [amdgpu]
 kfd_ioctl+0x19b/0x600 [amdgpu]
 __x64_sys_ioctl+0x81/0xb0
 do_syscall_64+0x34/0x80
entry_SYSCALL_64_after_hwframe+0x44/0xae

   -> #0 (>mutex){+.+.}-{3:3}:
 __lock_acquire+0x1365/0x23d0
 lock_acquire+0xc9/0x2e0
 __mutex_lock+0xa4/0x940
 kfd_process_notifier_release+0x96/0xe0 [amdgpu]
 __mmu_notifier_release+0x94/0x210
 exit_mmap+0x35/0x1f0
 mmput+0x63/0x120
 svm_range_deferred_list_work+0x177/0x2c0 [amdgpu]
 process_one_work+0x2a4/0x600
 worker_thread+0x39/0x3e0
 kthread+0x16d/0x1a0

   Possible unsafe locking scenario:

   CPU0CPU1
 
lock((work_completion)(>deferred_list_work));
 lock(>lock#2);
  lock((work_completion)(>deferred_list_work));
lock(>mutex);

Signed-off-by: Philip Yang 
---
  drivers/gpu/drm/amd/amdkfd/kfd_process.c | 21 +
  1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index fc38a4d81420..3c9cf9bdb63f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1115,6 +1115,15 @@ static void kfd_process_wq_release(struct work_struct 
*work)
struct kfd_process *p = container_of(work, struct kfd_process,
 release_work);
  
+	kfd_process_dequeue_from_all_devices(p);

+   pqm_uninit(>pqm);
+
+   /* Signal the eviction fence after user mode queues are
+* destroyed. This allows any BOs to be freed without
+* triggering pointless evictions or waiting for fences.
+*/
+   dma_fence_signal(p->ef);
+
kfd_process_remove_sysfs(p);
kfd_iommu_unbind_process(p);
  
@@ -1179,20 +1188,8 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn,

cancel_delayed_work_sync(>eviction_work);
cancel_delayed_work_sync(>restore_work);
  
-	mutex_lock(>mutex);

-
-   kfd_process_dequeue_from_all_devices(p);
-   pqm_uninit(>pqm);
-
/* Indicate to other users that MM is no longer valid */
p->mm = NULL;
-   /* Signal the eviction fence after user mode queues are
-* destroyed. This allows any BOs to be freed without
-* triggering pointless evictions or waiting for fences.
-*/
-   dma_fence_signal(p->ef);
-
-   mutex_unlock(>mutex);
  
  	mmu_notifier_put(>mmu_notifier);

  }

Re: [PATCH] drm/amdgpu: Remove one duplicated ef removal

[Felix Kuehling]

On 2022-07-07 21:53, xinhui pan wrote:

That has been done in BO release notify.

Signed-off-by: xinhui pan 


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 -
  1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 0f9811d02f61..49536fa8d269 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1583,11 +1583,6 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device 
*adev,
if (!process_info)
return;
  
-	/* Release eviction fence from PD */

-   amdgpu_bo_reserve(pd, false);
-   amdgpu_bo_fence(pd, NULL, false);
-   amdgpu_bo_unreserve(pd);
-
/* Update process info */
mutex_lock(_info->lock);
process_info->n_vms--;

[PATCH] drm/amd/display: fix unnecessary pipe split playing NV12 1080p MPO video

[Aurabindo Pillai]

From: Samson Tam 

[Why]
When playing NV12 1080p MPO video, it is pipe splitting so
we see two pipes in fullscreen and four pipes in windowed
mode. Pipe split is happening because we are setting
MaximumMPCCombine = 1

[How]
Algorithm for MaximumMPCCombine has extra conditions we do
not need.  Use DCN31 algorithm instead

Signed-off-by: Samson Tam 
---
 .../dc/dml/dcn32/display_mode_vba_32.c| 31 ++-
 1 file changed, 3 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 04b13e765a52..c6c3a9e6731a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -3733,35 +3733,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
mode_lib->vba.ModeIsSupported = 
mode_lib->vba.ModeSupport[i][0] == true
|| mode_lib->vba.ModeSupport[i][1] == 
true;
 
-   if ((mode_lib->vba.ModeSupport[i][0] == false && 
mode_lib->vba.ModeSupport[i][1] == true)
-   || MPCCombineMethodAsPossible
-   || 
(MPCCombineMethodAsNeededForPStateChangeAndVoltage
-   && mode_lib->vba.DRAMClockChangeRequirementFinal
-   && 
(((mode_lib->vba.DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vactive
-   || mode_lib->vba.DRAMClockChangeSupport[i][1] ==
-   
dm_dram_clock_change_vactive_w_mall_full_frame
-   || mode_lib->vba.DRAMClockChangeSupport[i][1] ==
-   
dm_dram_clock_change_vactive_w_mall_sub_vp)
-   && !(mode_lib->vba.DRAMClockChangeSupport[i][0] 
== dm_dram_clock_change_vactive
-   || mode_lib->vba.DRAMClockChangeSupport[i][0] ==
-   
dm_dram_clock_change_vactive_w_mall_full_frame
-   || mode_lib->vba.DRAMClockChangeSupport[i][0] ==
-   
dm_dram_clock_change_vactive_w_mall_sub_vp))
-   || ((mode_lib->vba.DRAMClockChangeSupport[i][1] 
== dm_dram_clock_change_vblank
-   || mode_lib->vba.DRAMClockChangeSupport[i][1] ==
-   
dm_dram_clock_change_vblank_w_mall_full_frame
-   || mode_lib->vba.DRAMClockChangeSupport[i][1] ==
-   
dm_dram_clock_change_vblank_w_mall_sub_vp)
-   && mode_lib->vba.DRAMClockChangeSupport[i][0] 
== dm_dram_clock_change_unsupported)))
-   || 
(MPCCombineMethodAsNeededForPStateChangeAndVoltage &&
-   mode_lib->vba.FCLKChangeRequirementFinal
-   && ((mode_lib->vba.FCLKChangeSupport[i][1] == 
dm_fclock_change_vactive
-   && mode_lib->vba.FCLKChangeSupport[i][0] != 
dm_fclock_change_vactive)
-   || (mode_lib->vba.FCLKChangeSupport[i][1] == 
dm_fclock_change_vblank
-   && mode_lib->vba.FCLKChangeSupport[i][0] == 
dm_fclock_change_unsupported {
-   MaximumMPCCombine = 1;
-   } else {
+   if (mode_lib->vba.ModeSupport[i][0] == true) {
MaximumMPCCombine = 0;
+   } else {
+   MaximumMPCCombine = 1;
}
}
}
-- 
2.37.0

[PATCH 12/21] drm/amd/display: 3.2.193

[Solomon Chiu]

From: Aric Cyr 

Acked-by: Solomon Chiu 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index a0812849794e..1dca016b5782 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.192"
+#define DC_VER "3.2.193"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.1

[PATCH 11/21] drm/amd/display: update DML1 logic for unbounded req handling

[Solomon Chiu]

From: "Lei, Jun" 

[why]
Unbounded request logic in resource/DML has some issues where
unbounded request is being enabled incorrectly.  SW today enables
unbounded request unconditionally in hardware, on the assumption
that HW can always support it in single pipe scenarios.

This worked until now because the same assumption is made in DML.
A new DML update is needed to fix a bug, where there are single
pipe scenarios where unbounded cannot be enabled, and this change
in DML needs to be ported in, and dcn32 resource logic fixed.

[how]
First, dcn32_resource should program unbounded req in HW according
to unbounded req enablement output from DML, as opposed to DML input

Second, port in DML1 update which disables unbounded req in some
scenarios to fix an issue with poor stutter performance

Reviewed-by: Nevenko Stupar 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Solomon Chiu 
Signed-off-by: Jun Lei 
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 9 +
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 9 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 95edca4c085b..607172542242 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -110,6 +110,7 @@ dml_get_attr_func(return_bw, mode_lib->vba.ReturnBW);
 dml_get_attr_func(tcalc, mode_lib->vba.TCalc);
 dml_get_attr_func(fraction_of_urgent_bandwidth, 
mode_lib->vba.FractionOfUrgentBandwidth);
 dml_get_attr_func(fraction_of_urgent_bandwidth_imm_flip, 
mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip);
+
 dml_get_attr_func(cstate_max_cap_mode, 
mode_lib->vba.DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
 dml_get_attr_func(comp_buffer_size_kbytes, 
mode_lib->vba.CompressedBufferSizeInkByte);
 dml_get_attr_func(pixel_chunk_size_in_kbyte, 
mode_lib->vba.PixelChunkSizeInKByte);
@@ -120,6 +121,11 @@ dml_get_attr_func(min_meta_chunk_size_in_byte, 
mode_lib->vba.MinMetaChunkSizeByt
 dml_get_attr_func(fclk_watermark, mode_lib->vba.Watermark.FCLKChangeWatermark);
 dml_get_attr_func(usr_retraining_watermark, 
mode_lib->vba.Watermark.USRRetrainingWatermark);
 
+dml_get_attr_func(comp_buffer_reserved_space_kbytes, 
mode_lib->vba.CompBufReservedSpaceKBytes);
+dml_get_attr_func(comp_buffer_reserved_space_64bytes, 
mode_lib->vba.CompBufReservedSpace64B);
+dml_get_attr_func(comp_buffer_reserved_space_zs, 
mode_lib->vba.CompBufReservedSpaceZs);
+dml_get_attr_func(unbounded_request_enabled, 
mode_lib->vba.UnboundedRequestEnabled);
+
 #define dml_get_pipe_attr_func(attr, var)  double get_##attr(struct 
display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned 
int num_pipes, unsigned int which_pipe) \
 {\
unsigned int which_plane; \
@@ -842,6 +848,9 @@ static void fetch_pipe_params(struct display_mode_lib 
*mode_lib)
 
mode_lib->vba.SynchronizeTimingsFinal = 
pipes[0].pipe.dest.synchronize_timings;
mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal = false;
+
+   mode_lib->vba.DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment 
= 0;
+
mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting;
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
if (pipes[k].pipe.src.unbounded_req_mode == 0)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 10ff536ef2a4..acb9434fb955 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -67,6 +67,10 @@ dml_get_attr_decl(min_pixel_chunk_size_in_byte);
 dml_get_attr_decl(min_meta_chunk_size_in_byte);
 dml_get_attr_decl(fclk_watermark);
 dml_get_attr_decl(usr_retraining_watermark);
+dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
+dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
+dml_get_attr_decl(comp_buffer_reserved_space_zs);
+dml_get_attr_decl(unbounded_request_enabled);
 
 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib 
*mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, 
unsigned int which_pipe)
 
@@ -470,6 +474,7 @@ struct vba_vars_st {
bool XFCEnabled[DC__NUM_DPP__MAX];
bool ScalerEnabled[DC__NUM_DPP__MAX];
unsigned int VBlankNom[DC__NUM_DPP__MAX];
+   bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment;
 
// Intermediates/Informational
bool ImmediateFlipSupport;
@@ -513,6 +518,10 @@ struct vba_vars_st {
double StutterPeriodBestCase;
Watermarks  Watermark;
bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
+   unsigned int CompBufReservedSpaceKBytes;
+   unsigned int CompBufReservedSpace64B;
+   unsigned int CompBufReservedSpaceZs;
+   bool CompBufReservedSpaceNeedAdjustment;
 
// These are the clocks calcuated by 

[PATCH 10/21] drm/amd/display: Reduce SCDC Status Flags Definition

[Solomon Chiu]

From: Chris Park 

[Why]
Status flags definition is reduced to read
less bytes in SCDC transaction for status update.

[How]
Reduce definition of reserved bytes from 3 to 1
for status update.

Reviewed-by: Charlene Liu 
Acked-by: Solomon Chiu 
Signed-off-by: Chris Park 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index b13a516ba0f2..d01d2eeed813 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -93,16 +93,13 @@ union hdmi_scdc_update_read_data {
 };
 
 union hdmi_scdc_status_flags_data {
-   uint8_t byte[2];
+   uint8_t byte;
struct {
uint8_t CLOCK_DETECTED:1;
uint8_t CH0_LOCKED:1;
uint8_t CH1_LOCKED:1;
uint8_t CH2_LOCKED:1;
uint8_t RESERVED:4;
-   uint8_t RESERVED2:8;
-   uint8_t RESERVED3:8;
-
} fields;
 };
 
@@ -770,7 +767,7 @@ void dal_ddc_service_read_scdc_data(struct ddc_service 
*ddc_service)
sizeof(scramble_status));
offset = HDMI_SCDC_STATUS_FLAGS;
dal_ddc_service_query_ddc_data(ddc_service, slave_address,
-   , sizeof(offset), status_data.byte,
+   , sizeof(offset), _data.byte,
sizeof(status_data.byte));
}
 }
-- 
2.25.1

[PATCH 09/21] drm/amd/display: make enable link independent from verified link caps

[Solomon Chiu]

From: Wenjing Liu 

[why]
Ideally link capability should be independent from the link
configuration that we decide to use in enable link. Otherwise if link
capability is changed after validation has completed, we could end up
enabling a link configuration with invalid configuration. This would
lead to over link bandwidth subscription or in the extreme case
causes us to enable HPO link to a DIO stream.

[how]
Add a new struct in pipe ctx called link config. This structure will
contain link configuration to enable a link. It will be populated
during map pool resources after we validate link bandwidth. Remove
the reference of verified link cap during enable link process and
use link config in pipe ctx instead.

Reviewed-by: George Shen 
Acked-by: Solomon Chiu 
Signed-off-by: Wenjing Liu 
---
 .../gpu/drm/amd/display/dc/core/dc_debug.c|  2 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 27 +--
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 45 +++
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 10 ++---
 .../gpu/drm/amd/display/dc/inc/core_status.h  |  1 +
 .../gpu/drm/amd/display/dc/inc/core_types.h   | 10 +
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  2 +-
 7 files changed, 44 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 283957dbdf93..69f1c2b89a57 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -424,6 +424,8 @@ char *dc_status_to_str(enum dc_status status)
return "No link encoder resource";
case DC_FAIL_DP_PAYLOAD_ALLOCATION:
return "Fail dp payload allocation";
+   case DC_FAIL_DP_LINK_BANDWIDTH:
+   return "Insufficient DP link bandwidth";
case DC_ERROR_UNEXPECTED:
return "Unexpected error";
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index dbdeda60e9e2..65269cd8cb78 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1969,7 +1969,8 @@ static enum dc_status enable_link_dp(struct dc_state 
*state,
enum dc_status status;
bool skip_video_pattern;
struct dc_link *link = stream->link;
-   struct dc_link_settings link_settings = {0};
+   const struct dc_link_settings *link_settings =
+   _ctx->link_config.dp_link_settings;
bool fec_enable;
int i;
bool apply_seamless_boot_optimization = false;
@@ -1986,9 +1987,6 @@ static enum dc_status enable_link_dp(struct dc_state 
*state,
}
}
 
-   /* get link settings for video mode timing */
-   decide_link_settings(stream, _settings);
-
/* Train with fallback when enabling DPIA link. Conventional links are
 * trained with fallback during sink detection.
 */
@@ -1999,7 +1997,7 @@ static enum dc_status enable_link_dp(struct dc_state 
*state,
 * Temporary w/a to get DP2.0 link rates to work with SST.
 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is 
resolved.
 */
-   if (dp_get_link_encoding_format(_settings) == 
DP_128b_132b_ENCODING &&
+   if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING 
&&
pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
link->dc->debug.set_mst_en_for_sst) {
dp_enable_mst_on_sink(link, true);
@@ -2012,11 +2010,11 @@ static enum dc_status enable_link_dp(struct dc_state 
*state,
link->dc->hwss.edp_wait_for_hpd_ready(link, true);
}
 
-   if (dp_get_link_encoding_format(_settings) == 
DP_128b_132b_ENCODING) {
+   if (dp_get_link_encoding_format(link_settings) == 
DP_128b_132b_ENCODING) {
/* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
} else {
pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
-   link_settings.link_rate * 
LINK_RATE_REF_FREQ_IN_KHZ;
+   link_settings->link_rate * 
LINK_RATE_REF_FREQ_IN_KHZ;
if (state->clk_mgr && !apply_seamless_boot_optimization)
state->clk_mgr->funcs->update_clocks(state->clk_mgr,
state, false);
@@ -2032,16 +2030,15 @@ static enum dc_status enable_link_dp(struct dc_state 
*state,
 
skip_video_pattern = true;
 
-   if (link_settings.link_rate == LINK_RATE_LOW)
+   if (link_settings->link_rate == LINK_RATE_LOW)
skip_video_pattern = false;
 
-   if (perform_link_training_with_retries(_settings,
+   if (perform_link_training_with_retries(link_settings,
   skip_video_pattern,
   

[PATCH 08/21] drm/amd/display: Fix black screen when disabling Freesync in OSD

[Solomon Chiu]

From: Ilya Bakoulin 

[Why]
Black screen encountered when disabling Freesync through OSD on some
displays.

[How]
Set the should_disable flag when new top pipe has no plane state to
ensure that pipes get cleaned up.

Reviewed-by: Chris Park 
Acked-by: Solomon Chiu 
Signed-off-by: Ilya Bakoulin 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a448696ee8f2..6b37c653f45e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1085,6 +1085,16 @@ static void disable_dangling_plane(struct dc *dc, struct 
dc_state *context)
dc->current_state->stream_count != 
context->stream_count)
should_disable = true;
 
+   if (old_stream && 
!dc->current_state->res_ctx.pipe_ctx[i].top_pipe) {
+   struct pipe_ctx *old_pipe, *new_pipe;
+
+   old_pipe = >current_state->res_ctx.pipe_ctx[i];
+   new_pipe = >res_ctx.pipe_ctx[i];
+
+   if (old_pipe->plane_state && !new_pipe->plane_state)
+   should_disable = true;
+   }
+
if (should_disable && old_stream) {
dc_rem_all_planes_for_stream(dc, old_stream, 
dangling_context);
disable_all_writeback_pipes_for_stream(dc, old_stream, 
dangling_context);
-- 
2.25.1

[PATCH 05/21] drm/amd/display: Fix windowed MPO video with ODM combine for DCN32

[Solomon Chiu]

From: Samson Tam 

[Why]
In single display configuration, windowed MPO does not work
 with ODM combine.

[How]
For ODM + MPO window on one half of ODM, only 3 pipes should
 be allocated and scaling parameters adjusted to handle this case.
 Otherwise, we use 4 pipes.
Move copy_surface_update_to_plane() before dc_add_plane_to_context()
 so that it gets the updated rect information when setting up
 the pipes.
Add dc_check_boundary_crossing_for_windowed_mpo_with_odm() to force
 a full update when we cross a boundary requiring us to reconfigure
 the number of pipes between 3 and 4 pipes.
Set config.enable_windowed_mpo_odm to true when we have the
 debug.enable_single_display_2to1_odm_policy set to true.
Don't fail validating ODM with windowed MPO if
 config.enable_windowed_mpo_odm is true.

Reviewed-by: Aric Cyr 
Acked-by: Solomon Chiu 
Signed-off-by: Samson Tam 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  94 ++
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 115 ++
 2 files changed, 188 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e13bf66f70e0..a448696ee8f2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2415,6 +2415,96 @@ static enum surface_update_type 
check_update_surfaces_for_stream(
return overall_type;
 }
 
+static bool dc_check_is_fullscreen_video(struct rect src, struct rect 
clip_rect)
+{
+   int view_height, view_width, clip_x, clip_y, clip_width, clip_height;
+
+   view_height = src.height;
+   view_width = src.width;
+
+   clip_x = clip_rect.x;
+   clip_y = clip_rect.y;
+
+   clip_width = clip_rect.width;
+   clip_height = clip_rect.height;
+
+   /* check for centered video accounting for off by 1 scaling truncation 
*/
+   if ((view_height - clip_y - clip_height <= clip_y + 1) &&
+   (view_width - clip_x - clip_width <= clip_x + 1) &&
+   (view_height - clip_y - clip_height >= clip_y - 1) &&
+   (view_width - clip_x - clip_width >= clip_x - 1)) {
+
+   /* when OS scales up/down to letter box, it may end up
+* with few blank pixels on the border due to truncating.
+* Add offset margin to account for this
+*/
+   if (clip_x <= 4 || clip_y <= 4)
+   return true;
+   }
+
+   return false;
+}
+
+static enum surface_update_type 
check_boundary_crossing_for_windowed_mpo_with_odm(struct dc *dc,
+   struct dc_surface_update *srf_updates, int surface_count,
+   enum surface_update_type update_type)
+{
+   enum surface_update_type new_update_type = update_type;
+   int i, j;
+   struct pipe_ctx *pipe = NULL;
+   struct dc_stream_state *stream;
+
+   /* Check that we are in windowed MPO with ODM
+* - look for MPO pipe by scanning pipes for first pipe matching
+*   surface that has moved ( position change )
+* - MPO pipe will have top pipe
+* - check that top pipe has ODM pointer
+*/
+   if ((surface_count > 1) && dc->config.enable_windowed_mpo_odm) {
+   for (i = 0; i < surface_count; i++) {
+   if (srf_updates[i].surface && 
srf_updates[i].scaling_info
+   && 
srf_updates[i].surface->update_flags.bits.position_change) {
+
+   for (j = 0; j < dc->res_pool->pipe_count; j++) {
+   if (srf_updates[i].surface == 
dc->current_state->res_ctx.pipe_ctx[j].plane_state) {
+   pipe = 
>current_state->res_ctx.pipe_ctx[j];
+   stream = pipe->stream;
+   break;
+   }
+   }
+
+   if (pipe && pipe->top_pipe && 
(get_num_odm_splits(pipe->top_pipe) > 0) && stream
+   && 
!dc_check_is_fullscreen_video(stream->src, 
srf_updates[i].scaling_info->clip_rect)) {
+   struct rect old_clip_rect, 
new_clip_rect;
+   bool old_clip_rect_left, 
old_clip_rect_right, old_clip_rect_middle;
+   bool new_clip_rect_left, 
new_clip_rect_right, new_clip_rect_middle;
+
+   old_clip_rect = 
srf_updates[i].surface->clip_rect;
+   new_clip_rect = 
srf_updates[i].scaling_info->clip_rect;
+
+   old_clip_rect_left = ((old_clip_rect.x 
+ old_clip_rect.width) <= (stream->src.x + (stream->src.width/2)));
+   old_clip_rect_right = (old_clip_rect.x 

[PATCH 06/21] drm/amd/display: Clear edid when unplug mst connector

[Solomon Chiu]

From: Wayne Lin 

[Why]
When unplug one sst monitor from a mst hub and plug in the same
port with another sst monitor, we don't read the corresponding
edid. That's because we detect there is already an edid stored in
aconnector->edid which is a stale one.

[How]
Clean up aconnector->edid when unplug mst connector.

Reviewed-by: Hersen Wu 
Acked-by: Solomon Chiu 
Signed-off-by: Wayne Lin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index ee5d6fa34a6b..8237029cedf5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -160,6 +160,7 @@ amdgpu_dm_mst_connector_early_unregister(struct 
drm_connector *connector)
 
dc_sink_release(dc_sink);
aconnector->dc_sink = NULL;
+   aconnector->edid = NULL;
}
drm_modeset_unlock(>mst_mgr.base.lock);
 }
@@ -411,6 +412,7 @@ dm_dp_mst_detect(struct drm_connector *connector,
 
dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL;
+   aconnector->edid = NULL;
}
 
return connection_status;
-- 
2.25.1

[PATCH 07/21] drm/amd/display: Disable PSRSU when DSC enabled on the specific sink

[Solomon Chiu]

From: Robin Chen 

[Why]
Some specific sink is not able to support PSRSU when DSC is turned on.
For this case, fall-back to use PSR1.

Reviewed-by: Anthony Koo 
Acked-by: Solomon Chiu 
Signed-off-by: Robin Chen 
---
 .../amd/display/modules/power/power_helpers.c | 33 ++-
 1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index bc239d38c3c7..235259d6c5a1 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -794,33 +794,34 @@ bool dmcu_load_iram(struct dmcu *dmcu,
  */
 bool is_psr_su_specific_panel(struct dc_link *link)
 {
-   if (link->dpcd_caps.edp_rev >= DP_EDP_14) {
-   if (link->dpcd_caps.psr_info.psr_version >= 
DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
-   return true;
+   bool isPSRSUSupported = false;
+   struct dpcd_caps *dpcd_caps = >dpcd_caps;
+
+   if (dpcd_caps->edp_rev >= DP_EDP_14) {
+   if (dpcd_caps->psr_info.psr_version >= 
DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
+   isPSRSUSupported = true;
/*
 * Some panels will report PSR capabilities over additional 
DPCD bits.
 * Such panels are approved despite reporting only PSR v3, as 
long as
 * the additional bits are reported.
 */
-   if (link->dpcd_caps.psr_info.psr_version < 
DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)
-   return false;
-
-   if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) {
+   if (dpcd_caps->sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) {
/*
-* FIXME:
 * This is the temporary workaround to disable PSRSU 
when system turned on
-* DSC function on the sepcific sink. Once the PSRSU + 
DSC is fixed, this
-* condition should be removed.
+* DSC function on the sepcific sink.
 */
-   if 
(link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)
-   return false;
-
-   if (link->dpcd_caps.psr_info.force_psrsu_cap == 0x1)
-   return true;
+   if (dpcd_caps->psr_info.psr_version < 
DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)
+   isPSRSUSupported = false;
+   else if 
(dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
+   ((dpcd_caps->sink_dev_id_str[1] == 0x08 && 
dpcd_caps->sink_dev_id_str[0] == 0x08) ||
+   (dpcd_caps->sink_dev_id_str[1] == 0x08 && 
dpcd_caps->sink_dev_id_str[0] == 0x07)))
+   isPSRSUSupported = false;
+   else if (dpcd_caps->psr_info.force_psrsu_cap == 0x1)
+   isPSRSUSupported = true;
}
}
 
-   return false;
+   return isPSRSUSupported;
 }
 
 /**
-- 
2.25.1

[PATCH 04/21] drm/amd/display: Removing assert statements for Linux

[Solomon Chiu]

From: Saaem Rizvi 

[WHY]
Assert statements causing several bugs on Linux DM

[HOW]
Removing assert statement for Linux DM
(ASSERT(result == VBIOSSMC_Result_OK)). Also adding
logging statements for setting dcfclk.

Reviewed-by: Gabe Teeger 
Acked-by: Solomon Chiu 
Signed-off-by: Saaem Rizvi 
---
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   | 8 ++--
 .../gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c| 7 ++-
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c  | 8 ++--
 .../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c| 8 ++--
 .../gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c| 8 ++--
 5 files changed, 30 insertions(+), 9 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 4137394a6ace..27fbe906682f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -101,9 +101,9 @@ static int rn_vbios_smu_send_msg_with_param(struct 
clk_mgr_internal *clk_mgr,
uint32_t result;
 
result = rn_smu_wait_for_response(clk_mgr, 10, 20);
-   ASSERT(result == VBIOSSMC_Result_OK);
 
-   smu_print("SMU response after wait: %d\n", result);
+   if (result != VBIOSSMC_Result_OK)
+   smu_print("SMU Response was not OK. SMU response after wait 
received is: %d\n", result);
 
if (result == VBIOSSMC_Status_BUSY) {
return -1;
@@ -188,6 +188,10 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct 
clk_mgr_internal *clk_mgr, int reque
VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
khz_to_mhz_ceil(requested_dcfclk_khz));
 
+#ifdef DBG
+   smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", 
actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
return actual_dcfclk_set_mhz * 1000;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
index d8f03328558b..e4f96b6fd79d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
@@ -102,7 +102,8 @@ static int dcn301_smu_send_msg_with_param(struct 
clk_mgr_internal *clk_mgr,
 
result = dcn301_smu_wait_for_response(clk_mgr, 10, 20);
 
-   smu_print("SMU response after wait: %d\n", result);
+   if (result != VBIOSSMC_Result_OK)
+   smu_print("SMU Response was not OK. SMU response after wait 
received is: %d\n", result);
 
if (result == VBIOSSMC_Status_BUSY) {
return -1;
@@ -179,6 +180,10 @@ int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal 
*clk_mgr, int request
VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
khz_to_mhz_ceil(requested_dcfclk_khz));
 
+#ifdef DBG
+   smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", 
actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
return actual_dcfclk_set_mhz * 1000;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index 6a17f7ed4d01..090b2c02aee1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -108,9 +108,9 @@ static int dcn31_smu_send_msg_with_param(struct 
clk_mgr_internal *clk_mgr,
uint32_t result;
 
result = dcn31_smu_wait_for_response(clk_mgr, 10, 20);
-   ASSERT(result == VBIOSSMC_Result_OK);
 
-   smu_print("SMU response after wait: %d\n", result);
+   if (result != VBIOSSMC_Result_OK)
+   smu_print("SMU Response was not OK. SMU response after wait 
received is: %d\n", result);
 
if (result == VBIOSSMC_Status_BUSY) {
return -1;
@@ -202,6 +202,10 @@ int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal 
*clk_mgr, int requeste
VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
khz_to_mhz_ceil(requested_dcfclk_khz));
 
+#ifdef DBG
+   smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", 
actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
return actual_dcfclk_set_mhz * 1000;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
index 74a78fda62fb..925d6e13620e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
@@ -136,9 +136,9 @@ static int dcn315_smu_send_msg_with_param(
uint32_t result;
 
result = dcn315_smu_wait_for_response(clk_mgr, 10, 20);
-   ASSERT(result == VBIOSSMC_Result_OK);
 
-   smu_print("SMU response after wait: %d\n", result);
+   if (result != 

[PATCH 03/21] drm/amd/display: Helper function for ALPM initialization

[Solomon Chiu]

From: muansari 

[WHY]
Needed a helper function for ALPM DPCD initialization

[HOW]
Refactoring to put ALPM initialization in a helper function

Reviewed-by: Anthony Koo 
Acked-by: Solomon Chiu 
Signed-off-by: Muhammad Ansari 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 27 ---
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  2 ++
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 335ca5b14fa7..dbdeda60e9e2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2734,6 +2734,22 @@ static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
 
 }
 
+bool dc_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
+{
+   bool ret = false;
+   union dpcd_alpm_configuration alpm_config;
+
+   if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
+   memset(_config, 0, sizeof(alpm_config));
+
+   alpm_config.bits.ENABLE = (enable ? true : false);
+   ret = dm_helpers_dp_write_dpcd(link->ctx, link,
+   DP_RECEIVER_ALPM_CONFIG, _config.raw,
+   sizeof(alpm_config.raw));
+   }
+   return ret;
+}
+
 /enable_link***/
 static enum dc_status enable_link(
struct dc_state *state,
@@ -3228,7 +3244,6 @@ bool dc_link_setup_psr(struct dc_link *link,
unsigned int panel_inst;
/* updateSinkPsrDpcdConfig*/
union dpcd_psr_configuration psr_configuration;
-   union dpcd_alpm_configuration alpm_configuration;
union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
 
psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
@@ -3284,15 +3299,7 @@ bool dc_link_setup_psr(struct dc_link *link,
sizeof(psr_configuration.raw));
 
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
-   memset(_configuration, 0, sizeof(alpm_configuration));
-
-   alpm_configuration.bits.ENABLE = 1;
-   dm_helpers_dp_write_dpcd(
-   link->ctx,
-   link,
-   DP_RECEIVER_ALPM_CONFIG,
-   _configuration.raw,
-   sizeof(alpm_configuration.raw));
+   dc_power_alpm_dpcd_enable(link, true);
psr_context->su_granularity_required =
psr_config->su_granularity_required;
psr_context->su_y_granularity =
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h 
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 29c0040a6dd4..023774b94da3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -320,6 +320,8 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
const struct dc_stream_state *stream, struct psr_config 
*psr_config,
struct psr_context *psr_context);
 
+bool dc_power_alpm_dpcd_enable(struct dc_link *link, bool enable);
+
 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t 
*residency);
 
 void dc_link_blank_all_dp_displays(struct dc *dc);
-- 
2.25.1

[PATCH 02/21] drm/amd/display: Check for DP2.0 when checking ODM combine

[Solomon Chiu]

From: Wesley Chalmers 

[WHY]
Certain DP 2.0 modes may fail validation if DP 2.0 is not considered for
ODM combine.

Reviewed-by: Wenjing Liu 
Acked-by: Solomon Chiu 
Signed-off-by: Wesley Chalmers 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 448fbbcdf88a..8d4c1cf1b8f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -4310,6 +4310,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
 
if (v->ODMCombinePolicy == 
dm_odm_combine_policy_none
|| !(v->Output[k] == dm_dp ||
+v->Output[k] == dm_dp2p0 ||
 v->Output[k] == dm_edp)) {
v->ODMCombineEnablePerState[i][k] = 
dm_odm_combine_mode_disabled;
v->PlaneRequiredDISPCLK = 
v->PlaneRequiredDISPCLKWithoutODMCombine;
-- 
2.25.1

[PATCH 01/21] drm/amd/display: Exit SubVP if MPO in use

[Solomon Chiu]

From: "Lee, Alvin" 

[Description]
Exit SubVP if MPO is in use since SubVP + MPO together is not supported.
- Don't add SubVP at validation time if we see MPO is in use

Issues fixed in the SubVP / MPO transition:
1. Enable phantom pipes in post unlock function to prevent underflow
when an active pipe is being transitioned to be a phantom pipe (VTG
updates take place right away). Also must wait for VUPDATE of the main
pipe to complete first

2. Don't wait for MPCC idle when transitioning a phantom pipe to an
actual pipe. MPCC_STATUS is never asserted due to OTG being off for
phantom pipes

3. When transitioning an active pipe to phantom, program DET right away
(same as disabling the pipe) or the DET update will only take when
the phantom pipe is enabled which can cause DET allocation errors.

4. For K1/K2 programming of phantom pipes, use same settings as the
main pipe. Also don't program K1 / K2 = 0xF ever since the field is only
1 / 2 bits wide.

Reviewed-by: Jun Lei 
Acked-by: Solomon Chiu 
Signed-off-by: Alvin Lee 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 27 +--
 drivers/gpu/drm/amd/display/dc/dc.h   |  2 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  4 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 72 +--
 4 files changed, 92 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 89a2f6749239..e13bf66f70e0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3208,15 +3208,21 @@ static void commit_planes_for_stream(struct dc *dc,
 
if (should_lock_all_pipes && 
dc->hwss.interdependent_update_lock) {
dc->hwss.interdependent_update_lock(dc, context, false);
+   } else {
+   dc->hwss.pipe_control_lock(dc, top_pipe_to_program, 
false);
+   }
+   dc->hwss.post_unlock_program_front_end(dc, context);
+
+   /* Since phantom pipe programming is moved to 
post_unlock_program_front_end,
+* move the SubVP lock to after the phantom pipes have been 
setup
+*/
+   if (should_lock_all_pipes && 
dc->hwss.interdependent_update_lock) {
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context, 
false, should_lock_all_pipes, NULL, subvp_prev_use);
} else {
-   dc->hwss.pipe_control_lock(dc, top_pipe_to_program, 
false);
if (dc->hwss.subvp_pipe_control_lock)
dc->hwss.subvp_pipe_control_lock(dc, context, 
false, should_lock_all_pipes, NULL, subvp_prev_use);
}
-
-   dc->hwss.post_unlock_program_front_end(dc, context);
return;
}
 
@@ -3346,12 +3352,8 @@ static void commit_planes_for_stream(struct dc *dc,
 
if (should_lock_all_pipes && 
dc->hwss.interdependent_update_lock) {
dc->hwss.interdependent_update_lock(dc, context, false);
-   if (dc->hwss.subvp_pipe_control_lock)
-   dc->hwss.subvp_pipe_control_lock(dc, context, 
false, should_lock_all_pipes, NULL, subvp_prev_use);
} else {
dc->hwss.pipe_control_lock(dc, top_pipe_to_program, 
false);
-   if (dc->hwss.subvp_pipe_control_lock)
-   dc->hwss.subvp_pipe_control_lock(dc, context, 
false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
}
 
if ((update_type != UPDATE_TYPE_FAST) && 
stream->update_flags.bits.dsc_changed)
@@ -3385,6 +3387,17 @@ static void commit_planes_for_stream(struct dc *dc,
if (update_type != UPDATE_TYPE_FAST)
dc->hwss.post_unlock_program_front_end(dc, context);
 
+   /* Since phantom pipe programming is moved to 
post_unlock_program_front_end,
+* move the SubVP lock to after the phantom pipes have been 
setup
+*/
+   if (should_lock_all_pipes && 
dc->hwss.interdependent_update_lock) {
+   if (dc->hwss.subvp_pipe_control_lock)
+   dc->hwss.subvp_pipe_control_lock(dc, context, 
false, should_lock_all_pipes, NULL, subvp_prev_use);
+   } else {
+   if (dc->hwss.subvp_pipe_control_lock)
+   dc->hwss.subvp_pipe_control_lock(dc, context, 
false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
+   }
+
// Fire manual trigger only when bottom plane is flipped
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 

[PATCH 00/21] DC Patches July 11, 2022

[Solomon Chiu]

This DC patchset brings improvements in multiple areas. In summary, we 
highlight:
 
- Fixes for MST, MPO, PSRSU, DP 2.0, Freesync and others
- Add register offsets of NBI and DCN.
- Improvement of ALPM
- Removing assert statement for Linux DM
- Re-implementing ARGB16161616 pixel format


Aric Cyr (2):
  drm/amd/display: 3.2.193
  drm/amd/display: 3.2.194

Aurabindo Pillai (1):
  drm/amd/display: Add NBIO reg offsets to DC

Charlene Liu (1):
  drm/amd/display: add system info table log

Chris Park (1):
  drm/amd/display: Reduce SCDC Status Flags Definition

Fangzhi Zuo (1):
  drm/amd/display: Ignore First MST Sideband Message Return Error

Harry Wentland (1):
  drm/amd/display: Add DCN reg offsets to DC

Ilya Bakoulin (1):
  drm/amd/display: Fix black screen when disabling Freesync in OSD

Lee, Alvin (1):
  drm/amd/display: Exit SubVP if MPO in use

Lei, Jun (1):
  drm/amd/display: update DML1 logic for unbounded req handling

Robin Chen (1):
  drm/amd/display: Disable PSRSU when DSC enabled on the specific sink

Rodrigo Siqueira (1):
  drm/amd/display: Fix wrong reference

Saaem Rizvi (1):
  drm/amd/display: Removing assert statements for Linux

Samson Tam (2):
  drm/amd/display: Fix windowed MPO video with ODM combine for DCN32
  drm/amd/display: Fix lag when moving windowed MPO across display using
ODM 2:1 combine

Wayne Lin (2):
  drm/amd/display: Clear edid when unplug mst connector
  drm/amd/display: Grab dc_lock before detecting link

Wellenreiter, Ethan (1):
  drm/amd/display: Re-implementing ARGB16161616 pixel format as 22

Wenjing Liu (1):
  drm/amd/display: make enable link independent from verified link caps

Wesley Chalmers (1):
  drm/amd/display: Check for DP2.0 when checking ODM combine

muansari (1):
  drm/amd/display: Helper function for ALPM initialization

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 115 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   8 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  11 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  19 +++
 .../drm/amd/display/dc/bios/bios_parser2.c|  30 
 .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   |   8 +-
 .../display/dc/clk_mgr/dcn301/dcn301_smu.c|   7 +-
 .../amd/display/dc/clk_mgr/dcn31/dcn31_smu.c  |   8 +-
 .../display/dc/clk_mgr/dcn315/dcn315_smu.c|   8 +-
 .../display/dc/clk_mgr/dcn316/dcn316_smu.c|   8 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 136 ++-
 .../gpu/drm/amd/display/dc/core/dc_debug.c|   2 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  54 +++---
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |   7 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  45 ++---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 157 ++
 drivers/gpu/drm/amd/display/dc/dc.h   |  16 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h  |   2 +
 drivers/gpu/drm/amd/display/dc/dc_types.h |   3 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  |   2 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   3 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   4 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c  |   2 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   3 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  72 +++-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c  |   2 +
 .../dc/dml/dcn31/display_mode_vba_31.c|   1 +
 .../drm/amd/display/dc/dml/display_mode_vba.c |   9 +
 .../drm/amd/display/dc/dml/display_mode_vba.h |   9 +
 .../gpu/drm/amd/display/dc/inc/core_status.h  |   1 +
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  37 +
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   2 +-
 .../amd/display/modules/power/power_helpers.c |  33 ++--
 33 files changed, 660 insertions(+), 164 deletions(-)

-- 
2.25.1

[PATCH] drm/amd/display: make some dc_dmub_srv functions static

[Alex Deucher]

Not used outside of dc_dmub_srv.c.

Reported-by: kernel test robot 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 832f7a4deb03..39b426d04037 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -270,7 +270,7 @@ void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t 
tg_inst, uint32_t vtotal
dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
 }
 
-uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state 
*stream)
+static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct 
dc_stream_state *stream)
 {
uint8_t pipes = 0;
int i = 0;
@@ -284,7 +284,7 @@ uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, 
struct dc_stream_state *
return pipes;
 }
 
-int dc_dmub_srv_get_timing_generator_offset(struct dc *dc, struct 
dc_stream_state *stream)
+static int dc_dmub_srv_get_timing_generator_offset(struct dc *dc, struct 
dc_stream_state *stream)
 {
int  tg_inst = 0;
int i = 0;
-- 
2.35.3

Re: Radeon Evergreen/NI, power modes & DL-DVI

[Alex Deucher]

On Fri, Jul 8, 2022 at 11:05 AM  wrote:
>
> Most Radeon Evergreen and Northern Island cards support power-saving modes
> with Linux and XOrg well, and have done for years. But if a dual link DVI
> monitor is in use (e.g. a 2560x1440 or 2560x1600 screen), the card will
> refuse to transition out of its high power mode while the display is
> active. I believe that this is because transitions are not supported when
> multiple displays are active, and dual link DVI is counted as being two
> displays.

This has nothing to do with dual link vs single link.  Whether or not
we can change memory clocks comes down to the length of the vblank
period.  We can only change the memory clock during display blanking
periods otherwise you get display disruptions.  WIth multiple displays
this is obviously more complex because the blanking periods may not
align at all.  With single displays however, the blanking period needs
to be long enough to allow the memory reclocking to complete.  Some
displays have a very short vblank period which is not long enough for
a memory reclock.  One option in that case is to tweak the display
timing a bit to extend the vblank period.  Also, depending on the
chip, mclk switching is not possible with very high refresh rates.  In
your particular case, you might be right on the edge of the time which
is why the driver disables mclk switching even though it might appear
to be possible.  Even in some rare cases where users were under the
limit, they were near enough to it that you periodically would see
display disruption during certain mclk reclocks.  See
radeon_dpm_single_display() in radeon_pm.c.

Alex

Radeon Evergreen/NI, power modes & DL-DVI

[mjr19]

Most Radeon Evergreen and Northern Island cards support power-saving modes 
with Linux and XOrg well, and have done for years. But if a dual link DVI 
monitor is in use (e.g. a 2560x1440 or 2560x1600 screen), the card will 
refuse to transition out of its high power mode while the display is 
active. I believe that this is because transitions are not supported when 
multiple displays are active, and dual link DVI is counted as being two 
displays.

If so, this seems wrong as the main issue with multiple displays is the 
difficulty of arranging to change the mclk when neither is mid-way through 
a scan line. With DL-DVI the two links are perfectly synchronised, and so 
this issue does not arise.

Unsurprisingly the cards do enter their low-power state when their output 
is off (e.g. "xset dpms force off"), but more surprisingly on awakening 
they remain in their low power state. The slightest provocation then 
causes a permanent transition to the high power state, showing that 
transitions with the display active work, and are invisible.

One can force them to run in their low power state by

echo low > /sys/class/drm/card0/device/power_dpm_force_performance_level

when they are already in the low power state. On many cards this provides 
adequate performance for most office-type applications, but it is hopeless 
at supporting any form of video.

So would it be possible to permit the high power to low power transition 
even when a DL-DVI display is active? (I believe that the AMDGPU driver 
gained the ability to do power level transitions with multiple 
synchonrised displays back in 2019 with amdgpu.dcfeaturemask=2 but I am 
unaware that the change was made to the older radeon driver, and DL-DVI is 
hardly two displays anyway.)

(Why do I care? I am responsible for several dozen machines with these 
cards, as, if one wants a cheap, passively-cooled card with good support 
from the free XOrg drivers, they are still quite good. I believe that the 
R5 230 is still in production too. The sort of office applications these 
machines display would allow the cards to stay in their low-power state 
most of the time, but not quite all of it. In the past most of our 
machines tended to have a single 1920x1080 monitor, so this did not 
matter, but now 2.5k monitors are becoming more common. AMD's habit of 
launching new CPUs some months before the corresponding APUs means that 
our need of simple passively-cooled cards is still quite current, as our 
programs do like the latest CPUs.)

Issue present on X.Org 1.21.1.3 radeon module 19.1.0 on Ubuntu 22.04 
x86_64.

Regards,

Michael

-- 
Dr MJ Rutter, TCM, Cavendish Lab, JJ Thomson Av, Cambridge. CB3 0HE
Email: mj...@cam.ac.uk  Ph: 01223 337386  https://www.mjr19.org.uk/

Re: [PATCH v8 02/15] mm: move page zone helpers into new header-specific file

[David Hildenbrand]

On 07.07.22 21:03, Alex Sierra wrote:
> [WHY]
> Have a cleaner way to expose all page zone helpers in one header

What exactly is a "page zone"? Do you mean a buddy zone as in
include/linux/mmzone.h ?


-- 
Thanks,

David / dhildenb

Re: [PATCH v8 01/15] mm: rename is_pinnable_pages to is_longterm_pinnable_pages

[David Hildenbrand]

On 07.07.22 21:03, Alex Sierra wrote:
> is_pinnable_page() and folio_is_pinnable() were renamed to
> is_longterm_pinnable_page() and folio_is_longterm_pinnable()
> respectively. These functions are used in the FOLL_LONGTERM flag
> context.
> 
> Signed-off-by: Alex Sierra 
> ---
>  include/linux/mm.h | 8 
>  mm/gup.c   | 4 ++--
>  mm/gup_test.c  | 2 +-
>  mm/hugetlb.c   | 2 +-
>  4 files changed, 8 insertions(+), 8 deletions(-)
> 

Reviewed-by: David Hildenbrand 


-- 
Thanks,

David / dhildenb

Re: [PATCH] drm/amd/display: Remove condition with no effect

[Harry Wentland]

On 2022-07-07 23:10, Zhongjun Tan wrote:
> From: Zhongjun Tan 
> 
> Remove condition with no effect

Please explain why you think this has no effect.

Harry

> 
> Signed-off-by: Zhongjun Tan 
> ---
>  .../drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c   | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git 
> a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c 
> b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
> index 07f3a85f8edf..ec3ea94d3802 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
> @@ -4670,10 +4670,6 @@ void dml32_CalculateMinAndMaxPrefetchMode(
>   } else if (AllowForPStateChangeOrStutterInVBlankFinal == 
> dm_prefetch_support_uclk_fclk_and_stutter) {
>   *MinPrefetchMode = 0;
>   *MaxPrefetchMode = 0;
> - } else if (AllowForPStateChangeOrStutterInVBlankFinal ==
> - dm_prefetch_support_uclk_fclk_and_stutter_if_possible) {
> - *MinPrefetchMode = 0;
> - *MaxPrefetchMode = 3;
>   } else {
>   *MinPrefetchMode = 0;
>   *MaxPrefetchMode = 3;

Re: [PATCH 1/3] drm/amdgpu: add AMDGPU_GEM_CREATE_DISCARDABLE

[Marek Olšák]

Christian, should we set this flag for GDS too? Will it help with GDS OOM
failures?

Marek

On Fri., May 13, 2022, 07:26 Christian König, <
ckoenig.leichtzumer...@gmail.com> wrote:

> Exactly that's what we can't do.
>
> See the kernel must always be able to move things to GTT or discard. So
> when you want to guarantee that something is in VRAM you must at the
> same time say you can discard it if it can't.
>
> Christian.
>
> Am 13.05.22 um 10:43 schrieb Pierre-Eric Pelloux-Prayer:
> > Hi Marek, Christian,
> >
> > If the main feature for Mesa of AMDGPU_GEM_CREATE_DISCARDABLE is
> > getting the best placement, maybe we should have 2 separate flags:
> >   * AMDGPU_GEM_CREATE_DISCARDABLE: indicates to the kernel that it can
> > discards the content on eviction instead of preserving it
> >   * AMDGPU_GEM_CREATE_FORCE_BEST_PLACEMENT (or
> > AMDGPU_GEM_CREATE_NO_GTT_FALLBACK ? or AMDGPU_CREATE_GEM_AVOID_GTT?):
> > tells the kernel that this bo really needs to be in VRAM
> >
> >
> > Pierre-Eric
> >
> > On 13/05/2022 00:17, Marek Olšák wrote:
> >> Would it be better to set the VM_ALWAYS_VALID flag to have a greater
> >> guarantee that the best placement will be chosen?
> >>
> >> See, the main feature is getting the best placement, not being
> >> discardable. The best placement is a hw design requirement due to
> >> using memory for uses that are expected to have performance similar
> >> to onchip SRAMs. We need to make sure the best placement is
> >> guaranteed if it's VRAM.
> >>
> >> Marek
> >>
> >> On Thu., May 12, 2022, 03:26 Christian König,
> >>  >> > wrote:
> >>
> >> Am 12.05.22 um 00:06 schrieb Marek Olšák:
> >>> 3rd question: Is it worth using this on APUs?
> >>
> >> It makes memory management somewhat easier when we are really OOM.
> >>
> >> E.g. it should also work for GTT allocations and when the core
> >> kernel says "Hey please free something up or I will start the
> >> OOM-killer" it's something we can easily throw away.
> >>
> >> Not sure how many of those buffers we have, but marking
> >> everything which is temporary with that flag is probably a good idea.
> >>
> >>>
> >>> Thanks,
> >>> Marek
> >>>
> >>> On Wed, May 11, 2022 at 5:58 PM Marek Olšák  >>> > wrote:
> >>>
> >>> Will the kernel keep all discardable buffers in VRAM if VRAM
> >>> is not overcommitted by discardable buffers, or will other buffers
> >>> also affect the placement of discardable buffers?
> >>>
> >>
> >> Regarding the eviction pressure the buffers will be handled like
> >> any other buffer, but instead of preserving the content it is just
> >> discarded on eviction.
> >>
> >>>
> >>> Do evictions deallocate the buffer, or do they keep an
> >>> allocation in GTT and only the copy is skipped?
> >>>
> >>
> >> It really deallocates the backing store of the buffer, just keeps
> >> a dummy page array around where all entries are NULL.
> >>
> >> There is a patch set on the mailing list to make this a little
> >> bit more efficient, but even using the dummy page array should only
> >> have a few bytes overhead.
> >>
> >> Regards,
> >> Christian.
> >>
> >>>
> >>> Thanks,
> >>> Marek
> >>>
> >>> On Wed, May 11, 2022 at 3:08 AM Marek Olšák
> >>> mailto:mar...@gmail.com>> wrote:
> >>>
> >>> OK that sounds good.
> >>>
> >>> Marek
> >>>
> >>> On Wed, May 11, 2022 at 2:04 AM Christian König
> >>>  >>> > wrote:
> >>>
> >>> Hi Marek,
> >>>
> >>> Am 10.05.22 um 22:43 schrieb Marek Olšák:
>  A better flag name would be:
>  AMDGPU_GEM_CREATE_BEST_PLACEMENT_OR_DISCARD
> >>>
> >>> A bit long for my taste and I think the best
> >>> placement is just a side effect.
> >>>
> 
>  Marek
> 
>  On Tue, May 10, 2022 at 4:13 PM Marek Olšák
>  mailto:mar...@gmail.com>> wrote:
> 
>  Does this really guarantee VRAM placement? The
>  code doesn't say anything about that.
> 
> >>>
> >>> Yes, see the code here:
> >>>
> 
>  diff --git
>  a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>  b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>  index 8b7ee1142d9a..1944ef37a61e 100644
>  ---
>  a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>  +++
>  b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>  @@ -567,6 +567,7 @@ int
>  amdgpu_bo_create(struct amdgpu_device *adev,
>  bp->domain;
>  bo->allowed_domains =
>  bo->preferred_domains;
>  if (bp->type != ttm_bo_type_kernel &&
> 

Re: [PATCH] drm/amd/display: fix 32 bit compilation errors in dc_dmub_srv.c

[Harry Wentland]

On 2022-07-08 01:26, Alex Deucher wrote:
> There are several things wrong here.  First, none of these
> numbers are FP, so there is no need to cast to double.  Next
> make sure to use proper 64 bit division helpers.
> 
> Fixes: 85f4bc0c333c ("drm/amd/display: Add SubVP required code")
> Signed-off-by: Alex Deucher 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/Makefile  | 26 
>  drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 67 ++--
>  2 files changed, 34 insertions(+), 59 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
> b/drivers/gpu/drm/amd/display/dc/Makefile
> index dfe82bcdd17d..64f40b10c163 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -22,31 +22,6 @@
>  #
>  # Makefile for Display Core (dc) component.
>  
> -ifdef CONFIG_X86
> -dmub_ccflags := -mhard-float -msse
> -endif
> -
> -ifdef CONFIG_PPC64
> -dmub_ccflags := -mhard-float -maltivec
> -endif
> -
> -ifdef CONFIG_CC_IS_GCC
> -ifeq ($(call cc-ifversion, -lt, 0701, y), y)
> -IS_OLD_GCC = 1
> -endif
> -endif
> -
> -ifdef CONFIG_X86
> -ifdef IS_OLD_GCC
> -# Stack alignment mismatch, proceed with caution.
> -# GCC < 7.1 cannot compile code using `double` and 
> -mpreferred-stack-boundary=3
> -# (8B stack alignment).
> -dmub_ccflags += -mpreferred-stack-boundary=4
> -else
> -dmub_ccflags += -msse2
> -endif
> -endif
> -
>  DC_LIBS = basics bios dml clk_mgr dce gpio irq link virtual
>  
>  ifdef CONFIG_DRM_AMD_DC_DCN
> @@ -99,7 +74,6 @@ AMD_DISPLAY_FILES += $(AMD_DISPLAY_CORE)
>  AMD_DISPLAY_FILES += $(AMD_DM_REG_UPDATE)
>  
>  DC_DMUB += dc_dmub_srv.o
> -CFLAGS_$(AMDDALPATH)/dc/dc_dmub_srv.o := $(dmub_ccflags)
>  DC_EDID += dc_edid_parser.o
>  AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))
>  AMD_DISPLAY_EDID = $(addprefix $(AMDDALPATH)/dc/,$(DC_EDID))
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 
> b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
> index 6b446ae9e91f..832f7a4deb03 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
> +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
> @@ -416,27 +416,28 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,
>   pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for 
> now don't use ramping
>   pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // 
> hardcode 4ms DRR window for now
>  
> - drr_frame_us = drr_timing->v_total * drr_timing->h_total /
> - (double)(drr_timing->pix_clk_100hz * 100) * 100;
> + drr_frame_us = div64_s64(drr_timing->v_total * drr_timing->h_total,
> +  (int64_t)(drr_timing->pix_clk_100hz * 100) * 
> 100);
>   // P-State allow width and FW delays already included 
> phantom_timing->v_addressable
> - mall_region_us = phantom_timing->v_addressable * 
> phantom_timing->h_total /
> - (double)(phantom_timing->pix_clk_100hz * 100) * 100;
> + mall_region_us = div64_s64(phantom_timing->v_addressable * 
> phantom_timing->h_total,
> +(int64_t)(phantom_timing->pix_clk_100hz * 
> 100) * 100);
>   min_drr_supported_us = drr_frame_us + mall_region_us + 
> SUBVP_DRR_MARGIN_US;
> - min_vtotal_supported = drr_timing->pix_clk_100hz * 100 * 
> ((double)min_drr_supported_us / 100) /
> - (double)drr_timing->h_total;
> -
> - prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) 
> * phantom_timing->h_total /
> - (double)(phantom_timing->pix_clk_100hz * 100) * 100 
> +
> - dc->caps.subvp_prefetch_end_to_mall_start_us;
> - subvp_active_us = main_timing->v_addressable * main_timing->h_total /
> - (double)(main_timing->pix_clk_100hz * 100) * 100;
> - drr_active_us = drr_timing->v_addressable * drr_timing->h_total /
> - (double)(drr_timing->pix_clk_100hz * 100) * 100;
> - max_drr_vblank_us = (double)(subvp_active_us - prefetch_us - 
> drr_active_us) / 2 + drr_active_us;
> + min_vtotal_supported = div64_s64(drr_timing->pix_clk_100hz * 100 *
> +  
> (div64_s64((int64_t)min_drr_supported_us, 100)),
> +  (int64_t)drr_timing->h_total);
> +
> + prefetch_us = div64_s64((phantom_timing->v_total - 
> phantom_timing->v_front_porch) * phantom_timing->h_total,
> + (int64_t)(phantom_timing->pix_clk_100hz * 100) 
> * 100 +
> + dc->caps.subvp_prefetch_end_to_mall_start_us);
> + subvp_active_us = div64_s64(main_timing->v_addressable * 
> main_timing->h_total,
> + (int64_t)(main_timing->pix_clk_100hz * 100) 
> * 100);
> + drr_active_us = div64_s64(drr_timing->v_addressable * 
> drr_timing->h_total,
> +   

RE: [PATCH 6/6] drm/ttm: stop allocating a dummy resource for pipelined gutting

[Ruhl, Michael J]

>-Original Message-
>From: dri-devel  On Behalf Of
>Christian König
>Sent: Thursday, July 7, 2022 6:25 AM
>To: intel-...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>nouv...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
>Cc: Christian König 
>Subject: [PATCH 6/6] drm/ttm: stop allocating a dummy resource for pipelined
>gutting
>
>That should not be necessary any more when drivers should at least be
>able to handle a move without a resource.
>
>Signed-off-by: Christian König 

Reviewed-by: Michael J. Ruhl 

M

>---
> drivers/gpu/drm/ttm/ttm_bo_util.c | 15 ++-
> 1 file changed, 2 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
>b/drivers/gpu/drm/ttm/ttm_bo_util.c
>index 1530982338e9..1e76149c62ff 100644
>--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
>+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
>@@ -603,16 +603,10 @@ EXPORT_SYMBOL(ttm_bo_move_sync_cleanup);
>  */
> int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo)
> {
>-  static const struct ttm_place sys_mem = { .mem_type =
>TTM_PL_SYSTEM };
>   struct ttm_buffer_object *ghost;
>-  struct ttm_resource *sys_res;
>   struct ttm_tt *ttm;
>   int ret;
>
>-  ret = ttm_resource_alloc(bo, _mem, _res);
>-  if (ret)
>-  return ret;
>-
>   /* If already idle, no need for ghost object dance. */
>   ret = ttm_bo_wait(bo, false, true);
>   if (ret != -EBUSY) {
>@@ -620,14 +614,13 @@ int ttm_bo_pipeline_gutting(struct
>ttm_buffer_object *bo)
>   /* See comment below about clearing. */
>   ret = ttm_tt_create(bo, true);
>   if (ret)
>-  goto error_free_sys_mem;
>+  return ret;
>   } else {
>   ttm_tt_unpopulate(bo->bdev, bo->ttm);
>   if (bo->type == ttm_bo_type_device)
>   ttm_tt_mark_for_clear(bo->ttm);
>   }
>   ttm_resource_free(bo, >resource);
>-  ttm_bo_assign_mem(bo, sys_res);
>   return 0;
>   }
>
>@@ -644,7 +637,7 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object
>*bo)
>   ret = ttm_tt_create(bo, true);
>   swap(bo->ttm, ttm);
>   if (ret)
>-  goto error_free_sys_mem;
>+  return ret;
>
>   ret = ttm_buffer_object_transfer(bo, );
>   if (ret)
>@@ -658,13 +651,9 @@ int ttm_bo_pipeline_gutting(struct
>ttm_buffer_object *bo)
>   dma_resv_unlock(>base._resv);
>   ttm_bo_put(ghost);
>   bo->ttm = ttm;
>-  ttm_bo_assign_mem(bo, sys_res);
>   return 0;
>
> error_destroy_tt:
>   ttm_tt_destroy(bo->bdev, ttm);
>-
>-error_free_sys_mem:
>-  ttm_resource_free(bo, _res);
>   return ret;
> }
>--
>2.25.1

RE: [PATCH 5/6] drm/ttm: stop allocating dummy resources during BO creation

[Ruhl, Michael J]

>-Original Message-
>From: dri-devel  On Behalf Of
>Christian König
>Sent: Thursday, July 7, 2022 6:25 AM
>To: intel-...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>nouv...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
>Cc: Christian König 
>Subject: [PATCH 5/6] drm/ttm: stop allocating dummy resources during BO
>creation
>
>That should not be necessary any more when drivers should at least be
>able to handle the move without a resource.
>
>Signed-off-by: Christian König 

Reviewed-by: Michael J. Ruhl 

M

>---
> drivers/gpu/drm/ttm/ttm_bo.c | 7 ---
> 1 file changed, 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
>index a2f49bdda8a1..f491be751a2f 100644
>--- a/drivers/gpu/drm/ttm/ttm_bo.c
>+++ b/drivers/gpu/drm/ttm/ttm_bo.c
>@@ -960,7 +960,6 @@ int ttm_bo_init_reserved(struct ttm_device *bdev,
>struct ttm_buffer_object *bo,
>struct sg_table *sg, struct dma_resv *resv,
>void (*destroy) (struct ttm_buffer_object *))
> {
>-  static const struct ttm_place sys_mem = { .mem_type =
>TTM_PL_SYSTEM };
>   int ret;
>
>   kref_init(>kref);
>@@ -978,12 +977,6 @@ int ttm_bo_init_reserved(struct ttm_device *bdev,
>struct ttm_buffer_object *bo,
>   bo->base.resv = >base._resv;
>   atomic_inc(_glob.bo_count);
>
>-  ret = ttm_resource_alloc(bo, _mem, >resource);
>-  if (unlikely(ret)) {
>-  ttm_bo_put(bo);
>-  return ret;
>-  }
>-
>   /*
>* For ttm_bo_type_device buffers, allocate
>* address space from the device.
>--
>2.25.1

RE: [Intel-gfx] [PATCH 4/6] drm/ttm: audit bo->resource usage v2

[Ruhl, Michael J]

>-Original Message-
>From: Intel-gfx  On Behalf Of
>Christian König
>Sent: Thursday, July 7, 2022 6:25 AM
>To: intel-...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>nouv...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
>Cc: Christian König 
>Subject: [Intel-gfx] [PATCH 4/6] drm/ttm: audit bo->resource usage v2
>
>Allow BOs to exist without backing store.
>
>v2: handle ttm_bo_move_memcpy as well.
>
>Signed-off-by: Christian König 

Reviewed-by: Michael J. Ruhl 

M

>---
> drivers/gpu/drm/ttm/ttm_bo.c  | 16 
> drivers/gpu/drm/ttm/ttm_bo_util.c |  7 +--
> 2 files changed, 13 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
>index 984535d6a2d0..a2f49bdda8a1 100644
>--- a/drivers/gpu/drm/ttm/ttm_bo.c
>+++ b/drivers/gpu/drm/ttm/ttm_bo.c
>@@ -117,12 +117,13 @@ static int ttm_bo_handle_move_mem(struct
>ttm_buffer_object *bo,
> struct ttm_operation_ctx *ctx,
> struct ttm_place *hop)
> {
>-  struct ttm_resource_manager *old_man, *new_man;
>   struct ttm_device *bdev = bo->bdev;
>+  bool old_use_tt, new_use_tt;
>   int ret;
>
>-  old_man = ttm_manager_type(bdev, bo->resource->mem_type);
>-  new_man = ttm_manager_type(bdev, mem->mem_type);
>+  old_use_tt = bo->resource &&
>+  ttm_manager_type(bdev, bo->resource->mem_type)-
>>use_tt;
>+  new_use_tt = ttm_manager_type(bdev, mem->mem_type)->use_tt;
>
>   ttm_bo_unmap_virtual(bo);
>
>@@ -130,11 +131,11 @@ static int ttm_bo_handle_move_mem(struct
>ttm_buffer_object *bo,
>* Create and bind a ttm if required.
>*/
>
>-  if (new_man->use_tt) {
>+  if (new_use_tt) {
>   /* Zero init the new TTM structure if the old location should
>* have used one as well.
>*/
>-  ret = ttm_tt_create(bo, old_man->use_tt);
>+  ret = ttm_tt_create(bo, old_use_tt);
>   if (ret)
>   goto out_err;
>
>@@ -160,8 +161,7 @@ static int ttm_bo_handle_move_mem(struct
>ttm_buffer_object *bo,
>   return 0;
>
> out_err:
>-  new_man = ttm_manager_type(bdev, bo->resource->mem_type);
>-  if (!new_man->use_tt)
>+  if (!old_use_tt)
>   ttm_bo_tt_destroy(bo);
>
>   return ret;
>@@ -904,7 +904,7 @@ int ttm_bo_validate(struct ttm_buffer_object *bo,
>   /*
>* Check whether we need to move buffer.
>*/
>-  if (!ttm_resource_compat(bo->resource, placement)) {
>+  if (!bo->resource || !ttm_resource_compat(bo->resource,
>placement)) {
>   ret = ttm_bo_move_buffer(bo, placement, ctx);
>   if (ret)
>   return ret;
>diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
>b/drivers/gpu/drm/ttm/ttm_bo_util.c
>index 1cbfb00c1d65..1530982338e9 100644
>--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
>+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
>@@ -137,8 +137,7 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object
>*bo,
>   ttm_manager_type(bo->bdev, dst_mem->mem_type);
>   struct ttm_tt *ttm = bo->ttm;
>   struct ttm_resource *src_mem = bo->resource;
>-  struct ttm_resource_manager *src_man =
>-  ttm_manager_type(bdev, src_mem->mem_type);
>+  struct ttm_resource_manager *src_man;
>   union {
>   struct ttm_kmap_iter_tt tt;
>   struct ttm_kmap_iter_linear_io io;
>@@ -147,6 +146,10 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object
>*bo,
>   bool clear;
>   int ret = 0;
>
>+  if (!src_mem)
>+  return 0;
>+
>+  src_man = ttm_manager_type(bdev, src_mem->mem_type);
>   if (ttm && ((ttm->page_flags & TTM_TT_FLAG_SWAPPED) ||
>   dst_man->use_tt)) {
>   ret = ttm_tt_populate(bdev, ttm, ctx);
>--
>2.25.1

RE: [Intel-gfx] [PATCH 3/6] drm/nouveau: audit bo->resource usage

[Ruhl, Michael J]

>-Original Message-
>From: Intel-gfx  On Behalf Of
>Christian König
>Sent: Thursday, July 7, 2022 6:25 AM
>To: intel-...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>nouv...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
>Cc: Christian König 
>Subject: [Intel-gfx] [PATCH 3/6] drm/nouveau: audit bo->resource usage
>
>Make sure we can at least move and release BOs without backing store.
>
>Signed-off-by: Christian König 

Reviewed-by: Michael J. Ruhl 

M

>---
> drivers/gpu/drm/nouveau/nouveau_bo.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
>b/drivers/gpu/drm/nouveau/nouveau_bo.c
>index 92cd19021084..f83fb43b2e44 100644
>--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
>+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
>@@ -1006,7 +1006,8 @@ nouveau_bo_move(struct ttm_buffer_object *bo,
>bool evict,
>   }
>
>   /* Fake bo copy. */
>-  if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
>+  if (!old_reg || (old_reg->mem_type == TTM_PL_SYSTEM &&
>+   !bo->ttm)) {
>   ttm_bo_move_null(bo, new_reg);
>   goto out;
>   }
>--
>2.25.1

RE: [Intel-gfx] [PATCH 2/6] drm/amdgpu: audit bo->resource usage

[Ruhl, Michael J]

>-Original Message-
>From: Intel-gfx  On Behalf Of
>Christian König
>Sent: Thursday, July 7, 2022 6:25 AM
>To: intel-...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>nouv...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
>Cc: Christian König 
>Subject: [Intel-gfx] [PATCH 2/6] drm/amdgpu: audit bo->resource usage
>
>Make sure we can at least move and release BOs without backing store.
>
>Signed-off-by: Christian König 

Reviewed-by: Michael J. Ruhl 

M

>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 3 ++-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>index d9cfe259f2a9..677d1dfab37f 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>@@ -1305,7 +1305,7 @@ void amdgpu_bo_release_notify(struct
>ttm_buffer_object *bo)
>   if (bo->base.resv == >base._resv)
>   amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
>
>-  if (bo->resource->mem_type != TTM_PL_VRAM ||
>+  if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM ||
>   !(abo->flags &
>AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||
>   adev->in_suspend || adev->shutdown)
>   return;
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>index be6f76a30ac6..3bddf266e8b5 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>@@ -471,7 +471,8 @@ static int amdgpu_bo_move(struct ttm_buffer_object
>*bo, bool evict,
>
>   adev = amdgpu_ttm_adev(bo->bdev);
>
>-  if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
>+  if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
>+   bo->ttm == NULL)) {
>   ttm_bo_move_null(bo, new_mem);
>   goto out;
>   }
>--
>2.25.1

RE: [PATCH 1/6] drm/ttm: rename and cleanup ttm_bo_init_reserved

[Ruhl, Michael J]

>-Original Message-
>From: dri-devel  On Behalf Of
>Christian König
>Sent: Thursday, July 7, 2022 6:25 AM
>To: intel-...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>nouv...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
>Cc: Christian König 
>Subject: [PATCH 1/6] drm/ttm: rename and cleanup ttm_bo_init_reserved
>
>Rename ttm_bo_init_reserved to ttm_bo_init_validate since that better
>matches what the function is actually doing.
>
>Remove the unused size parameter, move the function's kerneldoc to the
>implementation and cleanup the whole error handling.
>
>Signed-off-by: Christian König 
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |   2 +-
> drivers/gpu/drm/drm_gem_vram_helper.c  |   6 +-
> drivers/gpu/drm/i915/gem/i915_gem_ttm.c|   5 +-
> drivers/gpu/drm/nouveau/nouveau_bo.c   |   6 +-
> drivers/gpu/drm/qxl/qxl_object.c   |   2 +-
> drivers/gpu/drm/radeon/radeon_object.c |   6 +-
> drivers/gpu/drm/ttm/ttm_bo.c   | 147 +++--
> drivers/gpu/drm/vmwgfx/vmwgfx_bo.c |  12 +-
> include/drm/ttm/ttm_bo_api.h   |  93 ++---
> 9 files changed, 129 insertions(+), 150 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>index 2c82b1d5a0d7..d9cfe259f2a9 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>@@ -591,7 +591,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
>   if (!bp->destroy)
>   bp->destroy = _bo_destroy;
>
>-  r = ttm_bo_init_reserved(>mman.bdev, >tbo, size, bp-
>>type,
>+  r = ttm_bo_init_reserved(>mman.bdev, >tbo, bp->type,
>>placement, page_align, ,  NULL,
>bp->resv, bp->destroy);
>   if (unlikely(r != 0))
>diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
>b/drivers/gpu/drm/drm_gem_vram_helper.c
>index d607043716d3..125160b534be 100644
>--- a/drivers/gpu/drm/drm_gem_vram_helper.c
>+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
>@@ -226,9 +226,9 @@ struct drm_gem_vram_object
>*drm_gem_vram_create(struct drm_device *dev,
>* A failing ttm_bo_init will call ttm_buffer_object_destroy
>* to release gbo->bo.base and kfree gbo.
>*/
>-  ret = ttm_bo_init(bdev, >bo, size, ttm_bo_type_device,
>->placement, pg_align, false, NULL, NULL,
>-ttm_buffer_object_destroy);
>+  ret = ttm_bo_init_validate(bdev, >bo, ttm_bo_type_device,
>+ >placement, pg_align, false, NULL,
>NULL,
>+ ttm_buffer_object_destroy);
>   if (ret)
>   return ERR_PTR(ret);
>
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>index 4c25d9b2f138..70e2ed4e99df 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>@@ -1229,9 +1229,8 @@ int __i915_gem_ttm_object_init(struct
>intel_memory_region *mem,
>* Similarly, in delayed_destroy, we can't call ttm_bo_put()
>* until successful initialization.
>*/
>-  ret = ttm_bo_init_reserved(>bdev, i915_gem_to_ttm(obj),
>size,
>- bo_type, _sys_placement,
>- page_size >> PAGE_SHIFT,
>+  ret = ttm_bo_init_reserved(>bdev, i915_gem_to_ttm(obj),
>bo_type,
>+ _sys_placement, page_size >>
>PAGE_SHIFT,
>  , NULL, NULL, i915_ttm_bo_destroy);
>   if (ret)
>   return i915_ttm_err_to_gem(ret);
>diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
>b/drivers/gpu/drm/nouveau/nouveau_bo.c
>index 05076e530e7d..92cd19021084 100644
>--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
>+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
>@@ -307,9 +307,9 @@ nouveau_bo_init(struct nouveau_bo *nvbo, u64 size,
>int align, u32 domain,
>   nouveau_bo_placement_set(nvbo, domain, 0);
>   INIT_LIST_HEAD(>io_reserve_lru);
>
>-  ret = ttm_bo_init(nvbo->bo.bdev, >bo, size, type,
>->placement, align >> PAGE_SHIFT, false, sg,
>-robj, nouveau_bo_del_ttm);
>+  ret = ttm_bo_init_validate(nvbo->bo.bdev, >bo, type,
>+ >placement, align >> PAGE_SHIFT,
>false,
>+ sg, robj, nouveau_bo_del_ttm);
>   if (ret) {
>   /* ttm will call nouveau_bo_del_ttm if it fails.. */
>   return ret;
>diff --git a/drivers/gpu/drm/qxl/qxl_object.c
>b/drivers/gpu/drm/qxl/qxl_object.c
>index b42a657e4c2f..695d9308d1f0 100644
>--- a/drivers/gpu/drm/qxl/qxl_object.c
>+++ b/drivers/gpu/drm/qxl/qxl_object.c
>@@ -141,7 +141,7 @@ int qxl_bo_create(struct qxl_device *qdev, unsigned
>long size,
>   qxl_ttm_placement_from_domain(bo, domain);
>
>   bo->tbo.priority = priority;
>-  r = 

Re: [PATCH 3/3] Revert "drm/amdgpu: add drm buddy support to amdgpu"

[Christian König]

Am 08.07.22 um 11:30 schrieb Arunpravin Paneer Selvam:

This reverts commit c9cad937c0c58618fe5b0310fd539a854dc1ae95.

This is part of a revert of the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function into the C 
file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in amdgpu_vram_mgr_new")
commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")

[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.

Signed-off-by: Arunpravin Paneer Selvam 


I've opted out to pushing only this one here to drm-misc-fixes since the 
other two patches actually didn't made it upstream in 5.19.


Please keep testing and trying to figure out why this doesn't work as 
expected in some circumstances.


Thanks,
Christian.


---
  drivers/gpu/drm/Kconfig   |   1 -
  .../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h|  97 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |  10 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c  | 359 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h  |  89 -
  5 files changed, 176 insertions(+), 380 deletions(-)
  delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 6c2256e8474b..d438d5ff8b40 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -272,7 +272,6 @@ config DRM_AMDGPU
select HWMON
select BACKLIGHT_CLASS_DEVICE
select INTERVAL_TREE
-   select DRM_BUDDY
help
  Choose this option if you have a recent AMD Radeon graphics card.
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h

index 6546552e596c..acfa207cf970 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -30,15 +30,12 @@
  #include 
  #include 
  
-#include "amdgpu_vram_mgr.h"

-
  /* state back for walking over vram_mgr and gtt_mgr allocations */
  struct amdgpu_res_cursor {
uint64_tstart;
uint64_tsize;
uint64_tremaining;
-   void*node;
-   uint32_tmem_type;
+   struct drm_mm_node  *node;
  };
  
  /**

@@ -55,63 +52,27 @@ static inline void amdgpu_res_first(struct ttm_resource 
*res,
uint64_t start, uint64_t size,
struct amdgpu_res_cursor *cur)
  {
-   struct drm_buddy_block *block;
-   struct list_head *head, *next;
struct drm_mm_node *node;
  
-	if (!res)

-   goto fallback;
-
-   BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
-
-   cur->mem_type = res->mem_type;
-
-   switch (cur->mem_type) {
-   case TTM_PL_VRAM:
-   head = _amdgpu_vram_mgr_resource(res)->blocks;
-
-   block = list_first_entry_or_null(head,
-struct drm_buddy_block,
-link);
-   if (!block)
-   goto fallback;
-
-   while (start >= amdgpu_vram_mgr_block_size(block)) {
-   start -= amdgpu_vram_mgr_block_size(block);
-
-   next = block->link.next;
-   if (next != head)
-   block = list_entry(next, struct 
drm_buddy_block, link);
-   }
-
-   cur->start = amdgpu_vram_mgr_block_start(block) + start;
-   cur->size = min(amdgpu_vram_mgr_block_size(block) - start, 
size);
-   cur->remaining = size;
-   cur->node = block;
-   break;
-   case TTM_PL_TT:
-   node = to_ttm_range_mgr_node(res)->mm_nodes;
-   while (start >= node->size << PAGE_SHIFT)
-   start -= node++->size << PAGE_SHIFT;
-
-   cur->start = (node->start << PAGE_SHIFT) + start;
-   cur->size = min((node->size << PAGE_SHIFT) - start, size);
+   if (!res || res->mem_type == TTM_PL_SYSTEM) {
+   cur->start = start;
+   cur->size = size;
cur->remaining = size;
-   cur->node = node;
-   break;
-   default:
-   goto fallback;
+   cur->node = NULL;
+   WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT);
+   return;
}
  
-	return;

+   BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
  
-fallback:

-   cur->start = start;
-   cur->size = size;
+   node = to_ttm_range_mgr_node(res)->mm_nodes;
+   while (start >= node->size << PAGE_SHIFT)
+   start -= node++->size << PAGE_SHIFT;
+
+   cur->start = (node->start << PAGE_SHIFT) + start;
+   cur->size = min((node->size << PAGE_SHIFT) - start, size);

Re: [PATCH 1/3] Revert "drm/amdgpu: move internal vram_mgr function into the C file"

[Arunpravin Paneer Selvam]

On 7/8/2022 3:03 PM, Christian König wrote:

Am 08.07.22 um 11:30 schrieb Arunpravin Paneer Selvam:

This reverts commit 708d19d9f362766147cab79eccae60912c6d3068.

This is part of a revert of the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function 
into the C file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in 
amdgpu_vram_mgr_new")

commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")

[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.


Please squash all three patches into a single one. Apart from that 
looks good to me.


I sent a new patch squashing all the three patches into a single one.

Thanks,
Arun


Christian.



Signed-off-by: Arunpravin Paneer Selvam 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 29 
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 27 ++
  2 files changed, 27 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

index 7a5e8a7b4a1b..51d9d3a4456c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -50,35 +50,6 @@ to_amdgpu_device(struct amdgpu_vram_mgr *mgr)
  return container_of(mgr, struct amdgpu_device, mman.vram_mgr);
  }
  -static inline struct drm_buddy_block *
-amdgpu_vram_mgr_first_block(struct list_head *list)
-{
-    return list_first_entry_or_null(list, struct drm_buddy_block, 
link);

-}
-
-static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct 
list_head *head)

-{
-    struct drm_buddy_block *block;
-    u64 start, size;
-
-    block = amdgpu_vram_mgr_first_block(head);
-    if (!block)
-    return false;
-
-    while (head != block->link.next) {
-    start = amdgpu_vram_mgr_block_start(block);
-    size = amdgpu_vram_mgr_block_size(block);
-
-    block = list_entry(block->link.next, struct drm_buddy_block, 
link);

-    if (start + size != amdgpu_vram_mgr_block_start(block))
-    return false;
-    }
-
-    return true;
-}
-
-
-
  /**
   * DOC: mem_info_vram_total
   *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h

index 4b267bf1c5db..9a2db87186c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
@@ -53,6 +53,33 @@ static inline u64 
amdgpu_vram_mgr_block_size(struct drm_buddy_block *block)

  return PAGE_SIZE << drm_buddy_block_order(block);
  }
  +static inline struct drm_buddy_block *
+amdgpu_vram_mgr_first_block(struct list_head *list)
+{
+    return list_first_entry_or_null(list, struct drm_buddy_block, 
link);

+}
+
+static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct 
list_head *head)

+{
+    struct drm_buddy_block *block;
+    u64 start, size;
+
+    block = amdgpu_vram_mgr_first_block(head);
+    if (!block)
+    return false;
+
+    while (head != block->link.next) {
+    start = amdgpu_vram_mgr_block_start(block);
+    size = amdgpu_vram_mgr_block_size(block);
+
+    block = list_entry(block->link.next, struct drm_buddy_block, 
link);

+    if (start + size != amdgpu_vram_mgr_block_start(block))
+    return false;
+    }
+
+    return true;
+}
+
  static inline struct amdgpu_vram_mgr_resource *
  to_amdgpu_vram_mgr_resource(struct ttm_resource *res)
  {

[PATCH] Revert "drm/amdgpu: add drm buddy support to amdgpu"

[Arunpravin Paneer Selvam]

This reverts the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function into the C 
file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in amdgpu_vram_mgr_new")
commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")

[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.

Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/Kconfig   |   1 -
 .../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h|  97 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |  10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c  | 394 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h  |  62 ---
 5 files changed, 176 insertions(+), 388 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 6c2256e8474b..d438d5ff8b40 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -272,7 +272,6 @@ config DRM_AMDGPU
select HWMON
select BACKLIGHT_CLASS_DEVICE
select INTERVAL_TREE
-   select DRM_BUDDY
help
  Choose this option if you have a recent AMD Radeon graphics card.
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index 6546552e596c..acfa207cf970 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -30,15 +30,12 @@
 #include 
 #include 
 
-#include "amdgpu_vram_mgr.h"
-
 /* state back for walking over vram_mgr and gtt_mgr allocations */
 struct amdgpu_res_cursor {
uint64_tstart;
uint64_tsize;
uint64_tremaining;
-   void*node;
-   uint32_tmem_type;
+   struct drm_mm_node  *node;
 };
 
 /**
@@ -55,63 +52,27 @@ static inline void amdgpu_res_first(struct ttm_resource 
*res,
uint64_t start, uint64_t size,
struct amdgpu_res_cursor *cur)
 {
-   struct drm_buddy_block *block;
-   struct list_head *head, *next;
struct drm_mm_node *node;
 
-   if (!res)
-   goto fallback;
-
-   BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
-
-   cur->mem_type = res->mem_type;
-
-   switch (cur->mem_type) {
-   case TTM_PL_VRAM:
-   head = _amdgpu_vram_mgr_resource(res)->blocks;
-
-   block = list_first_entry_or_null(head,
-struct drm_buddy_block,
-link);
-   if (!block)
-   goto fallback;
-
-   while (start >= amdgpu_vram_mgr_block_size(block)) {
-   start -= amdgpu_vram_mgr_block_size(block);
-
-   next = block->link.next;
-   if (next != head)
-   block = list_entry(next, struct 
drm_buddy_block, link);
-   }
-
-   cur->start = amdgpu_vram_mgr_block_start(block) + start;
-   cur->size = min(amdgpu_vram_mgr_block_size(block) - start, 
size);
-   cur->remaining = size;
-   cur->node = block;
-   break;
-   case TTM_PL_TT:
-   node = to_ttm_range_mgr_node(res)->mm_nodes;
-   while (start >= node->size << PAGE_SHIFT)
-   start -= node++->size << PAGE_SHIFT;
-
-   cur->start = (node->start << PAGE_SHIFT) + start;
-   cur->size = min((node->size << PAGE_SHIFT) - start, size);
+   if (!res || res->mem_type == TTM_PL_SYSTEM) {
+   cur->start = start;
+   cur->size = size;
cur->remaining = size;
-   cur->node = node;
-   break;
-   default:
-   goto fallback;
+   cur->node = NULL;
+   WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT);
+   return;
}
 
-   return;
+   BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
 
-fallback:
-   cur->start = start;
-   cur->size = size;
+   node = to_ttm_range_mgr_node(res)->mm_nodes;
+   while (start >= node->size << PAGE_SHIFT)
+   start -= node++->size << PAGE_SHIFT;
+
+   cur->start = (node->start << PAGE_SHIFT) + start;
+   cur->size = min((node->size << PAGE_SHIFT) - start, size);
cur->remaining = size;
-   cur->node = NULL;
-   WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT);
-   return;
+   cur->node = node;
 }
 
 /**
@@ -124,9 +85,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
  */
 static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t 
size)
 {
-   struct drm_buddy_block *block;
-   struct drm_mm_node *node;
-  

[PATCH] drm/amdgpu: correct psp version number

[Yifan Zhang]

it should be 13.0.4 rather than 13.0.5

Fixes: a9cf7e4bd3f4b896c38848106ab3fb3f2c2dfe4b

Signed-off-by: Yifan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   | 2 +-
 drivers/gpu/drm/amd/amdgpu/psp_v13_0.c| 6 +++---
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 37234c2998d7..74060de9cc19 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1631,7 +1631,6 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct 
amdgpu_device *adev)
case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 4):
-   case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 7):
case IP_VERSION(13, 0, 8):
amdgpu_device_ip_block_add(adev, _v13_0_ip_block);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index e9411c28d88b..520609d12d32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -135,7 +135,7 @@ static int psp_early_init(void *handle)
break;
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
-   case IP_VERSION(13, 0, 5):
+   case IP_VERSION(13, 0, 4):
case IP_VERSION(13, 0, 8):
psp_v13_0_set_psp_funcs(psp);
psp->autoload_supported = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 30386d34d0d6..56e2fd5d4a4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -34,8 +34,8 @@ MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
-MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
-MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
+MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
+MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
@@ -93,7 +93,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
break;
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
-   case IP_VERSION(13, 0, 5):
+   case IP_VERSION(13, 0, 4):
case IP_VERSION(13, 0, 8):
err = psp_init_toc_microcode(psp, chip_name);
if (err)
-- 
2.35.1

Re: [PATCH] drm/amdgpu/gmc10: adjust gart size for parts that support S/G display

[Christian König]

Am 07.07.22 um 22:55 schrieb Alex Deucher:

For GMC 10 parts which support scatter/gather display (display
from system memory), we should allocate a larger gart size
to better handler larger displays.  This mirrors what we already
do for GMC 9 parts.

v2: fix typo (Alex)

Signed-off-by: Alex Deucher 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 17 ++---
  1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 25d5743ae91b..1772f006c61a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -834,10 +834,21 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
  
  	/* set the gart size */

-   if (amdgpu_gart_size == -1)
-   adev->gmc.gart_size = 512ULL << 20;
-   else
+   if (amdgpu_gart_size == -1) {
+   switch (adev->ip_versions[GC_HWIP][0]) {
+   default:
+   adev->gmc.gart_size = 512ULL << 20;
+   break;
+   case IP_VERSION(10, 3, 1):   /* DCE SG support */
+   case IP_VERSION(10, 3, 3):   /* DCE SG support */
+   case IP_VERSION(10, 3, 6):   /* DCE SG support */
+   case IP_VERSION(10, 3, 7):   /* DCE SG support */
+   adev->gmc.gart_size = 1024ULL << 20;
+   break;
+   }
+   } else {
adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+   }
  
  	gmc_v10_0_vram_gtt_location(adev, >gmc);
  

Re: [PATCH] drm/amdgpu: Remove one duplicated ef removal

[Christian König]

Am 08.07.22 um 03:53 schrieb xinhui pan:

That has been done in BO release notify.

Signed-off-by: xinhui pan 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 -
  1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 0f9811d02f61..49536fa8d269 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1583,11 +1583,6 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device 
*adev,
if (!process_info)
return;
  
-	/* Release eviction fence from PD */

-   amdgpu_bo_reserve(pd, false);
-   amdgpu_bo_fence(pd, NULL, false);
-   amdgpu_bo_unreserve(pd);
-
/* Update process info */
mutex_lock(_info->lock);
process_info->n_vms--;

Re: [linux-next:master] BUILD REGRESSION 088b9c375534d905a4d337c78db3b3bfbb52c4a0

[Dan Carpenter]

On Thu, Jul 07, 2022 at 07:02:58AM -0700, Guenter Roeck wrote:
> and the NULL
> dereferences in the binder driver are at the very least suspicious.

The NULL dereferences in binder are just nonsense Sparse annotations.
They don't affect runtime.

drivers/android/binder.c:1481:19-23: ERROR: from is NULL but dereferenced.
drivers/android/binder.c:2920:29-33: ERROR: target_thread is NULL but 
dereferenced.
drivers/android/binder.c:353:25-35: ERROR: node -> proc is NULL but 
dereferenced.
drivers/android/binder.c:4888:16-20: ERROR: t is NULL but dereferenced.

regards,
dan carpenter

Re: [PATCH 1/3] Revert "drm/amdgpu: move internal vram_mgr function into the C file"

[Christian König]

Am 08.07.22 um 11:30 schrieb Arunpravin Paneer Selvam:

This reverts commit 708d19d9f362766147cab79eccae60912c6d3068.

This is part of a revert of the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function into the C 
file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in amdgpu_vram_mgr_new")
commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")

[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.


Please squash all three patches into a single one. Apart from that looks 
good to me.


Christian.



Signed-off-by: Arunpravin Paneer Selvam 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 29 
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 27 ++
  2 files changed, 27 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 7a5e8a7b4a1b..51d9d3a4456c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -50,35 +50,6 @@ to_amdgpu_device(struct amdgpu_vram_mgr *mgr)
return container_of(mgr, struct amdgpu_device, mman.vram_mgr);
  }
  
-static inline struct drm_buddy_block *

-amdgpu_vram_mgr_first_block(struct list_head *list)
-{
-   return list_first_entry_or_null(list, struct drm_buddy_block, link);
-}
-
-static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct list_head *head)
-{
-   struct drm_buddy_block *block;
-   u64 start, size;
-
-   block = amdgpu_vram_mgr_first_block(head);
-   if (!block)
-   return false;
-
-   while (head != block->link.next) {
-   start = amdgpu_vram_mgr_block_start(block);
-   size = amdgpu_vram_mgr_block_size(block);
-
-   block = list_entry(block->link.next, struct drm_buddy_block, 
link);
-   if (start + size != amdgpu_vram_mgr_block_start(block))
-   return false;
-   }
-
-   return true;
-}
-
-
-
  /**
   * DOC: mem_info_vram_total
   *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
index 4b267bf1c5db..9a2db87186c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
@@ -53,6 +53,33 @@ static inline u64 amdgpu_vram_mgr_block_size(struct 
drm_buddy_block *block)
return PAGE_SIZE << drm_buddy_block_order(block);
  }
  
+static inline struct drm_buddy_block *

+amdgpu_vram_mgr_first_block(struct list_head *list)
+{
+   return list_first_entry_or_null(list, struct drm_buddy_block, link);
+}
+
+static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct list_head *head)
+{
+   struct drm_buddy_block *block;
+   u64 start, size;
+
+   block = amdgpu_vram_mgr_first_block(head);
+   if (!block)
+   return false;
+
+   while (head != block->link.next) {
+   start = amdgpu_vram_mgr_block_start(block);
+   size = amdgpu_vram_mgr_block_size(block);
+
+   block = list_entry(block->link.next, struct drm_buddy_block, 
link);
+   if (start + size != amdgpu_vram_mgr_block_start(block))
+   return false;
+   }
+
+   return true;
+}
+
  static inline struct amdgpu_vram_mgr_resource *
  to_amdgpu_vram_mgr_resource(struct ttm_resource *res)
  {

[PATCH 3/3] Revert "drm/amdgpu: add drm buddy support to amdgpu"

[Arunpravin Paneer Selvam]

This reverts commit c9cad937c0c58618fe5b0310fd539a854dc1ae95.

This is part of a revert of the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function into the C 
file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in amdgpu_vram_mgr_new")
commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")

[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.

Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/Kconfig   |   1 -
 .../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h|  97 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |  10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c  | 359 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h  |  89 -
 5 files changed, 176 insertions(+), 380 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 6c2256e8474b..d438d5ff8b40 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -272,7 +272,6 @@ config DRM_AMDGPU
select HWMON
select BACKLIGHT_CLASS_DEVICE
select INTERVAL_TREE
-   select DRM_BUDDY
help
  Choose this option if you have a recent AMD Radeon graphics card.
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index 6546552e596c..acfa207cf970 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -30,15 +30,12 @@
 #include 
 #include 
 
-#include "amdgpu_vram_mgr.h"
-
 /* state back for walking over vram_mgr and gtt_mgr allocations */
 struct amdgpu_res_cursor {
uint64_tstart;
uint64_tsize;
uint64_tremaining;
-   void*node;
-   uint32_tmem_type;
+   struct drm_mm_node  *node;
 };
 
 /**
@@ -55,63 +52,27 @@ static inline void amdgpu_res_first(struct ttm_resource 
*res,
uint64_t start, uint64_t size,
struct amdgpu_res_cursor *cur)
 {
-   struct drm_buddy_block *block;
-   struct list_head *head, *next;
struct drm_mm_node *node;
 
-   if (!res)
-   goto fallback;
-
-   BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
-
-   cur->mem_type = res->mem_type;
-
-   switch (cur->mem_type) {
-   case TTM_PL_VRAM:
-   head = _amdgpu_vram_mgr_resource(res)->blocks;
-
-   block = list_first_entry_or_null(head,
-struct drm_buddy_block,
-link);
-   if (!block)
-   goto fallback;
-
-   while (start >= amdgpu_vram_mgr_block_size(block)) {
-   start -= amdgpu_vram_mgr_block_size(block);
-
-   next = block->link.next;
-   if (next != head)
-   block = list_entry(next, struct 
drm_buddy_block, link);
-   }
-
-   cur->start = amdgpu_vram_mgr_block_start(block) + start;
-   cur->size = min(amdgpu_vram_mgr_block_size(block) - start, 
size);
-   cur->remaining = size;
-   cur->node = block;
-   break;
-   case TTM_PL_TT:
-   node = to_ttm_range_mgr_node(res)->mm_nodes;
-   while (start >= node->size << PAGE_SHIFT)
-   start -= node++->size << PAGE_SHIFT;
-
-   cur->start = (node->start << PAGE_SHIFT) + start;
-   cur->size = min((node->size << PAGE_SHIFT) - start, size);
+   if (!res || res->mem_type == TTM_PL_SYSTEM) {
+   cur->start = start;
+   cur->size = size;
cur->remaining = size;
-   cur->node = node;
-   break;
-   default:
-   goto fallback;
+   cur->node = NULL;
+   WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT);
+   return;
}
 
-   return;
+   BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
 
-fallback:
-   cur->start = start;
-   cur->size = size;
+   node = to_ttm_range_mgr_node(res)->mm_nodes;
+   while (start >= node->size << PAGE_SHIFT)
+   start -= node++->size << PAGE_SHIFT;
+
+   cur->start = (node->start << PAGE_SHIFT) + start;
+   cur->size = min((node->size << PAGE_SHIFT) - start, size);
cur->remaining = size;
-   cur->node = NULL;
-   WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT);
-   return;
+   cur->node = node;
 }
 
 /**
@@ -124,9 +85,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
  */
 static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t 
size)
 {

[PATCH 2/3] Revert "drm/amdgpu: fix start calculation in amdgpu_vram_mgr_new"

[Arunpravin Paneer Selvam]

This reverts commit 5e3f1e7729ec7a99e145e9d8ed58963d86cdfb98.

This is part of a revert of the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function into the C 
file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in amdgpu_vram_mgr_new")
commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")

[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.

Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 22 +++-
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 51d9d3a4456c..49e4092f447f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -496,23 +496,17 @@ static int amdgpu_vram_mgr_new(struct 
ttm_resource_manager *man,
list_splice_tail(trim_list, >blocks);
}
 
-   vres->base.start = 0;
-   list_for_each_entry(block, >blocks, link) {
-   unsigned long start;
-
-   start = amdgpu_vram_mgr_block_start(block) +
-   amdgpu_vram_mgr_block_size(block);
-   start >>= PAGE_SHIFT;
-
-   if (start > vres->base.num_pages)
-   start -= vres->base.num_pages;
-   else
-   start = 0;
-   vres->base.start = max(vres->base.start, start);
-
+   list_for_each_entry(block, >blocks, link)
vis_usage += amdgpu_vram_mgr_vis_size(adev, block);
+
+   block = amdgpu_vram_mgr_first_block(>blocks);
+   if (!block) {
+   r = -EINVAL;
+   goto error_fini;
}
 
+   vres->base.start = amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT;
+
if (amdgpu_is_vram_mgr_blocks_contiguous(>blocks))
vres->base.placement |= TTM_PL_FLAG_CONTIGUOUS;
 
-- 
2.25.1

[PATCH 1/3] Revert "drm/amdgpu: move internal vram_mgr function into the C file"

[Arunpravin Paneer Selvam]

This reverts commit 708d19d9f362766147cab79eccae60912c6d3068.

This is part of a revert of the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function into the C 
file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in amdgpu_vram_mgr_new")
commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")

[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.

Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 29 
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 27 ++
 2 files changed, 27 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 7a5e8a7b4a1b..51d9d3a4456c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -50,35 +50,6 @@ to_amdgpu_device(struct amdgpu_vram_mgr *mgr)
return container_of(mgr, struct amdgpu_device, mman.vram_mgr);
 }
 
-static inline struct drm_buddy_block *
-amdgpu_vram_mgr_first_block(struct list_head *list)
-{
-   return list_first_entry_or_null(list, struct drm_buddy_block, link);
-}
-
-static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct list_head *head)
-{
-   struct drm_buddy_block *block;
-   u64 start, size;
-
-   block = amdgpu_vram_mgr_first_block(head);
-   if (!block)
-   return false;
-
-   while (head != block->link.next) {
-   start = amdgpu_vram_mgr_block_start(block);
-   size = amdgpu_vram_mgr_block_size(block);
-
-   block = list_entry(block->link.next, struct drm_buddy_block, 
link);
-   if (start + size != amdgpu_vram_mgr_block_start(block))
-   return false;
-   }
-
-   return true;
-}
-
-
-
 /**
  * DOC: mem_info_vram_total
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
index 4b267bf1c5db..9a2db87186c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
@@ -53,6 +53,33 @@ static inline u64 amdgpu_vram_mgr_block_size(struct 
drm_buddy_block *block)
return PAGE_SIZE << drm_buddy_block_order(block);
 }
 
+static inline struct drm_buddy_block *
+amdgpu_vram_mgr_first_block(struct list_head *list)
+{
+   return list_first_entry_or_null(list, struct drm_buddy_block, link);
+}
+
+static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct list_head *head)
+{
+   struct drm_buddy_block *block;
+   u64 start, size;
+
+   block = amdgpu_vram_mgr_first_block(head);
+   if (!block)
+   return false;
+
+   while (head != block->link.next) {
+   start = amdgpu_vram_mgr_block_start(block);
+   size = amdgpu_vram_mgr_block_size(block);
+
+   block = list_entry(block->link.next, struct drm_buddy_block, 
link);
+   if (start + size != amdgpu_vram_mgr_block_start(block))
+   return false;
+   }
+
+   return true;
+}
+
 static inline struct amdgpu_vram_mgr_resource *
 to_amdgpu_vram_mgr_resource(struct ttm_resource *res)
 {
-- 
2.25.1

RE: [PATCH 1/3] drm/amdgpu/mes: fix mes submission in atomic context

[Zhang, Hawking]

[AMD Official Use Only - General]

Series is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Xiao, Jack  
Sent: Friday, July 8, 2022 16:54
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Hawking 
Cc: Xiao, Jack 
Subject: [PATCH 1/3] drm/amdgpu/mes: fix mes submission in atomic context

For some cases (accessing registers, unmap legacy queue), it needs access mes 
in atomic context. Use spinlock to protect agaist mes ring buffer race 
condition.

Signed-off-by: Jack Xiao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 +--  
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h |  1 +  
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c  | 55 +  
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c  | 63 ++---
 4 files changed, 50 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index ca44aa123a1e..db2138b7a858 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -150,6 +150,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
idr_init(>mes.queue_id_idr);
ida_init(>mes.doorbell_ida);
spin_lock_init(>mes.queue_id_lock);
+   spin_lock_init(>mes.ring_lock);
mutex_init(>mes.mutex_hidden);
 
adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK; @@ -794,8 
+795,6 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
struct mes_unmap_legacy_queue_input queue_input;
int r;
 
-   amdgpu_mes_lock(>mes);
-
queue_input.action = action;
queue_input.queue_type = ring->funcs->type;
queue_input.doorbell_offset = ring->doorbell_index; @@ -808,7 +807,6 @@ 
int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
if (r)
DRM_ERROR("failed to unmap legacy queue\n");
 
-   amdgpu_mes_unlock(>mes);
return r;
 }
 
@@ -817,8 +815,6 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, 
uint32_t reg)
struct mes_misc_op_input op_input;
int r, val = 0;
 
-   amdgpu_mes_lock(>mes);
-
op_input.op = MES_MISC_OP_READ_REG;
op_input.read_reg.reg_offset = reg;
op_input.read_reg.buffer_addr = adev->mes.read_val_gpu_addr; @@ -835,7 
+831,6 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)
val = *(adev->mes.read_val_ptr);
 
 error:
-   amdgpu_mes_unlock(>mes);
return val;
 }
 
@@ -845,8 +840,6 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev,
struct mes_misc_op_input op_input;
int r;
 
-   amdgpu_mes_lock(>mes);
-
op_input.op = MES_MISC_OP_WRITE_REG;
op_input.write_reg.reg_offset = reg;
op_input.write_reg.reg_value = val;
@@ -862,7 +855,6 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev,
DRM_ERROR("failed to write reg (0x%x)\n", reg);
 
 error:
-   amdgpu_mes_unlock(>mes);
return r;
 }
 
@@ -873,8 +865,6 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device 
*adev,
struct mes_misc_op_input op_input;
int r;
 
-   amdgpu_mes_lock(>mes);
-
op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT;
op_input.wrm_reg.reg0 = reg0;
op_input.wrm_reg.reg1 = reg1;
@@ -892,7 +882,6 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device 
*adev,
DRM_ERROR("failed to reg_write_reg_wait\n");
 
 error:
-   amdgpu_mes_unlock(>mes);
return r;
 }
 
@@ -902,8 +891,6 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, 
uint32_t reg,
struct mes_misc_op_input op_input;
int r;
 
-   amdgpu_mes_lock(>mes);
-
op_input.op = MES_MISC_OP_WRM_REG_WAIT;
op_input.wrm_reg.reg0 = reg;
op_input.wrm_reg.ref = val;
@@ -920,7 +907,6 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, 
uint32_t reg,
DRM_ERROR("failed to reg_write_reg_wait\n");
 
 error:
-   amdgpu_mes_unlock(>mes);
return r;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 17d58a08bbb7..02daffbda02d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -82,6 +82,7 @@ struct amdgpu_mes {
uint64_tdefault_gang_quantum;
 
struct amdgpu_ring  ring;
+   spinlock_t  ring_lock;
 
const struct firmware   *fw[AMDGPU_MAX_MES_PIPES];
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 
b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 18a129f36215..75cf92d38d41 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -87,21 +87,32 @@ static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs 
= {  };
 
 static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
-   void *pkt, int size)
+  

Re: [PATCH] drm/amdgpu: Fix a NULL pointer of fence

[Christian König]

Hi guys,

well the practice to remove all fences by adding a NULL exclusive fence 
was pretty much illegal in the first place because this also removes 
kernel internal fences which can lead to freeing up memory which is 
still accessed.


I've just didn't noticed that this was used by the KFD code as well 
otherwise I would have pushed to clean that up much earlier.


Regards,
Christian.

Am 08.07.22 um 03:08 schrieb Pan, Xinhui:

[AMD Official Use Only - General]

Felix,
Shared fences depend on exclusive fence, so add a new exclusive fence, say NULL 
would also remove all shared fences. That works before 5.18 . 
 From 5.18, adding a new exclusive fence(the write usage fence) did not remove 
any shared fences(the read usage fence). So that is broken.

And I also try the debug_evictions parameter. No unexpected eviction shows 
anyway.
I did a quick check and found amdgpu implement BO release notify and it will remove kfd 
ef on pt/pd BO. So we don’t need this duplicated ef removal. The interesting thing is 
that is done by patch f4a3c42b5c52("drm/amdgpu: Remove kfd eviction fence before 
release bo (v2)") which is from me  I totally forgot it.

So I would make a new patch to remove this duplicated ef removal.

-Original Message-
From: Kuehling, Felix 
Sent: Thursday, July 7, 2022 11:47 PM
To: Christian König ; Pan, Xinhui 
; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian 

Subject: Re: [PATCH] drm/amdgpu: Fix a NULL pointer of fence

Am 2022-07-07 um 05:54 schrieb Christian König:

Am 07.07.22 um 11:50 schrieb xinhui pan:

Fence is accessed by dma_resv_add_fence() now.
Use amdgpu_amdkfd_remove_eviction_fence instead.

Signed-off-by: xinhui pan 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++--
   1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 0036c9e405af..1e25c400ce4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1558,10 +1558,10 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct
amdgpu_device *adev,
 if (!process_info)
   return;
-
   /* Release eviction fence from PD */
   amdgpu_bo_reserve(pd, false);
-amdgpu_bo_fence(pd, NULL, false);
+amdgpu_amdkfd_remove_eviction_fence(pd,
+process_info->eviction_fence);

Good catch as well, but Felix needs to take a look at this.

This is weird. We used amdgpu_bo_fence(pd, NULL, false) here, which would have 
removed an exclusive fence. But as far as I can tell we added the fence as a 
shared fence in init_kfd_vm and amdgpu_amdkfd_gpuvm_restore_process_bos. So 
this probably never worked as intended.

You could try if this is really needed. Just remove the eviction fence removal. 
Then enable eviction debugging with

  echo Y > /sys/module/amdgpu/parameters/debug_evictions

Run some simple tests and check the kernel log to see if process termination is 
causing any unexpected evictions.

Regards,
Felix



Regards,
Christian.


   amdgpu_bo_unreserve(pd);
 /* Update process info */

[PATCH 3/3] drm/amdgpu/mes: set correct mes ring ready flag

[Jack Xiao]

Set corresponding ready flag for mes ring when enable or disable
mes ring.

Signed-off-by: Jack Xiao 
---
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 3 +++
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 
b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 75cf92d38d41..88317e77c0a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -1124,6 +1124,7 @@ static int mes_v10_1_hw_init(void *handle)
 * with MES enabled.
 */
adev->gfx.kiq.ring.sched.ready = false;
+   adev->mes.ring.sched.ready = true;
 
return 0;
 
@@ -1136,6 +1137,8 @@ static int mes_v10_1_hw_fini(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+   adev->mes.ring.sched.ready = false;
+
mes_v10_1_enable(adev, false);
 
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index b78e09910c7c..8dbce32fd9cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1190,6 +1190,9 @@ static int mes_v11_0_hw_init(void *handle)
 
 static int mes_v11_0_hw_fini(void *handle)
 {
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   adev->mes.ring.sched.ready = false;
return 0;
 }
 
-- 
2.35.1

[PATCH 1/3] drm/amdgpu/mes: fix mes submission in atomic context

[Jack Xiao]

For some cases (accessing registers, unmap legacy queue), it needs
access mes in atomic context. Use spinlock to protect agaist mes
ring buffer race condition.

Signed-off-by: Jack Xiao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h |  1 +
 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c  | 55 +
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c  | 63 ++---
 4 files changed, 50 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index ca44aa123a1e..db2138b7a858 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -150,6 +150,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
idr_init(>mes.queue_id_idr);
ida_init(>mes.doorbell_ida);
spin_lock_init(>mes.queue_id_lock);
+   spin_lock_init(>mes.ring_lock);
mutex_init(>mes.mutex_hidden);
 
adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK;
@@ -794,8 +795,6 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device 
*adev,
struct mes_unmap_legacy_queue_input queue_input;
int r;
 
-   amdgpu_mes_lock(>mes);
-
queue_input.action = action;
queue_input.queue_type = ring->funcs->type;
queue_input.doorbell_offset = ring->doorbell_index;
@@ -808,7 +807,6 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device 
*adev,
if (r)
DRM_ERROR("failed to unmap legacy queue\n");
 
-   amdgpu_mes_unlock(>mes);
return r;
 }
 
@@ -817,8 +815,6 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, 
uint32_t reg)
struct mes_misc_op_input op_input;
int r, val = 0;
 
-   amdgpu_mes_lock(>mes);
-
op_input.op = MES_MISC_OP_READ_REG;
op_input.read_reg.reg_offset = reg;
op_input.read_reg.buffer_addr = adev->mes.read_val_gpu_addr;
@@ -835,7 +831,6 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, 
uint32_t reg)
val = *(adev->mes.read_val_ptr);
 
 error:
-   amdgpu_mes_unlock(>mes);
return val;
 }
 
@@ -845,8 +840,6 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev,
struct mes_misc_op_input op_input;
int r;
 
-   amdgpu_mes_lock(>mes);
-
op_input.op = MES_MISC_OP_WRITE_REG;
op_input.write_reg.reg_offset = reg;
op_input.write_reg.reg_value = val;
@@ -862,7 +855,6 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev,
DRM_ERROR("failed to write reg (0x%x)\n", reg);
 
 error:
-   amdgpu_mes_unlock(>mes);
return r;
 }
 
@@ -873,8 +865,6 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device 
*adev,
struct mes_misc_op_input op_input;
int r;
 
-   amdgpu_mes_lock(>mes);
-
op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT;
op_input.wrm_reg.reg0 = reg0;
op_input.wrm_reg.reg1 = reg1;
@@ -892,7 +882,6 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device 
*adev,
DRM_ERROR("failed to reg_write_reg_wait\n");
 
 error:
-   amdgpu_mes_unlock(>mes);
return r;
 }
 
@@ -902,8 +891,6 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, 
uint32_t reg,
struct mes_misc_op_input op_input;
int r;
 
-   amdgpu_mes_lock(>mes);
-
op_input.op = MES_MISC_OP_WRM_REG_WAIT;
op_input.wrm_reg.reg0 = reg;
op_input.wrm_reg.ref = val;
@@ -920,7 +907,6 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, 
uint32_t reg,
DRM_ERROR("failed to reg_write_reg_wait\n");
 
 error:
-   amdgpu_mes_unlock(>mes);
return r;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 17d58a08bbb7..02daffbda02d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -82,6 +82,7 @@ struct amdgpu_mes {
uint64_tdefault_gang_quantum;
 
struct amdgpu_ring  ring;
+   spinlock_t  ring_lock;
 
const struct firmware   *fw[AMDGPU_MAX_MES_PIPES];
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c 
b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 18a129f36215..75cf92d38d41 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -87,21 +87,32 @@ static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs 
= {
 };
 
 static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
-   void *pkt, int size)
+   void *pkt, int size,
+   int api_status_off)
 {
int ndw = size / 4;
signed long r;
union MESAPI__ADD_QUEUE *x_pkt = pkt;
+   struct MES_API_STATUS *api_status;
struct amdgpu_device *adev = mes->adev;
struct 

[PATCH 2/3] drm/amdgpu/mes: fix bo va unmap issue in mes

[Jack Xiao]

Need reserve buffers before unmap mes ctx bo va.

Signed-off-by: Jack Xiao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 59 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h |  2 +
 2 files changed, 58 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index db2138b7a858..de80161fb27b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -1174,6 +1174,61 @@ int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device 
*adev,
return r;
 }
 
+int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,
+  struct amdgpu_mes_ctx_data *ctx_data)
+{
+   struct amdgpu_bo_va *bo_va = ctx_data->meta_data_va;
+   struct amdgpu_bo *bo = ctx_data->meta_data_obj;
+   struct amdgpu_vm *vm = bo_va->base.vm;
+   struct amdgpu_bo_list_entry vm_pd;
+   struct list_head list, duplicates;
+   struct dma_fence *fence = NULL;
+   struct ttm_validate_buffer tv;
+   struct ww_acquire_ctx ticket;
+   long r = 0;
+
+   INIT_LIST_HEAD();
+   INIT_LIST_HEAD();
+
+   tv.bo = >tbo;
+   tv.num_shared = 2;
+   list_add(, );
+
+   amdgpu_vm_get_pd_bo(vm, , _pd);
+
+   r = ttm_eu_reserve_buffers(, , false, );
+   if (r) {
+   dev_err(adev->dev, "leaking bo va because "
+   "we fail to reserve bo (%ld)\n", r);
+   return r;
+   }
+
+   amdgpu_vm_bo_del(adev, bo_va);
+   if (!amdgpu_vm_ready(vm))
+   goto out_unlock;
+
+   fence = dma_resv_excl_fence(bo->tbo.base.resv);
+   if (fence) {
+   amdgpu_bo_fence(bo, fence, true);
+   fence = NULL;
+   }
+
+   r = amdgpu_vm_clear_freed(adev, vm, );
+   if (r || !fence)
+   goto out_unlock;
+
+   dma_fence_wait(fence, false);
+   amdgpu_bo_fence(bo, fence, true);
+   dma_fence_put(fence);
+
+out_unlock:
+   if (unlikely(r < 0))
+   dev_err(adev->dev, "failed to clear page tables (%ld)\n", r);
+   ttm_eu_backoff_reservation(, );
+
+   return r;
+}
+
 static int amdgpu_mes_test_create_gang_and_queues(struct amdgpu_device *adev,
  int pasid, int *gang_id,
  int queue_type, int num_queue,
@@ -1335,9 +1390,7 @@ int amdgpu_mes_self_test(struct amdgpu_device *adev)
amdgpu_mes_destroy_process(adev, pasid);
 
 error_vm:
-   BUG_ON(amdgpu_bo_reserve(ctx_data.meta_data_obj, true));
-   amdgpu_vm_bo_del(adev, ctx_data.meta_data_va);
-   amdgpu_bo_unreserve(ctx_data.meta_data_obj);
+   amdgpu_mes_ctx_unmap_meta_data(adev, _data);
 
 error_fini:
amdgpu_vm_fini(adev, vm);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 02daffbda02d..3730df05f6b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -352,6 +352,8 @@ void amdgpu_mes_ctx_free_meta_data(struct 
amdgpu_mes_ctx_data *ctx_data);
 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,
 struct amdgpu_vm *vm,
 struct amdgpu_mes_ctx_data *ctx_data);
+int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,
+  struct amdgpu_mes_ctx_data *ctx_data);
 
 int amdgpu_mes_self_test(struct amdgpu_device *adev);
 
-- 
2.35.1