[PATCH 1/2] drm/amdgpu: added a sysfs interface for thermal throttling
added a sysfs interface for thermal throttling, then userspace can get/update
thermal limit
Jira ID: SWDEV-354511
Signed-off-by: Kun Liu
Change-Id: I9948cb8966b731d2d74d7aad87cbcdc840dd34c8
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 2 +
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 28 +++
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 76 +++
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 24 ++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 12 +++
6 files changed, 145 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index f3d64c78f..8394464ea 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -331,6 +331,8 @@ struct amd_pm_funcs {
int (*get_mclk_od)(void *handle);
int (*set_mclk_od)(void *handle, uint32_t value);
int (*read_sensor)(void *handle, int idx, void *value, int *size);
+ int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
+ int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
enum amd_dpm_forced_level (*get_performance_level)(void *handle);
enum amd_pm_state_type (*get_current_power_state)(void *handle);
int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 1b300c569..d9a9cf189 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -438,6 +438,34 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev,
enum amd_pp_sensors senso
return ret;
}
+int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t
*limit)
+{
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+ int ret = -EINVAL;
+
+ if (pp_funcs && pp_funcs->get_apu_thermal_limit) {
+ mutex_lock(&adev->pm.mutex);
+ ret =
pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit);
+ mutex_unlock(&adev->pm.mutex);
+ }
+
+ return ret;
+}
+
+int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t
limit)
+{
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+ int ret = -EINVAL;
+
+ if (pp_funcs && pp_funcs->set_apu_thermal_limit) {
+ mutex_lock(&adev->pm.mutex);
+ ret =
pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit);
+ mutex_unlock(&adev->pm.mutex);
+ }
+
+ return ret;
+}
+
void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev)
{
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 236657eec..99b249e55 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1685,6 +1685,81 @@ static ssize_t
amdgpu_set_thermal_throttling_logging(struct device *dev,
return count;
}
+/**
+ * DOC: apu_thermal_cap
+ *
+ * The amdgpu driver provides a sysfs API for retrieving/updating thermal
+ * limit temperature in millidegrees Celsius
+ *
+ * Reading back the file shows you core limit value
+ *
+ * Writing an integer to the file, sets a new thermal limit. The value
+ * should be between 0 and 100. If the value is less than 0 or greater
+ * than 100, then the write request will be ignored.
+ */
+static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
+struct device_attribute *attr,
+char *buf)
+{
+ int ret, size = 0;
+ u32 limit;
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ ret = pm_runtime_get_sync(ddev->dev);
+ if (ret < 0) {
+ pm_runtime_put_autosuspend(ddev->dev);
+ return size;
+ }
+
+ ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
+ if (!ret)
+ size = sysfs_emit(buf, "%u\n", limit);
+ else
+ size = sysfs_emit(buf, "failed to get thermal limit\n");
+
+ pm_runtime_mark_last_busy(ddev->dev);
+ pm_runtime_put_autosuspend(ddev->dev);
+
+ return size;
+}
+
+static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
+struct device_attribute *attr,
+const char *buf,
+size_t count)
+{
+ int ret;
+ u32 value;
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ ret = kstrtou32(buf, 10, &value);
+ if (ret)
+ return ret;
+
+ if (value < 0 || value > 100) {
+ dev_err(dev, "Invalid argument !\n");
+ return coun
[PATCH 3/3] drm/ttm: Change the meaning of the fields in the drm_mm_nodes structure from pfn to bytes v2
From: Somalapuram Amaranath
Change the ttm_range_man_alloc() allocation from pages to size in bytes.
Fix the dependent drm_mm_nodes start and size from pages to bytes.
v2 (chk): Change the drm_mm_node usage in amdgpu as well. re-order the
patch to be independent of the resource->start change.
Signed-off-by: Somalapuram Amaranath
Reviewed-by: Christian König
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c| 15 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h | 8
drivers/gpu/drm/i915/i915_scatterlist.c| 6 +++---
drivers/gpu/drm/ttm/ttm_range_manager.c| 17 -
4 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 44367f03316f..c90423cd1292 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -116,7 +116,6 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager
*man,
struct ttm_resource **res)
{
struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
- uint32_t num_pages = PFN_UP(tbo->base.size);
struct ttm_range_mgr_node *node;
int r;
@@ -134,17 +133,19 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager
*man,
if (place->lpfn) {
spin_lock(&mgr->lock);
r = drm_mm_insert_node_in_range(&mgr->mm, &node->mm_nodes[0],
- num_pages, tbo->page_alignment,
- 0, place->fpfn, place->lpfn,
+ tbo->base.size,
+ tbo->page_alignment <<
PAGE_SHIFT, 0,
+ place->fpfn << PAGE_SHIFT,
+ place->lpfn << PAGE_SHIFT,
DRM_MM_INSERT_BEST);
spin_unlock(&mgr->lock);
if (unlikely(r))
goto err_free;
- node->base.start = node->mm_nodes[0].start;
+ node->base.start = node->mm_nodes[0].start >> PAGE_SHIFT;
} else {
node->mm_nodes[0].start = 0;
- node->mm_nodes[0].size = PFN_UP(node->base.size);
+ node->mm_nodes[0].size = node->base.size;
node->base.start = AMDGPU_BO_INVALID_OFFSET;
}
@@ -285,8 +286,8 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev,
uint64_t gtt_size)
ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size);
- start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
- size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
+ start = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
AMDGPU_GTT_NUM_TRANSFER_WINDOWS) << PAGE_SHIFT;
+ size = adev->gmc.gart_size - start;
drm_mm_init(&mgr->mm, start, size);
spin_lock_init(&mgr->lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index 5c4f93ee0c57..5c78f0b09351 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -94,8 +94,8 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
while (start >= node->size << PAGE_SHIFT)
start -= node++->size << PAGE_SHIFT;
- cur->start = (node->start << PAGE_SHIFT) + start;
- cur->size = min((node->size << PAGE_SHIFT) - start, size);
+ cur->start = node->start + start;
+ cur->size = min(node->size - start, size);
cur->remaining = size;
cur->node = node;
break;
@@ -155,8 +155,8 @@ static inline void amdgpu_res_next(struct amdgpu_res_cursor
*cur, uint64_t size)
node = cur->node;
cur->node = ++node;
- cur->start = node->start << PAGE_SHIFT;
- cur->size = min(node->size << PAGE_SHIFT, cur->remaining);
+ cur->start = node->start;
+ cur->size = min(node->size, cur->remaining);
break;
default:
return;
diff --git a/drivers/gpu/drm/i915/i915_scatterlist.c
b/drivers/gpu/drm/i915/i915_scatterlist.c
index 756289e43dff..7defda1219d0 100644
--- a/drivers/gpu/drm/i915/i915_scatterlist.c
+++ b/drivers/gpu/drm/i915/i915_scatterlist.c
@@ -94,7 +94,7 @@ struct i915_refct_sgt *i915_rsgt_from_mm_node(const struct
drm_mm_node *node,
if (!rsgt)
return ERR_PTR(-ENOMEM);
- i915_refct_sgt_init(rsgt, node->size << PAGE_SHIFT);
+ i915_refct_sgt_init(rsgt, node->size);
st = &rsgt->table;
/* restricted by sg_alloc_table */
if (WARN_ON(overflows_type(DIV_ROUND_UP_ULL(node->size, segment_pages),
@@ -1
[PATCH 2/3] drm/ttm: Change the parameters of ttm_range_man_init() from pages to bytes
From: Somalapuram Amaranath
Change the parameters of ttm_range_man_init_nocheck()
size from page size to byte size.
Cleanup the PAGE_SHIFT operation on the depended caller functions.
Signed-off-by: Somalapuram Amaranath
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
drivers/gpu/drm/drm_gem_vram_helper.c | 2 +-
drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++--
drivers/gpu/drm/ttm/ttm_range_manager.c | 8
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 2 +-
include/drm/ttm/ttm_range_manager.h | 6 +++---
6 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index f62e5398e620..77c2da886f5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -75,10 +75,10 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device
*bdev,
static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
unsigned int type,
- uint64_t size_in_page)
+ uint64_t size)
{
return ttm_range_man_init(&adev->mman.bdev, type,
- false, size_in_page);
+ false, size << PAGE_SHIFT);
}
/**
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
b/drivers/gpu/drm/drm_gem_vram_helper.c
index d40b3edb52d0..f70d11e1cd47 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -999,7 +999,7 @@ static int drm_vram_mm_init(struct drm_vram_mm *vmm, struct
drm_device *dev,
return ret;
ret = ttm_range_man_init(&vmm->bdev, TTM_PL_VRAM,
-false, vram_size >> PAGE_SHIFT);
+false, vram_size);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
index 67075c85f847..78dd6a87fb65 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -70,13 +70,13 @@ struct radeon_device *radeon_get_rdev(struct ttm_device
*bdev)
static int radeon_ttm_init_vram(struct radeon_device *rdev)
{
return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM,
- false, rdev->mc.real_vram_size >> PAGE_SHIFT);
+ false, rdev->mc.real_vram_size);
}
static int radeon_ttm_init_gtt(struct radeon_device *rdev)
{
return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT,
- true, rdev->mc.gtt_size >> PAGE_SHIFT);
+ true, rdev->mc.gtt_size);
}
static void radeon_evict_flags(struct ttm_buffer_object *bo,
diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c
b/drivers/gpu/drm/ttm/ttm_range_manager.c
index ae11d07eb63a..62fddcc59f02 100644
--- a/drivers/gpu/drm/ttm/ttm_range_manager.c
+++ b/drivers/gpu/drm/ttm/ttm_range_manager.c
@@ -169,7 +169,7 @@ static const struct ttm_resource_manager_func
ttm_range_manager_func = {
* @bdev: ttm device
* @type: memory manager type
* @use_tt: if the memory manager uses tt
- * @p_size: size of area to be managed in pages.
+ * @size: size of area to be managed in bytes.
*
* The range manager is installed for this device in the type slot.
*
@@ -177,7 +177,7 @@ static const struct ttm_resource_manager_func
ttm_range_manager_func = {
*/
int ttm_range_man_init_nocheck(struct ttm_device *bdev,
unsigned type, bool use_tt,
- unsigned long p_size)
+ u64 size)
{
struct ttm_resource_manager *man;
struct ttm_range_manager *rman;
@@ -191,9 +191,9 @@ int ttm_range_man_init_nocheck(struct ttm_device *bdev,
man->func = &ttm_range_manager_func;
- ttm_resource_manager_init(man, bdev, p_size);
+ ttm_resource_manager_init(man, bdev, size);
- drm_mm_init(&rman->mm, 0, p_size);
+ drm_mm_init(&rman->mm, 0, size);
spin_lock_init(&rman->lock);
ttm_set_driver_manager(bdev, type, &rman->manager);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 2588615a2a38..18cf4edea197 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -706,7 +706,7 @@ static int vmw_vram_manager_init(struct vmw_private
*dev_priv)
{
int ret;
ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,
-dev_priv->vram_size >> PAGE_SHIFT);
+dev_priv->vram_size);
ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev,
TTM_PL_VRAM), false);
return ret;
}
diff --git a/include/drm/ttm/ttm_range_manager.h
b/include/drm/ttm/ttm_range_manager.h
index 7963b957e9ef..05bffded1b53 100644
--- a/include/drm/ttm/ttm_range_manager.h
+
[PATCH 1/3] drm/amdgpu: use amdgpu_res_cursor in more places v2
Instead of resource->start use the cursor to get this.
v2 (chk): remove changes to amdgpu_bo_gpu_offset_no_check(), that
won't work with the AGP aperture otherwise.
Signed-off-by: Somalapuram Amaranath
Reviewed-by: Christian König
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++--
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 6 +-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2cd081cbf706..f62e5398e620 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -845,6 +845,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
+ struct amdgpu_res_cursor cursor;
uint64_t flags;
int r;
@@ -892,7 +893,8 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
/* bind pages into GART page tables */
- gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
+ amdgpu_res_first(bo_mem, 0, bo_mem->size, &cursor);
+ gtt->offset = cursor.start;
amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
gtt->ttm.dma_address, flags);
gtt->bound = true;
@@ -912,6 +914,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct ttm_operation_ctx ctx = { false, false };
struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
+ struct amdgpu_res_cursor cursor;
struct ttm_placement placement;
struct ttm_place placements;
struct ttm_resource *tmp;
@@ -945,7 +948,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
/* Bind pages */
- gtt->offset = (u64)tmp->start << PAGE_SHIFT;
+ amdgpu_res_first(tmp, 0, tmp->size, &cursor);
+ gtt->offset = cursor.start;
amdgpu_ttm_gart_bind(adev, bo, flags);
amdgpu_gart_invalidate_tlb(adev);
ttm_resource_free(bo, &bo->resource);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index c06ada0844ba..9114393d2ee6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -200,8 +200,12 @@ static int add_queue_mes(struct device_queue_manager *dqm,
struct queue *q,
queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
if (q->wptr_bo) {
+ struct amdgpu_res_cursor cursor;
+
wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE
- 1);
- queue_input.wptr_mc_addr =
((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
+ amdgpu_res_first(q->wptr_bo->tbo.resource, 0,
+q->wptr_bo->tbo.resource->size, &cursor);
+ queue_input.wptr_mc_addr = cursor.start + wptr_addr_off;
}
queue_input.is_kfd_process = 1;
--
2.34.1
Change TTM from using pfn to bytes
Hi guys, this is an extract from Amar's earlier patch set with quite some re-ordering, bug fixes and separating changes into smaller patches. Background is that we want to use GEM/TTM to manage all kind of resources which most are not accounted in pages but rather bytes or even arbitary units (hw blocks for example). Sending this out so that the Intel CI can take another look at it. Regards, Christian.
[PATCH] drm/amd/pm: avoid unaligned access warnings
When building on OpenBSD/arm64 with clang 15, unaligned access
warnings are seen when a union is embedded inside a packed struct.
drm/amd/pm/powerplay/hwmgr/vega20_pptable.h:136:17: error: field
smcPPTable within 'struct _ATOM_VEGA20_POWERPLAYTABLE' is less aligned
than 'PPTable_t' and is usually due to
'struct _ATOM_VEGA20_POWERPLAYTABLE' being packed, which can lead to
unaligned accesses [-Werror,-Wunaligned-access]
PPTable_t smcPPTable;
^
Make PPTable_t packed to avoid this.
Signed-off-by: Jonathan Gray
---
drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h | 2 ++
drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h | 2 ++
drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h| 2 ++
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h | 2 ++
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h | 2 ++
.../amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h | 2 ++
.../drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_aldebaran.h| 2 ++
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 2 ++
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h | 2 ++
9 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h
b/drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h
index fdc6b7a57bc9..c2efc70ef288 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h
@@ -358,6 +358,7 @@ typedef struct {
QuadraticInt_t SsCurve;
} DpmDescriptor_t;
+#pragma pack(push, 1)
typedef struct {
uint32_t Version;
@@ -609,6 +610,7 @@ typedef struct {
uint32_t MmHubPadding[8];
} PPTable_t;
+#pragma pack(pop)
typedef struct {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h
b/drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h
index 2818c98ff5ca..faae4b918d90 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/inc/smu9_driver_if.h
@@ -122,6 +122,7 @@ typedef struct {
uint16_t Vid; /* min voltage in SVI2 VID */
} DisplayClockTable_t;
+#pragma pack(push, 1)
typedef struct {
/* PowerTune */
uint16_t SocketPowerLimit; /* Watts */
@@ -323,6 +324,7 @@ typedef struct {
uint32_t MmHubPadding[3]; /* SMU internal use */
} PPTable_t;
+#pragma pack(pop)
typedef struct {
uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h
b/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h
index b6ffd08784e7..6456bea5d2d5 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h
@@ -245,6 +245,7 @@ typedef struct {
QuadraticInt_t SsCurve;
} DpmDescriptor_t;
+#pragma pack(push, 1)
typedef struct {
uint32_t Version;
@@ -508,6 +509,7 @@ typedef struct {
uint32_t MmHubPadding[7];
} PPTable_t;
+#pragma pack(pop)
typedef struct {
diff --git
a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h
index 43d43d6addc0..d518dee18e1b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h
@@ -464,6 +464,7 @@ typedef struct {
uint16_t Padding16;
} DpmDescriptor_t;
+#pragma pack(push, 1)
typedef struct {
uint32_t Version;
@@ -733,6 +734,7 @@ typedef struct {
uint32_t MmHubPadding[8]; // SMU internal use
} PPTable_t;
+#pragma pack(pop)
typedef struct {
// Time constant parameters for clock averages in ms
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h
index 04752ade1016..c5c1943fb6a1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h
@@ -515,6 +515,7 @@ typedef struct {
uint32_t BoardLevelEnergyAccumulator;
} OutOfBandMonitor_t;
+#pragma pack(push, 1)
typedef struct {
uint32_t Version;
@@ -814,6 +815,7 @@ typedef struct {
uint32_t MmHubPadding[8]; // SMU internal use
} PPTable_t;
+#pragma pack(pop)
typedef struct {
// Time constant parameters for clock averages in ms
diff --git
a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
index 351a4af429b3..aa6d29de4002 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
@@ -599,6 +599,7 @@ typedef struct {
uint16_t Fmax;
} UclkDpmChangeRange_t;
+#pragma pack(push, 1)
typedef struct {
// MAJOR SE
[PATCH] drm/amd/display: avoid unaligned access warnings
When building on OpenBSD/arm64 with clang 15, unaligned access
warnings are seen when a union is embedded inside a packed struct.
drm/amd/display/dmub/inc/dmub_cmd.h:941:18: error: field
cursor_copy_src within 'struct dmub_rb_cmd_mall' is less aligned than
'union dmub_addr' and is usually due to 'struct dmub_rb_cmd_mall'
being packed, which can lead to unaligned accesses
[-Werror,-Wunaligned-access]
union dmub_addr cursor_copy_src; /**< Cursor copy address */
^
drm/amd/display/dmub/inc/dmub_cmd.h:942:18: error: field cursor_copy_dst
within 'struct dmub_rb_cmd_mall' is less aligned than
'union dmub_addr' and is usually due to 'struct dmub_rb_cmd_mall'
being packed, which can lead to unaligned accesses
[-Werror,-Wunaligned-access]
union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
^
Add pragma pack around dmub_addr to avoid this.
Signed-off-by: Jonathan Gray
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 33907feefebb..dc92d06572a3 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -162,6 +162,7 @@ extern "C" {
#define dmub_udelay(microseconds) udelay(microseconds)
#endif
+#pragma pack(push, 1)
/**
* union dmub_addr - DMUB physical/virtual 64-bit address.
*/
@@ -172,6 +173,7 @@ union dmub_addr {
} u; /*<< Low/high bit access */
uint64_t quad_part; /*<< 64 bit address */
};
+#pragma pack(pop)
/**
* Dirty rect definition.
--
2.39.1
Re: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new bad page
On 2/14/2023 11:42 AM, Zhou1, Tao wrote:
-Original Message-
From: Lazar, Lijo
Sent: Tuesday, February 14, 2023 12:55 PM
To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org; Zhang,
Hawking ; Yang, Stanley
; Chai, Thomas ; Li, Candice
Subject: Re: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new
bad page
On 2/14/2023 7:56 AM, Zhou1, Tao wrote:
-Original Message-
From: Lazar, Lijo
Sent: Monday, February 13, 2023 8:38 PM
To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org;
Zhang, Hawking ; Yang, Stanley
; Chai, Thomas ; Li,
Candice
Subject: Re: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if
no new bad page
On 2/10/2023 2:15 PM, Tao Zhou wrote:
If a UMC bad page is reserved but not freed by an application, the
application may trigger uncorrectable error repeatly by accessing the page.
There is amdgpu_ras_check_bad_page which checks if address is already
part of an existing bad page. Can't that be used?
Thanks,
Lijo
[Tao] amdgpu_ras_check_bad_page is already called in
amdgpu_ras_add_bad_pages, this patch just makes use of the result of
amdgpu_ras_check_bad_page.
In the patch, below two are called after error count is set to 0.
amdgpu_ras_save_bad_pages
amdgpu_dpm_send_hbm_bad_pages_num
Instead of that, just check if it's an existing badpage which is repeatedly
accessed and proceed directly to the next step (reset if
specified)
if (amdgpu_ras_check_bad_page(adev, address))
set error count to 0;
goto reset_logic;
Thanks,
Lijo
[Tao] 1. amdgpu_ras_check_bad_page checks only one page, but one ue can
generate 16 or more pages.
In this case, it makes sense to do as per the patch. Thanks for the
explanation.
Thanks,
Lijo
2. if no new bad page is found, amdgpu_ras_save_bad_pages will do nothing and
ras_num_recs won't increase.
3. gpu reset logic should follow the old way even ue count is set to 0.
This patch only set ue count to 0 if there is no new bad page, but other logic
has no change.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 -
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 6 +-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e85c4689ce2c..eafe01a24349 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2049,7 +2049,7 @@ int amdgpu_ras_add_bad_pages(struct
amdgpu_device *adev,
{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data *data;
- int ret = 0;
+ int ret = 0, old_cnt;
uint32_t i;
if (!con || !con->eh_data || !bps || pages <= 0) @@ -2060,6
+2060,8 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
if (!data)
goto out;
+ old_cnt = data->count;
+
for (i = 0; i < pages; i++) {
if (amdgpu_ras_check_bad_page_unlock(con,
bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
@@ -2079,6
+2081,11 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device
*adev,
data->count++;
data->space_left--;
}
+
+ /* all pages have been reserved before, no new bad page */
+ if (old_cnt == data->count)
+ ret = -EEXIST;
+
out:
mutex_unlock(&con->recovery_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 1c7fcb4f2380..772c431e4065 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -145,8 +145,12 @@ static int
amdgpu_umc_do_page_retirement(struct
amdgpu_device *adev,
if ((amdgpu_bad_page_threshold != 0) &&
err_data->err_addr_cnt) {
- amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
+ ret = amdgpu_ras_add_bad_pages(adev, err_data-
err_addr,
err_data->err_addr_cnt);
+ /* if no new bad page is found, no need to increase ue
count */
+ if (ret == -EEXIST)
+ err_data->ue_count = 0;
+
amdgpu_ras_save_bad_pages(adev);
amdgpu_dpm_send_hbm_bad_pages_num(adev,
con->eeprom_control.ras_num_recs);
RE: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new bad page
> -Original Message-
> From: Lazar, Lijo
> Sent: Tuesday, February 14, 2023 12:55 PM
> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org; Zhang,
> Hawking ; Yang, Stanley
> ; Chai, Thomas ; Li, Candice
>
> Subject: Re: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new
> bad page
>
>
>
> On 2/14/2023 7:56 AM, Zhou1, Tao wrote:
> >
> >
> >> -Original Message-
> >> From: Lazar, Lijo
> >> Sent: Monday, February 13, 2023 8:38 PM
> >> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org;
> >> Zhang, Hawking ; Yang, Stanley
> >> ; Chai, Thomas ; Li,
> >> Candice
> >> Subject: Re: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if
> >> no new bad page
> >>
> >>
> >>
> >> On 2/10/2023 2:15 PM, Tao Zhou wrote:
> >>> If a UMC bad page is reserved but not freed by an application, the
> >>> application may trigger uncorrectable error repeatly by accessing the
> >>> page.
> >>>
> >>
> >> There is amdgpu_ras_check_bad_page which checks if address is already
> >> part of an existing bad page. Can't that be used?
> >>
> >> Thanks,
> >> Lijo
> >
> > [Tao] amdgpu_ras_check_bad_page is already called in
> amdgpu_ras_add_bad_pages, this patch just makes use of the result of
> amdgpu_ras_check_bad_page.
> >
>
> In the patch, below two are called after error count is set to 0.
> amdgpu_ras_save_bad_pages
> amdgpu_dpm_send_hbm_bad_pages_num
>
> Instead of that, just check if it's an existing badpage which is repeatedly
> accessed and proceed directly to the next step (reset if
> specified)
>
> if (amdgpu_ras_check_bad_page(adev, address))
> set error count to 0;
> goto reset_logic;
>
> Thanks,
> Lijo
[Tao] 1. amdgpu_ras_check_bad_page checks only one page, but one ue can
generate 16 or more pages.
2. if no new bad page is found, amdgpu_ras_save_bad_pages will do nothing and
ras_num_recs won't increase.
3. gpu reset logic should follow the old way even ue count is set to 0.
This patch only set ue count to 0 if there is no new bad page, but other logic
has no change.
>
> >>
> >>> Signed-off-by: Tao Zhou
> >>> ---
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 -
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 6 +-
> >>>2 files changed, 13 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> >>> index e85c4689ce2c..eafe01a24349 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> >>> @@ -2049,7 +2049,7 @@ int amdgpu_ras_add_bad_pages(struct
> >> amdgpu_device *adev,
> >>>{
> >>> struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
> >>> struct ras_err_handler_data *data;
> >>> - int ret = 0;
> >>> + int ret = 0, old_cnt;
> >>> uint32_t i;
> >>>
> >>> if (!con || !con->eh_data || !bps || pages <= 0) @@ -2060,6
> >>> +2060,8 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
> >>> if (!data)
> >>> goto out;
> >>>
> >>> + old_cnt = data->count;
> >>> +
> >>> for (i = 0; i < pages; i++) {
> >>> if (amdgpu_ras_check_bad_page_unlock(con,
> >>> bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
> >> @@ -2079,6
> >>> +2081,11 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device
> *adev,
> >>> data->count++;
> >>> data->space_left--;
> >>> }
> >>> +
> >>> + /* all pages have been reserved before, no new bad page */
> >>> + if (old_cnt == data->count)
> >>> + ret = -EEXIST;
> >>> +
> >>>out:
> >>> mutex_unlock(&con->recovery_lock);
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> >>> index 1c7fcb4f2380..772c431e4065 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> >>> @@ -145,8 +145,12 @@ static int
> amdgpu_umc_do_page_retirement(struct
> >>> amdgpu_device *adev,
> >>>
> >>> if ((amdgpu_bad_page_threshold != 0) &&
> >>> err_data->err_addr_cnt) {
> >>> - amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
> >>> + ret = amdgpu_ras_add_bad_pages(adev, err_data-
> >>> err_addr,
> >>> err_data->err_addr_cnt);
> >>> + /* if no new bad page is found, no need to increase ue
> >> count */
> >>> + if (ret == -EEXIST)
> >>> + err_data->ue_count = 0;
> >>> +
> >>> amdgpu_ras_save_bad_pages(adev);
> >>>
> >>> amdgpu_dpm_send_hbm_bad_pages_num(adev,
> >>> con->eeprom_control.ras_num_recs);
Re: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new bad page
On 2/14/2023 7:56 AM, Zhou1, Tao wrote:
-Original Message-
From: Lazar, Lijo
Sent: Monday, February 13, 2023 8:38 PM
To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org; Zhang,
Hawking ; Yang, Stanley
; Chai, Thomas ; Li, Candice
Subject: Re: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new
bad page
On 2/10/2023 2:15 PM, Tao Zhou wrote:
If a UMC bad page is reserved but not freed by an application, the
application may trigger uncorrectable error repeatly by accessing the page.
There is amdgpu_ras_check_bad_page which checks if address is already part of
an existing bad page. Can't that be used?
Thanks,
Lijo
[Tao] amdgpu_ras_check_bad_page is already called in amdgpu_ras_add_bad_pages,
this patch just makes use of the result of amdgpu_ras_check_bad_page.
In the patch, below two are called after error count is set to 0.
amdgpu_ras_save_bad_pages
amdgpu_dpm_send_hbm_bad_pages_num
Instead of that, just check if it's an existing badpage which is
repeatedly accessed and proceed directly to the next step (reset if
specified)
if (amdgpu_ras_check_bad_page(adev, address))
set error count to 0;
goto reset_logic;
Thanks,
Lijo
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 -
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 6 +-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e85c4689ce2c..eafe01a24349 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2049,7 +2049,7 @@ int amdgpu_ras_add_bad_pages(struct
amdgpu_device *adev,
{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data *data;
- int ret = 0;
+ int ret = 0, old_cnt;
uint32_t i;
if (!con || !con->eh_data || !bps || pages <= 0) @@ -2060,6 +2060,8
@@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
if (!data)
goto out;
+ old_cnt = data->count;
+
for (i = 0; i < pages; i++) {
if (amdgpu_ras_check_bad_page_unlock(con,
bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
@@ -2079,6
+2081,11 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
data->count++;
data->space_left--;
}
+
+ /* all pages have been reserved before, no new bad page */
+ if (old_cnt == data->count)
+ ret = -EEXIST;
+
out:
mutex_unlock(&con->recovery_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 1c7fcb4f2380..772c431e4065 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -145,8 +145,12 @@ static int amdgpu_umc_do_page_retirement(struct
amdgpu_device *adev,
if ((amdgpu_bad_page_threshold != 0) &&
err_data->err_addr_cnt) {
- amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
+ ret = amdgpu_ras_add_bad_pages(adev, err_data-
err_addr,
err_data->err_addr_cnt);
+ /* if no new bad page is found, no need to increase ue
count */
+ if (ret == -EEXIST)
+ err_data->ue_count = 0;
+
amdgpu_ras_save_bad_pages(adev);
amdgpu_dpm_send_hbm_bad_pages_num(adev,
con->eeprom_control.ras_num_recs);
RE: [PATCH] drm/amd/amdgpu: fix warining during suspend
[AMD Official Use Only - General]
Reviewed-and-tested-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Jack
> Xiao
> Sent: Monday, February 13, 2023 6:52 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Xiao, Jack ; jfale...@redhat.com
> Subject: [PATCH] drm/amd/amdgpu: fix warining during suspend
>
> Freeing memory was warned during suspend.
> Move the self test out of suspend.
>
> Link: https://bugzilla.redhat.com/show_bug.cgi?id=2151825
> Cc: jfale...@redhat.com
> Signed-off-by: Jack Xiao
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index a10b627c8357..3842e7e62eda 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -4270,6 +4270,9 @@ int amdgpu_device_resume(struct drm_device
> *dev, bool fbcon)
> }
> adev->in_suspend = false;
>
> + if (adev->enable_mes)
> + amdgpu_mes_self_test(adev);
> +
> if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
> DRM_WARN("smart shift update failed\n");
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 62cdd2113135..5826eac270d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -1284,7 +1284,7 @@ static int mes_v11_0_late_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> /* it's only intended for use in mes_self_test case, not for s0ix and
> reset */
> - if (!amdgpu_in_reset(adev) && !adev->in_s0ix &&
> + if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev-
> >in_suspend &&
> (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)))
> amdgpu_mes_self_test(adev);
>
> --
> 2.37.3
RE: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new bad page
[AMD Official Use Only - General]
> -Original Message-
> From: Zhou1, Tao
> Sent: Monday, February 13, 2023 4:25 PM
> To: Zhang, Hawking ; amd-
> g...@lists.freedesktop.org; Yang, Stanley ; Chai,
> Thomas ; Li, Candice
> Subject: RE: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no
> new bad page
>
> [AMD Official Use Only - General]
>
> > -Original Message-
> > From: Zhang, Hawking
> > Sent: Friday, February 10, 2023 11:02 PM
> > To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org;
> > Yang, Stanley ; Chai, Thomas
> > ; Li, Candice
> > Subject: RE: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no
> > new bad page
> >
> > [AMD Official Use Only - General]
> >
> > + /* if no new bad page is found, no need to increase
> > ue count
> */
> > + if (ret == -EEXIST)
> > + err_data->ue_count = 0;
> >
> > Returning EEXIST in such case is not reasonable. Might consider return
> > a bool for
> > amdgpu_ras_add_bad_pages: true means it does add some new bad page;
> > false means it doesn't change anything.
> >
> > Regards,
> > Hawking
>
> [Tao] but it can returns -ENOMEM, amdgpu_ras_load_bad_pages and
> amdgpu_ras_recovery_init also need to check the return value. I'd like to
> keep the type of return value unchanged.
> How about -EINVAL?
Stanley: How about return -EALREADY?
Regards,
Stanley
>
> >
> > -Original Message-
> > From: Zhou1, Tao
> > Sent: Friday, February 10, 2023 16:45
> > To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> > ; Yang, Stanley ;
> Chai,
> > Thomas ; Li, Candice
> > Cc: Zhou1, Tao
> > Subject: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no
> new
> > bad page
> >
> > If a UMC bad page is reserved but not freed by an application, the
> > application may trigger uncorrectable error repeatly by accessing the page.
> >
> > Signed-off-by: Tao Zhou
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 -
> > drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 6 +-
> > 2 files changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > index e85c4689ce2c..eafe01a24349 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > @@ -2049,7 +2049,7 @@ int amdgpu_ras_add_bad_pages(struct
> > amdgpu_device *adev, {
> > struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
> > struct ras_err_handler_data *data;
> > - int ret = 0;
> > + int ret = 0, old_cnt;
> > uint32_t i;
> >
> > if (!con || !con->eh_data || !bps || pages <= 0) @@ -2060,6
> > +2060,8 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device
> *adev,
> > if (!data)
> > goto out;
> >
> > + old_cnt = data->count;
> > +
> > for (i = 0; i < pages; i++) {
> > if (amdgpu_ras_check_bad_page_unlock(con,
> > bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
> > @@ -2079,6
> > +2081,11 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device
> *adev,
> > data->count++;
> > data->space_left--;
> > }
> > +
> > + /* all pages have been reserved before, no new bad page */
> > + if (old_cnt == data->count)
> > + ret = -EEXIST;
> > +
> > out:
> > mutex_unlock(&con->recovery_lock);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> > index 1c7fcb4f2380..772c431e4065 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> > @@ -145,8 +145,12 @@ static int
> amdgpu_umc_do_page_retirement(struct
> > amdgpu_device *adev,
> >
> > if ((amdgpu_bad_page_threshold != 0) &&
> > err_data->err_addr_cnt) {
> > - amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
> > + ret = amdgpu_ras_add_bad_pages(adev,
> > + err_data->err_addr,
> >
> > err_data->err_addr_cnt);
> > + /* if no new bad page is found, no need to increase
> > ue count
> */
> > + if (ret == -EEXIST)
> > + err_data->ue_count = 0;
> > +
> > amdgpu_ras_save_bad_pages(adev);
> >
> > amdgpu_dpm_send_hbm_bad_pages_num(adev, con-
> > >eeprom_control.ras_num_recs);
> > --
> > 2.35.1
> >
>
RE: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new bad page
> -Original Message-
> From: Lazar, Lijo
> Sent: Monday, February 13, 2023 8:38 PM
> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org; Zhang,
> Hawking ; Yang, Stanley
> ; Chai, Thomas ; Li, Candice
>
> Subject: Re: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new
> bad page
>
>
>
> On 2/10/2023 2:15 PM, Tao Zhou wrote:
> > If a UMC bad page is reserved but not freed by an application, the
> > application may trigger uncorrectable error repeatly by accessing the page.
> >
>
> There is amdgpu_ras_check_bad_page which checks if address is already part of
> an existing bad page. Can't that be used?
>
> Thanks,
> Lijo
[Tao] amdgpu_ras_check_bad_page is already called in amdgpu_ras_add_bad_pages,
this patch just makes use of the result of amdgpu_ras_check_bad_page.
>
> > Signed-off-by: Tao Zhou
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 -
> > drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 6 +-
> > 2 files changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > index e85c4689ce2c..eafe01a24349 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> > @@ -2049,7 +2049,7 @@ int amdgpu_ras_add_bad_pages(struct
> amdgpu_device *adev,
> > {
> > struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
> > struct ras_err_handler_data *data;
> > - int ret = 0;
> > + int ret = 0, old_cnt;
> > uint32_t i;
> >
> > if (!con || !con->eh_data || !bps || pages <= 0) @@ -2060,6 +2060,8
> > @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
> > if (!data)
> > goto out;
> >
> > + old_cnt = data->count;
> > +
> > for (i = 0; i < pages; i++) {
> > if (amdgpu_ras_check_bad_page_unlock(con,
> > bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
> @@ -2079,6
> > +2081,11 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
> > data->count++;
> > data->space_left--;
> > }
> > +
> > + /* all pages have been reserved before, no new bad page */
> > + if (old_cnt == data->count)
> > + ret = -EEXIST;
> > +
> > out:
> > mutex_unlock(&con->recovery_lock);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> > index 1c7fcb4f2380..772c431e4065 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> > @@ -145,8 +145,12 @@ static int amdgpu_umc_do_page_retirement(struct
> > amdgpu_device *adev,
> >
> > if ((amdgpu_bad_page_threshold != 0) &&
> > err_data->err_addr_cnt) {
> > - amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
> > + ret = amdgpu_ras_add_bad_pages(adev, err_data-
> >err_addr,
> > err_data->err_addr_cnt);
> > + /* if no new bad page is found, no need to increase ue
> count */
> > + if (ret == -EEXIST)
> > + err_data->ue_count = 0;
> > +
> > amdgpu_ras_save_bad_pages(adev);
> >
> > amdgpu_dpm_send_hbm_bad_pages_num(adev,
> > con->eeprom_control.ras_num_recs);
RE: [PATCH] drm/amd/amdgpu: fix warining during suspend
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Jack Xiao
Sent: Monday, February 13, 2023 6:52 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; jfale...@redhat.com
Subject: [PATCH] drm/amd/amdgpu: fix warining during suspend
Freeing memory was warned during suspend.
Move the self test out of suspend.
Link: https://bugzilla.redhat.com/show_bug.cgi?id=2151825
Cc: jfale...@redhat.com
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a10b627c8357..3842e7e62eda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4270,6 +4270,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool
fbcon)
}
adev->in_suspend = false;
+ if (adev->enable_mes)
+ amdgpu_mes_self_test(adev);
+
if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
DRM_WARN("smart shift update failed\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 62cdd2113135..5826eac270d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1284,7 +1284,7 @@ static int mes_v11_0_late_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* it's only intended for use in mes_self_test case, not for s0ix and
reset */
- if (!amdgpu_in_reset(adev) && !adev->in_s0ix &&
+ if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend &&
(adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)))
amdgpu_mes_self_test(adev);
--
2.37.3
[PATCH v2] drm/amd: Don't allow s0ix on APUs older than Raven
APUs before Raven didn't support s0ix. As we just relieved some
of the safety checks for s0ix to improve power consumption on
APUs that support it but that are missing BIOS support a new
blind spot was introduced that a user could "try" to run s0ix.
Plug this hole so that if users try to run s0ix on anything older
than Raven it will just skip suspend of the GPU.
Fixes: cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support")
Suggested-by: Alexander Deucher
Signed-off-by: Mario Limonciello
---
v1->v2:
* Don't run any suspend code or resume code in this case
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index fa7375b97fd47..25e902077caf6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -1073,6 +1073,9 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device
*adev)
(pm_suspend_target_state != PM_SUSPEND_TO_IDLE))
return false;
+ if (adev->asic_type < CHIP_RAVEN)
+ return false;
+
/*
* If ACPI_FADT_LOW_POWER_S0 is not set in the FADT, it is generally
* risky to do any special firmware-related preparations for entering
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6c2fe50b528e0..1f6d93dc3d72b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2414,8 +2414,10 @@ static int amdgpu_pmops_suspend(struct device *dev)
if (amdgpu_acpi_is_s0ix_active(adev))
adev->in_s0ix = true;
- else
+ else if (amdgpu_acpi_is_s3_active(adev))
adev->in_s3 = true;
+ if (!adev->in_s0ix && !adev->in_s3)
+ return 0;
return amdgpu_device_suspend(drm_dev, true);
}
@@ -2436,6 +2438,9 @@ static int amdgpu_pmops_resume(struct device *dev)
struct amdgpu_device *adev = drm_to_adev(drm_dev);
int r;
+ if (!adev->in_s0ix && !adev->in_s3)
+ return 0;
+
/* Avoids registers access if device is physically gone */
if (!pci_device_is_present(adev->pdev))
adev->no_hw_access = true;
--
2.25.1
Re: [PATCH 08/10] drm/amd/display: Remove unused local variables
On Mon, Feb 13, 2023 at 3:50 PM Arthur Grillo wrote:
>
> Remove local variables that were just set but were never used. This
> decrease the number of -Wunused-but-set-variable warnings.
>
> Signed-off-by: Arthur Grillo
> ---
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 3 ---
> drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c | 7 ---
> drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c | 2 --
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c | 2 --
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 4
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 3 ---
> drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 5 +
> .../gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 4
> .../drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c | 2 --
> .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 4
> 10 files changed, 1 insertion(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
> index c4287147b853..81aa1631945a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
> @@ -1219,7 +1219,6 @@ void
> dcn10_link_encoder_update_mst_stream_allocation_table(
> const struct link_mst_stream_allocation_table *table)
> {
> struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
> - uint32_t value0 = 0;
> uint32_t value1 = 0;
> uint32_t value2 = 0;
> uint32_t slots = 0;
> @@ -1321,8 +1320,6 @@ void
> dcn10_link_encoder_update_mst_stream_allocation_table(
> do {
> udelay(10);
>
> - value0 = REG_READ(DP_MSE_SAT_UPDATE);
> -
This may have impacts on behavior since we are reading a register here.
Alex
> REG_GET(DP_MSE_SAT_UPDATE,
> DP_MSE_SAT_UPDATE, &value1);
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
> b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
> index f50ab961bc17..a7268027a472 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
> @@ -185,13 +185,6 @@ static bool dpp201_get_optimal_number_of_taps(
> struct scaler_data *scl_data,
> const struct scaling_taps *in_taps)
> {
> - uint32_t pixel_width;
> -
> - if (scl_data->viewport.width > scl_data->recout.width)
> - pixel_width = scl_data->recout.width;
> - else
> - pixel_width = scl_data->viewport.width;
> -
> if (scl_data->viewport.width != scl_data->h_active &&
> scl_data->viewport.height != scl_data->v_active &&
> dpp->caps->dscl_data_proc_format ==
> DSCL_DATA_PRCESSING_FIXED_FORMAT &&
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> index 61bcfa03c4e7..1aeb04fbd89d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> @@ -541,8 +541,6 @@ void dcn201_pipe_control_lock(
> bool lock)
> {
> struct dce_hwseq *hws = dc->hwseq;
> - struct hubp *hubp = NULL;
> - hubp = dc->res_pool->hubps[pipe->pipe_idx];
> /* use TG master update lock to lock everything on the TG
> * therefore only top pipe need to lock
> */
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
> index 95528e5ef89e..55e388c4c98b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
> @@ -123,7 +123,6 @@ void afmt3_se_audio_setup(
> {
> struct dcn30_afmt *afmt3 = DCN30_AFMT_FROM_AFMT(afmt);
>
> - uint32_t speakers = 0;
> uint32_t channels = 0;
>
> ASSERT(audio_info);
> @@ -131,7 +130,6 @@ void afmt3_se_audio_setup(
> if (audio_info == NULL)
> return;
>
> - speakers = audio_info->flags.info.ALLSPEAKERS;
> channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
>
> /* setup the audio stream source select (audio -> dig mapping) */
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
> index dc3e8df706b3..e46bbe7ddcc9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
> @@ -47,13 +47,9 @@ void hubp3_set_vm_system_aperture_settings(struct hubp
> *hubp,
> {
> struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>
> - PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
> PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
> PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
>
> - // The
Re: [PATCH 07/10] drm/amd/amdgpu: Deal with possible fail allocation
Am 13.02.23 um 21:49 schrieb Arthur Grillo: Deal with return value of an allocation. This reduces the number of -Wunused-but-set-variable warnings. Signed-off-by: Arthur Grillo --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 82e27bd4f038..00c0876840c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -1104,6 +1104,8 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, &ctx_data->meta_data_obj, &ctx_data->meta_data_mc_addr, &ctx_data->meta_data_ptr); + if (r) + return r; if (!ctx_data->meta_data_obj) return -ENOMEM; That change doesn't make much sense. We already check ctx_data->meta_data_obj and return -ENOMEM here when something goes wrong. We could potentially remove that, but it's not really a problem as far as I can see. Christian.
[PATCH 08/10] drm/amd/display: Remove unused local variables
Remove local variables that were just set but were never used. This
decrease the number of -Wunused-but-set-variable warnings.
Signed-off-by: Arthur Grillo
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 3 ---
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c | 7 ---
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c | 2 --
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c | 2 --
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 4
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 3 ---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 5 +
.../gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 4
.../drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c | 2 --
.../drm/amd/display/dc/link/protocols/link_dp_capability.c | 4
10 files changed, 1 insertion(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index c4287147b853..81aa1631945a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -1219,7 +1219,6 @@ void
dcn10_link_encoder_update_mst_stream_allocation_table(
const struct link_mst_stream_allocation_table *table)
{
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
- uint32_t value0 = 0;
uint32_t value1 = 0;
uint32_t value2 = 0;
uint32_t slots = 0;
@@ -1321,8 +1320,6 @@ void
dcn10_link_encoder_update_mst_stream_allocation_table(
do {
udelay(10);
- value0 = REG_READ(DP_MSE_SAT_UPDATE);
-
REG_GET(DP_MSE_SAT_UPDATE,
DP_MSE_SAT_UPDATE, &value1);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
index f50ab961bc17..a7268027a472 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
@@ -185,13 +185,6 @@ static bool dpp201_get_optimal_number_of_taps(
struct scaler_data *scl_data,
const struct scaling_taps *in_taps)
{
- uint32_t pixel_width;
-
- if (scl_data->viewport.width > scl_data->recout.width)
- pixel_width = scl_data->recout.width;
- else
- pixel_width = scl_data->viewport.width;
-
if (scl_data->viewport.width != scl_data->h_active &&
scl_data->viewport.height != scl_data->v_active &&
dpp->caps->dscl_data_proc_format ==
DSCL_DATA_PRCESSING_FIXED_FORMAT &&
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
index 61bcfa03c4e7..1aeb04fbd89d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
@@ -541,8 +541,6 @@ void dcn201_pipe_control_lock(
bool lock)
{
struct dce_hwseq *hws = dc->hwseq;
- struct hubp *hubp = NULL;
- hubp = dc->res_pool->hubps[pipe->pipe_idx];
/* use TG master update lock to lock everything on the TG
* therefore only top pipe need to lock
*/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
index 95528e5ef89e..55e388c4c98b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c
@@ -123,7 +123,6 @@ void afmt3_se_audio_setup(
{
struct dcn30_afmt *afmt3 = DCN30_AFMT_FROM_AFMT(afmt);
- uint32_t speakers = 0;
uint32_t channels = 0;
ASSERT(audio_info);
@@ -131,7 +130,6 @@ void afmt3_se_audio_setup(
if (audio_info == NULL)
return;
- speakers = audio_info->flags.info.ALLSPEAKERS;
channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
/* setup the audio stream source select (audio -> dig mapping) */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
index dc3e8df706b3..e46bbe7ddcc9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
@@ -47,13 +47,9 @@ void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
- PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
- // The format of default addr is 48:12 of the 48 bit addr
- mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
-
// The format of high/low are 48:18 of the 48 bit addr
mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
diff --git a/drivers/g
[PATCH 07/10] drm/amd/amdgpu: Deal with possible fail allocation
Deal with return value of an allocation. This reduces the number of -Wunused-but-set-variable warnings. Signed-off-by: Arthur Grillo --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 82e27bd4f038..00c0876840c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -1104,6 +1104,8 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, &ctx_data->meta_data_obj, &ctx_data->meta_data_mc_addr, &ctx_data->meta_data_ptr); + if (r) + return r; if (!ctx_data->meta_data_obj) return -ENOMEM; -- 2.39.1
[PATCH 06/10] drm/amd/display: Fix implicit enum conversion
Make implicit enum conversion to avoid -Wenum-conversion warning, such
as:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c:4109:88:
warning: implicit conversion from ‘enum ’ to ‘enum
odm_combine_mode’ [-Wenum-conversion]
4109 |
locals->ODMCombineEnablePerState[i][k] = true;
|
^
Signed-off-by: Arthur Grillo
---
.../amd/display/dc/dml/dcn20/display_mode_vba_20.c | 9 +
.../amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 10 +-
.../amd/display/dc/dml/dcn21/display_mode_vba_21.c | 12 ++--
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index d3b5b6fedf04..a7d1884ea38c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -26,6 +26,7 @@
#include "../display_mode_lib.h"
#include "display_mode_vba_20.h"
#include "../dml_inline_defs.h"
+#include "dml/display_mode_enums.h"
/*
* NOTE:
@@ -3897,14 +3898,14 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k]
/ 2
* (1 +
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
- locals->ODMCombineEnablePerState[i][k] = false;
+ locals->ODMCombineEnablePerState[i][k] = (enum
odm_combine_mode)false;
mode_lib->vba.PlaneRequiredDISPCLK =
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
if (mode_lib->vba.ODMCapability) {
if
(locals->PlaneRequiredDISPCLKWithoutODMCombine >
mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
-
locals->ODMCombineEnablePerState[i][k] = true;
+
locals->ODMCombineEnablePerState[i][k] = (enum odm_combine_mode)true;
mode_lib->vba.PlaneRequiredDISPCLK =
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
} else if (locals->HActive[k] >
DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
-
locals->ODMCombineEnablePerState[i][k] = true;
+
locals->ODMCombineEnablePerState[i][k] = (enum odm_combine_mode)true;
mode_lib->vba.PlaneRequiredDISPCLK =
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
}
}
@@ -3957,7 +3958,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
locals->RequiredDISPCLK[i][j] = 0.0;
locals->DISPCLK_DPPCLK_Support[i][j] = true;
for (k = 0; k <=
mode_lib->vba.NumberOfActivePlanes - 1; k++) {
- locals->ODMCombineEnablePerState[i][k]
= false;
+ locals->ODMCombineEnablePerState[i][k]
= (enum odm_combine_mode)false;
if (locals->SwathWidthYSingleDPP[k] <=
locals->MaximumSwathWidth[k]) {
locals->NoOfDPP[i][j][k] = 1;
locals->RequiredDPPCLK[i][j][k]
= locals->MinDPPCLKUsingSingleDPP[k]
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index edd098c7eb92..8e8096eec3f8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -4008,17 +4008,17 @@ void
dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k]
/ 2
* (1 +
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
- locals->ODMCombineEnablePerState[i][k] = false;
+ locals->ODMCombineEnablePerState[i][k] = (enum
odm_combine_mode)false;
mode_lib->vba.PlaneRequiredDISPCLK =
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
if (mode_lib->vba.ODMCapability) {
if
(loca
[PATCH 05/10] drm/amd/display: Fix excess arguments on kernel-doc
Remove arguments present on kernel-doc that are not present on the function declaration and add the new ones if present. Signed-off-by: Arthur Grillo --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c| 15 +++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 2 +- 3 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 3d36329be384..40e6b22daa22 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -273,8 +273,6 @@ static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse * * @ring: amdgpu ring pointer - * @job: job to retrieve vmid from - * @ib: IB object to schedule * * flush the IB by graphics cache rinse. */ @@ -326,7 +324,9 @@ static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring * * @ring: amdgpu ring pointer - * @fence: amdgpu fence object + * @addr: address + * @seq: fence seq number + * @flags: fence flags * * Add a DMA fence packet to the ring to write * the fence seq number and DMA trap packet to generate @@ -1060,10 +1060,9 @@ static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, * * @ib: indirect buffer to fill with commands * @pe: addr of the page entry - * @addr: dst addr to write into pe + * @value: dst addr to write into pe * @count: number of page entries to update * @incr: increase next addr by incr bytes - * @flags: access flags * * Update PTEs by writing them manually using sDMA. */ @@ -1167,7 +1166,6 @@ static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA * * @ring: amdgpu_ring pointer - * @vm: amdgpu_vm pointer * * Update the page table base and flush the VM TLB * using sDMA. @@ -1591,10 +1589,11 @@ static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) /** * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine * - * @ring: amdgpu_ring structure holding ring information + * @ib: indirect buffer to fill with commands * @src_offset: src GPU address * @dst_offset: dst GPU address * @byte_count: number of bytes to xfer + * @tmz: if a secure copy should be used * * Copy GPU buffers using the DMA engine. * Used by the amdgpu ttm implementation to move pages if @@ -1620,7 +1619,7 @@ static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, /** * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine * - * @ring: amdgpu_ring structure holding ring information + * @ib: indirect buffer to fill * @src_data: value to write to buffer * @dst_offset: dst GPU address * @byte_count: number of bytes to xfer diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 6ccf477d1c4d..c2092775ca88 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -698,7 +698,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, * * @dc: [in] current dc state * @context: [in] new dc state - * @cmd: [in] DMUB cmd to be populated with SubVP info + * @enable: [in] if true enables the pipes population * * This function loops through each pipe and populates the DMUB SubVP CMD info * based on the pipe (e.g. SubVP, VBLANK). diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index f607a0e28f14..f62368da875d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -581,7 +581,7 @@ static void dpp1_dscl_set_manual_ratio_init( * dpp1_dscl_set_recout - Set the first pixel of RECOUT in the OTG active area * * @dpp: DPP data struct - * @recount: Rectangle information + * @recout: Rectangle information * * This function sets the MPC RECOUT_START and RECOUT_SIZE registers based on * the values specified in the recount parameter. -- 2.39.1
[PATCH 04/10] drm/amd/display: Add previously missing includes
Add includes that were previously missing to reduce the number of
-Wmissing-prototypes warnings.
Signed-off-by: Arthur Grillo
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 1 +
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
index 330d7cbc7398..3069af3684c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -30,6 +30,7 @@
#include "dcn30/dcn30_hwseq.h"
#include "dcn31/dcn31_hwseq.h"
#include "dcn32_hwseq.h"
+#include "dcn32_init.h"
static const struct hw_sequencer_funcs dcn32_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c
b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c
index 04838a31e513..257f4fc065a5 100644
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c
@@ -24,6 +24,7 @@
*/
#include "dc_link.h"
#include "link_dp_trace.h"
+#include "link.h"
void dp_trace_init(struct dc_link *link)
{
--
2.39.1
[PATCH 03/10] drm/amd/amdgpu: Add function prototypes to headers
Add function prototypes to headers to reduce the number of
-Wmissing-prototypes warnings.
Signed-off-by: Arthur Grillo
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index bee93ab4298f..b03321e7d2d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -538,6 +538,7 @@ struct amdgpu_firmware {
void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
+void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
--
2.39.1
[PATCH 02/10] drm/amd/display: Add function prototypes to headers
Add function prototypes to headers to reduce the number of -Wmissing-prototypes warnings. Signed-off-by: Arthur Grillo --- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h | 2 ++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h | 2 ++ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h | 2 ++ 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h index e015e5a6c866..89d6208287b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h @@ -133,6 +133,8 @@ int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub, struct dcn_hubbub_phys_addr_config *pa_config); +void hubbub31_init(struct hubbub *hubbub); + void hubbub31_construct(struct dcn20_hubbub *hubbub3, struct dc_context *ctx, const struct dcn_hubbub_registers *hubbub_regs, diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h index bdc146890fca..b20eb04724bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h @@ -204,6 +204,8 @@ void hubbub32_force_usr_retraining_allow(struct hubbub *hubbub, bool allow); void hubbub32_force_wm_propagate_to_pipes(struct hubbub *hubbub); +void hubbub32_init(struct hubbub *hubbub); + void dcn32_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte); void hubbub32_construct(struct dcn20_hubbub *hubbub2, diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h index 56ef71151536..4cdbf63c952b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h @@ -61,6 +61,8 @@ void hubp32_phantom_hubp_post_enable(struct hubp *hubp); void hubp32_cursor_set_attributes(struct hubp *hubp, const struct dc_cursor_attributes *attr); +void hubp32_init(struct hubp *hubp); + bool hubp32_construct( struct dcn20_hubp *hubp2, struct dc_context *ctx, -- 2.39.1
[PATCH 01/10] drm/amd/display: Turn global functions into static
Turn global functions that are only used locally into static ones. This
reduces the number of -Wmissing-prototypes warnings.
Signed-off-by: Arthur Grillo
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 8c368bcc8e7e..a737782b2840 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -87,7 +87,7 @@ static int dcn315_get_active_display_cnt_wa(
return display_count;
}
-bool should_disable_otg(struct pipe_ctx *pipe)
+static bool should_disable_otg(struct pipe_ctx *pipe)
{
bool ret = true;
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
b/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
index 27dc8c9955f4..3c7cb3dc046b 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
@@ -37,7 +37,7 @@
#include "soc15_hw_ip.h"
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
-enum dc_irq_source to_dal_irq_source_dcn201(
+static enum dc_irq_source to_dal_irq_source_dcn201(
struct irq_service *irq_service,
uint32_t src_id,
uint32_t ext_id)
--
2.39.1
[PATCH 00/10] Resolve warnings from AMDGPU
Hi, This series resolve some of the warnings that appear when compiling AMDGPU with W=1. Each patch is focused in a specific warning. This is my First Patch for the GSoC Project Idea about increasing code coverage of the DRM code[1]. Thanks for reviewing! Best regards, Arthur Grillo [1]: https://www.x.org/wiki/DRMcoverage2023/#firstpatch --- Arthur Grillo (10): drm/amd/display: Turn global functions into static drm/amd/display: Add function prototypes to headers drm/amd/amdgpu: Add function prototypes to headers drm/amd/display: Add previously missing includes drm/amd/display: Fix excess arguments on kernel-doc drm/amd/display: Fix implicit enum conversion drm/amd/amdgpu: Deal with possible fail allocation drm/amd/display: Remove unused local variables drm/amd/display: Make variables declaration inside ifdef guard drm/amd/display: Remove unused local variables and function drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 + drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c| 15 --- .../dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 2 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 2 +- .../amd/display/dc/dcn10/dcn10_link_encoder.c | 3 -- .../drm/amd/display/dc/dcn201/dcn201_dpp.c| 7 .../drm/amd/display/dc/dcn201/dcn201_hwseq.c | 2 - .../gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c | 2 - .../gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 4 -- .../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 3 -- .../gpu/drm/amd/display/dc/dcn31/dcn31_apg.c | 41 --- .../drm/amd/display/dc/dcn31/dcn31_hubbub.h | 2 + .../drm/amd/display/dc/dcn32/dcn32_hubbub.h | 2 + .../gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h | 2 + .../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 1 + .../drm/amd/display/dc/dcn32/dcn32_resource.c | 5 +-- .../display/dc/dcn32/dcn32_resource_helpers.c | 4 -- .../dc/dml/dcn20/display_mode_vba_20.c| 9 ++-- .../dc/dml/dcn20/display_mode_vba_20v2.c | 10 ++--- .../dc/dml/dcn21/display_mode_vba_21.c| 12 +++--- .../dc/dml/dcn31/display_mode_vba_31.c| 4 ++ .../dc/dml/dcn31/display_rq_dlg_calc_31.c | 2 - .../dc/dml/dcn314/display_mode_vba_314.c | 4 ++ .../dc/irq/dcn201/irq_service_dcn201.c| 2 +- .../dc/link/accessories/link_dp_trace.c | 1 + .../dc/link/protocols/link_dp_capability.c| 4 -- 28 files changed, 47 insertions(+), 103 deletions(-) -- 2.39.1
Re: [RFC PATCH v2 00/18] Add DRM CRTC 3D LUT interface
On 02/13, Ville Syrjälä wrote:
> On Mon, Feb 13, 2023 at 11:01:31AM +0200, Pekka Paalanen wrote:
> > On Fri, 10 Feb 2023 14:47:50 -0500
> > Harry Wentland wrote:
> >
> > > On 2/10/23 04:28, Pekka Paalanen wrote:
> > > > On Thu, 9 Feb 2023 13:27:02 -0100
> > > > Melissa Wen wrote:
> > > >
> > > >> On 01/31, Pekka Paalanen wrote:
> > > >>> On Mon, 9 Jan 2023 14:38:09 -0100
> > > >>> Melissa Wen wrote:
> > > >>>
> > > On 01/09, Melissa Wen wrote:
> > > > Hi,
> > > >
> > > > After collecting comments in different places, here is a second
> > > > version
> > > > of the work on adding DRM CRTC 3D LUT support to the current DRM
> > > > color
> > > > mgmt interface. In comparison to previous proposals [1][2][3], here
> > > > we
> > > > add 3D LUT before gamma 1D LUT, but also a shaper 1D LUT before 3D
> > > > LUT,
> > > > that means the following DRM CRTC color correction pipeline:
> > > >
> > > > Blend -> Degamma 1D LUT -> CTM -> Shaper 1D LUT -> 3D LUT -> Gamma
> > > > 1D LUT
> >
> > ...
> >
> > > >>> +/*
> > > >>> + * struct drm_mode_lut3d_mode - 3D LUT mode information.
> > > >>> + * @lut_size: number of valid points on every dimension of 3D LUT.
> > > >>> + * @lut_stride: number of points on every dimension of 3D LUT.
> > > >>> + * @bit_depth: number of bits of RGB. If color_mode defines entries
> > > >>> with higher
> > > >>> + * bit_depth the least significant bits will be
> > > >>> truncated.
> > > >>> + * @color_format: fourcc values, ex. DRM_FORMAT_XRGB16161616 or
> > > >>> DRM_FORMAT_XBGR16161616.
> > > >>> + * @flags: flags for hardware-sepcific features
> > > >>> + */
> > > >>> +struct drm_mode_lut3d_mode {
> > > >>> + __u16 lut_size;
> > > >>> + __u16 lut_stride[3];
> > > >>> + __u16 bit_depth;
> > > >>> + __u32 color_format;
> > > >>> + __u32 flags;
> > > >>> +};
> >
> > ...
> >
> > > >>> What is "number of bits of RGB"? Input precision? Output precision?
> > > >>> Integer or floating point?
> > > >>
> > > >> It's the bit depth of the 3D LUT values, the same for every channels.
> > > >> In
> > > >> the AMD case, it's supports 10-bit and 12-bit, for example.
> > > >
> > > > Ok. So e.g. r5g6b5 is not a possible 3D LUT element type on any
> > > > hardware ever?
> > > >
> > >
> > > I haven't had a chance to go through all patches yet but if this is
> > > modeled after Alex Hung's work this should be covered by color_format.
> > > The idea is that color_format takes a FOURCC value and defines the
> > > format of the entries in the 3DLUT blob.
> > >
> > > The bit_depth describes the actual bit depth that the HW supports.
> > > E.g., color_format could be DRM_FORMAT_XRGB16161616 but HW might only
> > > support 12-bit precision. In that case the least significant bits get
> > > truncated.
> > >
> > > One could define the bit_depth per color, but I'm not sure that'll be
> > > necessary.
> >
> > Exactly. I just have no idea how sure we should be about that.
> >
> > > > What exactly is the truncation the comment refers to?
> > > >
> > > > It sounds like if input has higher precision than the LUT elements,
> > > > then "truncation" occurs. I can kind of see that, but I also think it
> > > > is a false characterisation. The LUT input precision affects the
> > > > precision of LUT indexing and the precision of interpolation between
> > > > the LUT elements. I would not expect those two precisions to be
> > > > truncated to the LUT element precision (but they could be truncated to
> > > > something else hardware specific). Instead, I do expect the
> > > > interpolation result to be truncated to the LUT output precision, which
> > > > probably is the same as the LUT element precision, but not necessarily.
> > > >
> > > > Maybe the comment about truncation should simply be removed? The result
> > > > is obvious if we know the LUT input, element, and output precision, and
> > > > what exactly happens with the indexing and interpolation is probably
> > > > good enough to be left hardware-specific if it is difficult to describe
> > > > in generic terms across different hardware.
> > > >
> > >
> > > Maybe it makes sense to just drop the bit_depth field.
> >
> > Well, it's really interesting information for userspace, but maybe it
> > should have a more holistic design. Precision is a factor, when
> > userspace considers whether it can use KMS hardware for a conversion or
> > not. Unfortunately, none of the existing KMS color pipeline elements
> > have any information on precision IIRC, so there is more to be fixed.
> >
> > The interesting thing is the minimum guaranteed precision of each
> > element and the connections between them. It might be different for
> > pass-through vs. not. Another interesting thing is the usable value
> > range.
> >
> > This is probably a complex problem, so there should be no need to solve
> > it before a 3D LUT interface can land, given old
Re: [RFC PATCH v2 00/18] Add DRM CRTC 3D LUT interface
On 02/10, Pekka Paalanen wrote: > On Thu, 9 Feb 2023 13:27:02 -0100 > Melissa Wen wrote: > > > On 01/31, Pekka Paalanen wrote: > > > On Mon, 9 Jan 2023 14:38:09 -0100 > > > Melissa Wen wrote: > > > > > > > On 01/09, Melissa Wen wrote: > > > > > Hi, > > > > > > > > > > After collecting comments in different places, here is a second > > > > > version > > > > > of the work on adding DRM CRTC 3D LUT support to the current DRM color > > > > > mgmt interface. In comparison to previous proposals [1][2][3], here we > > > > > add 3D LUT before gamma 1D LUT, but also a shaper 1D LUT before 3D > > > > > LUT, > > > > > that means the following DRM CRTC color correction pipeline: > > > > > > > > > > Blend -> Degamma 1D LUT -> CTM -> Shaper 1D LUT -> 3D LUT -> Gamma 1D > > > > > LUT > > > > > > Hi Melissa, > > > > > > that makes sense to me, for CRTCs. It would be really good to have that > > > as a diagram in the KMS UAPI documentation. > > > > > > > Hi Pekka, > > > > Thanks for your feedbacks and your time reviewing this proposal. > > No problem, and sorry it took so long! > > I'm just finishing the catch-up with everything that happened during > winter holidays. > > > > If someone wants to add a 3D LUT to KMS planes as well, then I'm not > > > sure if it should be this order or swapped. I will probably have an > > > opinion about that once Weston is fully HDR capable and has been tried > > > in the wild for a while with the HDR color operations fine-tuned based > > > on community feedback. IOW, not for a long time. The YUV to RGB > > > conversion factors in there as well. > > > > > I see, this is also the reason I reuse here Alex Hung's proposal for > > pre-blending API. I'll work on better documentation. > > > > > > > > > > > > > > > and we also add a DRM CRTC LUT3D_MODE property, based on Alex Hung > > > > > proposal for pre-blending 3D LUT [4] (Thanks!), instead of just a > > > > > LUT3D_SIZE, that allows userspace to use different supported settings > > > > > of > > > > > 3D LUT, fitting VA-API and new color API better. In this sense, I > > > > > adjusted the pre-blending proposal for post-blending usage. > > > > > > > > > > Patches 1-6 targets the addition of shaper LUT and 3D LUT properties > > > > > to > > > > > the current DRM CRTC color mgmt pipeline. Patch 6 can be considered an > > > > > extra/optional patch to define a default value for LUT3D_MODE, > > > > > inspired > > > > > by what we do for the plane blend mode property (pre-multiplied). > > > > > > > > > > Patches 7-18 targets AMD display code to enable shaper and 3D LUT > > > > > usage > > > > > on DCN 301 (our HW case). Patches 7-9 performs code cleanups on > > > > > current > > > > > AMD DM colors code, patch 10 updates AMD stream in case of user 3D LUT > > > > > changes, patch 11/12 rework AMD MPC 3D LUT resource handling by > > > > > context > > > > > for DCN 301 (easily extendible to other DCN families). Finally, from > > > > > 13-18, we wire up SHAPER LUT, LUT3D and LUT3D MODE to AMD display > > > > > driver, exposing modes supported by HW and programming user shaper and > > > > > 3D LUT accordingly. > > > > > > > > > > Our target userspace is Gamescope/SteamOS. > > > > > > > > > > Basic IGT tests were based on [5][6] and are available here > > > > > (in-progress): > > > > > https://gitlab.freedesktop.org/mwen/igt-gpu-tools/-/commits/crtc-lut3d-api > > > > > > > > > > [1] > > > > > https://lore.kernel.org/all/20201221015730.28333-1-laurent.pinchart+rene...@ideasonboard.com/ > > > > > [2] > > > > > https://github.com/vsyrjala/linux/commit/4d28e8ddf2a076f30f9e5bdc17cbb4656fe23e69 > > > > > [3] > > > > > https://lore.kernel.org/amd-gfx/20220619223104.667413-1-m...@igalia.com/ > > > > > [4] > > > > > https://lore.kernel.org/dri-devel/20221004211451.1475215-1-alex.h...@amd.com/ > > > > > [5] https://patchwork.freedesktop.org/series/90165/ > > > > > [6] https://patchwork.freedesktop.org/series/109402/ > > > > > [VA_API] > > > > > http://intel.github.io/libva/structVAProcFilterParameterBuffer3DLUT.html > > > > > [KMS_pipe_API] > > > > > https://gitlab.freedesktop.org/pq/color-and-hdr/-/issues/11 > > > > > > > > > > Let me know your thoughts. > > > > > > > > +Simon Ser, +Pekka Paalanen who might also be interested in this > > > > series. > > > > > > Unfortunately I don't have the patch emails to reply to, so here's a > > > messy bunch of comments. I'll concentrate on the UAPI design as always. > > > > Sorry, the patchset is here: > > https://lore.kernel.org/dri-devel/20230109143846.1966301-1-m...@igalia.com/ > > In the next version, I won't forget cc'ing you at first. > > > > > > +/* > > > + * struct drm_mode_lut3d_mode - 3D LUT mode information. > > > + * @lut_size: number of valid points on every dimension of 3D LUT. > > > + * @lut_stride: number of points on every dimension of 3D LUT. > > > + * @bit_depth: number of bits of RGB. If color_mode defines entries with > > > higher > > >
[linux-next:master] BUILD REGRESSION 09e41676e35ab06e4bce8870ea3bf1f191c3cb90
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 09e41676e35ab06e4bce8870ea3bf1f191c3cb90 Add linux-next specific files for 20230213 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202301300743.bp7dpazv-...@intel.com https://lore.kernel.org/oe-kbuild-all/202301302110.metnwkbd-...@intel.com https://lore.kernel.org/oe-kbuild-all/202302061911.c7xvhx9v-...@intel.com https://lore.kernel.org/oe-kbuild-all/202302062224.byzetxh1-...@intel.com https://lore.kernel.org/oe-kbuild-all/202302092211.54eydhyh-...@intel.com https://lore.kernel.org/oe-kbuild-all/202302111601.jty4lkra-...@intel.com https://lore.kernel.org/oe-kbuild-all/202302112104.g75cghzd-...@intel.com https://lore.kernel.org/oe-kbuild-all/202302131438.5tujp2sy-...@intel.com Error/Warning: (recently discovered and may have been fixed) Documentation/riscv/uabi.rst:24: WARNING: Enumerated list ends without a blank line; unexpected unindent. Documentation/sphinx/templates/kernel-toc.html: 1:36 Invalid token: #} ERROR: modpost: "devm_platform_ioremap_resource" [drivers/dma/fsl-edma.ko] undefined! ERROR: modpost: "devm_platform_ioremap_resource" [drivers/dma/idma64.ko] undefined! drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:294:6: warning: no previous prototype for 'optc3_wait_drr_doublebuffer_pending_clear' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hubbub.c:1011:6: warning: no previous prototype for 'hubbub31_init' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:948:6: warning: no previous prototype for 'hubbub32_init' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubp.c:158:6: warning: no previous prototype for 'hubp32_init' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:62:18: warning: variable 'cursor_bpp' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:1296:32: warning: variable 'result_write_min_hblank' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:280:42: warning: variable 'ds_port' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training.c:1586:38: warning: variable 'result' set but not used [-Wunused-but-set-variable] ftrace-ops.c:(.init.text+0x2c3): undefined reference to `__udivdi3' Unverified Error/Warning (likely false positive, please contact us if interested): drivers/firmware/arm_scmi/bus.c:128:18-22: ERROR: reference preceded by free on line 102 drivers/tty/serial/8250/8250_dfl.c:63 dfl_uart_get_params() error: uninitialized symbol 'clk_freq'. drivers/tty/serial/8250/8250_dfl.c:69 dfl_uart_get_params() error: uninitialized symbol 'fifo_len'. drivers/tty/serial/8250/8250_dfl.c:90 dfl_uart_get_params() error: uninitialized symbol 'reg_layout'. drivers/usb/gadget/composite.c:2082:33: sparse: sparse: restricted __le16 degrades to integer drivers/usb/gadget/function/uvc_configfs.c:545 uvcg_default_output_b_source_id_store() warn: inconsistent returns 'su_mutex'. pahole: .tmp_vmlinux.btf: No such file or directory Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-ds_port-set-but-not-used | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-result_write_min_hblank-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_training.c:warning:variable-result-set-but-not-used |-- arc-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-ds_port-set-but-not-used | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-result_write_min_hblank-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_training.c:warning:variable-result-set-but-not-used |-- arm-allmodconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-ds_port-set-but-not-used | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-result_write_min_hblank-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_training.c:warning:variable-result-set-but-not-used |-- arm-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:variable-ds_port-set-but-not-used | |-- drivers-gpu-drm-amd-amdgpu-..-display-dc-link-protocols-link_dp_capability.c:warning:varia
Re: [PATCH] drm/amd/display: Remove the unused variable pre_connection_type
Applied. Thanks!
On Thu, Feb 9, 2023 at 9:44 PM Jiapeng Chong
wrote:
>
> Variable pre_connection_type is not effectively used, so delete it.
>
> Reported-by: Abaci Robot
> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4031
> Signed-off-by: Jiapeng Chong
> ---
> drivers/gpu/drm/amd/display/dc/link/link_detection.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
> b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
> index 63e75c392031..d224a44c4cc8 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
> @@ -886,7 +886,6 @@ static bool detect_link_and_local_sink(struct dc_link
> *link,
> struct dc_sink *prev_sink = NULL;
> struct dpcd_caps prev_dpcd_caps;
> enum dc_connection_type new_connection_type = dc_connection_none;
> - enum dc_connection_type pre_connection_type = dc_connection_none;
> const uint32_t post_oui_delay = 30; // 30ms
>
> DC_LOGGER_INIT(link->ctx->logger);
> @@ -923,7 +922,6 @@ static bool detect_link_and_local_sink(struct dc_link
> *link,
>
> link_disconnect_sink(link);
> if (new_connection_type != dc_connection_none) {
> - pre_connection_type = link->type;
> link->type = new_connection_type;
> link->link_state_valid = false;
>
> --
> 2.20.1.7.g153144c
>
Re: [PATCH] drm/amd/display: Remove the unused variable ds_port
Applied. Thanks!
On Thu, Feb 9, 2023 at 9:28 PM Jiapeng Chong
wrote:
>
> Variable ds_port is not effectively used, so delete it.
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:280:35:
> warning: variable ‘ds_port’ set but not used.
>
> Reported-by: Abaci Robot
> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4030
> Signed-off-by: Jiapeng Chong
> ---
> .../drm/amd/display/dc/link/protocols/link_dp_capability.c| 4
> 1 file changed, 4 deletions(-)
>
> diff --git
> a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> index 24d356ebd7a9..816bf4ff8017 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> @@ -277,7 +277,6 @@ static void dp_wa_power_up_0010FA(struct dc_link *link,
> uint8_t *dpcd_data,
> int length)
> {
> int retry = 0;
> - union dp_downstream_port_present ds_port = { 0 };
>
> if (!link->dpcd_caps.dpcd_rev.raw) {
> do {
> @@ -290,9 +289,6 @@ static void dp_wa_power_up_0010FA(struct dc_link *link,
> uint8_t *dpcd_data,
> } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
> }
>
> - ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
> -DP_DPCD_REV];
> -
> if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
> switch (link->dpcd_caps.branch_dev_id) {
> /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power
> down
> --
> 2.20.1.7.g153144c
>
Re: [PATCH -next] drm/amd/display: clean up some inconsistent indentings
Applied. Thanks! On Thu, Feb 9, 2023 at 8:06 PM Yang Li wrote: > > drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:145 > get_ddc_line() warn: inconsistent indenting > drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:201 > dc_link_construct_phy() warn: inconsistent indenting > > Reported-by: Abaci Robot > Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4026 > Signed-off-by: Yang Li > --- > drivers/gpu/drm/amd/display/dc/link/link_factory.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c > b/drivers/gpu/drm/amd/display/dc/link/link_factory.c > index 13a766273755..23f668d90460 100644 > --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c > +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c > @@ -142,7 +142,7 @@ static enum channel_id get_ddc_line(struct dc_link *link) > struct ddc *ddc; > enum channel_id channel; > > - channel = CHANNEL_ID_UNKNOWN; > + channel = CHANNEL_ID_UNKNOWN; > > ddc = get_ddc_pin(link->ddc); > > @@ -196,8 +196,8 @@ static bool dc_link_construct_phy(struct dc_link *link, > > DC_LOGGER_INIT(dc_ctx->logger); > > - link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; > - link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID; > + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; > + link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID; > link->link_status.dpcd_caps = &link->dpcd_caps; > > link->dc = init_params->dc; > -- > 2.20.1.7.g153144c >
Re: [PATCH -next] drm/amd/display: Simplify bool conversion
Applied. Thanks.
On Thu, Feb 9, 2023 at 7:59 PM Yang Li wrote:
>
> ./drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c:1610:68-73:
> WARNING: conversion to bool not needed here
>
> Reported-by: Abaci Robot
> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4025
> Signed-off-by: Yang Li
> ---
> .../gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
> a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> index 24d356ebd7a9..cb38afde3fc8 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
> @@ -1607,7 +1607,7 @@ static bool retrieve_link_cap(struct dc_link *link)
> dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
>
> link->dpcd_caps.ext_receiver_cap_field_present =
> -
> aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1 ? true:false;
> +
> aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
>
> if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1)
> {
> uint8_t ext_cap_data[16];
> --
> 2.20.1.7.g153144c
>
Re: [PATCH] drm/amd/display: Fail atomic_check early on normalize_zpos error
On 2/13/23 10:51, sunpeng...@amd.com wrote:
From: Leo Li
[Why]
drm_atomic_normalize_zpos() can return an error code when there's
modeset lock contention. This was being ignored.
[How]
Bail out of atomic check if normalize_zpos() returns an error.
Fixes: b261509952bc ("drm/amd/display: Fix double cursor on non-video RGB MPO")
Signed-off-by: Leo Li
Tested-by: Mikhail Gavrilov
Cc: sta...@vger.kernel.org
Reviewed-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c10982f841f98..cb2a57503000d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9889,7 +9889,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
* `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
* atomic state, so call drm helper to normalize zpos.
*/
- drm_atomic_normalize_zpos(dev, state);
+ ret = drm_atomic_normalize_zpos(dev, state);
+ if (ret) {
+ drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
+ goto fail;
+ }
/* Remove exiting planes if they are modified */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state,
new_plane_state, i) {
--
Hamza
Re: [PATCH] drm/amd/amdgpu: fix warining during suspend
Am 13.02.23 um 11:52 schrieb Jack Xiao:
Freeing memory was warned during suspend.
Move the self test out of suspend.
Link: https://bugzilla.redhat.com/show_bug.cgi?id=2151825
Cc: jfale...@redhat.com
Signed-off-by: Jack Xiao
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a10b627c8357..3842e7e62eda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4270,6 +4270,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool
fbcon)
}
adev->in_suspend = false;
+ if (adev->enable_mes)
+ amdgpu_mes_self_test(adev);
+
if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
DRM_WARN("smart shift update failed\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 62cdd2113135..5826eac270d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1284,7 +1284,7 @@ static int mes_v11_0_late_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* it's only intended for use in mes_self_test case, not for s0ix and reset */
- if (!amdgpu_in_reset(adev) && !adev->in_s0ix &&
+ if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend &&
(adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)))
amdgpu_mes_self_test(adev);
[PATCH] drm/amd/display: Fail atomic_check early on normalize_zpos error
From: Leo Li
[Why]
drm_atomic_normalize_zpos() can return an error code when there's
modeset lock contention. This was being ignored.
[How]
Bail out of atomic check if normalize_zpos() returns an error.
Fixes: b261509952bc ("drm/amd/display: Fix double cursor on non-video RGB MPO")
Signed-off-by: Leo Li
Tested-by: Mikhail Gavrilov
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c10982f841f98..cb2a57503000d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9889,7 +9889,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
* `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
* atomic state, so call drm helper to normalize zpos.
*/
- drm_atomic_normalize_zpos(dev, state);
+ ret = drm_atomic_normalize_zpos(dev, state);
+ if (ret) {
+ drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
+ goto fail;
+ }
/* Remove exiting planes if they are modified */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state,
new_plane_state, i) {
--
2.39.1
RE: [PATCH 00/22] DC Patches Feb 13, 2023
[Public] Hi all, This week this patchset was tested on the following systems: Lenovo Thinkpad T14s Gen2, with AMD Ryzen 5 5650U Lenovo Thinkpad T13s Gen4 with AMD Ryzen 5 6600U Reference AMD RX6800 These systems were tested on the following display types: eDP, (1080p 60hz [5650U]) (1920x1200 60hz [6600U]) (2560x1600 120hz[6600U]) VGA and DVI (1680x1050 60HZ [DP to VGA/DVI, USB-C to DVI/VGA]) DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz [Includes USB-C to DP/HDMI adapters]) MST tested with Startech MST14DP123DP and 2x 4k 60Hz displays DSC tested with Cable Matters 101075 (DP to 3x DP), and 201375 (USB-C to 3x DP) with 3x 4k60 displays HP Hook G2 with 1 and 2 4k60 Displays The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to): Changing display configurations and settings Benchmark testing Feature testing (Freesync, etc.) Automated testing includes (but is not limited to): Script testing (scripts to automate some of the manual checks) IGT testing The patchset consists of the amd-staging-drm-next branch (Head commit - 87b54ffb9424 drm/amd/pm: bump SMU 13.0.7 driver_if header version) with new patches added on top of it. This branch is used for both Ubuntu and Chrome OS testing (ChromeOS on a bi-weekly basis). Tested on Ubuntu 22.04.1 and Chrome OS Tested-by: Daniel Wheeler Thank you, Dan Wheeler Sr. Technologist | AMD SW Display -- 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 amd.com -Original Message- From: Zhuo, Qingqing (Lillian) Sent: February 12, 2023 12:00 PM To: amd-gfx@lists.freedesktop.org Cc: Wentland, Harry ; Li, Sun peng (Leo) ; Lakha, Bhawanpreet ; Siqueira, Rodrigo ; Pillai, Aurabindo ; Zhuo, Qingqing (Lillian) ; Li, Roman ; Lin, Wayne ; Wang, Chao-kai (Stylon) ; Chiu, Solomon ; Kotarac, Pavle ; Gutierrez, Agustin ; Wheeler, Daniel Subject: [PATCH 00/22] DC Patches Feb 13, 2023 This DC patchset brings improvements in multiple areas. In summary, we highlight: - Move domain power control to DMCUB for DCN314 - Enable P-state validation check for DCN314 - Add support for multiple overlay planes - Fixes in prefetch, k1 k2 divider programming and more - Code cleanup Cc: Daniel Wheeler Alvin Lee (2): drm/amd/display: Set max vratio for prefetch to 7.9 for YUV420 MPO drm/amd/display: Fix prefetch vratio check Aric Cyr (1): drm/amd/display: Promote DAL to 3.2.223 Aurabindo Pillai (1): drm/amd/display: fix k1 k2 divider programming for phantom streams Ayush Gupta (1): drm/amd/display: temporary fix for page faulting Bhawanpreet Lakha (1): drm/amd/display: Add support for multiple overlay planes Charlene Liu (1): drm/amd/display: add NULL pointer check Daniel Miess (1): Revert "drm/amd/display: Correct bw_params population" Leo (Hanghong) Ma (1): drm/amd/display: Fix FreeSync active bit issue Mustapha Ghaddar (1): drm/amd/display: upstream link_dp_dpia_bw.c Nasir Osman (2): drm/amd/display: Remove stutter only configurations drm/amd/display: Disable unbounded request mode during rotation Nicholas Kazlauskas (4): drm/amd/display: Move DCN314 DOMAIN power control to DMCUB drm/amd/display: Enable P-state validation checks for DCN314 drm/amd/display: Update Z8 SR exit/enter latencies drm/amd/display: Disable HUBP/DPP PG on DCN314 for now Samson Tam (1): drm/amd/display: enable DPG when disabling plane for phantom pipe Tom Chung (1): drm/amd/display: Fix video glitch while drag window in PSR-SU Wenjing Liu (4): drm/amd/display: do not set RX back to SST mode for non 0 mst stream count drm/amd/display: Extract temp drm mst deallocation wa into its own function drm/amd/display: on dp link lost event toggle dpms for master pipe only drm/amd/display: move public dc link function implementation to dc_link_exports .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 83 +++- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 22 +- .../amd/display/amdgpu_dm/amdgpu_dm_plane.h | 1 + drivers/gpu/drm/amd/display/dc/Makefile | 2 +- .../dc/clk_mgr/dcn314/dcn314_clk_mgr.c| 31 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 47 +- .../drm/amd/display/dc/core/dc_link_exports.c | 103 + drivers/gpu/drm/amd/display/dc/dc.h | 211 + drivers/gpu/drm/amd/display/dc/dc_ddc_types.h | 3 + drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 136 ++ drivers/gpu/drm/amd/display/dc/dc_link.h | 60 +-- drivers/gpu/drm/amd/display/dc/dc_types.h | 109 ++--- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 +- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 16 +- .../drm/amd/display/dc/dcn30/dcn30_resource.h | 3 +- .../drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +- .../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 24 + .../drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 + .../drm/
Re: [RFC PATCH v2 00/18] Add DRM CRTC 3D LUT interface
On Mon, Feb 13, 2023 at 11:01:31AM +0200, Pekka Paalanen wrote:
> On Fri, 10 Feb 2023 14:47:50 -0500
> Harry Wentland wrote:
>
> > On 2/10/23 04:28, Pekka Paalanen wrote:
> > > On Thu, 9 Feb 2023 13:27:02 -0100
> > > Melissa Wen wrote:
> > >
> > >> On 01/31, Pekka Paalanen wrote:
> > >>> On Mon, 9 Jan 2023 14:38:09 -0100
> > >>> Melissa Wen wrote:
> > >>>
> > On 01/09, Melissa Wen wrote:
> > > Hi,
> > >
> > > After collecting comments in different places, here is a second
> > > version
> > > of the work on adding DRM CRTC 3D LUT support to the current DRM color
> > > mgmt interface. In comparison to previous proposals [1][2][3], here we
> > > add 3D LUT before gamma 1D LUT, but also a shaper 1D LUT before 3D
> > > LUT,
> > > that means the following DRM CRTC color correction pipeline:
> > >
> > > Blend -> Degamma 1D LUT -> CTM -> Shaper 1D LUT -> 3D LUT -> Gamma 1D
> > > LUT
>
> ...
>
> > >>> +/*
> > >>> + * struct drm_mode_lut3d_mode - 3D LUT mode information.
> > >>> + * @lut_size: number of valid points on every dimension of 3D LUT.
> > >>> + * @lut_stride: number of points on every dimension of 3D LUT.
> > >>> + * @bit_depth: number of bits of RGB. If color_mode defines entries
> > >>> with higher
> > >>> + * bit_depth the least significant bits will be truncated.
> > >>> + * @color_format: fourcc values, ex. DRM_FORMAT_XRGB16161616 or
> > >>> DRM_FORMAT_XBGR16161616.
> > >>> + * @flags: flags for hardware-sepcific features
> > >>> + */
> > >>> +struct drm_mode_lut3d_mode {
> > >>> + __u16 lut_size;
> > >>> + __u16 lut_stride[3];
> > >>> + __u16 bit_depth;
> > >>> + __u32 color_format;
> > >>> + __u32 flags;
> > >>> +};
>
> ...
>
> > >>> What is "number of bits of RGB"? Input precision? Output precision?
> > >>> Integer or floating point?
> > >>
> > >> It's the bit depth of the 3D LUT values, the same for every channels. In
> > >> the AMD case, it's supports 10-bit and 12-bit, for example.
> > >
> > > Ok. So e.g. r5g6b5 is not a possible 3D LUT element type on any
> > > hardware ever?
> > >
> >
> > I haven't had a chance to go through all patches yet but if this is
> > modeled after Alex Hung's work this should be covered by color_format.
> > The idea is that color_format takes a FOURCC value and defines the
> > format of the entries in the 3DLUT blob.
> >
> > The bit_depth describes the actual bit depth that the HW supports.
> > E.g., color_format could be DRM_FORMAT_XRGB16161616 but HW might only
> > support 12-bit precision. In that case the least significant bits get
> > truncated.
> >
> > One could define the bit_depth per color, but I'm not sure that'll be
> > necessary.
>
> Exactly. I just have no idea how sure we should be about that.
>
> > > What exactly is the truncation the comment refers to?
> > >
> > > It sounds like if input has higher precision than the LUT elements,
> > > then "truncation" occurs. I can kind of see that, but I also think it
> > > is a false characterisation. The LUT input precision affects the
> > > precision of LUT indexing and the precision of interpolation between
> > > the LUT elements. I would not expect those two precisions to be
> > > truncated to the LUT element precision (but they could be truncated to
> > > something else hardware specific). Instead, I do expect the
> > > interpolation result to be truncated to the LUT output precision, which
> > > probably is the same as the LUT element precision, but not necessarily.
> > >
> > > Maybe the comment about truncation should simply be removed? The result
> > > is obvious if we know the LUT input, element, and output precision, and
> > > what exactly happens with the indexing and interpolation is probably
> > > good enough to be left hardware-specific if it is difficult to describe
> > > in generic terms across different hardware.
> > >
> >
> > Maybe it makes sense to just drop the bit_depth field.
>
> Well, it's really interesting information for userspace, but maybe it
> should have a more holistic design. Precision is a factor, when
> userspace considers whether it can use KMS hardware for a conversion or
> not. Unfortunately, none of the existing KMS color pipeline elements
> have any information on precision IIRC, so there is more to be fixed.
>
> The interesting thing is the minimum guaranteed precision of each
> element and the connections between them. It might be different for
> pass-through vs. not. Another interesting thing is the usable value
> range.
>
> This is probably a complex problem, so there should be no need to solve
> it before a 3D LUT interface can land, given old elements already have
> the issue.
Yeah, I think all the precision stuff is all better handled by
eg. the proposed GAMMA_MODE property or something similar.
It's going to be needed for 1D LUTs as well. 1D LUTs would
also need it to expose diffrent LUT sizes with different
precision
Re: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new bad page
On 2/10/2023 2:15 PM, Tao Zhou wrote:
If a UMC bad page is reserved but not freed by an application, the
application may trigger uncorrectable error repeatly by accessing the page.
There is amdgpu_ras_check_bad_page which checks if address is already
part of an existing bad page. Can't that be used?
Thanks,
Lijo
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 -
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 6 +-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e85c4689ce2c..eafe01a24349 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2049,7 +2049,7 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data *data;
- int ret = 0;
+ int ret = 0, old_cnt;
uint32_t i;
if (!con || !con->eh_data || !bps || pages <= 0)
@@ -2060,6 +2060,8 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
if (!data)
goto out;
+ old_cnt = data->count;
+
for (i = 0; i < pages; i++) {
if (amdgpu_ras_check_bad_page_unlock(con,
bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
@@ -2079,6 +2081,11 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
data->count++;
data->space_left--;
}
+
+ /* all pages have been reserved before, no new bad page */
+ if (old_cnt == data->count)
+ ret = -EEXIST;
+
out:
mutex_unlock(&con->recovery_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 1c7fcb4f2380..772c431e4065 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -145,8 +145,12 @@ static int amdgpu_umc_do_page_retirement(struct
amdgpu_device *adev,
if ((amdgpu_bad_page_threshold != 0) &&
err_data->err_addr_cnt) {
- amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
+ ret = amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
err_data->err_addr_cnt);
+ /* if no new bad page is found, no need to increase ue
count */
+ if (ret == -EEXIST)
+ err_data->ue_count = 0;
+
amdgpu_ras_save_bad_pages(adev);
amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
Re: [regression][6.0] After commit b261509952bc19d1012cf732f853659be6ebc61e I see WARNING message at drivers/gpu/drm/drm_modeset_lock.c:276 drm_modeset_drop_locks+0x63/0x70
On Thu, Feb 9, 2023 at 10:17 PM Leo Li wrote: > > Hi Mikhail, seems like your report flew past me, thanks for the ping. > > This might be a simple issue of not backing off when deadlock was hit. > drm_atomic_normalize_zpos() can return an error code, and I ignored it > (oops!) > > Can you give this patch a try? > https://gitlab.freedesktop.org/-/snippets/7414 > > - Leo > Thanks, I think the time for testing was enough. I observed three computers with different GPUs 6800M, 6900XT and 7900XTX for more than 3 days. And a warning message about drm_modeset_drop_locks no longer appears anymore. I hope this patch will have time to be merged in 6.2 before release. Tested-by: Mikhail Gavrilov -- Best Regards, Mike Gavrilov. uptime.tar.xz Description: application/xz
[PATCH] drm/amd/amdgpu: fix warining during suspend
Freeing memory was warned during suspend.
Move the self test out of suspend.
Link: https://bugzilla.redhat.com/show_bug.cgi?id=2151825
Cc: jfale...@redhat.com
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a10b627c8357..3842e7e62eda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4270,6 +4270,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool
fbcon)
}
adev->in_suspend = false;
+ if (adev->enable_mes)
+ amdgpu_mes_self_test(adev);
+
if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
DRM_WARN("smart shift update failed\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 62cdd2113135..5826eac270d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1284,7 +1284,7 @@ static int mes_v11_0_late_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* it's only intended for use in mes_self_test case, not for s0ix and
reset */
- if (!amdgpu_in_reset(adev) && !adev->in_s0ix &&
+ if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend &&
(adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)))
amdgpu_mes_self_test(adev);
--
2.37.3
Re: [RFC PATCH v2 00/18] Add DRM CRTC 3D LUT interface
On Fri, 10 Feb 2023 14:47:50 -0500
Harry Wentland wrote:
> On 2/10/23 04:28, Pekka Paalanen wrote:
> > On Thu, 9 Feb 2023 13:27:02 -0100
> > Melissa Wen wrote:
> >
> >> On 01/31, Pekka Paalanen wrote:
> >>> On Mon, 9 Jan 2023 14:38:09 -0100
> >>> Melissa Wen wrote:
> >>>
> On 01/09, Melissa Wen wrote:
> > Hi,
> >
> > After collecting comments in different places, here is a second version
> > of the work on adding DRM CRTC 3D LUT support to the current DRM color
> > mgmt interface. In comparison to previous proposals [1][2][3], here we
> > add 3D LUT before gamma 1D LUT, but also a shaper 1D LUT before 3D LUT,
> > that means the following DRM CRTC color correction pipeline:
> >
> > Blend -> Degamma 1D LUT -> CTM -> Shaper 1D LUT -> 3D LUT -> Gamma 1D
> > LUT
...
> >>> +/*
> >>> + * struct drm_mode_lut3d_mode - 3D LUT mode information.
> >>> + * @lut_size: number of valid points on every dimension of 3D LUT.
> >>> + * @lut_stride: number of points on every dimension of 3D LUT.
> >>> + * @bit_depth: number of bits of RGB. If color_mode defines entries with
> >>> higher
> >>> + * bit_depth the least significant bits will be truncated.
> >>> + * @color_format: fourcc values, ex. DRM_FORMAT_XRGB16161616 or
> >>> DRM_FORMAT_XBGR16161616.
> >>> + * @flags: flags for hardware-sepcific features
> >>> + */
> >>> +struct drm_mode_lut3d_mode {
> >>> + __u16 lut_size;
> >>> + __u16 lut_stride[3];
> >>> + __u16 bit_depth;
> >>> + __u32 color_format;
> >>> + __u32 flags;
> >>> +};
...
> >>> What is "number of bits of RGB"? Input precision? Output precision?
> >>> Integer or floating point?
> >>
> >> It's the bit depth of the 3D LUT values, the same for every channels. In
> >> the AMD case, it's supports 10-bit and 12-bit, for example.
> >
> > Ok. So e.g. r5g6b5 is not a possible 3D LUT element type on any
> > hardware ever?
> >
>
> I haven't had a chance to go through all patches yet but if this is
> modeled after Alex Hung's work this should be covered by color_format.
> The idea is that color_format takes a FOURCC value and defines the
> format of the entries in the 3DLUT blob.
>
> The bit_depth describes the actual bit depth that the HW supports.
> E.g., color_format could be DRM_FORMAT_XRGB16161616 but HW might only
> support 12-bit precision. In that case the least significant bits get
> truncated.
>
> One could define the bit_depth per color, but I'm not sure that'll be
> necessary.
Exactly. I just have no idea how sure we should be about that.
> > What exactly is the truncation the comment refers to?
> >
> > It sounds like if input has higher precision than the LUT elements,
> > then "truncation" occurs. I can kind of see that, but I also think it
> > is a false characterisation. The LUT input precision affects the
> > precision of LUT indexing and the precision of interpolation between
> > the LUT elements. I would not expect those two precisions to be
> > truncated to the LUT element precision (but they could be truncated to
> > something else hardware specific). Instead, I do expect the
> > interpolation result to be truncated to the LUT output precision, which
> > probably is the same as the LUT element precision, but not necessarily.
> >
> > Maybe the comment about truncation should simply be removed? The result
> > is obvious if we know the LUT input, element, and output precision, and
> > what exactly happens with the indexing and interpolation is probably
> > good enough to be left hardware-specific if it is difficult to describe
> > in generic terms across different hardware.
> >
>
> Maybe it makes sense to just drop the bit_depth field.
Well, it's really interesting information for userspace, but maybe it
should have a more holistic design. Precision is a factor, when
userspace considers whether it can use KMS hardware for a conversion or
not. Unfortunately, none of the existing KMS color pipeline elements
have any information on precision IIRC, so there is more to be fixed.
The interesting thing is the minimum guaranteed precision of each
element and the connections between them. It might be different for
pass-through vs. not. Another interesting thing is the usable value
range.
This is probably a complex problem, so there should be no need to solve
it before a 3D LUT interface can land, given old elements already have
the issue.
Thanks,
pq
pgpqZF2w9aRpC.pgp
Description: OpenPGP digital signature
Re: [RFC PATCH 1/9] apple-gmux: use cpu_to_be32 instead of manual reorder
Hi,
On 2/11/23 00:30, Orlando Chamberlain wrote:
> On Fri, 10 Feb 2023 20:19:27 +0100
> Hans de Goede wrote:
>
>> Hi,
>>
>> On 2/10/23 20:09, Hans de Goede wrote:
>>> Hi,
>>>
>>> On 2/10/23 05:48, Orlando Chamberlain wrote:
Currently it manually flips the byte order, but we can instead use
cpu_to_be32(val) for this.
Signed-off-by: Orlando Chamberlain
---
drivers/platform/x86/apple-gmux.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/drivers/platform/x86/apple-gmux.c
b/drivers/platform/x86/apple-gmux.c index
9333f82cfa8a..e8cb084cb81f 100644 ---
a/drivers/platform/x86/apple-gmux.c +++
b/drivers/platform/x86/apple-gmux.c @@ -94,13 +94,7 @@ static u32
gmux_pio_read32(struct apple_gmux_data *gmux_data, int port)
static void gmux_pio_write32(struct apple_gmux_data *gmux_data,
int port, u32 val) {
- int i;
- u8 tmpval;
-
- for (i = 0; i < 4; i++) {
- tmpval = (val >> (i * 8)) & 0xff;
- outb(tmpval, gmux_data->iostart + port + i);
- }
+ outl(cpu_to_be32(val), gmux_data->iostart + port);
}
static int gmux_index_wait_ready(struct apple_gmux_data
*gmux_data)
>>>
>>> The ioport / indexed-ioport accessed apple_gmux-es likely are (part
>>> of?) LPC bus devices . Looking at the bus level you are now
>>> changing 4 io accesses with a size of 1 byte, to 1 32 bit io-access.
>>>
>>> Depending on the decoding hw in the chip this may work fine,
>>> or this may work not at all.
>>>
>>> I realized that you have asked for more testing, but most surviving
>>> macbooks from the older apple-gmux era appear to be models without
>>> a discrete GPU (which are often the first thing to break) and thus
>>> without a gmux.
>>>
>>> Unless we get a bunch of testers to show up, which I doubt. I would
>>> prefer slightly bigger / less pretty code and not change the
>>> functional behavior of the driver on these older models.
>>
>> A quick follow up on this, I just noticed that only the pio_write32
>> is doing the one byte at a time thing:
>>
>> static u32 gmux_pio_read32(struct apple_gmux_data *gmux_data, int
>> port) {
>> return inl(gmux_data->iostart + port);
>> }
>>
>> static void gmux_pio_write32(struct apple_gmux_data *gmux_data, int
>> port, u32 val)
>> {
>> int i;
>> u8 tmpval;
>>
>> for (i = 0; i < 4; i++) {
>> tmpval = (val >> (i * 8)) & 0xff;
>> outb(tmpval, gmux_data->iostart + port + i);
>> }
>> }
>>
>> And if you look closely gmux_pio_write32() is not swapping
>> the order to be32 at all, it is just taking the bytes
>> in little-endian memory order, starting with the first
>> (index 0) byte which is the least significant byte of
>> the value.
>>
>> On x86 the original code is no different then doing:
>>
>> static void gmux_pio_write32(struct apple_gmux_data *gmux_data, int
>> port, u32 val)
>> {
>> u8 *data = (u8 *)&val;
>> int i;
>>
>> for (i = 0; i < 4; i++)
>> outb(data[i], gmux_data->iostart + port + i);
>> }
>>
>> So yeah this patch is definitely wrong, it actually swaps
>> the byte order compared to the original code. Which becomes
>> clear when you look the weird difference between the read32 and
>> write32 functions after this patch.
>>
>> Presumably there is a specific reason why gmux_pio_write32()
>> is not already doing a single outl(..., val) and byte-ordering
>> is not the reason.
>>
>> Regards,
>>
>> Hans
>
> Sounds like it may be better to just drop this patch as there's very
> little benefit for the risk of causing a regression.
Yes if it is easy to drop this please drop this.
And the same more or less applies to 2/9. I would rather have
an extra "if () ... else ..." in the code in a couple of places
then change behavior on old hw where we cannot get proper test
coverage (but will likely eventually get regressions reports
if we break things).
Thanks & Regards,
Hans
@@ -177,16 +171,8 @@ static u32 gmux_index_read32(struct
apple_gmux_data *gmux_data, int port) static void
gmux_index_write32(struct apple_gmux_data *gmux_data, int port,
u32 val) {
- int i;
- u8 tmpval;
-
mutex_lock(&gmux_data->index_lock);
-
- for (i = 0; i < 4; i++) {
- tmpval = (val >> (i * 8)) & 0xff;
- outb(tmpval, gmux_data->iostart + GMUX_PORT_VALUE
+ i);
- }
-
+ outl(cpu_to_be32(val), gmux_data->iostart +
GMUX_PORT_VALUE); gmux_index_wait_ready(gmux_data);
outb(port & 0xff, gmux_data->iostart + GMUX_PORT_WRITE);
gmux_index_wait_complete(gmux_data);
>>>
>>
>
RE: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new bad page
[AMD Official Use Only - General]
> -Original Message-
> From: Zhang, Hawking
> Sent: Friday, February 10, 2023 11:02 PM
> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org; Yang,
> Stanley ; Chai, Thomas ; Li,
> Candice
> Subject: RE: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new
> bad page
>
> [AMD Official Use Only - General]
>
> + /* if no new bad page is found, no need to increase
> ue count */
> + if (ret == -EEXIST)
> + err_data->ue_count = 0;
>
> Returning EEXIST in such case is not reasonable. Might consider return a bool
> for
> amdgpu_ras_add_bad_pages: true means it does add some new bad page; false
> means it doesn't change anything.
>
> Regards,
> Hawking
[Tao] but it can returns -ENOMEM, amdgpu_ras_load_bad_pages and
amdgpu_ras_recovery_init also need to check the return value. I'd like to keep
the type of return value unchanged.
How about -EINVAL?
>
> -Original Message-
> From: Zhou1, Tao
> Sent: Friday, February 10, 2023 16:45
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Yang, Stanley ; Chai,
> Thomas ; Li, Candice
> Cc: Zhou1, Tao
> Subject: [PATCH] drm/amdgpu: don't increase UMC RAS UE count if no new bad
> page
>
> If a UMC bad page is reserved but not freed by an application, the application
> may trigger uncorrectable error repeatly by accessing the page.
>
> Signed-off-by: Tao Zhou
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 6 +-
> 2 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index e85c4689ce2c..eafe01a24349 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -2049,7 +2049,7 @@ int amdgpu_ras_add_bad_pages(struct
> amdgpu_device *adev, {
> struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
> struct ras_err_handler_data *data;
> - int ret = 0;
> + int ret = 0, old_cnt;
> uint32_t i;
>
> if (!con || !con->eh_data || !bps || pages <= 0) @@ -2060,6 +2060,8 @@
> int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
> if (!data)
> goto out;
>
> + old_cnt = data->count;
> +
> for (i = 0; i < pages; i++) {
> if (amdgpu_ras_check_bad_page_unlock(con,
> bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) @@
> -2079,6
> +2081,11 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
> data->count++;
> data->space_left--;
> }
> +
> + /* all pages have been reserved before, no new bad page */
> + if (old_cnt == data->count)
> + ret = -EEXIST;
> +
> out:
> mutex_unlock(&con->recovery_lock);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> index 1c7fcb4f2380..772c431e4065 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
> @@ -145,8 +145,12 @@ static int amdgpu_umc_do_page_retirement(struct
> amdgpu_device *adev,
>
> if ((amdgpu_bad_page_threshold != 0) &&
> err_data->err_addr_cnt) {
> - amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
> + ret = amdgpu_ras_add_bad_pages(adev,
> err_data->err_addr,
> err_data->err_addr_cnt);
> + /* if no new bad page is found, no need to increase
> ue count */
> + if (ret == -EEXIST)
> + err_data->ue_count = 0;
> +
> amdgpu_ras_save_bad_pages(adev);
>
> amdgpu_dpm_send_hbm_bad_pages_num(adev, con-
> >eeprom_control.ras_num_recs);
> --
> 2.35.1
>
