RE: [PATCH 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Samir Dhume
> Sent: Monday, July 17, 2023 11:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Dhume, Samir
> Subject: [PATCH 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
>
> initialization table handshake with mmsch
>
> Signed-off-by: Samir Dhume
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 264
> +---
> 1 file changed, 240 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 411c1d802823..ac405dfcfaf1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -31,6 +31,7 @@
> #include "soc15d.h"
> #include "soc15_hw_ip.h"
> #include "vcn_v2_0.h"
> +#include "mmsch_v4_0_3.h"
>
> #include "vcn/vcn_4_0_3_offset.h"
> #include "vcn/vcn_4_0_3_sh_mask.h"
> @@ -44,6 +45,7 @@
> #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
> #define VCN1_VID_SOC_ADDRESS_3_0 0x48300
>
> +static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); static
> int vcn_v4_0_3_set_powergating_state(void *handle, @@ -130,6 +132,12
> @@ static int vcn_v4_0_3_sw_init(void *handle)
> amdgpu_vcn_fwlog_init(>vcn.inst[i]);
> }
>
> + if (amdgpu_sriov_vf(adev)) {
> + r = amdgpu_virt_alloc_mm_table(adev);
amdgpu_virt_alloc_mm_table has an early check of amdgpu_sriov_vf(adev), so from
coding style's perspective, I think you can drop this superfluous check here
and directly call amdgpu_virt_alloc_mm_table.
> + if (r)
> + return r;
> + }
> +
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> adev->vcn.pause_dpg_mode =
> vcn_v4_0_3_pause_dpg_mode;
>
> @@ -167,6 +175,9 @@ static int vcn_v4_0_3_sw_fini(void *handle)
> drm_dev_exit(idx);
> }
>
> + if (amdgpu_sriov_vf(adev))
> + amdgpu_virt_free_mm_table(adev);
Same as above.
Regards,
Guchun
> r = amdgpu_vcn_suspend(adev);
> if (r)
> return r;
> @@ -189,33 +200,50 @@ static int vcn_v4_0_3_hw_init(void *handle)
> struct amdgpu_ring *ring;
> int i, r, vcn_inst;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - vcn_inst = GET_INST(VCN, i);
> - ring = >vcn.inst[i].ring_enc[0];
> + if (amdgpu_sriov_vf(adev)) {
> + r = vcn_v4_0_3_start_sriov(adev);
> + if (r)
> + goto done;
>
> - if (ring->use_doorbell) {
> - adev->nbio.funcs->vcn_doorbell_range(
> - adev, ring->use_doorbell,
> - (adev->doorbell_index.vcn.vcn_ring0_1 << 1)
> +
> - 9 * vcn_inst,
> - adev->vcn.inst[i].aid_id);
> -
> - WREG32_SOC15(
> - VCN, GET_INST(VCN, ring->me),
> - regVCN_RB1_DB_CTRL,
> - ring->doorbell_index
> - <<
> VCN_RB1_DB_CTRL__OFFSET__SHIFT |
> - VCN_RB1_DB_CTRL__EN_MASK);
> -
> - /* Read DB_CTRL to flush the write DB_CTRL
> command. */
> - RREG32_SOC15(
> - VCN, GET_INST(VCN, ring->me),
> - regVCN_RB1_DB_CTRL);
> + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + if (adev->vcn.harvest_config & (1 << i))
> + continue;
> +
> + ring = >vcn.inst[i].ring_enc[0];
> + ring->wptr = 0;
> + ring->wptr_old = 0;
> + vcn_v4_0_3_unified_ring_set_wptr(ring);
> + ring->sched.ready = true;
> }
> + } else {
> + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + vcn_inst = GET_INST(VCN, i);
> + ring = >vcn.inst[i].ring_enc[0];
> +
> + if (ring->use_doorbell) {
> + adev->nbio.funcs->vcn_doorbell_range(
> + adev, ring->use_doorbell,
> + (adev-
> >doorbell_index.vcn.vcn_ring0_1 << 1) +
> + 9 * vcn_inst,
> + adev->vcn.inst[i].aid_id);
> +
> + WREG32_SOC15(
> + VCN, GET_INST(VCN, ring->me),
> + regVCN_RB1_DB_CTRL,
> + ring->doorbell_index
> + <<
>
[PATCH 4/4] drm/amdgpu: use a macro to define no xcp partition case
~0 as no xcp partition is used in several places, so improve its
definition by a macro for code consistency.
Suggested-by: Christian König
Signed-off-by: Guchun Chen
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 2 ++
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 4 ++--
4 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index a7f314ddd173..d34c3ef8f3ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1709,7 +1709,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC)
?
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
}
- xcp_id = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id;
+ xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
+ 0 : fpriv->xcp_id;
} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
alloc_flags = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
index d175e862f222..9c9cca129498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
@@ -363,7 +363,7 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev,
if (!adev->xcp_mgr)
return 0;
- fpriv->xcp_id = ~0;
+ fpriv->xcp_id = AMDGPU_XCP_NO_PARTITION;
for (i = 0; i < MAX_XCP; ++i) {
if (!adev->xcp_mgr->xcp[i].ddev)
break;
@@ -381,7 +381,7 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev,
}
}
- fpriv->vm.mem_id = fpriv->xcp_id == ~0 ? -1 :
+ fpriv->vm.mem_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ? -1 :
adev->xcp_mgr->xcp[fpriv->xcp_id].mem_id;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
index 0f8026d64ea5..9a1036aeec2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
@@ -37,6 +37,8 @@
#define AMDGPU_XCP_FL_NONE 0
#define AMDGPU_XCP_FL_LOCKED (1 << 0)
+#define AMDGPU_XCP_NO_PARTITION (~0)
+
struct amdgpu_fpriv;
enum AMDGPU_XCP_IP_BLOCK {
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
index 16471b81a1f5..72b629a78c62 100644
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
@@ -68,7 +68,7 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device
*adev,
enum AMDGPU_XCP_IP_BLOCK ip_blk;
uint32_t inst_mask;
- ring->xcp_id = ~0;
+ ring->xcp_id = AMDGPU_XCP_NO_PARTITION;
if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE)
return;
@@ -177,7 +177,7 @@ static int aqua_vanjaram_select_scheds(
u32 sel_xcp_id;
int i;
- if (fpriv->xcp_id == ~0) {
+ if (fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION) {
u32 least_ref_cnt = ~0;
fpriv->xcp_id = 0;
--
2.25.1
[PATCH 3/4] drm/amdgpu/vm: use the same xcp_id from root PD
Other PDs/PTs allocation should just use the same xcp_id as that stored in root PD. Suggested-by: Christian König Signed-off-by: Guchun Chen Reviewed-by: Felix Kuehling Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index eb52dfe64948..83e1923f6775 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -607,7 +607,8 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev, return 0; amdgpu_vm_eviction_unlock(vm); - r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, , 0); + r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, , + vm->root.bo->xcp_id); amdgpu_vm_eviction_lock(vm); if (r) return r; -- 2.25.1
[PATCH 2/4] drm/amdgpu: fix slab-out-of-bounds issue in amdgpu_vm_pt_create
Recent code set xcp_id stored from file private data when opening
device to amdgpu bo for accounting memory usage etc, but not all
VMs are attached to this fpriv structure like the vm cases in
amdgpu_mes_self_test, otherwise, KASAN will complain below out
of bound access. And more importantly, VM code should not touch
fpriv structure, so drop fpriv code handling from amdgpu_vm_pt.
[ 77.292314] BUG: KASAN: slab-out-of-bounds in
amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu]
[ 77.293845] Read of size 4 at addr 888102c48a48 by task modprobe/1069
[ 77.294146] Call Trace:
[ 77.294178]
[ 77.294208] dump_stack_lvl+0x49/0x63
[ 77.294260] print_report+0x16f/0x4a6
[ 77.294307] ? amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu]
[ 77.295979] ? kasan_complete_mode_report_info+0x3c/0x200
[ 77.296057] ? amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu]
[ 77.297556] kasan_report+0xb4/0x130
[ 77.297609] ? amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu]
[ 77.299202] __asan_load4+0x6f/0x90
[ 77.299272] amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu]
[ 77.300796] ? amdgpu_init+0x6e/0x1000 [amdgpu]
[ 77.30] ? amdgpu_vm_pt_clear+0x750/0x750 [amdgpu]
[ 77.303721] ? preempt_count_sub+0x18/0xc0
[ 77.303786] amdgpu_vm_init+0x39e/0x870 [amdgpu]
[ 77.305186] ? amdgpu_vm_wait_idle+0x90/0x90 [amdgpu]
[ 77.306683] ? kasan_set_track+0x25/0x30
[ 77.306737] ? kasan_save_alloc_info+0x1b/0x30
[ 77.306795] ? __kasan_kmalloc+0x87/0xa0
[ 77.306852] amdgpu_mes_self_test+0x169/0x620 [amdgpu]
v2: without specifying xcp partition for PD/PT bo, the xcp id is -1.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2686
Fixes: ffc6deb773f7 ("drm/amdkfd: Store xcp partition id to amdgpu bo")
Signed-off-by: Guchun Chen
Tested-by: Mikhail Gavrilov
Reviewed-by: Felix Kuehling
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 11 ++-
5 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 53a024cf0544..cab2fdd5b76a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1236,7 +1236,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
if (r)
goto error_pasid;
- r = amdgpu_vm_init(adev, >vm);
+ r = amdgpu_vm_init(adev, >vm, fpriv->xcp_id);
if (r)
goto error_pasid;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index e9091ebfe230..f808841310fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -1382,7 +1382,7 @@ int amdgpu_mes_self_test(struct amdgpu_device *adev)
goto error_pasid;
}
- r = amdgpu_vm_init(adev, vm);
+ r = amdgpu_vm_init(adev, vm, -1);
if (r) {
DRM_ERROR("failed to initialize vm\n");
goto error_pasid;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 32adc31c093d..74380b21e7a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2121,13 +2121,14 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long
timeout)
*
* @adev: amdgpu_device pointer
* @vm: requested vm
+ * @xcp_id: GPU partition selection id
*
* Init @vm fields.
*
* Returns:
* 0 for success, error for failure.
*/
-int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t
xcp_id)
{
struct amdgpu_bo *root_bo;
struct amdgpu_bo_vm *root;
@@ -2177,7 +2178,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm)
vm->evicting = false;
r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
- false, );
+ false, , xcp_id);
if (r)
goto error_free_delayed;
root_bo = >bo;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 88ee4507f6b6..bca258c38919 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -398,7 +398,7 @@ int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
u32 pasid);
long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
-int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
+int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t
xcp_id);
int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
void
[PATCH 1/4] drm/amdgpu: Allocate root PD on correct partition
file_priv needs to be setup firstly, otherwise, root PD
will always be allocated on partition 0, even if opening
the device from other partitions.
Fixes: ffc6deb773f7 ("drm/amdkfd: Store xcp partition id to amdgpu bo")
Signed-off-by: Guchun Chen
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 85a0d5f419c8..53a024cf0544 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1232,13 +1232,13 @@ int amdgpu_driver_open_kms(struct drm_device *dev,
struct drm_file *file_priv)
pasid = 0;
}
- r = amdgpu_vm_init(adev, >vm);
+ r = amdgpu_xcp_open_device(adev, fpriv, file_priv);
if (r)
goto error_pasid;
- r = amdgpu_xcp_open_device(adev, fpriv, file_priv);
+ r = amdgpu_vm_init(adev, >vm);
if (r)
- goto error_vm;
+ goto error_pasid;
r = amdgpu_vm_set_pasid(adev, >vm, pasid);
if (r)
--
2.25.1
RE: [PATCH v2] drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4 to acquire gpu_metrics
[AMD Official Use Only - General]
Hi Wenyou,
I think you already got the greenlight(RB from Mario and ACK from me) to land
the change.
Go ahead please.
Evan
> -Original Message-
> From: Yang, WenYou
> Sent: Thursday, July 13, 2023 8:56 AM
> To: Yang, WenYou ; Deucher, Alexander
> ; Limonciello, Mario
> ; Koenig, Christian
> ; Pan, Xinhui ; Quan,
> Evan
> Cc: Yuan, Perry ; Liang, Richard qi
> ; amd-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; linux-ker...@vger.kernel.org
> Subject: RE: [PATCH v2] drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4
> to acquire gpu_metrics
>
> [AMD Official Use Only - General]
>
> Any comments? Any advice?
>
> Best Regards,
> Wenyou
>
> > -Original Message-
> > From: Wenyou Yang
> > Sent: Wednesday, June 21, 2023 2:32 PM
> > To: Deucher, Alexander ; Limonciello, Mario
> > ; Koenig, Christian
> > ; Pan, Xinhui ; Quan,
> > Evan
> > Cc: Yuan, Perry ; Liang, Richard qi
> > ; amd-gfx@lists.freedesktop.org; dri-
> > de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; Yang,
> > WenYou
> > Subject: [PATCH v2] drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4 to
> > acquire gpu_metrics
> >
> > To acquire the voltage and current info from gpu_metrics interface,
> > but
> > gpu_metrics_v2_3 doesn't contain them, and to be backward compatible,
> > add new gpu_metrics_v2_4 structure.
> >
> > Reviewed-by: Mario Limonciello
> > Acked-by: Evan Quan
> > Signed-off-by: Wenyou Yang
> > ---
> > .../gpu/drm/amd/include/kgd_pp_interface.h| 69 +++
> > .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 109
> -
> > -
> > drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 3 +
> > 3 files changed, 172 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > index 9f542f6e19ed..90989405eddc 100644
> > --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > @@ -892,4 +892,73 @@ struct gpu_metrics_v2_3 {
> > uint16_taverage_temperature_core[8]; //
> > average CPU core temperature on APUs
> > uint16_taverage_temperature_l3[2];
> > };
> > +
> > +struct gpu_metrics_v2_4 {
> > + struct metrics_table_header common_header;
> > +
> > + /* Temperature (unit: centi-Celsius) */
> > + uint16_ttemperature_gfx;
> > + uint16_ttemperature_soc;
> > + uint16_ttemperature_core[8];
> > + uint16_ttemperature_l3[2];
> > +
> > + /* Utilization (unit: centi) */
> > + uint16_taverage_gfx_activity;
> > + uint16_taverage_mm_activity;
> > +
> > + /* Driver attached timestamp (in ns) */
> > + uint64_tsystem_clock_counter;
> > +
> > + /* Power/Energy (unit: mW) */
> > + uint16_taverage_socket_power;
> > + uint16_taverage_cpu_power;
> > + uint16_taverage_soc_power;
> > + uint16_taverage_gfx_power;
> > + uint16_taverage_core_power[8];
> > +
> > + /* Average clocks (unit: MHz) */
> > + uint16_taverage_gfxclk_frequency;
> > + uint16_taverage_socclk_frequency;
> > + uint16_taverage_uclk_frequency;
> > + uint16_taverage_fclk_frequency;
> > + uint16_taverage_vclk_frequency;
> > + uint16_taverage_dclk_frequency;
> > +
> > + /* Current clocks (unit: MHz) */
> > + uint16_tcurrent_gfxclk;
> > + uint16_tcurrent_socclk;
> > + uint16_tcurrent_uclk;
> > + uint16_tcurrent_fclk;
> > + uint16_tcurrent_vclk;
> > + uint16_tcurrent_dclk;
> > + uint16_tcurrent_coreclk[8];
> > + uint16_tcurrent_l3clk[2];
> > +
> > + /* Throttle status (ASIC dependent) */
> > + uint32_tthrottle_status;
> > +
> > + /* Fans */
> > + uint16_tfan_pwm;
> > +
> > + uint16_tpadding[3];
> > +
> > + /* Throttle status (ASIC independent) */
> > + uint64_tindep_throttle_status;
> > +
> > + /* Average Temperature (unit: centi-Celsius) */
> > + uint16_taverage_temperature_gfx;
> > + uint16_taverage_temperature_soc;
> > + uint16_taverage_temperature_core[8];
> > + uint16_taverage_temperature_l3[2];
> > +
> > + /*
[PATCH] drm/amdgpu: Enabling FW workaround through shared memory for VCN4_0_2
This patch will enable VCN FW workaround using
DRM KEY INJECT WORKAROUND method,
which is helping in fixing the secure playback.
Signed-off-by: sguttula
---
Changes in v2:
-updated commit message as per veera's feedback
Changes in v3:
-updated commit message as enabling for 402
-updated the logic as per leo, feedback
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 9 +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 6 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 1f1d7dc94f90..a3eed90b6af0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -161,6 +161,7 @@
} while (0)
#define AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE (1 << 2)
+#define AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT (1 << 4)
#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB (1 << 6)
#define AMDGPU_VCN_MULTI_QUEUE_FLAG(1 << 8)
#define AMDGPU_VCN_SW_RING_FLAG(1 << 9)
@@ -180,6 +181,8 @@
#define AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU (0)
#define AMDGPU_VCN_SMU_DPM_INTERFACE_APU (1)
+#define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING 2
+
enum fw_queue_mode {
FW_QUEUE_RING_RESET = 1,
FW_QUEUE_DPG_HOLD_OFF = 2,
@@ -343,6 +346,11 @@ struct amdgpu_fw_shared_rb_setup {
uint32_t reserved[6];
};
+struct amdgpu_fw_shared_drm_key_wa {
+ uint8_t method;
+ uint8_t reserved[3];
+};
+
struct amdgpu_vcn4_fw_shared {
uint32_t present_flag_0;
uint8_t pad[12];
@@ -352,6 +360,7 @@ struct amdgpu_vcn4_fw_shared {
uint8_t pad2[20];
struct amdgpu_fw_shared_rb_setup rb_setup;
struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;
+ struct amdgpu_fw_shared_drm_key_wa drm_key_wa;
};
struct amdgpu_vcn_fwlog {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index e8c02ae10163..16ee73cfc3a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -169,6 +169,12 @@ static int vcn_v4_0_sw_init(void *handle)
fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags
& AMD_IS_APU) ?
AMDGPU_VCN_SMU_DPM_INTERFACE_APU :
AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
+ if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 2)) {
+ fw_shared->present_flag_0 |=
AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT;
+ fw_shared->drm_key_wa.method =
+
AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING;
+ }
+
if (amdgpu_sriov_vf(adev))
fw_shared->present_flag_0 |=
cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
--
2.25.1
RE: [PATCH 4/4] drm/amdgpu: use a macro to define no xcp partition case
[Public]
Thank you for review, Felix.
Hi Christian,
I forgot to add your RB in patch 2/patch3 when posting this series for review.
I will add it back when pushing. Hope it's fine to you.
Regards,
Guchun
> -Original Message-
> From: Kuehling, Felix
> Sent: Monday, July 17, 2023 10:58 PM
> To: Chen, Guchun ; amd-
> g...@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking
> ; Koenig, Christian
> ; Yang, Philip
> Subject: Re: [PATCH 4/4] drm/amdgpu: use a macro to define no xcp
> partition case
>
> On 2023-07-16 22:26, Guchun Chen wrote:
> > ~0 as no xcp partition is used in several places, so improve its
> > definition by a macro for code consistency.
> >
> > Suggested-by: Christian König
> > Signed-off-by: Guchun Chen
>
> The series is
>
> Reviewed-by: Felix Kuehling
>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 4 ++--
> > drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 2 ++
> > drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 4 ++--
> > 4 files changed, 8 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> > index a7f314ddd173..d34c3ef8f3ed 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> > @@ -1709,7 +1709,8 @@ int
> amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
> > alloc_flags |= (flags &
> KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
> > AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
> > }
> > - xcp_id = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id;
> > + xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
> > + 0 : fpriv->xcp_id;
> > } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
> > domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
> > alloc_flags = 0;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
> > index d175e862f222..9c9cca129498 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
> > @@ -363,7 +363,7 @@ int amdgpu_xcp_open_device(struct
> amdgpu_device *adev,
> > if (!adev->xcp_mgr)
> > return 0;
> >
> > - fpriv->xcp_id = ~0;
> > + fpriv->xcp_id = AMDGPU_XCP_NO_PARTITION;
> > for (i = 0; i < MAX_XCP; ++i) {
> > if (!adev->xcp_mgr->xcp[i].ddev)
> > break;
> > @@ -381,7 +381,7 @@ int amdgpu_xcp_open_device(struct
> amdgpu_device *adev,
> > }
> > }
> >
> > - fpriv->vm.mem_id = fpriv->xcp_id == ~0 ? -1 :
> > + fpriv->vm.mem_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
> -1 :
> > adev->xcp_mgr->xcp[fpriv->xcp_id].mem_id;
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
> > index 0f8026d64ea5..9a1036aeec2a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
> > @@ -37,6 +37,8 @@
> > #define AMDGPU_XCP_FL_NONE 0
> > #define AMDGPU_XCP_FL_LOCKED (1 << 0)
> >
> > +#define AMDGPU_XCP_NO_PARTITION (~0)
> > +
> > struct amdgpu_fpriv;
> >
> > enum AMDGPU_XCP_IP_BLOCK {
> > diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
> > b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
> > index 16471b81a1f5..72b629a78c62 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
> > @@ -68,7 +68,7 @@ static void aqua_vanjaram_set_xcp_id(struct
> amdgpu_device *adev,
> > enum AMDGPU_XCP_IP_BLOCK ip_blk;
> > uint32_t inst_mask;
> >
> > - ring->xcp_id = ~0;
> > + ring->xcp_id = AMDGPU_XCP_NO_PARTITION;
> > if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE)
> > return;
> >
> > @@ -177,7 +177,7 @@ static int aqua_vanjaram_select_scheds(
> > u32 sel_xcp_id;
> > int i;
> >
> > - if (fpriv->xcp_id == ~0) {
> > + if (fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION) {
> > u32 least_ref_cnt = ~0;
> >
> > fpriv->xcp_id = 0;
RE: [bug/bisected] commit a2848d08742c8e8494675892c02c0d22acbe3cf8 cause general protection fault, probably for non-canonical address 0xdffffc0000000000: 0000 [#1] PREEMPT SMP KASAN NOPTI
[Public] Hello Mike, I guess this patch can resolve your problem. https://patchwork.freedesktop.org/patch/547897/ Regards, Guchun > -Original Message- > From: amd-gfx On Behalf Of > Mikhail Gavrilov > Sent: Tuesday, July 18, 2023 3:34 AM > To: Koenig, Christian ; Pelloux-Prayer, Pierre- > Eric ; Deucher, Alexander > ; amd-gfx list g...@lists.freedesktop.org>; Linux List Kernel Mailing ker...@vger.kernel.org> > Subject: [bug/bisected] commit > a2848d08742c8e8494675892c02c0d22acbe3cf8 cause general protection > fault, probably for non-canonical address 0xdc00: [#1] > PREEMPT SMP KASAN NOPTI > > Hi, > at weekend I catched another problem. > I noted my computer starts hang after launching Steam and Google Chrome. > In the kernel log I saw such backtrace: > [ 90.002283] general protection fault, probably for non-canonical > address 0xdc00: [#1] PREEMPT SMP KASAN NOPTI > [ 90.002292] KASAN: null-ptr-deref in range > [0x-0x0007] > [ 90.002296] CPU: 12 PID: 3499 Comm: chrome:cs0 Tainted: GB W > L 6.4.0-rc7-07-a2848d08742c8e8494675892c02c0d22acbe3cf8+ #124 > [ 90.002299] Hardware name: ASUSTeK COMPUTER INC. ROG Strix > G513QY_G513QY/G513QY, BIOS G513QY.331 02/24/2023 > [ 90.002301] RIP: 0010:ttm_bo_evict_swapout_allowable+0x322/0x5e0 [ttm] > [ 90.002313] Code: b6 04 02 48 89 ea 83 e2 07 38 d0 7f 08 84 c0 0f > 85 e8 01 00 00 4c 89 e2 c6 45 00 00 48 b8 00 00 00 00 00 fc ff df 48 > c1 ea 03 <0f> b6 04 02 4c 89 e2 83 e2 07 38 d0 7f 08 84 c0 0f 85 ca 01 > 00 00 > [ 90.002316] RSP: 0018:c9000703ee08 EFLAGS: 00010256 > [ 90.002319] RAX: dc00 RBX: 888180ac1858 RCX: > c9000703ee90 > [ 90.002321] RDX: RSI: c9000703f228 RDI: > 888180ac1ab4 > [ 90.002323] RBP: c9000703ee90 R08: R09: > c9000703eed0 > [ 90.002324] R10: f52000e07db3 R11: b17dde80 R12: > > [ 90.002326] R13: c9000703f228 R14: c9000703eed0 R15: > 888180ac1858 > [ 90.002328] FS: 7f77461fe6c0() GS:888f9c80() > knlGS: > [ 90.002330] CS: 0010 DS: ES: CR0: 80050033 > [ 90.002332] CR2: 7f773549c000 CR3: 00024213e000 CR4: > 00750ee0 > [ 90.002334] PKRU: 5554 > [ 90.002335] Call Trace: > [ 90.002337] > [ 90.002339] ? die_addr+0x40/0xa0 > [ 90.002346] ? exc_general_protection+0x159/0x240 > [ 90.002352] ? asm_exc_general_protection+0x26/0x30 > [ 90.002357] ? ttm_bo_evict_swapout_allowable+0x322/0x5e0 [ttm] > [ 90.002365] ? ttm_bo_evict_swapout_allowable+0x42e/0x5e0 [ttm] > [ 90.002373] ttm_bo_swapout+0x134/0x7f0 [ttm] > [ 90.002383] ? __pfx_ttm_bo_swapout+0x10/0x10 [ttm] > [ 90.002391] ? lock_acquire+0x44d/0x4f0 > [ 90.002398] ? ttm_device_swapout+0xa5/0x260 [ttm] > [ 90.002412] ? lock_acquired+0x355/0xa00 > [ 90.002416] ? do_raw_spin_trylock+0xb6/0x190 > [ 90.002421] ? __pfx_lock_acquired+0x10/0x10 > [ 90.002426] ? ttm_global_swapout+0x25/0x210 [ttm] > [ 90.002442] ttm_device_swapout+0x198/0x260 [ttm] > [ 90.002456] ? __pfx_ttm_device_swapout+0x10/0x10 [ttm] > [ 90.002472] ttm_global_swapout+0x75/0x210 [ttm] > [ 90.002486] ttm_tt_populate+0x187/0x3f0 [ttm] > [ 90.002501] ttm_bo_handle_move_mem+0x437/0x590 [ttm] > [ 90.002517] ttm_bo_validate+0x275/0x430 [ttm] > [ 90.002530] ? __pfx_ttm_bo_validate+0x10/0x10 [ttm] > [ 90.002544] ? kasan_save_stack+0x33/0x60 > [ 90.002550] ? kasan_set_track+0x25/0x30 > [ 90.002554] ? __kasan_kmalloc+0x8f/0xa0 > [ 90.002558] ? amdgpu_gtt_mgr_new+0x81/0x420 [amdgpu] > [ 90.003023] ? ttm_resource_alloc+0xf6/0x220 [ttm] > [ 90.003038] amdgpu_bo_pin_restricted+0x2dd/0x8b0 [amdgpu] > [ 90.003210] ? __x64_sys_ioctl+0x131/0x1a0 > [ 90.003210] ? do_syscall_64+0x60/0x90 > [ 90.003210] ? __pfx_amdgpu_bo_pin_restricted+0x10/0x10 [amdgpu] > [ 90.003210] ? unmap_mapping_range+0xb6/0x250 > [ 90.003210] ? __pfx___might_resched+0x10/0x10 > [ 90.003210] ? lock_acquired+0x355/0xa00 > [ 90.003210] ? __down_read_trylock+0x1be/0x3a0 > [ 90.003210] dma_buf_map_attachment+0x1dd/0x560 > [ 90.003210] ? rcu_is_watching+0x15/0xb0 > [ 90.003210] amdgpu_bo_move+0x1227/0x1830 [amdgpu] > [ 90.003210] ? lock_release+0x4ec/0xba0 > [ 90.003210] ? ttm_bo_add_move_fence.isra.0+0x22/0x290 [ttm] > [ 90.003210] ? rcu_is_watching+0x15/0xb0 > [ 90.003210] ? __pfx_amdgpu_bo_move+0x10/0x10 [amdgpu] > [ 90.003210] ? dma_resv_reserve_fences+0xe8/0x7f0 > [ 90.003210] ? unmap_mapping_range+0xe3/0x250 > [ 90.003210] ? __pfx_dma_resv_reserve_fences+0x10/0x10 > [ 90.003210] ? _raw_spin_unlock+0x2d/0x50 > [ 90.003210] ? ttm_bo_add_move_fence.isra.0+0x12b/0x290 [ttm] > [ 90.003210] ttm_bo_handle_move_mem+0x244/0x590 [ttm] > [ 90.003210] ttm_bo_validate+0x275/0x430 [ttm] > [ 90.003210] ? __pfx_ttm_bo_validate+0x10/0x10 [ttm] > [ 90.003210]
[PATCH] drm/ttm: check null pointer before accessing when swapping
Add a check to avoid null pointer dereference.
Fixes: a2848d08742c ("drm/ttm: never consider pinned BOs for eviction")
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/ttm/ttm_bo.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 7139a522b2f3..54e3083076b7 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -519,7 +519,8 @@ static bool ttm_bo_evict_swapout_allowable(struct
ttm_buffer_object *bo,
if (bo->pin_count) {
*locked = false;
- *busy = false;
+ if (busy)
+ *busy = false;
return false;
}
--
2.25.1
Re: [PATCH] drm/amd/display: remove an unused file
On 7/17/23 17:01, Aurabindo Pillai wrote:
[Why]
Internal subvp state is not referenced in driver code, so it can be removed.
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 2 -
.../amd/display/dmub/inc/dmub_subvp_state.h | 183 --
2 files changed, 185 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_subvp_state.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index d52d5feeb311..a87afb796f47 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -47,11 +47,9 @@
#include "clk_mgr.h"
#include "dsc.h"
#include "dcn20/dcn20_optc.h"
-#include "dmub_subvp_state.h"
#include "dce/dmub_hw_lock_mgr.h"
#include "dcn32_resource.h"
#include "link.h"
-#include "dmub/inc/dmub_subvp_state.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_subvp_state.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_subvp_state.h
deleted file mode 100644
index 21b02bad696f..
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_subvp_state.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef DMUB_SUBVP_STATE_H
-#define DMUB_SUBVP_STATE_H
-
-#include "dmub_cmd.h"
-
-#define DMUB_SUBVP_INST0 0
-#define DMUB_SUBVP_INST1 1
-#define SUBVP_MAX_WATERMARK 0x
-
-struct dmub_subvp_hubp_state {
- uint32_t CURSOR0_0_CURSOR_POSITION;
- uint32_t CURSOR0_0_CURSOR_HOT_SPOT;
- uint32_t CURSOR0_0_CURSOR_DST_OFFSET;
- uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH;
- uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS;
- uint32_t CURSOR0_0_CURSOR_SIZE;
- uint32_t CURSOR0_0_CURSOR_CONTROL;
- uint32_t HUBPREQ0_CURSOR_SETTINGS;
- uint32_t HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH;
- uint32_t HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
-};
-
-enum subvp_error_code {
- DMUB_SUBVP_INVALID_STATE,
- DMUB_SUBVP_INVALID_TRANSITION,
-};
-
-enum subvp_state {
- DMUB_SUBVP_DISABLED,
- DMUB_SUBVP_IDLE,
- DMUB_SUBVP_TRY_ACQUIRE_LOCKS,
- DMUB_SUBVP_WAIT_FOR_LOCKS,
- DMUB_SUBVP_PRECONFIGURE,
- DMUB_SUBVP_PREPARE,
- DMUB_SUBVP_ENABLE,
- DMUB_SUBVP_SWITCHING,
- DMUB_SUBVP_END,
- DMUB_SUBVP_RESTORE,
-};
-
-/* Defines information for SUBVP to handle vertical interrupts. */
-struct dmub_subvp_vertical_interrupt_event {
- /**
-* @inst: Hardware instance of vertical interrupt.
-*/
- uint8_t otg_inst;
-
- /**
-* @pad: Align structure to 4 byte boundary.
-*/
- uint8_t pad[3];
-
- enum subvp_state curr_state;
-};
-
-struct dmub_subvp_vertical_interrupt_state {
- /**
-* @events: Event list.
-*/
- struct dmub_subvp_vertical_interrupt_event events[DMUB_MAX_STREAMS];
-};
-
-struct dmub_subvp_vline_interrupt_event {
-
- uint8_t hubp_inst;
- uint8_t pad[3];
-};
-
-struct dmub_subvp_vline_interrupt_state {
- struct dmub_subvp_vline_interrupt_event events[DMUB_MAX_PLANES];
-};
-
-struct dmub_subvp_interrupt_ctx {
- struct dmub_subvp_vertical_interrupt_state vertical_int;
- struct
[PATCH] drm/amd/display: remove an unused file
[Why]
Internal subvp state is not referenced in driver code, so it can be removed.
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 2 -
.../amd/display/dmub/inc/dmub_subvp_state.h | 183 --
2 files changed, 185 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_subvp_state.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index d52d5feeb311..a87afb796f47 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -47,11 +47,9 @@
#include "clk_mgr.h"
#include "dsc.h"
#include "dcn20/dcn20_optc.h"
-#include "dmub_subvp_state.h"
#include "dce/dmub_hw_lock_mgr.h"
#include "dcn32_resource.h"
#include "link.h"
-#include "dmub/inc/dmub_subvp_state.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_subvp_state.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_subvp_state.h
deleted file mode 100644
index 21b02bad696f..
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_subvp_state.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef DMUB_SUBVP_STATE_H
-#define DMUB_SUBVP_STATE_H
-
-#include "dmub_cmd.h"
-
-#define DMUB_SUBVP_INST0 0
-#define DMUB_SUBVP_INST1 1
-#define SUBVP_MAX_WATERMARK 0x
-
-struct dmub_subvp_hubp_state {
- uint32_t CURSOR0_0_CURSOR_POSITION;
- uint32_t CURSOR0_0_CURSOR_HOT_SPOT;
- uint32_t CURSOR0_0_CURSOR_DST_OFFSET;
- uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH;
- uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS;
- uint32_t CURSOR0_0_CURSOR_SIZE;
- uint32_t CURSOR0_0_CURSOR_CONTROL;
- uint32_t HUBPREQ0_CURSOR_SETTINGS;
- uint32_t HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH;
- uint32_t HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
- uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
-};
-
-enum subvp_error_code {
- DMUB_SUBVP_INVALID_STATE,
- DMUB_SUBVP_INVALID_TRANSITION,
-};
-
-enum subvp_state {
- DMUB_SUBVP_DISABLED,
- DMUB_SUBVP_IDLE,
- DMUB_SUBVP_TRY_ACQUIRE_LOCKS,
- DMUB_SUBVP_WAIT_FOR_LOCKS,
- DMUB_SUBVP_PRECONFIGURE,
- DMUB_SUBVP_PREPARE,
- DMUB_SUBVP_ENABLE,
- DMUB_SUBVP_SWITCHING,
- DMUB_SUBVP_END,
- DMUB_SUBVP_RESTORE,
-};
-
-/* Defines information for SUBVP to handle vertical interrupts. */
-struct dmub_subvp_vertical_interrupt_event {
- /**
-* @inst: Hardware instance of vertical interrupt.
-*/
- uint8_t otg_inst;
-
- /**
-* @pad: Align structure to 4 byte boundary.
-*/
- uint8_t pad[3];
-
- enum subvp_state curr_state;
-};
-
-struct dmub_subvp_vertical_interrupt_state {
- /**
-* @events: Event list.
-*/
- struct dmub_subvp_vertical_interrupt_event events[DMUB_MAX_STREAMS];
-};
-
-struct dmub_subvp_vline_interrupt_event {
-
- uint8_t hubp_inst;
- uint8_t pad[3];
-};
-
-struct dmub_subvp_vline_interrupt_state {
- struct dmub_subvp_vline_interrupt_event events[DMUB_MAX_PLANES];
-};
-
-struct dmub_subvp_interrupt_ctx {
- struct dmub_subvp_vertical_interrupt_state vertical_int;
- struct dmub_subvp_vline_interrupt_state vline_int;
-};
-
-struct dmub_subvp_pipe_state {
-
[PATCH] drm/amdgpu: allow secure submission on VCN4 ring
This patch will enable secure decode playback on VCN4_0_2
Signed-off-by: sguttula
---
Changes in v2:
-updated commit message only enabling for VCN402
-updated the logic as per Leo's feedback
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index e8c02ae10163..d2d89bb711b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1801,7 +1801,7 @@ static int vcn_v4_0_ring_patch_cs_in_place(struct
amdgpu_cs_parser *p,
return 0;
}
-static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
+static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
.type = AMDGPU_RING_TYPE_VCN_ENC,
.align_mask = 0x3f,
.nop = VCN_ENC_CMD_NO_OP,
@@ -1846,7 +1846,11 @@ static void vcn_v4_0_set_unified_ring_funcs(struct
amdgpu_device *adev)
if (adev->vcn.harvest_config & (1 << i))
continue;
- adev->vcn.inst[i].ring_enc[0].funcs =
_v4_0_unified_ring_vm_funcs;
+ if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 2))
+
vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true;
+
+ adev->vcn.inst[i].ring_enc[0].funcs =
+ (const struct amdgpu_ring_funcs
*)_v4_0_unified_ring_vm_funcs;
adev->vcn.inst[i].ring_enc[0].me = i;
DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
--
2.25.1
Re: [PATCH 4/5] selinux: use vma_is_stack() and vma_is_heap()
On Wed, Jul 12, 2023 at 10:25 AM Kefeng Wang wrote:
>
> Use the helpers to simplify code.
>
> Signed-off-by: Kefeng Wang
> ---
> security/selinux/hooks.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c
> index 4e46cf3d67b6..289ef2d6a427 100644
> --- a/security/selinux/hooks.c
> +++ b/security/selinux/hooks.c
> @@ -3775,13 +3775,10 @@ static int selinux_file_mprotect(struct
> vm_area_struct *vma,
> if (default_noexec &&
> (prot & PROT_EXEC) && !(vma->vm_flags & VM_EXEC)) {
> int rc = 0;
> - if (vma->vm_start >= vma->vm_mm->start_brk &&
> - vma->vm_end <= vma->vm_mm->brk) {
> + if (vma_is_heap(vma)) {
> rc = avc_has_perm(sid, sid, SECCLASS_PROCESS,
> PROCESS__EXECHEAP, NULL);
> - } else if (!vma->vm_file &&
> - ((vma->vm_start <= vma->vm_mm->start_stack &&
> -vma->vm_end >= vma->vm_mm->start_stack) ||
> + } else if (!vma->vm_file && vma_is_stack(vma) ||
> vma_is_stack_for_current(vma))) {
With the parens fix that Andrew already provided.
Acked-by: Paul Moore
> rc = avc_has_perm(sid, sid, SECCLASS_PROCESS,
> PROCESS__EXECSTACK, NULL);
> --
> 2.41.0
--
paul-moore.com
[PATCH 7/7] drm/amdgpu/vcn: change end doorbell index for vcn_v4_0_3
For sriov, doorbell index for vcn0 for AID needs to be on
32 byte boundary so we need to move the vcn end doorbell
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index f637574644c0..4a279960cd21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -330,14 +330,14 @@ typedef enum _AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 {
AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 0x19F,
/* IH: 0x1A0 ~ 0x1AF */
AMDGPU_DOORBELL_LAYOUT1_IH = 0x1A0,
- /* VCN: 0x1B0 ~ 0x1D4 */
+ /* VCN: 0x1B0 ~ 0x1E8 */
AMDGPU_DOORBELL_LAYOUT1_VCN_START = 0x1B0,
- AMDGPU_DOORBELL_LAYOUT1_VCN_END = 0x1D4,
+ AMDGPU_DOORBELL_LAYOUT1_VCN_END = 0x1E8,
AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP=
AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START,
AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP =
AMDGPU_DOORBELL_LAYOUT1_VCN_END,
- AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 0x1D4,
+ AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 0x1E8,
AMDGPU_DOORBELL_LAYOUT1_INVALID = 0x
} AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1;
--
2.34.1
[PATCH 5/7] drm/amdgpu/jpeg: sriov support for jpeg_v4_0_3
initialization table handshake with mmsch
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 171 ---
1 file changed, 150 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index ce2b22f7e4e4..85ee74fdb7e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -26,6 +26,7 @@
#include "soc15.h"
#include "soc15d.h"
#include "jpeg_v4_0_3.h"
+#include "mmsch_v4_0_3.h"
#include "vcn/vcn_4_0_3_offset.h"
#include "vcn/vcn_4_0_3_sh_mask.h"
@@ -41,6 +42,7 @@ static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device
*adev);
static int jpeg_v4_0_3_set_powergating_state(void *handle,
enum amd_powergating_state state);
static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
+static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
static int amdgpu_ih_srcid_jpeg[] = {
VCN_4_0__SRCID__JPEG_DECODE,
@@ -160,6 +162,117 @@ static int jpeg_v4_0_3_sw_fini(void *handle)
return r;
}
+static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev)
+{
+ struct amdgpu_ring *ring;
+ uint64_t ctx_addr;
+ uint32_t param, resp, expected;
+ uint32_t tmp, timeout;
+
+ struct amdgpu_mm_table *table = >virt.mm_table;
+ uint32_t *table_loc;
+ uint32_t table_size;
+ uint32_t size, size_dw, item_offset;
+ uint32_t init_status;
+ int i, j;
+
+ struct mmsch_v4_0_cmd_direct_write
+ direct_wt = { {0} };
+ struct mmsch_v4_0_cmd_end end = { {0} };
+ struct mmsch_v4_0_3_init_header header;
+
+ direct_wt.cmd_header.command_type =
+ MMSCH_COMMAND__DIRECT_REG_WRITE;
+ end.cmd_header.command_type =
+ MMSCH_COMMAND__END;
+
+ for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
+ memset(, 0, sizeof(struct mmsch_v4_0_3_init_header));
+ header.version = MMSCH_VERSION;
+ header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >>
2;
+
+ table_loc = (uint32_t *)table->cpu_addr;
+ table_loc += header.total_size;
+
+ item_offset = header.total_size;
+
+ for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) {
+ ring = >jpeg.inst[i].ring_dec[j];
+ table_size = 0;
+
+ tmp = SOC15_REG_OFFSET(JPEG, 0,
regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW);
+ MMSCH_V4_0_INSERT_DIRECT_WT(tmp,
lower_32_bits(ring->gpu_addr));
+ tmp = SOC15_REG_OFFSET(JPEG, 0,
regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH);
+ MMSCH_V4_0_INSERT_DIRECT_WT(tmp,
upper_32_bits(ring->gpu_addr));
+ tmp = SOC15_REG_OFFSET(JPEG, 0,
regUVD_JRBC0_UVD_JRBC_RB_SIZE);
+ MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4);
+
+ if (j <= 3) {
+ header.mjpegdec0[j].table_offset = item_offset;
+ header.mjpegdec0[j].init_status = 0;
+ header.mjpegdec0[j].table_size = table_size;
+ } else {
+ header.mjpegdec1[j-4].table_offset =
item_offset;
+ header.mjpegdec1[j-4].init_status = 0;
+ header.mjpegdec1[j-4].table_size = table_size;
+ }
+ header.total_size += table_size;
+ item_offset+= table_size;
+ }
+
+ MMSCH_V4_0_INSERT_END();
+
+ /* send init table to MMSCH */
+ size = sizeof(struct mmsch_v4_0_3_init_header);
+ table_loc = (uint32_t *)table->cpu_addr;
+ memcpy((void *)table_loc, , size);
+
+ ctx_addr = table->gpu_addr;
+ WREG32_SOC15(VCN, i, regMMSCH_VF_CTX_ADDR_LO,
lower_32_bits(ctx_addr));
+ WREG32_SOC15(VCN, i, regMMSCH_VF_CTX_ADDR_HI,
upper_32_bits(ctx_addr));
+
+ tmp = RREG32_SOC15(VCN, i, regMMSCH_VF_VMID);
+ tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
+ tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
+ WREG32_SOC15(VCN, i, regMMSCH_VF_VMID, tmp);
+
+ size = header.total_size;
+ WREG32_SOC15(VCN, i, regMMSCH_VF_CTX_SIZE, size);
+
+ WREG32_SOC15(VCN, i, regMMSCH_VF_MAILBOX_RESP, 0);
+
+ param = 0x0001;
+ WREG32_SOC15(VCN, i, regMMSCH_VF_MAILBOX_HOST, param);
+ tmp = 0;
+ timeout = 1000;
+ resp = 0;
+ expected = MMSCH_VF_MAILBOX_RESP__OK;
+ init_status = ((struct mmsch_v4_0_3_init_header
*)(table_loc))->mjpegdec0[i].init_status;
+
[PATCH 6/7] drm/amdgpu/jpeg: mmsch_v3_0_4 requires doorbell on 32 byte boundary
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 85ee74fdb7e3..896e2f895884 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -111,9 +111,20 @@ static int jpeg_v4_0_3_sw_init(void *handle)
ring = >jpeg.inst[i].ring_dec[j];
ring->use_doorbell = true;
ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id);
- ring->doorbell_index =
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 1 + j + 9 * jpeg_inst;
+ if (!amdgpu_sriov_vf(adev)) {
+ ring->doorbell_index =
+ (adev->doorbell_index.vcn.vcn_ring0_1
<< 1) +
+ 1 + j + 9 * jpeg_inst;
+ } else {
+ if (j < 4)
+ ring->doorbell_index =
+
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 4 + j + 32 * jpeg_inst;
+ else
+ ring->doorbell_index =
+
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 8 + j + 32 * jpeg_inst;
+ }
sprintf(ring->name, "jpeg_dec_%d.%d",
adev->jpeg.inst[i].aid_id, j);
r = amdgpu_ring_init(adev, ring, 512,
>jpeg.inst->irq, 0,
AMDGPU_RING_PRIO_DEFAULT, NULL);
--
2.34.1
[PATCH 4/7] drm/amdgpu/vcn: mmsch_v3_0_4 requires doorbell on 32 byte boundary
Signed-off-by: Samir Dhume --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index ac405dfcfaf1..fa9abcb08c22 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -113,9 +113,16 @@ static int vcn_v4_0_3_sw_init(void *handle) ring = >vcn.inst[i].ring_enc[0]; ring->use_doorbell = true; - ring->doorbell_index = - (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + - 9 * vcn_inst; + + if (!amdgpu_sriov_vf(adev)) + ring->doorbell_index = + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 9 * vcn_inst; + else + ring->doorbell_index = + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 32 * vcn_inst; + ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); r = amdgpu_ring_init(adev, ring, 512, >vcn.inst->irq, 0, -- 2.34.1
[PATCH 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
initialization table handshake with mmsch
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 264 +---
1 file changed, 240 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 411c1d802823..ac405dfcfaf1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -31,6 +31,7 @@
#include "soc15d.h"
#include "soc15_hw_ip.h"
#include "vcn_v2_0.h"
+#include "mmsch_v4_0_3.h"
#include "vcn/vcn_4_0_3_offset.h"
#include "vcn/vcn_4_0_3_sh_mask.h"
@@ -44,6 +45,7 @@
#define VCN_VID_SOC_ADDRESS_2_00x1fb00
#define VCN1_VID_SOC_ADDRESS_3_0 0x48300
+static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v4_0_3_set_powergating_state(void *handle,
@@ -130,6 +132,12 @@ static int vcn_v4_0_3_sw_init(void *handle)
amdgpu_vcn_fwlog_init(>vcn.inst[i]);
}
+ if (amdgpu_sriov_vf(adev)) {
+ r = amdgpu_virt_alloc_mm_table(adev);
+ if (r)
+ return r;
+ }
+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
@@ -167,6 +175,9 @@ static int vcn_v4_0_3_sw_fini(void *handle)
drm_dev_exit(idx);
}
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_free_mm_table(adev);
+
r = amdgpu_vcn_suspend(adev);
if (r)
return r;
@@ -189,33 +200,50 @@ static int vcn_v4_0_3_hw_init(void *handle)
struct amdgpu_ring *ring;
int i, r, vcn_inst;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- vcn_inst = GET_INST(VCN, i);
- ring = >vcn.inst[i].ring_enc[0];
+ if (amdgpu_sriov_vf(adev)) {
+ r = vcn_v4_0_3_start_sriov(adev);
+ if (r)
+ goto done;
- if (ring->use_doorbell) {
- adev->nbio.funcs->vcn_doorbell_range(
- adev, ring->use_doorbell,
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 9 * vcn_inst,
- adev->vcn.inst[i].aid_id);
-
- WREG32_SOC15(
- VCN, GET_INST(VCN, ring->me),
- regVCN_RB1_DB_CTRL,
- ring->doorbell_index
- <<
VCN_RB1_DB_CTRL__OFFSET__SHIFT |
- VCN_RB1_DB_CTRL__EN_MASK);
-
- /* Read DB_CTRL to flush the write DB_CTRL command. */
- RREG32_SOC15(
- VCN, GET_INST(VCN, ring->me),
- regVCN_RB1_DB_CTRL);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+
+ ring = >vcn.inst[i].ring_enc[0];
+ ring->wptr = 0;
+ ring->wptr_old = 0;
+ vcn_v4_0_3_unified_ring_set_wptr(ring);
+ ring->sched.ready = true;
}
+ } else {
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ vcn_inst = GET_INST(VCN, i);
+ ring = >vcn.inst[i].ring_enc[0];
+
+ if (ring->use_doorbell) {
+ adev->nbio.funcs->vcn_doorbell_range(
+ adev, ring->use_doorbell,
+ (adev->doorbell_index.vcn.vcn_ring0_1
<< 1) +
+ 9 * vcn_inst,
+ adev->vcn.inst[i].aid_id);
+
+ WREG32_SOC15(
+ VCN, GET_INST(VCN, ring->me),
+ regVCN_RB1_DB_CTRL,
+ ring->doorbell_index
+ <<
VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
+
+ /* Read DB_CTRL to flush the write DB_CTRL
command. */
+ RREG32_SOC15(
+ VCN, GET_INST(VCN, ring->me),
+ regVCN_RB1_DB_CTRL);
+ }
- r = amdgpu_ring_test_helper(ring);
- if (r)
- goto done;
+ r = amdgpu_ring_test_helper(ring);
+
[PATCH 1/7] drm/amdgpu/vcn: Add MMSCH v4_0_3 support for sriov
The structures are the same as v4_0 except for the
init header
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h | 37 +++
1 file changed, 37 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
b/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
new file mode 100644
index ..db7eb5260295
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0_3.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __MMSCH_V4_0_3_H__
+#define __MMSCH_V4_0_3_H__
+
+#include "amdgpu_vcn.h"
+#include "mmsch_v4_0.h"
+
+struct mmsch_v4_0_3_init_header {
+ uint32_t version;
+ uint32_t total_size;
+ struct mmsch_v4_0_table_info vcn0;
+ struct mmsch_v4_0_table_info mjpegdec0[4];
+ struct mmsch_v4_0_table_info mjpegdec1[4];
+};
+#endif
--
2.34.1
[PATCH 2/7] drm/amdgpu/vcn : Skip vcn power-gating change for sriov
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 550ac040b4be..411c1d802823 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1317,6 +1317,15 @@ static int vcn_v4_0_3_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
+ /* for SRIOV, guest should not control VCN Power-gating
+* MMSCH FW should control Power-gating and clock-gating
+* guest should avoid touching CGC and PG
+*/
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
+
if (state == adev->vcn.cur_state)
return 0;
--
2.34.1
Re: radeon.ko/i586: BUG: kernel NULL pointer dereference, address:00000004
On Fri, 14 Jul 2023 14:34:04 +0900 wrote: > Patch in > https://bugzilla.kernel.org/show_bug.cgi?id=217669#c4 > fixed the problem in freedesktop.org kernel 5.18.0-rc2 . > This may explain that in kernel.org tree, the said commit is in kernel-5.19. You mean the patch that adds: #if defined(FTRACE_MCOUNT_MAX_OFFSET) && (FTRACE_MCOUNT_MAX_OFFSET) ? Nothing should be setting FTRACE_MCOUNT_MAX_OFFSET to anything but non zero. But doing a grep, I now see: # define FTRACE_MCOUNT_MAX_OFFSET ENDBR_INSN_SIZE Where it breaks that assumption if ENDBR_INSN_SIZE == 0 :-p (and that's my code!) OK, does this fix it? (I haven't tested nor compiled this) -- Steve diff --git a/arch/x86/include/asm/ftrace.h b/arch/x86/include/asm/ftrace.h index 897cf02c20b1..801f4414da3e 100644 --- a/arch/x86/include/asm/ftrace.h +++ b/arch/x86/include/asm/ftrace.h @@ -13,7 +13,7 @@ #ifdef CONFIG_HAVE_FENTRY # include /* Add offset for endbr64 if IBT enabled */ -# define FTRACE_MCOUNT_MAX_OFFSET ENDBR_INSN_SIZE +# define FTRACE_MCOUNT_MAX_OFFSET (ENDBR_INSN_SIZE + MCOUNT_INSN_SIZE) #endif #ifdef CONFIG_DYNAMIC_FTRACE
Re: radeon.ko/i586: BUG: kernel NULL pointer dereference,address:00000004
On Sat, 15 Jul 2023 11:39:11 +0900
wrote:
> Yes, this is puzzling. That's why I need other people's opinion on this.
> Does it matter the DUT is a slow machine (Pentium 120MHz)?
>
Hmm, I wonder because the workqueue is running __init functions, could it
possibly be that it didn't finish before the end of boot, where it frees
all the functions? It shouldn't do that because there's code to make sure
it's done before it continues further.
But just in case something isn't working as planned, you could try this
patch to see if the bug goes away.
-- Steve
diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
index 05c0024815bf..af5a40ef3be4 100644
--- a/kernel/trace/ftrace.c
+++ b/kernel/trace/ftrace.c
@@ -3771,13 +3771,13 @@ static int test_for_valid_rec(struct dyn_ftrace *rec)
return 1;
}
-static struct workqueue_struct *ftrace_check_wq __initdata;
-static struct work_struct ftrace_check_work __initdata;
+static struct workqueue_struct *ftrace_check_wq;
+static struct work_struct ftrace_check_work;
/*
* Scan all the mcount/fentry entries to make sure they are valid.
*/
-static __init void ftrace_check_work_func(struct work_struct *work)
+static void ftrace_check_work_func(struct work_struct *work)
{
struct ftrace_page *pg;
struct dyn_ftrace *rec;
Re: [PATCH v2] drm: Spelling s/sempahore/semaphore/
On Mon, Jul 17, 2023 at 03:23:20PM +0200, Geert Uytterhoeven wrote: > Fix misspellings of "semaphore". > > Signed-off-by: Geert Uytterhoeven > Reviewed-by: Hamza Mahfooz > --- > v2: > - Add Reviewed-by. > --- > drivers/gpu/drm/i915/i915_request.c | 2 +- > drivers/gpu/drm/radeon/cik.c| 2 +- > drivers/gpu/drm/radeon/r600.c | 2 +- > include/drm/task_barrier.h | 2 +- > 4 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_request.c > b/drivers/gpu/drm/i915/i915_request.c > index 894068bb37b6f1b6..32323bb801a139b7 100644 > --- a/drivers/gpu/drm/i915/i915_request.c > +++ b/drivers/gpu/drm/i915/i915_request.c > @@ -1220,7 +1220,7 @@ emit_semaphore_wait(struct i915_request *to, > /* >* If this or its dependents are waiting on an external fence >* that may fail catastrophically, then we want to avoid using > - * sempahores as they bypass the fence signaling metadata, and we > + * semaphores as they bypass the fence signaling metadata, and we >* lose the fence->error propagation. >*/ > if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN) Acked-by: Rodrigo Vivi to take this through drm-misc > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index 5819737c21c678d3..5d6b81a6578ef2ba 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -3603,7 +3603,7 @@ void cik_fence_compute_ring_emit(struct radeon_device > *rdev, > * @rdev: radeon_device pointer > * @ring: radeon ring buffer object > * @semaphore: radeon semaphore object > - * @emit_wait: Is this a sempahore wait? > + * @emit_wait: Is this a semaphore wait? > * > * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP > * from running ahead of semaphore waits. > diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c > index 382795a8b3c064ba..a17b95eec65fb810 100644 > --- a/drivers/gpu/drm/radeon/r600.c > +++ b/drivers/gpu/drm/radeon/r600.c > @@ -2918,7 +2918,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev, > * @rdev: radeon_device pointer > * @ring: radeon ring buffer object > * @semaphore: radeon semaphore object > - * @emit_wait: Is this a sempahore wait? > + * @emit_wait: Is this a semaphore wait? > * > * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP > * from running ahead of semaphore waits. > diff --git a/include/drm/task_barrier.h b/include/drm/task_barrier.h > index 087e3f649c52f02d..217c1cf21c1ab7d5 100644 > --- a/include/drm/task_barrier.h > +++ b/include/drm/task_barrier.h > @@ -25,7 +25,7 @@ > > /* > * Reusable 2 PHASE task barrier (randevouz point) implementation for N > tasks. > - * Based on the Little book of sempahores - > https://greenteapress.com/wp/semaphores/ > + * Based on the Little book of semaphores - > https://greenteapress.com/wp/semaphores/ > */ > > > -- > 2.34.1 >
Re: [PATCH 4/4] drm/amdgpu: use a macro to define no xcp partition case
On 2023-07-16 22:26, Guchun Chen wrote:
~0 as no xcp partition is used in several places, so improve its
definition by a macro for code consistency.
Suggested-by: Christian König
Signed-off-by: Guchun Chen
The series is
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 2 ++
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 4 ++--
4 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index a7f314ddd173..d34c3ef8f3ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1709,7 +1709,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC)
?
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
}
- xcp_id = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id;
+ xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
+ 0 : fpriv->xcp_id;
} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
alloc_flags = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
index d175e862f222..9c9cca129498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
@@ -363,7 +363,7 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev,
if (!adev->xcp_mgr)
return 0;
- fpriv->xcp_id = ~0;
+ fpriv->xcp_id = AMDGPU_XCP_NO_PARTITION;
for (i = 0; i < MAX_XCP; ++i) {
if (!adev->xcp_mgr->xcp[i].ddev)
break;
@@ -381,7 +381,7 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev,
}
}
- fpriv->vm.mem_id = fpriv->xcp_id == ~0 ? -1 :
+ fpriv->vm.mem_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ? -1 :
adev->xcp_mgr->xcp[fpriv->xcp_id].mem_id;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
index 0f8026d64ea5..9a1036aeec2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
@@ -37,6 +37,8 @@
#define AMDGPU_XCP_FL_NONE 0
#define AMDGPU_XCP_FL_LOCKED (1 << 0)
+#define AMDGPU_XCP_NO_PARTITION (~0)
+
struct amdgpu_fpriv;
enum AMDGPU_XCP_IP_BLOCK {
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
index 16471b81a1f5..72b629a78c62 100644
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
@@ -68,7 +68,7 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device
*adev,
enum AMDGPU_XCP_IP_BLOCK ip_blk;
uint32_t inst_mask;
- ring->xcp_id = ~0;
+ ring->xcp_id = AMDGPU_XCP_NO_PARTITION;
if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE)
return;
@@ -177,7 +177,7 @@ static int aqua_vanjaram_select_scheds(
u32 sel_xcp_id;
int i;
- if (fpriv->xcp_id == ~0) {
+ if (fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION) {
u32 least_ref_cnt = ~0;
fpriv->xcp_id = 0;
Re: [PATCH v3 4/9] PCI/VGA: Improve the default VGA device selection
Hi,
Fixes: f6b1772b2555 ('vgaarb: remove the unused irq_set_state argument
to vga_client_register')
Because after applied that patch, there have only one callback mechanism
we can use, not two anymore.
On 2023/7/12 00:43, Sui Jingfeng wrote:
From: Sui Jingfeng
Currently, the strategy of selecting the default boot on a multiple video
card coexistence system is not perfect. Potential problems are:
1) This function is a no-op on non-x86 architectures.
2) It does not take the PCI Bar may get relocated into consideration.
3) It is not effective for the PCI device without a dedicated VRAM Bar.
4) It is device-agnostic, thus it has to waste the effort to iterate all
of the PCI Bar to find the VRAM aperture.
5) It has invented lots of methods to determine which one is the default
boot device, but this is still a policy because it doesn't give the
user a choice to override.
With the observation that device drivers may have better knowledge about
which PCI bar contains the firmware FB. This patch tries to solve the above
problems by introducing a function callback to the vga_client_register()
function interface. DRM device drivers for the PCI device could provide
a xx_vga_is_primary_gpu() function callback during the driver loading time.
Once the driver binds the device successfully, VRAARB will call back to
the driver. This gives the device drivers a chance to provide accurate
boot device identification. Which in turn unlock the abitration service
to non-x86 architectures. A device driver can also just pass a NULL pointer
to keep the original behavior.
This patch is intended to introducing the mechanism only, the specific
implementation is left to the authors of various device driver. Also honor
the comment: "Clients have *TWO* callback mechanisms they can use"
Cc: Alex Deucher
Cc: Christian Konig
Cc: Pan Xinhui
Cc: David Airlie
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Ben Skeggs
Cc: Karol Herbst
Cc: Lyude Paul
Cc: Bjorn Helgaas
Cc: Alex Williamson
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: Hawking Zhang
Cc: Mario Limonciello
Cc: Lijo Lazar
Cc: YiPeng Chai
Cc: Bokun Zhang
Cc: Likun Gao
Cc: Ville Syrjala
Cc: Jason Gunthorpe
CC: Kevin Tian
Cc: Cornelia Huck
Cc: Yishai Hadas
Cc: Abhishek Sahu
Cc: Yi Liu
Acked-by: Jani Nikula # i915
Reviewed-by: Lyude Paul # nouveau
Signed-off-by: Sui Jingfeng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/i915/display/intel_vga.c | 3 +-
drivers/gpu/drm/loongson/lsdc_drv.c| 2 +-
drivers/gpu/drm/nouveau/nouveau_vga.c | 2 +-
drivers/gpu/drm/radeon/radeon_device.c | 2 +-
drivers/pci/vgaarb.c | 55 --
drivers/vfio/pci/vfio_pci_core.c | 2 +-
include/linux/vgaarb.h | 8 ++--
8 files changed, 61 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a92c6189b4b6..d98f0801ac77 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4103,7 +4103,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
/* this will fail for cards that aren't VGA class devices, just
* ignore it */
if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
- vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
+ vga_client_register(adev->pdev, amdgpu_device_vga_set_decode,
NULL);
px = amdgpu_device_supports_px(ddev);
diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
index 286a0bdd28c6..98d7d4dffe9f 100644
--- a/drivers/gpu/drm/i915/display/intel_vga.c
+++ b/drivers/gpu/drm/i915/display/intel_vga.c
@@ -115,7 +115,6 @@ intel_vga_set_decode(struct pci_dev *pdev, bool
enable_decode)
int intel_vga_register(struct drm_i915_private *i915)
{
-
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
int ret;
@@ -127,7 +126,7 @@ int intel_vga_register(struct drm_i915_private *i915)
* then we do not take part in VGA arbitration and the
* vga_client_register() fails with -ENODEV.
*/
- ret = vga_client_register(pdev, intel_vga_set_decode);
+ ret = vga_client_register(pdev, intel_vga_set_decode, NULL);
if (ret && ret != -ENODEV)
return ret;
diff --git a/drivers/gpu/drm/loongson/lsdc_drv.c b/drivers/gpu/drm/loongson/lsdc_drv.c
index 188ec82afcfb..d10a28c2c494 100644
--- a/drivers/gpu/drm/loongson/lsdc_drv.c
+++ b/drivers/gpu/drm/loongson/lsdc_drv.c
@@ -289,7 +289,7 @@ static int lsdc_pci_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
pci_set_drvdata(pdev, ddev);
- vga_client_register(pdev, lsdc_vga_set_decode);
+ vga_client_register(pdev, lsdc_vga_set_decode, NULL);
[PATCH v2] drm: Spelling s/sempahore/semaphore/
Fix misspellings of "semaphore". Signed-off-by: Geert Uytterhoeven Reviewed-by: Hamza Mahfooz --- v2: - Add Reviewed-by. --- drivers/gpu/drm/i915/i915_request.c | 2 +- drivers/gpu/drm/radeon/cik.c| 2 +- drivers/gpu/drm/radeon/r600.c | 2 +- include/drm/task_barrier.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 894068bb37b6f1b6..32323bb801a139b7 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1220,7 +1220,7 @@ emit_semaphore_wait(struct i915_request *to, /* * If this or its dependents are waiting on an external fence * that may fail catastrophically, then we want to avoid using -* sempahores as they bypass the fence signaling metadata, and we +* semaphores as they bypass the fence signaling metadata, and we * lose the fence->error propagation. */ if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 5819737c21c678d3..5d6b81a6578ef2ba 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -3603,7 +3603,7 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev, * @rdev: radeon_device pointer * @ring: radeon ring buffer object * @semaphore: radeon semaphore object - * @emit_wait: Is this a sempahore wait? + * @emit_wait: Is this a semaphore wait? * * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP * from running ahead of semaphore waits. diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 382795a8b3c064ba..a17b95eec65fb810 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -2918,7 +2918,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev, * @rdev: radeon_device pointer * @ring: radeon ring buffer object * @semaphore: radeon semaphore object - * @emit_wait: Is this a sempahore wait? + * @emit_wait: Is this a semaphore wait? * * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP * from running ahead of semaphore waits. diff --git a/include/drm/task_barrier.h b/include/drm/task_barrier.h index 087e3f649c52f02d..217c1cf21c1ab7d5 100644 --- a/include/drm/task_barrier.h +++ b/include/drm/task_barrier.h @@ -25,7 +25,7 @@ /* * Reusable 2 PHASE task barrier (randevouz point) implementation for N tasks. - * Based on the Little book of sempahores - https://greenteapress.com/wp/semaphores/ + * Based on the Little book of semaphores - https://greenteapress.com/wp/semaphores/ */ -- 2.34.1
Re: [PATCH 28/29] drm/amdkfd: Refactor migrate init to support partition switch
On 5/10/23 23:23, Alex Deucher wrote: > From: Philip Yang > > Rename smv_migrate_init to a better name kgd2kfd_init_zone_device > because it setup zone devive pgmap for page migration and keep it in > kfd_migrate.c to access static functions svm_migrate_pgmap_ops. Call it > only once in amdgpu_device_ip_init after adev ip blocks are initialized, > but before amdgpu_amdkfd_device_init initialize kfd nodes which enable > SVM support based on pgmap. > > svm_range_set_max_pages is called by kgd2kfd_device_init everytime after > switching compute partition mode. > > Signed-off-by: Philip Yang > Reviewed-by: Felix Kuehling > Signed-off-by: Alex Deucher I bisected a regression to this commit, which broke HW acceleration on this ThinkPad E595 with Picasso APU. The IB test fails for the compute rings, see dmesg below. Reverting this commit on top of the DRM changes merged for 6.5 fixes the issue. [drm] amdgpu kernel modesetting enabled. amdgpu: Topology: Add APU node [0x0:0x0] [drm] initializing kernel modesetting (RAVEN 0x1002:0x15D8 0x17AA:0x5124 0xC1). [drm] register mmio base: 0xD050 [drm] register mmio size: 524288 [drm] MCBP is enabled [drm] add ip block number 0 [drm] add ip block number 1 [drm] add ip block number 2 [drm] add ip block number 3 [drm] add ip block number 4 [drm] add ip block number 5 [drm] add ip block number 6 [drm] add ip block number 7 [drm] add ip block number 8 [...] [drm] BIOS signature incorrect 0 0 amdgpu :05:00.0: amdgpu: Fetched VBIOS from ROM BAR amdgpu: ATOM BIOS: 113-PICASSO-114 [drm] VCN decode is enabled in VM mode [drm] VCN encode is enabled in VM mode [drm] JPEG decode is enabled in VM mode Console: switching to colour dummy device 80x25 amdgpu :05:00.0: vgaarb: deactivate vga console amdgpu :05:00.0: amdgpu: Trusted Memory Zone (TMZ) feature enabled stackdepot: allocating hash table of 1048576 entries via kvcalloc [drm] vm size is 262144 GB, 4 levels, block size is 9-bit, fragment size is 9-bit amdgpu :05:00.0: amdgpu: VRAM: 2048M 0x00F4 - 0x00F47FFF (2048M used) amdgpu :05:00.0: amdgpu: GART: 1024M 0x - 0x3FFF amdgpu :05:00.0: amdgpu: AGP: 267419648M 0x00F8 - 0x [drm] Detected VRAM RAM=2048M, BAR=2048M [drm] RAM width 64bits DDR4 [drm] amdgpu: 2048M of VRAM memory ready [drm] amdgpu: 6926M of GTT memory ready. [drm] GART: num cpu pages 262144, num gpu pages 262144 [drm] PCIE GART of 1024M enabled. [drm] PTB located at 0x00F400A0 amdgpu: hwmgr_sw_init smu backed is smu10_smu [drm] Found VCN firmware Version ENC: 1.13 DEC: 2 VEP: 0 Revision: 4 amdgpu :05:00.0: amdgpu: Will use PSP to load VCN firmware [drm] reserve 0x40 from 0xf47fc0 for PSP TMR amdgpu :05:00.0: amdgpu: RAS: optional ras ta ucode is not available amdgpu :05:00.0: amdgpu: RAP: optional rap ta ucode is not available [...] [drm] DM_PPLIB: values for F clock [drm] DM_PPLIB: 40 in kHz, 2749 in mV [drm] DM_PPLIB: 933000 in kHz, 3224 in mV [drm] DM_PPLIB: 1067000 in kHz, 3924 in mV [drm] DM_PPLIB: 120 in kHz, 4074 in mV [drm] DM_PPLIB: values for DCF clock [drm] DM_PPLIB: 30 in kHz, 2749 in mV [drm] DM_PPLIB: 60 in kHz, 3224 in mV [drm] DM_PPLIB: 626000 in kHz, 3924 in mV [drm] DM_PPLIB: 654000 in kHz, 4074 in mV [drm] Display Core initialized with v3.2.236! DCN 1.0 [...] [drm] DM_MST: Differing MST start on aconnector: 8d5d4db0 [id: 94] [drm] kiq ring mec 2 pipe 1 q 0 [drm] VCN decode and encode initialized successfully(under SPG Mode). amdgpu: HMM registered 2048MB device memory kfd kfd: amdgpu: Allocated 3969056 bytes on gart kfd kfd: amdgpu: Total number of KFD nodes to be created: 1 amdgpu: Topology: Add APU node [0x15d8:0x1002] amdgpu :05:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x address=0x169801800 flags=0x0070] amdgpu :05:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x address=0x13957d380 flags=0x0070] kfd kfd: amdgpu: added device 1002:15d8 amdgpu :05:00.0: amdgpu: SE 1, SH per SE 1, CU per SH 11, active_cu_number 10 amdgpu :05:00.0: amdgpu: ring gfx uses VM inv eng 0 on hub 0 amdgpu :05:00.0: amdgpu: ring gfx_low uses VM inv eng 1 on hub 0 amdgpu :05:00.0: amdgpu: ring gfx_high uses VM inv eng 4 on hub 0 amdgpu :05:00.0: amdgpu: ring comp_1.0.0 uses VM inv eng 5 on hub 0 amdgpu :05:00.0: amdgpu: ring comp_1.1.0 uses VM inv eng 6 on hub 0 amdgpu :05:00.0: amdgpu: ring comp_1.2.0 uses VM inv eng 7 on hub 0 amdgpu :05:00.0: amdgpu: ring comp_1.3.0 uses VM inv eng 8 on hub 0 amdgpu :05:00.0: amdgpu: ring comp_1.0.1 uses VM inv eng 9 on hub 0 amdgpu :05:00.0: amdgpu: ring comp_1.1.1 uses VM inv eng 10 on hub 0 amdgpu :05:00.0: amdgpu: ring comp_1.2.1 uses VM inv eng 11 on hub 0 amdgpu :05:00.0: amdgpu: ring comp_1.3.1 uses VM inv eng 12 on hub 0 amdgpu :05:00.0: amdgpu: ring kiq_0.2.1.0
Re: [PATCH 1/5] mm: introduce vma_is_stack() and vma_is_heap()
On 12.07.23 16:38, Kefeng Wang wrote:
Introduce the two helpers for general use.
Signed-off-by: Kefeng Wang
---
include/linux/mm.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 1462cf15badf..0bbeb31ac750 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -926,6 +926,18 @@ static inline bool vma_is_anonymous(struct vm_area_struct
*vma)
return !vma->vm_ops;
}
+static inline bool vma_is_heap(struct vm_area_struct *vma)
+{
+ return vma->vm_start <= vma->vm_mm->brk &&
+ vma->vm_end >= vma->vm_mm->start_brk;
+}
+
+static inline bool vma_is_stack(struct vm_area_struct *vma)
+{
+ return vma->vm_start <= vma->vm_mm->start_stack &&
+ vma->vm_end >= vma->vm_mm->start_stack;
+}
+
static inline bool vma_is_temporary_stack(struct vm_area_struct *vma)
{
int maybe_stack = vma->vm_flags & (VM_GROWSDOWN | VM_GROWSUP);
Looking at the comments in patch #3, should these functions be called
vma_is_initial_heap / vma_is_initial_stack ?
--
Cheers,
David / dhildenb
Re: [PATCH 2/5] mm: use vma_is_stack() and vma_is_heap()
On 12.07.23 16:38, Kefeng Wang wrote: Use the helpers to simplify code. Signed-off-by: Kefeng Wang --- fs/proc/task_mmu.c | 24 fs/proc/task_nommu.c | 15 +-- 2 files changed, 5 insertions(+), 34 deletions(-) Please squash patch #1 and this patch and call it something like "mm: factor out VMA stack and heap checks" And then, maybe also keep the comments in these functions, they sound reasonable to have. -- Cheers, David / dhildenb
[PATCH v5 05/11] drm/amdgpu: Use RMW accessors for changing LNKCTL
Don't assume that only the driver would be accessing LNKCTL. ASPM
policy changes can trigger write to LNKCTL outside of driver's control.
And in the case of upstream bridge, the driver does not even own the
device it's changing the registers for.
Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value.
Fixes: a2e73f56fa62 ("drm/amdgpu: Add support for CIK parts")
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Suggested-by: Lukas Wunner
Signed-off-by: Ilpo Järvinen
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/amd/amdgpu/cik.c | 36 +---
drivers/gpu/drm/amd/amdgpu/si.c | 36 +---
2 files changed, 20 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 5641cf05d856..e63abdf52b6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1574,17 +1574,8 @@ static void cik_pcie_gen3_enable(struct amdgpu_device
*adev)
u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp;
- pcie_capability_read_word(root, PCI_EXP_LNKCTL,
- _cfg);
- pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
- _cfg);
-
- tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
- pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
-
- tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
- pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
- tmp16);
+ pcie_capability_set_word(root, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD);
+ pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD);
tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
max_lw = (tmp &
PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
@@ -1637,21 +1628,14 @@ static void cik_pcie_gen3_enable(struct amdgpu_device
*adev)
msleep(100);
/* linkctl */
- pcie_capability_read_word(root, PCI_EXP_LNKCTL,
- );
- tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
- tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
- pcie_capability_write_word(root, PCI_EXP_LNKCTL,
- tmp16);
-
- pcie_capability_read_word(adev->pdev,
- PCI_EXP_LNKCTL,
- );
- tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
- tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
- pcie_capability_write_word(adev->pdev,
- PCI_EXP_LNKCTL,
- tmp16);
+ pcie_capability_clear_and_set_word(root,
PCI_EXP_LNKCTL,
+
PCI_EXP_LNKCTL_HAWD,
+ bridge_cfg &
+
PCI_EXP_LNKCTL_HAWD);
+ pcie_capability_clear_and_set_word(adev->pdev,
PCI_EXP_LNKCTL,
+
PCI_EXP_LNKCTL_HAWD,
+ gpu_cfg &
+
PCI_EXP_LNKCTL_HAWD);
/* linkctl2 */
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index f64b87b11b1b..4b81f29e5fd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -2276,17 +2276,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device
*adev)
u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp;
- pcie_capability_read_word(root, PCI_EXP_LNKCTL,
- _cfg);
- pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
- _cfg);
-
- tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
- pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
-
- tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
-
[PATCH v5 06/11] drm/radeon: Use RMW accessors for changing LNKCTL
Don't assume that only the driver would be accessing LNKCTL. ASPM
policy changes can trigger write to LNKCTL outside of driver's control.
And in the case of upstream bridge, the driver does not even own the
device it's changing the registers for.
Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value.
Fixes: 8a7cd27679d0 ("drm/radeon/cik: add support for pcie gen1/2/3 switching")
Fixes: b9d305dfb66c ("drm/radeon: implement pcie gen2/3 support for SI")
Suggested-by: Lukas Wunner
Signed-off-by: Ilpo Järvinen
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/radeon/cik.c | 36 ++-
drivers/gpu/drm/radeon/si.c | 37 ++--
2 files changed, 20 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 5819737c21c6..a6f3c811ceb8 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9534,17 +9534,8 @@ static void cik_pcie_gen3_enable(struct radeon_device
*rdev)
u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp;
- pcie_capability_read_word(root, PCI_EXP_LNKCTL,
- _cfg);
- pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
- _cfg);
-
- tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
- pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
-
- tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
- pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
- tmp16);
+ pcie_capability_set_word(root, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD);
+ pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD);
tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >>
LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -9591,21 +9582,14 @@ static void cik_pcie_gen3_enable(struct radeon_device
*rdev)
msleep(100);
/* linkctl */
- pcie_capability_read_word(root, PCI_EXP_LNKCTL,
- );
- tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
- tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
- pcie_capability_write_word(root, PCI_EXP_LNKCTL,
- tmp16);
-
- pcie_capability_read_word(rdev->pdev,
- PCI_EXP_LNKCTL,
- );
- tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
- tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
- pcie_capability_write_word(rdev->pdev,
- PCI_EXP_LNKCTL,
- tmp16);
+ pcie_capability_clear_and_set_word(root,
PCI_EXP_LNKCTL,
+
PCI_EXP_LNKCTL_HAWD,
+ bridge_cfg &
+
PCI_EXP_LNKCTL_HAWD);
+ pcie_capability_clear_and_set_word(rdev->pdev,
PCI_EXP_LNKCTL,
+
PCI_EXP_LNKCTL_HAWD,
+ gpu_cfg &
+
PCI_EXP_LNKCTL_HAWD);
/* linkctl2 */
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 8d5e4b25609d..a91012447b56 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7131,17 +7131,8 @@ static void si_pcie_gen3_enable(struct radeon_device
*rdev)
u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp;
- pcie_capability_read_word(root, PCI_EXP_LNKCTL,
- _cfg);
- pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
- _cfg);
-
- tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
- pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
-
- tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
-
Re: [PATCH 1/2] drm/amdgpu: allow secure submission on VCN4 ring
Since the changes will affect multiple ASICs, if you only tested with
VCN4_0_4, please just apply the set to that HW.
Regards,
Leo
On 2023-07-16 23:15, Guttula, Suresh wrote:
Hi Leo,
There are two issues here.
This change fixing the Crash while secure playback and we see below error:
2023-07-14T15:51:24.837592Z ERR kernel: [ 129.255823] amdgpu :c2:00.0: amdgpu:
secure submissions not supported on ring
2023-07-14T15:51:24.837601Z ERR kernel: [ 129.255827] [drm:amdgpu_job_run]
*ERROR* Error scheduling IBs (-22)
2023-07-14T15:51:24.837603Z INFO kernel: [ 129.255834] [drm] Skip scheduling
IBs!
The second one : https://patchwork.freedesktop.org/patch/547587/
Fixing the garbage/corruption.
With both patches playback working fine.
Thanks,
Suresh G
-Original Message-
From: Liu, Leo
Sent: Friday, July 14, 2023 7:08 PM
To: Guttula, Suresh ; Deucher, Alexander
; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/amdgpu: allow secure submission on VCN4 ring
On 2023-07-14 05:44, sguttula wrote:
This patch will enable secure decode playback on VCN4
Signed-off-by: sguttula
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index e8c02ae10163..d199f87febd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1804,6 +1804,7 @@ static int vcn_v4_0_ring_patch_cs_in_place(struct
amdgpu_cs_parser *p,
static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
.type = AMDGPU_RING_TYPE_VCN_ENC,
.align_mask = 0x3f,
+ .secure_submission_supported = true,
We should set it to true with VCN4_0_4 only for now, and check either this
boolean or VCN4_0_4 with your implementation from patch 2
Regards,
Leo
.nop = VCN_ENC_CMD_NO_OP,
.get_rptr = vcn_v4_0_unified_ring_get_rptr,
.get_wptr = vcn_v4_0_unified_ring_get_wptr,
[PATCH v2] drm/amdgpu: load sdma ucode in the guest machine
[why]
User mode driver need to check the sdma ucode version to
see whether the sdma engine supports a new type of PM4 packet.
In SRIOV, sdma is loaded by the host. And, there is no way
to check the sdma ucode version of CHIP_NAVI12 and
CHIP_SIENNA_CICHLID of the host in the guest machine.
[how]
Load the sdma ucode for CHIP_NAVI12 and CHIP_SIENNA_CICHLID
in the guest machine.
Signed-off-by: YuanShang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 11 +++
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +++-
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index dacf281d2b21..e2b9392d7f0d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -239,9 +239,6 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,
sizeof(struct amdgpu_sdma_instance));
}
- if (amdgpu_sriov_vf(adev))
- return 0;
-
DRM_DEBUG("psp_load == '%s'\n",
adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" :
"false");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 41aa853a07d2..ab76817d94ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -845,6 +845,17 @@ bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device
*adev, uint32_t ucode_i
return false;
else
return true;
+ case IP_VERSION(13, 0, 7):
+ case IP_VERSION(13, 0, 9):
+ /* black list for CHIP_NAVI12 and CHIP_SIENNA_CICHLID */
+ if (ucode_id == AMDGPU_UCODE_ID_RLC_G
+ || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
+ || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
+ || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
+ || ucode_id == AMDGPU_UCODE_ID_SMC)
+ return true;
+ else
+ return false;
case IP_VERSION(13, 0, 10):
/* white list */
if (ucode_id == AMDGPU_UCODE_ID_CAP
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 5c4d4df9cf94..1cc34efb455b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -237,17 +237,15 @@ static void sdma_v5_0_init_golden_registers(struct
amdgpu_device *adev)
// emulation only, won't work on real chip
// navi10 real chip need to use PSP to load firmware
static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
-{ int ret, i;
-
- if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] ==
IP_VERSION(5, 0, 5)))
- return 0;
+{
+ int ret, i;
for (i = 0; i < adev->sdma.num_instances; i++) {
ret = amdgpu_sdma_init_microcode(adev, i, false);
if (ret)
return ret;
}
-
+
return ret;
}
--
2.25.1
Re: [PATCH v4 12/18] staging: Remove flag FBINFO_FLAG_DEFAULT from fbdev drivers
On Sat, Jul 15, 2023 at 08:51:54PM +0200, Thomas Zimmermann wrote: > The flag FBINFO_FLAG_DEFAULT is 0 and has no effect, as struct > fbinfo.flags has been allocated to zero by framebuffer_alloc(). So do > not set it. > > Flags should signal differences from the default values. After cleaning > up all occurrences of FBINFO_DEFAULT, the token will be removed. > > v2: > * fix commit message (Miguel) > > Signed-off-by: Thomas Zimmermann > Acked-by: Sam Ravnborg > Cc: Greg Kroah-Hartman > Cc: Sudip Mukherjee > Cc: Teddy Wang Acked-by: Greg Kroah-Hartman
[PATCH] drm/connector: mark enum counter value as private
Mark the DRM_MODE_COLORIMETRY_COUNT enum value as private in
kernel-doc to prevent a build warning:
include/drm/drm_connector.h:527: warning: Enum value
'DRM_MODE_COLORIMETRY_COUNT' not described in enum 'drm_colorspace'
Fixes: c627087cb164 ("drm/connector: Use common colorspace_names array")
Signed-off-by: Randy Dunlap
Cc: David Airlie
Cc: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: dri-de...@lists.freedesktop.org
Cc: Harry Wentland
Cc: Alex Deucher
Cc: amd-gfx@lists.freedesktop.org
---
include/drm/drm_connector.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- linux-next-20230714.orig/include/drm/drm_connector.h
+++ linux-next-20230714/include/drm/drm_connector.h
@@ -522,7 +522,7 @@ enum drm_colorspace {
DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED = 13,
DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT = 14,
DRM_MODE_COLORIMETRY_BT601_YCC = 15,
- /* not a valid value; merely used for counting */
+ /* private: not a valid value; merely used for counting */
DRM_MODE_COLORIMETRY_COUNT
};
