RE: [PATCH] drm/amdgpu: Restore HQD persistent state register
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Tuesday, July 25, 2023 13:46
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kamal, Asad
Subject: [PATCH] drm/amdgpu: Restore HQD persistent state register
On GFX v9.4.3, compute queue MQD is populated using the values in HQD
persistent state register. Hence don't clear the values on module unload,
instead restore it to the default reset value so that MQD is initialized
correctly during next module load. In particular, preload flag needs to be set
on compute queue MQD, otherwise it could cause uninitialized values being used
at device reset state resulting in EDC.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 8b361aa87d01..306dc6533397 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -46,6 +46,7 @@ MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L
#define GOLDEN_GB_ADDR_CONFIG 0x2a114042
+#define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301
struct amdgpu_gfx_ras gfx_v9_4_3_ras;
@@ -1726,7 +1727,7 @@ static int gfx_v9_4_3_xcc_q_fini_register(struct
amdgpu_ring *ring,
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);
- WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,
0);
+ WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,
+CP_HQD_PERSISTENT_STATE_DEFAULT);
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
regCP_HQD_PQ_DOORBELL_CONTROL, 0x4000);
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
regCP_HQD_PQ_DOORBELL_CONTROL, 0);
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);
--
2.25.1
[PATCH] drm/amdgpu: Restore HQD persistent state register
On GFX v9.4.3, compute queue MQD is populated using the values in HQD
persistent state register. Hence don't clear the values on module
unload, instead restore it to the default reset value so that MQD is
initialized correctly during next module load. In particular, preload
flag needs to be set on compute queue MQD, otherwise it could cause
uninitialized values being used at device reset state resulting in EDC.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 8b361aa87d01..306dc6533397 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -46,6 +46,7 @@ MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L
#define GOLDEN_GB_ADDR_CONFIG 0x2a114042
+#define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301
struct amdgpu_gfx_ras gfx_v9_4_3_ras;
@@ -1726,7 +1727,7 @@ static int gfx_v9_4_3_xcc_q_fini_register(struct
amdgpu_ring *ring,
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);
- WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,
0);
+ WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,
CP_HQD_PERSISTENT_STATE_DEFAULT);
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
regCP_HQD_PQ_DOORBELL_CONTROL, 0x4000);
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
regCP_HQD_PQ_DOORBELL_CONTROL, 0);
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);
--
2.25.1
RE: [PATCH V2] drm/amdgpu: remove redundant variable declaration
[Public]
Reviewed-by: Srinivasan Shanmugam
-Original Message-
From: amd-gfx On Behalf Of Bob Zhou
Sent: Monday, July 24, 2023 2:06 PM
To: amd-gfx@lists.freedesktop.org; Pelloux-Prayer, Pierre-Eric
Cc: Zhou, Bob ; Chen, Guchun
Subject: [PATCH V2] drm/amdgpu: remove redundant variable declaration
building with gcc and W=1 reports
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:1618:15:
error: unused variable 'domain' [-Werror=unused-variable] unsigned int domain;
^~
The variable domain is repeated, so remove it.
Fixes: d769528e4649 ("drm/amdgpu: add VISIBLE info in amdgpu_bo_print_info")
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5ac7544cc068..3f98174fb764 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1578,7 +1578,6 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo,
struct seq_file *m) {
struct dma_buf_attachment *attachment;
struct dma_buf *dma_buf;
- unsigned int domain;
const char *placement;
unsigned int pin_count;
u64 size;
--
2.34.1
RE: [PATCH] drm/amdgpu: Fix ENOSYS means 'invalid syscall nr' in amdgpu_device.c
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Srinivasan Shanmugam
> Sent: Sunday, July 23, 2023 2:16 PM
> To: Koenig, Christian ; Deucher, Alexander
>
> Cc: SHANMUGAM, SRINIVASAN ;
> amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: Fix ENOSYS means 'invalid syscall nr' in
> amdgpu_device.c
>
> ENOSYS should be used for nonexistent syscalls only, replace ENOSYS with
> EINVAL & other style fixes
>
> WARNING: ENOSYS means 'invalid syscall nr' and nothing else
> + if (r == -ENOSYS)
>
> WARNING: ENOSYS means 'invalid syscall nr' and nothing else
> + if (r == -ENOSYS)
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
Reviewed-by: Guchun Chen
Regards,
Guchun
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 60 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 4 +-
> 2 files changed, 33 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 1c786190a84e..ec166c797b9a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -159,7 +159,7 @@ static ssize_t
> amdgpu_device_get_pcie_replay_count(struct device *dev,
> return sysfs_emit(buf, "%llu\n", cnt); }
>
> -static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
> +static DEVICE_ATTR(pcie_replay_count, 0444,
> amdgpu_device_get_pcie_replay_count, NULL);
>
> static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
> @@ -183,7 +183,7 @@ static ssize_t
> amdgpu_device_get_product_name(struct device *dev,
> return sysfs_emit(buf, "%s\n", adev->product_name); }
>
> -static DEVICE_ATTR(product_name, S_IRUGO,
> +static DEVICE_ATTR(product_name, 0444,
> amdgpu_device_get_product_name, NULL);
>
> /**
> @@ -205,7 +205,7 @@ static ssize_t
> amdgpu_device_get_product_number(struct device *dev,
> return sysfs_emit(buf, "%s\n", adev->product_number); }
>
> -static DEVICE_ATTR(product_number, S_IRUGO,
> +static DEVICE_ATTR(product_number, 0444,
> amdgpu_device_get_product_number, NULL);
>
> /**
> @@ -227,7 +227,7 @@ static ssize_t
> amdgpu_device_get_serial_number(struct device *dev,
> return sysfs_emit(buf, "%s\n", adev->serial); }
>
> -static DEVICE_ATTR(serial_number, S_IRUGO,
> +static DEVICE_ATTR(serial_number, 0444,
> amdgpu_device_get_serial_number, NULL);
>
> /**
> @@ -481,8 +481,7 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device
> *adev,
> /*
> * MMIO register read with bytes helper functions
> * @offset:bytes offset from MMIO start
> - *
> -*/
> + */
>
> /**
> * amdgpu_mm_rreg8 - read a memory mapped IO register @@ -506,8
> +505,8 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev,
> uint32_t offset)
> * MMIO register write with bytes helper functions
> * @offset:bytes offset from MMIO start
> * @value: the value want to be written to the register
> - *
> -*/
> + */
> +
> /**
> * amdgpu_mm_wreg8 - read a memory mapped IO register
> *
> @@ -991,7 +990,7 @@ static void amdgpu_device_mem_scratch_fini(struct
> amdgpu_device *adev)
> * @registers: pointer to the register array
> * @array_size: size of the register array
> *
> - * Programs an array or registers with and and or masks.
> + * Programs an array or registers with and or masks.
> * This is a helper for setting golden registers.
> */
> void amdgpu_device_program_register_sequence(struct amdgpu_device
> *adev, @@ -1157,7 +1156,7 @@ int amdgpu_device_resize_fb_bar(struct
> amdgpu_device *adev)
> int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
> struct pci_bus *root;
> struct resource *res;
> - unsigned i;
> + unsigned int i;
> u16 cmd;
> int r;
>
> @@ -1226,9 +1225,8 @@ int amdgpu_device_resize_fb_bar(struct
> amdgpu_device *adev)
>
> static bool amdgpu_device_read_bios(struct amdgpu_device *adev) {
> - if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU)) {
> + if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
> return false;
> - }
>
> return true;
> }
> @@ -1264,6 +1262,7 @@ bool amdgpu_device_need_post(struct
> amdgpu_device *adev)
> if (adev->asic_type == CHIP_FIJI) {
> int err;
> uint32_t fw_ver;
> +
> err = request_firmware(&adev->pm.fw,
> "amdgpu/fiji_smc.bin", adev->dev);
> /* force vPost if error occured */
> if (err)
> @@ -1366,6 +1365,7 @@ static unsigned int
> amdgpu_device_vga_set_decode(struct pci_dev *pdev,
> bool state)
> {
> struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
> +
> amdgpu_asic_set_vga_state(adev, state);
> if (state)
> return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
> @@ -1388,7 +1388,8 @@ static void
> amdgpu
RE: [PATCH] drm/amdgpu: Move externs to amdgpu.h file from amdgpu_drv.c
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Srinivasan Shanmugam
> Sent: Tuesday, July 25, 2023 12:42 PM
> To: Koenig, Christian ; Deucher, Alexander
>
> Cc: SHANMUGAM, SRINIVASAN ;
> amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: Move externs to amdgpu.h file from
> amdgpu_drv.c
>
> WARNING: externs should be avoided in .c files
> +extern const struct attribute_group amdgpu_vram_mgr_attr_group;
>
> WARNING: externs should be avoided in .c files
> +extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
>
> WARNING: externs should be avoided in .c files
> +extern const struct attribute_group amdgpu_flash_attr_group;
>
> And other style fixes:
>
> WARNING: Block comments should align the * on each line
> WARNING: void function return statements are not generally useful
> WARNING: braces {} are not necessary for single statement blocks
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 28 +
> 2 files changed, 14 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index a046160b6a0e..93d0f4c7b560 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1524,4 +1524,8 @@ static inline bool amdgpu_is_tmz(struct
> amdgpu_device *adev)
>
> int amdgpu_in_reset(struct amdgpu_device *adev);
>
> +extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern
> +const struct attribute_group amdgpu_gtt_mgr_attr_group; extern const
> +struct attribute_group amdgpu_flash_attr_group;
> +
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index c315fe390e71..84446bbc3509 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -313,9 +313,7 @@ module_param_named(msi, amdgpu_msi, int, 0444);
> * jobs is 1. The timeout for compute is 6.
> */
> MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default:
> for bare metal 1 for non-compute jobs and 6 for compute jobs; "
> - "for passthrough or sriov, 1 for all jobs."
> - " 0: keep default value. negative: infinity timeout), "
> - "format: for bare metal [Non-Compute] or
> [GFX,Compute,SDMA,Video]; "
> + "for passthrough or sriov, 1 for all jobs. 0: keep default
> value. negative: infinity timeout), format: for bare metal [Non-Compute] or
> [GFX,Compute,SDMA,Video]; "
> "for passthrough or sriov [all jobs] or
> [GFX,Compute,SDMA,Video]."); module_param_string(lockup_timeout,
> amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
>
> @@ -585,7 +583,7 @@ module_param_named(timeout_period,
> amdgpu_watchdog_timer.period, uint, 0644); #ifdef
> CONFIG_DRM_AMDGPU_SI
>
> #if IS_ENABLED(CONFIG_DRM_RADEON) ||
> IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
> -int amdgpu_si_support = 0;
I guess we should leave it as it is.
> +int amdgpu_si_support;
> MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled
> (default))"); #else int amdgpu_si_support = 1; @@ -604,7 +602,7 @@
> module_param_named(si_support, amdgpu_si_support, int, 0444); #ifdef
> CONFIG_DRM_AMDGPU_CIK
>
> #if IS_ENABLED(CONFIG_DRM_RADEON) ||
> IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
> -int amdgpu_cik_support = 0;
> +int amdgpu_cik_support;
Same as above.
With the 2 nitpicks fixed, this patch is: Reviewed-by: Guchun Chen
Regards,
Guchun
> MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled
> (default))"); #else int amdgpu_cik_support = 1; @@ -620,8 +618,7 @@
> module_param_named(cik_support, amdgpu_cik_support, int, 0444);
> * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The
> default is 0 (disabled).
> */
> MODULE_PARM_DESC(smu_memory_pool_size,
> - "reserve gtt for smu debug usage, 0 = disable,"
> - "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 =
> 2GByte");
> + "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 =
> +512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
> module_param_named(smu_memory_pool_size,
> amdgpu_smu_memory_pool_size, uint, 0444);
>
> /**
> @@ -791,9 +788,9 @@ module_param(hws_gws_support, bool, 0444);
> MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS
> barriers (false = rely on FW version check (Default), true = force
> supported)");
>
> /**
> - * DOC: queue_preemption_timeout_ms (int)
> - * queue preemption timeout in ms (1 = Minimum, 9000 = default)
> - */
> + * DOC: queue_preemption_timeout_ms (int)
> + * queue preemption timeout in ms (1 = Minimum, 9000 = default) */
> int queue_preemption_timeout_ms = 9000;
> module_param(queue_preemption_timeout_ms, int, 0644);
> MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption
> timeo
RE: [PATCH] drm/amdgpu: Fix unused variable 'domain' in 'amdgpu_bo_print_info'
[Public]
Thanks for your patch, Srini. This has been fixed by
https://patchwork.freedesktop.org/patch/549040/.
> -Original Message-
> From: amd-gfx On Behalf Of
> Srinivasan Shanmugam
> Sent: Monday, July 24, 2023 10:41 PM
> To: Koenig, Christian ; Deucher, Alexander
>
> Cc: SHANMUGAM, SRINIVASAN ;
> amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: Fix unused variable 'domain' in
> 'amdgpu_bo_print_info'
>
> Fixes the following:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c: In function
> ‘amdgpu_bo_print_info’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:1581:15: warning: unused
> variable ‘domain’ [-Wunused-variable]
> 1581 | unsigned int domain;
> | ^~
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 5ac7544cc068..3f98174fb764 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -1578,7 +1578,6 @@ u64 amdgpu_bo_print_info(int id, struct
> amdgpu_bo *bo, struct seq_file *m) {
> struct dma_buf_attachment *attachment;
> struct dma_buf *dma_buf;
> - unsigned int domain;
> const char *placement;
> unsigned int pin_count;
> u64 size;
> --
> 2.25.1
<>
[PATCH v2] drm/amdgpu: Move externs to amdgpu.h file from amdgpu_drv.c
Fixes the following:
WARNING: externs should be avoided in .c files
+extern const struct attribute_group amdgpu_vram_mgr_attr_group;
WARNING: externs should be avoided in .c files
+extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
WARNING: externs should be avoided in .c files
+extern const struct attribute_group amdgpu_flash_attr_group;
And other style fixes:
ERROR: do not initialise globals to 0
WARNING: Block comments should align the * on each line
WARNING: void function return statements are not generally useful
WARNING: braces {} are not necessary for single statement blocks
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
v2:
- Updated commit message - Added "ERROR: do not initialise globals to
0"
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 28 +
2 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a046160b6a0e..93d0f4c7b560 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1524,4 +1524,8 @@ static inline bool amdgpu_is_tmz(struct amdgpu_device
*adev)
int amdgpu_in_reset(struct amdgpu_device *adev);
+extern const struct attribute_group amdgpu_vram_mgr_attr_group;
+extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
+extern const struct attribute_group amdgpu_flash_attr_group;
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c315fe390e71..84446bbc3509 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -313,9 +313,7 @@ module_param_named(msi, amdgpu_msi, int, 0444);
* jobs is 1. The timeout for compute is 6.
*/
MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare
metal 1 for non-compute jobs and 6 for compute jobs; "
- "for passthrough or sriov, 1 for all jobs."
- " 0: keep default value. negative: infinity timeout), "
- "format: for bare metal [Non-Compute] or
[GFX,Compute,SDMA,Video]; "
+ "for passthrough or sriov, 1 for all jobs. 0: keep default
value. negative: infinity timeout), format: for bare metal [Non-Compute] or
[GFX,Compute,SDMA,Video]; "
"for passthrough or sriov [all jobs] or
[GFX,Compute,SDMA,Video].");
module_param_string(lockup_timeout, amdgpu_lockup_timeout,
sizeof(amdgpu_lockup_timeout), 0444);
@@ -585,7 +583,7 @@ module_param_named(timeout_period,
amdgpu_watchdog_timer.period, uint, 0644);
#ifdef CONFIG_DRM_AMDGPU_SI
#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
-int amdgpu_si_support = 0;
+int amdgpu_si_support;
MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled
(default))");
#else
int amdgpu_si_support = 1;
@@ -604,7 +602,7 @@ module_param_named(si_support, amdgpu_si_support, int,
0444);
#ifdef CONFIG_DRM_AMDGPU_CIK
#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
-int amdgpu_cik_support = 0;
+int amdgpu_cik_support;
MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled
(default))");
#else
int amdgpu_cik_support = 1;
@@ -620,8 +618,7 @@ module_param_named(cik_support, amdgpu_cik_support, int,
0444);
* E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The
default is 0 (disabled).
*/
MODULE_PARM_DESC(smu_memory_pool_size,
- "reserve gtt for smu debug usage, 0 = disable,"
- "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
+ "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 =
512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint,
0444);
/**
@@ -791,9 +788,9 @@ module_param(hws_gws_support, bool, 0444);
MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false
= rely on FW version check (Default), true = force supported)");
/**
- * DOC: queue_preemption_timeout_ms (int)
- * queue preemption timeout in ms (1 = Minimum, 9000 = default)
- */
+ * DOC: queue_preemption_timeout_ms (int)
+ * queue preemption timeout in ms (1 = Minimum, 9000 = default)
+ */
int queue_preemption_timeout_ms = 9000;
module_param(queue_preemption_timeout_ms, int, 0644);
MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms
(1 = Minimum, 9000 = default)");
@@ -2417,7 +2414,6 @@ static void amdgpu_drv_delayed_reset_work_handler(struct
work_struct *work)
amdgpu_amdkfd_device_init(adev);
amdgpu_ttm_set_buffer_funcs_status(adev, true);
}
- return;
}
static int amdgpu_pmops_prepare(struct device *dev)
@@ -2614,6 +2610,7 @@ static int amdgpu_pmops_runtime_suspend(struct device
*dev)
/* wait for all rings to drain before suspe
[PATCH] drm/amdgpu: Move externs to amdgpu.h file from amdgpu_drv.c
WARNING: externs should be avoided in .c files
+extern const struct attribute_group amdgpu_vram_mgr_attr_group;
WARNING: externs should be avoided in .c files
+extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
WARNING: externs should be avoided in .c files
+extern const struct attribute_group amdgpu_flash_attr_group;
And other style fixes:
WARNING: Block comments should align the * on each line
WARNING: void function return statements are not generally useful
WARNING: braces {} are not necessary for single statement blocks
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 28 +
2 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a046160b6a0e..93d0f4c7b560 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1524,4 +1524,8 @@ static inline bool amdgpu_is_tmz(struct amdgpu_device
*adev)
int amdgpu_in_reset(struct amdgpu_device *adev);
+extern const struct attribute_group amdgpu_vram_mgr_attr_group;
+extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
+extern const struct attribute_group amdgpu_flash_attr_group;
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c315fe390e71..84446bbc3509 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -313,9 +313,7 @@ module_param_named(msi, amdgpu_msi, int, 0444);
* jobs is 1. The timeout for compute is 6.
*/
MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare
metal 1 for non-compute jobs and 6 for compute jobs; "
- "for passthrough or sriov, 1 for all jobs."
- " 0: keep default value. negative: infinity timeout), "
- "format: for bare metal [Non-Compute] or
[GFX,Compute,SDMA,Video]; "
+ "for passthrough or sriov, 1 for all jobs. 0: keep default
value. negative: infinity timeout), format: for bare metal [Non-Compute] or
[GFX,Compute,SDMA,Video]; "
"for passthrough or sriov [all jobs] or
[GFX,Compute,SDMA,Video].");
module_param_string(lockup_timeout, amdgpu_lockup_timeout,
sizeof(amdgpu_lockup_timeout), 0444);
@@ -585,7 +583,7 @@ module_param_named(timeout_period,
amdgpu_watchdog_timer.period, uint, 0644);
#ifdef CONFIG_DRM_AMDGPU_SI
#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
-int amdgpu_si_support = 0;
+int amdgpu_si_support;
MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled
(default))");
#else
int amdgpu_si_support = 1;
@@ -604,7 +602,7 @@ module_param_named(si_support, amdgpu_si_support, int,
0444);
#ifdef CONFIG_DRM_AMDGPU_CIK
#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
-int amdgpu_cik_support = 0;
+int amdgpu_cik_support;
MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled
(default))");
#else
int amdgpu_cik_support = 1;
@@ -620,8 +618,7 @@ module_param_named(cik_support, amdgpu_cik_support, int,
0444);
* E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The
default is 0 (disabled).
*/
MODULE_PARM_DESC(smu_memory_pool_size,
- "reserve gtt for smu debug usage, 0 = disable,"
- "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
+ "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 =
512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint,
0444);
/**
@@ -791,9 +788,9 @@ module_param(hws_gws_support, bool, 0444);
MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false
= rely on FW version check (Default), true = force supported)");
/**
- * DOC: queue_preemption_timeout_ms (int)
- * queue preemption timeout in ms (1 = Minimum, 9000 = default)
- */
+ * DOC: queue_preemption_timeout_ms (int)
+ * queue preemption timeout in ms (1 = Minimum, 9000 = default)
+ */
int queue_preemption_timeout_ms = 9000;
module_param(queue_preemption_timeout_ms, int, 0644);
MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms
(1 = Minimum, 9000 = default)");
@@ -2417,7 +2414,6 @@ static void amdgpu_drv_delayed_reset_work_handler(struct
work_struct *work)
amdgpu_amdkfd_device_init(adev);
amdgpu_ttm_set_buffer_funcs_status(adev, true);
}
- return;
}
static int amdgpu_pmops_prepare(struct device *dev)
@@ -2614,6 +2610,7 @@ static int amdgpu_pmops_runtime_suspend(struct device
*dev)
/* wait for all rings to drain before suspending */
for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
struct amdgpu_ring *ring = adev->rings[i];
+
if (ring
RE: [PATCH 2/3] drm/amdgpu: add ih 6.1 support
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, July 25, 2023 4:05 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Li, Ben
>
> Subject: [PATCH 2/3] drm/amdgpu: add ih 6.1 support
>
> From: benl
>
> Add initial support for IH 6.1.
>
> Signed-off-by: benl
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 769
> +++ drivers/gpu/drm/amd/amdgpu/ih_v6_1.h
> | 28 +
> 3 files changed, 799 insertions(+), 1 deletion(-) create mode 100644
> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/ih_v6_1.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 29325981778a0..384b798a9bad1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -129,7 +129,8 @@ amdgpu-y += \
> vega10_ih.o \
> vega20_ih.o \
> navi10_ih.o \
> - ih_v6_0.o
> + ih_v6_0.o \
> + ih_v6_1.o
>
> # add PSP block
> amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> new file mode 100644
> index 0..5795a66ccbc5d
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> @@ -0,0 +1,769 @@
> +/*
> + * Copyright 2021 Advanced Micro Devices, Inc.
> + *
I guess the copyright year here should be 2023? Same for the new header file
ih_v6_1.h if it's right.
Regards,
Guchun
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> +"Software"),
> + * to deal in the Software without restriction, including without
> +limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> +sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> +the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> +included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> +MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> +SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> +DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> +OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE
> +OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include
> +
> +#include "amdgpu.h"
> +#include "amdgpu_ih.h"
> +
> +#include "oss/osssys_6_1_0_offset.h"
> +#include "oss/osssys_6_1_0_sh_mask.h"
> +
> +#include "soc15_common.h"
> +#include "ih_v6_1.h"
> +
> +#define MAX_REARM_RETRY 10
> +
> +static void ih_v6_1_set_interrupt_funcs(struct amdgpu_device *adev);
> +
> +/**
> + * ih_v6_1_init_register_offset - Initialize register offset for ih
> +rings
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * Initialize register offset ih rings (IH_V6_0).
> + */
> +static void ih_v6_1_init_register_offset(struct amdgpu_device *adev) {
> + struct amdgpu_ih_regs *ih_regs;
> +
> + /* ih ring 2 is removed
> + * ih ring and ih ring 1 are available */
> + if (adev->irq.ih.ring_size) {
> + ih_regs = &adev->irq.ih.ih_regs;
> + ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_RB_BASE);
> + ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_RB_BASE_HI);
> + ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_RB_CNTL);
> + ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_RB_WPTR);
> + ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_RB_RPTR);
> + ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_DOORBELL_RPTR);
> + ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS,
> 0, regIH_RB_WPTR_ADDR_LO);
> + ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS,
> 0, regIH_RB_WPTR_ADDR_HI);
> + ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
> + }
> +
> + if (adev->irq.ih1.ring_size) {
> + ih_regs = &adev->irq.ih1.ih_regs;
> + ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_RB_BASE_RING1);
> + ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_RB_BASE_HI_RING1);
> + ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_RB_CNTL_RING1);
> + ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_RB_WPTR_RING1);
> + ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_RB_RPTR_RING1);
> + ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0,
> regIH_DOORBELL_RPTR_RING1);
> + ih_reg
Non-robust apps and resets (was Re: [PATCH v5 1/1] drm/doc: Document DRM device reset expectations)
Hi everyone, It's not clear what we should do about non-robust OpenGL apps after GPU resets, so I'll try to summarize the topic, show some options and my proposal to move forward on that. Em 27/06/2023 10:23, André Almeida escreveu: +Robustness +-- + +The only way to try to keep an application working after a reset is if it +complies with the robustness aspects of the graphical API that it is using. + +Graphical APIs provide ways to applications to deal with device resets. However, +there is no guarantee that the app will use such features correctly, and the +UMD can implement policies to close the app if it is a repeating offender, +likely in a broken loop. This is done to ensure that it does not keep blocking +the user interface from being correctly displayed. This should be done even if +the app is correct but happens to trigger some bug in the hardware/driver. + Depending on the OpenGL version, there are different robustness API available: - OpenGL ABR extension [0] - OpenGL KHR extension [1] - OpenGL ES extension [2] Apps written in OpenGL should use whatever version is available for them to make the app robust for GPU resets. That usually means calling GetGraphicsResetStatusARB(), checking the status, and if it encounter something different from NO_ERROR, that means that a reset has happened, the context is considered lost and should be recreated. If an app follow this, it will likely succeed recovering a reset. What should non-robustness apps do then? They certainly will not be notified if a reset happens, and thus can't recover if their context is lost. OpenGL specification does not explicitly define what should be done in such situations[3], and I believe that usually when the spec mandates to close the app, it would explicitly note it. However, in reality there are different types of device resets, causing different results. A reset can be precise enough to damage only the guilty context, and keep others alive. Given that, I believe drivers have the following options: a) Kill all non-robust apps after a reset. This may lead to lose work from innocent applications. b) Ignore all non-robust apps OpenGL calls. That means that applications would still be alive, but the user interface would be freeze. The user would need to close it manually anyway, but in some corner cases, the app could autosave some work or the user might be able to interact with it using some alternative method (command line?). c) Kill just the affected non-robust applications. To do that, the driver need to be 100% sure on the impact of its resets. RadeonSI currently implements a), as can be seen at [4], while Iris implements what I think it's c)[5]. For the user experience point-of-view, c) is clearly the best option, but it's the hardest to archive. There's not much gain on having b) over a), perhaps it could be an optional env var for such corner case applications. My proposal for the documentation is: implement a) if nothing else is available, have a MESA_NO_RESET_KILL for people that want b), ideally implement c) if the driver is able to know for sure that the non-guilty apps can still work after a reset. Thanks, André [0] https://registry.khronos.org/OpenGL/extensions/ARB/ARB_robustness.txt [1] https://registry.khronos.org/OpenGL/extensions/KHR/KHR_robustness.txt [2] https://registry.khronos.org/OpenGL/extensions/EXT/EXT_robustness.txt [3] https://registry.khronos.org/OpenGL/specs/gl/glspec46.core.pdf [4] https://gitlab.freedesktop.org/mesa/mesa/-/blob/23.1/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c#L1657 [5] https://gitlab.freedesktop.org/mesa/mesa/-/blob/23.1/src/gallium/drivers/iris/iris_batch.c#L842
RE: [PATCH v2] drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4 to acquire gpu_metrics
[AMD Official Use Only - General]
Hi Wenyou,
Could you merge the patch?
Thanks,
Richard
-Original Message-
From: Quan, Evan
Sent: Tuesday, July 18, 2023 12:03 AM
To: Yang, WenYou ; Deucher, Alexander
; Limonciello, Mario ;
Koenig, Christian ; Pan, Xinhui
Cc: Yuan, Perry ; Liang, Richard qi
; amd-gfx@lists.freedesktop.org;
dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org
Subject: RE: [PATCH v2] drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4 to
acquire gpu_metrics
[AMD Official Use Only - General]
Hi Wenyou,
I think you already got the greenlight(RB from Mario and ACK from me) to land
the change.
Go ahead please.
Evan
> -Original Message-
> From: Yang, WenYou
> Sent: Thursday, July 13, 2023 8:56 AM
> To: Yang, WenYou ; Deucher, Alexander
> ; Limonciello, Mario
> ; Koenig, Christian
> ; Pan, Xinhui ; Quan,
> Evan
> Cc: Yuan, Perry ; Liang, Richard qi
> ; amd-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; linux-ker...@vger.kernel.org
> Subject: RE: [PATCH v2] drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4
> to acquire gpu_metrics
>
> [AMD Official Use Only - General]
>
> Any comments? Any advice?
>
> Best Regards,
> Wenyou
>
> > -Original Message-
> > From: Wenyou Yang
> > Sent: Wednesday, June 21, 2023 2:32 PM
> > To: Deucher, Alexander ; Limonciello,
> > Mario ; Koenig, Christian
> > ; Pan, Xinhui ; Quan,
> > Evan
> > Cc: Yuan, Perry ; Liang, Richard qi
> > ; amd-gfx@lists.freedesktop.org; dri-
> > de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; Yang,
> > WenYou
> > Subject: [PATCH v2] drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4 to
> > acquire gpu_metrics
> >
> > To acquire the voltage and current info from gpu_metrics interface,
> > but
> > gpu_metrics_v2_3 doesn't contain them, and to be backward
> > compatible, add new gpu_metrics_v2_4 structure.
> >
> > Reviewed-by: Mario Limonciello
> > Acked-by: Evan Quan
> > Signed-off-by: Wenyou Yang
> > ---
> > .../gpu/drm/amd/include/kgd_pp_interface.h| 69 +++
> > .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 109
> -
> > -
> > drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 3 +
> > 3 files changed, 172 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > index 9f542f6e19ed..90989405eddc 100644
> > --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > @@ -892,4 +892,73 @@ struct gpu_metrics_v2_3 {
> > uint16_taverage_temperature_core[8]; //
> > average CPU core temperature on APUs
> > uint16_taverage_temperature_l3[2];
> > };
> > +
> > +struct gpu_metrics_v2_4 {
> > + struct metrics_table_header common_header;
> > +
> > + /* Temperature (unit: centi-Celsius) */
> > + uint16_ttemperature_gfx;
> > + uint16_ttemperature_soc;
> > + uint16_ttemperature_core[8];
> > + uint16_ttemperature_l3[2];
> > +
> > + /* Utilization (unit: centi) */
> > + uint16_taverage_gfx_activity;
> > + uint16_taverage_mm_activity;
> > +
> > + /* Driver attached timestamp (in ns) */
> > + uint64_tsystem_clock_counter;
> > +
> > + /* Power/Energy (unit: mW) */
> > + uint16_taverage_socket_power;
> > + uint16_taverage_cpu_power;
> > + uint16_taverage_soc_power;
> > + uint16_taverage_gfx_power;
> > + uint16_taverage_core_power[8];
> > +
> > + /* Average clocks (unit: MHz) */
> > + uint16_taverage_gfxclk_frequency;
> > + uint16_taverage_socclk_frequency;
> > + uint16_taverage_uclk_frequency;
> > + uint16_taverage_fclk_frequency;
> > + uint16_taverage_vclk_frequency;
> > + uint16_taverage_dclk_frequency;
> > +
> > + /* Current clocks (unit: MHz) */
> > + uint16_tcurrent_gfxclk;
> > + uint16_tcurrent_socclk;
> > + uint16_tcurrent_uclk;
> > + uint16_tcurrent_fclk;
> > + uint16_tcurrent_vclk;
> > + uint16_tcurrent_dclk;
> > + uint16_tcurrent_coreclk[8];
> > + uint16_tcurrent_l3clk[2];
> > +
> > + /* Throttle status (ASIC dependent) */
> > + uint32_tthrottle_status;
> > +
> > + /* Fans */
> > + uint16_tfan_pwm;
> > +
> > + uint16_t
Re: [PATCH] drm/amd/pm: open brace '{' following struct go on the same line
Applied. Thanks!
On Mon, Jul 24, 2023 at 5:08 AM wrote:
>
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: Ran Sun
> ---
> .../amd/pm/swsmu/inc/smu_v13_0_7_pptable.h| 21 +++
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> index eadbe0149cae..eb694f9f556d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> @@ -41,8 +41,7 @@
> #define SMU_13_0_7_PP_OVERDRIVE_VERSION 0x83// OverDrive 8
> Table Version 0.2
> #define SMU_13_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
> Clock Table Version 1.00
>
> -enum SMU_13_0_7_ODFEATURE_CAP
> -{
> +enum SMU_13_0_7_ODFEATURE_CAP {
> SMU_13_0_7_ODCAP_GFXCLK_LIMITS = 0,
> SMU_13_0_7_ODCAP_UCLK_LIMITS,
> SMU_13_0_7_ODCAP_POWER_LIMIT,
> @@ -62,8 +61,7 @@ enum SMU_13_0_7_ODFEATURE_CAP
> SMU_13_0_7_ODCAP_COUNT,
> };
>
> -enum SMU_13_0_7_ODFEATURE_ID
> -{
> +enum SMU_13_0_7_ODFEATURE_ID {
> SMU_13_0_7_ODFEATURE_GFXCLK_LIMITS = 1 <<
> SMU_13_0_7_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
> SMU_13_0_7_ODFEATURE_UCLK_LIMITS = 1 <<
> SMU_13_0_7_ODCAP_UCLK_LIMITS, //UCLK Limit feature
> SMU_13_0_7_ODFEATURE_POWER_LIMIT = 1 <<
> SMU_13_0_7_ODCAP_POWER_LIMIT, //Power Limit feature
> @@ -85,8 +83,7 @@ enum SMU_13_0_7_ODFEATURE_ID
>
> #define SMU_13_0_7_MAX_ODFEATURE 32 //Maximum Number of OD Features
>
> -enum SMU_13_0_7_ODSETTING_ID
> -{
> +enum SMU_13_0_7_ODSETTING_ID {
> SMU_13_0_7_ODSETTING_GFXCLKFMAX = 0,
> SMU_13_0_7_ODSETTING_GFXCLKFMIN,
> SMU_13_0_7_ODSETTING_UCLKFMIN,
> @@ -123,8 +120,7 @@ enum SMU_13_0_7_ODSETTING_ID
> };
> #define SMU_13_0_7_MAX_ODSETTING 64 //Maximum Number of ODSettings
>
> -enum SMU_13_0_7_PWRMODE_SETTING
> -{
> +enum SMU_13_0_7_PWRMODE_SETTING {
> SMU_13_0_7_PMSETTING_POWER_LIMIT_QUIET = 0,
> SMU_13_0_7_PMSETTING_POWER_LIMIT_BALANCE,
> SMU_13_0_7_PMSETTING_POWER_LIMIT_TURBO,
> @@ -144,8 +140,7 @@ enum SMU_13_0_7_PWRMODE_SETTING
> };
> #define SMU_13_0_7_MAX_PMSETTING 32 //Maximum Number of PowerMode
> Settings
>
> -struct smu_13_0_7_overdrive_table
> -{
> +struct smu_13_0_7_overdrive_table {
> uint8_t revision; //Revision =
> SMU_13_0_7_PP_OVERDRIVE_VERSION
> uint8_t reserve[3]; //Zero filled field
> reserved for future use
> uint32_t feature_count; //Total number of
> supported features
> @@ -156,8 +151,7 @@ struct smu_13_0_7_overdrive_table
> int16_t pm_setting[SMU_13_0_7_MAX_PMSETTING]; //Optimized power
> mode feature settings
> };
>
> -enum SMU_13_0_7_PPCLOCK_ID
> -{
> +enum SMU_13_0_7_PPCLOCK_ID {
> SMU_13_0_7_PPCLOCK_GFXCLK = 0,
> SMU_13_0_7_PPCLOCK_SOCCLK,
> SMU_13_0_7_PPCLOCK_UCLK,
> @@ -175,8 +169,7 @@ enum SMU_13_0_7_PPCLOCK_ID
> };
> #define SMU_13_0_7_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
>
> -struct smu_13_0_7_powerplay_table
> -{
> +struct smu_13_0_7_powerplay_table {
> struct atom_common_table_header header; //For PLUM_BONITO,
> header.format_revision = 15, header.content_revision = 0
> uint8_t table_revision; //For PLUM_BONITO,
> table_revision = 2
> uint8_t padding;
Re: [PATCH] drm/amd/pm: Clean up errors in smu_v13_0_1_pmfw.h
This doesn't apply cleanly.
Alex
On Mon, Jul 24, 2023 at 4:57 AM wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: trailing whitespace
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
> index c5e26d619bf0..8ec588248aac 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
> @@ -30,7 +30,7 @@
>
> #define ENABLE_DEBUG_FEATURES
>
> -// Firmware features
> +// Firmware features
> // Feature Control Defines
> #define FEATURE_CCLK_DPM_BIT 0
> #define FEATURE_FAN_CONTROLLER_BIT 1
> @@ -92,7 +92,7 @@
> #define FEATURE_ZSTATES_ECO_BIT 57
> #define FEATURE_CC6_BIT 58
> #define FEATURE_DS_UMCCLK_BIT 59
> -#define FEATURE_DS_HSPCLK_BIT 60
> +#define FEATURE_DS_HSPCLK_BIT 60
> #define NUM_FEATURES61
>
> typedef struct {
Re: [PATCH] drm/amd/pm: Clean up errors in smu_v11_0_7_pptable.h
This one doesn't apply cleanly.
Alex
On Mon, Jul 24, 2023 at 4:54 AM wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: trailing whitespace
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: Ran Sun
> ---
> .../amd/pm/swsmu/inc/smu_v11_0_7_pptable.h| 41 +--
> 1 file changed, 19 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> index 1cb399dbc7cc..64d60d48846a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> @@ -42,23 +42,23 @@
> #define SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION0x01
> // Power Saving Clock Table Version 1.00
>
> enum SMU_11_0_7_ODFEATURE_CAP {
> -SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0,
> -SMU_11_0_7_ODCAP_GFXCLK_CURVE,
> -SMU_11_0_7_ODCAP_UCLK_LIMITS,
> -SMU_11_0_7_ODCAP_POWER_LIMIT,
> -SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,
> -SMU_11_0_7_ODCAP_FAN_SPEED_MIN,
> -SMU_11_0_7_ODCAP_TEMPERATURE_FAN,
> -SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM,
> -SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE,
> -SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL,
> -SMU_11_0_7_ODCAP_AUTO_UV_ENGINE,
> -SMU_11_0_7_ODCAP_AUTO_OC_ENGINE,
> -SMU_11_0_7_ODCAP_AUTO_OC_MEMORY,
> +SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0,
> +SMU_11_0_7_ODCAP_GFXCLK_CURVE,
> +SMU_11_0_7_ODCAP_UCLK_LIMITS,
> +SMU_11_0_7_ODCAP_POWER_LIMIT,
> +SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,
> +SMU_11_0_7_ODCAP_FAN_SPEED_MIN,
> +SMU_11_0_7_ODCAP_TEMPERATURE_FAN,
> +SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM,
> +SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE,
> +SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL,
> +SMU_11_0_7_ODCAP_AUTO_UV_ENGINE,
> +SMU_11_0_7_ODCAP_AUTO_OC_ENGINE,
> +SMU_11_0_7_ODCAP_AUTO_OC_MEMORY,
> SMU_11_0_7_ODCAP_FAN_CURVE,
> SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,
> -SMU_11_0_7_ODCAP_POWER_MODE,
> -SMU_11_0_7_ODCAP_COUNT,
> +SMU_11_0_7_ODCAP_POWER_MODE,
> +SMU_11_0_7_ODCAP_COUNT,
> };
>
> enum SMU_11_0_7_ODFEATURE_ID {
> @@ -130,8 +130,7 @@ enum SMU_11_0_7_PWRMODE_SETTING {
> };
> #define SMU_11_0_7_MAX_PMSETTING 32//Maximum Number of
> PowerMode Settings
>
> -struct smu_11_0_7_overdrive_table
> -{
> +struct smu_11_0_7_overdrive_table {
> uint8_t revision;
> //Revision = SMU_11_0_7_PP_OVERDRIVE_VERSION
> uint8_t reserve[3]; //Zero
> filled field reserved for future use
> uint32_t feature_count; //Total
> number of supported features
> @@ -160,8 +159,7 @@ enum SMU_11_0_7_PPCLOCK_ID {
> };
> #define SMU_11_0_7_MAX_PPCLOCK 16 //Maximum Number of PP
> Clocks
>
> -struct smu_11_0_7_power_saving_clock_table
> -{
> +struct smu_11_0_7_power_saving_clock_table {
> uint8_t revision;
> //Revision = SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION
> uint8_t reserve[3]; //Zero
> filled field reserved for future use
> uint32_t count;
> //power_saving_clock_count = SMU_11_0_7_PPCLOCK_COUNT
> @@ -169,8 +167,7 @@ struct smu_11_0_7_power_saving_clock_table
> uint32_t min[SMU_11_0_7_MAX_PPCLOCK];
> //PowerSavingClock Mode Clock Minimum array In MHz
> };
>
> -struct smu_11_0_7_powerplay_table
> -{
> +struct smu_11_0_7_powerplay_table {
> struct atom_common_table_header header; //For
> sienna_cichlid, header.format_revision = 15, header.content_revision = 0
> uint8_t table_revision; //For
> sienna_cichlid, table_revision = 2
> uint16_t table_size; //Driver portion
> table size. The offset to smc_pptable including header size
> @@ -178,7 +175,7 @@ struct smu_11_0_7_powerplay_table
> uint32_t golden_revision; //PPGen use only:
> PP Table Revision on the Golden Data Base
> uint16_t format_id; //PPGen use only:
> PPTable for different ASICs. For sienna_cichlid this should be 0x80
> uint32_t platform_caps;
> //POWERPLAYABLE::ulPlatformCaps
> -
> +
> uint8_t thermal_controller_type; //one of
> SMU_11_0_7_PP_THERMALCONTROLLER
>
> uint16_t small_power_limit1;
Re: [PATCH] drm/amd/pm: open brace '{' following function definitions go on the next line
Applied. Thanks!
On Mon, Jul 24, 2023 at 4:44 AM wrote:
>
> ERROR: open brace '{' following function definitions go on the next line
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
> index c788aa7a99a9..5e408a195860 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
> @@ -205,7 +205,8 @@ int smu_v12_0_set_default_dpm_tables(struct
> smu_context *smu)
> return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
> smu_table->clocks_table, false);
> }
>
> -int smu_v12_0_mode2_reset(struct smu_context *smu){
> +int smu_v12_0_mode2_reset(struct smu_context *smu)
> +{
> return smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
> }
Re: [PATCH] drm/amd/pm: that open brace { should be on the previous line
Applied. Thanks!
On Mon, Jul 24, 2023 at 4:42 AM wrote:
>
> ERROR: that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_11_0_cdr_table.h | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_11_0_cdr_table.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_11_0_cdr_table.h
> index beab6d7b28b7..630132c4a76b 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_11_0_cdr_table.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_11_0_cdr_table.h
> @@ -52,8 +52,7 @@ static unsigned int DbiPrbs7[] =
>
>
> //4096 bytes, 256 byte aligned
> -static unsigned int NoDbiPrbs7[] =
> -{
> +static unsigned int NoDbiPrbs7[] = {
> 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f00f0f, 0x0f0f0f0f,
> 0x0f0f0f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f00f0f, 0xf0f00f0f,
> 0x0f0f0f0f, 0xf0f0f0f0, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f00f0f,
> 0x0f0f0f0f, 0xf0f00f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0,
> 0xf0f00f0f, 0xf0f00f0f, 0xf0f00f0f, 0x0f0ff0f0, 0xf0f0f0f0, 0xf0f0f0f0,
> 0x0f0ff0f0, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f0f0f0, 0xf0f00f0f,
> 0x0f0f0f0f, 0xf0f00f0f, 0x0f0ff0f0, 0x0f0f0f0f, 0xf0f0f0f0,
> 0x0f0ff0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf0f0f0f0, 0x0f0ff0f0, 0xf0f0f0f0,
> 0xf0f00f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0x0f0ff0f0, 0xf0f00f0f,
> @@ -121,8 +120,7 @@ static unsigned int NoDbiPrbs7[] =
> };
>
> // 4096 bytes, 256 byte aligned
> -static unsigned int DbiPrbs7[] =
> -{
> +static unsigned int DbiPrbs7[] = {
> 0x, 0x, 0x, 0x, 0x,
> 0x, 0x, 0x, 0x, 0x, 0x,
> 0x, 0x, 0x, 0x, 0x,
> 0x, 0x, 0x, 0x, 0x,
> 0x, 0x, 0x, 0x, 0x, 0x,
> 0x, 0x, 0x, 0x, 0x,
> 0x, 0x, 0x, 0x, 0x,
> 0x, 0x, 0x, 0x, 0x, 0x,
> 0x, 0x, 0x, 0x, 0x,
Re: [PATCH] drm/amd/pm: Clean up errors in smu11_driver_if_sienna_cichlid.h
This doesn't apply cleanly.
Alex
On Mon, Jul 24, 2023 at 4:34 AM wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: trailing whitespace
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
> index c5e26d619bf0..8ec588248aac 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
> @@ -30,7 +30,7 @@
>
> #define ENABLE_DEBUG_FEATURES
>
> -// Firmware features
> +// Firmware features
> // Feature Control Defines
> #define FEATURE_CCLK_DPM_BIT 0
> #define FEATURE_FAN_CONTROLLER_BIT 1
> @@ -92,7 +92,7 @@
> #define FEATURE_ZSTATES_ECO_BIT 57
> #define FEATURE_CC6_BIT 58
> #define FEATURE_DS_UMCCLK_BIT 59
> -#define FEATURE_DS_HSPCLK_BIT 60
> +#define FEATURE_DS_HSPCLK_BIT 60
> #define NUM_FEATURES61
>
> typedef struct {
Re: [PATCH] drm/amd/pm: Clean up errors in smu11_driver_if_sienna_cichlid.h
This doesn't apply cleanly.
Alex
On Mon, Jul 24, 2023 at 4:30 AM wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: trailing whitespace
> ERROR: space prohibited before open square bracket '['
> ERROR: space prohibited before that close square bracket ']'
>
> Signed-off-by: Ran Sun
> ---
> .../pmfw_if/smu11_driver_if_sienna_cichlid.h | 386 +-
> 1 file changed, 193 insertions(+), 193 deletions(-)
>
> diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> index aa6d29de4002..703ade13d9f4 100644
> ---
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> +++
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> @@ -225,33 +225,33 @@ typedef enum {
> #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6
> #define FW_DSTATE_SOC_LIV_MIN_BIT 7
> #define FW_DSTATE_SOC_PLL_PWRDN_BIT 8
> -#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9
> +#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9
> #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10
> #define FW_DSTATE_MEM_PSI_BIT 11
> #define FW_DSTATE_HSR_NON_STROBE_BIT12
> #define FW_DSTATE_MP0_ENTER_WFI_BIT 13
>
> -#define FW_DSTATE_SOC_ULV_MASK(1 <<
> FW_DSTATE_SOC_ULV_BIT )
> -#define FW_DSTATE_G6_HSR_MASK (1 <<
> FW_DSTATE_G6_HSR_BIT )
> -#define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 <<
> FW_DSTATE_G6_PHY_VDDCI_OFF_BIT )
> -#define FW_DSTATE_MP1_DS_MASK (1 <<
> FW_DSTATE_MP1_DS_BIT )
> -#define FW_DSTATE_MP0_DS_MASK (1 <<
> FW_DSTATE_MP0_DS_BIT )
> -#define FW_DSTATE_SMN_DS_MASK (1 <<
> FW_DSTATE_SMN_DS_BIT )
> -#define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 <<
> FW_DSTATE_MP1_WHISPER_MODE_BIT )
> -#define FW_DSTATE_SOC_LIV_MIN_MASK(1 <<
> FW_DSTATE_SOC_LIV_MIN_BIT )
> -#define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 <<
> FW_DSTATE_SOC_PLL_PWRDN_BIT)
> -#define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 <<
> FW_DSTATE_MEM_PLL_PWRDN_BIT)
> -#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 <<
> FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT)
> -#define FW_DSTATE_MEM_PSI_MASK(1 <<
> FW_DSTATE_MEM_PSI_BIT)
> -#define FW_DSTATE_HSR_NON_STROBE_MASK (1 <<
> FW_DSTATE_HSR_NON_STROBE_BIT)
> -#define FW_DSTATE_MP0_ENTER_WFI_MASK (1 <<
> FW_DSTATE_MP0_ENTER_WFI_BIT)
> +#define FW_DSTATE_SOC_ULV_MASK(1 <<
> FW_DSTATE_SOC_ULV_BIT)
> +#define FW_DSTATE_G6_HSR_MASK (1 <<
> FW_DSTATE_G6_HSR_BIT)
> +#define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 <<
> FW_DSTATE_G6_PHY_VDDCI_OFF_BIT)
> +#define FW_DSTATE_MP1_DS_MASK (1 <<
> FW_DSTATE_MP1_DS_BIT)
> +#define FW_DSTATE_MP0_DS_MASK (1 <<
> FW_DSTATE_MP0_DS_BIT)
> +#define FW_DSTATE_SMN_DS_MASK (1 <<
> FW_DSTATE_SMN_DS_BIT)
> +#define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 <<
> FW_DSTATE_MP1_WHISPER_MODE_BIT)
> +#define FW_DSTATE_SOC_LIV_MIN_MASK(1 <<
> FW_DSTATE_SOC_LIV_MIN_BIT)
> +#define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 <<
> FW_DSTATE_SOC_PLL_PWRDN_BIT)
> +#define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 <<
> FW_DSTATE_MEM_PLL_PWRDN_BIT)
> +#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 <<
> FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT)
> +#define FW_DSTATE_MEM_PSI_MASK(1 <<
> FW_DSTATE_MEM_PSI_BIT)
> +#define FW_DSTATE_HSR_NON_STROBE_MASK (1 <<
> FW_DSTATE_HSR_NON_STROBE_BIT)
> +#define FW_DSTATE_MP0_ENTER_WFI_MASK (1 <<
> FW_DSTATE_MP0_ENTER_WFI_BIT)
>
> // GFX GPO Feature Contains PACE and DEM sub features
> #define GFX_GPO_PACE_BIT 0
> #define GFX_GPO_DEM_BIT1
>
> #define GFX_GPO_PACE_MASK (1 << GFX_GPO_PACE_BIT)
> -#define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT )
> +#define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT)
>
> #define GPO_UPDATE_REQ_UCLKDPM_MASK 0x1
> #define GPO_UPDATE_REQ_FCLKDPM_MASK 0x2
> @@ -312,10 +312,10 @@ typedef enum {
> I2C_CONTROLLER_NAME_VR_VDDCI,
> I2C_CONTROLLER_NAME_VR_MVDD,
> I2C_CONTROLLER_NAME_LIQUID0,
> - I2C_CONTROLLER_NAME_LIQUID1,
> + I2C_CONTROLLER_NAME_LIQUID1,
> I2C_CONTROLLER_NAME_PLX,
> I2C_CONTROLLER_NAME_OTHER,
> - I2C_CONTROLLER_NAME_COUNT,
> + I2C_CONTROLLER_NAME_COUNT,
> } I2cControllerName_e;
>
> typedef enum {
> @@ -325,10 +325,10 @@ typedef enum {
> I2C_CONTROLLER_THROTTLER_VR_VDDCI,
> I2C_CONTROLLER_THROTTLER_VR_MVDD,
> I2C_CONTROLLER_THROTTLER_LIQUID0,
> - I2C_CONTROLLER_THROTTLER_LIQUID1,
> + I2C_CONTROLLER_THROTTLER_LIQUID1,
> I2C_CONTROLLER_THROTTLER_PLX,
>
Re: [PATCH] drm/amd/pm: Clean up errors in arcturus_ppt.c
Applied. Thanks!
On Mon, Jul 24, 2023 at 3:49 AM wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: "foo* bar" should be "foo *bar"
> ERROR: spaces required around that '=' (ctx:VxW)
> ERROR: space prohibited before that close parenthesis ')'
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> index 3ecb900e6ecd..b26e9ac1ac30 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> @@ -691,7 +691,7 @@ int smu_cmn_feature_set_enabled(struct smu_context
> *smu,
>
> #undef __SMU_DUMMY_MAP
> #define __SMU_DUMMY_MAP(fea) #fea
> -static const char* __smu_feature_names[] = {
> +static const char *__smu_feature_names[] = {
> SMU_FEATURE_MASKS
> };
>
> @@ -927,7 +927,7 @@ int smu_cmn_get_metrics_table(struct smu_context
> *smu,
> void *metrics_table,
> bool bypass_cache)
> {
> - struct smu_table_context *smu_table= &smu->smu_table;
> + struct smu_table_context *smu_table = &smu->smu_table;
> uint32_t table_size =
> smu_table->tables[SMU_TABLE_SMU_METRICS].size;
> int ret = 0;
> @@ -969,7 +969,7 @@ void smu_cmn_init_soft_gpu_metrics(void *table,
> uint8_t frev, uint8_t crev)
> struct metrics_table_header *header = (struct metrics_table_header
> *)table;
> uint16_t structure_size;
>
> -#define METRICS_VERSION(a, b) ((a << 16) | b )
> +#define METRICS_VERSION(a, b) ((a << 16) | b)
>
> switch (METRICS_VERSION(frev, crev)) {
> case METRICS_VERSION(1, 0):
Re: [PATCH] drm/amd/pm: Clean up errors in arcturus_ppt.c
Applied. thanks!
On Mon, Jul 24, 2023 at 3:32 AM wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: spaces required around that '=' (ctx:VxW)
> ERROR: spaces required around that '>=' (ctx:WxV)
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 3bb18396d2f9..c49f770c97b3 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -598,7 +598,7 @@ static int arcturus_get_smu_metrics_data(struct
> smu_context *smu,
> MetricsMember_t member,
> uint32_t *value)
> {
> - struct smu_table_context *smu_table= &smu->smu_table;
> + struct smu_table_context *smu_table = &smu->smu_table;
> SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
> int ret = 0;
>
> @@ -1482,7 +1482,7 @@ static int arcturus_set_power_profile_mode(struct
> smu_context *smu,
> return ret;
>
> if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
> -(smu_version >=0x360d00)) {
> +(smu_version >= 0x360d00)) {
> ret = smu_cmn_update_table(smu,
>SMU_TABLE_ACTIVITY_MONITOR_COEFF,
>WORKLOAD_PPLIB_CUSTOM_BIT,
Re: [PATCH] drm/amd/pm: Clean up errors in navi10_ppt.c
Applied. Thanks!
On Mon, Jul 24, 2023 at 3:21 AM wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: open brace '{' following function definitions go on the next line
> ERROR: space required before the open parenthesis '('
> ERROR: space required after that ',' (ctx:VxV)
> ERROR: spaces required around that '=' (ctx:VxW)
>
> Signed-off-by: Ran Sun
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 25 ++-
> 1 file changed, 13 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 95f6d821bacb..e655071516b7 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -136,7 +136,7 @@ static struct cmn2asic_msg_mapping
> navi10_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg,
> 0),
> MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME,
> 0),
> MSG_MAP(ArmD3, PPSMC_MSG_ArmD3,
> 0),
> -
> MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange,
> 0),
> + MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,
> PPSMC_MSG_DALDisableDummyPstateChange, 0),
>
> MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE,
> PPSMC_MSG_DALEnableDummyPstateChange, 0),
> MSG_MAP(GetVoltageByDpm,PPSMC_MSG_GetVoltageByDpm,
> 0),
>
> MSG_MAP(GetVoltageByDpmOverdrive,
> PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
> @@ -556,7 +556,7 @@ static int navi10_get_legacy_smu_metrics_data(struct
> smu_context *smu,
> MetricsMember_t member,
> uint32_t *value)
> {
> - struct smu_table_context *smu_table= &smu->smu_table;
> + struct smu_table_context *smu_table = &smu->smu_table;
> SmuMetrics_legacy_t *metrics =
> (SmuMetrics_legacy_t *)smu_table->metrics_table;
> int ret = 0;
> @@ -642,7 +642,7 @@ static int navi10_get_smu_metrics_data(struct
> smu_context *smu,
>MetricsMember_t member,
>uint32_t *value)
> {
> - struct smu_table_context *smu_table= &smu->smu_table;
> + struct smu_table_context *smu_table = &smu->smu_table;
> SmuMetrics_t *metrics =
> (SmuMetrics_t *)smu_table->metrics_table;
> int ret = 0;
> @@ -731,7 +731,7 @@ static int navi12_get_legacy_smu_metrics_data(struct
> smu_context *smu,
> MetricsMember_t member,
> uint32_t *value)
> {
> - struct smu_table_context *smu_table= &smu->smu_table;
> + struct smu_table_context *smu_table = &smu->smu_table;
> SmuMetrics_NV12_legacy_t *metrics =
> (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
> int ret = 0;
> @@ -817,7 +817,7 @@ static int navi12_get_smu_metrics_data(struct
> smu_context *smu,
>MetricsMember_t member,
>uint32_t *value)
> {
> - struct smu_table_context *smu_table= &smu->smu_table;
> + struct smu_table_context *smu_table = &smu->smu_table;
> SmuMetrics_NV12_t *metrics =
> (SmuMetrics_NV12_t *)smu_table->metrics_table;
> int ret = 0;
> @@ -1686,7 +1686,7 @@ static int navi10_force_clk_levels(struct
> smu_context *smu,
> return 0;
> break;
> case SMU_DCEFCLK:
> - dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is
> not
> supported!\n");
> + dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level
> is not
> supported!\n");
> break;
>
> default:
> @@ -2182,7 +2182,7 @@ static int navi10_read_sensor(struct smu_context
> *smu,
> struct smu_table_context *table_context = &smu->smu_table;
> PPTable_t *pptable = table_context->driver_pptable;
>
> - if(!data || !size)
> + if (!data || !size)
> return -EINVAL;
>
> switch (sensor) {
> @@ -2317,15 +2317,15 @@ static int
> navi10_display_disable_memory_clock_switch(struct smu_context *smu,
> uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
> uint32_t max_memory_clock = max_sustainable_clocks->uclock;
>
> - if(smu->disable_uclk_switch == disable_memory_clock_switch)
> + if (smu->disable_uclk_switch == disable_memory_clock_switch)
> return 0;
>
> - if(disable_memory_clock_switch)
> + if (disable_memory_clock_switch)
> ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK,
> max_memory_clock, 0);
> else
>
Re: [PATCH] drm/amd/pm: add missing spaces before '('
Applied. Thanks!
On Mon, Jul 24, 2023 at 3:02 AM wrote:
>
> ERROR: space required before the open parenthesis '('
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> index 8a8ba25c9ad7..a7569354229d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> @@ -262,15 +262,15 @@ static int renoir_get_profiling_clk_mask(struct
> smu_context *smu,
> /* mclk levels are in reverse order */
> *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
> } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
> - if(sclk_mask)
> + if (sclk_mask)
> /* The sclk as gfxclk and has three level about
> max/min/current */
> *sclk_mask = 3 - 1;
>
> - if(mclk_mask)
> + if (mclk_mask)
> /* mclk levels are in reverse order */
> *mclk_mask = 0;
>
> - if(soc_mask)
> + if (soc_mask)
> *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
> }
Re: [PATCH] drm/radeon: Move assignment outside if condition
Applied. Thanks!
On Sun, Jul 23, 2023 at 11:45 PM wrote:
>
> Fixes the following checkpatch errors:
>
> ERROR: do not use assignment in if condition
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/radeon/radeon_legacy_tv.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
> b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
> index 12e180b119ac..7883e9ec0bae 100644
> --- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
> +++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
> @@ -724,12 +724,14 @@ void radeon_legacy_tv_mode_set(struct drm_encoder
> *encoder,
> }
>
> for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) {
> - if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0)
> + tv_dac->tv.h_code_timing[i] = hor_timing[i];
> + if (tv_dac->tv.h_code_timing[i] == 0)
> break;
> }
>
> for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) {
> - if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0)
> + tv_dac->tv.v_code_timing[i] = vert_timing[i];
> + if (tv_dac->tv.v_code_timing[i] == 0)
> break;
> }
Re: [PATCH] drm/radeon: that open brace { should be on the previous line
Applied. thanks!
Alex
On Sun, Jul 23, 2023 at 11:40 PM wrote:
>
> ERROR: that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/radeon/rv770_smc.c | 36 ++
> 1 file changed, 12 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/rv770_smc.c
> b/drivers/gpu/drm/radeon/rv770_smc.c
> index 45575c0d0a1d..09fa7f5e7c41 100644
> --- a/drivers/gpu/drm/radeon/rv770_smc.c
> +++ b/drivers/gpu/drm/radeon/rv770_smc.c
> @@ -34,8 +34,7 @@
> #define FIRST_SMC_INT_VECT_REG 0xFFD8
> #define FIRST_INT_VECT_S19 0xFFC0
>
> -static const u8 rv770_smc_int_vectors[] =
> -{
> +static const u8 rv770_smc_int_vectors[] = {
> 0x08, 0x10, 0x08, 0x10,
> 0x08, 0x10, 0x08, 0x10,
> 0x08, 0x10, 0x08, 0x10,
> @@ -54,8 +53,7 @@ static const u8 rv770_smc_int_vectors[] =
> 0x03, 0x51, 0x03, 0x51
> };
>
> -static const u8 rv730_smc_int_vectors[] =
> -{
> +static const u8 rv730_smc_int_vectors[] = {
> 0x08, 0x15, 0x08, 0x15,
> 0x08, 0x15, 0x08, 0x15,
> 0x08, 0x15, 0x08, 0x15,
> @@ -74,8 +72,7 @@ static const u8 rv730_smc_int_vectors[] =
> 0x03, 0x56, 0x03, 0x56
> };
>
> -static const u8 rv710_smc_int_vectors[] =
> -{
> +static const u8 rv710_smc_int_vectors[] = {
> 0x08, 0x04, 0x08, 0x04,
> 0x08, 0x04, 0x08, 0x04,
> 0x08, 0x04, 0x08, 0x04,
> @@ -94,8 +91,7 @@ static const u8 rv710_smc_int_vectors[] =
> 0x03, 0x51, 0x03, 0x51
> };
>
> -static const u8 rv740_smc_int_vectors[] =
> -{
> +static const u8 rv740_smc_int_vectors[] = {
> 0x08, 0x10, 0x08, 0x10,
> 0x08, 0x10, 0x08, 0x10,
> 0x08, 0x10, 0x08, 0x10,
> @@ -114,8 +110,7 @@ static const u8 rv740_smc_int_vectors[] =
> 0x03, 0x51, 0x03, 0x51
> };
>
> -static const u8 cedar_smc_int_vectors[] =
> -{
> +static const u8 cedar_smc_int_vectors[] = {
> 0x0B, 0x05, 0x0B, 0x05,
> 0x0B, 0x05, 0x0B, 0x05,
> 0x0B, 0x05, 0x0B, 0x05,
> @@ -134,8 +129,7 @@ static const u8 cedar_smc_int_vectors[] =
> 0x04, 0xF6, 0x04, 0xF6
> };
>
> -static const u8 redwood_smc_int_vectors[] =
> -{
> +static const u8 redwood_smc_int_vectors[] = {
> 0x0B, 0x05, 0x0B, 0x05,
> 0x0B, 0x05, 0x0B, 0x05,
> 0x0B, 0x05, 0x0B, 0x05,
> @@ -154,8 +148,7 @@ static const u8 redwood_smc_int_vectors[] =
> 0x04, 0xF6, 0x04, 0xF6
> };
>
> -static const u8 juniper_smc_int_vectors[] =
> -{
> +static const u8 juniper_smc_int_vectors[] = {
> 0x0B, 0x05, 0x0B, 0x05,
> 0x0B, 0x05, 0x0B, 0x05,
> 0x0B, 0x05, 0x0B, 0x05,
> @@ -174,8 +167,7 @@ static const u8 juniper_smc_int_vectors[] =
> 0x04, 0xF6, 0x04, 0xF6
> };
>
> -static const u8 cypress_smc_int_vectors[] =
> -{
> +static const u8 cypress_smc_int_vectors[] = {
> 0x0B, 0x05, 0x0B, 0x05,
> 0x0B, 0x05, 0x0B, 0x05,
> 0x0B, 0x05, 0x0B, 0x05,
> @@ -194,8 +186,7 @@ static const u8 cypress_smc_int_vectors[] =
> 0x04, 0xF6, 0x04, 0xF6
> };
>
> -static const u8 barts_smc_int_vectors[] =
> -{
> +static const u8 barts_smc_int_vectors[] = {
> 0x0C, 0x14, 0x0C, 0x14,
> 0x0C, 0x14, 0x0C, 0x14,
> 0x0C, 0x14, 0x0C, 0x14,
> @@ -214,8 +205,7 @@ static const u8 barts_smc_int_vectors[] =
> 0x05, 0x0A, 0x05, 0x0A
> };
>
> -static const u8 turks_smc_int_vectors[] =
> -{
> +static const u8 turks_smc_int_vectors[] = {
> 0x0C, 0x14, 0x0C, 0x14,
> 0x0C, 0x14, 0x0C, 0x14,
> 0x0C, 0x14, 0x0C, 0x14,
> @@ -234,8 +224,7 @@ static const u8 turks_smc_int_vectors[] =
> 0x05, 0x0A, 0x05, 0x0A
> };
>
> -static const u8 caicos_smc_int_vectors[] =
> -{
> +static const u8 caicos_smc_int_vectors[] = {
> 0x0C, 0x14, 0x0C, 0x14,
> 0x0C, 0x14, 0x0C, 0x14,
> 0x0C, 0x14, 0x0C, 0x14,
> @@ -254,8 +243,7 @@ static const u8 caicos_smc_int_vectors[] =
> 0x05, 0x0A, 0x05, 0x0A
> };
>
> -static const u8 cayman_smc_int_vectors[] =
> -{
> +static const u8 cayman_smc_int_vectors[] = {
> 0x12, 0x05, 0x12, 0x05,
> 0x12, 0x05, 0x12, 0x05,
> 0x12, 0x05, 0x12, 0x05,
Re: [PATCH] drm/radeon: that open brace { should be on the previous line
Applied. Thanks!
On Sun, Jul 23, 2023 at 11:37 PM wrote:
>
> ERROR: that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/radeon/clearstate_si.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/clearstate_si.h
> b/drivers/gpu/drm/radeon/clearstate_si.h
> index 356219c6c7f2..7da8418704fe 100644
> --- a/drivers/gpu/drm/radeon/clearstate_si.h
> +++ b/drivers/gpu/drm/radeon/clearstate_si.h
> @@ -23,8 +23,7 @@
>
> #include "clearstate_defs.h"
>
> -static const u32 si_SECT_CONTEXT_def_1[] =
> -{
> +static const u32 si_SECT_CONTEXT_def_1[] = {
> 0x, // DB_RENDER_CONTROL
> 0x, // DB_COUNT_CONTROL
> 0x, // DB_DEPTH_VIEW
Re: [PATCH] drm/radeon: add missing spaces after ', ' and else should follow close brace '}'
Applied. Thanks!
Alex
On Sun, Jul 23, 2023 at 11:30 PM wrote:
>
> ERROR: else should follow close brace '}'
>
> ERROR: space required after that ',' (ctx:VxV)
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/radeon/radeon_connectors.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
> b/drivers/gpu/drm/radeon/radeon_connectors.c
> index 07193cd0c417..4ceceb972e8d 100644
> --- a/drivers/gpu/drm/radeon/radeon_connectors.c
> +++ b/drivers/gpu/drm/radeon/radeon_connectors.c
> @@ -198,8 +198,7 @@ int radeon_get_monitor_bpc(struct drm_connector
> *connector)
> DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds
> max tmds clock. Using
> %d bpc.\n",
> connector->name, bpc);
> }
> - }
> - else if (bpc > 8) {
> + } else if (bpc > 8) {
> /* max_tmds_clock missing, but hdmi spec mandates it
> for deep color.
> */
> DRM_DEBUG("%s: Required max tmds clock for HDMI deep
> color missing.
> Using 8 bpc.\n",
> connector->name);
> @@ -1372,7 +1371,7 @@ radeon_dvi_detect(struct drm_connector *connector,
> bool force)
> /* assume digital unless load
> detected otherwise */
> radeon_connector->use_digital = true;
> lret = encoder_funcs->detect(encoder,
> connector);
> - DRM_DEBUG_KMS("load_detect %x
> returned:
> %x\n",encoder->encoder_type,lret);
> + DRM_DEBUG_KMS("load_detect %x
> returned: %x\n",
> encoder->encoder_type, lret);
> if (lret ==
> connector_status_connected)
> radeon_connector->use_digital
> = false;
> }
Re: [PATCH] drm/radeon: that open brace { should be on the previous line
On Sun, Jul 23, 2023 at 11:12 PM wrote:
>
> ERROR: that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/radeon/ni_dpm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/ni_dpm.c
> b/drivers/gpu/drm/radeon/ni_dpm.c
> index a101ba00ea30..1cf4de4cda23 100644
> --- a/drivers/gpu/drm/radeon/ni_dpm.c
> +++ b/drivers/gpu/drm/radeon/ni_dpm.c
> @@ -625,7 +625,7 @@ static const u32 cayman_mgcg_disable[] =
> };
> #define CAYMAN_MGCG_DISABLE_LENGTH sizeof(cayman_mgcg_disable) / (3 *
> sizeof(u32))
>
> -static const u32 cayman_mgcg_enable[] = :621 {
> +static const u32 cayman_mgcg_enable[] = : 621 {
Something weird here.
Alex
> 0x802c, 0xc000, 0x,
> 0x08f8, 0x, 0x,
> 0x08fc, 0x, 0x,
Re: [PATCH] drm/radeon: add missing spaces before ';'
Applied. Thanks! On Sun, Jul 23, 2023 at 11:00 PM wrote: > > ERROR: space required after that ';' (ctx:BxV) > > Signed-off-by: Ran Sun > --- > drivers/gpu/drm/radeon/radeon_vce.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/radeon_vce.c > b/drivers/gpu/drm/radeon/radeon_vce.c > index ca4a36464340..d1871af967d4 100644 > --- a/drivers/gpu/drm/radeon/radeon_vce.c > +++ b/drivers/gpu/drm/radeon/radeon_vce.c > @@ -95,7 +95,7 @@ int radeon_vce_init(struct radeon_device *rdev) > > size = rdev->vce_fw->size - strlen(fw_version) - 9; > c = rdev->vce_fw->data; > - for (;size > 0; --size, ++c) > + for (; size > 0; --size, ++c) > if (strncmp(c, fw_version, strlen(fw_version)) == 0) > break; > > @@ -110,7 +110,7 @@ int radeon_vce_init(struct radeon_device *rdev) > > size = rdev->vce_fw->size - strlen(fb_version) - 3; > c = rdev->vce_fw->data; > - for (;size > 0; --size, ++c) > + for (; size > 0; --size, ++c) > if (strncmp(c, fb_version, strlen(fb_version)) == 0) > break;
Re: [PATCH] drm/radeon/si_dpm: open brace '{' following struct go on the same line
Applied. Thanks.
Alex
On Sun, Jul 23, 2023 at 10:55 PM wrote:
>
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: Ran Sun
> ---
> drivers/gpu/drm/radeon/sislands_smc.h | 51 +--
> 1 file changed, 17 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/sislands_smc.h
> b/drivers/gpu/drm/radeon/sislands_smc.h
> index 4ea1cb2e45a3..4b7dee3cf58b 100644
> --- a/drivers/gpu/drm/radeon/sislands_smc.h
> +++ b/drivers/gpu/drm/radeon/sislands_smc.h
> @@ -89,8 +89,7 @@ struct PP_SIslands_PAPMStatus
> };
> typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
>
> -struct PP_SIslands_PAPMParameters
> -{
> +struct PP_SIslands_PAPMParameters {
> uint32_tNearTDPLimitTherm;
> uint32_tNearTDPLimitPAPM;
> uint32_tPlatformPowerLimit;
> @@ -100,8 +99,7 @@ struct PP_SIslands_PAPMParameters
> };
> typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
>
> -struct SISLANDS_SMC_SCLK_VALUE
> -{
> +struct SISLANDS_SMC_SCLK_VALUE {
> uint32_tvCG_SPLL_FUNC_CNTL;
> uint32_tvCG_SPLL_FUNC_CNTL_2;
> uint32_tvCG_SPLL_FUNC_CNTL_3;
> @@ -113,8 +111,7 @@ struct SISLANDS_SMC_SCLK_VALUE
>
> typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
>
> -struct SISLANDS_SMC_MCLK_VALUE
> -{
> +struct SISLANDS_SMC_MCLK_VALUE {
> uint32_tvMPLL_FUNC_CNTL;
> uint32_tvMPLL_FUNC_CNTL_1;
> uint32_tvMPLL_FUNC_CNTL_2;
> @@ -129,8 +126,7 @@ struct SISLANDS_SMC_MCLK_VALUE
>
> typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
>
> -struct SISLANDS_SMC_VOLTAGE_VALUE
> -{
> +struct SISLANDS_SMC_VOLTAGE_VALUE {
> uint16_tvalue;
> uint8_t index;
> uint8_t phase_settings;
> @@ -138,8 +134,7 @@ struct SISLANDS_SMC_VOLTAGE_VALUE
>
> typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
>
> -struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
> -{
> +struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL {
> uint8_t ACIndex;
> uint8_t displayWatermark;
> uint8_t gen2PCIE;
> @@ -180,8 +175,7 @@ struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
>
> typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
> SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
>
> -struct SISLANDS_SMC_SWSTATE
> -{
> +struct SISLANDS_SMC_SWSTATE {
> uint8_t flags;
> uint8_t levelCount;
> uint8_t padding2;
> @@ -205,8 +199,7 @@ struct SISLANDS_SMC_SWSTATE_SINGLE {
> #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3
> #define SISLANDS_SMC_VOLTAGEMASK_MAX 4
>
> -struct SISLANDS_SMC_VOLTAGEMASKTABLE
> -{
> +struct SISLANDS_SMC_VOLTAGEMASKTABLE {
> uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
> };
>
> @@ -214,8 +207,7 @@ typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE
> SISLANDS_SMC_VOLTAGEMASKTABLE;
>
> #define SISLANDS_MAX_NO_VREG_STEPS 32
>
> -struct SISLANDS_SMC_STATETABLE
> -{
> +struct SISLANDS_SMC_STATETABLE {
> uint8_t thermalProtectType;
> uint8_t systemFlags;
> uint8_t maxVDDCIndexInPPTable;
> @@ -254,8 +246,7 @@ typedef struct SISLANDS_SMC_STATETABLE
> SISLANDS_SMC_STATETABLE;
> #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c
> #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120
>
> -struct PP_SIslands_FanTable
> -{
> +struct PP_SIslands_FanTable {
> uint8_t fdo_mode;
> uint8_t padding;
> int16_t temp_min;
> @@ -285,8 +276,7 @@ typedef struct PP_SIslands_FanTable
> PP_SIslands_FanTable;
> #define SMC_SISLANDS_SCALE_I 7
> #define SMC_SISLANDS_SCALE_R 12
>
> -struct PP_SIslands_CacConfig
> -{
> +struct PP_SIslands_CacConfig {
> uint16_t
> cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
> uint32_t lkge_lut_V0;
> uint32_t lkge_lut_Vstep;
> @@ -308,23 +298,20 @@ typedef struct PP_SIslands_CacConfig
> PP_SIslands_CacConfig;
> #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
> #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
>
> -struct SMC_SIslands_MCRegisterAddress
> -{
> +struct SMC_SIslands_MCRegisterAddress {
> uint16_t s0;
> uint16_t s1;
> };
>
> typedef struct SMC_SIslands_MCRegisterAddress
> SMC_SIslands_MCRegisterAddress;
>
> -struct SMC_SIslands_MCRegisterSet
> -{
> +struct SMC_SIslands_MCRegisterSet {
> uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
> };
>
> typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
>
> -struct SMC_SIslands_MCRegisters
> -{
> +struct SMC_SIslands_MCRegisters {
> uint8_t last;
> uint8_t reserved[3];
> SMC_SIslands_MCRegisterAddress
> address[SMC_SISLANDS_MC_REGISTER_AR
Re: [PATCH] drm/amdgpu: Use seq_puts() instead of seq_printf()
On Sun, Jul 23, 2023 at 2:51 AM Srinivasan Shanmugam
wrote:
>
> For a constant format without additional arguments, use seq_puts()
> instead of seq_printf(). Also, it fixes the following warning.
>
> WARNING: Prefer seq_puts to seq_printf
>
> And other style fixes:
>
> WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
> WARNING: Block comments should align the * on each line
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 22 +++---
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index e0d3e3aa2e31..0cbaf78e8828 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -62,7 +62,7 @@
> * Returns 0 on success, error on failure.
> */
> int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> - unsigned size, enum amdgpu_ib_pool_type pool_type,
> + unsigned int size, enum amdgpu_ib_pool_type pool_type,
> struct amdgpu_ib *ib)
> {
> int r;
> @@ -123,7 +123,7 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct
> amdgpu_ib *ib,
> * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
> * to SI there was just a DE IB.
> */
> -int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
> +int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
>struct amdgpu_ib *ibs, struct amdgpu_job *job,
>struct dma_fence **f)
> {
> @@ -131,16 +131,16 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring,
> unsigned num_ibs,
> struct amdgpu_ib *ib = &ibs[0];
> struct dma_fence *tmp = NULL;
> bool need_ctx_switch;
> - unsigned patch_offset = ~0;
> + unsigned int patch_offset = ~0;
> struct amdgpu_vm *vm;
> uint64_t fence_ctx;
> uint32_t status = 0, alloc_size;
> - unsigned fence_flags = 0;
> + unsigned int fence_flags = 0;
> bool secure, init_shadow;
> u64 shadow_va, csa_va, gds_va;
> int vmid = AMDGPU_JOB_GET_VMID(job);
>
> - unsigned i;
> + unsigned int i;
> int r = 0;
> bool need_pipe_sync = false;
>
> @@ -282,7 +282,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
> num_ibs,
> amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0);
>
> if (ring->funcs->init_cond_exec) {
> - unsigned ce_offset = ~0;
> + unsigned int ce_offset = ~0;
>
> ce_offset = amdgpu_ring_init_cond_exec(ring);
> if (ce_offset != ~0 && ring->funcs->patch_cond_exec)
> @@ -386,7 +386,7 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
> {
> long tmo_gfx, tmo_mm;
> int r, ret = 0;
> - unsigned i;
> + unsigned int i;
>
> tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT;
> if (amdgpu_sriov_vf(adev)) {
> @@ -403,7 +403,7 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
> /* for CP & SDMA engines since they are scheduled together so
> * need to make the timeout width enough to cover the time
> * cost waiting for it coming back under RUNTIME only
> - */
> +*/
> tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT;
> } else if (adev->gmc.xgmi.hive_id) {
> tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT;
> @@ -466,13 +466,13 @@ static int amdgpu_debugfs_sa_info_show(struct seq_file
> *m, void *unused)
> {
> struct amdgpu_device *adev = m->private;
>
> - seq_printf(m, "- DELAYED -
> \n");
> + seq_puts(m, "- DELAYED -\n");
> amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DELAYED],
> m);
> - seq_printf(m, " IMMEDIATE
> \n");
> + seq_puts(m, " IMMEDIATE \n");
>
> amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_IMMEDIATE],
> m);
> - seq_printf(m, "- DIRECT --
> \n");
> + seq_puts(m, "- DIRECT --\n");
> amdgpu_sa_bo_dump_debug_info(&adev->ib_pools[AMDGPU_IB_POOL_DIRECT],
> m);
>
> return 0;
> --
> 2.25.1
>
[PATCH 1/3] drm/amdgpu: add ih 6.1 registers
From: benl Add new registers. v2: updates (Alex) Signed-off-by: Ben Li Signed-off-by: Alex Deucher --- .../asic_reg/oss/osssys_6_1_0_offset.h| 279 + .../asic_reg/oss/osssys_6_1_0_sh_mask.h | 1019 + 2 files changed, 1298 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_1_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_1_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_1_0_offset.h new file mode 100644 index 0..a5e7ba5d99caf --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_1_0_offset.h @@ -0,0 +1,279 @@ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _osssys_6_1_0_OFFSET_HEADER +#define _osssys_6_1_0_OFFSET_HEADER + + + +// addressBlock: osssys_osssysdec +// base address: 0x4280 +#define regIH_VMID_0_LUT 0x +#define regIH_VMID_0_LUT_BASE_IDX 0 +#define regIH_VMID_1_LUT 0x0001 +#define regIH_VMID_1_LUT_BASE_IDX 0 +#define regIH_VMID_2_LUT 0x0002 +#define regIH_VMID_2_LUT_BASE_IDX 0 +#define regIH_VMID_3_LUT 0x0003 +#define regIH_VMID_3_LUT_BASE_IDX 0 +#define regIH_VMID_4_LUT 0x0004 +#define regIH_VMID_4_LUT_BASE_IDX 0 +#define regIH_VMID_5_LUT 0x0005 +#define regIH_VMID_5_LUT_BASE_IDX 0 +#define regIH_VMID_6_LUT 0x0006 +#define regIH_VMID_6_LUT_BASE_IDX 0 +#define regIH_VMID_7_LUT 0x0007 +#define regIH_VMID_7_LUT_BASE_IDX 0 +#define regIH_VMID_8_LUT 0x0008 +#define regIH_VMID_8_LUT_BASE_IDX 0 +#define regIH_VMID_9_LUT 0x0009 +#define regIH_VMID_9_LUT_BASE_IDX 0 +#define regIH_VMID_10_LUT 0x000a +#define regIH_VMID_10_LUT_BASE_IDX 0 +#define regIH_VMID_11_LUT 0x000b +#define regIH_VMID_11_LUT_BASE_IDX 0 +#define regIH_VMID_12_LUT 0x000c +#define regIH_VMID_12_LUT_BASE_IDX 0 +#define regIH_VMID_13_LUT
[PATCH 2/3] drm/amdgpu: add ih 6.1 support
From: benl
Add initial support for IH 6.1.
Signed-off-by: benl
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 769 +++
drivers/gpu/drm/amd/amdgpu/ih_v6_1.h | 28 +
3 files changed, 799 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/ih_v6_1.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 29325981778a0..384b798a9bad1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -129,7 +129,8 @@ amdgpu-y += \
vega10_ih.o \
vega20_ih.o \
navi10_ih.o \
- ih_v6_0.o
+ ih_v6_0.o \
+ ih_v6_1.o
# add PSP block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
new file mode 100644
index 0..5795a66ccbc5d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -0,0 +1,769 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include
+
+#include "amdgpu.h"
+#include "amdgpu_ih.h"
+
+#include "oss/osssys_6_1_0_offset.h"
+#include "oss/osssys_6_1_0_sh_mask.h"
+
+#include "soc15_common.h"
+#include "ih_v6_1.h"
+
+#define MAX_REARM_RETRY 10
+
+static void ih_v6_1_set_interrupt_funcs(struct amdgpu_device *adev);
+
+/**
+ * ih_v6_1_init_register_offset - Initialize register offset for ih rings
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Initialize register offset ih rings (IH_V6_0).
+ */
+static void ih_v6_1_init_register_offset(struct amdgpu_device *adev)
+{
+ struct amdgpu_ih_regs *ih_regs;
+
+ /* ih ring 2 is removed
+* ih ring and ih ring 1 are available */
+ if (adev->irq.ih.ring_size) {
+ ih_regs = &adev->irq.ih.ih_regs;
+ ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_BASE);
+ ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_BASE_HI);
+ ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_CNTL);
+ ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_WPTR);
+ ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_RPTR);
+ ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_DOORBELL_RPTR);
+ ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_WPTR_ADDR_LO);
+ ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_WPTR_ADDR_HI);
+ ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
+ }
+
+ if (adev->irq.ih1.ring_size) {
+ ih_regs = &adev->irq.ih1.ih_regs;
+ ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_BASE_RING1);
+ ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_BASE_HI_RING1);
+ ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_CNTL_RING1);
+ ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_WPTR_RING1);
+ ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_RB_RPTR_RING1);
+ ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0,
regIH_DOORBELL_RPTR_RING1);
+ ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
+ }
+}
+
+/**
+ * force_update_wptr_for_self_int - Force update the wptr for self interrupt
+ *
+ * @adev: amdgpu_device pointer
+ * @threshold: threshold to trigger the wptr reporting
+ * @timeout: timeout to trigger the wptr reporting
+ * @enabled: Enable/disable timeout flush mechanism
+ *
+ * threshold input range: 0 ~ 15, default 0,
+ * real_threshold = 2^threshold
+ * timeout input range: 0 ~ 20, default 8,
+ * real_timeout = (2^timeout) * 1024 / (socclk_freq)
+ *
+ * Force update wptr for self interrupt ( >= SIENNA_CICHLI
[PATCH 3/3] drm/amdgpu/discovery: add ih 6.1.0 support
From: Prike Liang Add to IP discovery table. Signed-off-by: Prike Liang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 59ed6d4ebfed0..9d8d08daca57a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -65,6 +65,7 @@ #include "soc21.h" #include "navi10_ih.h" #include "ih_v6_0.h" +#include "ih_v6_1.h" #include "gfx_v10_0.h" #include "gfx_v11_0.h" #include "sdma_v5_0.h" @@ -1702,6 +1703,9 @@ static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(6, 0, 2): amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); break; + case IP_VERSION(6, 1, 0): + amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); + break; default: dev_err(adev->dev, "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", -- 2.41.0
Re: [PATCH 28/29] drm/amdkfd: Refactor migrate init to support partition switch
Hi Michel,
Please check if this patch "drm/amdkfd: start_cpsch don't map
queues" can fix the driver loading ring test failed issue on your
system, I am still not able to repro the issue.
Regards,
Philip
On 2023-07-21 09:30, Philip Yang wrote:
On 2023-07-21 04:55, Michel Dänzer
wrote:
On 7/20/23 22:48, Philip Yang wrote:
On 2023-07-20 06:46, Michel Dänzer wrote:
On 7/17/23 15:09, Michel Dänzer wrote:
On 5/10/23 23:23, Alex Deucher wrote:
From: Philip Yang
Rename smv_migrate_init to a better name kgd2kfd_init_zone_device
because it setup zone devive pgmap for page migration and keep it in
kfd_migrate.c to access static functions svm_migrate_pgmap_ops. Call it
only once in amdgpu_device_ip_init after adev ip blocks are initialized,
but before amdgpu_amdkfd_device_init initialize kfd nodes which enable
SVM support based on pgmap.
svm_range_set_max_pages is called by kgd2kfd_device_init everytime after
switching compute partition mode.
Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
I bisected a regression to this commit, which broke HW acceleration on this ThinkPad E595 with Picasso APU.
Actually, it doesn't seem to break HW acceleration completely. GDM eventually comes up with HW acceleration, it takes a long time (~30s or so) to start up though.
Later, the same messages as described in https://gitlab.freedesktop.org/drm/amd/-/issues/2659 appear.
Reverting this commit fixes all of the above symptoms.
I reproduced all of the above symptoms with amd-staging-drm-next commit 75515acf4b60 ("i2c: nvidia-gpu: Add ACPI property to align with device-tree") as well.
For full disclosure, I use these kernel command line arguments:
fbcon=font:10x18 drm_kms_helper.drm_fbdev_overalloc=112 amdgpu.noretry=1 amdgpu.mcbp=1
Thanks for the issue report and full disclosure, but I am not able to reproduce this issue, with both drm-next branch and amd-staging-drm-next branch tip on gitlab. The test system has same device id, running Ubuntu 22.04, latest linux-firmware-20230625.tar.gz, and same BIOS version.
FWIW, your system has PCI revision ID 0xC2, while mine has 0xC1.
Also, I'm currently using linux-firmware 20230515. AFAICT there are no relevant changes in 20230625, but I'm attaching the contents of /sys/kernel/debug/dri/0/amdgpu_firmware_info just in case.
I attached full dmesg log, could you help check if there is other difference, maybe kernel config, gcc version... it is hard to guess what could cause the basic driver gfx ring IB test timeout.
I suspect the IOMMU page faults logged in my dmesg might be relevant:
amdgpu: Topology: Add APU node [0x15d8:0x1002]
amdgpu :05:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x address=0x122201800 flags=0x0070]
amdgpu :05:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x address=0x1125fe380 flags=0x0070]
kfd kfd: amdgpu: added device 1002:15d8
There are no such page faults with the commit reverted.
Other than that and the IB test failure messages, our dmesg outputs are mostly identical indeed.
Yes, I don't have IO_PAGE_FAULT message on my system, thanks
for the finding, I will continue investigating the root cause.
You are right, the error message could cause gfx ring IB test
timeout failure, this patch does change the order of driver
memory allocation. IOMMU is in translation mode on Ubuntu
config.
To help confirm if this is caused by IOMMU, please add this to
kernel boot option to set IOMMU to passthrough mode, check if
this can workaround the issue
iommu=pt
Regards,
Philip
Re: [PATCH] drm/amdkfd: start_cpsch don't map queues
On 2023-07-24 13:52, Philip Yang wrote:
start_cpsch map queues when kfd_init_node have race condition with
IOMMUv2 init, and cause the gfx ring test failed later. Remove it
from start_cpsch because map queues will be done when creating queues
and resume queues.
Reported-by: Michel Dänzer
Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
Michel, can you test whether this fixes your regression on Raven? Would
be good to get a Tested-by for this patch, since we haven't been able to
reproduce the problem yet.
Thanks,
Felix
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 71b7f16c0173..a2d0d0bcf853 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1658,9 +1658,6 @@ static int start_cpsch(struct device_queue_manager *dqm)
dqm->is_resetting = false;
dqm->sched_running = true;
- if (!dqm->dev->kfd->shared_resources.enable_mes)
- execute_queues_cpsch(dqm,
KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
-
/* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU */
if (amdgpu_emu_mode == 0 && dqm->dev->adev->gmc.is_app_apu &&
(KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 3))) {
[PATCH] drm/amdgpu/discovery: add hdp 6.1.0 support
From: Prike Liang Add to IP discovery table. Signed-off-by: Prike Liang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 910eb9ffb802d..59ed6d4ebfed0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2447,6 +2447,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) break; case IP_VERSION(6, 0, 0): case IP_VERSION(6, 0, 1): + case IP_VERSION(6, 1, 0): adev->hdp.funcs = &hdp_v6_0_funcs; break; default: -- 2.41.0
Re: [PATCH] drm/amdgpu: Checkpoint and Restore VRAM BOs without VA
On 2023-07-24 11:57, Ramesh Errabolu wrote:
Extend checkpoint logic to allow inclusion of VRAM BOs that
do not have a VA attached
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 40ac093b5035..5cc00ff4b635 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1845,7 +1845,8 @@ static uint32_t get_process_num_bos(struct kfd_process *p)
idr_for_each_entry(&pdd->alloc_idr, mem, id) {
struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
- if ((uint64_t)kgd_mem->va > pdd->gpuvm_base)
+ if (((uint64_t)kgd_mem->va > pdd->gpuvm_base) ||
+ (kgd_mem->va == 0))
I'm trying to remember what this condition is there to protect against,
because it almost looks like we could drop the entire condition. I think
it's there to avoid checkpointing the TMA/TBA BOs allocated by KFD itself.
That said, you have some unnecessary parentheses in this expression. And
just using !x to check for 0 is usually preferred in the kernel. This
should work and is more readable IMO:
+ if ((uint64_t)kgd_mem->va > pdd->gpuvm_base ||
!kgd_mem->va)
num_of_bos++;
}
}
@@ -1917,7 +1918,8 @@ static int criu_checkpoint_bos(struct kfd_process *p,
kgd_mem = (struct kgd_mem *)mem;
dumper_bo = kgd_mem->bo;
- if ((uint64_t)kgd_mem->va <= pdd->gpuvm_base)
+ if (((uint64_t)kgd_mem->va <= pdd->gpuvm_base) &&
+ !(kgd_mem->va == 0))
Similar to above:
+ if (kgd_mem->va && (uint64_t)kgd_mem->va <=
pdd->gpuvm_base)
Regards,
Felix
continue;
bo_bucket = &bo_buckets[bo_index];
[PATCH 1/2] drm/amdgpu/sdma6: initialize sdma 6.1.0
From: Prike Liang
Add firmware declaration.
Signed-off-by: Prike Liang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 3b03dda854fdc..45be0af2570b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -48,6 +48,7 @@ MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
+MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin");
#define SDMA1_REG_OFFSET 0x600
#define SDMA0_HYP_DEC_REG_START 0x5880
--
2.41.0
[PATCH 2/2] drm/amdgpu/discovery: enable sdma6 for SDMA 6.1.0
From: Prike Liang Add to IP discovery table. Signed-off-by: Prike Liang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index f2b95c38ac3d9..910eb9ffb802d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1967,6 +1967,7 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(6, 0, 1): case IP_VERSION(6, 0, 2): case IP_VERSION(6, 0, 3): + case IP_VERSION(6, 1, 0): amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); break; default: -- 2.41.0
[PATCH] drm/amdgpu/discovery: add smuio 14.0.0 support
From: Prike Liang Add to IP discovery table. Signed-off-by: Prike Liang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 13686f194d104..f2b95c38ac3d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2508,6 +2508,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) break; case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 8): + case IP_VERSION(14, 0, 0): adev->smuio.funcs = &smuio_v13_0_6_funcs; break; default: -- 2.41.0
[PATCH 1/2] drm/amdgpu: add PSP 14.0.0 support
From: Li Ma
Uses same driver interface as 13.0.
Signed-off-by: Li Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 6ffc1a640d2dc..4e428060a1fa2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -202,6 +202,7 @@ static int psp_early_init(void *handle)
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 8):
case IP_VERSION(13, 0, 11):
+ case IP_VERSION(14, 0, 0):
psp_v13_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index e1a392bcea70d..d23827d3d8cca 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -50,6 +50,8 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
+MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
+MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
/* For large FW files the time to complete can be very long */
#define USBC_PD_POLLING_LIMIT_S 240
@@ -94,6 +96,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 8):
case IP_VERSION(13, 0, 11):
+ case IP_VERSION(14, 0, 0):
err = psp_init_toc_microcode(psp, ucode_prefix);
if (err)
return err;
--
2.41.0
[PATCH 2/2] drm/amdgpu/discovery: enable PSP 14.0.0 support
From: Li Ma Add it to IP discovery. Signed-off-by: Li Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 16cf7b199457e..13686f194d104 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1750,6 +1750,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(13, 0, 8): case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 11): + case IP_VERSION(14, 0, 0): amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); break; case IP_VERSION(13, 0, 4): -- 2.41.0
[PATCH] drm/amdkfd: fix and enable ttmp setup for gfx11
The MES cached process context must be cleared on adding any queue for
the first time.
For proper debug support, the MES will clear it's cached process context
on the first call to SET_SHADER_DEBUGGER.
This allows TTMPs to be pesistently enabled in a safe manner.
Signed-off-by: Jonathan Kim
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c| 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 13 -
drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 19 +--
drivers/gpu/drm/amd/amdkfd/kfd_debug.h| 11 ++-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 2 ++
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 +---
6 files changed, 39 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
index 77ca5cbfb601..d67d003bada2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
@@ -637,7 +637,7 @@ static uint32_t kgd_gfx_v11_disable_debug_trap(struct
amdgpu_device *adev,
{
uint32_t data = 0;
- data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN,
keep_trap_enabled);
+ data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);
data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index e0f9cf6dd8fd..42df972357e9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -2755,6 +2755,16 @@ static int runtime_enable(struct kfd_process *p,
uint64_t r_debug,
if (pdd->qpd.queue_count)
return -EEXIST;
+
+ /*
+* Setup TTMPs by default.
+* Note that this call must remain here for MES ADD QUEUE to
+* skip_process_ctx_clear unconditionally as the first call to
+* SET_SHADER_DEBUGGER clears any stale process context data
+* saved in MES.
+*/
+ if (pdd->dev->kfd->shared_resources.enable_mes)
+ kfd_dbg_set_mes_debug_mode(pdd,
!kfd_dbg_has_cwsr_workaround(pdd->dev));
}
p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED;
@@ -2848,7 +2858,8 @@ static int runtime_disable(struct kfd_process *p)
if (!pdd->dev->kfd->shared_resources.enable_mes)
debug_refresh_runlist(pdd->dev->dqm);
else
- kfd_dbg_set_mes_debug_mode(pdd);
+ kfd_dbg_set_mes_debug_mode(pdd,
+
!kfd_dbg_has_cwsr_workaround(pdd->dev));
}
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index 1f82caea59ba..9ec750666382 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -344,11 +344,10 @@ static int kfd_dbg_set_workaround(struct kfd_process
*target, bool enable)
return r;
}
-int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd)
+int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en)
{
uint32_t spi_dbg_cntl = pdd->spi_dbg_override |
pdd->spi_dbg_launch_mode;
uint32_t flags = pdd->process->dbg_flags;
- bool sq_trap_en = !!spi_dbg_cntl ||
!kfd_dbg_has_cwsr_workaround(pdd->dev);
if (!kfd_dbg_is_per_vmid_supported(pdd->dev))
return 0;
@@ -432,7 +431,7 @@ int kfd_dbg_trap_clear_dev_address_watch(struct
kfd_process_device *pdd,
if (!pdd->dev->kfd->shared_resources.enable_mes)
r = debug_map_and_unlock(pdd->dev->dqm);
else
- r = kfd_dbg_set_mes_debug_mode(pdd);
+ r = kfd_dbg_set_mes_debug_mode(pdd, true);
kfd_dbg_clear_dev_watch_id(pdd, watch_id);
@@ -474,7 +473,7 @@ int kfd_dbg_trap_set_dev_address_watch(struct
kfd_process_device *pdd,
if (!pdd->dev->kfd->shared_resources.enable_mes)
r = debug_map_and_unlock(pdd->dev->dqm);
else
- r = kfd_dbg_set_mes_debug_mode(pdd);
+ r = kfd_dbg_set_mes_debug_mode(pdd, true);
/* HWS is broken so no point in HW rollback but release the watchpoint
anyways */
if (r)
@@ -516,7 +515,7 @@ int kfd_dbg_trap_set_flags(struct kfd_process *target,
uint32_t *flags)
if (!pdd->dev->kfd->shared_resources.enable_mes)
r = debug_refresh_runlist(pdd->dev->dqm);
else
- r = kfd_dbg_set_mes_debug_mode(pdd);
+ r = kfd_dbg_set_mes_debug_mode(pdd, true);
if (r) {
target->d
[PATCH] drm/amdkfd: start_cpsch don't map queues
start_cpsch map queues when kfd_init_node have race condition with
IOMMUv2 init, and cause the gfx ring test failed later. Remove it
from start_cpsch because map queues will be done when creating queues
and resume queues.
Reported-by: Michel Dänzer
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 71b7f16c0173..a2d0d0bcf853 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1658,9 +1658,6 @@ static int start_cpsch(struct device_queue_manager *dqm)
dqm->is_resetting = false;
dqm->sched_running = true;
- if (!dqm->dev->kfd->shared_resources.enable_mes)
- execute_queues_cpsch(dqm,
KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
-
/* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU */
if (amdgpu_emu_mode == 0 && dqm->dev->adev->gmc.is_app_apu &&
(KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 3))) {
--
2.35.1
Re: [PATCH] drm/amdgpu: Remove volatile from 'wb' & from 'ptr' in amdgpu.h
On Mon, Jul 24, 2023 at 11:54 AM Srinivasan Shanmugam
wrote:
>
> Fixes the following from checkpatch.pl:
>
> WARNING: Use of volatile is usually wrong: see
> Documentation/process/volatile-considered-harmful.rst
> + volatile uint32_t *wb;
>
> WARNING: Use of volatile is usually wrong: see
> Documentation/process/volatile-considered-harmful.rst
> + volatile uint32_t *ptr;
>
> 'wb' field from 'amdgpu_wb' struct & 'ptr' field from
> 'amdgpu_mem_scratch', is not used to access h/w directly, neither they
> are shared variables, so volatile is not necessary
How did you come to that determination? Both are GPU accessible
memory allocations. The writeback (wb) allocation happens to be in
GTT so it's system memory, but the the mem_scratch allocation can be
in device memory.
Alex
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index a046160b6a0e..06f79a84ff4b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -502,7 +502,7 @@ int amdgpu_file_to_fpriv(struct file *filp, struct
> amdgpu_fpriv **fpriv);
>
> struct amdgpu_wb {
> struct amdgpu_bo*wb_obj;
> - volatile uint32_t *wb;
> + u32 *wb;
> uint64_tgpu_addr;
> u32 num_wb; /* Number of wb slots actually
> reserved for amdgpu. */
> unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB,
> BITS_PER_LONG)];
> @@ -621,7 +621,7 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev,
> void *data,
> /* VRAM scratch page for HDP bug, default vram page */
> struct amdgpu_mem_scratch {
> struct amdgpu_bo*robj;
> - volatile uint32_t *ptr;
> + u32 *ptr;
> u64 gpu_addr;
> };
>
> --
> 2.25.1
>
[PATCH] drm/amdgpu: Checkpoint and Restore VRAM BOs without VA
Extend checkpoint logic to allow inclusion of VRAM BOs that
do not have a VA attached
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 40ac093b5035..5cc00ff4b635 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1845,7 +1845,8 @@ static uint32_t get_process_num_bos(struct kfd_process *p)
idr_for_each_entry(&pdd->alloc_idr, mem, id) {
struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
- if ((uint64_t)kgd_mem->va > pdd->gpuvm_base)
+ if (((uint64_t)kgd_mem->va > pdd->gpuvm_base) ||
+ (kgd_mem->va == 0))
num_of_bos++;
}
}
@@ -1917,7 +1918,8 @@ static int criu_checkpoint_bos(struct kfd_process *p,
kgd_mem = (struct kgd_mem *)mem;
dumper_bo = kgd_mem->bo;
- if ((uint64_t)kgd_mem->va <= pdd->gpuvm_base)
+ if (((uint64_t)kgd_mem->va <= pdd->gpuvm_base) &&
+ !(kgd_mem->va == 0))
continue;
bo_bucket = &bo_buckets[bo_index];
--
2.25.1
[PATCH] drm/amdgpu: Remove volatile from 'wb' & from 'ptr' in amdgpu.h
Fixes the following from checkpatch.pl:
WARNING: Use of volatile is usually wrong: see
Documentation/process/volatile-considered-harmful.rst
+ volatile uint32_t *wb;
WARNING: Use of volatile is usually wrong: see
Documentation/process/volatile-considered-harmful.rst
+ volatile uint32_t *ptr;
'wb' field from 'amdgpu_wb' struct & 'ptr' field from
'amdgpu_mem_scratch', is not used to access h/w directly, neither they
are shared variables, so volatile is not necessary
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a046160b6a0e..06f79a84ff4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -502,7 +502,7 @@ int amdgpu_file_to_fpriv(struct file *filp, struct
amdgpu_fpriv **fpriv);
struct amdgpu_wb {
struct amdgpu_bo*wb_obj;
- volatile uint32_t *wb;
+ u32 *wb;
uint64_tgpu_addr;
u32 num_wb; /* Number of wb slots actually reserved
for amdgpu. */
unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB,
BITS_PER_LONG)];
@@ -621,7 +621,7 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev,
void *data,
/* VRAM scratch page for HDP bug, default vram page */
struct amdgpu_mem_scratch {
struct amdgpu_bo*robj;
- volatile uint32_t *ptr;
+ u32 *ptr;
u64 gpu_addr;
};
--
2.25.1
[PATCH] drm/amdgpu: Fix unused variable 'domain' in 'amdgpu_bo_print_info'
Fixes the following:
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c: In function ‘amdgpu_bo_print_info’:
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:1581:15: warning: unused variable
‘domain’ [-Wunused-variable]
1581 | unsigned int domain;
| ^~
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5ac7544cc068..3f98174fb764 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1578,7 +1578,6 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo,
struct seq_file *m)
{
struct dma_buf_attachment *attachment;
struct dma_buf *dma_buf;
- unsigned int domain;
const char *placement;
unsigned int pin_count;
u64 size;
--
2.25.1
Re: [PATCH] drm/amdgpu: Update min() to min_t() in 'amdgpu_info_ioctl'
On Sun, Jul 23, 2023 at 3:06 AM Srinivasan Shanmugam
wrote:
>
> Fixes the following:
>
> WARNING: min() should probably be min_t(size_t, size, sizeof(ip))
> + ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
>
> And other style fixes:
>
> WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
> WARNING: Missing a blank line after declarations
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 12f3c7ad7d04..631c5ab3f7dc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -557,6 +557,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data,
> struct drm_file *filp)
> crtc = (struct drm_crtc *)minfo->crtcs[i];
> if (crtc && crtc->base.id == info->mode_crtc.id) {
> struct amdgpu_crtc *amdgpu_crtc =
> to_amdgpu_crtc(crtc);
> +
> ui32 = amdgpu_crtc->crtc_id;
> found = 1;
> break;
> @@ -575,7 +576,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data,
> struct drm_file *filp)
> if (ret)
> return ret;
>
> - ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
> + ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
> return ret ? -EFAULT : 0;
> }
> case AMDGPU_INFO_HW_IP_COUNT: {
> @@ -721,17 +722,18 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
> *data, struct drm_file *filp)
> ? -EFAULT : 0;
> }
> case AMDGPU_INFO_READ_MMR_REG: {
> - unsigned n, alloc_size;
> + unsigned int n, alloc_size;
> uint32_t *regs;
> - unsigned se_num = (info->read_mmr_reg.instance >>
> + unsigned int se_num = (info->read_mmr_reg.instance >>
>AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
> AMDGPU_INFO_MMR_SE_INDEX_MASK;
> - unsigned sh_num = (info->read_mmr_reg.instance >>
> + unsigned int sh_num = (info->read_mmr_reg.instance >>
>AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
> AMDGPU_INFO_MMR_SH_INDEX_MASK;
>
> /* set full masks if the userspace set all bits
> -* in the bitfields */
> +* in the bitfields
> +*/
> if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
> se_num = 0x;
> else if (se_num >= AMDGPU_GFX_MAX_SE)
> @@ -896,7 +898,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data,
> struct drm_file *filp)
> return ret;
> }
> case AMDGPU_INFO_VCE_CLOCK_TABLE: {
> - unsigned i;
> + unsigned int i;
> struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
> struct amd_vce_state *vce_state;
>
> --
> 2.25.1
>
Re: [PATCH] drm/amdgpu: Add EXT_COHERENCE memory allocation flags
Cover letter got lost, here it is:
This is in support of a RCCL change that requires specific
coherence behaviour.
Corresponding Thunk patch is at
https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/pull/88
These flags (for GEM and SVM allocations) allocate
memory that allows for system-scope atomic semantics.
On GFX943 these flags cause caches to be avoided on
non-local memory.
On all other ASICs they are identical in functionality to the
equivalent COHERENT flags.
Signed-off-by: David Francis
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 5 -
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 10 +-
include/uapi/drm/amdgpu_drm.h| 7 +++
include/uapi/linux/kfd_ioctl.h | 3 +++
7 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 9e18fe5eb190..67634e9f6466 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1790,6 +1790,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
+ if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENCE)
+ alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENCE;
if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 1c07459e2bd2..6a6f6068bea0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -631,6 +631,7 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
}
if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
+ AMDGPU_GEM_CREATE_EXT_COHERENCE |
AMDGPU_GEM_CREATE_UNCACHED))
*flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index a6ee0220db56..ff330c7c0232 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -540,6 +540,7 @@ static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
}
if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
+ AMDGPU_GEM_CREATE_EXT_COHERENCE |
AMDGPU_GEM_CREATE_UNCACHED))
*flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 8447fcada8bb..17cf19c868e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1180,7 +1180,8 @@ static void gmc_v9_0_get_coherence_flags(struct
amdgpu_device *adev,
{
struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM;
- bool coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT;
+ bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
AMDGPU_GEM_CREATE_EXT_COHERENCE);
+ bool ext_coherence = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENCE;
bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
struct amdgpu_vm *vm = mapping->bo_va->base.vm;
unsigned int mtype_local, mtype;
@@ -1248,6 +1249,8 @@ static void gmc_v9_0_get_coherence_flags(struct
amdgpu_device *adev,
snoop = true;
if (uncached) {
mtype = MTYPE_UC;
+ } else if (ext_coherence) {
+ mtype = is_local ? MTYPE_CC : MTYPE_UC;
} else if (adev->flags & AMD_IS_APU) {
mtype = is_local ? mtype_local : MTYPE_NC;
} else {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 909f1ef8927d..acb87b2fe8df 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1157,7 +1157,8 @@ svm_range_get_pte_flags(struct kfd_node *node,
uint32_t mapping_flags = 0;
uint64_t pte_flags;
bool snoop = (domain != SVM_RANGE_VRAM_DOMAIN);
- bool coherent = flags & KFD_IOCTL_SVM_FLAG_COHERENT;
+ bool coherent = flags & (KFD_IOCTL_SVM_FLAG_COHERENT |
KFD_IOCTL_SVM_FLAG_EXT_COHERENCE);
+ bool ext_coherence = flags & KFD_IOCTL_SVM_FLAG_EXT_COHERENCE;
bool uncached = false; /*flags & KFD_IOCTL_SVM_FLAG_UNCACHED;*/
unsigned int mtype_local;
@@ -1205,6 +1206,13 @@
[PATCH] drm/amdgpu: Add EXT_COHERENCE memory allocation flags
These flags (for GEM and SVM allocations) allocate
memory that allows for system-scope atomic semantics.
On GFX943 these flags cause caches to be avoided on
non-local memory.
On all other ASICs they are identical in functionality to the
equivalent COHERENT flags.
Signed-off-by: David Francis
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 5 -
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 10 +-
include/uapi/drm/amdgpu_drm.h| 7 +++
include/uapi/linux/kfd_ioctl.h | 3 +++
7 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 9e18fe5eb190..67634e9f6466 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1790,6 +1790,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
+ if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENCE)
+ alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENCE;
if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 1c07459e2bd2..6a6f6068bea0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -631,6 +631,7 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
}
if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
+ AMDGPU_GEM_CREATE_EXT_COHERENCE |
AMDGPU_GEM_CREATE_UNCACHED))
*flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index a6ee0220db56..ff330c7c0232 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -540,6 +540,7 @@ static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
}
if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
+ AMDGPU_GEM_CREATE_EXT_COHERENCE |
AMDGPU_GEM_CREATE_UNCACHED))
*flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 8447fcada8bb..17cf19c868e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1180,7 +1180,8 @@ static void gmc_v9_0_get_coherence_flags(struct
amdgpu_device *adev,
{
struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM;
- bool coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT;
+ bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
AMDGPU_GEM_CREATE_EXT_COHERENCE);
+ bool ext_coherence = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENCE;
bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
struct amdgpu_vm *vm = mapping->bo_va->base.vm;
unsigned int mtype_local, mtype;
@@ -1248,6 +1249,8 @@ static void gmc_v9_0_get_coherence_flags(struct
amdgpu_device *adev,
snoop = true;
if (uncached) {
mtype = MTYPE_UC;
+ } else if (ext_coherence) {
+ mtype = is_local ? MTYPE_CC : MTYPE_UC;
} else if (adev->flags & AMD_IS_APU) {
mtype = is_local ? mtype_local : MTYPE_NC;
} else {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 909f1ef8927d..acb87b2fe8df 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1157,7 +1157,8 @@ svm_range_get_pte_flags(struct kfd_node *node,
uint32_t mapping_flags = 0;
uint64_t pte_flags;
bool snoop = (domain != SVM_RANGE_VRAM_DOMAIN);
- bool coherent = flags & KFD_IOCTL_SVM_FLAG_COHERENT;
+ bool coherent = flags & (KFD_IOCTL_SVM_FLAG_COHERENT |
KFD_IOCTL_SVM_FLAG_EXT_COHERENCE);
+ bool ext_coherence = flags & KFD_IOCTL_SVM_FLAG_EXT_COHERENCE;
bool uncached = false; /*flags & KFD_IOCTL_SVM_FLAG_UNCACHED;*/
unsigned int mtype_local;
@@ -1205,6 +1206,13 @@ svm_range_get_pte_flags(struct kfd_node *node,
snoop = true;
if (uncached) {
mapping_flags |= AMDGPU_VM_MTYPE_UC;
+ } else if (ext_coherence) {
+
[no subject]
This is in support of a RCCL change that requires specific coherence behaviour. Corresponding Thunk patch is at https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/pull/88
Re: [PATCH] drm/amd/display: Remove else after return in 'dm_vblank_get_counter' & 'amdgpu_dm_backlight_get_level'
On 7/23/23 05:31, Srinivasan Shanmugam wrote:
Expressions under 'else' branch in function 'dm_vblank_get_counter' &
'amdgpu_dm_backlight_get_level' are executed whenever the expression in
'if' is False. Otherwise, return from case occurs. Therefore, there is
no need in 'else', and it has been removed.
Fixes the following:
WARNING: else is not generally useful after a break or return
+ return 0;
+ else {
WARNING: else is not generally useful after a break or return
+ return convert_brightness_to_user(&caps, avg);
+ } else {
Cc: Rodrigo Siqueira
Cc: Aurabindo Pillai
Signed-off-by: Srinivasan Shanmugam
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 31 ++-
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1e1a38014475..77d970a2ee69 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -245,19 +245,20 @@ is_timing_unchanged_for_freesync(struct drm_crtc_state
*old_crtc_state,
*/
static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
{
+ struct amdgpu_crtc *acrtc = NULL;
+
if (crtc >= adev->mode_info.num_crtc)
return 0;
- else {
- struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
- if (acrtc->dm_irq_params.stream == NULL) {
- DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
- crtc);
- return 0;
- }
+ acrtc = adev->mode_info.crtcs[crtc];
- return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
+ if (!acrtc->dm_irq_params.stream) {
+ DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
+ crtc);
+ return 0;
}
+
+ return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
}
static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
@@ -4091,6 +4092,7 @@ static int amdgpu_dm_backlight_update_status(struct
backlight_device *bd)
static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
int bl_idx)
{
+ int ret;
struct amdgpu_dm_backlight_caps caps;
struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
@@ -4105,13 +4107,14 @@ static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
if (!rc)
return dm->brightness[bl_idx];
return convert_brightness_to_user(&caps, avg);
- } else {
- int ret = dc_link_get_backlight_level(link);
-
- if (ret == DC_ERROR_UNEXPECTED)
- return dm->brightness[bl_idx];
- return convert_brightness_to_user(&caps, ret);
}
+
+ ret = dc_link_get_backlight_level(link);
+
+ if (ret == DC_ERROR_UNEXPECTED)
+ return dm->brightness[bl_idx];
+
+ return convert_brightness_to_user(&caps, ret);
}
static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
Reviewed-by: Rodrigo Siqueira
Re: [PATCH 3/3] drm/amd/display: Implement zpos property
Hi Joshua,
It looks like this patch caused a regression in the following IGT test:
kms_atomic@plane-immutable-zpos
This issue is causing failures in our CI; we probably need to revert it.
Could you check it?
Thanks
Siqueira
On 7/13/23 13:55, Harry Wentland wrote:
On 2023-07-08 22:06, Joshua Ashton wrote:
Despite certain GPUs supporting multiple overlay planes already in
AMDGPU, the driver did not expose the zpos property which is required
for userspace to take advantage of multiple overlay planes in any
meaningful way.
The driver was already hooked up to normalized_zpos, but was just
missing the exposure of it.
Signed-off-by: Joshua Ashton
Series is
Reviewed-by: Harry Wentland
Harry
Cc: Harry Wentland
Cc: Melissa Wen
Cc: Simon Ser
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 8eeca160d434..2198df96ed6f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1468,6 +1468,15 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager
*dm,
drm_plane_create_blend_mode_property(plane, blend_caps);
}
+ if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
+ drm_plane_create_zpos_immutable_property(plane, 0);
+ } else if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
+ unsigned int zpos = 1 + drm_plane_index(plane);
+ drm_plane_create_zpos_property(plane, zpos, 1, 254);
+ } else if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+ drm_plane_create_zpos_immutable_property(plane, 255);
+ }
+
if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
plane_cap &&
(plane_cap->pixel_format_support.nv12 ||
Re: [PATCH V7 4/9] wifi: mac80211: Add support for ACPI WBRF
On 7/24/2023 04:22, Andrew Lunn wrote:
@@ -1395,6 +1395,8 @@ int ieee80211_register_hw(struct ieee80211_hw *hw)
debugfs_hw_add(local);
rate_control_add_debugfs(local);
+ ieee80211_check_wbrf_support(local);
+
rtnl_lock();
wiphy_lock(hw->wiphy);
+void ieee80211_check_wbrf_support(struct ieee80211_local *local)
+{
+ struct wiphy *wiphy = local->hw.wiphy;
+ struct device *dev;
+
+ if (!wiphy)
+ return;
+
+ dev = wiphy->dev.parent;
+ if (!dev)
+ return;
+
+ local->wbrf_supported = wbrf_supported_producer(dev);
+ dev_dbg(dev, "WBRF is %s supported\n",
+ local->wbrf_supported ? "" : "not");
+}
This seems wrong. wbrf_supported_producer() is about "Should this
device report the frequencies it is using?" The answer to that depends
on a combination of: Are there consumers registered with the core, and
is the policy set so WBRF should take actions. >
The problem here is, you have no idea of the probe order. It could be
this device probes before others, so wbrf_supported_producer() reports
false, but a few second later would report true, once other devices
have probed.
It should be an inexpensive call into the core, so can be made every
time the channel changes. All the core needs to do is check if the
list of consumers is empty, and if not, check a Boolean policy value.
Andrew
No, it's not a combination of whether consumers are registered with the
core. If a consumer probes later it needs to know the current in use
frequencies too.
The reason is because of this sequence of events:
1) Producer probes.
2) Producer selects a frequency.
3) Consumer probes.
4) Producer stays at same frequency.
If the producer doesn't notify the frequency because a consumer isn't
yet loaded then the consumer won't be able to get the current frequency.
Re: [PATCH] drm/amd/pm: Clean up errors in sienna_cichlid_ppt.c
Hi,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on drm/drm-next drm-exynos/exynos-drm-next
drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip
linus/master v6.5-rc3 next-20230724]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/sunran001-208suo-com/drm-amd-pm-Clean-up-errors-in-sienna_cichlid_ppt-c/20230724-153134
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/ea1cf43d5545fa917127694a294a57da%40208suo.com
patch subject: [PATCH] drm/amd/pm: Clean up errors in sienna_cichlid_ppt.c
config: riscv-randconfig-r014-20230724
(https://download.01.org/0day-ci/archive/20230724/202307242115.lz6dajqo-...@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project.git
f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce:
(https://download.01.org/0day-ci/archive/20230724/202307242115.lz6dajqo-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202307242115.lz6dajqo-...@intel.com/
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:595:28:
>> error: use of undeclared identifier 'smu_table'; did you mean 'smu_tabl'?
(SmuMetricsExternal_t *)(smu_table->metrics_table);
^
smu_tabl
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:593:28:
note: 'smu_tabl' declared here
struct smu_table_context *smu_tabl = &smu->smu_table;
^
1 error generated.
vim +595 drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c
b455159c053130d drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c Likun
Gao2020-05-29 590
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 591 static uint32_t
sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 592 {
34af41f9a039153 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
sunran...@208suo.com 2023-07-24 593struct smu_table_context *smu_tabl =
&smu->smu_table;
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 594SmuMetricsExternal_t *metrics_ext =
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 @595(SmuMetricsExternal_t
*)(smu_table->metrics_table);
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 596uint32_t throttler_status = 0;
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 597int i;
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 598
1d789535a03679e drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Alex
Deucher 2021-10-04 599if ((smu->adev->ip_versions[MP1_HWIP][0] ==
IP_VERSION(11, 0, 7)) &&
7952fa0d3e18750 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Danijel
Slivka 2022-03-02 600 (smu->smc_fw_version >= 0x3A4900)) {
7952fa0d3e18750 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Danijel
Slivka 2022-03-02 601for (i = 0; i < THROTTLER_COUNT; i++)
7952fa0d3e18750 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Danijel
Slivka 2022-03-02 602throttler_status |=
7952fa0d3e18750 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Danijel
Slivka 2022-03-02 603
(metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
7952fa0d3e18750 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Danijel
Slivka 2022-03-02 604} else if ((smu->adev->ip_versions[MP1_HWIP][0]
== IP_VERSION(11, 0, 7)) &&
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 605 (smu->smc_fw_version >= 0x3A4300)) {
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 606for (i = 0; i < THROTTLER_COUNT; i++)
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sie
Re: [PATCH v2] drm/amdgpu: Add -ENOMEM error handling when there is no memory
On Sun, Jul 23, 2023 at 8:53 AM Srinivasan Shanmugam
wrote:
>
> Return -ENOMEM, when there is no sufficient dynamically allocated memory
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
Reviewed-by: Alex Deucher
> ---
>
> v2:
> - Added -ENOMEM - when it failed to create MQD backup,
>while creating MQD for each KCQ
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 17 ++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 1 +
> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 4 +++-
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 +++-
> 4 files changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 6639fde5dd5c..c76b6bfc4dab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -110,9 +110,9 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device
> *adev,
> * The bitmask of CUs to be disabled in the shader array determined by se and
> * sh is stored in mask[se * max_sh + sh].
> */
> -void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned
> max_sh)
> +void amdgpu_gfx_parse_disable_cu(unsigned int *mask, unsigned int max_se,
> unsigned int max_sh)
> {
> - unsigned se, sh, cu;
> + unsigned int se, sh, cu;
> const char *p;
>
> memset(mask, 0, sizeof(*mask) * max_se * max_sh);
> @@ -124,6 +124,7 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned
> max_se, unsigned max_s
> for (;;) {
> char *next;
> int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
> +
> if (ret < 3) {
> DRM_ERROR("amdgpu: could not parse disable_cu\n");
> return;
> @@ -349,7 +350,7 @@ void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int
> xcc_id)
> }
>
> int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
> - unsigned hpd_size, int xcc_id)
> + unsigned int hpd_size, int xcc_id)
> {
> int r;
> u32 *hpd;
> @@ -376,7 +377,7 @@ int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
>
> /* create MQD for each compute/gfx queue */
> int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
> - unsigned mqd_size, int xcc_id)
> + unsigned int mqd_size, int xcc_id)
> {
> int r, i, j;
> struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
> @@ -454,8 +455,10 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
> ring->mqd_size = mqd_size;
> /* prepare MQD backup */
> adev->gfx.mec.mqd_backup[j] = kmalloc(mqd_size,
> GFP_KERNEL);
> - if (!adev->gfx.mec.mqd_backup[j])
> + if (!adev->gfx.mec.mqd_backup[j]) {
> dev_warn(adev->dev, "no memory to create MQD
> backup for ring %s\n", ring->name);
> + return -ENOMEM;
> + }
> }
> }
>
> @@ -1286,11 +1289,11 @@ static ssize_t
> amdgpu_gfx_get_available_compute_partition(struct device *dev,
> return sysfs_emit(buf, "%s\n", supported_partition);
> }
>
> -static DEVICE_ATTR(current_compute_partition, S_IRUGO | S_IWUSR,
> +static DEVICE_ATTR(current_compute_partition, 0644,
>amdgpu_gfx_get_current_compute_partition,
>amdgpu_gfx_set_compute_partition);
>
> -static DEVICE_ATTR(available_compute_partition, S_IRUGO,
> +static DEVICE_ATTR(available_compute_partition, 0444,
>amdgpu_gfx_get_available_compute_partition, NULL);
>
> int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> index 03dc59cbe8aa..7e91b24784e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> @@ -500,6 +500,7 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct
> amdgpu_device *adev)
> hive = kzalloc(sizeof(*hive), GFP_KERNEL);
> if (!hive) {
> dev_err(adev->dev, "XGMI: allocation failed\n");
> + ret = -ENOMEM;
> hive = NULL;
> goto pro_end;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> index 36a123e6c8ee..eb06d749876f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> @@ -909,10 +909,12 @@ static int mes_v10_1_mqd_sw_init(struct amdgpu_device
> *adev,
>
> /* prepare MQD backup */
> adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
> - if (!adev->mes.mqd_backup[pipe])
> + if (!adev->mes.mqd_backup[pipe]) {
> dev_warn(adev->dev,
> "no m
[PATCH] drm/radeon: that open brace { should be on the previous line
ERROR: that open brace { should be on the previous line
Signed-off-by: Ran Sun
---
drivers/gpu/drm/radeon/ni_dpm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c
b/drivers/gpu/drm/radeon/ni_dpm.c
index a101ba00ea30..1cf4de4cda23 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -625,7 +625,7 @@ static const u32 cayman_mgcg_disable[] =
};
#define CAYMAN_MGCG_DISABLE_LENGTH sizeof(cayman_mgcg_disable) / (3 *
sizeof(u32))
-static const u32 cayman_mgcg_enable[] = :621 {
+static const u32 cayman_mgcg_enable[] = : 621 {
0x802c, 0xc000, 0x,
0x08f8, 0x, 0x,
0x08fc, 0x, 0x,
Re: radeon.ko/i586: BUG: kernel NULL pointer dereference,address:00000004
On Sat, 22 Jul 2023 11:30:14 +0900 wrote: > >> diff --git a/arch/x86/include/asm/ftrace.h b/arch/x86/include/asm/ftrace.h > >> index 897cf02c20b1..801f4414da3e 100644 > >> --- a/arch/x86/include/asm/ftrace.h > >> +++ b/arch/x86/include/asm/ftrace.h > >> @@ -13,7 +13,7 @@ > >> #ifdef CONFIG_HAVE_FENTRY > >> # include > >> /* Add offset for endbr64 if IBT enabled */ > >> -# define FTRACE_MCOUNT_MAX_OFFSET ENDBR_INSN_SIZE > >> +# define FTRACE_MCOUNT_MAX_OFFSET (ENDBR_INSN_SIZE + MCOUNT_INSN_SIZE) > >> #endif > >> > >> #ifdef CONFIG_DYNAMIC_FTRACE > >> > > Above patch didn't work, but > Does it matter that I am compiling with "gcc -fcf-protection=none" > to not emit endbr32 instructions for i586? This patch is supposed to address the case when ENDBR_INSN_SIZE is zero. So I would think that that wouldn't matter. -- Steve
[PATCH] drm/amd/pm: Clean up errors in arcturus_ppt.c
Fix the following errors reported by checkpatch:
ERROR: "foo* bar" should be "foo *bar"
ERROR: spaces required around that '=' (ctx:VxW)
ERROR: space prohibited before that close parenthesis ')'
Signed-off-by: Ran Sun
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 3ecb900e6ecd..b26e9ac1ac30 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -691,7 +691,7 @@ int smu_cmn_feature_set_enabled(struct smu_context
*smu,
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(fea) #fea
-static const char* __smu_feature_names[] = {
+static const char *__smu_feature_names[] = {
SMU_FEATURE_MASKS
};
@@ -927,7 +927,7 @@ int smu_cmn_get_metrics_table(struct smu_context
*smu,
void *metrics_table,
bool bypass_cache)
{
- struct smu_table_context *smu_table= &smu->smu_table;
+ struct smu_table_context *smu_table = &smu->smu_table;
uint32_t table_size =
smu_table->tables[SMU_TABLE_SMU_METRICS].size;
int ret = 0;
@@ -969,7 +969,7 @@ void smu_cmn_init_soft_gpu_metrics(void *table,
uint8_t frev, uint8_t crev)
struct metrics_table_header *header = (struct metrics_table_header
*)table;
uint16_t structure_size;
-#define METRICS_VERSION(a, b) ((a << 16) | b )
+#define METRICS_VERSION(a, b) ((a << 16) | b)
switch (METRICS_VERSION(frev, crev)) {
case METRICS_VERSION(1, 0):
[PATCH] drm/radeon: that open brace { should be on the previous line
ERROR: that open brace { should be on the previous line
Signed-off-by: Ran Sun
---
drivers/gpu/drm/radeon/rv770_smc.c | 36 ++
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/radeon/rv770_smc.c
b/drivers/gpu/drm/radeon/rv770_smc.c
index 45575c0d0a1d..09fa7f5e7c41 100644
--- a/drivers/gpu/drm/radeon/rv770_smc.c
+++ b/drivers/gpu/drm/radeon/rv770_smc.c
@@ -34,8 +34,7 @@
#define FIRST_SMC_INT_VECT_REG 0xFFD8
#define FIRST_INT_VECT_S19 0xFFC0
-static const u8 rv770_smc_int_vectors[] =
-{
+static const u8 rv770_smc_int_vectors[] = {
0x08, 0x10, 0x08, 0x10,
0x08, 0x10, 0x08, 0x10,
0x08, 0x10, 0x08, 0x10,
@@ -54,8 +53,7 @@ static const u8 rv770_smc_int_vectors[] =
0x03, 0x51, 0x03, 0x51
};
-static const u8 rv730_smc_int_vectors[] =
-{
+static const u8 rv730_smc_int_vectors[] = {
0x08, 0x15, 0x08, 0x15,
0x08, 0x15, 0x08, 0x15,
0x08, 0x15, 0x08, 0x15,
@@ -74,8 +72,7 @@ static const u8 rv730_smc_int_vectors[] =
0x03, 0x56, 0x03, 0x56
};
-static const u8 rv710_smc_int_vectors[] =
-{
+static const u8 rv710_smc_int_vectors[] = {
0x08, 0x04, 0x08, 0x04,
0x08, 0x04, 0x08, 0x04,
0x08, 0x04, 0x08, 0x04,
@@ -94,8 +91,7 @@ static const u8 rv710_smc_int_vectors[] =
0x03, 0x51, 0x03, 0x51
};
-static const u8 rv740_smc_int_vectors[] =
-{
+static const u8 rv740_smc_int_vectors[] = {
0x08, 0x10, 0x08, 0x10,
0x08, 0x10, 0x08, 0x10,
0x08, 0x10, 0x08, 0x10,
@@ -114,8 +110,7 @@ static const u8 rv740_smc_int_vectors[] =
0x03, 0x51, 0x03, 0x51
};
-static const u8 cedar_smc_int_vectors[] =
-{
+static const u8 cedar_smc_int_vectors[] = {
0x0B, 0x05, 0x0B, 0x05,
0x0B, 0x05, 0x0B, 0x05,
0x0B, 0x05, 0x0B, 0x05,
@@ -134,8 +129,7 @@ static const u8 cedar_smc_int_vectors[] =
0x04, 0xF6, 0x04, 0xF6
};
-static const u8 redwood_smc_int_vectors[] =
-{
+static const u8 redwood_smc_int_vectors[] = {
0x0B, 0x05, 0x0B, 0x05,
0x0B, 0x05, 0x0B, 0x05,
0x0B, 0x05, 0x0B, 0x05,
@@ -154,8 +148,7 @@ static const u8 redwood_smc_int_vectors[] =
0x04, 0xF6, 0x04, 0xF6
};
-static const u8 juniper_smc_int_vectors[] =
-{
+static const u8 juniper_smc_int_vectors[] = {
0x0B, 0x05, 0x0B, 0x05,
0x0B, 0x05, 0x0B, 0x05,
0x0B, 0x05, 0x0B, 0x05,
@@ -174,8 +167,7 @@ static const u8 juniper_smc_int_vectors[] =
0x04, 0xF6, 0x04, 0xF6
};
-static const u8 cypress_smc_int_vectors[] =
-{
+static const u8 cypress_smc_int_vectors[] = {
0x0B, 0x05, 0x0B, 0x05,
0x0B, 0x05, 0x0B, 0x05,
0x0B, 0x05, 0x0B, 0x05,
@@ -194,8 +186,7 @@ static const u8 cypress_smc_int_vectors[] =
0x04, 0xF6, 0x04, 0xF6
};
-static const u8 barts_smc_int_vectors[] =
-{
+static const u8 barts_smc_int_vectors[] = {
0x0C, 0x14, 0x0C, 0x14,
0x0C, 0x14, 0x0C, 0x14,
0x0C, 0x14, 0x0C, 0x14,
@@ -214,8 +205,7 @@ static const u8 barts_smc_int_vectors[] =
0x05, 0x0A, 0x05, 0x0A
};
-static const u8 turks_smc_int_vectors[] =
-{
+static const u8 turks_smc_int_vectors[] = {
0x0C, 0x14, 0x0C, 0x14,
0x0C, 0x14, 0x0C, 0x14,
0x0C, 0x14, 0x0C, 0x14,
@@ -234,8 +224,7 @@ static const u8 turks_smc_int_vectors[] =
0x05, 0x0A, 0x05, 0x0A
};
-static const u8 caicos_smc_int_vectors[] =
-{
+static const u8 caicos_smc_int_vectors[] = {
0x0C, 0x14, 0x0C, 0x14,
0x0C, 0x14, 0x0C, 0x14,
0x0C, 0x14, 0x0C, 0x14,
@@ -254,8 +243,7 @@ static const u8 caicos_smc_int_vectors[] =
0x05, 0x0A, 0x05, 0x0A
};
-static const u8 cayman_smc_int_vectors[] =
-{
+static const u8 cayman_smc_int_vectors[] = {
0x12, 0x05, 0x12, 0x05,
0x12, 0x05, 0x12, 0x05,
0x12, 0x05, 0x12, 0x05,
[PATCH] drm/amd/pm: Clean up errors in smu_v13_0_1_pmfw.h
Fix the following errors reported by checkpatch:
ERROR: trailing whitespace
Signed-off-by: Ran Sun
---
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
index c5e26d619bf0..8ec588248aac 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
@@ -30,7 +30,7 @@
#define ENABLE_DEBUG_FEATURES
-// Firmware features
+// Firmware features
// Feature Control Defines
#define FEATURE_CCLK_DPM_BIT 0
#define FEATURE_FAN_CONTROLLER_BIT 1
@@ -92,7 +92,7 @@
#define FEATURE_ZSTATES_ECO_BIT 57
#define FEATURE_CC6_BIT 58
#define FEATURE_DS_UMCCLK_BIT 59
-#define FEATURE_DS_HSPCLK_BIT 60
+#define FEATURE_DS_HSPCLK_BIT 60
#define NUM_FEATURES61
typedef struct {
[PATCH] drm/amd/pm: Clean up errors in smu_v11_0_7_pptable.h
Fix the following errors reported by checkpatch:
ERROR: trailing whitespace
ERROR: open brace '{' following struct go on the same line
Signed-off-by: Ran Sun
---
.../amd/pm/swsmu/inc/smu_v11_0_7_pptable.h| 41 +--
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
index 1cb399dbc7cc..64d60d48846a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
@@ -42,23 +42,23 @@
#define SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION0x01
// Power Saving Clock Table Version 1.00
enum SMU_11_0_7_ODFEATURE_CAP {
-SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0,
-SMU_11_0_7_ODCAP_GFXCLK_CURVE,
-SMU_11_0_7_ODCAP_UCLK_LIMITS,
-SMU_11_0_7_ODCAP_POWER_LIMIT,
-SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,
-SMU_11_0_7_ODCAP_FAN_SPEED_MIN,
-SMU_11_0_7_ODCAP_TEMPERATURE_FAN,
-SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM,
-SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE,
-SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL,
-SMU_11_0_7_ODCAP_AUTO_UV_ENGINE,
-SMU_11_0_7_ODCAP_AUTO_OC_ENGINE,
-SMU_11_0_7_ODCAP_AUTO_OC_MEMORY,
+SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0,
+SMU_11_0_7_ODCAP_GFXCLK_CURVE,
+SMU_11_0_7_ODCAP_UCLK_LIMITS,
+SMU_11_0_7_ODCAP_POWER_LIMIT,
+SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,
+SMU_11_0_7_ODCAP_FAN_SPEED_MIN,
+SMU_11_0_7_ODCAP_TEMPERATURE_FAN,
+SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM,
+SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE,
+SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL,
+SMU_11_0_7_ODCAP_AUTO_UV_ENGINE,
+SMU_11_0_7_ODCAP_AUTO_OC_ENGINE,
+SMU_11_0_7_ODCAP_AUTO_OC_MEMORY,
SMU_11_0_7_ODCAP_FAN_CURVE,
SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,
-SMU_11_0_7_ODCAP_POWER_MODE,
-SMU_11_0_7_ODCAP_COUNT,
+SMU_11_0_7_ODCAP_POWER_MODE,
+SMU_11_0_7_ODCAP_COUNT,
};
enum SMU_11_0_7_ODFEATURE_ID {
@@ -130,8 +130,7 @@ enum SMU_11_0_7_PWRMODE_SETTING {
};
#define SMU_11_0_7_MAX_PMSETTING 32//Maximum Number of
PowerMode Settings
-struct smu_11_0_7_overdrive_table
-{
+struct smu_11_0_7_overdrive_table {
uint8_t revision;
//Revision = SMU_11_0_7_PP_OVERDRIVE_VERSION
uint8_t reserve[3]; //Zero
filled field reserved for future use
uint32_t feature_count; //Total
number of supported features
@@ -160,8 +159,7 @@ enum SMU_11_0_7_PPCLOCK_ID {
};
#define SMU_11_0_7_MAX_PPCLOCK 16 //Maximum Number of PP
Clocks
-struct smu_11_0_7_power_saving_clock_table
-{
+struct smu_11_0_7_power_saving_clock_table {
uint8_t revision;
//Revision = SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION
uint8_t reserve[3]; //Zero
filled field reserved for future use
uint32_t count;
//power_saving_clock_count = SMU_11_0_7_PPCLOCK_COUNT
@@ -169,8 +167,7 @@ struct smu_11_0_7_power_saving_clock_table
uint32_t min[SMU_11_0_7_MAX_PPCLOCK];
//PowerSavingClock Mode Clock Minimum array In MHz
};
-struct smu_11_0_7_powerplay_table
-{
+struct smu_11_0_7_powerplay_table {
struct atom_common_table_header header; //For
sienna_cichlid, header.format_revision = 15, header.content_revision = 0
uint8_t table_revision; //For
sienna_cichlid, table_revision = 2
uint16_t table_size; //Driver portion
table size. The offset to smc_pptable including header size
@@ -178,7 +175,7 @@ struct smu_11_0_7_powerplay_table
uint32_t golden_revision; //PPGen use only:
PP Table Revision on the Golden Data Base
uint16_t format_id; //PPGen use only:
PPTable for different ASICs. For sienna_cichlid this should be 0x80
uint32_t platform_caps;
//POWERPLAYABLE::ulPlatformCaps
-
+
uint8_t thermal_controller_type; //one of
SMU_11_0_7_PP_THERMALCONTROLLER
uint16_t small_power_limit1;
[PATCH] drm/amd/pm: open brace '{' following struct go on the same line
ERROR: open brace '{' following struct go on the same line
Signed-off-by: Ran Sun
---
.../amd/pm/swsmu/inc/smu_v13_0_7_pptable.h| 21 +++
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
index eadbe0149cae..eb694f9f556d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
@@ -41,8 +41,7 @@
#define SMU_13_0_7_PP_OVERDRIVE_VERSION 0x83// OverDrive 8
Table Version 0.2
#define SMU_13_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving
Clock Table Version 1.00
-enum SMU_13_0_7_ODFEATURE_CAP
-{
+enum SMU_13_0_7_ODFEATURE_CAP {
SMU_13_0_7_ODCAP_GFXCLK_LIMITS = 0,
SMU_13_0_7_ODCAP_UCLK_LIMITS,
SMU_13_0_7_ODCAP_POWER_LIMIT,
@@ -62,8 +61,7 @@ enum SMU_13_0_7_ODFEATURE_CAP
SMU_13_0_7_ODCAP_COUNT,
};
-enum SMU_13_0_7_ODFEATURE_ID
-{
+enum SMU_13_0_7_ODFEATURE_ID {
SMU_13_0_7_ODFEATURE_GFXCLK_LIMITS = 1 <<
SMU_13_0_7_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
SMU_13_0_7_ODFEATURE_UCLK_LIMITS = 1 <<
SMU_13_0_7_ODCAP_UCLK_LIMITS, //UCLK Limit feature
SMU_13_0_7_ODFEATURE_POWER_LIMIT = 1 <<
SMU_13_0_7_ODCAP_POWER_LIMIT, //Power Limit feature
@@ -85,8 +83,7 @@ enum SMU_13_0_7_ODFEATURE_ID
#define SMU_13_0_7_MAX_ODFEATURE 32 //Maximum Number of OD Features
-enum SMU_13_0_7_ODSETTING_ID
-{
+enum SMU_13_0_7_ODSETTING_ID {
SMU_13_0_7_ODSETTING_GFXCLKFMAX = 0,
SMU_13_0_7_ODSETTING_GFXCLKFMIN,
SMU_13_0_7_ODSETTING_UCLKFMIN,
@@ -123,8 +120,7 @@ enum SMU_13_0_7_ODSETTING_ID
};
#define SMU_13_0_7_MAX_ODSETTING 64 //Maximum Number of ODSettings
-enum SMU_13_0_7_PWRMODE_SETTING
-{
+enum SMU_13_0_7_PWRMODE_SETTING {
SMU_13_0_7_PMSETTING_POWER_LIMIT_QUIET = 0,
SMU_13_0_7_PMSETTING_POWER_LIMIT_BALANCE,
SMU_13_0_7_PMSETTING_POWER_LIMIT_TURBO,
@@ -144,8 +140,7 @@ enum SMU_13_0_7_PWRMODE_SETTING
};
#define SMU_13_0_7_MAX_PMSETTING 32 //Maximum Number of PowerMode
Settings
-struct smu_13_0_7_overdrive_table
-{
+struct smu_13_0_7_overdrive_table {
uint8_t revision; //Revision =
SMU_13_0_7_PP_OVERDRIVE_VERSION
uint8_t reserve[3]; //Zero filled field
reserved for future use
uint32_t feature_count; //Total number of
supported features
@@ -156,8 +151,7 @@ struct smu_13_0_7_overdrive_table
int16_t pm_setting[SMU_13_0_7_MAX_PMSETTING]; //Optimized power
mode feature settings
};
-enum SMU_13_0_7_PPCLOCK_ID
-{
+enum SMU_13_0_7_PPCLOCK_ID {
SMU_13_0_7_PPCLOCK_GFXCLK = 0,
SMU_13_0_7_PPCLOCK_SOCCLK,
SMU_13_0_7_PPCLOCK_UCLK,
@@ -175,8 +169,7 @@ enum SMU_13_0_7_PPCLOCK_ID
};
#define SMU_13_0_7_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
-struct smu_13_0_7_powerplay_table
-{
+struct smu_13_0_7_powerplay_table {
struct atom_common_table_header header; //For PLUM_BONITO,
header.format_revision = 15, header.content_revision = 0
uint8_t table_revision; //For PLUM_BONITO,
table_revision = 2
uint8_t padding;
Re: [PATCH AUTOSEL 4.14 1/9] drm/radeon: Fix integer overflow in radeon_cs_parser_init
Hi! > From: hackyzh002 > > [ Upstream commit f828b681d0cd566f86351c0b913e6cb6ed8c7b9c ] > > The type of size is unsigned, if size is 0x4000, there will be an > integer overflow, size will be zero after size *= sizeof(uint32_t), > will cause uninitialized memory to be referenced later I only got the first patch of the series via lkml, rest seems to have been lost somewhere :-(. Best regards, Pavel -- People of Russia, stop Putin before his war on Ukraine escalates. signature.asc Description: PGP signature
[PATCH] drm/radeon/si_dpm: open brace '{' following struct go on the same line
ERROR: open brace '{' following struct go on the same line
Signed-off-by: Ran Sun
---
drivers/gpu/drm/radeon/sislands_smc.h | 51 +--
1 file changed, 17 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/radeon/sislands_smc.h
b/drivers/gpu/drm/radeon/sislands_smc.h
index 4ea1cb2e45a3..4b7dee3cf58b 100644
--- a/drivers/gpu/drm/radeon/sislands_smc.h
+++ b/drivers/gpu/drm/radeon/sislands_smc.h
@@ -89,8 +89,7 @@ struct PP_SIslands_PAPMStatus
};
typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
-struct PP_SIslands_PAPMParameters
-{
+struct PP_SIslands_PAPMParameters {
uint32_tNearTDPLimitTherm;
uint32_tNearTDPLimitPAPM;
uint32_tPlatformPowerLimit;
@@ -100,8 +99,7 @@ struct PP_SIslands_PAPMParameters
};
typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
-struct SISLANDS_SMC_SCLK_VALUE
-{
+struct SISLANDS_SMC_SCLK_VALUE {
uint32_tvCG_SPLL_FUNC_CNTL;
uint32_tvCG_SPLL_FUNC_CNTL_2;
uint32_tvCG_SPLL_FUNC_CNTL_3;
@@ -113,8 +111,7 @@ struct SISLANDS_SMC_SCLK_VALUE
typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
-struct SISLANDS_SMC_MCLK_VALUE
-{
+struct SISLANDS_SMC_MCLK_VALUE {
uint32_tvMPLL_FUNC_CNTL;
uint32_tvMPLL_FUNC_CNTL_1;
uint32_tvMPLL_FUNC_CNTL_2;
@@ -129,8 +126,7 @@ struct SISLANDS_SMC_MCLK_VALUE
typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
-struct SISLANDS_SMC_VOLTAGE_VALUE
-{
+struct SISLANDS_SMC_VOLTAGE_VALUE {
uint16_tvalue;
uint8_t index;
uint8_t phase_settings;
@@ -138,8 +134,7 @@ struct SISLANDS_SMC_VOLTAGE_VALUE
typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
-struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
-{
+struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL {
uint8_t ACIndex;
uint8_t displayWatermark;
uint8_t gen2PCIE;
@@ -180,8 +175,7 @@ struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
-struct SISLANDS_SMC_SWSTATE
-{
+struct SISLANDS_SMC_SWSTATE {
uint8_t flags;
uint8_t levelCount;
uint8_t padding2;
@@ -205,8 +199,7 @@ struct SISLANDS_SMC_SWSTATE_SINGLE {
#define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3
#define SISLANDS_SMC_VOLTAGEMASK_MAX 4
-struct SISLANDS_SMC_VOLTAGEMASKTABLE
-{
+struct SISLANDS_SMC_VOLTAGEMASKTABLE {
uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
};
@@ -214,8 +207,7 @@ typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE
SISLANDS_SMC_VOLTAGEMASKTABLE;
#define SISLANDS_MAX_NO_VREG_STEPS 32
-struct SISLANDS_SMC_STATETABLE
-{
+struct SISLANDS_SMC_STATETABLE {
uint8_t thermalProtectType;
uint8_t systemFlags;
uint8_t maxVDDCIndexInPPTable;
@@ -254,8 +246,7 @@ typedef struct SISLANDS_SMC_STATETABLE
SISLANDS_SMC_STATETABLE;
#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c
#define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120
-struct PP_SIslands_FanTable
-{
+struct PP_SIslands_FanTable {
uint8_t fdo_mode;
uint8_t padding;
int16_t temp_min;
@@ -285,8 +276,7 @@ typedef struct PP_SIslands_FanTable
PP_SIslands_FanTable;
#define SMC_SISLANDS_SCALE_I 7
#define SMC_SISLANDS_SCALE_R 12
-struct PP_SIslands_CacConfig
-{
+struct PP_SIslands_CacConfig {
uint16_t
cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
uint32_t lkge_lut_V0;
uint32_t lkge_lut_Vstep;
@@ -308,23 +298,20 @@ typedef struct PP_SIslands_CacConfig
PP_SIslands_CacConfig;
#define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
#define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
-struct SMC_SIslands_MCRegisterAddress
-{
+struct SMC_SIslands_MCRegisterAddress {
uint16_t s0;
uint16_t s1;
};
typedef struct SMC_SIslands_MCRegisterAddress
SMC_SIslands_MCRegisterAddress;
-struct SMC_SIslands_MCRegisterSet
-{
+struct SMC_SIslands_MCRegisterSet {
uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
};
typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
-struct SMC_SIslands_MCRegisters
-{
+struct SMC_SIslands_MCRegisters {
uint8_t last;
uint8_t reserved[3];
SMC_SIslands_MCRegisterAddress
address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
@@ -333,8 +320,7 @@ struct SMC_SIslands_MCRegisters
typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters;
-struct SMC_SIslands_MCArbDramTimingRegisterSet
-{
+struct SMC_SIslands_MCArbDramTimingRegisterSet {
uint32_t mc_arb_dram_timing;
uint32_t mc_arb_dram_timing2;
uint8_t mc_arb_rfsh_rate;
@@ -344,8 +330,7 @@ struct S
Re: radeon.ko/i586: BUG: kernel NULL pointer dereference, address:00000004
Since the problem with enabling FTRACE_MCOUNT_MAX_OFFSET may be
test_for_valid_rec() returning wrong results, I made a small patch to
catch the result:
patch-test_for_valid_rec-printk.patch
diff -up ./kernel/trace/ftrace.c.ft ./kernel/trace/ftrace.c
--- ./kernel/trace/ftrace.c.ft 2023-07-21 21:51:29.450928552 +0900
+++ ./kernel/trace/ftrace.c 2023-07-23 01:59:59.321558953 +0900
@@ -3678,6 +3678,7 @@ static int test_for_valid_rec(struct dyn
/* Weak functions can cause invalid addresses */
if (!ret || offset > FTRACE_MCOUNT_MAX_OFFSET) {
rec->flags |= FTRACE_FL_DISABLED;
+ printk("%s: disable ftrace for %s offset 0x%lx\n", __func__,
str, offset);
return 0;
}
return 1;
I will attach the console output (with another panic).
Steve, does this look sane?
Another panic seems to occuring here:
void drm_vblank_cancel_pending_works(struct drm_vblank_crtc *vblank)
{
struct drm_vblank_work *work, *next;
assert_spin_locked(&vblank->dev->event_lock); <node);
drm_vblank_put(vblank->dev, vblank->pipe);
}
wake_up_all(&vblank->work_wait_queue);
}
So I tried to trap NULL and return:
patch-drm_vblank_cancel_pending_works-printk-NULL-ret.patch
diff -up ./drivers/gpu/drm/drm_vblank_work.c.pk2
./drivers/gpu/drm/drm_vblank_work.c
--- ./drivers/gpu/drm/drm_vblank_work.c.pk2 2023-06-06 20:50:40.0
+0900
+++ ./drivers/gpu/drm/drm_vblank_work.c 2023-07-23 14:29:56.383093673 +0900
@@ -71,6 +71,10 @@ void drm_vblank_cancel_pending_works(str
{
struct drm_vblank_work *work, *next;
+ if (!vblank->dev) {
+ printk(KERN_WARNING "%s: vblank->dev == NULL? returning\n",
__func__);
+ return;
+ }
assert_spin_locked(&vblank->dev->event_lock);
list_for_each_entry_safe(work, next, &vblank->pending_work, node) {
This time, the printk trap does not happen!! and radeon.ko works.
(NULL check for vblank->worker is still fireing though)
Now this is puzzling.
Is this a timing issue?
Is systemd-udevd doing something not favaorble to kernel?
Is drm vblank code running without enough initialization?
Puzzling is, that purely useland activity
(logging in on tty1 before radeon.ko load)
is affecting kernel panic/no-panic.
--
kabe[0.00] Linux version 5.18.0-13.4.el9.v1.i586 (k...@rocky9.five.ten)
(gcc (GCC) 11.3.1 20221121 (Red Hat 11.3.1-4), GNU ld version 2.35.2-24.el9.v1)
#1 SMP PREEMPT_DYNAMIC Sun Jul 23 11:55:32 JST 2023
[0.00] x86/fpu: x87 FPU will use FSAVE
[0.00] signal: max sigframe size: 928
[0.00] BIOS-provided physical RAM map:
[0.00] BIOS-e820: [mem 0x-0x0009fbff] usable
[0.00] BIOS-e820: [mem 0x0009fc00-0x0009] reserved
[0.00] BIOS-e820: [mem 0x000e-0x000f] reserved
[0.00] BIOS-e820: [mem 0x0010-0x3ffe] usable
[0.00] BIOS-e820: [mem 0x3fff-0x3fff7fff] ACPI data
[0.00] BIOS-e820: [mem 0x3fff8000-0x3fff] ACPI NVS
[0.00] BIOS-e820: [mem 0xfec0-0xfec00fff] reserved
[0.00] BIOS-e820: [mem 0xfee0-0xfee00fff] reserved
[0.00] BIOS-e820: [mem 0xfffe-0x] reserved
[0.00] Notice: NX (Execute Disable) protection missing in CPU!
[0.00] Legacy DMI 2.0 present.
[0.00] DMI: System Manufacturer System Name/ALADDIN5, BIOS 0626 07/15/95
[0.00] tsc: Fast TSC calibration using PIT
[0.00] tsc: Detected 120.091 MHz processor
[0.035691] last_pfn = 0x3fff0 max_arch_pfn = 0x10
[0.035797] Disabled
[0.035867] x86/PAT: MTRRs disabled, skipping PAT initialization too.
[0.035967] x86/PAT: Configuration [0-7]: WB WT UC- UC WB WT UC- UC
[0.114904] RAMDISK: [mem 0x360a5000-0x3704afff]
[0.115027] Allocated new RAMDISK: [mem 0x350ff000-0x360a47e0]
[1.057630] Move RAMDISK from [mem 0x360a5000-0x3704a7e0] to [mem
0x350ff000-0x360a47e0]
[1.057799] ACPI: Early table checksum verification disabled
[1.058084] ACPI: RSDP 0x000F6DF0 14 (v00 AMIINT)
[1.058297] ACPI: RSDT 0x3FFF 28 (v01 ALi_
MSFT 0097)
[1.058576] ACPI: FACP 0x3FFF0030 74 (v01 ALi_
MSFT 0097)
[1.058886] ACPI: DSDT 0x3FFF00B0 001FAA (v01 MSIMSI-5169
1000 MSFT 010A)
[1.059139] ACPI: FACS 0x3FFF8000 40
[1.059335] ACPI: Reserving FACP table memory at [mem 0x3fff0030-0x3fff00a3]
[1.059451] ACPI: Reserving DSDT table memory at [mem 0x3fff00b0-0x3fff2059]
[1.059560] ACPI: Reserving FACS table memory at [mem 0x3fff80
[PATCH] drm/radeon: Move assignment outside if condition
Fixes the following checkpatch errors:
ERROR: do not use assignment in if condition
Signed-off-by: Ran Sun
---
drivers/gpu/drm/radeon/radeon_legacy_tv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
index 12e180b119ac..7883e9ec0bae 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -724,12 +724,14 @@ void radeon_legacy_tv_mode_set(struct drm_encoder
*encoder,
}
for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) {
- if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0)
+ tv_dac->tv.h_code_timing[i] = hor_timing[i];
+ if (tv_dac->tv.h_code_timing[i] == 0)
break;
}
for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) {
- if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0)
+ tv_dac->tv.v_code_timing[i] = vert_timing[i];
+ if (tv_dac->tv.v_code_timing[i] == 0)
break;
}
[PATCH] drm/radeon: that open brace { should be on the previous line
ERROR: that open brace { should be on the previous line
Signed-off-by: Ran Sun
---
drivers/gpu/drm/radeon/clearstate_si.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/clearstate_si.h
b/drivers/gpu/drm/radeon/clearstate_si.h
index 356219c6c7f2..7da8418704fe 100644
--- a/drivers/gpu/drm/radeon/clearstate_si.h
+++ b/drivers/gpu/drm/radeon/clearstate_si.h
@@ -23,8 +23,7 @@
#include "clearstate_defs.h"
-static const u32 si_SECT_CONTEXT_def_1[] =
-{
+static const u32 si_SECT_CONTEXT_def_1[] = {
0x, // DB_RENDER_CONTROL
0x, // DB_COUNT_CONTROL
0x, // DB_DEPTH_VIEW
Re: radeon.ko/i586: BUG: kernel NULL pointer dereference,address:00000004
On Sun, 23 Jul 2023 20:55:06 +0900
wrote:
> So I tried to trap NULL and return:
>
> patch-drm_vblank_cancel_pending_works-printk-NULL-ret.patch
> diff -up ./drivers/gpu/drm/drm_vblank_work.c.pk2
> ./drivers/gpu/drm/drm_vblank_work.c
> --- ./drivers/gpu/drm/drm_vblank_work.c.pk2 2023-06-06 20:50:40.0
> +0900
> +++ ./drivers/gpu/drm/drm_vblank_work.c 2023-07-23 14:29:56.383093673
> +0900
> @@ -71,6 +71,10 @@ void drm_vblank_cancel_pending_works(str
> {
> struct drm_vblank_work *work, *next;
>
> + if (!vblank->dev) {
> + printk(KERN_WARNING "%s: vblank->dev == NULL? returning\n",
> __func__);
> + return;
> + }
> assert_spin_locked(&vblank->dev->event_lock);
>
> list_for_each_entry_safe(work, next, &vblank->pending_work, node) {
>
>
> This time, the printk trap does not happen!! and radeon.ko works.
> (NULL check for vblank->worker is still fireing though)
>
> Now this is puzzling.
> Is this a timing issue?
It could very well be. And the ftrace patch could possibly not be the
cause at all. But the thread that is created to do the work is causing
the race window to be opened up, which is why you see it with the patch
and don't without it. It may not be the problem, it may just tickle the
timings enough to trigger the bug, and is causing you to go on a wild
goose chase in the wrong direction.
-- Steve
> Is systemd-udevd doing something not favaorble to kernel?
> Is drm vblank code running without enough initialization?
>
> Puzzling is, that purely useland activity
> (logging in on tty1 before radeon.ko load)
> is affecting kernel panic/no-panic.
[PATCH] drm/amd/pm: open brace '{' following function definitions go on the next line
ERROR: open brace '{' following function definitions go on the next line
Signed-off-by: Ran Sun
---
drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
index c788aa7a99a9..5e408a195860 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
@@ -205,7 +205,8 @@ int smu_v12_0_set_default_dpm_tables(struct
smu_context *smu)
return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
smu_table->clocks_table, false);
}
-int smu_v12_0_mode2_reset(struct smu_context *smu){
+int smu_v12_0_mode2_reset(struct smu_context *smu)
+{
return smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
}
[PATCH] drm/radeon: add missing spaces after ',' and else should follow close brace '}'
ERROR: else should follow close brace '}'
ERROR: space required after that ',' (ctx:VxV)
Signed-off-by: Ran Sun
---
drivers/gpu/drm/radeon/radeon_connectors.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 07193cd0c417..4ceceb972e8d 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -198,8 +198,7 @@ int radeon_get_monitor_bpc(struct drm_connector
*connector)
DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using
%d bpc.\n",
connector->name, bpc);
}
- }
- else if (bpc > 8) {
+ } else if (bpc > 8) {
/* max_tmds_clock missing, but hdmi spec mandates it for deep color.
*/
DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing.
Using 8 bpc.\n",
connector->name);
@@ -1372,7 +1371,7 @@ radeon_dvi_detect(struct drm_connector *connector,
bool force)
/* assume digital unless load detected
otherwise */
radeon_connector->use_digital = true;
lret = encoder_funcs->detect(encoder,
connector);
- DRM_DEBUG_KMS("load_detect %x returned:
%x\n",encoder->encoder_type,lret);
+ DRM_DEBUG_KMS("load_detect %x returned: %x\n",
encoder->encoder_type, lret);
if (lret == connector_status_connected)
radeon_connector->use_digital =
false;
}
[PATCH] drm/amd/pm: Clean up errors in navi10_ppt.c
Fix the following errors reported by checkpatch:
ERROR: open brace '{' following function definitions go on the next line
ERROR: space required before the open parenthesis '('
ERROR: space required after that ',' (ctx:VxV)
ERROR: spaces required around that '=' (ctx:VxW)
Signed-off-by: Ran Sun
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 25 ++-
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 95f6d821bacb..e655071516b7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -136,7 +136,7 @@ static struct cmn2asic_msg_mapping
navi10_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg,
0),
MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME,
0),
MSG_MAP(ArmD3, PPSMC_MSG_ArmD3,
0),
-
MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange,
0),
+ MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,
PPSMC_MSG_DALDisableDummyPstateChange, 0),
MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0),
MSG_MAP(GetVoltageByDpm,PPSMC_MSG_GetVoltageByDpm,
0),
MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
@@ -556,7 +556,7 @@ static int navi10_get_legacy_smu_metrics_data(struct
smu_context *smu,
MetricsMember_t member,
uint32_t *value)
{
- struct smu_table_context *smu_table= &smu->smu_table;
+ struct smu_table_context *smu_table = &smu->smu_table;
SmuMetrics_legacy_t *metrics =
(SmuMetrics_legacy_t *)smu_table->metrics_table;
int ret = 0;
@@ -642,7 +642,7 @@ static int navi10_get_smu_metrics_data(struct
smu_context *smu,
MetricsMember_t member,
uint32_t *value)
{
- struct smu_table_context *smu_table= &smu->smu_table;
+ struct smu_table_context *smu_table = &smu->smu_table;
SmuMetrics_t *metrics =
(SmuMetrics_t *)smu_table->metrics_table;
int ret = 0;
@@ -731,7 +731,7 @@ static int navi12_get_legacy_smu_metrics_data(struct
smu_context *smu,
MetricsMember_t member,
uint32_t *value)
{
- struct smu_table_context *smu_table= &smu->smu_table;
+ struct smu_table_context *smu_table = &smu->smu_table;
SmuMetrics_NV12_legacy_t *metrics =
(SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
int ret = 0;
@@ -817,7 +817,7 @@ static int navi12_get_smu_metrics_data(struct
smu_context *smu,
MetricsMember_t member,
uint32_t *value)
{
- struct smu_table_context *smu_table= &smu->smu_table;
+ struct smu_table_context *smu_table = &smu->smu_table;
SmuMetrics_NV12_t *metrics =
(SmuMetrics_NV12_t *)smu_table->metrics_table;
int ret = 0;
@@ -1686,7 +1686,7 @@ static int navi10_force_clk_levels(struct
smu_context *smu,
return 0;
break;
case SMU_DCEFCLK:
- dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not
supported!\n");
+ dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not
supported!\n");
break;
default:
@@ -2182,7 +2182,7 @@ static int navi10_read_sensor(struct smu_context
*smu,
struct smu_table_context *table_context = &smu->smu_table;
PPTable_t *pptable = table_context->driver_pptable;
- if(!data || !size)
+ if (!data || !size)
return -EINVAL;
switch (sensor) {
@@ -2317,15 +2317,15 @@ static int
navi10_display_disable_memory_clock_switch(struct smu_context *smu,
uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
uint32_t max_memory_clock = max_sustainable_clocks->uclock;
- if(smu->disable_uclk_switch == disable_memory_clock_switch)
+ if (smu->disable_uclk_switch == disable_memory_clock_switch)
return 0;
- if(disable_memory_clock_switch)
+ if (disable_memory_clock_switch)
ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK,
max_memory_clock, 0);
else
ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK,
min_memory_clock, 0);
- if(!ret)
+ if (!ret)
smu->disable_uclk_switch = disable_memory_clock_switch;
return ret;
@@ -2559,7 +2559,8 @@ static int navi10_set_default_od_settings(struct
smu_context *smu)
return 0;
}
-static int
[PATCH] drm/amd/pm: Clean up errors in smu11_driver_if_sienna_cichlid.h
Fix the following errors reported by checkpatch:
ERROR: trailing whitespace
Signed-off-by: Ran Sun
---
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
index c5e26d619bf0..8ec588248aac 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
@@ -30,7 +30,7 @@
#define ENABLE_DEBUG_FEATURES
-// Firmware features
+// Firmware features
// Feature Control Defines
#define FEATURE_CCLK_DPM_BIT 0
#define FEATURE_FAN_CONTROLLER_BIT 1
@@ -92,7 +92,7 @@
#define FEATURE_ZSTATES_ECO_BIT 57
#define FEATURE_CC6_BIT 58
#define FEATURE_DS_UMCCLK_BIT 59
-#define FEATURE_DS_HSPCLK_BIT 60
+#define FEATURE_DS_HSPCLK_BIT 60
#define NUM_FEATURES61
typedef struct {
[PATCH] drm/amd/pm: Clean up errors in sienna_cichlid_ppt.c
Fix the following errors reported by checkpatch:
ERROR: space required after that ',' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '=' (ctx:VxW)
Signed-off-by: Ran Sun
---
.../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 0cda3b276f61..5c233eda09ee 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -78,7 +78,7 @@
(*member) = (smu->smu_table.driver_pptable +
offsetof(PPTable_beige_goby_t, field));\
else\
(*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t,
field));\
-} while(0)
+} while (0)
/* STB FIFO depth is in 64bit units */
#define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
@@ -590,7 +590,7 @@ static int sienna_cichlid_tables_init(struct
smu_context *smu)
static uint32_t sienna_cichlid_get_throttler_status_locked(struct
smu_context *smu)
{
- struct smu_table_context *smu_table= &smu->smu_table;
+ struct smu_table_context *smu_tabl = &smu->smu_table;
SmuMetricsExternal_t *metrics_ext =
(SmuMetricsExternal_t *)(smu_table->metrics_table);
uint32_t throttler_status = 0;
@@ -711,7 +711,7 @@ static int
sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
MetricsMember_t member,
uint32_t *value)
{
- struct smu_table_context *smu_table= &smu->smu_table;
+ struct smu_table_context *smu_table = &smu->smu_table;
SmuMetrics_t *metrics =
&(((SmuMetricsExternal_t
*)(smu_table->metrics_table))->SmuMetrics);
SmuMetrics_V2_t *metrics_v2 =
@@ -1461,7 +1461,7 @@ static int sienna_cichlid_force_clk_levels(struct
smu_context *smu,
goto forec_level_out;
break;
case SMU_DCEFCLK:
- dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not
supported!\n");
+ dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not
supported!\n");
break;
default:
break;
@@ -1881,7 +1881,7 @@ static int sienna_cichlid_read_sensor(struct
smu_context *smu,
uint16_t *temp;
struct amdgpu_device *adev = smu->adev;
- if(!data || !size)
+ if (!data || !size)
return -EINVAL;
switch (sensor) {
@@ -2067,15 +2067,15 @@ static int
sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
uint32_t max_memory_clock = max_sustainable_clocks->uclock;
- if(smu->disable_uclk_switch == disable_memory_clock_switch)
+ if (smu->disable_uclk_switch == disable_memory_clock_switch)
return 0;
- if(disable_memory_clock_switch)
+ if (disable_memory_clock_switch)
ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK,
max_memory_clock, 0);
else
ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK,
min_memory_clock, 0);
- if(!ret)
+ if (!ret)
smu->disable_uclk_switch = disable_memory_clock_switch;
return ret;
[PATCH] drm/amd/pm: Clean up errors in arcturus_ppt.c
Fix the following errors reported by checkpatch:
ERROR: spaces required around that '=' (ctx:VxW)
ERROR: spaces required around that '>=' (ctx:WxV)
Signed-off-by: Ran Sun
---
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 3bb18396d2f9..c49f770c97b3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -598,7 +598,7 @@ static int arcturus_get_smu_metrics_data(struct
smu_context *smu,
MetricsMember_t member,
uint32_t *value)
{
- struct smu_table_context *smu_table= &smu->smu_table;
+ struct smu_table_context *smu_table = &smu->smu_table;
SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
int ret = 0;
@@ -1482,7 +1482,7 @@ static int arcturus_set_power_profile_mode(struct
smu_context *smu,
return ret;
if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
-(smu_version >=0x360d00)) {
+(smu_version >= 0x360d00)) {
ret = smu_cmn_update_table(smu,
SMU_TABLE_ACTIVITY_MONITOR_COEFF,
WORKLOAD_PPLIB_CUSTOM_BIT,
Re: [PATCH V7 4/9] wifi: mac80211: Add support for ACPI WBRF
> @@ -1395,6 +1395,8 @@ int ieee80211_register_hw(struct ieee80211_hw *hw)
> debugfs_hw_add(local);
> rate_control_add_debugfs(local);
>
> + ieee80211_check_wbrf_support(local);
> +
> rtnl_lock();
> wiphy_lock(hw->wiphy);
>
> +void ieee80211_check_wbrf_support(struct ieee80211_local *local)
> +{
> + struct wiphy *wiphy = local->hw.wiphy;
> + struct device *dev;
> +
> + if (!wiphy)
> + return;
> +
> + dev = wiphy->dev.parent;
> + if (!dev)
> + return;
> +
> + local->wbrf_supported = wbrf_supported_producer(dev);
> + dev_dbg(dev, "WBRF is %s supported\n",
> + local->wbrf_supported ? "" : "not");
> +}
This seems wrong. wbrf_supported_producer() is about "Should this
device report the frequencies it is using?" The answer to that depends
on a combination of: Are there consumers registered with the core, and
is the policy set so WBRF should take actions.
The problem here is, you have no idea of the probe order. It could be
this device probes before others, so wbrf_supported_producer() reports
false, but a few second later would report true, once other devices
have probed.
It should be an inexpensive call into the core, so can be made every
time the channel changes. All the core needs to do is check if the
list of consumers is empty, and if not, check a Boolean policy value.
Andrew
[PATCH] drm/amd/pm: add missing spaces before '('
ERROR: space required before the open parenthesis '('
Signed-off-by: Ran Sun
---
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 8a8ba25c9ad7..a7569354229d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -262,15 +262,15 @@ static int renoir_get_profiling_clk_mask(struct
smu_context *smu,
/* mclk levels are in reverse order */
*mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
- if(sclk_mask)
+ if (sclk_mask)
/* The sclk as gfxclk and has three level about
max/min/current */
*sclk_mask = 3 - 1;
- if(mclk_mask)
+ if (mclk_mask)
/* mclk levels are in reverse order */
*mclk_mask = 0;
- if(soc_mask)
+ if (soc_mask)
*soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
}
Re: radeon.ko/i586: BUG: kernel NULL pointer dereference, address:00000004
rost...@goodmis.org sed in <20230717113623.41878...@gandalf.local.home> >> On Fri, 14 Jul 2023 14:34:04 +0900 >> wrote: >> >> > Patch in >> > https://bugzilla.kernel.org/show_bug.cgi?id=217669#c4 >> > fixed the problem in freedesktop.org kernel 5.18.0-rc2 . >> > This may explain that in kernel.org tree, the said commit is in >> > kernel-5.19. >> >> You mean the patch that adds: >> >> #if defined(FTRACE_MCOUNT_MAX_OFFSET) && (FTRACE_MCOUNT_MAX_OFFSET) >> >> ? >> >> Nothing should be setting FTRACE_MCOUNT_MAX_OFFSET to anything but non >> zero. But doing a grep, I now see: >> >> # define FTRACE_MCOUNT_MAX_OFFSET ENDBR_INSN_SIZE >> >> Where it breaks that assumption if ENDBR_INSN_SIZE == 0 :-p >> (and that's my code!) >> >> OK, does this fix it? (I haven't tested nor compiled this) >> >> -- Steve >> >> diff --git a/arch/x86/include/asm/ftrace.h b/arch/x86/include/asm/ftrace.h >> index 897cf02c20b1..801f4414da3e 100644 >> --- a/arch/x86/include/asm/ftrace.h >> +++ b/arch/x86/include/asm/ftrace.h >> @@ -13,7 +13,7 @@ >> #ifdef CONFIG_HAVE_FENTRY >> # include >> /* Add offset for endbr64 if IBT enabled */ >> -# define FTRACE_MCOUNT_MAX_OFFSET ENDBR_INSN_SIZE >> +# define FTRACE_MCOUNT_MAX_OFFSET (ENDBR_INSN_SIZE + MCOUNT_INSN_SIZE) >> #endif >> >> #ifdef CONFIG_DYNAMIC_FTRACE >> Above patch didn't work, but Does it matter that I am compiling with "gcc -fcf-protection=none" to not emit endbr32 instructions for i586? -- kabe
[PATCH] drm/radeon: add missing spaces before ';'
ERROR: space required after that ';' (ctx:BxV) Signed-off-by: Ran Sun --- drivers/gpu/drm/radeon/radeon_vce.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index ca4a36464340..d1871af967d4 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c @@ -95,7 +95,7 @@ int radeon_vce_init(struct radeon_device *rdev) size = rdev->vce_fw->size - strlen(fw_version) - 9; c = rdev->vce_fw->data; - for (;size > 0; --size, ++c) + for (; size > 0; --size, ++c) if (strncmp(c, fw_version, strlen(fw_version)) == 0) break; @@ -110,7 +110,7 @@ int radeon_vce_init(struct radeon_device *rdev) size = rdev->vce_fw->size - strlen(fb_version) - 3; c = rdev->vce_fw->data; - for (;size > 0; --size, ++c) + for (; size > 0; --size, ++c) if (strncmp(c, fb_version, strlen(fb_version)) == 0) break;
[PATCH] drm/amd/pm: Clean up errors in smu11_driver_if_sienna_cichlid.h
Fix the following errors reported by checkpatch:
ERROR: trailing whitespace
ERROR: space prohibited before open square bracket '['
ERROR: space prohibited before that close square bracket ']'
Signed-off-by: Ran Sun
---
.../pmfw_if/smu11_driver_if_sienna_cichlid.h | 386 +-
1 file changed, 193 insertions(+), 193 deletions(-)
diff --git
a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
index aa6d29de4002..703ade13d9f4 100644
---
a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
+++
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
@@ -225,33 +225,33 @@ typedef enum {
#define FW_DSTATE_MP1_WHISPER_MODE_BIT 6
#define FW_DSTATE_SOC_LIV_MIN_BIT 7
#define FW_DSTATE_SOC_PLL_PWRDN_BIT 8
-#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9
+#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9
#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10
#define FW_DSTATE_MEM_PSI_BIT 11
#define FW_DSTATE_HSR_NON_STROBE_BIT12
#define FW_DSTATE_MP0_ENTER_WFI_BIT 13
-#define FW_DSTATE_SOC_ULV_MASK(1 <<
FW_DSTATE_SOC_ULV_BIT )
-#define FW_DSTATE_G6_HSR_MASK (1 <<
FW_DSTATE_G6_HSR_BIT )
-#define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 <<
FW_DSTATE_G6_PHY_VDDCI_OFF_BIT )
-#define FW_DSTATE_MP1_DS_MASK (1 <<
FW_DSTATE_MP1_DS_BIT )
-#define FW_DSTATE_MP0_DS_MASK (1 <<
FW_DSTATE_MP0_DS_BIT )
-#define FW_DSTATE_SMN_DS_MASK (1 <<
FW_DSTATE_SMN_DS_BIT )
-#define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 <<
FW_DSTATE_MP1_WHISPER_MODE_BIT )
-#define FW_DSTATE_SOC_LIV_MIN_MASK(1 <<
FW_DSTATE_SOC_LIV_MIN_BIT )
-#define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 <<
FW_DSTATE_SOC_PLL_PWRDN_BIT)
-#define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 <<
FW_DSTATE_MEM_PLL_PWRDN_BIT)
-#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 <<
FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT)
-#define FW_DSTATE_MEM_PSI_MASK(1 <<
FW_DSTATE_MEM_PSI_BIT)
-#define FW_DSTATE_HSR_NON_STROBE_MASK (1 <<
FW_DSTATE_HSR_NON_STROBE_BIT)
-#define FW_DSTATE_MP0_ENTER_WFI_MASK (1 <<
FW_DSTATE_MP0_ENTER_WFI_BIT)
+#define FW_DSTATE_SOC_ULV_MASK(1 <<
FW_DSTATE_SOC_ULV_BIT)
+#define FW_DSTATE_G6_HSR_MASK (1 <<
FW_DSTATE_G6_HSR_BIT)
+#define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 <<
FW_DSTATE_G6_PHY_VDDCI_OFF_BIT)
+#define FW_DSTATE_MP1_DS_MASK (1 <<
FW_DSTATE_MP1_DS_BIT)
+#define FW_DSTATE_MP0_DS_MASK (1 <<
FW_DSTATE_MP0_DS_BIT)
+#define FW_DSTATE_SMN_DS_MASK (1 <<
FW_DSTATE_SMN_DS_BIT)
+#define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 <<
FW_DSTATE_MP1_WHISPER_MODE_BIT)
+#define FW_DSTATE_SOC_LIV_MIN_MASK(1 <<
FW_DSTATE_SOC_LIV_MIN_BIT)
+#define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 <<
FW_DSTATE_SOC_PLL_PWRDN_BIT)
+#define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 <<
FW_DSTATE_MEM_PLL_PWRDN_BIT)
+#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 <<
FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT)
+#define FW_DSTATE_MEM_PSI_MASK(1 <<
FW_DSTATE_MEM_PSI_BIT)
+#define FW_DSTATE_HSR_NON_STROBE_MASK (1 <<
FW_DSTATE_HSR_NON_STROBE_BIT)
+#define FW_DSTATE_MP0_ENTER_WFI_MASK (1 <<
FW_DSTATE_MP0_ENTER_WFI_BIT)
// GFX GPO Feature Contains PACE and DEM sub features
#define GFX_GPO_PACE_BIT 0
#define GFX_GPO_DEM_BIT1
#define GFX_GPO_PACE_MASK (1 << GFX_GPO_PACE_BIT)
-#define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT )
+#define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT)
#define GPO_UPDATE_REQ_UCLKDPM_MASK 0x1
#define GPO_UPDATE_REQ_FCLKDPM_MASK 0x2
@@ -312,10 +312,10 @@ typedef enum {
I2C_CONTROLLER_NAME_VR_VDDCI,
I2C_CONTROLLER_NAME_VR_MVDD,
I2C_CONTROLLER_NAME_LIQUID0,
- I2C_CONTROLLER_NAME_LIQUID1,
+ I2C_CONTROLLER_NAME_LIQUID1,
I2C_CONTROLLER_NAME_PLX,
I2C_CONTROLLER_NAME_OTHER,
- I2C_CONTROLLER_NAME_COUNT,
+ I2C_CONTROLLER_NAME_COUNT,
} I2cControllerName_e;
typedef enum {
@@ -325,10 +325,10 @@ typedef enum {
I2C_CONTROLLER_THROTTLER_VR_VDDCI,
I2C_CONTROLLER_THROTTLER_VR_MVDD,
I2C_CONTROLLER_THROTTLER_LIQUID0,
- I2C_CONTROLLER_THROTTLER_LIQUID1,
+ I2C_CONTROLLER_THROTTLER_LIQUID1,
I2C_CONTROLLER_THROTTLER_PLX,
I2C_CONTROLLER_THROTTLER_INA3221,
- I2C_CONTROLLER_THROTTLER_COUNT,
+ I2C_CONTROLLER_THROTTLER_COUNT,
} I2cControllerThrottler_e;
typedef enum {
@@ -336,24 +336,24 @@ typedef enum {
I2C_CONTROLLER_PROTOCOL_VR_IR35217,
I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
I2C_CONTROLLER_PROTOCOL_I
Re: radeon.ko/i586: BUG: kernel NULL pointerdereference, address:00000004
rost...@goodmis.org sed in <20230717112138.1fd48...@gandalf.local.home>
>> On Sat, 15 Jul 2023 11:39:11 +0900
>> wrote:
>>
>>
>> > Yes, this is puzzling. That's why I need other people's opinion on this.
>> > Does it matter the DUT is a slow machine (Pentium 120MHz)?
>> >
>>
>> Hmm, I wonder because the workqueue is running __init functions, could it
>> possibly be that it didn't finish before the end of boot, where it frees
>> all the functions? It shouldn't do that because there's code to make sure
>> it's done before it continues further.
>>
>> But just in case something isn't working as planned, you could try this
>> patch to see if the bug goes away.
>>
>> -- Steve
>>
>> diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
>> index 05c0024815bf..af5a40ef3be4 100644
>> --- a/kernel/trace/ftrace.c
>> +++ b/kernel/trace/ftrace.c
>> @@ -3771,13 +3771,13 @@ static int test_for_valid_rec(struct dyn_ftrace *rec)
>> return 1;
>> }
>>
>> -static struct workqueue_struct *ftrace_check_wq __initdata;
>> -static struct work_struct ftrace_check_work __initdata;
>> +static struct workqueue_struct *ftrace_check_wq;
>> +static struct work_struct ftrace_check_work;
>>
>> /*
>> * Scan all the mcount/fentry entries to make sure they are valid.
>> */
>> -static __init void ftrace_check_work_func(struct work_struct *work)
>> +static void ftrace_check_work_func(struct work_struct *work)
>> {
>> struct ftrace_page *pg;
>> struct dyn_ftrace *rec;
>>
Just in case I tried this patch too;
no banana, it panics (vblank->worker == NULL check fires)
--
kabe
[PATCH] drm/amd/pm: that open brace { should be on the previous line
ERROR: that open brace { should be on the previous line
Signed-off-by: Ran Sun
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_11_0_cdr_table.h | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_11_0_cdr_table.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_11_0_cdr_table.h
index beab6d7b28b7..630132c4a76b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_11_0_cdr_table.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_11_0_cdr_table.h
@@ -52,8 +52,7 @@ static unsigned int DbiPrbs7[] =
//4096 bytes, 256 byte aligned
-static unsigned int NoDbiPrbs7[] =
-{
+static unsigned int NoDbiPrbs7[] = {
0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f00f0f, 0x0f0f0f0f,
0x0f0f0f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f00f0f, 0xf0f00f0f,
0x0f0f0f0f, 0xf0f0f0f0, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f00f0f,
0x0f0f0f0f, 0xf0f00f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0,
0xf0f00f0f, 0xf0f00f0f, 0xf0f00f0f, 0x0f0ff0f0, 0xf0f0f0f0, 0xf0f0f0f0,
0x0f0ff0f0, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f0f0f0, 0xf0f00f0f,
0x0f0f0f0f, 0xf0f00f0f, 0x0f0ff0f0, 0x0f0f0f0f, 0xf0f0f0f0,
0x0f0ff0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf0f0f0f0, 0x0f0ff0f0, 0xf0f0f0f0,
0xf0f00f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0x0f0ff0f0, 0xf0f00f0f,
@@ -121,8 +120,7 @@ static unsigned int NoDbiPrbs7[] =
};
// 4096 bytes, 256 byte aligned
-static unsigned int DbiPrbs7[] =
-{
+static unsigned int DbiPrbs7[] = {
0x, 0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x, 0x,
[PATCH] drm/amd/pm:open brace '{' following function definitions go on the next line
ERROR: open brace '{' following function definitions go on the next line
Signed-off-by: Ran Sun
---
drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
index c788aa7a99a9..5e408a195860 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
@@ -205,7 +205,8 @@ int smu_v12_0_set_default_dpm_tables(struct
smu_context *smu)
return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
smu_table->clocks_table, false);
}
-int smu_v12_0_mode2_reset(struct smu_context *smu){
+int smu_v12_0_mode2_reset(struct smu_context *smu)
+{
return smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
}
Re: [PATCH v3 0/9] PCI/VGA: Improve the default VGA device selection
Hi,
On 2023/7/20 03:32, Bjorn Helgaas wrote:
"drm/loongson: Add an implement for ..." also solves a problem, but it
lacks a commit log, so I don't know what the problem is.
I have already telling you one yeas ago.
I want remove the pci_fixup_vgadev() function in arch/loongarch/pci/pci.c
I was the original author of this workaround at our downstream kernel.
While the time is not mature until this patch set be merged.
I don't want mention this, as you asked this question.
So, I think I have to explain.
-static void pci_fixup_vgadev(struct pci_dev *pdev)
-{
- struct pci_dev *devp = NULL;
-
- while ((devp = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, devp))) {
- if (devp->vendor != PCI_VENDOR_ID_LOONGSON) {
- vga_set_default_device(devp);
- dev_info(&pdev->dev,
- "Overriding boot device as %X:%X\n",
- devp->vendor, devp->device);
- }
- }
-}
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
PCI_DEVICE_ID_LOONGSON_DC1, pci_fixup_vgadev);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
PCI_DEVICE_ID_LOONGSON_DC2, pci_fixup_vgadev);
Re: [PATCH v3 4/9] PCI/VGA: Improve the default VGA device selection
Hi,
Thanks for you noticed my change.
On 2023/7/20 03:32, Bjorn Helgaas wrote:
@@ -1509,13 +1543,24 @@ static int pci_notify(struct notifier_block *nb,
unsigned long action,
* cases of hotplugable vga cards.
*/
- if (action == BUS_NOTIFY_ADD_DEVICE)
+ switch (action) {
+ case BUS_NOTIFY_ADD_DEVICE:
notify = vga_arbiter_add_pci_device(pdev);
- else if (action == BUS_NOTIFY_DEL_DEVICE)
+ if (notify)
+ vga_arbiter_notify_clients();
+ break;
+ case BUS_NOTIFY_DEL_DEVICE:
notify = vga_arbiter_del_pci_device(pdev);
+ if (notify)
+ vga_arbiter_notify_clients();
+ break;
+ case BUS_NOTIFY_BOUND_DRIVER:
+ vga_arbiter_do_arbitration(pdev);
+ break;
+ default:
+ break;
+ }
Changing from if/else to switch makes the patch bigger than necessary
for no real benefit and obscures what is really changing.
Actually, the logic become more clear after this patch applied.
```
switch (action) {
case BUS_NOTIFY_ADD_DEVICE:
notify = vga_arbiter_add_pci_device(pdev);
if (notify)
vga_arbiter_notify_clients();
break;
case BUS_NOTIFY_DEL_DEVICE:
notify = vga_arbiter_del_pci_device(pdev);
if (notify)
vga_arbiter_notify_clients();
break;
case BUS_NOTIFY_BOUND_DRIVER:
vga_arbiter_do_arbitration(pdev);
break;
default:
break;
}
```
Because we only need call vga_arbiter_notify_clients() when action ==
BUS_NOTIFY_ADD_DEVICE or action == BUS_NOTIFY_DEL_DEVICE,
But *NOT* when the action equals to BUS_NOTIFY_BOUND_DRIVER.
Re: [PATCH v3 4/9] PCI/VGA: Improve the default VGA device selection
Hi, On 2023/7/20 03:32, Bjorn Helgaas wrote: 2) It does not take the PCI Bar may get relocated into consideration. 3) It is not effective for the PCI device without a dedicated VRAM Bar. 4) It is device-agnostic, thus it has to waste the effort to iterate all of the PCI Bar to find the VRAM aperture. 5) It has invented lots of methods to determine which one is the default boot device, but this is still a policy because it doesn't give the user a choice to override. I don't think we need a list of*potential* problems. We need an example of the specific problem this will solve, i.e., what currently does not work? This version do allow the arbitration service works on non-x86 arch, which also allow me remove a arch-specific workaround. I will give more detail at the next version. But I want to provide one more drawback of vgaarb here: (6) It does not works for non VGA-compatible PCI(e) display controllers. Because, currently, vgaarb deal with PCI VGA compatible devices only. See another my patch set [1] for more elaborate discussion. It also ignore PCI_CLASS_NOT_DEFINED_VGA as Maciej puts it[2]. While my approach do not required the display controller to be VGA-compatible to enjoy the arbitration service. What do you think then? [1] https://patchwork.freedesktop.org/patch/546690/?series=120548&rev=1 [2] https://lkml.org/lkml/2023/6/18/315
Re: [PATCH] drm/amd/pm: Clean up errors in sienna_cichlid_ppt.c
Hi,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm/drm-next drm-exynos/exynos-drm-next
drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip
linus/master v6.5-rc3 next-20230724]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/sunran001-208suo-com/drm-amd-pm-Clean-up-errors-in-sienna_cichlid_ppt-c/20230724-153134
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/ea1cf43d5545fa917127694a294a57da%40208suo.com
patch subject: [PATCH] drm/amd/pm: Clean up errors in sienna_cichlid_ppt.c
config: i386-buildonly-randconfig-r004-20230724
(https://download.01.org/0day-ci/archive/20230724/202307241921.8w1kdtyk-...@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce:
(https://download.01.org/0day-ci/archive/20230724/202307241921.8w1kdtyk-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202307241921.8w1kdtyk-...@intel.com/
All warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c: In
function 'sienna_cichlid_get_throttler_status_locked':
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:595:42:
error: 'smu_table' undeclared (first use in this function)
595 | (SmuMetricsExternal_t *)(smu_table->metrics_table);
| ^
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:595:42:
note: each undeclared identifier is reported only once for each function it
appears in
>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:593:35:
>> warning: unused variable 'smu_tabl' [-Wunused-variable]
593 | struct smu_table_context *smu_tabl = &smu->smu_table;
| ^~~~
vim +/smu_tabl +593
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c
590
591 static uint32_t sienna_cichlid_get_throttler_status_locked(struct
smu_context *smu)
592 {
> 593 struct smu_table_context *smu_tabl = &smu->smu_table;
594 SmuMetricsExternal_t *metrics_ext =
595 (SmuMetricsExternal_t *)(smu_table->metrics_table);
596 uint32_t throttler_status = 0;
597 int i;
598
599 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0,
7)) &&
600 (smu->smc_fw_version >= 0x3A4900)) {
601 for (i = 0; i < THROTTLER_COUNT; i++)
602 throttler_status |=
603
(metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
604 } else if ((smu->adev->ip_versions[MP1_HWIP][0] ==
IP_VERSION(11, 0, 7)) &&
605 (smu->smc_fw_version >= 0x3A4300)) {
606 for (i = 0; i < THROTTLER_COUNT; i++)
607 throttler_status |=
608
(metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
609 } else {
610 throttler_status =
metrics_ext->SmuMetrics.ThrottlerStatus;
611 }
612
613 return throttler_status;
614 }
615
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Re: [PATCH v3 4/9] PCI/VGA: Improve the default VGA device selection
Hi, I was too hurry reply to you. I'm may miss the point for part of your reviews, Sorry. On 2023/7/20 03:32, Bjorn Helgaas wrote: CONFIG_DRM_AST is a tristate. We're talking about identifying the boot-time console device. Yes, my patch will only works *after* the module gets loaded successfully. But generally, vgaarb will select a default boot device before my patch taking into effect. I means that vgaarb will select a default boot device by calling vga_arbiter_add_pci_device() function. In practice, I still not notice any obvious problems. I'm lack the knowledge about the boot-time console, what is the potential problems with such a condition? So if CONFIG_DRM_AST=m, I guess we don't get the benefit of the new callback unless the module gets loaded? Yes, my approach will not works until the device driver kernel module gets loaded successfully. So what's the problem with such a situation, do you see something weird ?
Re: [PATCH] drm/amd/pm: Clean up errors in sienna_cichlid_ppt.c
Hi,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on drm/drm-next drm-exynos/exynos-drm-next
drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm-tip/drm-tip
linus/master v6.5-rc3 next-20230724]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/sunran001-208suo-com/drm-amd-pm-Clean-up-errors-in-sienna_cichlid_ppt-c/20230724-153134
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/ea1cf43d5545fa917127694a294a57da%40208suo.com
patch subject: [PATCH] drm/amd/pm: Clean up errors in sienna_cichlid_ppt.c
config: arc-randconfig-r024-20230724
(https://download.01.org/0day-ci/archive/20230724/202307241820.vkirpe2r-...@intel.com/config)
compiler: arceb-elf-gcc (GCC) 12.3.0
reproduce:
(https://download.01.org/0day-ci/archive/20230724/202307241820.vkirpe2r-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202307241820.vkirpe2r-...@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c: In
function 'sienna_cichlid_get_throttler_status_locked':
>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:595:42:
>> error: 'smu_table' undeclared (first use in this function)
595 | (SmuMetricsExternal_t *)(smu_table->metrics_table);
| ^
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:595:42:
note: each undeclared identifier is reported only once for each function it
appears in
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:593:35:
warning: unused variable 'smu_tabl' [-Wunused-variable]
593 | struct smu_table_context *smu_tabl = &smu->smu_table;
| ^~~~
vim +/smu_table +595
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c
b455159c053130d drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c Likun
Gao2020-05-29 590
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 591 static uint32_t
sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 592 {
34af41f9a039153 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
sunran...@208suo.com 2023-07-24 593struct smu_table_context *smu_tabl =
&smu->smu_table;
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 594SmuMetricsExternal_t *metrics_ext =
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 @595(SmuMetricsExternal_t
*)(smu_table->metrics_table);
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 596uint32_t throttler_status = 0;
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 597int i;
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 598
1d789535a03679e drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Alex
Deucher 2021-10-04 599if ((smu->adev->ip_versions[MP1_HWIP][0] ==
IP_VERSION(11, 0, 7)) &&
7952fa0d3e18750 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Danijel
Slivka 2022-03-02 600 (smu->smc_fw_version >= 0x3A4900)) {
7952fa0d3e18750 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Danijel
Slivka 2022-03-02 601for (i = 0; i < THROTTLER_COUNT; i++)
7952fa0d3e18750 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Danijel
Slivka 2022-03-02 602throttler_status |=
7952fa0d3e18750 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Danijel
Slivka 2022-03-02 603
(metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
7952fa0d3e18750 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Danijel
Slivka 2022-03-02 604} else if ((smu->adev->ip_versions[MP1_HWIP][0]
== IP_VERSION(11, 0, 7)) &&
be22e2b9f4f92ed drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c Evan
Quan2021-07-06 605 (smu->smc_fw_version >= 0x3A4300)) {
be22
Re: [PATCH AUTOSEL 6.1 28/41] Revert "drm/amd/display: Do not set drr on pipe commit"
On 7/24/23 03:21, Sasha Levin wrote: > From: Michel Dänzer > > [ Upstream commit 8e1b45c578b799510f9a01a9745a737e74f43cb1 ] > > This reverts commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be. The reverted commit is the same as patch 1 in this series... Same issue with the autosel patches for 6.4. -- Earthling Michel Dänzer| https://redhat.com Libre software enthusiast | Mesa and Xwayland developer
RE: [PATCH V2] drm/amdgpu: remove redundant variable declaration
[Public]
Reviewed-by: Guchun Chen
> -Original Message-
> From: Bob Zhou
> Sent: Monday, July 24, 2023 4:36 PM
> To: amd-gfx@lists.freedesktop.org; Pelloux-Prayer, Pierre-Eric eric.pelloux-pra...@amd.com>
> Cc: Chen, Guchun ; Zhou, Bob
>
> Subject: [PATCH V2] drm/amdgpu: remove redundant variable declaration
>
> building with gcc and W=1 reports
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:1618:15:
> error: unused variable 'domain' [-Werror=unused-variable] unsigned int
> domain;
> ^~
>
> The variable domain is repeated, so remove it.
>
> Fixes: d769528e4649 ("drm/amdgpu: add VISIBLE info in
> amdgpu_bo_print_info")
> Signed-off-by: Bob Zhou
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 5ac7544cc068..3f98174fb764 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -1578,7 +1578,6 @@ u64 amdgpu_bo_print_info(int id, struct
> amdgpu_bo *bo, struct seq_file *m) {
> struct dma_buf_attachment *attachment;
> struct dma_buf *dma_buf;
> - unsigned int domain;
> const char *placement;
> unsigned int pin_count;
> u64 size;
> --
> 2.34.1
[PATCH V2] drm/amdgpu: remove redundant variable declaration
building with gcc and W=1 reports
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:1618:15:
error: unused variable 'domain' [-Werror=unused-variable]
unsigned int domain;
^~
The variable domain is repeated, so remove it.
Fixes: d769528e4649 ("drm/amdgpu: add VISIBLE info in amdgpu_bo_print_info")
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5ac7544cc068..3f98174fb764 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1578,7 +1578,6 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo,
struct seq_file *m)
{
struct dma_buf_attachment *attachment;
struct dma_buf *dma_buf;
- unsigned int domain;
const char *placement;
unsigned int pin_count;
u64 size;
--
2.34.1
RE: [PATCH] drm/amdgpu: remove repeat variable domain
[Public]
Please add a Fixes tag like "Fixes: d769528e4649 ("drm/amdgpu: add VISIBLE info
in amdgpu_bo_print_info")" in commit message.
Regards,
Guchun
> -Original Message-
> From: Bob Zhou
> Sent: Monday, July 24, 2023 2:43 PM
> To: amd-gfx@lists.freedesktop.org; Pelloux-Prayer, Pierre-Eric eric.pelloux-pra...@amd.com>
> Cc: Chen, Guchun ; Zhou, Bob
>
> Subject: [PATCH] drm/amdgpu: remove repeat variable domain
>
> building with gcc and W=1 reports
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:1618:15:
> error: unused variable 'domain' [-Werror=unused-variable] unsigned int
> domain;
> ^~
>
> The variable domain is repeated, so remove it.
>
> Signed-off-by: Bob Zhou
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 5ac7544cc068..3f98174fb764 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -1578,7 +1578,6 @@ u64 amdgpu_bo_print_info(int id, struct
> amdgpu_bo *bo, struct seq_file *m) {
> struct dma_buf_attachment *attachment;
> struct dma_buf *dma_buf;
> - unsigned int domain;
> const char *placement;
> unsigned int pin_count;
> u64 size;
> --
> 2.34.1
RE: [PATCH] drm/amdgpu: Remove else after return in 'is_fru_eeprom_supported'
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Srinivasan Shanmugam
> Sent: Sunday, July 23, 2023 2:38 PM
> To: Koenig, Christian ; Deucher, Alexander
>
> Cc: SHANMUGAM, SRINIVASAN ;
> amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: Remove else after return in
> 'is_fru_eeprom_supported'
>
> Expressions under 'else' branch under case 'CHIP_SIENNA_CICHLID' in
> function 'is_fru_eeprom_supported' are executed whenever the expression
> in 'if' is False. Otherwise, return from case occurs. Therefore, there is no
> need in 'else', and it has been removed.
>
> Fixes the following:
>
> WARNING: else is not generally useful after a break or return
> + return false;
> + } else {
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> index c9f16eab0f3d..8c3ee042556a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
> @@ -83,11 +83,12 @@ static bool is_fru_eeprom_supported(struct
> amdgpu_device *adev, u32 *fru_addr)
> if (strnstr(atom_ctx->vbios_pn, "D603GLXE",
> sizeof(atom_ctx->vbios_pn))) {
> return false;
We can drop the {} for above if case, as it's only a single code line.
With that fixed, this patch is:
Reviewed-by: Guchun Chen
Regards,
Guchun
> - } else {
> - if (fru_addr)
> - *fru_addr = FRU_EEPROM_MADDR_6;
> - return true;
> }
> +
> + if (fru_addr)
> + *fru_addr = FRU_EEPROM_MADDR_6;
> + return true;
> +
> } else {
> return false;
> }
> --
> 2.25.1
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