RE: [PATCH] drm/amdgpu: Add timeout for sync wait
[AMD Official Use Only - General]
Hi Felix,
Yes, will correct the description. Will add another patch to handle the
return for sync wait.
Emily Deng
Best Wishes
>-Original Message-
>From: Kuehling, Felix
>Sent: Friday, October 20, 2023 12:05 AM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu: Add timeout for sync wait
>
>On 2023-10-19 05:31, Emily Deng wrote:
>> Issue: Dead heappen during gpu recover
>>
>> [56433.829492] amdgpu :04:00.0: amdgpu: GPU reset begin!
>> [56550.499625] INFO: task kworker/u80:0:10 blocked for more than 120
>seconds.
>> [56550.520215] Tainted: G OE 6.2.0-34-generic
>> #34~22.04.1-
>Ubuntu
>> [56550.542883] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs"
>disables this message.
>> [56550.566313] task:kworker/u80:0 state:D stack:0 pid:10ppid:2
>flags:0x4000
>> [56550.591318] Workqueue: kfd_restore_wq restore_process_worker
>> [amdgpu] [56550.611391] Call Trace:
>> [56550.618698]
>> [56550.624968] __schedule+0x2b7/0x5f0 [56550.635416]
>> schedule+0x68/0x110 [56550.645090] schedule_timeout+0x151/0x160
>> [56550.657096] ? amdgpu_vm_bo_update+0x46e/0x660 [amdgpu]
>> [56550.673245] dma_fence_default_wait+0x1a2/0x1e0
>> [56550.686818] ? __pfx_dma_fence_default_wait_cb+0x10/0x10
>> [56550.702728] dma_fence_wait_timeout+0x117/0x140
>> [56550.716301] amdgpu_sync_wait+0x62/0xa0 [amdgpu] [56550.730654]
>> amdgpu_amdkfd_gpuvm_restore_process_bos+0x59e/0x770 [amdgpu]
>> [56550.751668] ? newidle_balance+0x298/0x490 [56550.763936]
>> restore_process_worker+0x42/0x270 [amdgpu] [56550.780183]
>> process_one_work+0x21f/0x440 [56550.792193] worker_thread+0x50/0x3f0
>> [56550.803165] ? __pfx_worker_thread+0x10/0x10 [56550.815934]
>> kthread+0xee/0x120 [56550.825342] ? __pfx_kthread+0x10/0x10
>> [56550.836548] ret_from_fork+0x2c/0x50 [56550.847262] [
>> 1935.215502] Call Trace:
>> [ 1935.222827]
>> [ 1935.229121] __schedule+0x23d/0x5a0 [ 1935.239583]
>> schedule+0x4e/0xc0 [ 1935.248983] schedule_timeout+0x103/0x140 [
>> 1935.261002] __wait_for_common+0xae/0x150 [ 1935.273008] ?
>> usleep_range_state+0x90/0x90 [ 1935.285546]
>> wait_for_completion+0x24/0x30 [ 1935.297813]
>> __flush_work.isra.0+0x175/0x280 [ 1935.310611] ?
>> worker_detach_from_pool+0xc0/0xc0 [ 1935.324436]
>> flush_delayed_work+0x31/0x50 [ 1935.336455]
>> kfd_suspend_all_processes+0x96/0x150 [amdgpu] [ 1935.353429]
>> kgd2kfd_suspend+0xb8/0xe0 [amdgpu] [ 1935.367469]
>> kgd2kfd_pre_reset+0x81/0xf0 [amdgpu] [ 1935.382036]
>> amdgpu_amdkfd_pre_reset+0x1a/0x30 [amdgpu] [ 1935.398156]
>> amdgpu_device_gpu_recover.cold+0x210/0xcf2 [amdgpu] [ 1935.416722]
>> amdgpu_job_timedout+0x19f/0x1e0 [amdgpu] [ 1935.432367]
>> drm_sched_job_timedout+0x6f/0x120 [amd_sched] [ 1935.448792]
>> process_one_work+0x22b/0x3d0 [ 1935.460806]
>worker_thread+0x53/0x420
>> [ 1935.471777] ? process_one_work+0x3d0/0x3d0 [ 1935.484307]
>> kthread+0x12a/0x150 [ 1935.493993] ? set_kthread_struct+0x50/0x50 [
>> 1935.506513] ret_from_fork+0x22/0x30
>
>Looking at the time stamps, this seems to be a mash-up of two different logs. I
>think you're trying to show how a restore_processes worker is stuck on a fence,
>and that's causing kgd2kfd_pre_reset to hang when it tries to flush the work.
>
>The fence it's hanging on is probably something related to a page table update
>that got caught up in the GPU hang. Adding a timeout here seems reasonable.
>There may be another problem, because
>amdgpu_amdkfd_gpuvm_restore_process_bos ignores the return value of
>amdgpu_sync_wait. We shouldi probably handle the timeout gracefully with a
>"goto validate_map_fail".
>
>Regards,
> Felix
>
>
>>
>> It is because the amdgpu_sync_wait is waiting for the bad job's fence,
>> and never return, so the recover couldn't continue.
>>
>>
>> Signed-off-by: Emily Deng
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 16 +---
>> 1 file changed, 13 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
>> index dcd8c066bc1f..c922867c5675 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
>> @@ -406,9 +406,19 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync,
>bool intr)
>> int i, r;
>>
>> hash_for_each_safe(sync->fences, i, tmp, e, node) {
>> -r = dma_fence_wait(e->fence, intr);
>> -if (r)
>> -return r;
>> +struct drm_sched_fence *s_fence = to_drm_sched_fence(e-
>>fence);
>> +
>> +if (s_fence) {
>> +r = dma_fence_wait_timeout(e->fence, intr, s_fence-
>>sched->timeout);
>> +if (r == 0)
>> +r = -ETIMEDOUT;
>> +if (r < 0)
>> +return r;
>> +} else {
>> +r = dma_fence_wait(e->fence, intr);
>> +
[PATCH v2 5/9] drm/ci: clean up xfails (specially flakes list)
Since the script that collected the list of the expectation files was bogus and placing test to the flakes list incorrectly, restart the expectation files with the correct script. This reduces a lot the number of tests in the flakes list. Signed-off-by: Helen Koike Reviewed-by: David Heidelberg --- v2: - fix typo in the commit message - re-add kms_cursor_legacy@flip-vs-cursor-toggle back to msm-sdm845-flakes.txt - removed kms_async_flips@crc,Fail from i915-cml-fails.txt --- .../gpu/drm/ci/xfails/amdgpu-stoney-fails.txt | 13 -- .../drm/ci/xfails/amdgpu-stoney-flakes.txt| 20 - drivers/gpu/drm/ci/xfails/i915-amly-fails.txt | 9 .../gpu/drm/ci/xfails/i915-amly-flakes.txt| 32 --- drivers/gpu/drm/ci/xfails/i915-apl-fails.txt | 11 - drivers/gpu/drm/ci/xfails/i915-apl-flakes.txt | 1 - drivers/gpu/drm/ci/xfails/i915-cml-fails.txt | 14 ++- drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt | 38 - drivers/gpu/drm/ci/xfails/i915-glk-fails.txt | 17 drivers/gpu/drm/ci/xfails/i915-glk-flakes.txt | 41 --- drivers/gpu/drm/ci/xfails/i915-kbl-fails.txt | 7 drivers/gpu/drm/ci/xfails/i915-kbl-flakes.txt | 26 drivers/gpu/drm/ci/xfails/i915-tgl-fails.txt | 1 - drivers/gpu/drm/ci/xfails/i915-tgl-flakes.txt | 5 --- drivers/gpu/drm/ci/xfails/i915-whl-flakes.txt | 1 - .../drm/ci/xfails/mediatek-mt8173-flakes.txt | 0 .../drm/ci/xfails/mediatek-mt8183-fails.txt | 5 ++- .../drm/ci/xfails/mediatek-mt8183-flakes.txt | 14 --- .../gpu/drm/ci/xfails/meson-g12b-fails.txt| 14 --- .../gpu/drm/ci/xfails/meson-g12b-flakes.txt | 4 -- .../gpu/drm/ci/xfails/msm-apq8016-flakes.txt | 4 -- .../gpu/drm/ci/xfails/msm-apq8096-fails.txt | 2 + .../gpu/drm/ci/xfails/msm-apq8096-flakes.txt | 4 -- .../gpu/drm/ci/xfails/msm-sc7180-fails.txt| 15 --- .../gpu/drm/ci/xfails/msm-sc7180-flakes.txt | 24 +++ .../gpu/drm/ci/xfails/msm-sc7180-skips.txt| 18 +--- .../gpu/drm/ci/xfails/msm-sdm845-fails.txt| 9 +--- .../gpu/drm/ci/xfails/msm-sdm845-flakes.txt | 19 + .../drm/ci/xfails/rockchip-rk3288-fails.txt | 6 +++ .../drm/ci/xfails/rockchip-rk3288-flakes.txt | 9 .../drm/ci/xfails/rockchip-rk3399-fails.txt | 40 +- .../drm/ci/xfails/rockchip-rk3399-flakes.txt | 28 +++-- .../drm/ci/xfails/virtio_gpu-none-flakes.txt | 0 33 files changed, 162 insertions(+), 289 deletions(-) delete mode 100644 drivers/gpu/drm/ci/xfails/i915-amly-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/i915-apl-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/i915-glk-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/i915-kbl-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/i915-tgl-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/i915-whl-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/mediatek-mt8173-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/mediatek-mt8183-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/meson-g12b-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/msm-apq8016-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/msm-apq8096-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/rockchip-rk3288-flakes.txt delete mode 100644 drivers/gpu/drm/ci/xfails/virtio_gpu-none-flakes.txt diff --git a/drivers/gpu/drm/ci/xfails/amdgpu-stoney-fails.txt b/drivers/gpu/drm/ci/xfails/amdgpu-stoney-fails.txt index bd9392536e7c..aa57aaa8869b 100644 --- a/drivers/gpu/drm/ci/xfails/amdgpu-stoney-fails.txt +++ b/drivers/gpu/drm/ci/xfails/amdgpu-stoney-fails.txt @@ -1,8 +1,14 @@ kms_addfb_basic@bad-pitch-65536,Fail kms_addfb_basic@bo-too-small,Fail +kms_addfb_basic@too-high,Fail +kms_async_flips@async-flip-with-page-flip-events,Fail +kms_async_flips@crc,Fail kms_async_flips@invalid-async-flip,Fail -kms_atomic@plane-immutable-zpos,Fail +kms_atomic_transition@plane-all-modeset-transition-internal-panels,Fail +kms_atomic_transition@plane-all-transition,Fail +kms_atomic_transition@plane-all-transition-nonblocking,Fail kms_atomic_transition@plane-toggle-modeset-transition,Fail +kms_atomic_transition@plane-use-after-nonblocking-unbind,Fail kms_bw@linear-tiling-1-displays-2560x1440p,Fail kms_bw@linear-tiling-1-displays-3840x2160p,Fail kms_bw@linear-tiling-2-displays-3840x2160p,Fail @@ -11,9 +17,10 @@ kms_color@degamma,Fail kms_cursor_crc@cursor-size-change,Fail kms_cursor_crc@pipe-A-cursor-size-change,Fail kms_cursor_crc@pipe-B-cursor-size-change,Fail -kms_cursor_legacy@forked-move,Fail +kms_flip@flip-vs-modeset-vs-hang,Fail +kms_flip@flip-vs-panning-vs-hang,Fail kms_hdr@bpc-switch,Fail kms_hdr@bpc-switch-dpms,Fail +kms_plane@pixel-format,Fail kms_plane_multiple@atomic-pipe-A-tiling-none,Fail -kms_rmfb@close-fd,Fail kms_rotation_crc@primary-rotation-180,Fail diff --git
[pull] amdgpu drm-fixes-6.6
Hi Dave, Sima, Fixes for 6.6. The following changes since commit 58720809f52779dc0f08e53e54b014209d13eebb: Linux 6.6-rc6 (2023-10-15 13:34:39 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-6.6-2023-10-19 for you to fetch changes up to 316baf09d355aec1179981b6dfe28eba50c5ee5b: drm/amdgpu: Reserve fences for VM update (2023-10-19 18:56:57 -0400) amd-drm-fixes-6.6-2023-10-19: amdgpu: - Fix possible NULL pointer dereference - Avoid possible BUG_ON in GPUVM updates Felix Kuehling (2): drm/amdgpu: Fix possible null pointer dereference drm/amdgpu: Reserve fences for VM update drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 5 - drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++- 2 files changed, 6 insertions(+), 2 deletions(-)
[linux-next:master] BUILD REGRESSION 4230ea146b1e64628f11e44290bb4008e391bc24
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 4230ea146b1e64628f11e44290bb4008e391bc24 Add linux-next specific
files for 20231019
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202309200103.grxwdktx-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202310171905.azfrkoid-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202310181800.bh66q0t1-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202310181854.pkthd7fd-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202310182303.v3ttgnqz-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202310190116.5jjceozj-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202310190741.mbptqrpd-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202310190833.oil4wrlx-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202310191301.qrq2ba0o-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202310200550.p46be4w7-...@intel.com
Error/Warning: (recently discovered and may have been fixed)
arch/m68k/include/asm/raw_io.h:20:18: warning: array subscript 0 is outside
array bounds of 'const volatile u8[0]' {aka 'const volatile unsigned char[]'}
[-Warray-bounds=]
arch/s390/include/asm/ctlreg.h:129:9: warning: array subscript 0 is outside
array bounds of 'struct ctlreg[0]' [-Warray-bounds=]
arch/sparc/include/asm/string.h:15:25: warning: '__builtin_memcpy' offset [0,
2] is out of the bounds [0, 0] [-Warray-bounds=]
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.c:286:52: warning:
'%s' directive output may be truncated writing up to 29 bytes into a region of
size 23 [-Wformat-truncation=]
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu14/smu_v14_0.c:72:52: warning: '%s'
directive output may be truncated writing up to 29 bytes into a region of size
23 [-Wformat-truncation=]
drivers/net/wireless/mediatek/mt76/mt7996/mcu.c:483:61: warning: array
subscript is outside array bounds of 'struct [0]'
[-Warray-bounds=]
fs/bcachefs/btree_trans_commit.c:702:35: warning: array subscript 0 is outside
the bounds of an interior zero-length array 'struct bkey_i[0]'
[-Wzero-length-bounds]
fs/bcachefs/btree_update_interior.c:2414:28: warning: array subscript 0 is
outside the bounds of an interior zero-length array 'struct bkey_i[0]'
[-Wzero-length-bounds]
fs/bcachefs/btree_update_interior.h:274:50: warning: array subscript 0 is
outside the bounds of an interior zero-length array 'struct bkey_packed[0]'
[-Wzero-length-bounds]
fs/bcachefs/extents.h:55:26: warning: array subscript 'const union
bch_extent_entry[0]' is partly outside array bounds of 'struct
bch_extent_stripe_ptr[1]' [-Warray-bounds=]
fs/bcachefs/journal_seq_blacklist.c:110:18: warning: array subscript 'i' is
outside the bounds of an interior zero-length array 'struct
journal_seq_blacklist_entry[0]' [-Wzero-length-bounds]
fs/bcachefs/journal_seq_blacklist.c:148:26: warning: array subscript
is outside array bounds of 'struct journal_seq_blacklist_table_entry[0]'
[-Warray-bounds=]
fs/bcachefs/journal_seq_blacklist.c:176:27: warning: array subscript i is
outside array bounds of 'struct journal_seq_blacklist_table_entry[0]'
[-Warray-bounds=]
fs/bcachefs/journal_seq_blacklist.c:176:64: warning: array subscript '(unsigned
int) _33 + 4294967295' is outside the bounds of an interior zero-length array
'struct journal_seq_blacklist_entry[0]' [-Wzero-length-bounds]
fs/bcachefs/journal_seq_blacklist.c:53:34: warning: array subscript 268435454
is outside the bounds of an interior zero-length array 'struct
journal_seq_blacklist_entry[0]' [-Wzero-length-bounds]
fs/bcachefs/journal_seq_blacklist.c:53:34: warning: array subscript 4294967294
is outside the bounds of an interior zero-length array 'struct
journal_seq_blacklist_entry[0]' [-Wzero-length-bounds]
fs/bcachefs/journal_seq_blacklist.h:9:56: warning: array subscript 0 is outside
the bounds of an interior zero-length array 'struct
journal_seq_blacklist_entry[0]' [-Wzero-length-bounds]
fs/bcachefs/recovery.c:214:44: warning: array subscript 0 is outside the bounds
of an interior zero-length array 'struct bkey_i[0]' [-Wzero-length-bounds]
fs/bcachefs/snapshot.c:134:70: warning: array subscript is outside
array bounds of 'struct snapshot_t[0]' [-Warray-bounds=]
fs/bcachefs/snapshot.c:168:16: warning: array subscript idx is outside array
bounds of 'struct snapshot_t[0]' [-Warray-bounds=]
fs/bcachefs/snapshot.h:36:16: warning: array subscript is outside
array bounds of 'struct snapshot_t[0]' [-Warray-bounds=]
fs/bcachefs/snapshot.h:36:21: warning: array subscript is outside
array bounds of 'struct snapshot_t[0]' [-Warray-bounds=]
fs/tracefs/event_inode.c:734:10: error: casting from randomized structure
pointer type 'struct dentry *' to 'struct eventfs_inode *'
include/asm-generic/rwonce.h:44:26: warning: array subscript 0 is outside array
bounds of '__u8[0]' {aka 'unsigned char[]'} [-Warray-bounds=]
include/asm-generic/rwonce.h:44:26: warning: array subscript 0 is outside
Re: [linux-next:master] BUILD REGRESSION 2dac75696c6da3c848daa118a729827541c89d33
On Thu, Oct 19, 2023 at 05:32:05PM +0200, Heiko Carstens wrote: > On Thu, Oct 19, 2023 at 04:07:35AM +0800, kernel test robot wrote: > > arch/s390/include/asm/ctlreg.h:129:9: warning: array subscript 0 is outside > > array bounds of 'struct ctlreg[0]' [-Warray-bounds=] > > arch/s390/include/asm/ctlreg.h:80:9: warning: array subscript 0 is outside > > array bounds of 'struct ctlreg[0]' [-Warray-bounds=] > ... > > |-- s390-defconfig > > | `-- > > arch-s390-include-asm-ctlreg.h:warning:array-subscript-is-outside-array-bounds-of-struct-ctlreg > ... > > s390defconfig gcc > > I'm wondering how this warning can appear in the builds. array-bounds > warnings are explicitly disabled, see init/Kconfig: CC_NO_ARRAY_BOUNDS. And > as expected, if I compile the kernel with gcc, defconfig, and with or > without W=1 the option -Wno-array-bounds is passed to the compiler. > > And also as expected I do not see the above warnings. > > So something is quite odd here. Sorry about this Heiko, this is a bug in the bot that it wrongly ignores the CC_NO_ARRAY_BOUNDS config and always test with -Warray-bounds. We will fix this asap. >
Re: [PATCH] drm/amdkfd: remap unaligned svm ranges that have split
On 2023-10-19 16:51, Alex Sierra wrote:
Split SVM ranges that have been mapped into 2MB page table entries,
require to be remap in case the split has happened in a non-aligned
VA.
[WHY]:
This condition causes the 2MB page table entries be split into 4KB
PTEs.
Signed-off-by: Alex Sierra
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 43 +---
1 file changed, 32 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 7b81233bc9ae..aa2996d6f818 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1104,26 +1104,32 @@ svm_range_split(struct svm_range *prange, uint64_t
start, uint64_t last,
}
static int
-svm_range_split_tail(struct svm_range *prange,
-uint64_t new_last, struct list_head *insert_list)
+svm_range_split_tail(struct svm_range *prange, uint64_t new_last,
+struct list_head *insert_list, struct list_head
*remap_list)
{
struct svm_range *tail;
int r = svm_range_split(prange, prange->start, new_last, );
- if (!r)
+ if (!r) {
list_add(>list, insert_list);
+ if (!IS_ALIGNED(new_last + 1, 1UL << prange->granularity))
+ list_add(>update_list, remap_list);
+ }
return r;
}
static int
-svm_range_split_head(struct svm_range *prange,
-uint64_t new_start, struct list_head *insert_list)
+svm_range_split_head(struct svm_range *prange, uint64_t new_start,
+struct list_head *insert_list, struct list_head
*remap_list)
{
struct svm_range *head;
int r = svm_range_split(prange, new_start, prange->last, );
- if (!r)
+ if (!r) {
list_add(>list, insert_list);
+ if (!IS_ALIGNED(new_start, 1UL << prange->granularity))
+ list_add(>update_list, remap_list);
+ }
return r;
}
@@ -2113,7 +2119,7 @@ static int
svm_range_add(struct kfd_process *p, uint64_t start, uint64_t size,
uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs,
struct list_head *update_list, struct list_head *insert_list,
- struct list_head *remove_list)
+ struct list_head *remove_list, struct list_head *remap_list)
{
unsigned long last = start + size - 1UL;
struct svm_range_list *svms = >svms;
@@ -2129,6 +2135,7 @@ svm_range_add(struct kfd_process *p, uint64_t start,
uint64_t size,
INIT_LIST_HEAD(insert_list);
INIT_LIST_HEAD(remove_list);
INIT_LIST_HEAD(_list);
+ INIT_LIST_HEAD(remap_list);
node = interval_tree_iter_first(>objects, start, last);
while (node) {
@@ -2153,6 +2160,7 @@ svm_range_add(struct kfd_process *p, uint64_t start,
uint64_t size,
struct svm_range *old = prange;
prange = svm_range_clone(old);
+
if (!prange) {
r = -ENOMEM;
goto out;
@@ -2161,18 +2169,17 @@ svm_range_add(struct kfd_process *p, uint64_t start,
uint64_t size,
list_add(>update_list, remove_list);
list_add(>list, insert_list);
list_add(>update_list, update_list);
-
if (node->start < start) {
pr_debug("change old range start\n");
r = svm_range_split_head(prange, start,
-insert_list);
+insert_list,
remap_list);
if (r)
goto out;
}
if (node->last > last) {
pr_debug("change old range last\n");
r = svm_range_split_tail(prange, last,
-insert_list);
+insert_list,
remap_list);
if (r)
goto out;
}
@@ -3565,6 +3572,7 @@ svm_range_set_attr(struct kfd_process *p, struct
mm_struct *mm,
struct list_head update_list;
struct list_head insert_list;
struct list_head remove_list;
+ struct list_head remap_list;
struct svm_range_list *svms;
struct svm_range *prange;
struct svm_range *next;
@@ -3596,7 +3604,7 @@ svm_range_set_attr(struct kfd_process *p, struct
mm_struct *mm,
/* Add new range and split existing ranges as needed */
r = svm_range_add(p, start, size, nattr, attrs, _list,
- _list, _list);
+ _list, _list, _list);
if (r) {
Re: [PATCH] drm/amdkfd: remap unaligned svm ranges that have split
On 2023-10-19 16:53, Philip Yang wrote:
On 2023-10-19 16:05, Felix Kuehling wrote:
On 2023-10-18 18:26, Alex Sierra wrote:
Split SVM ranges that have been mapped into 2MB page table entries,
require to be remap in case the split has happened in a non-aligned
VA.
[WHY]:
This condition causes the 2MB page table entries be split into 4KB
PTEs.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 45
+---
1 file changed, 34 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 7b81233bc9ae..1dd9a1cf2358 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1104,26 +1104,34 @@ svm_range_split(struct svm_range *prange,
uint64_t start, uint64_t last,
}
static int
-svm_range_split_tail(struct svm_range *prange,
- uint64_t new_last, struct list_head *insert_list)
+svm_range_split_tail(struct svm_range *prange, uint64_t new_last,
+ struct list_head *insert_list, struct list_head
*remap_list)
{
struct svm_range *tail;
int r = svm_range_split(prange, prange->start, new_last, );
- if (!r)
+ if (!r) {
list_add(>list, insert_list);
+ if (!IS_ALIGNED(tail->last + 1 - tail->start,
+ 1UL << tail->granularity))
I'm not sure about this condition. I thought this condition should be
about the point where the range is split, not the size of it. So my
understanding is that this should be
if (!IS_ALIGNED(new_last+1, 1UL << prange->granularity))
I think prange->granularity is not always 9, 512 pages, we should
check the original prange size is larger than 512.
if (!IS_ALIGNED(new_last + 1, 512) && tail->last -
prange->start >= 512)
That's if you only want to protect against splitting of 2MB pages. If
you also want to protect against splitting of fragments (together with
your WIP patch series for the mapping bitmap), then we should use
granularity.
Regards,
Felix
+ list_add(>update_list, remap_list);
+ }
return r;
}
static int
-svm_range_split_head(struct svm_range *prange,
- uint64_t new_start, struct list_head *insert_list)
+svm_range_split_head(struct svm_range *prange, uint64_t new_start,
+ struct list_head *insert_list, struct list_head
*remap_list)
{
struct svm_range *head;
int r = svm_range_split(prange, new_start, prange->last, );
- if (!r)
+ if (!r) {
list_add(>list, insert_list);
+ if (!IS_ALIGNED(head->last + 1 - head->start,
+ 1UL << head->granularity))
Similar as above.
if (!IS_ALIGNED(new_start, 1UL << prange->granularity))
if (!IS_ALIGNED(new_start, 512) && prange->last -
head->start >= 512)
Regards,
Felix
+ list_add(>update_list, remap_list);
+ }
return r;
}
@@ -2113,7 +2121,7 @@ static int
svm_range_add(struct kfd_process *p, uint64_t start, uint64_t size,
uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs,
struct list_head *update_list, struct list_head
*insert_list,
- struct list_head *remove_list)
+ struct list_head *remove_list, struct list_head *remap_list)
{
unsigned long last = start + size - 1UL;
struct svm_range_list *svms = >svms;
@@ -2129,6 +2137,7 @@ svm_range_add(struct kfd_process *p, uint64_t
start, uint64_t size,
INIT_LIST_HEAD(insert_list);
INIT_LIST_HEAD(remove_list);
INIT_LIST_HEAD(_list);
+ INIT_LIST_HEAD(remap_list);
node = interval_tree_iter_first(>objects, start, last);
while (node) {
@@ -2153,6 +2162,7 @@ svm_range_add(struct kfd_process *p, uint64_t
start, uint64_t size,
struct svm_range *old = prange;
prange = svm_range_clone(old);
+
unnecessary change.
Regards,
Philip
if (!prange) {
r = -ENOMEM;
goto out;
@@ -2161,18 +2171,17 @@ svm_range_add(struct kfd_process *p,
uint64_t start, uint64_t size,
list_add(>update_list, remove_list);
list_add(>list, insert_list);
list_add(>update_list, update_list);
-
if (node->start < start) {
pr_debug("change old range start\n");
r = svm_range_split_head(prange, start,
- insert_list);
+ insert_list, remap_list);
if (r)
goto out;
}
if (node->last > last) {
pr_debug("change old range last\n");
r = svm_range_split_tail(prange, last,
- insert_list);
+ insert_list, remap_list);
if (r)
goto out;
}
@@ -3565,6 +3574,7 @@ svm_range_set_attr(struct kfd_process *p,
struct mm_struct
Re: [PATCH] drm/amdkfd: remap unaligned svm ranges that have split
On 2023-10-19 16:05, Felix Kuehling
wrote:
On 2023-10-18 18:26, Alex Sierra wrote:
Split SVM ranges that have been mapped
into 2MB page table entries,
require to be remap in case the split has happened in a
non-aligned
VA.
[WHY]:
This condition causes the 2MB page table entries be split into
4KB
PTEs.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 45
+---
1 file changed, 34 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 7b81233bc9ae..1dd9a1cf2358 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1104,26 +1104,34 @@ svm_range_split(struct svm_range
*prange, uint64_t start, uint64_t last,
}
static int
-svm_range_split_tail(struct svm_range *prange,
- uint64_t new_last, struct list_head *insert_list)
+svm_range_split_tail(struct svm_range *prange, uint64_t
new_last,
+ struct list_head *insert_list, struct list_head
*remap_list)
{
struct svm_range *tail;
int r = svm_range_split(prange, prange->start,
new_last, );
- if (!r)
+ if (!r) {
list_add(>list, insert_list);
+ if (!IS_ALIGNED(tail->last + 1 - tail->start,
+ 1UL << tail->granularity))
I'm not sure about this condition. I thought this condition should
be about the point where the range is split, not the size of it.
So my understanding is that this should be
if (!IS_ALIGNED(new_last+1, 1UL <<
prange->granularity))
I think prange->granularity is not always 9, 512 pages, we
should check the original prange size is larger than 512.
if (!IS_ALIGNED(new_last + 1, 512) &&
tail->last - prange->start >= 512)
+
list_add(>update_list, remap_list);
+ }
return r;
}
static int
-svm_range_split_head(struct svm_range *prange,
- uint64_t new_start, struct list_head *insert_list)
+svm_range_split_head(struct svm_range *prange, uint64_t
new_start,
+ struct list_head *insert_list, struct list_head
*remap_list)
{
struct svm_range *head;
int r = svm_range_split(prange, new_start,
prange->last, );
- if (!r)
+ if (!r) {
list_add(>list, insert_list);
+ if (!IS_ALIGNED(head->last + 1 - head->start,
+ 1UL << head->granularity))
Similar as above.
if (!IS_ALIGNED(new_start, 1UL <<
prange->granularity))
if (!IS_ALIGNED(new_start, 512) &&
prange->last - head->start >= 512)
Regards,
Felix
+
list_add(>update_list, remap_list);
+ }
return r;
}
@@ -2113,7 +2121,7 @@ static int
svm_range_add(struct kfd_process *p, uint64_t start, uint64_t
size,
uint32_t nattr, struct kfd_ioctl_svm_attribute
*attrs,
struct list_head *update_list, struct list_head
*insert_list,
- struct list_head *remove_list)
+ struct list_head *remove_list, struct list_head
*remap_list)
{
unsigned long last = start + size - 1UL;
struct svm_range_list *svms = >svms;
@@ -2129,6 +2137,7 @@ svm_range_add(struct kfd_process *p,
uint64_t start, uint64_t size,
INIT_LIST_HEAD(insert_list);
INIT_LIST_HEAD(remove_list);
INIT_LIST_HEAD(_list);
+ INIT_LIST_HEAD(remap_list);
node = interval_tree_iter_first(>objects,
start, last);
while (node) {
@@ -2153,6
[PATCH] drm/amdkfd: remap unaligned svm ranges that have split
Split SVM ranges that have been mapped into 2MB page table entries,
require to be remap in case the split has happened in a non-aligned
VA.
[WHY]:
This condition causes the 2MB page table entries be split into 4KB
PTEs.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 43 +---
1 file changed, 32 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 7b81233bc9ae..aa2996d6f818 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1104,26 +1104,32 @@ svm_range_split(struct svm_range *prange, uint64_t
start, uint64_t last,
}
static int
-svm_range_split_tail(struct svm_range *prange,
-uint64_t new_last, struct list_head *insert_list)
+svm_range_split_tail(struct svm_range *prange, uint64_t new_last,
+struct list_head *insert_list, struct list_head
*remap_list)
{
struct svm_range *tail;
int r = svm_range_split(prange, prange->start, new_last, );
- if (!r)
+ if (!r) {
list_add(>list, insert_list);
+ if (!IS_ALIGNED(new_last + 1, 1UL << prange->granularity))
+ list_add(>update_list, remap_list);
+ }
return r;
}
static int
-svm_range_split_head(struct svm_range *prange,
-uint64_t new_start, struct list_head *insert_list)
+svm_range_split_head(struct svm_range *prange, uint64_t new_start,
+struct list_head *insert_list, struct list_head
*remap_list)
{
struct svm_range *head;
int r = svm_range_split(prange, new_start, prange->last, );
- if (!r)
+ if (!r) {
list_add(>list, insert_list);
+ if (!IS_ALIGNED(new_start, 1UL << prange->granularity))
+ list_add(>update_list, remap_list);
+ }
return r;
}
@@ -2113,7 +2119,7 @@ static int
svm_range_add(struct kfd_process *p, uint64_t start, uint64_t size,
uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs,
struct list_head *update_list, struct list_head *insert_list,
- struct list_head *remove_list)
+ struct list_head *remove_list, struct list_head *remap_list)
{
unsigned long last = start + size - 1UL;
struct svm_range_list *svms = >svms;
@@ -2129,6 +2135,7 @@ svm_range_add(struct kfd_process *p, uint64_t start,
uint64_t size,
INIT_LIST_HEAD(insert_list);
INIT_LIST_HEAD(remove_list);
INIT_LIST_HEAD(_list);
+ INIT_LIST_HEAD(remap_list);
node = interval_tree_iter_first(>objects, start, last);
while (node) {
@@ -2153,6 +2160,7 @@ svm_range_add(struct kfd_process *p, uint64_t start,
uint64_t size,
struct svm_range *old = prange;
prange = svm_range_clone(old);
+
if (!prange) {
r = -ENOMEM;
goto out;
@@ -2161,18 +2169,17 @@ svm_range_add(struct kfd_process *p, uint64_t start,
uint64_t size,
list_add(>update_list, remove_list);
list_add(>list, insert_list);
list_add(>update_list, update_list);
-
if (node->start < start) {
pr_debug("change old range start\n");
r = svm_range_split_head(prange, start,
-insert_list);
+insert_list,
remap_list);
if (r)
goto out;
}
if (node->last > last) {
pr_debug("change old range last\n");
r = svm_range_split_tail(prange, last,
-insert_list);
+insert_list,
remap_list);
if (r)
goto out;
}
@@ -3565,6 +3572,7 @@ svm_range_set_attr(struct kfd_process *p, struct
mm_struct *mm,
struct list_head update_list;
struct list_head insert_list;
struct list_head remove_list;
+ struct list_head remap_list;
struct svm_range_list *svms;
struct svm_range *prange;
struct svm_range *next;
@@ -3596,7 +3604,7 @@ svm_range_set_attr(struct kfd_process *p, struct
mm_struct *mm,
/* Add new range and split existing ranges as needed */
r = svm_range_add(p, start, size, nattr, attrs, _list,
- _list, _list);
+ _list, _list, _list);
if (r) {
mutex_unlock(>lock);
Re: [PATCH] drm/amdkfd: Use partial mapping in GPU page fault recovery
On 10/19/2023 2:40 PM, Philip Yang wrote:
On 2023-10-19 12:20, Chen, Xiaogang wrote:
On 10/19/2023 11:08 AM, Philip Yang wrote:
On 2023-10-19 10:24, Xiaogang.Chen wrote:
From: Xiaogang Chen
After partial migration to recover GPU page fault this patch does
GPU vm
space mapping for same page range that got migrated instead of
mapping all
pages of svm range in which the page fault happened.
Signed-off-by: Xiaogang Chen
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 33
+---
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 54af7a2b29f8..81dbcc8a4ccc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1619,6 +1619,7 @@ static void *kfd_svm_page_owner(struct
kfd_process *p, int32_t gpuidx)
* 5. Release page table (and SVM BO) reservation
*/
static int svm_range_validate_and_map(struct mm_struct *mm,
+ unsigned long map_start, unsigned long
map_last,
struct svm_range *prange, int32_t gpuidx,
bool intr, bool wait, bool flush_tlb)
{
@@ -1630,6 +1631,12 @@ static int svm_range_validate_and_map(struct
mm_struct *mm,
int32_t idx;
int r = 0;
+ if (map_start < prange->start || map_last > prange->last) {
This is not needed, as this case should never happen, and you also
use max/min to limit map_start, map_last below.
This was just a sanity check, I can remove it.
+ pr_debug("range [0x%lx 0x%lx] out prange [0x%lx 0x%lx]\n",
+ map_start, map_last, prange->start, prange->last);
+ return -EFAULT;
+ }
+
ctx = kzalloc(sizeof(struct svm_validate_context), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
@@ -1747,9 +1754,16 @@ static int svm_range_validate_and_map(struct
mm_struct *mm,
r = -EAGAIN;
}
- if (!r)
- r = svm_range_map_to_gpus(prange, offset, npages,
readonly,
- ctx->bitmap, wait, flush_tlb);
+ if (!r) {
+ map_start = max(map_start, prange->start + offset);
+ map_last = min(map_last, prange->start + offset +
npages);
This should move forward to outside the for loop, otherwise
amdgpu_hmm_range_get_pages and svm_range_dma_map still work on the
entire prange, and then prange->vram_pages update logic should be
changed accordingly.
We need use hmm function to get all vram page number on whole range
as we did not know how many vram pages after partial migration, then
we know if can release vram bo.
ok,migrate to vram and migrate to ram have the vram pages updated
already, the is needed for the splite prange. We could update
prange->vram_pages when splitting prange, this can be done in another
patch.
map_last is inclusive,
+ map_last = min(map_last, prange->start + offset + npages
- 1);
ok, will update it.
Regards
Xiaogang
Regards,
Philip
Regards
Xiaogang
Regards,
Philip
+ if (map_start <= map_last) {
+ offset = map_start - prange->start;
+ npages = map_last - map_start + 1;
+ r = svm_range_map_to_gpus(prange, offset, npages,
readonly,
+ ctx->bitmap, wait, flush_tlb);
+ }
+ }
if (!r && next == end)
prange->mapped_to_gpu = true;
@@ -1855,8 +1869,8 @@ static void svm_range_restore_work(struct
work_struct *work)
*/
mutex_lock(>migrate_mutex);
- r = svm_range_validate_and_map(mm, prange,
MAX_GPU_INSTANCE,
- false, true, false);
+ r = svm_range_validate_and_map(mm, prange->start,
prange->last, prange,
+ MAX_GPU_INSTANCE, false, true, false);
if (r)
pr_debug("failed %d to map 0x%lx to gpus\n", r,
prange->start);
@@ -3069,6 +3083,8 @@ svm_range_restore_pages(struct amdgpu_device
*adev, unsigned int pasid,
kfd_smi_event_page_fault_start(node, p->lead_thread->pid, addr,
write_fault, timestamp);
+ start = prange->start;
+ last = prange->last;
if (prange->actual_loc != 0 || best_loc != 0) {
migration = true;
/* Align migration range start and size to granularity
size */
@@ -3102,10 +3118,11 @@ svm_range_restore_pages(struct
amdgpu_device *adev, unsigned int pasid,
}
}
- r = svm_range_validate_and_map(mm, prange, gpuidx, false,
false, false);
+ r = svm_range_validate_and_map(mm, start, last, prange,
gpuidx, false,
+ false, false);
if (r)
pr_debug("failed %d to map svms 0x%p [0x%lx 0x%lx] to
gpus\n",
- r, svms, prange->start, prange->last);
+ r, svms, start, last);
kfd_smi_event_page_fault_end(node, p->lead_thread->pid, addr,
Re: [PATCH] drm/amdkfd: remap unaligned svm ranges that have split
On 2023-10-18 18:26, Alex Sierra wrote:
Split SVM ranges that have been mapped into 2MB page table entries,
require to be remap in case the split has happened in a non-aligned
VA.
[WHY]:
This condition causes the 2MB page table entries be split into 4KB
PTEs.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 45 +---
1 file changed, 34 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 7b81233bc9ae..1dd9a1cf2358 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1104,26 +1104,34 @@ svm_range_split(struct svm_range *prange, uint64_t
start, uint64_t last,
}
static int
-svm_range_split_tail(struct svm_range *prange,
-uint64_t new_last, struct list_head *insert_list)
+svm_range_split_tail(struct svm_range *prange, uint64_t new_last,
+struct list_head *insert_list, struct list_head
*remap_list)
{
struct svm_range *tail;
int r = svm_range_split(prange, prange->start, new_last, );
- if (!r)
+ if (!r) {
list_add(>list, insert_list);
+ if (!IS_ALIGNED(tail->last + 1 - tail->start,
+ 1UL << tail->granularity))
I'm not sure about this condition. I thought this condition should be
about the point where the range is split, not the size of it. So my
understanding is that this should be
if (!IS_ALIGNED(new_last+1, 1UL << prange->granularity))
+ list_add(>update_list, remap_list);
+ }
return r;
}
static int
-svm_range_split_head(struct svm_range *prange,
-uint64_t new_start, struct list_head *insert_list)
+svm_range_split_head(struct svm_range *prange, uint64_t new_start,
+struct list_head *insert_list, struct list_head
*remap_list)
{
struct svm_range *head;
int r = svm_range_split(prange, new_start, prange->last, );
- if (!r)
+ if (!r) {
list_add(>list, insert_list);
+ if (!IS_ALIGNED(head->last + 1 - head->start,
+ 1UL << head->granularity))
Similar as above.
if (!IS_ALIGNED(new_start, 1UL << prange->granularity))
Regards,
Felix
+ list_add(>update_list, remap_list);
+ }
return r;
}
@@ -2113,7 +2121,7 @@ static int
svm_range_add(struct kfd_process *p, uint64_t start, uint64_t size,
uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs,
struct list_head *update_list, struct list_head *insert_list,
- struct list_head *remove_list)
+ struct list_head *remove_list, struct list_head *remap_list)
{
unsigned long last = start + size - 1UL;
struct svm_range_list *svms = >svms;
@@ -2129,6 +2137,7 @@ svm_range_add(struct kfd_process *p, uint64_t start,
uint64_t size,
INIT_LIST_HEAD(insert_list);
INIT_LIST_HEAD(remove_list);
INIT_LIST_HEAD(_list);
+ INIT_LIST_HEAD(remap_list);
node = interval_tree_iter_first(>objects, start, last);
while (node) {
@@ -2153,6 +2162,7 @@ svm_range_add(struct kfd_process *p, uint64_t start,
uint64_t size,
struct svm_range *old = prange;
prange = svm_range_clone(old);
+
if (!prange) {
r = -ENOMEM;
goto out;
@@ -2161,18 +2171,17 @@ svm_range_add(struct kfd_process *p, uint64_t start,
uint64_t size,
list_add(>update_list, remove_list);
list_add(>list, insert_list);
list_add(>update_list, update_list);
-
if (node->start < start) {
pr_debug("change old range start\n");
r = svm_range_split_head(prange, start,
-insert_list);
+insert_list,
remap_list);
if (r)
goto out;
}
if (node->last > last) {
pr_debug("change old range last\n");
r = svm_range_split_tail(prange, last,
-insert_list);
+insert_list,
remap_list);
if (r)
goto out;
}
@@ -3565,6 +3574,7 @@ svm_range_set_attr(struct kfd_process *p, struct
mm_struct *mm,
struct list_head update_list;
struct list_head insert_list;
struct list_head remove_list;
+ struct list_head
Re: [PATCH] drm/amdkfd: Use partial mapping in GPU page fault recovery
On 2023-10-19 12:20, Chen, Xiaogang
wrote:
On 10/19/2023 11:08 AM, Philip Yang wrote:
On 2023-10-19 10:24, Xiaogang.Chen wrote:
From: Xiaogang
Chen
After partial migration to recover GPU page fault this patch
does GPU vm
space mapping for same page range that got migrated instead of
mapping all
pages of svm range in which the page fault happened.
Signed-off-by: Xiaogang Chen
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 33
+---
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 54af7a2b29f8..81dbcc8a4ccc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1619,6 +1619,7 @@ static void *kfd_svm_page_owner(struct
kfd_process *p, int32_t gpuidx)
* 5. Release page table (and SVM BO) reservation
*/
static int svm_range_validate_and_map(struct mm_struct *mm,
+ unsigned long map_start, unsigned long
map_last,
struct svm_range *prange, int32_t
gpuidx,
bool intr, bool wait, bool flush_tlb)
{
@@ -1630,6 +1631,12 @@ static int
svm_range_validate_and_map(struct mm_struct *mm,
int32_t idx;
int r = 0;
+ if (map_start < prange->start || map_last >
prange->last) {
This is not needed, as this case should never happen, and you
also use max/min to limit map_start, map_last below.
This was just a sanity check, I can remove it.
+ pr_debug("range [0x%lx 0x%lx]
out prange [0x%lx 0x%lx]\n",
+ map_start, map_last, prange->start,
prange->last);
+ return -EFAULT;
+ }
+
ctx = kzalloc(sizeof(struct svm_validate_context),
GFP_KERNEL);
if (!ctx)
return -ENOMEM;
@@ -1747,9 +1754,16 @@ static int
svm_range_validate_and_map(struct mm_struct *mm,
r = -EAGAIN;
}
- if (!r)
- r = svm_range_map_to_gpus(prange, offset, npages,
readonly,
- ctx->bitmap, wait, flush_tlb);
+ if (!r) {
+ map_start = max(map_start, prange->start +
offset);
+ map_last = min(map_last, prange->start +
offset + npages);
This should move forward to outside the for loop, otherwise
amdgpu_hmm_range_get_pages and svm_range_dma_map still work on
the entire prange, and then prange->vram_pages update logic
should be changed accordingly.
We need use hmm function to get all vram page number on whole
range as we did not know how many vram pages after partial
migration, then we know if can release vram bo.
ok,migrate to vram and migrate to ram have the vram pages updated
already, the is needed for the splite prange. We could update
prange->vram_pages when splitting prange, this can be done in
another patch.
map_last is inclusive,
+ map_last = min(map_last, prange->start + offset +
npages - 1);
Regards,
Philip
Regards
Xiaogang
Regards,
Philip
+ if (map_start <=
map_last) {
+ offset = map_start - prange->start;
+ npages = map_last - map_start + 1;
+ r = svm_range_map_to_gpus(prange, offset,
npages, readonly,
+ ctx->bitmap, wait,
flush_tlb);
+ }
+ }
if (!r && next == end)
Re: [PATCH] drm/amdkfd: Fix shift out-of-bounds issue and remove unused code.
On 2023-10-18 21:56, Jesse Zhang wrote:
[ 567.613292] shift exponent 255 is too large for 64-bit type 'long unsigned int'
[ 567.614498] CPU: 5 PID: 238 Comm: kworker/5:1 Tainted: G OE 6.2.0-34-generic #34~22.04.1-Ubuntu
[ 567.614502] Hardware name: AMD Splinter/Splinter-RPL, BIOS WS43927N_871 09/25/2023
[ 567.614504] Workqueue: events send_exception_work_handler [amdgpu]
[ 567.614748] Call Trace:
[ 567.614750]
[ 567.614753] dump_stack_lvl+0x48/0x70
[ 567.614761] dump_stack+0x10/0x20
[ 567.614763] __ubsan_handle_shift_out_of_bounds+0x156/0x310
[ 567.614769] ? srso_alias_return_thunk+0x5/0x7f
[ 567.614773] ? update_sd_lb_stats.constprop.0+0xf2/0x3c0
[ 567.614780] svm_range_split_by_granularity.cold+0x2b/0x34 [amdgpu]
[ 567.615047] ? srso_alias_return_thunk+0x5/0x7f
[ 567.615052] svm_migrate_to_ram+0x185/0x4d0 [amdgpu]
[ 567.615286] do_swap_page+0x7b6/0xa30
[ 567.615291] ? srso_alias_return_thunk+0x5/0x7f
[ 567.615294] ? __free_pages+0x119/0x130
[ 567.615299] handle_pte_fault+0x227/0x280
[ 567.615303] __handle_mm_fault+0x3c0/0x720
[ 567.615311] handle_mm_fault+0x119/0x330
[ 567.615314] ? lock_mm_and_find_vma+0x44/0x250
[ 567.615318] do_user_addr_fault+0x1a9/0x640
[ 567.615323] exc_page_fault+0x81/0x1b0
[ 567.615328] asm_exc_page_fault+0x27/0x30
[ 567.615332] RIP: 0010:__get_user_8+0x1c/0x30
Suggested-by: Philip Yang
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 62 +---
drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 3 --
2 files changed, 1 insertion(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 54af7a2b29f8..ccaf86a4c02a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -781,7 +781,7 @@ svm_range_apply_attrs(struct kfd_process *p, struct svm_range *prange,
prange->flags &= ~attrs[i].value;
break;
case KFD_IOCTL_SVM_ATTR_GRANULARITY:
- prange->granularity = attrs[i].value;
+ prange->granularity = attrs[i].value & 0x3F;
Thinks again, this should be prange->granularity =
min_t(uint32_t, attrs[i].value, 0x3F);
Please separate to another patch to remove
svm_range_split_by_granularity.
Regards,
Philip
break;
default:
WARN_ONCE(1, "svm_range_check_attrs wasn't called?");
@@ -1139,66 +1139,6 @@ svm_range_add_child(struct svm_range *prange, struct mm_struct *mm,
list_add_tail(>child_list, >child_list);
}
-/**
- * svm_range_split_by_granularity - collect ranges within granularity boundary
- *
- * @p: the process with svms list
- * @mm: mm structure
- * @addr: the vm fault address in pages, to split the prange
- * @parent: parent range if prange is from child list
- * @prange: prange to split
- *
- * Trims @prange to be a single aligned block of prange->granularity if
- * possible. The head and tail are added to the child_list in @parent.
- *
- * Context: caller must hold mmap_read_lock and prange->lock
- *
- * Return:
- * 0 - OK, otherwise error code
- */
-int
-svm_range_split_by_granularity(struct kfd_process *p, struct mm_struct *mm,
- unsigned long addr, struct svm_range *parent,
- struct svm_range *prange)
-{
- struct svm_range *head, *tail;
- unsigned long start, last, size;
- int r;
-
- /* Align splited range start and size to granularity size, then a single
- * PTE will be used for whole range, this reduces the number of PTE
- * updated and the L1 TLB space used for translation.
- */
- size = 1UL << prange->granularity;
- start = ALIGN_DOWN(addr, size);
- last = ALIGN(addr + 1, size) - 1;
-
- pr_debug("svms 0x%p split [0x%lx 0x%lx] to [0x%lx 0x%lx] size 0x%lx\n",
- prange->svms, prange->start, prange->last, start, last, size);
-
- if (start > prange->start) {
- r = svm_range_split(prange, start, prange->last, );
- if (r)
- return r;
- svm_range_add_child(parent, mm, head, SVM_OP_ADD_RANGE);
- }
-
- if (last < prange->last) {
- r = svm_range_split(prange, prange->start, last, );
- if (r)
- return r;
- svm_range_add_child(parent, mm, tail, SVM_OP_ADD_RANGE);
- }
-
- /* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */
- if (p->xnack_enabled && prange->work_item.op == SVM_OP_ADD_RANGE) {
- prange->work_item.op = SVM_OP_ADD_RANGE_AND_MAP;
- pr_debug("change prange 0x%p [0x%lx 0x%lx] op %d\n",
- prange, prange->start, prange->last,
- SVM_OP_ADD_RANGE_AND_MAP);
- }
- return 0;
-}
static bool
svm_nodes_in_same_hive(struct kfd_node *node_a, struct kfd_node *node_b)
{
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
index be11ba0c4289..026863a0abcd 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
@@ -172,9 +172,6 @@ struct kfd_node *svm_range_get_node_by_id(struct svm_range *prange,
int svm_range_vram_node_new(struct kfd_node *node, struct svm_range
Re: [PATCH] drm/amdkfd: Use partial mapping in GPU page fault recovery
On 10/19/2023 11:08 AM, Philip Yang wrote:
On 2023-10-19 10:24, Xiaogang.Chen wrote:
From: Xiaogang Chen
After partial migration to recover GPU page fault this patch does GPU vm
space mapping for same page range that got migrated instead of mapping all
pages of svm range in which the page fault happened.
Signed-off-by: Xiaogang Chen
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 33 +---
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 54af7a2b29f8..81dbcc8a4ccc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1619,6 +1619,7 @@ static void *kfd_svm_page_owner(struct kfd_process *p,
int32_t gpuidx)
* 5. Release page table (and SVM BO) reservation
*/
static int svm_range_validate_and_map(struct mm_struct *mm,
+ unsigned long map_start, unsigned long
map_last,
struct svm_range *prange, int32_t gpuidx,
bool intr, bool wait, bool flush_tlb)
{
@@ -1630,6 +1631,12 @@ static int svm_range_validate_and_map(struct mm_struct
*mm,
int32_t idx;
int r = 0;
+ if (map_start < prange->start || map_last > prange->last) {
This is not needed, as this case should never happen, and you also use
max/min to limit map_start, map_last below.
This was just a sanity check, I can remove it.
+ pr_debug("range [0x%lx 0x%lx] out prange [0x%lx 0x%lx]\n",
+map_start, map_last, prange->start,
prange->last);
+ return -EFAULT;
+ }
+
ctx = kzalloc(sizeof(struct svm_validate_context), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
@@ -1747,9 +1754,16 @@ static int svm_range_validate_and_map(struct mm_struct
*mm,
r = -EAGAIN;
}
- if (!r)
- r = svm_range_map_to_gpus(prange, offset, npages,
readonly,
- ctx->bitmap, wait, flush_tlb);
+ if (!r) {
+ map_start = max(map_start, prange->start + offset);
+ map_last = min(map_last, prange->start + offset +
npages);
This should move forward to outside the for loop, otherwise
amdgpu_hmm_range_get_pages and svm_range_dma_map still work on the
entire prange, and then prange->vram_pages update logic should be
changed accordingly.
We need use hmm function to get all vram page number on whole range as
we did not know how many vram pages after partial migration, then we
know if can release vram bo.
Regards
Xiaogang
Regards,
Philip
+ if (map_start <= map_last) {
+ offset = map_start - prange->start;
+ npages = map_last - map_start + 1;
+ r = svm_range_map_to_gpus(prange, offset,
npages, readonly,
+ ctx->bitmap, wait,
flush_tlb);
+ }
+ }
if (!r && next == end)
prange->mapped_to_gpu = true;
@@ -1855,8 +1869,8 @@ static void svm_range_restore_work(struct work_struct
*work)
*/
mutex_lock(>migrate_mutex);
- r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE,
- false, true, false);
+ r = svm_range_validate_and_map(mm, prange->start, prange->last,
prange,
+ MAX_GPU_INSTANCE, false, true,
false);
if (r)
pr_debug("failed %d to map 0x%lx to gpus\n", r,
prange->start);
@@ -3069,6 +3083,8 @@ svm_range_restore_pages(struct amdgpu_device *adev,
unsigned int pasid,
kfd_smi_event_page_fault_start(node, p->lead_thread->pid, addr,
write_fault, timestamp);
+ start = prange->start;
+ last = prange->last;
if (prange->actual_loc != 0 || best_loc != 0) {
migration = true;
/* Align migration range start and size to granularity size */
@@ -3102,10 +3118,11 @@ svm_range_restore_pages(struct amdgpu_device *adev,
unsigned int pasid,
}
}
- r = svm_range_validate_and_map(mm, prange, gpuidx, false, false, false);
+ r = svm_range_validate_and_map(mm, start, last, prange, gpuidx, false,
+ false, false);
if (r)
pr_debug("failed %d to map svms 0x%p [0x%lx 0x%lx] to gpus\n",
-r, svms, prange->start, prange->last);
+r, svms, start, last);
kfd_smi_event_page_fault_end(node, p->lead_thread->pid, addr,
migration);
@@
Re: [PATCH] drm/amdkfd: Use partial mapping in GPU page fault recovery
On 2023-10-19 10:24, Xiaogang.Chen
wrote:
From: Xiaogang Chen
After partial migration to recover GPU page fault this patch does GPU vm
space mapping for same page range that got migrated instead of mapping all
pages of svm range in which the page fault happened.
Signed-off-by: Xiaogang Chen
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 33 +---
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 54af7a2b29f8..81dbcc8a4ccc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1619,6 +1619,7 @@ static void *kfd_svm_page_owner(struct kfd_process *p, int32_t gpuidx)
* 5. Release page table (and SVM BO) reservation
*/
static int svm_range_validate_and_map(struct mm_struct *mm,
+ unsigned long map_start, unsigned long map_last,
struct svm_range *prange, int32_t gpuidx,
bool intr, bool wait, bool flush_tlb)
{
@@ -1630,6 +1631,12 @@ static int svm_range_validate_and_map(struct mm_struct *mm,
int32_t idx;
int r = 0;
+ if (map_start < prange->start || map_last > prange->last) {
This is not needed, as this case should never happen, and you also
use max/min to limit map_start, map_last below.
+ pr_debug("range [0x%lx 0x%lx] out prange [0x%lx 0x%lx]\n",
+ map_start, map_last, prange->start, prange->last);
+ return -EFAULT;
+ }
+
ctx = kzalloc(sizeof(struct svm_validate_context), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
@@ -1747,9 +1754,16 @@ static int svm_range_validate_and_map(struct mm_struct *mm,
r = -EAGAIN;
}
- if (!r)
- r = svm_range_map_to_gpus(prange, offset, npages, readonly,
- ctx->bitmap, wait, flush_tlb);
+ if (!r) {
+ map_start = max(map_start, prange->start + offset);
+ map_last = min(map_last, prange->start + offset + npages);
This should move forward to outside the for loop, otherwise
amdgpu_hmm_range_get_pages and svm_range_dma_map still work on the
entire prange, and then prange->vram_pages update logic should
be changed accordingly.
Regards,
Philip
+ if (map_start <= map_last) {
+offset = map_start - prange->start;
+npages = map_last - map_start + 1;
+r = svm_range_map_to_gpus(prange, offset, npages, readonly,
+ ctx->bitmap, wait, flush_tlb);
+ }
+ }
if (!r && next == end)
prange->mapped_to_gpu = true;
@@ -1855,8 +1869,8 @@ static void svm_range_restore_work(struct work_struct *work)
*/
mutex_lock(>migrate_mutex);
- r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE,
- false, true, false);
+ r = svm_range_validate_and_map(mm, prange->start, prange->last, prange,
+ MAX_GPU_INSTANCE, false, true, false);
if (r)
pr_debug("failed %d to map 0x%lx to gpus\n", r,
prange->start);
@@ -3069,6 +3083,8 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,
kfd_smi_event_page_fault_start(node, p->lead_thread->pid, addr,
write_fault, timestamp);
+ start = prange->start;
+ last = prange->last;
if (prange->actual_loc != 0 || best_loc != 0) {
migration = true;
/* Align migration range start and size to granularity size */
@@ -3102,10 +3118,11 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,
}
}
- r = svm_range_validate_and_map(mm, prange, gpuidx, false, false, false);
+ r = svm_range_validate_and_map(mm, start, last, prange, gpuidx, false,
+ false, false);
if (r)
pr_debug("failed %d to map svms 0x%p [0x%lx 0x%lx] to gpus\n",
- r, svms, prange->start, prange->last);
+ r, svms, start, last);
kfd_smi_event_page_fault_end(node, p->lead_thread->pid, addr,
migration);
@@ -3650,7 +3667,7 @@ svm_range_set_attr(struct kfd_process *p, struct mm_struct *mm,
flush_tlb = !migrated && update_mapping && prange->mapped_to_gpu;
- r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE,
+ r = svm_range_validate_and_map(mm, prange->start, prange->last, prange, MAX_GPU_INSTANCE,
true, true, flush_tlb);
if (r)
pr_debug("failed %d to map svm range\n", r);
Re: [PATCH] drm/amdgpu: Add timeout for sync wait
On 2023-10-19 05:31, Emily Deng wrote:
Issue: Dead heappen during gpu recover
[56433.829492] amdgpu :04:00.0: amdgpu: GPU reset begin!
[56550.499625] INFO: task kworker/u80:0:10 blocked for more than 120 seconds.
[56550.520215] Tainted: G OE 6.2.0-34-generic
#34~22.04.1-Ubuntu
[56550.542883] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this
message.
[56550.566313] task:kworker/u80:0 state:D stack:0 pid:10ppid:2
flags:0x4000
[56550.591318] Workqueue: kfd_restore_wq restore_process_worker [amdgpu]
[56550.611391] Call Trace:
[56550.618698]
[56550.624968] __schedule+0x2b7/0x5f0
[56550.635416] schedule+0x68/0x110
[56550.645090] schedule_timeout+0x151/0x160
[56550.657096] ? amdgpu_vm_bo_update+0x46e/0x660 [amdgpu]
[56550.673245] dma_fence_default_wait+0x1a2/0x1e0
[56550.686818] ? __pfx_dma_fence_default_wait_cb+0x10/0x10
[56550.702728] dma_fence_wait_timeout+0x117/0x140
[56550.716301] amdgpu_sync_wait+0x62/0xa0 [amdgpu]
[56550.730654] amdgpu_amdkfd_gpuvm_restore_process_bos+0x59e/0x770 [amdgpu]
[56550.751668] ? newidle_balance+0x298/0x490
[56550.763936] restore_process_worker+0x42/0x270 [amdgpu]
[56550.780183] process_one_work+0x21f/0x440
[56550.792193] worker_thread+0x50/0x3f0
[56550.803165] ? __pfx_worker_thread+0x10/0x10
[56550.815934] kthread+0xee/0x120
[56550.825342] ? __pfx_kthread+0x10/0x10
[56550.836548] ret_from_fork+0x2c/0x50
[56550.847262]
[ 1935.215502] Call Trace:
[ 1935.222827]
[ 1935.229121] __schedule+0x23d/0x5a0
[ 1935.239583] schedule+0x4e/0xc0
[ 1935.248983] schedule_timeout+0x103/0x140
[ 1935.261002] __wait_for_common+0xae/0x150
[ 1935.273008] ? usleep_range_state+0x90/0x90
[ 1935.285546] wait_for_completion+0x24/0x30
[ 1935.297813] __flush_work.isra.0+0x175/0x280
[ 1935.310611] ? worker_detach_from_pool+0xc0/0xc0
[ 1935.324436] flush_delayed_work+0x31/0x50
[ 1935.336455] kfd_suspend_all_processes+0x96/0x150 [amdgpu]
[ 1935.353429] kgd2kfd_suspend+0xb8/0xe0 [amdgpu]
[ 1935.367469] kgd2kfd_pre_reset+0x81/0xf0 [amdgpu]
[ 1935.382036] amdgpu_amdkfd_pre_reset+0x1a/0x30 [amdgpu]
[ 1935.398156] amdgpu_device_gpu_recover.cold+0x210/0xcf2 [amdgpu]
[ 1935.416722] amdgpu_job_timedout+0x19f/0x1e0 [amdgpu]
[ 1935.432367] drm_sched_job_timedout+0x6f/0x120 [amd_sched]
[ 1935.448792] process_one_work+0x22b/0x3d0
[ 1935.460806] worker_thread+0x53/0x420
[ 1935.471777] ? process_one_work+0x3d0/0x3d0
[ 1935.484307] kthread+0x12a/0x150
[ 1935.493993] ? set_kthread_struct+0x50/0x50
[ 1935.506513] ret_from_fork+0x22/0x30
Looking at the time stamps, this seems to be a mash-up of two different
logs. I think you're trying to show how a restore_processes worker is
stuck on a fence, and that's causing kgd2kfd_pre_reset to hang when it
tries to flush the work.
The fence it's hanging on is probably something related to a page table
update that got caught up in the GPU hang. Adding a timeout here seems
reasonable. There may be another problem, because
amdgpu_amdkfd_gpuvm_restore_process_bos ignores the return value of
amdgpu_sync_wait. We shouldi probably handle the timeout gracefully with
a "goto validate_map_fail".
Regards,
Felix
It is because the amdgpu_sync_wait is waiting for the bad job's fence, and
never return, so the recover couldn't continue.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index dcd8c066bc1f..c922867c5675 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -406,9 +406,19 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr)
int i, r;
hash_for_each_safe(sync->fences, i, tmp, e, node) {
- r = dma_fence_wait(e->fence, intr);
- if (r)
- return r;
+ struct drm_sched_fence *s_fence = to_drm_sched_fence(e->fence);
+
+ if (s_fence) {
+ r = dma_fence_wait_timeout(e->fence, intr,
s_fence->sched->timeout);
+ if (r == 0)
+ r = -ETIMEDOUT;
+ if (r < 0)
+ return r;
+ } else {
+ r = dma_fence_wait(e->fence, intr);
+ if (r)
+ return r;
+ }
amdgpu_sync_entry_free(e);
}
Re: [PATCH v2] drm/amdgpu: Add EXT_COHERENT support for APU and NUMA systems
On 2023-10-19 09:32, David Francis wrote:
On gfx943 APU, EXT_COHERENT should give MTYPE_CC for local and
MTYPE_UC for nonlocal memory.
On NUMA systems, local memory gets the local mtype, set by an
override callback. If EXT_COHERENT is set, memory will be set as
MTYPE_UC by default, with local memory MTYPE_CC.
Add an option in the override function for this case, and
add a check to ensure it is not used on UNCACHED memory.
Signed-off-by: David Francis
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 8 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 33 +++
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 8 +++---
5 files changed, 42 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 46d27c87..189341944bf1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -761,6 +761,7 @@ static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
* @immediate: immediate submission in a page fault
* @unlocked: unlocked invalidation during MM callback
* @flush_tlb: trigger tlb invalidation after update completed
+ * @allow_override: change MTYPE for local NUMA nodes
* @resv: fences we need to sync to
* @start: start of mapped range
* @last: last mapped entry
@@ -777,7 +778,7 @@ static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
* 0 for success, negative erro code for failure.
*/
int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- bool immediate, bool unlocked, bool flush_tlb,
+ bool immediate, bool unlocked, bool flush_tlb, bool
allow_override,
struct dma_resv *resv, uint64_t start, uint64_t last,
uint64_t flags, uint64_t offset, uint64_t vram_base,
struct ttm_resource *res, dma_addr_t *pages_addr,
@@ -815,6 +816,7 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
params.immediate = immediate;
params.pages_addr = pages_addr;
params.unlocked = unlocked;
+ params.allow_override = allow_override;
/* Implicitly sync to command submissions in the same VM before
* unmapping. Sync to moving fences before mapping.
@@ -1062,6 +1064,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va,
trace_amdgpu_vm_bo_update(mapping);
r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
+ !(bo->flags &
AMDGPU_GEM_CREATE_UNCACHED),
resv, mapping->start, mapping->last,
update_flags, mapping->offset,
vram_base, mem, pages_addr,
@@ -1257,8 +1260,8 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
mapping->start < AMDGPU_GMC_HOLE_START)
init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
- r = amdgpu_vm_update_range(adev, vm, false, false, true, resv,
- mapping->start, mapping->last,
+ r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
+ resv, mapping->start, mapping->last,
init_pte_value, 0, 0, NULL, NULL,
);
amdgpu_vm_free_mapping(adev, vm, mapping, f);
@@ -2546,8 +2549,8 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev,
u32 pasid,
goto error_unlock;
}
- r = amdgpu_vm_update_range(adev, vm, true, false, false, NULL, addr,
- addr, flags, value, 0, NULL, NULL, NULL);
+ r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
+ NULL, addr, addr, flags, value, 0, NULL,
NULL, NULL);
if (r)
goto error_unlock;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 6e71978db13f..9ea8b5b644e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -244,6 +244,12 @@ struct amdgpu_vm_update_params {
* @table_freed: return true if page table is freed when updating
*/
bool table_freed;
+
+ /**
+* @allow_override: true for memory that is not uncached: allows MTYPE
+* to be overridden for NUMA local memory.
+*/
+ bool allow_override;
};
struct amdgpu_vm_update_funcs {
@@ -436,7 +442,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
struct amdgpu_vm
Re: [linux-next:master] BUILD REGRESSION 2dac75696c6da3c848daa118a729827541c89d33
On Thu, Oct 19, 2023 at 04:07:35AM +0800, kernel test robot wrote: > arch/s390/include/asm/ctlreg.h:129:9: warning: array subscript 0 is outside > array bounds of 'struct ctlreg[0]' [-Warray-bounds=] > arch/s390/include/asm/ctlreg.h:80:9: warning: array subscript 0 is outside > array bounds of 'struct ctlreg[0]' [-Warray-bounds=] ... > |-- s390-defconfig > | `-- > arch-s390-include-asm-ctlreg.h:warning:array-subscript-is-outside-array-bounds-of-struct-ctlreg ... > s390defconfig gcc I'm wondering how this warning can appear in the builds. array-bounds warnings are explicitly disabled, see init/Kconfig: CC_NO_ARRAY_BOUNDS. And as expected, if I compile the kernel with gcc, defconfig, and with or without W=1 the option -Wno-array-bounds is passed to the compiler. And also as expected I do not see the above warnings. So something is quite odd here.
RE: [PATCH Review 1/1] drm/amdgpu: Enable RAS feature by default for APU
[AMD Official Use Only - General] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: amd-gfx On Behalf Of Stanley.Yang Sent: Thursday, October 19, 2023 22:52 To: amd-gfx@lists.freedesktop.org Cc: Yang, Stanley Subject: [PATCH Review 1/1] drm/amdgpu: Enable RAS feature by default for APU Enable RAS feature by default for aqua vanjaram on apu platform. Change-Id: I02105d07d169d1356251c994249a134ca5dd2a7a Signed-off-by: Stanley.Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 ++ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 01c2e8e8fb69..3dc82a213e96 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2640,18 +2640,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) /* hw_supported needs to be aligned with RAS block mask. */ adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; - - /* -* Disable ras feature for aqua vanjaram -* by default on apu platform. -*/ - if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) && - adev->gmc.is_app_apu) - adev->ras_enabled = amdgpu_ras_enable != 1 ? 0 : - adev->ras_hw_enabled & amdgpu_ras_mask; - else - adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : - adev->ras_hw_enabled & amdgpu_ras_mask; + adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : + adev->ras_hw_enabled & amdgpu_ras_mask; } static void amdgpu_ras_counte_dw(struct work_struct *work) -- 2.25.1
[PATCH Review 1/1] drm/amdgpu: Enable RAS feature by default for APU
Enable RAS feature by default for aqua vanjaram on apu platform. Change-Id: I02105d07d169d1356251c994249a134ca5dd2a7a Signed-off-by: Stanley.Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 ++ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 01c2e8e8fb69..3dc82a213e96 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2640,18 +2640,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) /* hw_supported needs to be aligned with RAS block mask. */ adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; - - /* -* Disable ras feature for aqua vanjaram -* by default on apu platform. -*/ - if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) && - adev->gmc.is_app_apu) - adev->ras_enabled = amdgpu_ras_enable != 1 ? 0 : - adev->ras_hw_enabled & amdgpu_ras_mask; - else - adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : - adev->ras_hw_enabled & amdgpu_ras_mask; + adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : + adev->ras_hw_enabled & amdgpu_ras_mask; } static void amdgpu_ras_counte_dw(struct work_struct *work) -- 2.25.1
Re: [PATCH] drm/amd/display: clean up some inconsistent indenting
Applied. Thanks! Alex On Wed, Oct 18, 2023 at 11:38 PM Jiapeng Chong wrote: > > No functional modification involved. > > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2902 dm_resume() > warn: inconsistent indenting. > > Reported-by: Abaci Robot > Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6940 > Signed-off-by: Jiapeng Chong > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 801f87a12ccf..0e1f8c5d7f9b 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -2899,7 +2899,7 @@ static int dm_resume(void *handle) > } > > /* power on hardware */ > -dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); > + dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); > > /* program HPD filter */ > dc_resume(dm->dc); > -- > 2.20.1.7.g153144c >
[PATCH] drm/amdkfd: Use partial mapping in GPU page fault recovery
From: Xiaogang Chen
After partial migration to recover GPU page fault this patch does GPU vm
space mapping for same page range that got migrated instead of mapping all
pages of svm range in which the page fault happened.
Signed-off-by: Xiaogang Chen
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 33 +---
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 54af7a2b29f8..81dbcc8a4ccc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1619,6 +1619,7 @@ static void *kfd_svm_page_owner(struct kfd_process *p,
int32_t gpuidx)
* 5. Release page table (and SVM BO) reservation
*/
static int svm_range_validate_and_map(struct mm_struct *mm,
+ unsigned long map_start, unsigned long
map_last,
struct svm_range *prange, int32_t gpuidx,
bool intr, bool wait, bool flush_tlb)
{
@@ -1630,6 +1631,12 @@ static int svm_range_validate_and_map(struct mm_struct
*mm,
int32_t idx;
int r = 0;
+ if (map_start < prange->start || map_last > prange->last) {
+ pr_debug("range [0x%lx 0x%lx] out prange [0x%lx 0x%lx]\n",
+map_start, map_last, prange->start,
prange->last);
+ return -EFAULT;
+ }
+
ctx = kzalloc(sizeof(struct svm_validate_context), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
@@ -1747,9 +1754,16 @@ static int svm_range_validate_and_map(struct mm_struct
*mm,
r = -EAGAIN;
}
- if (!r)
- r = svm_range_map_to_gpus(prange, offset, npages,
readonly,
- ctx->bitmap, wait, flush_tlb);
+ if (!r) {
+ map_start = max(map_start, prange->start + offset);
+ map_last = min(map_last, prange->start + offset +
npages);
+ if (map_start <= map_last) {
+ offset = map_start - prange->start;
+ npages = map_last - map_start + 1;
+ r = svm_range_map_to_gpus(prange, offset,
npages, readonly,
+ ctx->bitmap, wait,
flush_tlb);
+ }
+ }
if (!r && next == end)
prange->mapped_to_gpu = true;
@@ -1855,8 +1869,8 @@ static void svm_range_restore_work(struct work_struct
*work)
*/
mutex_lock(>migrate_mutex);
- r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE,
- false, true, false);
+ r = svm_range_validate_and_map(mm, prange->start, prange->last,
prange,
+ MAX_GPU_INSTANCE, false, true,
false);
if (r)
pr_debug("failed %d to map 0x%lx to gpus\n", r,
prange->start);
@@ -3069,6 +3083,8 @@ svm_range_restore_pages(struct amdgpu_device *adev,
unsigned int pasid,
kfd_smi_event_page_fault_start(node, p->lead_thread->pid, addr,
write_fault, timestamp);
+ start = prange->start;
+ last = prange->last;
if (prange->actual_loc != 0 || best_loc != 0) {
migration = true;
/* Align migration range start and size to granularity size */
@@ -3102,10 +3118,11 @@ svm_range_restore_pages(struct amdgpu_device *adev,
unsigned int pasid,
}
}
- r = svm_range_validate_and_map(mm, prange, gpuidx, false, false, false);
+ r = svm_range_validate_and_map(mm, start, last, prange, gpuidx, false,
+ false, false);
if (r)
pr_debug("failed %d to map svms 0x%p [0x%lx 0x%lx] to gpus\n",
-r, svms, prange->start, prange->last);
+r, svms, start, last);
kfd_smi_event_page_fault_end(node, p->lead_thread->pid, addr,
migration);
@@ -3650,7 +3667,7 @@ svm_range_set_attr(struct kfd_process *p, struct
mm_struct *mm,
flush_tlb = !migrated && update_mapping &&
prange->mapped_to_gpu;
- r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE,
+ r = svm_range_validate_and_map(mm, prange->start, prange->last,
prange, MAX_GPU_INSTANCE,
true, true, flush_tlb);
if (r)
pr_debug("failed %d to map svm range\n", r);
--
2.25.1
RE: [PATCH] drm/amdgpu: refine ras error kernel log print
[AMD Official Use Only - General]
dev_info(adev->dev, "socket: %d, die: %d "
-"%lld correctable hardware errors detected in
%s block\n",
+"new %lld correctable hardware errors detected
in %s block, "
+"no user action is needed.\n",
Hi Hawking,
There socket/die id information is already here for new error detect,
For the accumulated error of the current block, socket/die information is not
recorded now.
you mean we need to add socket/die id information for accumulated error?
Best Regards,
Kevin
-Original Message-
From: Zhang, Hawking
Sent: Thursday, October 19, 2023 9:23 PM
To: Wang, Yang(Kevin) ; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Chai, Thomas
Subject: RE: [PATCH] drm/amdgpu: refine ras error kernel log print
[AMD Official Use Only - General]
As discussed, please add socket id and die id in the output message.
Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin)
Sent: Thursday, October 19, 2023 20:51
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ;
Chai, Thomas ; Wang, Yang(Kevin)
Subject: [PATCH] drm/amdgpu: refine ras error kernel log print
refine ras error kernel log to avoid user-ridden ambiguity.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 5b831ba0ebb3..cebc19d810e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1034,10 +1034,11 @@ static void amdgpu_ras_error_print_error_data(struct
amdgpu_device *adev,
struct ras_err_info *err_info;
if (is_ue)
- dev_info(adev->dev, "%ld uncorrectable hardware errors detected
in %s block\n",
+ dev_info(adev->dev, "%ld uncorrectable hardware errors
+detected in total in %s block\n",
ras_mgr->err_data.ue_count, blk_name);
else
- dev_info(adev->dev, "%ld correctable hardware errors detected
in %s block\n",
+ dev_info(adev->dev, "%ld correctable hardware errors detected
in total in %s block, "
+"no user action is needed.\n",
ras_mgr->err_data.ce_count, blk_name);
for_each_ras_error(err_node, err_data) { @@ -1045,14 +1046,15 @@ static
void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
mcm_info = _info->mcm_info;
if (is_ue && err_info->ue_count) {
dev_info(adev->dev, "socket: %d, die: %d "
-"%lld uncorrectable hardware errors detected
in %s block\n",
+"new %lld uncorrectable hardware errors
+ detected in %s block\n",
mcm_info->socket_id,
mcm_info->die_id,
err_info->ue_count,
blk_name);
} else if (!is_ue && err_info->ce_count) {
dev_info(adev->dev, "socket: %d, die: %d "
-"%lld correctable hardware errors detected in
%s block\n",
+"new %lld correctable hardware errors detected
in %s block, "
+"no user action is needed.\n",
mcm_info->socket_id,
mcm_info->die_id,
err_info->ce_count,
--
2.34.1
[PATCH v2 23/24] drm/amd/display: Read before writing Backlight Mode Set Register
From: Iswara Nagulendran
[HOW]
Reading the value from
DP_EDP_BACKLIGHT_MODE_SET_REGISTER, DPCD 0x721
before setting the
BP_EDP_PANEL_LUMINANC_CONTROL_ENABLE bit
to ensure there are no accidental overwrites.
Reviewed-by: Sreeja Golui
Reviewed-by: Harry Vanzylldejong
Acked-by: Roman Li
Signed-off-by: Iswara Nagulendran
---
.../amd/display/dc/link/protocols/link_edp_panel_control.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 86f97ddcc595..e32a7974a4bc 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -182,7 +182,7 @@ bool edp_set_backlight_level_nits(struct dc_link *link,
_control, 1) != DC_OK)
return false;
} else {
- const uint8_t backlight_enable =
DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
+ uint8_t backlight_enable = 0;
struct target_luminance_value *target_luminance = NULL;
//if target luminance value is greater than 24 bits, clip the
value to 24 bits
@@ -191,6 +191,11 @@ bool edp_set_backlight_level_nits(struct dc_link *link,
target_luminance = (struct target_luminance_value
*)_millinits;
+ core_link_read_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ _enable, sizeof(uint8_t));
+
+ backlight_enable |= DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
+
if (core_link_write_dpcd(link,
DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
_enable,
sizeof(backlight_enable)) != DC_OK)
--
2.34.1
[PATCH v2 20/24] drm/amd/display: Fix shaper using bad LUT params
From: Ilya Bakoulin
[Why]
LUT params are not cleared after setting blend TF, which can lead to
same params being used for the shaper, if the shaper func is bypassed.
[How]
Set lut_params to NULL after program_1dlut.
Reviewed-by: Krunoslav Kovac
Acked-by: Roman Li
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index e837554b8a28..1b9f21fd4f17 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -494,6 +494,7 @@ bool dcn32_set_mcm_luts(
}
}
result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
+ lut_params = NULL;
// Shaper
if (plane_state->in_shaper_func) {
--
2.34.1
[PATCH v2 22/24] drm/amd/display: Disable SYMCLK32_SE RCO on DCN314
From: Michael Strauss
[WHY]
Currently causes some DP link layer failures, backing out until
the failures are root caused.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Roman Li
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 2d7436f2ea82..48bd56ca729b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -916,7 +916,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.hdmistream = true,
.hdmichar = true,
.dpstream = true,
- .symclk32_se = true,
+ .symclk32_se = false,
.symclk32_le = true,
.symclk_fe = true,
.physymclk = true,
--
2.34.1
[PATCH v2 19/24] drm/amd/display: add null check for invalid opps
From: Samson Tam
[Why]
In cases where number of pipes available is less
than num_opp, there will opp instances that are
null
[How]
Add null check to skip over these opp instances
Fixes: 9e241124fe13 ("drm/amd/display: Update OPP counter from new interface")
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c4962cc4bb93..52e8528aedbe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3574,7 +3574,8 @@ static void wait_for_outstanding_hw_updates(struct dc
*dc, const struct dc_state
mpcc_inst = hubp->inst;
// MPCC inst is equal to pipe index in practice
for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
- if
(dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
+ if ((dc->res_pool->opps[opp_inst] != NULL) &&
+
(dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
break;
--
2.34.1
[PATCH v2 17/24] drm/amd/display: fix num_ways overflow error
From: Samson Tam
[Why]
Helper function calculates num_ways using 32-bit. But is
returned as 8-bit. If num_ways exceeds 8-bit, then it
reports back the incorrect num_ways and erroneously
uses MALL when it should not
[How]
Make returned value 32-bit and convert after it checks
against caps.cache_num_ways, which is under 8-bit
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 68dc99034eba..2173d84e4953 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -217,7 +217,7 @@ static bool dcn32_check_no_memory_request_for_cab(struct dc
*dc)
static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state
*ctx)
{
int i;
- uint8_t num_ways = 0;
+ uint32_t num_ways = 0;
uint32_t mall_ss_size_bytes = 0;
mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
@@ -247,7 +247,8 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc
*dc, struct dc_state *c
bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
{
union dmub_rb_cmd cmd;
- uint8_t ways, i;
+ uint8_t i;
+ uint32_t ways;
int j;
bool mall_ss_unsupported = false;
struct dc_plane_state *plane = NULL;
@@ -307,7 +308,7 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc,
bool enable)
cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
cmd.cab.header.sub_type =
DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
cmd.cab.header.payload_bytes = sizeof(cmd.cab)
- sizeof(cmd.cab.header);
- cmd.cab.cab_alloc_ways = ways;
+ cmd.cab.cab_alloc_ways = (uint8_t)ways;
dm_execute_dmub_cmd(dc->ctx, ,
DM_DMUB_WAIT_TYPE_NO_WAIT);
--
2.34.1
[PATCH v2 24/24] drm/amd/display: add interface to query SubVP status
From: Aurabindo Pillai
[Why]
To enable automated testing through IGT, expose an API that is
accessible through debugfs to query current status of SubVP feature.
Reviewed-by: Alvin Lee
Acked-by: Roman Li
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 3 ++-
4 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 1259d6351c50..13a177d34376 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -3645,7 +3645,9 @@ static int capabilities_show(struct seq_file *m, void
*unused)
struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
struct dc *dc = adev->dm.dc;
bool mall_supported = dc->caps.mall_size_total;
+ bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
unsigned int mall_in_use = false;
+ unsigned int subvp_in_use = dc->cap_funcs.get_subvp_en(dc,
dc->current_state);
struct hubbub *hubbub = dc->res_pool->hubbub;
if (hubbub->funcs->get_mall_en)
@@ -3653,6 +3655,8 @@ static int capabilities_show(struct seq_file *m, void
*unused)
seq_printf(m, "mall supported: %s, enabled: %s\n",
mall_supported ? "yes" : "no", mall_in_use ? "yes" :
"no");
+ seq_printf(m, "sub-viewport supported: %s, enabled: %s\n",
+ subvp_supported ? "yes" : "no", subvp_in_use ? "yes"
: "no");
return 0;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index aa4684be1d62..e6e6377a8ce3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -382,6 +382,7 @@ struct dc_cap_funcs {
bool (*get_dcc_compression_cap)(const struct dc *dc,
const struct dc_dcc_surface_param *input,
struct dc_surface_dcc_cap *output);
+ bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
};
struct link_training_settings;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 0e1d395a9340..89b072447dba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1993,7 +1993,8 @@ int dcn32_populate_dml_pipes_from_context(
}
static struct dc_cap_funcs cap_funcs = {
- .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+ .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
+ .get_subvp_en = dcn32_subvp_in_use,
};
void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 9f6186be7cd8..be953cf8103d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1570,7 +1570,8 @@ static void dcn321_destroy_resource_pool(struct
resource_pool **pool)
}
static struct dc_cap_funcs cap_funcs = {
- .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+ .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
+ .get_subvp_en = dcn32_subvp_in_use,
};
static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params
*bw_params)
--
2.34.1
[PATCH v2 21/24] drm/amd/display: 3.2.256
From: Aric Cyr DC v3.2.256 Summary: * Fixes null-deref regression after "drm/amd/display: Update OPP counter from new interface" * Fixes display flashing when VSR and HDR enabled on dcn32 * Fixes dcn3x intermittent hangs due to FPO * Fixes MST Multi-Stream light up on dcn35 * Fixes green screen on DCN31x when DVI and HDMI monitors attached * Adds DML2 improvements * Adds idle power optimization improvements * Accommodates panels with lower nit backlight * Updates SDP VSC colorimetry from DP test automation request * Reverts "drm/amd/display: allow edp updates for virtual signal" Acked-by: Roman Li Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 47b767fb1ee8..aa4684be1d62 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -49,7 +49,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.255" +#define DC_VER "3.2.256" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.34.1
[PATCH v2 18/24] drm/amd/display: Update FAMS sequence for DCN30 & DCN32
From: Alvin Lee
Provide DCN32 specific sequence and update DCN30 sequence
Reviewed-by: Samson Tam
Acked-by: Roman Li
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 2 +-
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 21 ++---
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 31 +++
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 3 ++
4 files changed, 38 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
index 90f061edb64c..427cfc8c24a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -60,7 +60,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
.pipe_control_lock = dcn20_pipe_control_lock,
.interdependent_update_lock = dcn10_lock_all_pipes,
.cursor_lock = dcn10_cursor_lock,
- .prepare_bandwidth = dcn30_prepare_bandwidth,
+ .prepare_bandwidth = dcn32_prepare_bandwidth,
.optimize_bandwidth = dcn20_optimize_bandwidth,
.update_bandwidth = dcn20_update_bandwidth,
.set_drr = dcn10_set_drr,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 9247a8ed5570..fd8a8c10a201 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -997,11 +997,7 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
void dcn30_prepare_bandwidth(struct dc *dc,
struct dc_state *context)
{
- bool p_state_change_support =
context->bw_ctx.bw.dcn.clk.p_state_change_support;
- /* Any transition into an FPO config should disable MCLK switching
first to avoid
-* driver and FW P-State synchronization issues.
-*/
- if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||
dc->clk_mgr->clks.fw_based_mclk_switching) {
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching &&
!dc->clk_mgr->clks.fw_based_mclk_switching) {
dc->optimized_required = true;
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
}
@@ -1012,20 +1008,9 @@ void dcn30_prepare_bandwidth(struct dc *dc,
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr,
dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries
- 1].memclk_mhz);
dcn20_prepare_bandwidth(dc, context);
- /*
-* enabled -> enabled: do not disable
-* enabled -> disabled: disable
-* disabled -> enabled: don't care
-* disabled -> disabled: don't care
-*/
- if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
- dc_dmub_srv_p_state_delegate(dc, false, context);
- if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||
dc->clk_mgr->clks.fw_based_mclk_switching) {
- /* After disabling P-State, restore the original value to
ensure we get the correct P-State
-* on the next optimize. */
- context->bw_ctx.bw.dcn.clk.p_state_change_support =
p_state_change_support;
- }
+ if (!dc->clk_mgr->clks.fw_based_mclk_switching)
+ dc_dmub_srv_p_state_delegate(dc, false, context);
}
void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 2173d84e4953..e837554b8a28 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -50,6 +50,7 @@
#include "dce/dmub_hw_lock_mgr.h"
#include "dcn32/dcn32_resource.h"
#include "link.h"
+#include "../dcn20/dcn20_hwseq.h"
#define DC_LOGGER_INIT(logger)
@@ -1677,3 +1678,33 @@ bool dcn32_is_pipe_topology_transition_seamless(struct
dc *dc,
return is_seamless;
}
+
+void dcn32_prepare_bandwidth(struct dc *dc,
+ struct dc_state *context)
+{
+ bool p_state_change_support =
context->bw_ctx.bw.dcn.clk.p_state_change_support;
+ /* Any transition into an FPO config should disable MCLK switching
first to avoid
+* driver and FW P-State synchronization issues.
+*/
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||
dc->clk_mgr->clks.fw_based_mclk_switching) {
+ dc->optimized_required = true;
+ context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
+ }
+
+ if (dc->clk_mgr->dc_mode_softmax_enabled)
+ if (dc->clk_mgr->clks.dramclk_khz <=
dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
+ context->bw_ctx.bw.dcn.clk.dramclk_khz >
dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
+ dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr,
[PATCH v2 16/24] drm/amd/display: Add prefix for plane functions
From: Rodrigo Siqueira
This commit adds the amdgpu_dm_plane_ prefix for all functions in the
amdgpu_dm_plane.c. This change enables an easy way to filter code paths
via ftrace.
Reviewed-by: Aurabindo Pillai
Acked-by: Roman Li
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 542 +-
.../amd/display/amdgpu_dm/amdgpu_dm_plane.h | 2 +-
3 files changed, 275 insertions(+), 271 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 23088ddac649..cc0c819506cf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -10144,7 +10144,7 @@ static int dm_update_plane_state(struct dc *dc,
/* Block top most plane from being a video plane */
if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
- if
(is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
+ if
(amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) &&
*is_top_most_overlay)
return -EINVAL;
*is_top_most_overlay = false;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 03df26bd8e83..116121e647ca 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -139,7 +139,7 @@ void amdgpu_dm_plane_fill_blending_from_plane_state(const
struct drm_plane_state
}
}
-static void add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap,
uint64_t mod)
+static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size,
uint64_t *cap, uint64_t mod)
{
if (!*mods)
return;
@@ -164,12 +164,12 @@ static void add_modifier(uint64_t **mods, uint64_t *size,
uint64_t *cap, uint64_
*size += 1;
}
-static bool modifier_has_dcc(uint64_t modifier)
+static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier)
{
return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
}
-static unsigned int modifier_gfx9_swizzle_mode(uint64_t modifier)
+static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t
modifier)
{
if (modifier == DRM_FORMAT_MOD_LINEAR)
return 0;
@@ -177,8 +177,8 @@ static unsigned int modifier_gfx9_swizzle_mode(uint64_t
modifier)
return AMD_FMT_MOD_GET(TILE, modifier);
}
-static void fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
-uint64_t tiling_flags)
+static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union
dc_tiling_info *tiling_info,
+uint64_t
tiling_flags)
{
/* Fill GFX8 params */
if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) ==
DC_ARRAY_2D_TILED_THIN1) {
@@ -209,8 +209,8 @@ static void fill_gfx8_tiling_info_from_flags(union
dc_tiling_info *tiling_info,
AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
}
-static void fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
- union dc_tiling_info *tiling_info)
+static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct
amdgpu_device *adev,
+ union
dc_tiling_info *tiling_info)
{
/* Fill GFX9 params */
tiling_info->gfx9.num_pipes =
@@ -230,9 +230,9 @@ static void fill_gfx9_tiling_info_from_device(const struct
amdgpu_device *adev,
tiling_info->gfx9.num_pkrs =
adev->gfx.config.gb_addr_config_fields.num_pkrs;
}
-static void fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device
*adev,
- union dc_tiling_info *tiling_info,
- uint64_t modifier)
+static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct
amdgpu_device *adev,
+ union
dc_tiling_info *tiling_info,
+ uint64_t
modifier)
{
unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS,
modifier);
unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS,
modifier);
@@ -241,7 +241,7 @@ static void fill_gfx9_tiling_info_from_modifier(const
struct amdgpu_device *adev
pipes_log2 = min(5u, mod_pipe_xor_bits);
- fill_gfx9_tiling_info_from_device(adev, tiling_info);
+ amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info);
if (!IS_AMD_FMT_MOD(modifier))
return;
@@ -258,13 +258,13 @@ static void fill_gfx9_tiling_info_from_modifier(const
[PATCH v2 15/24] drm/amd/display: Add prefix to amdgpu crtc functions
From: Rodrigo Siqueira
The ftrace debug feature allows filtering functions based on a prefix,
which can be helpful in some complex debug scenarios. The driver can
benefit more from this feature if the function name follows some
patterns; for this reason, this commit adds the prefix amdgpu_dm_crtc_
to all the functions that do not have it in the amdgpu_dm_crtc.c file.
Reviewed-by: Aurabindo Pillai
Acked-by: Roman Li
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 48 +--
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 440fc0869a34..611849e3bf91 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -95,7 +95,7 @@ bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
}
-static void vblank_control_worker(struct work_struct *work)
+static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
{
struct vblank_control_work *vblank_work =
container_of(work, struct vblank_control_work, work);
@@ -144,7 +144,7 @@ static void vblank_control_worker(struct work_struct *work)
kfree(vblank_work);
}
-static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
+static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
{
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
@@ -184,7 +184,7 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool
enable)
if (!work)
return -ENOMEM;
- INIT_WORK(>work, vblank_control_worker);
+ INIT_WORK(>work, amdgpu_dm_crtc_vblank_control_worker);
work->dm = dm;
work->acrtc = acrtc;
work->enable = enable;
@@ -202,15 +202,15 @@ static inline int dm_set_vblank(struct drm_crtc *crtc,
bool enable)
int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
{
- return dm_set_vblank(crtc, true);
+ return amdgpu_dm_crtc_set_vblank(crtc, true);
}
void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
{
- dm_set_vblank(crtc, false);
+ amdgpu_dm_crtc_set_vblank(crtc, false);
}
-static void dm_crtc_destroy_state(struct drm_crtc *crtc,
+static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct dm_crtc_state *cur = to_dm_crtc_state(state);
@@ -226,7 +226,7 @@ static void dm_crtc_destroy_state(struct drm_crtc *crtc,
kfree(state);
}
-static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc)
+static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc
*crtc)
{
struct dm_crtc_state *state, *cur;
@@ -266,12 +266,12 @@ static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
kfree(crtc);
}
-static void dm_crtc_reset_state(struct drm_crtc *crtc)
+static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
{
struct dm_crtc_state *state;
if (crtc->state)
- dm_crtc_destroy_state(crtc, crtc->state);
+ amdgpu_dm_crtc_destroy_state(crtc, crtc->state);
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (WARN_ON(!state))
@@ -291,12 +291,12 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc
*crtc)
/* Implemented only the options currently available for the driver */
static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
- .reset = dm_crtc_reset_state,
+ .reset = amdgpu_dm_crtc_reset_state,
.destroy = amdgpu_dm_crtc_destroy,
.set_config = drm_atomic_helper_set_config,
.page_flip = drm_atomic_helper_page_flip,
- .atomic_duplicate_state = dm_crtc_duplicate_state,
- .atomic_destroy_state = dm_crtc_destroy_state,
+ .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
+ .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
.set_crc_source = amdgpu_dm_crtc_set_crc_source,
.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
@@ -309,11 +309,11 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs =
{
#endif
};
-static void dm_crtc_helper_disable(struct drm_crtc *crtc)
+static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
{
}
-static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
+static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state
*new_crtc_state)
{
struct drm_atomic_state *state = new_crtc_state->state;
struct drm_plane *plane;
@@ -345,8 +345,8 @@ static int count_crtc_active_planes(struct drm_crtc_state
[PATCH v2 14/24] drm/amd/display: Correct enum typo
From: Rodrigo Siqueira
This commit just replaces dc_interrupt_po*r*larity with its correct
name, which is dc_interrupt_polarity.
Reviewed-by: Aurabindo Pillai
Acked-by: Roman Li
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/irq_types.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h
b/drivers/gpu/drm/amd/display/dc/irq_types.h
index 530c2578db40..93354bff456a 100644
--- a/drivers/gpu/drm/amd/display/dc/irq_types.h
+++ b/drivers/gpu/drm/amd/display/dc/irq_types.h
@@ -178,7 +178,7 @@ enum dc_interrupt_context {
INTERRUPT_CONTEXT_NUMBER
};
-enum dc_interrupt_porlarity {
+enum dc_interrupt_polarity {
INTERRUPT_POLARITY_DEFAULT = 0,
INTERRUPT_POLARITY_LOW = INTERRUPT_POLARITY_DEFAULT,
INTERRUPT_POLARITY_HIGH,
@@ -199,12 +199,12 @@ struct dc_interrupt_params {
/* The polarity *change* which will trigger an interrupt.
* If 'requested_polarity == INTERRUPT_POLARITY_BOTH', then
* 'current_polarity' must be initialised. */
- enum dc_interrupt_porlarity requested_polarity;
+ enum dc_interrupt_polarity requested_polarity;
/* If 'requested_polarity == INTERRUPT_POLARITY_BOTH',
* 'current_polarity' should contain the current state, which means
* the interrupt will be triggered when state changes from what is,
* in 'current_polarity'. */
- enum dc_interrupt_porlarity current_polarity;
+ enum dc_interrupt_polarity current_polarity;
enum dc_irq_source irq_source;
enum dc_interrupt_context int_context;
};
--
2.34.1
[PATCH v2 11/24] drm/amd/display: Fix HDMI framepack 3D test issue
From: Sung Joon Kim
[why]
Bandwidth validation failure on framepack tests.
Need to double pixel clock when 3D format is
framepack. Also for HDMI displays, we need to
keep the ITC flag to 1 by default.
[how]
Double the pixel clock when using framepack 3D format.
Set hdmi ITC bit to 1.
Reviewed-by: Charlene Liu
Acked-by: Roman Li
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 97f402123fbb..f0e437f8ea3f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -4228,7 +4228,7 @@ static void set_avi_info_frame(
switch (stream->content_type) {
case DISPLAY_CONTENT_TYPE_NO_DATA:
hdmi_info.bits.CN0_CN1 = 0;
- hdmi_info.bits.ITC = 0;
+ hdmi_info.bits.ITC = 1;
break;
case DISPLAY_CONTENT_TYPE_GRAPHICS:
hdmi_info.bits.CN0_CN1 = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index e5ccd2887c94..adf835279d6b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -569,6 +569,8 @@ static void
populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *
out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) /
in->timing.h_total) / in->timing.v_total;
out->VFrontPorch[location] = in->timing.v_front_porch;
out->PixelClock[location] = in->timing.pix_clk_100hz / 1.00;
+ if (in->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
+ out->PixelClock[location] *= 2;
out->HTotal[location] = in->timing.h_total;
out->VTotal[location] = in->timing.v_total;
out->Interlace[location] = in->timing.flags.INTERLACE;
--
2.34.1
[PATCH v2] drm/amdgpu: Add EXT_COHERENT support for APU and NUMA systems
On gfx943 APU, EXT_COHERENT should give MTYPE_CC for local and
MTYPE_UC for nonlocal memory.
On NUMA systems, local memory gets the local mtype, set by an
override callback. If EXT_COHERENT is set, memory will be set as
MTYPE_UC by default, with local memory MTYPE_CC.
Add an option in the override function for this case, and
add a check to ensure it is not used on UNCACHED memory.
Signed-off-by: David Francis
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 8 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 33 +++
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 8 +++---
5 files changed, 42 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 46d27c87..189341944bf1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -761,6 +761,7 @@ static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
* @immediate: immediate submission in a page fault
* @unlocked: unlocked invalidation during MM callback
* @flush_tlb: trigger tlb invalidation after update completed
+ * @allow_override: change MTYPE for local NUMA nodes
* @resv: fences we need to sync to
* @start: start of mapped range
* @last: last mapped entry
@@ -777,7 +778,7 @@ static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
* 0 for success, negative erro code for failure.
*/
int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- bool immediate, bool unlocked, bool flush_tlb,
+ bool immediate, bool unlocked, bool flush_tlb, bool
allow_override,
struct dma_resv *resv, uint64_t start, uint64_t last,
uint64_t flags, uint64_t offset, uint64_t vram_base,
struct ttm_resource *res, dma_addr_t *pages_addr,
@@ -815,6 +816,7 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
params.immediate = immediate;
params.pages_addr = pages_addr;
params.unlocked = unlocked;
+ params.allow_override = allow_override;
/* Implicitly sync to command submissions in the same VM before
* unmapping. Sync to moving fences before mapping.
@@ -1062,6 +1064,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va,
trace_amdgpu_vm_bo_update(mapping);
r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
+ !(bo->flags &
AMDGPU_GEM_CREATE_UNCACHED),
resv, mapping->start, mapping->last,
update_flags, mapping->offset,
vram_base, mem, pages_addr,
@@ -1257,8 +1260,8 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
mapping->start < AMDGPU_GMC_HOLE_START)
init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
- r = amdgpu_vm_update_range(adev, vm, false, false, true, resv,
- mapping->start, mapping->last,
+ r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
+ resv, mapping->start, mapping->last,
init_pte_value, 0, 0, NULL, NULL,
);
amdgpu_vm_free_mapping(adev, vm, mapping, f);
@@ -2546,8 +2549,8 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev,
u32 pasid,
goto error_unlock;
}
- r = amdgpu_vm_update_range(adev, vm, true, false, false, NULL, addr,
- addr, flags, value, 0, NULL, NULL, NULL);
+ r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
+ NULL, addr, addr, flags, value, 0, NULL,
NULL, NULL);
if (r)
goto error_unlock;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 6e71978db13f..9ea8b5b644e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -244,6 +244,12 @@ struct amdgpu_vm_update_params {
* @table_freed: return true if page table is freed when updating
*/
bool table_freed;
+
+ /**
+* @allow_override: true for memory that is not uncached: allows MTYPE
+* to be overridden for NUMA local memory.
+*/
+ bool allow_override;
};
struct amdgpu_vm_update_funcs {
@@ -436,7 +442,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
struct amdgpu_vm *vm, struct amdgpu_bo *bo);
int
[PATCH v2 13/24] drm/amd/display: Set emulated sink type to HDMI accordingly.
From: Alex Hung [WHY & HOW] Virtual sink is not audio-capable and this causes kms_hdmi_inject's inject-audio to fail. Set it to HDMI according to EDID. Reviewed-by: Chao-kai Wang Acked-by: Roman Li Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 02eca0856eca..23088ddac649 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6593,6 +6593,9 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) return; } + if (drm_detect_hdmi_monitor(edid)) + init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; + aconnector->edid = edid; aconnector->dc_em_sink = dc_link_add_remote_sink( -- 2.34.1
[PATCH v2 12/24] drm/amd/display: Revert "drm/amd/display: allow edp updates for virtual signal"
From: Alex Hung
This reverts commit 4ad3ee5ccc77aa3f9d702f7b9ad4d9cfeca6c443.
[WHY & HOW]
Virtual signal is not supported as audio capable by DC.
Reviewed-by: Chao-kai Wang
Acked-by: Roman Li
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/include/signal_types.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h
b/drivers/gpu/drm/amd/display/include/signal_types.h
index 325c5ba4c82a..1b14b17a79c7 100644
--- a/drivers/gpu/drm/amd/display/include/signal_types.h
+++ b/drivers/gpu/drm/amd/display/include/signal_types.h
@@ -132,7 +132,6 @@ static inline bool dc_is_audio_capable_signal(enum
signal_type signal)
{
return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
- signal == SIGNAL_TYPE_VIRTUAL ||
dc_is_hdmi_signal(signal));
}
--
2.34.1
[PATCH v2 10/24] drm/amd/display: Fix IPS handshake for idle optimizations
From: Nicholas Kazlauskas
[Why]
Intermittent reboot hangs are observed introduced by
"Improve x86 and dmub ips handshake".
[How]
Bring back the commit but fix the polling.
Avoid hanging in place forever by bounding the delay and ensure that
we still message DMCUB on IPS2 exit to notify driver idle has been
cleared.
Reviewed-by: Duncan Ma
Reviewed-by: Jun Lei
Acked-by: Roman Li
Signed-off-by: Nicholas Kazlauskas
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 37 ++
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 14 +++-
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.h | 4 +-
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 73 ---
.../gpu/drm/amd/display/dc/dcn35/dcn35_init.c | 2 +
.../drm/amd/display/dc/dcn35/dcn35_resource.c | 2 +
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 30 +---
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 3 +
.../drm/amd/display/dc/hwss/hw_sequencer.h| 1 -
10 files changed, 141 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 302a3d348c76..f80917f6153b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -808,6 +808,34 @@ static void dcn35_set_low_power_state(struct clk_mgr
*clk_mgr_base)
}
}
+static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ struct dc *dc = clk_mgr_base->ctx->dc;
+ uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);
+
+ if (dc->config.disable_ips == 0) {
+ val |= DMUB_IPS1_ALLOW_MASK;
+ val |= DMUB_IPS2_ALLOW_MASK;
+ } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
+ val = val & ~DMUB_IPS1_ALLOW_MASK;
+ val = val & ~DMUB_IPS2_ALLOW_MASK;
+ } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
+ val |= DMUB_IPS1_ALLOW_MASK;
+ val = val & ~DMUB_IPS2_ALLOW_MASK;
+ } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
+ val |= DMUB_IPS1_ALLOW_MASK;
+ val |= DMUB_IPS2_ALLOW_MASK;
+ }
+
+ if (!allow_idle) {
+ val = val & ~DMUB_IPS1_ALLOW_MASK;
+ val = val & ~DMUB_IPS2_ALLOW_MASK;
+ }
+
+ dcn35_smu_write_ips_scratch(clk_mgr, val);
+}
+
static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
@@ -827,6 +855,13 @@ static bool dcn35_is_ips_supported(struct clk_mgr
*clk_mgr_base)
return ips_supported;
}
+static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+ return dcn35_smu_read_ips_scratch(clk_mgr);
+}
+
static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
{
dcn35_init_clocks(clk_mgr);
@@ -914,6 +949,8 @@ static struct clk_mgr_funcs dcn35_funcs = {
.set_low_power_state = dcn35_set_low_power_state,
.exit_low_power_state = dcn35_exit_low_power_state,
.is_ips_supported = dcn35_is_ips_supported,
+ .set_idle_state = dcn35_set_idle_state,
+ .get_idle_state = dcn35_get_idle_state
};
struct clk_mgr_funcs dcn35_fpga_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index b20b3a5eb3c4..b6b8c3ca1572 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -444,9 +444,9 @@ void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct
clk_mgr_internal *cl
enable);
}
-void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
+int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
{
- dcn35_smu_send_msg_with_param(
+ return dcn35_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_DispPsrExit,
0);
@@ -459,3 +459,13 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal
*clk_mgr)
VBIOSSMC_MSG_QueryIPS2Support,
0);
}
+
+void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t
param)
+{
+ REG_WRITE(MP1_SMN_C2PMSG_71, param);
+}
+
+uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
+{
+ return REG_READ(MP1_SMN_C2PMSG_71);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
index 38b7a4420d6c..2b8e6959a03d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
+++
[PATCH v2 09/24] drm/amd/display: implement map dc pipe with callback in DML2
From: Wenjing Liu
[why]
Unify pipe resource management logic in dc resource layer.
V2:
Add default case for switch.
CC: Hamza Mahfooz
Reviewed-by: Chaitanya Dhere
Signed-off-by: Wenjing Liu
Reviewed-by: Rodrigo Siqueira
Reviewed-by: Jun Lei
Acked-by: Roman Li
Signed-off-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 146 ++
.../drm/amd/display/dc/dml2/dml2_wrapper.h| 1 +
3 files changed, 148 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 02d3168f1673..0e1d395a9340 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2481,6 +2481,7 @@ static bool dcn32_resource_construct(
dc->dml2_options.max_segments_per_hubp = 18;
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
+ dc->dml2_options.map_dc_pipes_with_callbacks = true;
if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) &&
(dc->config.sdpif_request_limit_words_per_umc == 0))
dc->config.sdpif_request_limit_words_per_umc = 16;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
index 36baf35bb170..fc266c6e1398 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
@@ -756,6 +756,148 @@ static void map_pipes_for_plane(struct dml2_context *ctx,
struct dc_state *state
free_unused_pipes_for_plane(ctx, state, plane, >pipe_pool,
stream->stream_id);
}
+static unsigned int get_mpc_factor(struct dml2_context *ctx,
+ const struct dc_state *state,
+ const struct dml_display_cfg_st *disp_cfg,
+ struct dml2_dml_to_dc_pipe_mapping *mapping,
+ const struct dc_stream_status *status, unsigned int stream_id,
+ int plane_idx)
+{
+ unsigned int plane_id;
+ unsigned int cfg_idx;
+
+ get_plane_id(state, status->plane_states[plane_idx], stream_id,
_id);
+ cfg_idx = find_disp_cfg_idx_by_plane_id(mapping, plane_id);
+ if (ctx->architecture == dml2_architecture_20)
+ return (unsigned int)disp_cfg->hw.DPPPerSurface[cfg_idx];
+ ASSERT(false);
+ return 1;
+}
+
+static unsigned int get_odm_factor(
+ const struct dml2_context *ctx,
+ const struct dml_display_cfg_st *disp_cfg,
+ struct dml2_dml_to_dc_pipe_mapping *mapping,
+ const struct dc_stream_state *stream)
+{
+ unsigned int cfg_idx = find_disp_cfg_idx_by_stream_id(
+ mapping, stream->stream_id);
+
+ if (ctx->architecture == dml2_architecture_20)
+ switch (disp_cfg->hw.ODMMode[cfg_idx]) {
+ case dml_odm_mode_bypass:
+ return 1;
+ case dml_odm_mode_combine_2to1:
+ return 2;
+ case dml_odm_mode_combine_4to1:
+ return 4;
+ default:
+ break;
+ }
+ ASSERT(false);
+ return 1;
+}
+
+static void populate_mpc_factors_for_stream(
+ struct dml2_context *ctx,
+ const struct dml_display_cfg_st *disp_cfg,
+ struct dml2_dml_to_dc_pipe_mapping *mapping,
+ const struct dc_state *state,
+ unsigned int stream_idx,
+ unsigned int odm_factor,
+ unsigned int mpc_factors[MAX_PIPES])
+{
+ const struct dc_stream_status *status =
>stream_status[stream_idx];
+ unsigned int stream_id = state->streams[stream_idx]->stream_id;
+ int i;
+
+ for (i = 0; i < status->plane_count; i++)
+ if (odm_factor == 1)
+ mpc_factors[i] = get_mpc_factor(
+ ctx, state, disp_cfg, mapping, status,
+ stream_id, i);
+ else
+ mpc_factors[i] = 1;
+}
+
+static void populate_odm_factors(const struct dml2_context *ctx,
+ const struct dml_display_cfg_st *disp_cfg,
+ struct dml2_dml_to_dc_pipe_mapping *mapping,
+ const struct dc_state *state,
+ unsigned int odm_factors[MAX_PIPES])
+{
+ int i;
+
+ for (i = 0; i < state->stream_count; i++)
+ odm_factors[i] = get_odm_factor(
+ ctx, disp_cfg, mapping, state->streams[i]);
+}
+
+static bool map_dc_pipes_for_stream(struct dml2_context *ctx,
+ struct dc_state *state,
+ const struct dc_state *existing_state,
+ const struct dc_stream_state *stream,
+ const struct dc_stream_status *status,
+
[PATCH v2 06/24] drm/amd/display: Update SDP VSC colorimetry from DP test automation request
From: George Shen [Why] Certain test equipment vendors check the SDP VSC for colorimetry against the value from the test request during certain DP link layer tests for YCbCr test cases. [How] Update SDP VSC with colorimetry from test automation request. Reviewed-by: Wenjing Liu Acked-by: Roman Li Signed-off-by: George Shen --- .../gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index 0894e6aef3dd..21a39afd274b 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -839,6 +839,12 @@ bool dp_set_test_pattern( pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range else pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7); + + if (color_space == COLOR_SPACE_YCBCR601_LIMITED) + pipe_ctx->stream->vsc_infopacket.sb[16] &= 0xf0; + else if (color_space == COLOR_SPACE_YCBCR709_LIMITED) + pipe_ctx->stream->vsc_infopacket.sb[16] |= 1; + resource_build_info_frame(pipe_ctx); link->dc->hwss.update_info_frame(pipe_ctx); } -- 2.34.1
[PATCH v2 08/24] drm/amd/display: add pipe resource management callbacks to DML2
From: Wenjing Liu
[why]
Need DML2 to support new pipe resource management APIs.
Reviewed-by: Chaitanya Dhere
Acked-by: Roman Li
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 5 +
.../drm/amd/display/dc/dcn321/dcn321_resource.c | 5 +
.../gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 5 +
.../gpu/drm/amd/display/dc/dml2/dml2_wrapper.h| 15 +++
4 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 81b0588fa80b..02d3168f1673 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2445,6 +2445,11 @@ static bool dcn32_resource_construct(
dc->dml2_options.callbacks.build_scaling_params =
_build_scaling_params;
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch
= _can_support_mclk_switch_using_fw_based_vblank_stretch;
dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm =
_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
+ dc->dml2_options.callbacks.update_pipes_for_stream_with_slice_count =
_update_pipes_for_stream_with_slice_count;
+ dc->dml2_options.callbacks.update_pipes_for_plane_with_slice_count =
_update_pipes_for_plane_with_slice_count;
+ dc->dml2_options.callbacks.get_mpc_slice_index =
_get_mpc_slice_index;
+ dc->dml2_options.callbacks.get_odm_slice_index =
_get_odm_slice_index;
+ dc->dml2_options.callbacks.get_opp_head = _get_opp_head;
dc->dml2_options.svp_pstate.callbacks.dc = dc;
dc->dml2_options.svp_pstate.callbacks.add_plane_to_context =
_add_plane_to_context;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 44caf6711589..9f6186be7cd8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1998,6 +1998,11 @@ static bool dcn321_resource_construct(
dc->dml2_options.callbacks.build_scaling_params =
_build_scaling_params;
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch
= _can_support_mclk_switch_using_fw_based_vblank_stretch;
dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm =
_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
+ dc->dml2_options.callbacks.update_pipes_for_stream_with_slice_count =
_update_pipes_for_stream_with_slice_count;
+ dc->dml2_options.callbacks.update_pipes_for_plane_with_slice_count =
_update_pipes_for_plane_with_slice_count;
+ dc->dml2_options.callbacks.get_mpc_slice_index =
_get_mpc_slice_index;
+ dc->dml2_options.callbacks.get_odm_slice_index =
_get_odm_slice_index;
+ dc->dml2_options.callbacks.get_opp_head = _get_opp_head;
dc->dml2_options.svp_pstate.callbacks.dc = dc;
dc->dml2_options.svp_pstate.callbacks.add_plane_to_context =
_add_plane_to_context;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index 4e03c9d663de..682bf93049b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -2082,6 +2082,11 @@ static bool dcn35_resource_construct(
dc->dml2_options.callbacks.build_scaling_params =
_build_scaling_params;
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch
= _can_support_mclk_switch_using_fw_based_vblank_stretch;
dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm =
_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
+ dc->dml2_options.callbacks.update_pipes_for_stream_with_slice_count =
_update_pipes_for_stream_with_slice_count;
+ dc->dml2_options.callbacks.update_pipes_for_plane_with_slice_count =
_update_pipes_for_plane_with_slice_count;
+ dc->dml2_options.callbacks.get_mpc_slice_index =
_get_mpc_slice_index;
+ dc->dml2_options.callbacks.get_odm_slice_index =
_get_odm_slice_index;
+ dc->dml2_options.callbacks.get_opp_head = _get_opp_head;
dc->dml2_options.max_segments_per_hubp = 24;
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
index f3b85b0891d3..c3d5b84ee914 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
@@ -71,6 +71,21 @@ struct dml2_dc_callbacks {
bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);
bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc
*dc, struct dc_state *context);
bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct
dc_state *state,
[PATCH v2 04/24] drm/amd/display: Revert "Improve x86 and dmub ips handshake"
From: Nicholas Kazlauskas
This reverts commit 8316378d272ed96f60177cc9a8beaadb8640f745.
Causes intermittent hangs during reboot stress testing.
Reviewed-by: Duncan Ma
Acked-by: Roman Li
Signed-off-by: Nicholas Kazlauskas
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 37
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 14 +
.../amd/display/dc/clk_mgr/dcn35/dcn35_smu.h | 4 +-
drivers/gpu/drm/amd/display/dc/dc.h | 2 -
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 57 ---
.../gpu/drm/amd/display/dc/dcn35/dcn35_init.c | 2 -
.../drm/amd/display/dc/dcn35/dcn35_resource.c | 2 -
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 30 --
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 3 -
.../drm/amd/display/dc/hwss/hw_sequencer.h| 3 +-
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 -
11 files changed, 27 insertions(+), 129 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index f80917f6153b..302a3d348c76 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -808,34 +808,6 @@ static void dcn35_set_low_power_state(struct clk_mgr
*clk_mgr_base)
}
}
-static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
-{
- struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
- struct dc *dc = clk_mgr_base->ctx->dc;
- uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);
-
- if (dc->config.disable_ips == 0) {
- val |= DMUB_IPS1_ALLOW_MASK;
- val |= DMUB_IPS2_ALLOW_MASK;
- } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
- val = val & ~DMUB_IPS1_ALLOW_MASK;
- val = val & ~DMUB_IPS2_ALLOW_MASK;
- } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
- val |= DMUB_IPS1_ALLOW_MASK;
- val = val & ~DMUB_IPS2_ALLOW_MASK;
- } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
- val |= DMUB_IPS1_ALLOW_MASK;
- val |= DMUB_IPS2_ALLOW_MASK;
- }
-
- if (!allow_idle) {
- val = val & ~DMUB_IPS1_ALLOW_MASK;
- val = val & ~DMUB_IPS2_ALLOW_MASK;
- }
-
- dcn35_smu_write_ips_scratch(clk_mgr, val);
-}
-
static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
@@ -855,13 +827,6 @@ static bool dcn35_is_ips_supported(struct clk_mgr
*clk_mgr_base)
return ips_supported;
}
-static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base)
-{
- struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-
- return dcn35_smu_read_ips_scratch(clk_mgr);
-}
-
static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
{
dcn35_init_clocks(clk_mgr);
@@ -949,8 +914,6 @@ static struct clk_mgr_funcs dcn35_funcs = {
.set_low_power_state = dcn35_set_low_power_state,
.exit_low_power_state = dcn35_exit_low_power_state,
.is_ips_supported = dcn35_is_ips_supported,
- .set_idle_state = dcn35_set_idle_state,
- .get_idle_state = dcn35_get_idle_state
};
struct clk_mgr_funcs dcn35_fpga_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index b6b8c3ca1572..b20b3a5eb3c4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -444,9 +444,9 @@ void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct
clk_mgr_internal *cl
enable);
}
-int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
+void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
{
- return dcn35_smu_send_msg_with_param(
+ dcn35_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_DispPsrExit,
0);
@@ -459,13 +459,3 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal
*clk_mgr)
VBIOSSMC_MSG_QueryIPS2Support,
0);
}
-
-void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t
param)
-{
- REG_WRITE(MP1_SMN_C2PMSG_71, param);
-}
-
-uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
-{
- return REG_READ(MP1_SMN_C2PMSG_71);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
index 2b8e6959a03d..38b7a4420d6c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
@@ -194,10 +194,8 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal
*clk_mgr, enum
[PATCH v2 07/24] drm/amd/display: Reduce default backlight min from 5 nits to 1 nits
From: Swapnil Patel
[Why & How]
Currently set_default_brightness_aux function uses 5 nits as lower limit
to check for valid default_backlight setting. However some newer panels
can support even lower default settings
Reviewed-by: Agustin Gutierrez
Acked-by: Roman Li
Signed-off-by: Swapnil Patel
---
.../amd/display/dc/link/protocols/link_edp_panel_control.c| 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 938df1f0f7da..86f97ddcc595 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -283,8 +283,8 @@ bool set_default_brightness_aux(struct dc_link *link)
if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
if (!read_default_bl_aux(link, _backlight))
default_backlight = 15;
- // if < 5 nits or > 5000, it might be wrong readback
- if (default_backlight < 5000 || default_backlight > 500)
+ // if < 1 nits or > 5000, it might be wrong readback
+ if (default_backlight < 1000 || default_backlight > 500)
default_backlight = 15; //
return edp_set_backlight_level_nits(link, true,
--
2.34.1
[PATCH v2 05/24] drm/amd/display: Add a check for idle power optimization
From: Sung Joon Kim
[why]
Need a helper function to check idle power is allowed
so that dc doesn't access any registers that are power-gated.
[how]
Implement helper function to check idle power optimization.
Enable a hook to check if detection is allowed.
V2:
Add function hooks for set and get idle states.
Check if function hook was properly initialized.
Reviewed-by: Aric Cyr
Reviewed-by: Nicholas Choi
Acked-by: Roman Li
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 23 +++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 4 +++-
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 8 ++-
.../drm/amd/display/dc/hwss/hw_sequencer.h| 2 ++
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 ++
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 1 +
7 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f602ff0d4146..c4962cc4bb93 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4883,6 +4883,9 @@ void dc_allow_idle_optimizations(struct dc *dc, bool
allow)
if (dc->debug.disable_idle_power_optimizations)
return;
+ if (dc->caps.ips_support && dc->config.disable_ips)
+ return;
+
if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
return;
@@ -4894,6 +4897,26 @@ void dc_allow_idle_optimizations(struct dc *dc, bool
allow)
dc->idle_optimizations_allowed = allow;
}
+bool dc_dmub_is_ips_idle_state(struct dc *dc)
+{
+ uint32_t idle_state = 0;
+
+ if (dc->debug.disable_idle_power_optimizations)
+ return false;
+
+ if (!dc->caps.ips_support || dc->config.disable_ips)
+ return false;
+
+ if (dc->hwss.get_idle_state)
+ idle_state = dc->hwss.get_idle_state(dc);
+
+ if ((idle_state & DMUB_IPS1_ALLOW_MASK) ||
+ (idle_state & DMUB_IPS2_ALLOW_MASK))
+ return true;
+
+ return false;
+}
+
/* set min and max memory clock to lowest and highest DPM level, respectively
*/
void dc_unlock_memory_clock_frequency(struct dc *dc)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index cc1cae4d7329..e3b8c71e2c31 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -2362,6 +2362,7 @@ bool dc_is_plane_eligible_for_idle_optimizations(struct
dc *dc, struct dc_plane_
struct dc_cursor_attributes *cursor_attr);
void dc_allow_idle_optimizations(struct dc *dc, bool allow);
+bool dc_dmub_is_ips_idle_state(struct dc *dc);
/* set min and max memory clock to lowest and highest DPM level, respectively
*/
void dc_unlock_memory_clock_frequency(struct dc *dc);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 5daedd893923..5d62805f3bdf 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -586,7 +586,9 @@ void dcn31_reset_hw_ctx_wrap(
struct clock_source *old_clk =
pipe_ctx_old->clock_source;
/* Reset pipe which is seamless boot stream. */
- if (!pipe_ctx_old->plane_state) {
+ if (!pipe_ctx_old->plane_state &&
+ dc->res_pool->hubbub->funcs->program_det_size &&
+
dc->res_pool->hubbub->funcs->wait_for_det_apply) {
dc->res_pool->hubbub->funcs->program_det_size(
dc->res_pool->hubbub,
pipe_ctx_old->plane_res.hubp->inst, 0);
/* Wait det size changed. */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 12821cb9ab6c..36d2b91aa337 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -627,12 +627,8 @@ void dcn35_power_down_on_boot(struct dc *dc)
if (dc->clk_mgr->funcs->set_low_power_state)
dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);
- if (dc->clk_mgr->clks.pwr_state == DCN_PWR_STATE_LOW_POWER) {
- if (!dc->idle_optimizations_allowed) {
- dc_dmub_srv_notify_idle(dc, true);
- dc->idle_optimizations_allowed = true;
- }
- }
+ if (dc->clk_mgr->clks.pwr_state == DCN_PWR_STATE_LOW_POWER)
+ dc_allow_idle_optimizations(dc, true);
}
bool dcn35_apply_idle_power_optimizations(struct dc
[PATCH v2 03/24] drm/amd/display: Fix MST Multi-Stream Not Lighting Up on dcn35
From: Fangzhi Zuo
dcn35 misses .enable_symclk_se hook that makes MST DSC
not functional when having multiple FE clk to be enabled.
Reviewed-by: Rodrigo Siqueira
Acked-by: Roman Li
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 4d6493e0ccfc..608221b0dd5d 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2746,6 +2746,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
struct dce_hwseq *hws = dc->hwseq;
unsigned int k1_div = PIXEL_RATE_DIV_NA;
unsigned int k2_div = PIXEL_RATE_DIV_NA;
+ struct link_encoder *link_enc =
link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
+ struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
if (dc->hwseq->funcs.setup_hpo_hw_control)
@@ -2765,6 +2767,10 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
dto_params.timing = _ctx->stream->timing;
dto_params.ref_dtbclk_khz =
dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
dccg->funcs->set_dtbclk_dto(dccg, _params);
+ } else {
+ if (dccg->funcs->enable_symclk_se)
+ dccg->funcs->enable_symclk_se(dccg,
stream_enc->stream_enc_inst,
+ link_enc->transmitter -
TRANSMITTER_UNIPHY_A);
}
if (hws->funcs.calculate_dccg_k1_k2_values &&
dc->res_pool->dccg->funcs->set_pixel_rate_div) {
hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, _div,
_div);
--
2.34.1
[PATCH v2 02/24] drm/amd/display: Remove power sequencing check
From: Agustin Gutierrez
[Why]
Some ASICs keep backlight powered on after dpms off
command has been issued.
[How]
The check for no edp power sequencing was never going to pass.
The value is never changed from what it is set by design.
Cc: sta...@vger.kernel.org # 6.1+
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2765
Reviewed-by: Swapnil Patel
Acked-by: Roman Li
Signed-off-by: Agustin Gutierrez
---
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 4538451945b4..34a4a8c0e18c 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -1932,8 +1932,7 @@ static void disable_link_dp(struct dc_link *link,
dp_disable_link_phy(link, link_res, signal);
if (link->connector_signal == SIGNAL_TYPE_EDP) {
- if (!link->dc->config.edp_no_power_sequencing &&
- !link->skip_implict_edp_power_control)
+ if (!link->skip_implict_edp_power_control)
link->dc->hwss.edp_power_control(link, false);
}
--
2.34.1
[PATCH v2 01/24] drm/amd/display: reprogram det size while seamless boot
From: Hugo Hu
[Why]
During system boot in second screen only mode on a seamless boot system,
there is a chance that the pipe's det size might not be reset.
[How]
Reset the det size while resetting the pipe during seamless boot.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Roman Li
Signed-off-by: Hugo Hu
---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 23 +++
.../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 9
.../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 1 +
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
index f6b59c29cee2..5b5b5e0775fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
@@ -109,6 +109,28 @@ static void dcn31_program_det_size(struct hubbub *hubbub,
int hubp_inst, unsigne
+ hubbub2->det3_size + hubbub2->compbuf_size_segments
<= hubbub2->crb_size_segs);
}
+static void dcn31_wait_for_det_apply(struct hubbub *hubbub, int hubp_inst)
+{
+ struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+ switch (hubp_inst) {
+ case 0:
+ REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,
hubbub2->det0_size, 1000, 30);
+ break;
+ case 1:
+ REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,
hubbub2->det1_size, 1000, 30);
+ break;
+ case 2:
+ REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,
hubbub2->det2_size, 1000, 30);
+ break;
+ case 3:
+ REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,
hubbub2->det3_size, 1000, 30);
+ break;
+ default:
+ break;
+ }
+}
+
static void dcn31_program_compbuf_size(struct hubbub *hubbub, unsigned int
compbuf_size_kb, bool safe_to_increase)
{
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
@@ -1041,6 +1063,7 @@ static const struct hubbub_funcs hubbub31_funcs = {
.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
.verify_allow_pstate_change_high =
hubbub31_verify_allow_pstate_change_high,
.program_det_size = dcn31_program_det_size,
+ .wait_for_det_apply = dcn31_wait_for_det_apply,
.program_compbuf_size = dcn31_program_compbuf_size,
.init_crb = dcn31_init_crb,
.hubbub_read_state = hubbub2_read_state,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index c339f756b8e7..5daedd893923 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -585,6 +585,15 @@ void dcn31_reset_hw_ctx_wrap(
pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
struct clock_source *old_clk =
pipe_ctx_old->clock_source;
+ /* Reset pipe which is seamless boot stream. */
+ if (!pipe_ctx_old->plane_state) {
+ dc->res_pool->hubbub->funcs->program_det_size(
+ dc->res_pool->hubbub,
pipe_ctx_old->plane_res.hubp->inst, 0);
+ /* Wait det size changed. */
+ dc->res_pool->hubbub->funcs->wait_for_det_apply(
+ dc->res_pool->hubbub,
pipe_ctx_old->plane_res.hubp->inst);
+ }
+
dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old,
dc->current_state);
if (hws->funcs.enable_stream_gating)
hws->funcs.enable_stream_gating(dc,
pipe_ctx_old);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index cea05843990c..901891316dfb 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -188,6 +188,7 @@ struct hubbub_funcs {
* compressed or detiled buffers.
*/
void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned
det_buffer_size_in_kbyte);
+ void (*wait_for_det_apply)(struct hubbub *hubbub, int hubp_inst);
void (*program_compbuf_size)(struct hubbub *hubbub, unsigned
compbuf_size_kb, bool safe_to_increase);
void (*init_crb)(struct hubbub *hubbub);
void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow);
--
2.34.1
[PATCH v2 00/24] DC Patches October 18, 2023
From: Roman Li This DC patchset brings improvements in multiple areas. In summary, we highlight: * Fixes null-deref regression after "drm/amd/display: Update OPP counter from new interface" * Fixes display flashing when VSR and HDR enabled on dcn32 * Fixes dcn3x intermittent hangs due to FPO * Fixes MST Multi-Stream light up on dcn35 * Fixes green screen on DCN31x when DVI and HDMI monitors attached * Adds DML2 improvements * Adds idle power optimization improvements * Accommodates panels with lower nit backlight * Updates SDP VSC colorimetry from DP test automation request * Reverts "drm/amd/display: allow edp updates for virtual signal" Cc: Daniel Wheeler Agustin Gutierrez (1): drm/amd/display: Remove power sequencing check Alex Hung (2): drm/amd/display: Revert "drm/amd/display: allow edp updates for virtual signal" drm/amd/display: Set emulated sink type to HDMI accordingly. Alvin Lee (1): drm/amd/display: Update FAMS sequence for DCN30 & DCN32 Aric Cyr (1): drm/amd/display: 3.2.256 Aurabindo Pillai (1): drm/amd/display: add interface to query SubVP status Fangzhi Zuo (1): drm/amd/display: Fix MST Multi-Stream Not Lighting Up on dcn35 George Shen (1): drm/amd/display: Update SDP VSC colorimetry from DP test automation request Hugo Hu (1): drm/amd/display: reprogram det size while seamless boot Ilya Bakoulin (1): drm/amd/display: Fix shaper using bad LUT params Iswara Nagulendran (1): drm/amd/display: Read before writing Backlight Mode Set Register Michael Strauss (1): drm/amd/display: Disable SYMCLK32_SE RCO on DCN314 Nicholas Kazlauskas (2): drm/amd/display: Revert "Improve x86 and dmub ips handshake" drm/amd/display: Fix IPS handshake for idle optimizations Rodrigo Siqueira (3): drm/amd/display: Correct enum typo drm/amd/display: Add prefix to amdgpu crtc functions drm/amd/display: Add prefix for plane functions Samson Tam (2): drm/amd/display: fix num_ways overflow error drm/amd/display: add null check for invalid opps Sung Joon Kim (2): drm/amd/display: Add a check for idle power optimization drm/amd/display: Fix HDMI framepack 3D test issue Swapnil Patel (1): drm/amd/display: Reduce default backlight min from 5 nits to 1 nits Wenjing Liu (2): drm/amd/display: add pipe resource management callbacks to DML2 drm/amd/display: implement map dc pipe with callback in DML2 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 48 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4 + .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 542 +- .../amd/display/amdgpu_dm/amdgpu_dm_plane.h | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 26 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 4 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 26 +- .../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 23 + .../amd/display/dc/dcn314/dcn314_resource.c | 2 +- .../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 2 +- .../drm/amd/display/dc/dcn32/dcn32_resource.c | 9 +- .../amd/display/dc/dcn321/dcn321_resource.c | 8 +- .../drm/amd/display/dc/dcn35/dcn35_resource.c | 5 + .../display/dc/dml2/dml2_dc_resource_mgmt.c | 146 + .../display/dc/dml2/dml2_translation_helper.c | 2 + .../drm/amd/display/dc/dml2/dml2_wrapper.h| 16 + .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 6 + .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 21 +- .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 11 + .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 39 +- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 3 + .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 8 +- .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 1 + drivers/gpu/drm/amd/display/dc/irq_types.h| 6 +- .../display/dc/link/accessories/link_dp_cts.c | 6 + .../gpu/drm/amd/display/dc/link/link_dpms.c | 3 +- .../link/protocols/link_edp_panel_control.c | 11 +- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 1 + .../drm/amd/display/include/signal_types.h| 1 - 31 files changed, 646 insertions(+), 343 deletions(-) -- 2.34.1
RE: [PATCH] drm/amdgpu: refine ras error kernel log print
[AMD Official Use Only - General]
As discussed, please add socket id and die id in the output message.
Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin)
Sent: Thursday, October 19, 2023 20:51
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ;
Chai, Thomas ; Wang, Yang(Kevin)
Subject: [PATCH] drm/amdgpu: refine ras error kernel log print
refine ras error kernel log to avoid user-ridden ambiguity.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 5b831ba0ebb3..cebc19d810e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1034,10 +1034,11 @@ static void amdgpu_ras_error_print_error_data(struct
amdgpu_device *adev,
struct ras_err_info *err_info;
if (is_ue)
- dev_info(adev->dev, "%ld uncorrectable hardware errors detected
in %s block\n",
+ dev_info(adev->dev, "%ld uncorrectable hardware errors detected
in
+total in %s block\n",
ras_mgr->err_data.ue_count, blk_name);
else
- dev_info(adev->dev, "%ld correctable hardware errors detected
in %s block\n",
+ dev_info(adev->dev, "%ld correctable hardware errors detected
in total in %s block, "
+"no user action is needed.\n",
ras_mgr->err_data.ce_count, blk_name);
for_each_ras_error(err_node, err_data) { @@ -1045,14 +1046,15 @@ static
void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
mcm_info = _info->mcm_info;
if (is_ue && err_info->ue_count) {
dev_info(adev->dev, "socket: %d, die: %d "
-"%lld uncorrectable hardware errors detected
in %s block\n",
+"new %lld uncorrectable hardware errors
detected in %s block\n",
mcm_info->socket_id,
mcm_info->die_id,
err_info->ue_count,
blk_name);
} else if (!is_ue && err_info->ce_count) {
dev_info(adev->dev, "socket: %d, die: %d "
-"%lld correctable hardware errors detected in
%s block\n",
+"new %lld correctable hardware errors detected
in %s block, "
+"no user action is needed.\n",
mcm_info->socket_id,
mcm_info->die_id,
err_info->ce_count,
--
2.34.1
[PATCH] drm/amdgpu: refine ras error kernel log print
refine ras error kernel log to avoid user-ridden ambiguity.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 5b831ba0ebb3..cebc19d810e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1034,10 +1034,11 @@ static void amdgpu_ras_error_print_error_data(struct
amdgpu_device *adev,
struct ras_err_info *err_info;
if (is_ue)
- dev_info(adev->dev, "%ld uncorrectable hardware errors detected
in %s block\n",
+ dev_info(adev->dev, "%ld uncorrectable hardware errors detected
in total in %s block\n",
ras_mgr->err_data.ue_count, blk_name);
else
- dev_info(adev->dev, "%ld correctable hardware errors detected
in %s block\n",
+ dev_info(adev->dev, "%ld correctable hardware errors detected
in total in %s block, "
+"no user action is needed.\n",
ras_mgr->err_data.ce_count, blk_name);
for_each_ras_error(err_node, err_data) {
@@ -1045,14 +1046,15 @@ static void amdgpu_ras_error_print_error_data(struct
amdgpu_device *adev,
mcm_info = _info->mcm_info;
if (is_ue && err_info->ue_count) {
dev_info(adev->dev, "socket: %d, die: %d "
-"%lld uncorrectable hardware errors detected
in %s block\n",
+"new %lld uncorrectable hardware errors
detected in %s block\n",
mcm_info->socket_id,
mcm_info->die_id,
err_info->ue_count,
blk_name);
} else if (!is_ue && err_info->ce_count) {
dev_info(adev->dev, "socket: %d, die: %d "
-"%lld correctable hardware errors detected in
%s block\n",
+"new %lld correctable hardware errors detected
in %s block, "
+"no user action is needed.\n",
mcm_info->socket_id,
mcm_info->die_id,
err_info->ce_count,
--
2.34.1
Re: [PATCH] drm/amdgpu: ignore duplicate BOs again
Am 17.10.23 um 15:04 schrieb Alex Deucher:
On Tue, Oct 17, 2023 at 8:22 AM Christian König
wrote:
Looks like RADV is actually hitting this.
Signed-off-by: Christian König
Fixes: ca6c1e210aa7 ("drm/amdgpu: use the new drm_exec object for CS v3")
Acked-by: Alex Deucher
Pushed to drm-misc-fixes since the original patch causing the problems
isn't even merged into amd-staging-drm-next yet.
Regards,
Christian.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index efdb1c48f431..d93a8961274c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -65,7 +65,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
}
amdgpu_sync_create(>sync);
- drm_exec_init(>exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
+ drm_exec_init(>exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
+ DRM_EXEC_IGNORE_DUPLICATES);
return 0;
}
--
2.34.1
[PATCH] drm/amd check num of link levels when update pcie param
In SR-IOV environment, the value of pcie_table->num_of_link_levels will
be 0, and num_of_levels - 1 will cause array index out of bounds
Signed-off-by: Lin.Cao
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index bcb7ab9d2221..6906b0a7d1d1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2437,6 +2437,9 @@ int smu_v13_0_update_pcie_parameters(struct smu_context
*smu,
uint32_t smu_pcie_arg;
int ret, i;
+ if (!num_of_levels)
+ return 0;
+
if (!amdgpu_device_pcie_dynamic_switching_supported()) {
if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
--
2.25.1
[PATCH] drm/amdgpu: Add timeout for sync wait
Issue: Dead heappen during gpu recover
[56433.829492] amdgpu :04:00.0: amdgpu: GPU reset begin!
[56550.499625] INFO: task kworker/u80:0:10 blocked for more than 120 seconds.
[56550.520215] Tainted: G OE 6.2.0-34-generic
#34~22.04.1-Ubuntu
[56550.542883] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this
message.
[56550.566313] task:kworker/u80:0 state:D stack:0 pid:10ppid:2
flags:0x4000
[56550.591318] Workqueue: kfd_restore_wq restore_process_worker [amdgpu]
[56550.611391] Call Trace:
[56550.618698]
[56550.624968] __schedule+0x2b7/0x5f0
[56550.635416] schedule+0x68/0x110
[56550.645090] schedule_timeout+0x151/0x160
[56550.657096] ? amdgpu_vm_bo_update+0x46e/0x660 [amdgpu]
[56550.673245] dma_fence_default_wait+0x1a2/0x1e0
[56550.686818] ? __pfx_dma_fence_default_wait_cb+0x10/0x10
[56550.702728] dma_fence_wait_timeout+0x117/0x140
[56550.716301] amdgpu_sync_wait+0x62/0xa0 [amdgpu]
[56550.730654] amdgpu_amdkfd_gpuvm_restore_process_bos+0x59e/0x770 [amdgpu]
[56550.751668] ? newidle_balance+0x298/0x490
[56550.763936] restore_process_worker+0x42/0x270 [amdgpu]
[56550.780183] process_one_work+0x21f/0x440
[56550.792193] worker_thread+0x50/0x3f0
[56550.803165] ? __pfx_worker_thread+0x10/0x10
[56550.815934] kthread+0xee/0x120
[56550.825342] ? __pfx_kthread+0x10/0x10
[56550.836548] ret_from_fork+0x2c/0x50
[56550.847262]
[ 1935.215502] Call Trace:
[ 1935.222827]
[ 1935.229121] __schedule+0x23d/0x5a0
[ 1935.239583] schedule+0x4e/0xc0
[ 1935.248983] schedule_timeout+0x103/0x140
[ 1935.261002] __wait_for_common+0xae/0x150
[ 1935.273008] ? usleep_range_state+0x90/0x90
[ 1935.285546] wait_for_completion+0x24/0x30
[ 1935.297813] __flush_work.isra.0+0x175/0x280
[ 1935.310611] ? worker_detach_from_pool+0xc0/0xc0
[ 1935.324436] flush_delayed_work+0x31/0x50
[ 1935.336455] kfd_suspend_all_processes+0x96/0x150 [amdgpu]
[ 1935.353429] kgd2kfd_suspend+0xb8/0xe0 [amdgpu]
[ 1935.367469] kgd2kfd_pre_reset+0x81/0xf0 [amdgpu]
[ 1935.382036] amdgpu_amdkfd_pre_reset+0x1a/0x30 [amdgpu]
[ 1935.398156] amdgpu_device_gpu_recover.cold+0x210/0xcf2 [amdgpu]
[ 1935.416722] amdgpu_job_timedout+0x19f/0x1e0 [amdgpu]
[ 1935.432367] drm_sched_job_timedout+0x6f/0x120 [amd_sched]
[ 1935.448792] process_one_work+0x22b/0x3d0
[ 1935.460806] worker_thread+0x53/0x420
[ 1935.471777] ? process_one_work+0x3d0/0x3d0
[ 1935.484307] kthread+0x12a/0x150
[ 1935.493993] ? set_kthread_struct+0x50/0x50
[ 1935.506513] ret_from_fork+0x22/0x30
It is because the amdgpu_sync_wait is waiting for the bad job's fence, and
never return, so the recover couldn't continue.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index dcd8c066bc1f..c922867c5675 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -406,9 +406,19 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr)
int i, r;
hash_for_each_safe(sync->fences, i, tmp, e, node) {
- r = dma_fence_wait(e->fence, intr);
- if (r)
- return r;
+ struct drm_sched_fence *s_fence = to_drm_sched_fence(e->fence);
+
+ if (s_fence) {
+ r = dma_fence_wait_timeout(e->fence, intr,
s_fence->sched->timeout);
+ if (r == 0)
+ r = -ETIMEDOUT;
+ if (r < 0)
+ return r;
+ } else {
+ r = dma_fence_wait(e->fence, intr);
+ if (r)
+ return r;
+ }
amdgpu_sync_entry_free(e);
}
--
2.36.1
Re: [PATCH v4 13/17] platform/x86/amd/pmf: Add PMF-AMDGPU get interface
Am 18.10.23 um 19:05 schrieb Shyam Sundar S K: On 10/18/2023 9:37 PM, Christian König wrote: Am 18.10.23 um 17:47 schrieb Mario Limonciello: On 10/18/2023 08:40, Christian König wrote: Am 18.10.23 um 11:28 schrieb Shyam Sundar S K: On 10/18/2023 2:50 PM, Ilpo Järvinen wrote: On Wed, 18 Oct 2023, Shyam Sundar S K wrote: In order to provide GPU inputs to TA for the Smart PC solution to work, we need to have interface between the PMF driver and the AMDGPU driver. Add the initial code path for get interface from AMDGPU. Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello Signed-off-by: Shyam Sundar S K --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_pmf.c | 138 drivers/platform/x86/amd/pmf/Kconfig | 1 + drivers/platform/x86/amd/pmf/core.c | 1 + drivers/platform/x86/amd/pmf/pmf.h | 3 + drivers/platform/x86/amd/pmf/spc.c | 13 +++ drivers/platform/x86/amd/pmf/tee-if.c | 26 + include/linux/amd-pmf-io.h | 35 ++ 9 files changed, 220 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmf.c create mode 100644 include/linux/amd-pmf-io.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 384b798a9bad..7fafccefbd7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -86,6 +86,8 @@ amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o +amdgpu-$(CONFIG_AMD_PMF) += amdgpu_pmf.o + # add asic specific block amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o \ dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index a79d53bdbe13..26ffa1b4fe57 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -50,6 +50,7 @@ #include #include #include +#include #include #include diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmf.c new file mode 100644 index ..ac981848df50 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmf.c @@ -0,0 +1,138 @@ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. This is MIT, right? Add the required SPDX-License-Identifier line for it at the top of the file, thank you. all the files in drivers/gpu/drm/amd/amdgpu/* carry the same license text. So, have retained it to maintain uniformity. Please add the SPDX License Identifier for any file you add. OK. I thought to keep it same like the other files. I will change this to SPDX in the next revision. Apart from that the whole approach of attaching this directly to amdgpu looks extremely questionable to me. What's the long term outlook for things that are needed directly from amdgpu? Is there going to be more besides the backlight and the display count/type? Yeah, that goes into the same direction as my concern. PMF is an APU only feature and will need inputs from multiple subsystems (in this case its GPU) to send changing system information to PMF TA (Trusted Application, running on ASP/PSP) as input. Its not only about the display count/type and backlight, there are many others things in pipe like the GPU engine running time, utilization percentage etc, that guide the TA to make better decisions. This series is only targeted to build the initial plubming with the subsystems inside the kernel and later keep adding changes to get more information from other subsystems. Yeah, and that's what I strongly disagree on. Don't come up with such an approach without consulting with upstream maintainers first. What you propose here is a system wide framework for improving power management, that's fine.
[PATCH -next 1/2] drm/amd/display: clean up one inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/display_mode_util.c:150 dml_max() warn: inconsistent indenting Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6933 Signed-off-by: Yang Li --- drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c index 7dd1f8a12582..3a70838abfba 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c @@ -147,7 +147,7 @@ dml_float_t dml_max(dml_float_t x, dml_float_t y) return y; if (y != y) return x; -if (x > y) + if (x > y) return x; else return y; -- 2.20.1.7.g153144c
[PATCH] drm/amd/display: clean up some inconsistent indenting
No functional modification involved. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2902 dm_resume() warn: inconsistent indenting. Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6940 Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 801f87a12ccf..0e1f8c5d7f9b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2899,7 +2899,7 @@ static int dm_resume(void *handle) } /* power on hardware */ -dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); + dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); /* program HPD filter */ dc_resume(dm->dc); -- 2.20.1.7.g153144c
[PATCH -next 2/2] drm/amd/display: clean up one inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml2_policy.c:206 dml2_policy_build_synthetic_soc_states() warn: inconsistent indenting Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6933 Signed-off-by: Yang Li --- drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c index f8e9aa32ceab..0b3ab7aaea87 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c @@ -203,7 +203,7 @@ int dml2_policy_build_synthetic_soc_states(struct dml2_policy_build_synthetic_so s->entry.fabricclk_mhz = p->in_states->state_array[i].fabricclk_mhz; s->entry.dram_speed_mts = 0; - insert_entry_into_table_sorted(p->in_bbox, p->out_states, >entry); + insert_entry_into_table_sorted(p->in_bbox, p->out_states, >entry); } } // Add max FCLK -- 2.20.1.7.g153144c
RE: [PATCH Review 1/1] drm/amdgpu: Fix delete nodes that have been relesed
Fixes: d479ef0d5fbd ("drm/amdgpu: add ras_err_info to identify RAS error
source")
Please add above comment.
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Stanley.Yang
Sent: Thursday, October 19, 2023 3:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Yang, Stanley
Subject: [PATCH Review 1/1] drm/amdgpu: Fix delete nodes that have been relesed
Fix delete nodes that it has been freed.
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 8831859a2c49..867afbf84223 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -3499,10 +3499,8 @@ void amdgpu_ras_error_data_fini(struct ras_err_data
*err_data) {
struct ras_err_node *err_node, *tmp;
- list_for_each_entry_safe(err_node, tmp, _data->err_node_list, node)
{
+ list_for_each_entry_safe(err_node, tmp, _data->err_node_list,
+node)
amdgpu_ras_error_node_release(err_node);
- list_del(_node->node);
- }
}
static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct
ras_err_data *err_data,
--
2.25.1
RE: [PATCH] drm/amdgpu: fix typo for amdgpu ras error data print
[AMD Official Use Only - General]
Reviewed-by: Candice Li
Thanks,
Candice
-Original Message-
From: amd-gfx On Behalf Of Yang Wang
Sent: Thursday, October 19, 2023 3:15 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) ; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: fix typo for amdgpu ras error data print
typo fix.
Fixes: d479ef0d5fbd ("drm/amdgpu: add ras_err_info to identify RAS error
source")
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index c7f8dcb3b4d2..5b831ba0ebb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1038,7 +1038,7 @@ static void amdgpu_ras_error_print_error_data(struct
amdgpu_device *adev,
ras_mgr->err_data.ue_count, blk_name);
else
dev_info(adev->dev, "%ld correctable hardware errors detected
in %s block\n",
-ras_mgr->err_data.ue_count, blk_name);
+ras_mgr->err_data.ce_count, blk_name);
for_each_ras_error(err_node, err_data) {
err_info = _node->err_info;
@@ -1055,7 +1055,7 @@ static void amdgpu_ras_error_print_error_data(struct
amdgpu_device *adev,
"%lld correctable hardware errors detected in
%s block\n",
mcm_info->socket_id,
mcm_info->die_id,
-err_info->ue_count,
+err_info->ce_count,
blk_name);
}
}
--
2.34.1
[PATCH] drm/amdgpu: fix typo for amdgpu ras error data print
typo fix.
Fixes: d479ef0d5fbd ("drm/amdgpu: add ras_err_info to identify RAS error
source")
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index c7f8dcb3b4d2..5b831ba0ebb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1038,7 +1038,7 @@ static void amdgpu_ras_error_print_error_data(struct
amdgpu_device *adev,
ras_mgr->err_data.ue_count, blk_name);
else
dev_info(adev->dev, "%ld correctable hardware errors detected
in %s block\n",
-ras_mgr->err_data.ue_count, blk_name);
+ras_mgr->err_data.ce_count, blk_name);
for_each_ras_error(err_node, err_data) {
err_info = _node->err_info;
@@ -1055,7 +1055,7 @@ static void amdgpu_ras_error_print_error_data(struct
amdgpu_device *adev,
"%lld correctable hardware errors detected in
%s block\n",
mcm_info->socket_id,
mcm_info->die_id,
-err_info->ue_count,
+err_info->ce_count,
blk_name);
}
}
--
2.34.1
[PATCH Review 1/1] drm/amdgpu: Fix delete nodes that have been relesed
Fix delete nodes that it has been freed.
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 8831859a2c49..867afbf84223 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -3499,10 +3499,8 @@ void amdgpu_ras_error_data_fini(struct ras_err_data
*err_data)
{
struct ras_err_node *err_node, *tmp;
- list_for_each_entry_safe(err_node, tmp, _data->err_node_list, node)
{
+ list_for_each_entry_safe(err_node, tmp, _data->err_node_list, node)
amdgpu_ras_error_node_release(err_node);
- list_del(_node->node);
- }
}
static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct
ras_err_data *err_data,
--
2.25.1
Re: [PATCH v12 0/9] Enable Wifi RFI interference mitigation feature support
ping... Any other comments? Regards, Ma Jun On 10/17/2023 10:53 AM, Ma Jun wrote: > Due to electrical and mechanical constraints in certain platform designs there > may be likely interference of relatively high-powered harmonics of the (G-)DDR > memory clocks with local radio module frequency bands used by Wifi 6/6e/7. To > mitigate possible RFI interference we introuduced WBRF(Wifi Band RFI > mitigation Feature). > Producers can advertise the frequencies in use and consumers can use this > information > to avoid using these frequencies for sensitive features. > > The whole patch set is based on Linux 6.5.0. With some brief introductions > as below: > Patch1: Document about WBRF > Patch2: Core functionality setup for WBRF feature support > Patch3 - 4: Bring WBRF support to wifi subsystem. > Patch5 - 9: Bring WBRF support to AMD graphics driver. > > Evan Quan (7): > cfg80211: expose nl80211_chan_width_to_mhz for wide sharing > wifi: mac80211: Add support for WBRF features > drm/amd/pm: update driver_if and ppsmc headers for coming wbrf feature > drm/amd/pm: setup the framework to support Wifi RFI mitigation feature > drm/amd/pm: add flood detection for wbrf events > drm/amd/pm: enable Wifi RFI mitigation feature support for SMU13.0.0 > drm/amd/pm: enable Wifi RFI mitigation feature support for SMU13.0.7 > > Ma Jun (2): > Documentation/driver-api: Add document about WBRF mechanism > platform/x86/amd: Add support for AMD ACPI based Wifi band RFI > mitigation feature > > Documentation/driver-api/wbrf.rst | 71 +++ > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 17 + > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 214 + > drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 33 ++ > .../inc/pmfw_if/smu13_driver_if_v13_0_0.h | 14 +- > .../inc/pmfw_if/smu13_driver_if_v13_0_7.h | 14 +- > .../pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h | 3 +- > .../pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h | 3 +- > drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 +- > drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 3 + > .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 9 + > .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 60 +++ > .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 59 +++ > drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 3 + > drivers/platform/x86/amd/Kconfig | 15 + > drivers/platform/x86/amd/Makefile | 1 + > drivers/platform/x86/amd/wbrf.c | 422 ++ > include/linux/acpi_amd_wbrf.h | 101 + > include/linux/ieee80211.h | 1 + > include/net/cfg80211.h| 8 + > net/mac80211/Makefile | 2 + > net/mac80211/chan.c | 9 + > net/mac80211/ieee80211_i.h| 9 + > net/mac80211/main.c | 2 + > net/mac80211/wbrf.c | 105 + > net/wireless/chan.c | 3 +- > 27 files changed, 1180 insertions(+), 6 deletions(-) > create mode 100644 Documentation/driver-api/wbrf.rst > create mode 100644 drivers/platform/x86/amd/wbrf.c > create mode 100644 include/linux/acpi_amd_wbrf.h > create mode 100644 net/mac80211/wbrf.c >
Re: [PATCH] drm/amd/pm: drop unneeded dpm features disablement for SMU 14.0.0
[AMD Official Use Only - General]
This patch is:
Reviewed-by: Yifan Zhang
发件人: amd-gfx 代表 jiadong@amd.com
发送时间: Thursday, October 19, 2023 11:38:45 AM
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhu, Jiadong
主题: [PATCH] drm/amd/pm: drop unneeded dpm features disablement for SMU 14.0.0
From: Jiadong Zhu
PMFW will handle the features disablement properly for gpu reset case,
driver involvement may cause some unexpected issues.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7c3356d6da5e..ace71abbbcf6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1677,13 +1677,14 @@ static int smu_disable_dpms(struct smu_context *smu)
}
/*
-* For SMU 13.0.4/11, PMFW will handle the features disablement properly
+* For SMU 13.0.4/11 and 14.0.0, PMFW will handle the features
disablement properly
* for gpu reset and S0i3 cases. Driver involvement is unnecessary.
*/
if (amdgpu_in_reset(adev) || adev->in_s0ix) {
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
case IP_VERSION(13, 0, 4):
case IP_VERSION(13, 0, 11):
+ case IP_VERSION(14, 0, 0):
return 0;
default:
break;
--
2.25.1
Re: [PATCH] drm/amdgpu: add tmz support for GC IP v11.5.0
[AMD Official Use Only - General]
Reviewed-by: Yifan Zhang
发件人: amd-gfx 代表 jiadong@amd.com
发送时间: Thursday, October 19, 2023 11:40:25 AM
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhu, Jiadong
主题: [PATCH] drm/amdgpu: add tmz support for GC IP v11.5.0
From: Jiadong Zhu
Add tmz support for GC 11.5.0.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index a02992bff6af..2dce338b0f1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -786,6 +786,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
/* YELLOW_CARP*/
case IP_VERSION(10, 3, 3):
case IP_VERSION(11, 0, 4):
+ case IP_VERSION(11, 5, 0):
/* Don't enable it by default yet.
*/
if (amdgpu_tmz < 1) {
--
2.25.1
