[linux-next:master] BUILD REGRESSION ad5c60d66016e544c51ed98635a74073f761f45d
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: ad5c60d66016e544c51ed98635a74073f761f45d Add linux-next specific files for 20240119 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202401192143.jldjbiy3-...@intel.com https://lore.kernel.org/oe-kbuild-all/202401192357.wu4nprdn-...@intel.com https://lore.kernel.org/oe-kbuild-all/202401200016.e774fjbx-...@intel.com https://lore.kernel.org/oe-kbuild-all/202401200106.pmtn6g56-...@intel.com Error/Warning: (recently discovered and may have been fixed) checksum_kunit.c:(.text+0x5c): relocation truncated to fit: R_OR1K_INSN_REL_26 against undefined symbol `csum_ipv6_magic' checksum_kunit.c:(.text+0x64): relocation truncated to fit: R_NIOS2_CALL26 against `csum_ipv6_magic' checksum_kunit.c:(.text+0x64): undefined reference to `csum_ipv6_magic' ld.lld: error: undefined symbol: csum_ipv6_magic lib/checksum_kunit.c:616:(.text+0x44): undefined reference to `csum_ipv6_magic' Unverified Error/Warning (likely false positive, please contact us if interested): fs/bcachefs/buckets.c:730 bch2_trans_account_disk_usage_change() error: we previously assumed 'trans->disk_res' could be null (see line 700) Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-dst_addr-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-filled_descs_num-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-size-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-src_addr-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-sw_desc-not-described-in-xdma_fill_descs | `-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst |-- arc-allmodconfig | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-dst_addr-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-filled_descs_num-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-size-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-src_addr-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-sw_desc-not-described-in-xdma_fill_descs | `-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst |-- arc-allyesconfig | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-dst_addr-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-filled_descs_num-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-size-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-src_addr-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-sw_desc-not-described-in-xdma_fill_descs | `-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst |-- arm-allmodconfig | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-dst_addr-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-filled_descs_num-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-size-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-src_addr-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-sw_desc-not-described-in-xdma_fill_descs | `-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst |-- arm-allyesconfig | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-dst_addr-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-filled_descs_num-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:warning:Function-parameter-or-struct-member-size-not-described-in-xdma_fill_descs | |-- drivers-dma-xilinx-xdma.c:war
[PATCH] drm/amdkfd: Add cache line sizes to KFD topology
The KFD topology includes cache line size, but we have not been
filling that information out unless we are parsing a CRAT table.
Fill in this information for the devices where we have cache
information structs, and pipe this information to the topology
sysfs files.
Signed-off-by: Joseph Greathouse
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 93 ++-
drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +
3 files changed, 94 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index cd8e459201f1..002b08fa632f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -55,6 +55,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = {
/* TCP L1 Cache per CU */
.cache_size = 16,
.cache_level = 1,
+ .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -64,6 +65,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = {
/* Scalar L1 Instruction Cache (in SQC module) per bank */
.cache_size = 16,
.cache_level = 1,
+ .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_INST_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -73,6 +75,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = {
/* Scalar L1 Data Cache (in SQC module) per bank */
.cache_size = 8,
.cache_level = 1,
+ .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -88,6 +91,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
/* TCP L1 Cache per CU */
.cache_size = 16,
.cache_level = 1,
+ .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -95,8 +99,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
},
{
/* Scalar L1 Instruction Cache (in SQC module) per bank */
- .cache_size = 8,
+ .cache_size = 32,
.cache_level = 1,
+ .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_INST_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -104,8 +109,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
},
{
/* Scalar L1 Data Cache (in SQC module) per bank. */
- .cache_size = 4,
+ .cache_size = 16,
.cache_level = 1,
+ .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -135,6 +141,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
/* TCP L1 Cache per CU */
.cache_size = 16,
.cache_level = 1,
+ .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -144,6 +151,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
/* Scalar L1 Instruction Cache per SQC */
.cache_size = 32,
.cache_level = 1,
+ .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_INST_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -153,6 +161,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
/* Scalar L1 Data Cache per SQC */
.cache_size = 16,
.cache_level = 1,
+ .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -162,6 +171,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
/* L2 Data Cache per GPU (Total Tex Cache) */
.cache_size = 4096,
.cache_level = 2,
+ .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
Re: [PATCH 1/2] drm/atomic: Allow drivers to write their own plane check for async flips
Hi André, kernel test robot noticed the following build warnings: [auto build test WARNING on drm-misc/drm-misc-next] [also build test WARNING on drm/drm-next drm-exynos/exynos-drm-next drm-intel/for-linux-next drm-tip/drm-tip linus/master next-20240119] [cannot apply to drm-intel/for-linux-next-fixes v6.7] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Andr-Almeida/drm-atomic-Allow-drivers-to-write-their-own-plane-check-for-async-flips/20240116-125406 base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next patch link: https://lore.kernel.org/r/20240116045159.1015510-2-andrealmeid%40igalia.com patch subject: [PATCH 1/2] drm/atomic: Allow drivers to write their own plane check for async flips config: hexagon-randconfig-002-20240119 (https://download.01.org/0day-ci/archive/20240120/202401200526.xggix2de-...@intel.com/config) compiler: clang version 18.0.0git (https://github.com/llvm/llvm-project d92ce344bf641e6bb025b41b3f1a77dd25e2b3e9) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240120/202401200526.xggix2de-...@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202401200526.xggix2de-...@intel.com/ All warnings (new ones prefixed by >>): In file included from drivers/gpu/drm/drm_atomic_uapi.c:31: In file included from include/drm/drm_atomic.h:31: In file included from include/drm/drm_crtc.h:32: In file included from include/drm/drm_modes.h:33: In file included from include/drm/drm_connector.h:32: In file included from include/drm/drm_util.h:35: In file included from include/linux/interrupt.h:11: In file included from include/linux/hardirq.h:11: In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1: In file included from include/asm-generic/hardirq.h:17: In file included from include/linux/irq.h:20: In file included from include/linux/io.h:13: In file included from arch/hexagon/include/asm/io.h:337: include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 547 | val = __raw_readb(PCI_IOBASE + addr); | ~~ ^ include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 560 | val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr)); | ~~ ^ include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu' 37 | #define __le16_to_cpu(x) ((__force __u16)(__le16)(x)) | ^ In file included from drivers/gpu/drm/drm_atomic_uapi.c:31: In file included from include/drm/drm_atomic.h:31: In file included from include/drm/drm_crtc.h:32: In file included from include/drm/drm_modes.h:33: In file included from include/drm/drm_connector.h:32: In file included from include/drm/drm_util.h:35: In file included from include/linux/interrupt.h:11: In file included from include/linux/hardirq.h:11: In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1: In file included from include/asm-generic/hardirq.h:17: In file included from include/linux/irq.h:20: In file included from include/linux/io.h:13: In file included from arch/hexagon/include/asm/io.h:337: include/asm-generic/io.h:573:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 573 | val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr)); | ~~ ^ include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu' 35 | #define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) | ^ In file included from drivers/gpu/drm/drm_atomic_uapi.c:31: In file included from include/drm/drm_atomic.h:31: In file included from include/drm/drm_crtc.h:32: In file included from include/drm/drm_modes.h:33: In file included from include/drm/drm_connector.h:32: In file included from include/drm/drm_util.h:35: In file included from include/linux/interrupt.h:11: In file included from include/linux/hardirq.h:11: In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1: In file included from include/asm-gener
Re: [PATCH v2] drm/amdgpu: change vm->task_info handling
On 2024-01-18 14:21, Shashank Sharma wrote:
This patch changes the handling and lifecycle of vm->task_info object.
The major changes are:
- vm->task_info is a dynamically allocated ptr now, and its uasge is
reference counted.
- introducing two new helper funcs for task_info lifecycle management
- amdgpu_vm_get_task_info: reference counts up task_info before
returning this info
- amdgpu_vm_put_task_info: reference counts down task_info
- last put to task_info() frees task_info from the vm.
This patch also does logistical changes required for existing usage
of vm->task_info.
V2: Do not block all the prints when task_info not found (Felix)
Cc: Christian Koenig
Cc: Alex Deucher
Cc: Felix Kuehling
Signed-off-by: Shashank Sharma
Nit-picks inline.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 18 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 12 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 142 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 26 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 30 +++--
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 31 +++--
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 22 +--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 26 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c| 26 ++--
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 20 +--
13 files changed, 287 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 0e61ebdb3f3e..99c736b6e32c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1775,9 +1775,12 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file
*m, void *unused)
list_for_each_entry(file, &dev->filelist, lhead) {
struct amdgpu_fpriv *fpriv = file->driver_priv;
struct amdgpu_vm *vm = &fpriv->vm;
+ struct amdgpu_task_info *ti;
+
+ ti = amdgpu_vm_get_task_info_vm(vm);
Can ti be NULL here? I think it can, so you'd need a NULL check to avoid
a possible kernel oops.
+ seq_printf(m, "pid:%d\tProcess:%s --\n", ti->pid,
ti->process_name);
+ amdgpu_vm_put_task_info_vm(ti, vm);
- seq_printf(m, "pid:%d\tProcess:%s --\n",
- vm->task_info.pid, vm->task_info.process_name);
r = amdgpu_bo_reserve(vm->root.bo, true);
if (r)
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 1f357198533f..af23746821b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -35,7 +35,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct
drm_sched_job *s_job)
{
struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
struct amdgpu_job *job = to_amdgpu_job(s_job);
- struct amdgpu_task_info ti;
+ struct amdgpu_task_info *ti;
struct amdgpu_device *adev = ring->adev;
int idx;
int r;
@@ -48,7 +48,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct
drm_sched_job *s_job)
return DRM_GPU_SCHED_STAT_ENODEV;
}
- memset(&ti, 0, sizeof(struct amdgpu_task_info));
+
adev->job_hang = true;
if (amdgpu_gpu_recovery &&
@@ -58,12 +58,16 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct
drm_sched_job *s_job)
goto exit;
}
- amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
- job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
- ring->fence_drv.sync_seq);
- DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
- ti.process_name, ti.tgid, ti.task_name, ti.pid);
+ job->base.sched->name,
atomic_read(&ring->fence_drv.last_seq),
+ ring->fence_drv.sync_seq);
Unnecessary (and incorrect) indentation change.
+
+ ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid);
+ if (ti) {
+ DRM_ERROR("Process information: process %s pid %d thread %s pid
%d\n",
+ ti->process_name, ti->tgid, ti->task_name, ti->pid);
+ amdgpu_vm_put_task_info_pasid(ring->adev, ti, job->pasid);
+ }
dma_fence_set_error(&s_job->s_fence->finished, -ETIME);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 4baa300121d8..bfd7a6067edd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -230,8 +230,16 @@ vo
Re: [PATCH] Revert "drm/amd/pm: fix the high voltage and temperature issue"
[AMD Official Use Only - General]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Mario
Limonciello
Sent: Friday, January 19, 2024 4:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Limonciello, Mario
; sta...@vger.kernel.org
Subject: [PATCH] Revert "drm/amd/pm: fix the high voltage and temperature issue"
This reverts commit 5f38ac54e60562323ea4abb1bfb37d043ee23357.
This causes issues with rebooting and the 7800XT.
Cc: Kenneth Feng
Cc: sta...@vger.kernel.org
Fixes: 5f38ac54e605 ("drm/amd/pm: fix the high voltage and temperature issue")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3062
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 24 --
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 33 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 -
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 8 +
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 8 +
5 files changed, 11 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b4c19e3d0bf1..56d9dfa61290 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4131,23 +4131,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
}
}
} else {
- switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
- case IP_VERSION(13, 0, 0):
- case IP_VERSION(13, 0, 7):
- case IP_VERSION(13, 0, 10):
- r = psp_gpu_reset(adev);
- break;
- default:
- tmp = amdgpu_reset_method;
- /* It should do a default reset when loading or
reloading the driver,
-* regardless of the module parameter
reset_method.
-*/
- amdgpu_reset_method = AMD_RESET_METHOD_NONE;
- r = amdgpu_asic_reset(adev);
- amdgpu_reset_method = tmp;
- break;
- }
-
+ tmp = amdgpu_reset_method;
+ /* It should do a default reset when loading or
reloading the driver,
+* regardless of the module parameter reset_method.
+*/
+ amdgpu_reset_method = AMD_RESET_METHOD_NONE;
+ r = amdgpu_asic_reset(adev);
+ amdgpu_reset_method = tmp;
if (r) {
dev_err(adev->dev, "asic reset on init
failed\n");
goto failed;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index c16703868e5c..961cd2aaf137 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -733,7 +733,7 @@ static int smu_early_init(void *handle)
smu->adev = adev;
smu->pm_enabled = !!amdgpu_dpm;
smu->is_apu = false;
- smu->smu_baco.state = SMU_BACO_STATE_NONE;
+ smu->smu_baco.state = SMU_BACO_STATE_EXIT;
smu->smu_baco.platform_support = false;
smu->user_dpm_profile.fan_mode = -1;
@@ -1961,31 +1961,10 @@ static int smu_smc_hw_cleanup(struct smu_context *smu)
return 0;
}
-static int smu_reset_mp1_state(struct smu_context *smu)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret = 0;
-
- if ((!adev->in_runpm) && (!adev->in_suspend) &&
- (!amdgpu_in_reset(adev)))
- switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
- case IP_VERSION(13, 0, 0):
- case IP_VERSION(13, 0, 7):
- case IP_VERSION(13, 0, 10):
- ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
- break;
- default:
- break;
- }
-
- return ret;
-}
-
static int smu_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = adev->powerplay.pp_handle;
- int ret;
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
@@ -2003,15 +1982,7 @@ static int smu_hw_fini(void *handle)
adev->pm.dpm_enabled = false;
- ret = smu_smc_hw_cleanup(smu);
- if (ret)
- return ret;
-
- ret = smu_reset_mp1_state(smu);
- if (ret)
- return ret;
-
- return 0;
+ return smu_smc_hw_cleanup(smu);
}
static void smu_late_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_sm
[PATCH] Revert "drm/amd/pm: fix the high voltage and temperature issue"
This reverts commit 5f38ac54e60562323ea4abb1bfb37d043ee23357.
This causes issues with rebooting and the 7800XT.
Cc: Kenneth Feng
Cc: sta...@vger.kernel.org
Fixes: 5f38ac54e605 ("drm/amd/pm: fix the high voltage and temperature issue")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3062
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 24 --
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 33 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 -
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 8 +
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 8 +
5 files changed, 11 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b4c19e3d0bf1..56d9dfa61290 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4131,23 +4131,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
}
}
} else {
- switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
- case IP_VERSION(13, 0, 0):
- case IP_VERSION(13, 0, 7):
- case IP_VERSION(13, 0, 10):
- r = psp_gpu_reset(adev);
- break;
- default:
- tmp = amdgpu_reset_method;
- /* It should do a default reset when loading or
reloading the driver,
-* regardless of the module parameter
reset_method.
-*/
- amdgpu_reset_method = AMD_RESET_METHOD_NONE;
- r = amdgpu_asic_reset(adev);
- amdgpu_reset_method = tmp;
- break;
- }
-
+ tmp = amdgpu_reset_method;
+ /* It should do a default reset when loading or
reloading the driver,
+* regardless of the module parameter reset_method.
+*/
+ amdgpu_reset_method = AMD_RESET_METHOD_NONE;
+ r = amdgpu_asic_reset(adev);
+ amdgpu_reset_method = tmp;
if (r) {
dev_err(adev->dev, "asic reset on init
failed\n");
goto failed;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index c16703868e5c..961cd2aaf137 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -733,7 +733,7 @@ static int smu_early_init(void *handle)
smu->adev = adev;
smu->pm_enabled = !!amdgpu_dpm;
smu->is_apu = false;
- smu->smu_baco.state = SMU_BACO_STATE_NONE;
+ smu->smu_baco.state = SMU_BACO_STATE_EXIT;
smu->smu_baco.platform_support = false;
smu->user_dpm_profile.fan_mode = -1;
@@ -1961,31 +1961,10 @@ static int smu_smc_hw_cleanup(struct smu_context *smu)
return 0;
}
-static int smu_reset_mp1_state(struct smu_context *smu)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret = 0;
-
- if ((!adev->in_runpm) && (!adev->in_suspend) &&
- (!amdgpu_in_reset(adev)))
- switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
- case IP_VERSION(13, 0, 0):
- case IP_VERSION(13, 0, 7):
- case IP_VERSION(13, 0, 10):
- ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
- break;
- default:
- break;
- }
-
- return ret;
-}
-
static int smu_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = adev->powerplay.pp_handle;
- int ret;
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
@@ -2003,15 +1982,7 @@ static int smu_hw_fini(void *handle)
adev->pm.dpm_enabled = false;
- ret = smu_smc_hw_cleanup(smu);
- if (ret)
- return ret;
-
- ret = smu_reset_mp1_state(smu);
- if (ret)
- return ret;
-
- return 0;
+ return smu_smc_hw_cleanup(smu);
}
static void smu_late_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 2aa4fea87314..66e84defd0b6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -424,7 +424,6 @@ enum smu_reset_mode {
enum smu_baco_state {
SMU_BACO_STATE_ENTER = 0,
SMU_BACO_STATE_EXIT,
- SMU_BACO_STATE_NONE,
};
struct smu_b
Re: [PATCH 1/2] drm/amdgpu: Reset IH OVERFLOW_CLEAR bit after writing rptr
On 2024-01-18 07:07, Christian König wrote: Am 18.01.24 um 00:44 schrieb Friedrich Vock: On 18.01.24 00:00, Alex Deucher wrote: [SNIP] Right now, IH overflows, even if they occur repeatedly, only get registered once. If not registering IH overflows can trivially lead to system crashes, it's amdgpu's current handling that is broken. It's years that we last tested this but according to the HW documentation this should work fine. What could potentially happen is that the IH has silenced the source of the overflow. We never implemented resetting those, but in this case that here won't help either. If the IH silenced the page faults (which quite clearly cause the overflow here), then how are the page faults still logged in dmesg? There should be a hardware rate limit for the page faults, e.g. there can only be X faults reported in N clock cycles and then a delay is inserted. @Christian Koenig Is that tied to xnack (i.e., noretry)? The default is noretry=1 on gfx10.3 and newer. But it can be overridden. It was not set on some older kernels, maybe that is the problem? @Friedrich Vock does setting amdgpu.noretry=1 fix the issue? No, amdgpu.noretry=1 does not change anything. Well the good news first the hw engineer answered rather quickly. The bad news is that the hardware really doesn't work as documented in multiple ways. First of all the CLEAR bit is a level and not a trigger, so the intention to clear it is indeed correct. For now please modify this patch so that the CLEAR bit is set and cleared directly after setting it, this way we should be able to detect further overflows immediately. Then the APU the Steam Deck uses simply doesn't have the filter function for page faults in the hardware, the really bad news is it also doesn't have the extra IH rings where we could re-route the faults to prevent overflows. That full explains the behavior you have been seeing, but doesn't really provide a doable solution to mitigate this problem. I'm going to dig deeper into the hw documentation and specification to see if we can use a different feature to avoid the overflow. If we're not enabling retry faults, then each wave front should generate at most one fault. You should be able to avoid overflows by making the IH ring large enough to accommodate one fault per wave front. If the faults are coming from SDMA, that may be another problem. I'm not sure whether it can generate multiple no-retry faults from the same queue. Regards, Felix Thanks, Christian. Regards, Friedrich Alex The possibility of a repeated IH overflow in between reading the wptr and updating the rptr is a good point, but how can we detect that at all? It seems to me like we can't set the OVERFLOW_CLEAR bit at all then, because we're guaranteed to miss any overflows that happen while the bit is set. When an IH overflow is signaled we clear that flag by writing 1 into the OVERFLOW_CLEAR bit and skip one entry in the IH ring buffer. What can of course happen is that the IH ring buffer overflows more than this single entry and we process IVs which are potentially corrupted, but we won't miss any additional overflows since we only start processing after resetting the flag. An IH overflow is also something you should *never* see in a production system. This is purely for driver bringup and as fallback when there is a severe incorrect programming of the HW. The only exception of that is page fault handling on MI products because of a hardware bug, to mitigate this we are processing page faults on a separate IH ring on those parts. On all other hw generations the IH should have some rate limit for the number of faults generated per second, so that the CPU is always able to catch up. I'm wondering if there is another bug in here somewhere. Your explanation of how it's supposed to work makes a lot of sense, but from what I can tell it doesn't work that way when I test it. From the printk_ratelimit stats it would seem like >2000 faults arrive in less than a second, so perhaps your theory about fault interrupt ratelimiting not working is correct (but it's hard for me to verify what is going on without the documentation). I'm going to ping the relevant engineer and putting someone on the task to take a look. Thanks, Christian. Regards, Friedrich Regards, Christian. Regards, Friedrich When you clear the overflow again when updating the RPTR you could loose another overflow which might have happened in between and so potentially process corrupted IVs. That can trivially crash the system. Regards, Christian. } static int cik_ih_early_init(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index b8c47e0cf37a..076559668573 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -215,7 +215,7 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev, tmp = RREG32(mmIH_RB_CNTL);
Re: [PATCH v2 2/2] drm/amdgpu: Implement check_async_props for planes
On Fri, Jan 19, 2024 at 03:12:35PM -0300, André Almeida wrote:
> AMD GPUs can do async flips with changes on more properties than just
> the FB ID, so implement a custom check_async_props for AMD planes.
>
> Allow amdgpu to do async flips with IN_FENCE_ID and FB_DAMAGE_CLIPS
> properties. For userspace to check if a driver support this two
> properties, the strategy for now is to use TEST_ONLY commits.
>
> Signed-off-by: André Almeida
> ---
> v2: Drop overlay plane option for now
>
> .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 29 +++
> 1 file changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> index 116121e647ca..7afe8c1b62d4 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> @@ -25,6 +25,7 @@
> */
>
> #include
> +#include
> #include
> #include
> #include
> @@ -1430,6 +1431,33 @@ static void
> amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane,
> drm_atomic_helper_plane_destroy_state(plane, state);
> }
>
> +static int amdgpu_dm_plane_check_async_props(struct drm_property *prop,
> + struct drm_plane *plane,
> + struct drm_plane_state *plane_state,
> + struct drm_mode_object *obj,
> + u64 prop_value, u64 old_val)
> +{
> + struct drm_mode_config *config = &plane->dev->mode_config;
> + int ret;
> +
> + if (prop != config->prop_fb_id &&
> + prop != config->prop_in_fence_fd &&
IN_FENCE should just be allowed always.
> + prop != config->prop_fb_damage_clips) {
This seems a bit dubious to me. How is amdgpu using the damage
information during async flips?
> + ret = drm_atomic_plane_get_property(plane, plane_state,
> + prop, &old_val);
> + return drm_atomic_check_prop_changes(ret, old_val, prop_value,
> prop);
> + }
> +
> + if (plane_state->plane->type != DRM_PLANE_TYPE_PRIMARY) {
> + drm_dbg_atomic(prop->dev,
> +"[OBJECT:%d] Only primary planes can be changed
> during async flip\n",
> +obj->id);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static const struct drm_plane_funcs dm_plane_funcs = {
> .update_plane = drm_atomic_helper_update_plane,
> .disable_plane = drm_atomic_helper_disable_plane,
> @@ -1438,6 +1466,7 @@ static const struct drm_plane_funcs dm_plane_funcs = {
> .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state,
> .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state,
> .format_mod_supported = amdgpu_dm_plane_format_mod_supported,
> + .check_async_props = amdgpu_dm_plane_check_async_props,
> };
>
> int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
> --
> 2.43.0
--
Ville Syrjälä
Intel
[PATCH v2 2/2] drm/amdgpu: Implement check_async_props for planes
AMD GPUs can do async flips with changes on more properties than just
the FB ID, so implement a custom check_async_props for AMD planes.
Allow amdgpu to do async flips with IN_FENCE_ID and FB_DAMAGE_CLIPS
properties. For userspace to check if a driver support this two
properties, the strategy for now is to use TEST_ONLY commits.
Signed-off-by: André Almeida
---
v2: Drop overlay plane option for now
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 116121e647ca..7afe8c1b62d4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -25,6 +25,7 @@
*/
#include
+#include
#include
#include
#include
@@ -1430,6 +1431,33 @@ static void
amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane,
drm_atomic_helper_plane_destroy_state(plane, state);
}
+static int amdgpu_dm_plane_check_async_props(struct drm_property *prop,
+ struct drm_plane *plane,
+ struct drm_plane_state *plane_state,
+ struct drm_mode_object *obj,
+ u64 prop_value, u64 old_val)
+{
+ struct drm_mode_config *config = &plane->dev->mode_config;
+ int ret;
+
+ if (prop != config->prop_fb_id &&
+ prop != config->prop_in_fence_fd &&
+ prop != config->prop_fb_damage_clips) {
+ ret = drm_atomic_plane_get_property(plane, plane_state,
+ prop, &old_val);
+ return drm_atomic_check_prop_changes(ret, old_val, prop_value,
prop);
+ }
+
+ if (plane_state->plane->type != DRM_PLANE_TYPE_PRIMARY) {
+ drm_dbg_atomic(prop->dev,
+ "[OBJECT:%d] Only primary planes can be changed
during async flip\n",
+ obj->id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const struct drm_plane_funcs dm_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -1438,6 +1466,7 @@ static const struct drm_plane_funcs dm_plane_funcs = {
.atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state,
.atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state,
.format_mod_supported = amdgpu_dm_plane_format_mod_supported,
+ .check_async_props = amdgpu_dm_plane_check_async_props,
};
int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
--
2.43.0
[PATCH v2 1/2] drm/atomic: Allow drivers to write their own plane check for async flips
Some hardware are more flexible on what they can flip asynchronously, so
rework the plane check so drivers can implement their own check, lifting
up some of the restrictions.
Signed-off-by: André Almeida
---
drivers/gpu/drm/drm_atomic_uapi.c | 62 ++-
include/drm/drm_atomic_uapi.h | 12 ++
include/drm/drm_plane.h | 5 +++
3 files changed, 62 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index aee4a65d4959..6d5b9fec90c7 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -620,7 +620,7 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
return 0;
}
-static int
+int
drm_atomic_plane_get_property(struct drm_plane *plane,
const struct drm_plane_state *state,
struct drm_property *property, uint64_t *val)
@@ -683,6 +683,7 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
return 0;
}
+EXPORT_SYMBOL(drm_atomic_plane_get_property);
static int drm_atomic_set_writeback_fb_for_connector(
struct drm_connector_state *conn_state,
@@ -1026,18 +1027,54 @@ int drm_atomic_connector_commit_dpms(struct
drm_atomic_state *state,
return ret;
}
-static int drm_atomic_check_prop_changes(int ret, uint64_t old_val, uint64_t
prop_value,
+int drm_atomic_check_prop_changes(int ret, uint64_t old_val, uint64_t
prop_value,
struct drm_property *prop)
{
if (ret != 0 || old_val != prop_value) {
drm_dbg_atomic(prop->dev,
- "[PROP:%d:%s] No prop can be changed during
async flip\n",
+ "[PROP:%d:%s] This prop cannot be changed during
async flip\n",
prop->base.id, prop->name);
return -EINVAL;
}
return 0;
}
+EXPORT_SYMBOL(drm_atomic_check_prop_changes);
+
+/* plane changes may have exceptions, so we have a special function for them */
+static int drm_atomic_check_plane_changes(struct drm_property *prop,
+ struct drm_plane *plane,
+ struct drm_plane_state *plane_state,
+ struct drm_mode_object *obj,
+ u64 prop_value, u64 old_val)
+{
+ struct drm_mode_config *config = &plane->dev->mode_config;
+ int ret;
+
+ if (plane->funcs->check_async_props)
+ return plane->funcs->check_async_props(prop, plane, plane_state,
+obj, prop_value,
old_val);
+
+ /*
+* if you are trying to change something other than the FB ID, your
+* change will be either rejected or ignored, so we can stop the check
+* here
+*/
+ if (prop != config->prop_fb_id) {
+ ret = drm_atomic_plane_get_property(plane, plane_state,
+ prop, &old_val);
+ return drm_atomic_check_prop_changes(ret, old_val, prop_value,
prop);
+ }
+
+ if (plane_state->plane->type != DRM_PLANE_TYPE_PRIMARY) {
+ drm_dbg_atomic(prop->dev,
+ "[OBJECT:%d] Only primary planes can be changed
during async flip\n",
+ obj->id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
int drm_atomic_set_property(struct drm_atomic_state *state,
struct drm_file *file_priv,
@@ -1100,7 +1137,6 @@ int drm_atomic_set_property(struct drm_atomic_state
*state,
case DRM_MODE_OBJECT_PLANE: {
struct drm_plane *plane = obj_to_plane(obj);
struct drm_plane_state *plane_state;
- struct drm_mode_config *config = &plane->dev->mode_config;
plane_state = drm_atomic_get_plane_state(state, plane);
if (IS_ERR(plane_state)) {
@@ -1108,19 +1144,11 @@ int drm_atomic_set_property(struct drm_atomic_state
*state,
break;
}
- if (async_flip && prop != config->prop_fb_id) {
- ret = drm_atomic_plane_get_property(plane, plane_state,
- prop, &old_val);
- ret = drm_atomic_check_prop_changes(ret, old_val,
prop_value, prop);
- break;
- }
-
- if (async_flip && plane_state->plane->type !=
DRM_PLANE_TYPE_PRIMARY) {
- drm_dbg_atomic(prop->dev,
- "[OBJECT:%d] Only primary planes can be
changed during async flip\n",
- obj->id);
- ret = -EINVAL;
- break;
+ if (async_flip) {
+
[PATCH v2 0/2] drm/atomic: Allow drivers to write their own plane check for async
Hi, AMD hardware can do more on the async flip path than just the primary plane, so to lift up the current restrictions, this patchset allows drivers to write their own check for planes for async flips. For now this patchset only allow for async commits with IN_FENCE_ID and FB_DAMAGE_CLIPS. Userspace can query if a driver supports this with TEST_ONLY commits. I will left overlay planes for a next iteration. Changes from v1: - Drop overlay planes option for now v1: https://lore.kernel.org/dri-devel/20240116045159.1015510-1-andrealm...@igalia.com/ André André Almeida (2): drm/atomic: Allow drivers to write their own plane check for async flips drm/amdgpu: Implement check_async_props for planes .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 29 + drivers/gpu/drm/drm_atomic_uapi.c | 62 ++- include/drm/drm_atomic_uapi.h | 12 include/drm/drm_plane.h | 5 ++ 4 files changed, 91 insertions(+), 17 deletions(-) -- 2.43.0
RE: [PATCH 00/12] DC Patches January 18, 2024
[Public] Hi all, This week this patchset was tested on the following systems: * Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U * MSI Gaming X Trio RX 6800 * Gigabyte Gaming OC RX 7900 XTX These systems were tested on the following display/connection types: * eDP, (1080p 60hz [5650U]) (1920x1200 60hz [6600U]) (2560x1600 120hz[6600U]) * VGA and DVI (1680x1050 60hz [DP to VGA/DVI, USB-C to VGA/DVI]) * DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz, 4k 240hz [Includes USB-C to DP/HDMI adapters]) * Thunderbolt (LG Ultrafine 5k) * MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60Hz displays) * DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60 displays, and HP Hook G2 with 1 4k60 display) * USB 4 (Kensington SD5700T and 1x 4k 60Hz display) * PCON (Club3D CAC-1085 and 1x 4k 144Hz display [at 4k 120HZ, as that is the max the adapter supports]) The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to): * Changing display configurations and settings * Benchmark testing * Feature testing (Freesync, etc.) Automated testing includes (but is not limited to): * Script testing (scripts to automate some of the manual checks) * IGT testing The patchset consists of the amd-staging-drm-next branch (Head commit - 00263633aa58 drm/amd/display: Fix timing bandwidth calculation for HDMI) with new patches added on top of it. Tested on Ubuntu 22.04.3, on Wayland and X11, using KDE Plasma and Gnome. Tested-by: Daniel Wheeler Thank you, Dan Wheeler Sr. Technologist | AMD SW Display -- 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 amd.com -Original Message- From: amd-gfx On Behalf Of roman...@amd.com Sent: Thursday, January 18, 2024 9:34 AM To: amd-gfx@lists.freedesktop.org Cc: Chung, ChiaHsuan (Tom) ; Li, Sun peng (Leo) ; Siqueira, Rodrigo ; Li, Roman ; Zuo, Jerry ; Pillai, Aurabindo ; Wu, Hersen ; Lin, Wayne ; Wentland, Harry ; Gutierrez, Agustin Subject: [PATCH 00/12] DC Patches January 18, 2024 From: Roman Li This DC patchset brings improvements in multiple areas. In summary, we highlight: * Add power_state/pme_pending flag/usb4_bw_alloc_support flags * Add GART memory support * Improvements for HDMI, IPS, DML2 and others Allen Pan (1): drm/amd/display: Add NULL-checks in dml2 assigned pipe search Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.201.0 Aric Cyr (2): drm/amd/display: Promote DAL to 3.2.268 drm/amd/display: Promote DAL to 3.2.269 Charlene Liu (1): drm/amd/display: Revert "Rework DC Z10 restore" ChunTao Tso (1): drm/amd/display: Replay + IPS + ABM in Full Screen VPB Fudongwang (1): drm/amd/display: Add GART memory support for dmcub Leo (Hanghong) Ma (1): drm/amd/display: Fix timing bandwidth calculation for HDMI Muhammad Ahmed (1): drm/amd/display: add power_state and pme_pending flag Peichen Huang (1): drm/amd/display: Add usb4_bw_alloc_support flag Roman Li (1): drm/amd/display: Add IPS checks before dcn register access Wenjing Liu (1): drm/amd/display: turn off windowed Mpo ODM feature for dcn321 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 +++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +- .../gpu/drm/amd/display/dc/core/dc_stream.c | 9 +- drivers/gpu/drm/amd/display/dc/dc.h | 4 +- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 + drivers/gpu/drm/amd/display/dc/dc_types.h | 5 + .../display/dc/dml2/dml2_dc_resource_mgmt.c | 19 ++-- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 5 + .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 + .../amd/display/dc/inc/hw/clk_mgr_internal.h | 1 + .../drm/amd/display/dc/link/link_detection.c | 18 +++ .../gpu/drm/amd/display/dc/link/link_dpms.c | 58 ++ .../dc/resource/dcn321/dcn321_resource.c | 1 + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 19 +++- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 59 -- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 106 -- .../amd/display/modules/power/power_helpers.c | 5 + .../amd/display/modules/power/power_helpers.h | 1 + 18 files changed, 244 insertions(+), 109 deletions(-) -- 2.34.1
Re: [PATCH v3 0/9] drm/amd/display: improve DTN color state log
On 2023-11-28 12:52, Melissa Wen wrote: > This series updates the color state section of the AMD DTN log to match > color resource differences between DCN versions. > > Currently, the DTN log considers the DCN10 color pipeline, which is > useless for newer DCN versions due to all the color capability > differences. In addition to the new color blocks and features, some > semantic differences meant that the DCN10 output was no longer suitable > for newer families. > > This version addresses comments from Siqueira and Harry [1]. It also > contains some improvements: DPP and MPC gamut remap matrix data in 31.32 > fixed point format and coverage of DCN2+ and DCN3+. > > - The first patch decouple DCN10 color state from HW log in a > preparation for color logs specific to each DCN family. > - Harry kindly provided the second patch with a way to read Gamut Remap > Matrix data in 31.32 fixed point format instead of HW values. > - With this, I replaced the DCN10 gamut remap output to display values > in the new format (third patch). > - Patches 4 and 6 fill up the color state of DPP and MPC blocks for DCN3 > from the right registers. > - As DCN3+ has a new MPC color block for post-blending Gamut Remap > matrix, in the patch 5 I reuse Harry's approach for reading DPP gamut > remap matrix and create a helper to read data of MPC gamut remap > matrix. > - Patch 7 and 9 create the new color state log specific for DCN2+ and > DCN3+. I didn't extend to DCN32 (and also DCN35) because I observed > some differences in the shaper and 3D LUT registers of this version. > - Patch 8 adds description of DPP and MPC color blocks for for better > interpretation of data. > > This new approach works well with the driver-specific color > properties[2] and steamdeck/gamescope[3] together, where we can see > color state changing from default values. I also tested with > steamdeck/KDE and DCN21/GNOME. > > Please find some `before vs after` results below: > > === > > DCN301 - Before: > --- > > DPP:IGAM format IGAM modeDGAM modeRGAM mode GAMUT mode C11 C12 > C13 C14 C21 C22 C23 C24 C31 C32 C33 C34 > [ 0]:0h BypassFixed Bypass Bypass0 > h h h h h h > [ 1]:0h BypassFixed Bypass Bypass0 > h h h h h h > [ 2]:0h BypassFixed Bypass Bypass0 > h h h h h h > [ 3]:0h BypassFixed Bypass Bypass0 > h h h h h h > > MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE > [ 0]: 0h 0h 2h 3 01 0 0 > [ 1]: 0h 1h fh 2 20 0 0 > [ 2]: 0h 2h 3h 3 01 0 0 > [ 3]: 0h 3h 1h 3 20 0 0 > > > DCN301 - After (Gamescope): > --- > > DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode 3DLUT mode 3DLUT bit > depth 3DLUT size RGAM mode GAMUT adjust C11C12C13 > C14C21C22C23C24C31C32 > C33C34 > [ 0]:1 sRGBBypassRAM B RAM A > 12-bit17x17x17 RAM ABypass 00 00 00 > 00 00 00 00 00 00 00 > 00 00 > [ 1]:1 sRGBBypassRAM B RAM A > 12-bit17x17x17 RAM ABypass 00 00 00 > 00 00 00 00 00 00 00 > 00 00 > [ 2]:1 sRGBBypassRAM B RAM A > 12-bit17x17x17 RAM ABypass 00 00 00 > 00 00 00 00 00 00 00 > 00 00 > [ 3]:1 sRGBBypassRAM B RAM A > 12-bit17x17x17 RAM ABypass 00 00 00 > 00 00 00 00 00 00 00 > 00 00 > > DPP Color Caps: input_lut_shared:0 icsc:1 dgam_ram:0 dgam_rom: > srgb:1,bt2020:1,gamma2_2:1,pq:1,hlg:1 post_csc:1 gamcor:1 > dgam_rom_for_yuv:0 3d_lut:1 blnd_lut:1 oscs:0 > > MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE > SHAPER mode 3DLUT mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT > GAMUT adjust C11C12C13C14C21C22 > C23C24C31C32C33C34 > [ 0]: 0h 0h 2h 3
Re: [PATCH] drm/amd/pm: update the power cap setting
On Fri, Jan 19, 2024 at 3:47 AM Kenneth Feng wrote:
>
> update the power cap setting for smu_v13.0.0/smu_v13.0.7
>
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2356
Acked-by: Alex Deucher
> Signed-off-by: Kenneth Feng
> ---
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 54 ++-
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 54 ++-
> 2 files changed, 104 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index 231122622a9c..e769adb8da2c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -2357,6 +2357,7 @@ static int smu_v13_0_0_get_power_limit(struct
> smu_context *smu,
> PPTable_t *pptable = table_context->driver_pptable;
> SkuTable_t *skutable = &pptable->SkuTable;
> uint32_t power_limit, od_percent_upper, od_percent_lower;
> + uint32_t msg_limit =
> skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
>
> if (smu_v13_0_get_current_power_limit(smu, &power_limit))
> power_limit = smu->adev->pm.ac_power ?
> @@ -2380,7 +2381,7 @@ static int smu_v13_0_0_get_power_limit(struct
> smu_context *smu,
> od_percent_upper, od_percent_lower,
> power_limit);
>
> if (max_power_limit) {
> - *max_power_limit = power_limit * (100 + od_percent_upper);
> + *max_power_limit = msg_limit * (100 + od_percent_upper);
> *max_power_limit /= 100;
> }
>
> @@ -2960,6 +2961,55 @@ static bool smu_v13_0_0_wbrf_support_check(struct
> smu_context *smu)
> }
> }
>
> +static int smu_v13_0_0_set_power_limit(struct smu_context *smu,
> + enum smu_ppt_limit_type limit_type,
> + uint32_t limit)
> +{
> + PPTable_t *pptable = smu->smu_table.driver_pptable;
> + SkuTable_t *skutable = &pptable->SkuTable;
> + uint32_t msg_limit =
> skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
> + struct smu_table_context *table_context = &smu->smu_table;
> + OverDriveTableExternal_t *od_table =
> + (OverDriveTableExternal_t *)table_context->overdrive_table;
> + int ret = 0;
> +
> + if (limit_type != SMU_DEFAULT_PPT_LIMIT)
> + return -EINVAL;
> +
> + if (limit <= msg_limit) {
> + if (smu->current_power_limit > msg_limit) {
> + od_table->OverDriveTable.Ppt = 0;
> + od_table->OverDriveTable.FeatureCtrlMask |= 1U <<
> PP_OD_FEATURE_PPT_BIT;
> +
> + ret = smu_v13_0_0_upload_overdrive_table(smu,
> od_table);
> + if (ret) {
> + dev_err(smu->adev->dev, "Failed to upload
> overdrive table!\n");
> + return ret;
> + }
> + }
> + return smu_v13_0_set_power_limit(smu, limit_type, limit);
> + } else if (smu->od_enabled) {
> + ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
> + if (ret)
> + return ret;
> +
> + od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit -
> 100;
> + od_table->OverDriveTable.FeatureCtrlMask |= 1U <<
> PP_OD_FEATURE_PPT_BIT;
> +
> + ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
> + if (ret) {
> + dev_err(smu->adev->dev, "Failed to upload overdrive
> table!\n");
> + return ret;
> + }
> +
> + smu->current_power_limit = limit;
> + } else {
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
> .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
> .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
> @@ -3014,7 +3064,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs
> = {
> .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
> .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
> .get_power_limit = smu_v13_0_0_get_power_limit,
> - .set_power_limit = smu_v13_0_set_power_limit,
> + .set_power_limit = smu_v13_0_0_set_power_limit,
> .set_power_source = smu_v13_0_set_power_source,
> .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
> .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> index 59606a19e3d2..7c3e162e2d81 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/sw
Re: [PATCH v2 1/2] drm/amdgpu: Reset IH OVERFLOW_CLEAR bit
On Fri, Jan 19, 2024 at 3:11 AM Christian König
wrote:
>
>
>
> Am 18.01.24 um 19:54 schrieb Friedrich Vock:
> > Allows us to detect subsequent IH ring buffer overflows as well.
> >
> > Cc: Joshua Ashton
> > Cc: Alex Deucher
> > Cc: Christian König
> > Cc: sta...@vger.kernel.org
> >
> > Signed-off-by: Friedrich Vock
> > ---
> > v2: Reset CLEAR_OVERFLOW bit immediately after setting it
> >
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 2 ++
> > drivers/gpu/drm/amd/amdgpu/cik_ih.c | 7 +++
> > drivers/gpu/drm/amd/amdgpu/cz_ih.c | 6 ++
> > drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 6 ++
> > drivers/gpu/drm/amd/amdgpu/ih_v6_0.c| 7 +++
> > drivers/gpu/drm/amd/amdgpu/ih_v6_1.c| 8
> > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 7 +++
> > drivers/gpu/drm/amd/amdgpu/si_ih.c | 7 +++
> > drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 7 +++
> > drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 7 +++
> > drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 7 +++
> > 11 files changed, 71 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> > index 508f02eb0cf8..6041ec727f06 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> > @@ -69,6 +69,8 @@ struct amdgpu_ih_ring {
> > unsignedrptr;
> > struct amdgpu_ih_regs ih_regs;
> >
> > + bool overflow;
> > +
>
> That flag isn't needed any more in this patch as far as I can see.
It's used in patch 2.
Alex
>
> Regards,
> Christian.
>
> > /* For waiting on IH processing at checkpoint. */
> > wait_queue_head_t wait_process;
> > uint64_tprocessed_timestamp;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> > index 6f7c031dd197..bbadf2e530b8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> > @@ -204,6 +204,13 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
> > tmp = RREG32(mmIH_RB_CNTL);
> > tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
> > WREG32(mmIH_RB_CNTL, tmp);
> > +
> > + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> > + * can be detected.
> > + */
> > + tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
> > + WREG32(mmIH_RB_CNTL, tmp);
> > + ih->overflow = true;
> > }
> > return (wptr & ih->ptr_mask);
> > }
> > diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> > index b8c47e0cf37a..e5c4ed44bad9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> > @@ -216,6 +216,12 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> > WREG32(mmIH_RB_CNTL, tmp);
> >
> > + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> > + * can be detected.
> > + */
> > + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> > + WREG32(mmIH_RB_CNTL, tmp);
> > + ih->overflow = true;
> >
> > out:
> > return (wptr & ih->ptr_mask);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> > index aecad530b10a..075e5c1a5549 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> > @@ -215,6 +215,12 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device
> > *adev,
> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> > WREG32(mmIH_RB_CNTL, tmp);
> >
> > + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> > + * can be detected.
> > + */
> > + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> > + WREG32(mmIH_RB_CNTL, tmp);
> > + ih->overflow = true;
> >
> > out:
> > return (wptr & ih->ptr_mask);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> > b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> > index d9ed7332d805..d0a5a08edd55 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> > @@ -418,6 +418,13 @@ static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev,
> > tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> > WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> > +
> > + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
> > + * can be detected.
> > + */
> > + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
> > + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
> > + ih->overflow = true;
> > out:
> > return (wptr & ih->ptr_mask);
> > }
> > diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> > b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
Re: [PATCH v2 2/4] drm/uAPI: Add "force color format" drm property as setting for userspace
On Wed, 17 Jan 2024 12:58:15 + Andri Yngvason wrote: > mið., 17. jan. 2024 kl. 09:21 skrifaði Pekka Paalanen : ... > > EDID and DisplayID standards also evolve. The kernel could be behind > > userspace in chasing them, which was the reason why the kernel does not > > validate HDR_OUTPUT_METADATA against EDID. > > > > The design of today with HDR_OUTPUT_METADATA and whatnot is > > that userspace is responsible for checking sink capabilities, and > > atomic check is responsible for driver and display controller > > capabilities. > > I'm not really sure where you're going with this. Are you for or > against userspace parsing EDID instead of getting the information from > the kernel? In that specific email, neither. I attempted to describe the current situation without any bias towards whether I think that is a good or not design. There is an existing behaviour, and if you want to deviate from that, you need more justification than for following it. Even the video modes list that I mentioned as the major example of things that userspace should not parse from EDID itself is not exhaustive nor exclusive. Userspace can still craft an arbitrary video mode and set it. If the driver and display controller can do it, it passes I believe, even if it would literally destroy the sink (in the CRT era, you could burn the flyback transistor of an unfortunate monitor). If you want me to take a stance, I think the kernel not gating settings based on EDID for these things is a good idea for these reasons: - EDID can easily be wrong, and it is easier to test sink "unsupported" configurations if you do not need to craft a modified EDID and (reboot to?) load it in the kernel first. - EDID spec gets occasionally extended. If the kernel gated settings, you would not be able to test new features without getting an updated kernel that allows them to pass. This mostly applies to blob properties, and not enums, because you cannot set arbitrary values to enum properties. Finally, as to why userspace parsing EDID at all is a good idea: - The kernel is not interested in most of the stuff contained in EDIDs, so it has no inherent reason to parse everything. - EDID is a fairly wide "API" and gets occasionally extended. Replicating all that in a kernel UAPI is a lot of work that won't benefit the kernel itself. There does not seem to be benefit in reinventing EDID information encoding in fine-grained UAPI structures, but there certainly is risk, because UAPI is written in stone once published. Userspace can get the equivalent from libraries like libdisplay-info which are much easier to develop and replace than UAPI. Thanks, pq pgpxW1a7kitxX.pgp Description: OpenPGP digital signature
[PATCH] drm/amd/pm: update the power cap setting
update the power cap setting for smu_v13.0.0/smu_v13.0.7
Signed-off-by: Kenneth Feng
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 54 ++-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 54 ++-
2 files changed, 104 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 231122622a9c..e769adb8da2c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -2357,6 +2357,7 @@ static int smu_v13_0_0_get_power_limit(struct smu_context
*smu,
PPTable_t *pptable = table_context->driver_pptable;
SkuTable_t *skutable = &pptable->SkuTable;
uint32_t power_limit, od_percent_upper, od_percent_lower;
+ uint32_t msg_limit =
skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
if (smu_v13_0_get_current_power_limit(smu, &power_limit))
power_limit = smu->adev->pm.ac_power ?
@@ -2380,7 +2381,7 @@ static int smu_v13_0_0_get_power_limit(struct smu_context
*smu,
od_percent_upper, od_percent_lower,
power_limit);
if (max_power_limit) {
- *max_power_limit = power_limit * (100 + od_percent_upper);
+ *max_power_limit = msg_limit * (100 + od_percent_upper);
*max_power_limit /= 100;
}
@@ -2960,6 +2961,55 @@ static bool smu_v13_0_0_wbrf_support_check(struct
smu_context *smu)
}
}
+static int smu_v13_0_0_set_power_limit(struct smu_context *smu,
+ enum smu_ppt_limit_type limit_type,
+ uint32_t limit)
+{
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
+ SkuTable_t *skutable = &pptable->SkuTable;
+ uint32_t msg_limit =
skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
+ struct smu_table_context *table_context = &smu->smu_table;
+ OverDriveTableExternal_t *od_table =
+ (OverDriveTableExternal_t *)table_context->overdrive_table;
+ int ret = 0;
+
+ if (limit_type != SMU_DEFAULT_PPT_LIMIT)
+ return -EINVAL;
+
+ if (limit <= msg_limit) {
+ if (smu->current_power_limit > msg_limit) {
+ od_table->OverDriveTable.Ppt = 0;
+ od_table->OverDriveTable.FeatureCtrlMask |= 1U <<
PP_OD_FEATURE_PPT_BIT;
+
+ ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
+ if (ret) {
+ dev_err(smu->adev->dev, "Failed to upload
overdrive table!\n");
+ return ret;
+ }
+ }
+ return smu_v13_0_set_power_limit(smu, limit_type, limit);
+ } else if (smu->od_enabled) {
+ ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
+ if (ret)
+ return ret;
+
+ od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
+ od_table->OverDriveTable.FeatureCtrlMask |= 1U <<
PP_OD_FEATURE_PPT_BIT;
+
+ ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
+ if (ret) {
+ dev_err(smu->adev->dev, "Failed to upload overdrive
table!\n");
+ return ret;
+ }
+
+ smu->current_power_limit = limit;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
@@ -3014,7 +3064,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs =
{
.set_fan_control_mode = smu_v13_0_set_fan_control_mode,
.enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
.get_power_limit = smu_v13_0_0_get_power_limit,
- .set_power_limit = smu_v13_0_set_power_limit,
+ .set_power_limit = smu_v13_0_0_set_power_limit,
.set_power_source = smu_v13_0_set_power_source,
.get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
.set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 59606a19e3d2..7c3e162e2d81 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -2321,6 +2321,7 @@ static int smu_v13_0_7_get_power_limit(struct smu_context
*smu,
PPTable_t *pptable = table_context->driver_pptable;
SkuTable_t *skutable = &pptable->SkuTable;
uint32_t power_limit, od_percent_upper, od_percent_lower;
+ uint32_t msg_limit =
skutable->MsgLimits.Power[PPT_THROTT
