RE: [PATCH] drm/amdgpu: Fix return type in 'aca_bank_hwip_is_matched()'

[Wang, Yang(Kevin)]

[AMD Official Use Only - General]

Thanks,

Reviewed-by: Yang Wang 

Best Regards,
Kevin

-Original Message-
From: SHANMUGAM, SRINIVASAN 
Sent: Tuesday, January 23, 2024 3:26 PM
To: Koenig, Christian ; Deucher, Alexander 

Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN 
; Wang, Yang(Kevin) ; 
Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: Fix return type in 'aca_bank_hwip_is_matched()'

Change the return type of "if (!bank || type == ACA_HWIP_TYPE_UNKNOW)"
to be bool instead of int.

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c:185 aca_bank_hwip_is_matched() warn: 
signedness bug returning '(-22)'

Cc: Yang Wang 
Cc: Hawking Zhang 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
index 8a3c3a49415d..d2662f4d3d75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
@@ -182,7 +182,7 @@ static bool aca_bank_hwip_is_matched(struct aca_bank *bank, 
enum aca_hwip_type t
u64 ipid;

if (!bank || type == ACA_HWIP_TYPE_UNKNOW)
-   return -EINVAL;
+   return false;

hwip = &aca_hwid_mcatypes[type];
if (!hwip->hwid)
--
2.34.1

[PATCH] drm/amdgpu: Fix return type in 'aca_bank_hwip_is_matched()'

[Srinivasan Shanmugam]

Change the return type of "if (!bank || type == ACA_HWIP_TYPE_UNKNOW)"
to be bool instead of int.

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c:185 aca_bank_hwip_is_matched() warn: 
signedness bug returning '(-22)'

Cc: Yang Wang 
Cc: Hawking Zhang 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
index 8a3c3a49415d..d2662f4d3d75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
@@ -182,7 +182,7 @@ static bool aca_bank_hwip_is_matched(struct aca_bank *bank, 
enum aca_hwip_type t
u64 ipid;
 
if (!bank || type == ACA_HWIP_TYPE_UNKNOW)
-   return -EINVAL;
+   return false;
 
hwip = &aca_hwid_mcatypes[type];
if (!hwip->hwid)
-- 
2.34.1

Re: [PATCH 2/2] drm/amdgpu/pm: Use macro definitions in the smu IH process function

[Ma, Jun]

On 1/22/2024 8:44 PM, Lazar, Lijo wrote:
> 
> 
> On 1/22/2024 2:12 PM, Ma Jun wrote:
>> Replace the hard-coded numbers with macro definition
>>
>> Signed-off-by: Ma Jun 
>> ---
>>  .../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 11 +--
>>  .../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h | 11 ---
>>  drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h   |  5 +
>>  drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h   | 10 ++
>>  drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h   |  2 ++
>>  drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 10 +-
>>  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 14 +++---
>>  drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c |  2 +-
>>  8 files changed, 31 insertions(+), 34 deletions(-)
>>
>> diff --git 
>> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h 
>> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
>> index b114d14fc053..c6b7f904e742 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
>> @@ -1618,15 +1618,6 @@ typedef struct {
>>  #define TABLE_WIFIBAND12
>>  #define TABLE_COUNT   13
>>  
>> -//IH Interupt ID
>> -#define IH_INTERRUPT_ID_TO_DRIVER   0xFE
>> -#define IH_INTERRUPT_CONTEXT_ID_BACO0x2
>> -#define IH_INTERRUPT_CONTEXT_ID_AC  0x3
>> -#define IH_INTERRUPT_CONTEXT_ID_DC  0x4
>> -#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D00x5
>> -#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D30x6
>> -#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING  0x7
>> -#define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL0x8
>> -#define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY0x9
>> +
>>  
>>  #endif
>> diff --git 
>> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h 
>> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
>> index 8b1496f8ce58..33937c1d984f 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
>> @@ -1608,15 +1608,4 @@ typedef struct {
>>  #define TABLE_WIFIBAND12
>>  #define TABLE_COUNT   13
>>  
>> -//IH Interupt ID
>> -#define IH_INTERRUPT_ID_TO_DRIVER   0xFE
>> -#define IH_INTERRUPT_CONTEXT_ID_BACO0x2
>> -#define IH_INTERRUPT_CONTEXT_ID_AC  0x3
>> -#define IH_INTERRUPT_CONTEXT_ID_DC  0x4
>> -#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D00x5
>> -#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D30x6
>> -#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING  0x7
>> -#define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL0x8
>> -#define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY0x9
>> -
>>  #endif
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h 
>> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
>> index a0e5ad0381d6..9fe26497e75e 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
>> @@ -63,6 +63,11 @@
>>  #define LINK_WIDTH_MAX  6
>>  #define LINK_SPEED_MAX  3
>>  
>> +#define IH_INTERRUPT_ID_TO_DRIVER   0xFE
>> +#define IH_INTERRUPT_CONTEXT_ID_AC  0x3
>> +#define IH_INTERRUPT_CONTEXT_ID_DC  0x4
>> +#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING  0x7
>> +
>>  static const __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
>>  
>>  static const
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h 
>> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
>> index 46b972f3..436705a18e99 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
>> @@ -59,6 +59,16 @@ extern const int pmfw_decoded_link_width[7];
>>  #define DECODE_GEN_SPEED(gen_speed_idx) 
>> (pmfw_decoded_link_speed[gen_speed_idx])
>>  #define DECODE_LANE_WIDTH(lane_width_idx)   
>> (pmfw_decoded_link_width[lane_width_idx])
>>  
>> +#define IH_INTERRUPT_ID_TO_DRIVER   0xFE
>> +#define IH_INTERRUPT_CONTEXT_ID_BACO0x2
>> +#define IH_INTERRUPT_CONTEXT_ID_AC  0x3
>> +#define IH_INTERRUPT_CONTEXT_ID_DC  0x4
>> +#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D00x5
>> +#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D30x6
>> +#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING  0x7
>> +#define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL0x8
>> +#define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY0x9
>> +
> 
> Since the context_ids are unique across SOCs, these may be kept in
> smu_cmn.h.
> 
Thanks, will fix this in v2.

Regards,
Ma Jun
> Thanks,
> Lijo
> 
>>  struct smu_13_0_max_sustainable_clocks {
>>  uint32_t display_clock;
>>  uint32_

[linux-next:master] BUILD REGRESSION 319fbd8fc6d339e0a1c7b067eed870c518a13a02

[kernel test robot]

tree/branch: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 319fbd8fc6d339e0a1c7b067eed870c518a13a02  Add linux-next specific 
files for 20240122

Unverified Error/Warning (likely false positive, please contact us if 
interested):

drivers/gpu/drm/etnaviv/etnaviv_drv.c:614:3-14: ERROR: probable double put.

Error/Warning ids grouped by kconfigs:

gcc_recent_errors
|-- alpha-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- arc-allmodconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- arc-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- arm-allmodconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- arm-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- csky-allmodconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- csky-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- csky-randconfig-002-20240122
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- loongarch-allmodconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- loongarch-defconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- loongarch-randconfig-r122-20240122
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- microblaze-allmodconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- microblaze-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- mips-allyesconfig
|   |-- 
(.ref.text):relocation-truncated-to-fit:R_MIPS_26-against-start_secondary
|   |-- (.text):relocation-truncated-to-fit:R_MIPS_26-against-kernel_entry
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- openrisc-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- parisc-allmodconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- parisc-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- riscv-allmodconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- riscv-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- s390-allmodconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- s390-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm_crtc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|-- sh-randconfig-r131-20240122
|   |-- 
drivers

RE: [PATCH 2/2] drm/amdgpu/gfx11: set UNORD_DISPATCH in compute MQDs

[Xu, Feifei]

[AMD Official Use Only - General]

Series is Reviewed-by: Feifei Xu 

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Tuesday, January 23, 2024 3:47 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; sta...@vger.kernel.org
Subject: [PATCH 2/2] drm/amdgpu/gfx11: set UNORD_DISPATCH in compute MQDs

This needs to be set to 1 to avoid a potential deadlock in the GC 10.x and 
newer.  On GC 9.x and older, this needs to be set to 0. This can lead to hangs 
in some mixed graphics and compute workloads. Updated firmware is also required 
for AQL.

Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c   | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 043eff309100..c1e10760 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -3846,7 +3846,7 @@ static int gfx_v11_0_compute_mqd_init(struct 
amdgpu_device *adev, void *m,
(order_base_2(prop->queue_size / 4) - 1));
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
(order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
-   tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
+   tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
prop->allow_tunneling);
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); diff --git 
a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
index 15277f1d5cf0..d722cbd31783 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
@@ -224,6 +224,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
m->cp_hqd_pq_control |=
ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
+   m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);

m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
--
2.42.0

Re: [PATCH v2 0/8] Expand and improve AMDGPU documentation

[Mario Limonciello]

On 1/22/2024 15:24, Rodrigo Siqueira wrote:

This patchset improves how the AMDGPU display documentation is
organized, expands the kernel-doc to extract information from the
source, and adds more context about DC workflow. Finally, at the end of
this series, we also introduce a contribution section for those
interested in contributing to the display code.

Changes since V1:
- Remove unprecise information about the DC process.
- Expand the contribution list.
- Rebase.

Thanks
Siqueira

Rodrigo Siqueira (8):
   Documentation/gpu: Add basic page for HUBP
   Documentation/gpu: Add simple doc page for DCHUBBUB
   Documentation/gpu: Add kernel doc entry for DPP
   Documentation/gpu: Add kernel doc entry for MPC
   Documentation/gpu: Add entry for OPP in the kernel doc
   Documentation/gpu: Add entry for the DIO component
   Documentation/gpu: Add an explanation about the DC weekly patches
   Documentation/gpu: Introduce a simple contribution list for display
 code

  .../gpu/amdgpu/display/dcn-blocks.rst |  78 ++
  .../amdgpu/display/display-contributing.rst   | 168 
  .../gpu/amdgpu/display/display-manager.rst|   3 -
  Documentation/gpu/amdgpu/display/index.rst|  78 +-
  drivers/gpu/drm/amd/display/TODO  | 110 
  .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |   6 +
  drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   |  26 ++
  drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |  13 +-
  drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   | 250 --
  drivers/gpu/drm/amd/display/dc/inc/hw/opp.h   |  16 ++
  .../amd/display/dc/link/hwss/link_hwss_dio.h  |  10 +
  11 files changed, 560 insertions(+), 198 deletions(-)
  create mode 100644 Documentation/gpu/amdgpu/display/dcn-blocks.rst
  create mode 100644 Documentation/gpu/amdgpu/display/display-contributing.rst
  delete mode 100644 drivers/gpu/drm/amd/display/TODO



Reviewed-by: Mario Limonciello 

Re: [PATCH 1/2] drm/amdgpu: Reset IH OVERFLOW_CLEAR bit after writing rptr

[Joshua Ashton]

On 1/22/24 13:35, Christian König wrote:

Am 22.01.24 um 11:45 schrieb Friedrich Vock:

On 22.01.24 11:21, Friedrich Vock wrote:

On 22.01.24 11:10, Christian König wrote:

Am 19.01.24 um 20:18 schrieb Felix Kuehling:

On 2024-01-18 07:07, Christian König wrote:

Am 18.01.24 um 00:44 schrieb Friedrich Vock:

On 18.01.24 00:00, Alex Deucher wrote:
[SNIP]
No, amdgpu.noretry=1 does not change anything.


Well the good news first the hw engineer answered rather quickly.
The bad news is that the hardware really doesn't work as documented
in multiple ways.

First of all the CLEAR bit is a level and not a trigger, so the
intention to clear it is indeed correct. For now please modify this
patch so that the CLEAR bit is set and cleared directly after
setting it, this way we should be able to detect further overflows
immediately.

Then the APU the Steam Deck uses simply doesn't have the filter
function for page faults in the hardware, the really bad news is it
also doesn't have the extra IH rings where we could re-route the
faults to prevent overflows.

That full explains the behavior you have been seeing, but doesn't
really provide a doable solution to mitigate this problem.

I'm going to dig deeper into the hw documentation and specification
to see if we can use a different feature to avoid the overflow.


If we're not enabling retry faults, then each wave front should
generate at most one fault. You should be able to avoid overflows by
making the IH ring large enough to accommodate one fault per wave
front.


That is the exact same argument our HW engineers came up with when we
asked why the APU is missing all those nice IH ring overflow avoidance
features the dGPUs have :)


I can reproduce IH overflows on my RX 6700 XT dGPU as well FWIW.


Interesting data point. We have probably looked to much into the faults 
on MI* products and never checked Navi.


Can you try to just setting WPTR_OVERFLOW_ENABLE to 0? At least in 
theory that should disable IH overflows altogether on Navi without 
causing loss of IVs.





The only problem with this approach is that on Navi when a wave is
blocked by waiting on a fault you can't kill it using soft recovery
any more (at least when my understanding is correct).


Killing page-faulted waves via soft recovery works. From my testing on
Deck, it seems to take a bit of time, but if you try for long enough
soft recovery eventually succeeds.


Ok that is massively strange. We had tons of discussions about that 
shader can't be interrupted while they wait for a fault on Navi.


Maybe killing them is still possible, need to double check that as well.




On second thought, could it be that this is the critical flaw in the "at
most one fault per wave" thinking?


Well completely agree that this. That rational to leave out the new IH 
features on APUs is rather weak.




Most work submissions in practice submit more waves than the number of
wave slots the GPU has.
As far as I understand soft recovery, the only thing it does is kill all
active waves. This frees up the CUs so more waves are launched, which
can fault again, and that leads to potentially lots of faults for a
single wave slot in the end.


Exactly that, but killing each wave takes a moment since we do that in a 
loop with a bit delay in there.


So the interrupt handler should at least in theory have time to catch up.


I don't think there is any delay in that loop is there?

while (!dma_fence_is_signaled(fence) &&
   ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
ring->funcs->soft_recovery(ring, vmid);

(soft_recovery function does not have a delay/sleep/whatever either)

FWIW, two other changes we did in SteamOS to make recovery more reliable 
on VANGOGH was:


1) Move the timeout determination after the spinlock setting the fence 
error.


2) Raise the timeout from 0.1s to 1s.

- Joshie 🐸✨




Regards,
Christian.



Regards,
Friedrich

[PATCH v2 3/8] Documentation/gpu: Add kernel doc entry for DPP

[Rodrigo Siqueira]

This commit introduces basic DPP information and the struct scan for
code documentation.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: Harry Wentland 
Cc: Hamza Mahfooz 
Cc: Christian König 
Cc: Aurabindo Pillai 
Signed-off-by: Rodrigo Siqueira 
---
 .../gpu/amdgpu/display/dcn-blocks.rst | 12 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   | 26 +++
 2 files changed, 38 insertions(+)

diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst 
b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
index e4e0a4ddca4e..83fc4a03113e 100644
--- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst
+++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
@@ -28,3 +28,15 @@ HUBP
 
 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
:internal:
+
+DPP
+---
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+   :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+   :export:
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+   :internal:
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 4e604bf24f51..a962a9f36845 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -27,6 +27,32 @@
 #ifndef __DAL_DPP_H__
 #define __DAL_DPP_H__
 
+/**
+ * DOC: overview
+ *
+ * The DPP (Display Pipe and Plane) block is the unified display data
+ * processing engine in DCN for processing graphic or video data on per DPP
+ * rectangle base. This rectangle can be a part of SLS (Single Large Surface),
+ * or a layer to be blended with other DPP, or a rectangle associated with a
+ * display tile.
+ *
+ * It provides various functions including:
+ * - graphic color keyer
+ * - graphic cursor compositing
+ * - graphic or video image source to destination scaling
+ * - image sharping
+ * - video format conversion from 4:2:0 or 4:2:2 to 4:4:4
+ * - Color Space Conversion
+ * - Host LUT gamma adjustment
+ * - Color Gamut Remap
+ * - brightness and contrast adjustment.
+ *
+ * DPP pipe consists of Converter and Cursor (CNVC), Scaler (DSCL), Color
+ * Management (CM), Output Buffer (OBUF) and Digital Bypass (DPB) module
+ * connected in a video/graphics pipeline.
+ */
+
+
 #include "transform.h"
 #include "cursor_reg_cache.h"
 
-- 
2.43.0

[PATCH v2 6/8] Documentation/gpu: Add entry for the DIO component

[Rodrigo Siqueira]

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: Harry Wentland 
Cc: Hamza Mahfooz 
Cc: Christian König 
Cc: Aurabindo Pillai 
Signed-off-by: Rodrigo Siqueira 
---
 Documentation/gpu/amdgpu/display/dcn-blocks.rst  | 12 
 .../gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h | 10 ++
 2 files changed, 22 insertions(+)

diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst 
b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
index 5ba3c04c1db0..a3fbd3ea028b 100644
--- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst
+++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
@@ -64,3 +64,15 @@ OPP
 
 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
:internal:
+
+DIO
+---
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
+   :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
+   :export:
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
+   :internal:
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h 
b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
index f4633d3cf9b9..a1f72fe378ee 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h
@@ -22,6 +22,16 @@
  * Authors: AMD
  *
  */
+
+/**
+ * DOC: overview
+ *
+ * Display Input Output (DIO), is the display input and output unit in DCN. It
+ * includes output encoders to support different display output, like
+ * DisplayPort, HDMI, DVI interface, and others. It also includes the control
+ * and status channels for these interfaces.
+ */
+
 #ifndef __LINK_HWSS_DIO_H__
 #define __LINK_HWSS_DIO_H__
 
-- 
2.43.0

[PATCH v2 7/8] Documentation/gpu: Add an explanation about the DC weekly patches

[Rodrigo Siqueira]

This commit introduces some explanation about the display team
validation.

Changes since V1:
- Remove unprecise information about the DC process for now, can be
  added later on.
- Jani: Fix bullets

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: Harry Wentland 
Cc: Hamza Mahfooz 
Cc: Christian König 
Cc: Aurabindo Pillai 
Signed-off-by: Rodrigo Siqueira 
---
 Documentation/gpu/amdgpu/display/index.rst | 76 --
 1 file changed, 69 insertions(+), 7 deletions(-)

diff --git a/Documentation/gpu/amdgpu/display/index.rst 
b/Documentation/gpu/amdgpu/display/index.rst
index b09d1434754d..aa89e8f9ab89 100644
--- a/Documentation/gpu/amdgpu/display/index.rst
+++ b/Documentation/gpu/amdgpu/display/index.rst
@@ -7,18 +7,80 @@ drm/amd/display - Display Core (DC)
 AMD display engine is partially shared with other operating systems; for this
 reason, our Display Core Driver is divided into two pieces:
 
-1. **Display Core (DC)** contains the OS-agnostic components. Things like
+#. **Display Core (DC)** contains the OS-agnostic components. Things like
hardware programming and resource management are handled here.
-2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
-   amdgpu base driver and DRM are implemented here.
+#. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
+   amdgpu base driver and DRM are implemented here. For example, you can check
+   display/amdgpu_dm/ folder.
+
+--
+DC Code validation
+--
+
+Maintaining the same code base across multiple OSes requires a lot of
+synchronization effort between repositories and exhaustive validation. In the
+DC case, we maintain a tree to centralize code from different parts. The shared
+repository has integration tests with our Internal Linux CI farm, and we run a
+comprehensive set of IGT tests in various AMD GPUs/APUs (mostly recent dGPUs
+and APUs). Our CI also checks ARM64/32, PPC64/32, and x86_64/32 compilation
+with DCN enabled and disabled.
+
+When we upstream a new feature or some patches, we pack them in a patchset with
+the prefix **DC Patches for **, which is created based on the latest
+`amd-staging-drm-next `_. All of
+those patches are under a DC version tested as follows:
+
+* Ensure that every patch compiles and the entire series pass our set of IGT
+  test in different hardware.
+* Prepare a branch with those patches for our validation team. If there is an
+  error, a developer will debug as fast as possible; usually, a simple bisect
+  in the series is enough to point to a bad change, and two possible actions
+  emerge: fix the issue or drop the patch. If it is not an easy fix, the bad
+  patch is dropped.
+* Finally, developers wait a few days for community feedback before we merge
+  the series.
+
+It is good to stress that the test phase is something that we take extremely
+seriously, and we never merge anything that fails our validation. Follows an
+overview of our test set:
+
+#. Manual test
+* Multiple Hotplugs with DP and HDMI.
+* Stress test with multiple display configuration changes via the user 
interface.
+* Validate VRR behaviour.
+* Check PSR.
+* Validate MPO when playing video.
+* Test more than two displays connected at the same time.
+* Check suspend/resume.
+* Validate FPO.
+* Check MST.
+#. Automated test
+* IGT tests in a farm with GPUs and APUs that support DCN and DCE.
+* Compilation validation with the latest GCC and Clang from LTS distro.
+* Cross-compilation for PowerPC 64/32, ARM 64/32, and x86 32.
+
+In terms of test setup for CI and manual tests, we usually use:
+
+#. The latest Ubuntu LTS.
+#. In terms of userspace, we only use fully updated open-source components
+   provided by the distribution official package manager.
+#. Regarding IGT, we use the latest code from the upstream.
+#. Most of the manual tests are conducted in the GNome but we also use KDE.
+
+Notice that someone from our test team will always reply to the cover letter
+with the test report.
+
+--
+DC Information
+--
 
 The display pipe is responsible for "scanning out" a rendered frame from the
 GPU memory (also called VRAM, FrameBuffer, etc.) to a display. In other words,
 it would:
 
-1. Read frame information from memory;
-2. Perform required transformation;
-3. Send pixel data to sink devices.
+#. Read frame information from memory;
+#. Perform required transformation;
+#. Send pixel data to sink devices.
 
 If you want to learn more about our driver details, take a look at the below
 table of content:
@@ -26,8 +88,8 @@ table of content:
 .. toctree::
 
display-manager.rst
-   dc-debug.rst
dcn-overview.rst
dcn-blocks.rst
mpo-overview.rst
+   dc-debug.rst
dc-glossary.rst
-- 
2.43.0

[PATCH v2 4/8] Documentation/gpu: Add kernel doc entry for MPC

[Rodrigo Siqueira]

This commit adds a kernel-doc entry for the MPC block. Since it enabled
the kernel-doc to parse some of the documentation in the mpc.h file,
fixing some of the comments was required.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: Harry Wentland 
Cc: Hamza Mahfooz 
Cc: Christian König 
Cc: Aurabindo Pillai 
Signed-off-by: Rodrigo Siqueira 
---
 .../gpu/amdgpu/display/dcn-blocks.rst |  12 +
 .../gpu/amdgpu/display/display-manager.rst|   3 -
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   | 250 --
 3 files changed, 185 insertions(+), 80 deletions(-)

diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst 
b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
index 83fc4a03113e..1a223f33202e 100644
--- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst
+++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
@@ -40,3 +40,15 @@ DPP
 
 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
:internal:
+
+MPC
+---
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+   :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+   :export:
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+   :internal:
diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst 
b/Documentation/gpu/amdgpu/display/display-manager.rst
index be2651ecdd7f..67a811e6891f 100644
--- a/Documentation/gpu/amdgpu/display/display-manager.rst
+++ b/Documentation/gpu/amdgpu/display/display-manager.rst
@@ -131,9 +131,6 @@ The DRM blend mode and its elements are then mapped by 
AMDGPU display manager
 (DM) to program the blending configuration of the Multiple Pipe/Plane Combined
 (MPC), as follows:
 
-.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
-   :doc: mpc-overview
-
 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
:functions: mpcc_blnd_cfg
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index a11e40fddc44..ba9b942ce09f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -23,13 +23,28 @@
  */
 
 /**
- * DOC: mpc-overview
+ * DOC: overview
  *
- * Multiple Pipe/Plane Combined (MPC) is a component in the hardware pipeline
+ * Multiple Pipe/Plane Combiner (MPC) is a component in the hardware pipeline
  * that performs blending of multiple planes, using global and per-pixel alpha.
  * It also performs post-blending color correction operations according to the
  * hardware capabilities, such as color transformation matrix and gamma 1D and
  * 3D LUT.
+ *
+ * MPC receives output from all DPP pipes and combines them to multiple outputs
+ * supporting "M MPC inputs -> N MPC outputs" flexible composition
+ * architecture. It features:
+ *
+ * - Programmable blending structure to allow software controlled blending and
+ *   cascading;
+ * - Programmable window location of each DPP in active region of display;
+ * - Combining multiple DPP pipes in one active region when a single DPP pipe
+ *   cannot process very large surface;
+ * - Combining multiple DPP from different SLS with blending;
+ * - Stereo formats from single DPP in top-bottom or side-by-side modes;
+ * - Stereo formats from 2 DPPs;
+ * - Alpha blending of multiple layers from different DPP pipes;
+ * - Programmable background color;
  */
 
 #ifndef __DC_MPCC_H__
@@ -83,34 +98,66 @@ enum mpcc_alpha_blend_mode {
 
 /**
  * struct mpcc_blnd_cfg - MPCC blending configuration
- *
- * @black_color: background color
- * @alpha_mode: alpha blend mode (MPCC_ALPHA_BLND_MODE)
- * @pre_multiplied_alpha: whether pixel color values were pre-multiplied by the
- * alpha channel (MPCC_ALPHA_MULTIPLIED_MODE)
- * @global_gain: used when blend mode considers both pixel alpha and plane
- * alpha value and assumes the global alpha value.
- * @global_alpha: plane alpha value
- * @overlap_only: whether overlapping of different planes is allowed
- * @bottom_gain_mode: blend mode for bottom gain setting
- * @background_color_bpc: background color for bpc
- * @top_gain: top gain setting
- * @bottom_inside_gain: blend mode for bottom inside
- * @bottom_outside_gain:  blend mode for bottom outside
  */
 struct mpcc_blnd_cfg {
-   struct tg_color black_color;/* background color */
-   enum mpcc_alpha_blend_mode alpha_mode;  /* alpha blend mode */
-   bool pre_multiplied_alpha;  /* alpha pre-multiplied mode flag */
+   /**
+* @black_color: background color.
+*/
+   struct tg_color black_color;
+
+   /**
+* @alpha_mode: alpha blend mode (MPCC_ALPHA_BLND_MODE).
+*/
+   enum mpcc_alpha_blend_mode alpha_mode;
+
+   /***
+* @@pre_multiplied_alpha:
+*
+* Whether pixel color values were pre-multiplied by the alpha channel
+* (MPCC_ALPHA_MULTIPLIED_MODE).
+*/
+   bool pre_multiplied_alpha;
+
+   /**
+* @global_gain: Used when blend mode considers both pixel alpha and 
plane.
+

[PATCH v2 8/8] Documentation/gpu: Introduce a simple contribution list for display code

[Rodrigo Siqueira]

This commit adds a contribution list for display under the kernel
documentation with some first suggestions. It also drops an old TODO
list from the display folder.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: Harry Wentland 
Cc: Hamza Mahfooz 
Cc: Christian König 
Cc: Aurabindo Pillai 
Signed-off-by: Rodrigo Siqueira 
---
 .../amdgpu/display/display-contributing.rst   | 168 ++
 Documentation/gpu/amdgpu/display/index.rst|   1 +
 drivers/gpu/drm/amd/display/TODO  | 110 
 3 files changed, 169 insertions(+), 110 deletions(-)
 create mode 100644 Documentation/gpu/amdgpu/display/display-contributing.rst
 delete mode 100644 drivers/gpu/drm/amd/display/TODO

diff --git a/Documentation/gpu/amdgpu/display/display-contributing.rst 
b/Documentation/gpu/amdgpu/display/display-contributing.rst
new file mode 100644
index ..fdb2bea01d53
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/display-contributing.rst
@@ -0,0 +1,168 @@
+.. _display_todos:
+
+==
+AMDGPU - Display Contributions
+==
+
+First of all, if you are here, you probably want to give some technical
+contribution to the display code, and for that, we say thank you :)
+
+This page summarizes some of the issues you can help with; keep in mind that
+this is a static page, and it is always a good idea to try to reach developers
+in the amdgfx or some of the maintainers. Finally, this page follows the DRM
+way of creating a TODO list; for more information, check
+'Documentation/gpu/todo.rst'.
+
+Gitlab issues
+=
+
+Users can report issues associated with AMD GPUs at:
+
+- https://gitlab.freedesktop.org/drm/amd
+
+Usually, we try to add a proper label to all new tickets to make it easy to
+filter issues. If you can reproduce any problem, you could help by adding more
+information or fixing the issue.
+
+Level: diverse
+
+IGT
+===
+
+`IGT`_ provides many integration tests that can be run on your GPU. We always
+want to pass a large set of tests to increase the test coverage in our CI. If
+you wish to contribute to the display code but are unsure where a good place
+is, we recommend you run all IGT tests and try to fix any failure you see in
+your hardware. Keep in mind that this failure can be an IGT problem or a kernel
+issue; it is necessary to analyze case-by-case.
+
+Level: diverse
+
+.. _IGT: https://gitlab.freedesktop.org/drm/igt-gpu-tools
+
+Compilation
+===
+
+Fix compilation warnings
+
+
+Enable the W1 or W2 warning level in the kernel compilation and try to fix the
+issues on the display side.
+
+Level: Starter
+
+Fix compilation issues when using um architecture
+-
+
+Linux has a User-mode Linux (UML) feature, and the kernel can be compiled to
+the **um** architecture. Compiling for **um** can bring multiple advantages
+from the test perspective. We currently have some compilation issues in this
+area that we need to fix.
+
+Level: Intermediate
+
+Code Refactor
+=
+
+Add prefix to DC functions to improve the debug with ftrace
+---
+
+The Ftrace debug feature (check 'Documentation/trace/ftrace.rst') is a
+fantastic way to check the code path when developers try to make sense of a
+bug. Ftrace provides a filter mechanism that can be useful when the developer
+has some hunch of which part of the code can cause the issue; for this reason,
+if a set of functions has a proper prefix, it becomes easy to create a good
+filter. Additionally, prefixes can improve stack trace readability.
+
+The DC code does not follow some prefix rules, which makes the Ftrace filter
+more complicated and reduces the readability of the stack trace. If you want
+something simple to start contributing to the display, you can make patches for
+adding prefixes to DC functions. To create those prefixes, use part of the file
+name as a prefix for all functions in the target file. Check the
+'amdgpu_dm_crtc.c` and `amdgpu_dm_plane.c` for some references. However, we
+strongly advise not to send huge patches changing these prefixes; otherwise, it
+will be hard to review and test, which can generate second thoughts from
+maintainers. Try small steps; in case of double, you can ask before you put in
+effort. We recommend first looking at folders like dceXYZ, dcnXYZ, basics,
+bios, core, clk_mgr, hwss, resource, and irq.
+
+Level: Starter
+
+Reduce code duplication
+---
+
+AMD has an extensive portfolio with various dGPUs and APUs that amdgpu
+supports. To maintain the new hardware release cadence, DCE/DCN was designed in
+a modular design, making the bring-up for new hardware fast. Over the years,
+amdgpu accumulated some technical debt in the code duplication area. For this
+task, it would be a good idea to find a tool that can discover code duplication
+(including patterns) and use it as guidance to

[PATCH v2 2/8] Documentation/gpu: Add simple doc page for DCHUBBUB

[Rodrigo Siqueira]

Enable the documentation to extract code documentation from dchubbub.h
file.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: Harry Wentland 
Cc: Hamza Mahfooz 
Cc: Christian König 
Cc: Aurabindo Pillai 
Signed-off-by: Rodrigo Siqueira 
---
 Documentation/gpu/amdgpu/display/dcn-blocks.rst  | 12 
 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h |  6 ++
 2 files changed, 18 insertions(+)

diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst 
b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
index 5da34d5b73d8..e4e0a4ddca4e 100644
--- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst
+++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
@@ -5,6 +5,18 @@ DCN Blocks
 In this section, you will find some extra details about some of the DCN blocks
 and the code documentation when it is automatically generated.
 
+DCHUBBUB
+
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+   :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+   :export:
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+   :internal:
+
 HUBP
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index 901891316dfb..2ae7484d18af 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -26,6 +26,12 @@
 #ifndef __DAL_DCHUBBUB_H__
 #define __DAL_DCHUBBUB_H__
 
+/**
+ * DOC: overview
+ *
+ * There is only one common DCHUBBUB. It contains the common request and return
+ * blocks for the Data Fabric Interface that are not clock/power gated.
+ */
 
 enum dcc_control {
dcc_control__256_256_xxx,
-- 
2.43.0

[PATCH v2 5/8] Documentation/gpu: Add entry for OPP in the kernel doc

[Rodrigo Siqueira]

Introduce OPP as part of the kernel documentation.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: Harry Wentland 
Cc: Hamza Mahfooz 
Cc: Christian König 
Cc: Aurabindo Pillai 
Signed-off-by: Rodrigo Siqueira 
---
 Documentation/gpu/amdgpu/display/dcn-blocks.rst | 12 
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 16 
 2 files changed, 28 insertions(+)

diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst 
b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
index 1a223f33202e..5ba3c04c1db0 100644
--- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst
+++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
@@ -52,3 +52,15 @@ MPC
 
 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
:internal:
+
+OPP
+---
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+   :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+   :export:
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+   :internal:
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 7617fabbd16e..aee5372e292c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -23,6 +23,22 @@
  *
  */
 
+/**
+ * DOC: overview
+ *
+ * The Output Plane Processor (OPP) block groups have functions that format
+ * pixel streams such that they are suitable for display at the display device.
+ * The key functions contained in the OPP are:
+ *
+ * - Adaptive Backlight Modulation (ABM)
+ * - Formatter (FMT) which provide pixel-by-pixel operations for format the
+ *   incoming pixel stream.
+ * - Output Buffer that provide pixel replication, and overlapping.
+ * - Interface between MPC and OPTC.
+ * - Clock and reset generation.
+ * - CRC generation.
+ */
+
 #ifndef __DAL_OPP_H__
 #define __DAL_OPP_H__
 
-- 
2.43.0

[PATCH v2 1/8] Documentation/gpu: Add basic page for HUBP

[Rodrigo Siqueira]

Create the HUBP documentation page and add the doc references to extract
the HUBP code documentation.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: Harry Wentland 
Cc: Hamza Mahfooz 
Cc: Christian König 
Cc: Aurabindo Pillai 
Signed-off-by: Rodrigo Siqueira 
---
 .../gpu/amdgpu/display/dcn-blocks.rst  | 18 ++
 Documentation/gpu/amdgpu/display/index.rst |  1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h   | 13 -
 3 files changed, 31 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/gpu/amdgpu/display/dcn-blocks.rst

diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst 
b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
new file mode 100644
index ..5da34d5b73d8
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
@@ -0,0 +1,18 @@
+==
+DCN Blocks
+==
+
+In this section, you will find some extra details about some of the DCN blocks
+and the code documentation when it is automatically generated.
+
+HUBP
+
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+   :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+   :export:
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+   :internal:
diff --git a/Documentation/gpu/amdgpu/display/index.rst 
b/Documentation/gpu/amdgpu/display/index.rst
index f8a4f53d70d8..b09d1434754d 100644
--- a/Documentation/gpu/amdgpu/display/index.rst
+++ b/Documentation/gpu/amdgpu/display/index.rst
@@ -28,5 +28,6 @@ table of content:
display-manager.rst
dc-debug.rst
dcn-overview.rst
+   dcn-blocks.rst
mpo-overview.rst
dc-glossary.rst
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 7f3f9b69e903..dedc5370023e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -26,13 +26,24 @@
 #ifndef __DAL_HUBP_H__
 #define __DAL_HUBP_H__
 
+/**
+ * DOC: overview
+ *
+ * Display Controller Hub (DCHUB) is the gateway between the Scalable Data Port
+ * (SDP) and DCN. This component has multiple features, such as memory
+ * arbitration, rotation, and cursor manipulation.
+ *
+ * There is one HUBP allocated per pipe, which fetches data and converts
+ * different pixel formats (i.e. ARGB, NV12, etc) into linear, interleaved
+ * and fixed-depth streams of pixel data.
+ */
+
 #include "mem_input.h"
 #include "cursor_reg_cache.h"
 
 #define OPP_ID_INVALID 0xf
 #define MAX_TTU 0xff
 
-
 enum cursor_pitch {
CURSOR_PITCH_64_PIXELS = 0,
CURSOR_PITCH_128_PIXELS,
-- 
2.43.0

[PATCH v2 0/8] Expand and improve AMDGPU documentation

[Rodrigo Siqueira]

This patchset improves how the AMDGPU display documentation is
organized, expands the kernel-doc to extract information from the
source, and adds more context about DC workflow. Finally, at the end of
this series, we also introduce a contribution section for those
interested in contributing to the display code.

Changes since V1:
- Remove unprecise information about the DC process.
- Expand the contribution list.
- Rebase.

Thanks
Siqueira

Rodrigo Siqueira (8):
  Documentation/gpu: Add basic page for HUBP
  Documentation/gpu: Add simple doc page for DCHUBBUB
  Documentation/gpu: Add kernel doc entry for DPP
  Documentation/gpu: Add kernel doc entry for MPC
  Documentation/gpu: Add entry for OPP in the kernel doc
  Documentation/gpu: Add entry for the DIO component
  Documentation/gpu: Add an explanation about the DC weekly patches
  Documentation/gpu: Introduce a simple contribution list for display
code

 .../gpu/amdgpu/display/dcn-blocks.rst |  78 ++
 .../amdgpu/display/display-contributing.rst   | 168 
 .../gpu/amdgpu/display/display-manager.rst|   3 -
 Documentation/gpu/amdgpu/display/index.rst|  78 +-
 drivers/gpu/drm/amd/display/TODO  | 110 
 .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |   6 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   |  26 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |  13 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   | 250 --
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h   |  16 ++
 .../amd/display/dc/link/hwss/link_hwss_dio.h  |  10 +
 11 files changed, 560 insertions(+), 198 deletions(-)
 create mode 100644 Documentation/gpu/amdgpu/display/dcn-blocks.rst
 create mode 100644 Documentation/gpu/amdgpu/display/display-contributing.rst
 delete mode 100644 drivers/gpu/drm/amd/display/TODO

-- 
2.43.0

Re: [PATCH] drm/amdgpu: check flag ring->no_scheduler before usage

[Alex Deucher]

On Mon, Jan 22, 2024 at 7:06 AM Christian König
 wrote:
>
> Am 21.01.24 um 01:19 schrieb vitaly.pros...@amd.com:
> > From: Vitaly Prosyak 
> >
> > The issue started to appear after the following commit
> >   11b3b9f461c5c4f700f6c8da202fcc2fd6418e1f (scheduler to variable number
> >   of run-queues). The scheduler flag ready (ring->sched.ready) could not be
> >   used to validate multiple scenarios, for example, check job is running,
> >   gpu_reset, PCI errors etc. The reason is that after GPU reset, the flag
> >   is set to true unconditionally even for those rings with an uninitialized 
> > scheduler.
>
> That's probably a bug we should fix instead.
>
> scheduler.ready means that the engines was initialized and should
> *never* be touched during GPU reset.
>
> The only exception to this is when the GPU reset fails and we can't get
> the engine working again. In this case the scheduler.ready flag should
> be set to false.
>
> The problem is that when we moved this flag into the scheduler we had
> some rings (like KIQ) which don't have a scheduler but still need to
> toggle this flag. We should probably look into cleaning that up instead.
>

I think this is the right fix in this case.  The queues with
no_scheduler set aren't using the GPU scheduler in the first place, so
we don't really care what the status is, we should just not be
touching them at all in cases which involve the scheduler.  That said,
I agree we should clean up the sched.ready handling in general.

Alex


> Regards,
> Christian.
>
> >   As a result, we called drm_sched_stop, drm_sched_start for the 
> > uninitialized
> >   schedule and NULL pointer dereference is occured. For example, the 
> > following
> >   occurs on Navi10 during GPU reset:
> >
> >   [  354.231044] Hardware name: TYAN B8021G88V2HR-2T/S8021GM2NR-2T, BIOS 
> > V1.03.B10 04/01/2019
> >   [  354.239152] Workqueue: amdgpu-reset-dev drm_sched_job_timedout 
> > [gpu_sched]
> >   [  354.246047] RIP: 0010:__flush_work.isra.0+0x23a/0x250
> >   [  354.251110] Code: 8b 04 25 40 2e 03 00 48 89 44 24 40 48 8b 73 40 8b 
> > 4b 30 e9 f9 fe ff ff 40 30 f6 4c 8b 36 e9 37 fe ff ff 0f 0b e9 3a ff ff ff 
> > <0f> 0b e9 33 ff ff ff 66
> >   66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00
> >   [  354.269876] RSP: 0018:b234c00e3c20 EFLAGS: 00010246
> >   [  354.275121] RAX: 0011 RBX: 9796d9796de0 RCX: 
> > 
> >   [  354.282271] RDX: 0001 RSI:  RDI: 
> > 9796d9796de0
> >   [  354.289420] RBP: 9796d9796de0 R08: 977780401940 R09: 
> > a1a5c620
> >   [  354.296570] R10:  R11:  R12: 
> > 
> >   [  354.303720] R13: 0001 R14: 9796d97905c8 R15: 
> > 9796d9790230
> >   [  354.310868] FS:  () GS:97865f04() 
> > knlGS:
> >   [  354.318963] CS:  0010 DS:  ES:  CR0: 80050033
> >   [  354.324717] CR2: 7fd5341fca50 CR3: 002c27a22000 CR4: 
> > 003506f0
> >   [  354.324717] CR2: 7fd5341fca50 CR3: 002c27a22000 CR4: 
> > 003506f0
> >   [  354.331859] Call Trace:
> >   [  354.334320]  
> >   [  354.336433]  ? __flush_work.isra.0+0x23a/0x250
> >   [  354.340891]  ? __warn+0x81/0x130
> >   [  354.344139]  ? __flush_work.isra.0+0x23a/0x250
> >   [  354.348594]  ? report_bug+0x171/0x1a0
> >   [  354.352279]  ? handle_bug+0x3c/0x80
> >   [  354.355787]  ? exc_invalid_op+0x17/0x70
> >   [  354.359635]  ? asm_exc_invalid_op+0x1a/0x20
> >   [  354.363844]  ? __flush_work.isra.0+0x23a/0x250
> >   [  354.368307]  ? srso_return_thunk+0x5/0x5f
> >   [  354.372331]  ? srso_return_thunk+0x5/0x5f
> >   [  354.376351]  ? desc_read_finalized_seq+0x1f/0x70
> >   [  354.380982]  ? srso_return_thunk+0x5/0x5f
> >   [  354.385011]  ? _prb_read_valid+0x20e/0x280
> >   [  354.389130]  __cancel_work_timer+0xd3/0x160
> >   [  354.39]  drm_sched_stop+0x46/0x1f0 [gpu_sched]
> >   [  354.398143]  amdgpu_device_gpu_recover+0x318/0xca0 [amdgpu]
> >   [  354.403995]  ? __drm_err+0x1/0x70 [drm]
> >   [  354.407884]  amdgpu_job_timedout+0x151/0x240 [amdgpu]
> >   [  354.413279]  drm_sched_job_timedout+0x76/0x100 [gpu_sched]
> >   [  354.418787]  process_one_work+0x174/0x340
> >   [  354.422816]  worker_thread+0x27b/0x3a0
> >   [  354.426586]  ? __pfx_worker_thread+0x10/0x10
> >   [  354.430874]  kthread+0xe8/0x120
> >   [  354.434030]  ? __pfx_kthread+0x10/0x10
> >   [  354.437790]  ret_from_fork+0x34/0x50
> >   [  354.441377]  ? __pfx_kthread+0x10/0x10
> >   [  354.445139]  ret_from_fork_asm+0x1b/0x30
> >   [  354.449079]  
> >   [  354.451285] ---[ end trace  ]---
> >   [  354.455917] BUG: kernel NULL pointer dereference, address: 
> > 0008
> >   [  354.462883] #PF: supervisor read access in kernel mode
> >   [  354.468029] #PF: error_code(0x) - not-present page
> >   [  354.473167] PGD 0 P4D 0
> >   [  354.475705] Oops:  [#1] PREEMPT SMP NOPTI
> >   [  354.4800

Re: [PATCH] drm/amdkfd: Add cache line sizes to KFD topology

[Felix Kuehling]

On 2024-01-19 21:21, Joseph Greathouse wrote:

The KFD topology includes cache line size, but we have not been
filling that information out unless we are parsing a CRAT table.
Fill in this information for the devices where we have cache
information structs, and pipe this information to the topology
sysfs files.

Signed-off-by: Joseph Greathouse


Looks good to me in general. I can't be sure about the correctness of 
the information. Some observations:


 * Cache line sizes seem to be 64 or 128
 * On GFXv9 parts cache line sizes are 64, except on Aldebaran, L2 data
   cache lines are 128
 * On various Navis, most cache lines are 128 except L1 scalar data and
   instruction caches as well as L3 cache
 * You fixed L1 scalar data and instruction cache sizes for Carrizo.
   Was that intentional?

If that sounds correct and how it's meant to be, you can add my

Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 93 ++-
  drivers/gpu/drm/amd/amdkfd/kfd_crat.h |  1 +
  drivers/gpu/drm/amd/amdkfd/kfd_topology.c |  2 +
  3 files changed, 94 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index cd8e459201f1..002b08fa632f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -55,6 +55,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = {
/* TCP L1 Cache per CU */
.cache_size = 16,
.cache_level = 1,
+   .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -64,6 +65,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = {
/* Scalar L1 Instruction Cache (in SQC module) per bank */
.cache_size = 16,
.cache_level = 1,
+   .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_INST_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -73,6 +75,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = {
/* Scalar L1 Data Cache (in SQC module) per bank */
.cache_size = 8,
.cache_level = 1,
+   .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -88,6 +91,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
/* TCP L1 Cache per CU */
.cache_size = 16,
.cache_level = 1,
+   .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -95,8 +99,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
},
{
/* Scalar L1 Instruction Cache (in SQC module) per bank */
-   .cache_size = 8,
+   .cache_size = 32,
.cache_level = 1,
+   .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_INST_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -104,8 +109,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
},
{
/* Scalar L1 Data Cache (in SQC module) per bank. */
-   .cache_size = 4,
+   .cache_size = 16,
.cache_level = 1,
+   .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -135,6 +141,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
/* TCP L1 Cache per CU */
.cache_size = 16,
.cache_level = 1,
+   .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_DATA_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -144,6 +151,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
/* Scalar L1 Instruction Cache per SQC */
.cache_size = 32,
.cache_level = 1,
+   .cache_line_size = 64,
.flags = (CRAT_CACHE_FLAGS_ENABLED |
CRAT_CACHE_FLAGS_INST_CACHE |
CRAT_CACHE_FLAGS_SIMD_CACHE),
@@ -153,6 +161,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
/* Scalar L1 Data Cache per SQC */
.cache_size = 16,
.cache_le

[PATCH 1/2] drm/amdgpu/gfx10: set UNORD_DISPATCH in compute MQDs

[Alex Deucher]

This needs to be set to 1 to avoid a potential deadlock in
the GC 10.x and newer.  On GC 9.x and older, this needs
to be set to 0.  This can lead to hangs in some mixed
graphics and compute workloads.  Updated firmware is also
required for AQL.

Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 420c82b54650..be4d5c1e826f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6589,7 +6589,7 @@ static int gfx_v10_0_compute_mqd_init(struct 
amdgpu_device *adev, void *m,
 #ifdef __BIG_ENDIAN
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
 #endif
-   tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
+   tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
prop->allow_tunneling);
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
index 8b7fed913526..22cbfa1bdadd 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
@@ -170,6 +170,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
m->cp_hqd_pq_control |=
ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
+   m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
 
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
-- 
2.42.0

[PATCH 2/2] drm/amdgpu/gfx11: set UNORD_DISPATCH in compute MQDs

[Alex Deucher]

This needs to be set to 1 to avoid a potential deadlock in
the GC 10.x and newer.  On GC 9.x and older, this needs
to be set to 0. This can lead to hangs in some mixed
graphics and compute workloads. Updated firmware is also
required for AQL.

Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c   | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 043eff309100..c1e10760 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -3846,7 +3846,7 @@ static int gfx_v11_0_compute_mqd_init(struct 
amdgpu_device *adev, void *m,
(order_base_2(prop->queue_size / 4) - 1));
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
(order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
-   tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
+   tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
prop->allow_tunneling);
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
index 15277f1d5cf0..d722cbd31783 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
@@ -224,6 +224,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
m->cp_hqd_pq_control |=
ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
+   m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
 
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
-- 
2.42.0

Re: [PATCH] drm/amdgpu/pptable: convert some variable sized arrays to [] style

[Christian König]

Am 22.01.24 um 17:00 schrieb Alex Deucher:

Replace [1] with [].  Silences UBSAN warnings.

Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2039926
Signed-off-by: Alex Deucher 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/include/pptable.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/pptable.h 
b/drivers/gpu/drm/amd/include/pptable.h
index ef3feb0b6674..2e8e6c9875f6 100644
--- a/drivers/gpu/drm/amd/include/pptable.h
+++ b/drivers/gpu/drm/amd/include/pptable.h
@@ -658,7 +658,7 @@ typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record
  
  typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{

  UCHAR numEntries;
-ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1];
+ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[];
  }ATOM_PPLIB_SAMClk_Voltage_Limit_Table;
  
  typedef struct _ATOM_PPLIB_SAMU_Table

[PATCH] drm/amdgpu/pptable: convert some variable sized arrays to [] style

[Alex Deucher]

Replace [1] with [].  Silences UBSAN warnings.

Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2039926
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/include/pptable.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/pptable.h 
b/drivers/gpu/drm/amd/include/pptable.h
index ef3feb0b6674..2e8e6c9875f6 100644
--- a/drivers/gpu/drm/amd/include/pptable.h
+++ b/drivers/gpu/drm/amd/include/pptable.h
@@ -658,7 +658,7 @@ typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record
 
 typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{
 UCHAR numEntries;
-ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1];
+ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[];
 }ATOM_PPLIB_SAMClk_Voltage_Limit_Table;
 
 typedef struct _ATOM_PPLIB_SAMU_Table
-- 
2.42.0

Re: [PATCH v2 2/2] drm/amdgpu: Implement check_async_props for planes

[Harry Wentland]

On 2024-01-19 13:25, Ville Syrjälä wrote:

On Fri, Jan 19, 2024 at 03:12:35PM -0300, André Almeida wrote:

AMD GPUs can do async flips with changes on more properties than just
the FB ID, so implement a custom check_async_props for AMD planes.

Allow amdgpu to do async flips with IN_FENCE_ID and FB_DAMAGE_CLIPS
properties. For userspace to check if a driver support this two
properties, the strategy for now is to use TEST_ONLY commits.

Signed-off-by: André Almeida 
---
v2: Drop overlay plane option for now

  .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   | 29 +++
  1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 116121e647ca..7afe8c1b62d4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -25,6 +25,7 @@
   */
  
  #include 

+#include 
  #include 
  #include 
  #include 
@@ -1430,6 +1431,33 @@ static void 
amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane,
drm_atomic_helper_plane_destroy_state(plane, state);
  }
  
+static int amdgpu_dm_plane_check_async_props(struct drm_property *prop,

+ struct drm_plane *plane,
+ struct drm_plane_state *plane_state,
+ struct drm_mode_object *obj,
+ u64 prop_value, u64 old_val)
+{
+   struct drm_mode_config *config = &plane->dev->mode_config;
+   int ret;
+
+   if (prop != config->prop_fb_id &&
+   prop != config->prop_in_fence_fd &&


IN_FENCE should just be allowed always.


+   prop != config->prop_fb_damage_clips) {


This seems a bit dubious to me. How is amdgpu using the damage
information during async flips?


Yeah, I'm also not sure this is right. Has anyone tested this
with a PSR SU panel?

Harry




+   ret = drm_atomic_plane_get_property(plane, plane_state,
+   prop, &old_val);
+   return drm_atomic_check_prop_changes(ret, old_val, prop_value, 
prop);
+   }
+
+   if (plane_state->plane->type != DRM_PLANE_TYPE_PRIMARY) {
+   drm_dbg_atomic(prop->dev,
+  "[OBJECT:%d] Only primary planes can be changed 
during async flip\n",
+  obj->id);
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
  static const struct drm_plane_funcs dm_plane_funcs = {
.update_plane   = drm_atomic_helper_update_plane,
.disable_plane  = drm_atomic_helper_disable_plane,
@@ -1438,6 +1466,7 @@ static const struct drm_plane_funcs dm_plane_funcs = {
.atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state,
.atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state,
.format_mod_supported = amdgpu_dm_plane_format_mod_supported,
+   .check_async_props = amdgpu_dm_plane_check_async_props,
  };
  
  int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,

--
2.43.0

Re: [PATCH] drm/amdkfd: Add cache line sizes to KFD topology

[Alex Deucher]

On Fri, Jan 19, 2024 at 9:46 PM Joseph Greathouse
 wrote:
>
> The KFD topology includes cache line size, but we have not been
> filling that information out unless we are parsing a CRAT table.
> Fill in this information for the devices where we have cache
> information structs, and pipe this information to the topology
> sysfs files.
>
> Signed-off-by: Joseph Greathouse 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 93 ++-
>  drivers/gpu/drm/amd/amdkfd/kfd_crat.h |  1 +
>  drivers/gpu/drm/amd/amdkfd/kfd_topology.c |  2 +
>  3 files changed, 94 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> index cd8e459201f1..002b08fa632f 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> @@ -55,6 +55,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = {
> /* TCP L1 Cache per CU */
> .cache_size = 16,
> .cache_level = 1,
> +   .cache_line_size = 64,
> .flags = (CRAT_CACHE_FLAGS_ENABLED |
> CRAT_CACHE_FLAGS_DATA_CACHE |
> CRAT_CACHE_FLAGS_SIMD_CACHE),
> @@ -64,6 +65,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = {
> /* Scalar L1 Instruction Cache (in SQC module) per bank */
> .cache_size = 16,
> .cache_level = 1,
> +   .cache_line_size = 64,
> .flags = (CRAT_CACHE_FLAGS_ENABLED |
> CRAT_CACHE_FLAGS_INST_CACHE |
> CRAT_CACHE_FLAGS_SIMD_CACHE),
> @@ -73,6 +75,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = {
> /* Scalar L1 Data Cache (in SQC module) per bank */
> .cache_size = 8,
> .cache_level = 1,
> +   .cache_line_size = 64,
> .flags = (CRAT_CACHE_FLAGS_ENABLED |
> CRAT_CACHE_FLAGS_DATA_CACHE |
> CRAT_CACHE_FLAGS_SIMD_CACHE),
> @@ -88,6 +91,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
> /* TCP L1 Cache per CU */
> .cache_size = 16,
> .cache_level = 1,
> +   .cache_line_size = 64,
> .flags = (CRAT_CACHE_FLAGS_ENABLED |
> CRAT_CACHE_FLAGS_DATA_CACHE |
> CRAT_CACHE_FLAGS_SIMD_CACHE),
> @@ -95,8 +99,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
> },
> {
> /* Scalar L1 Instruction Cache (in SQC module) per bank */
> -   .cache_size = 8,
> +   .cache_size = 32,
> .cache_level = 1,
> +   .cache_line_size = 64,
> .flags = (CRAT_CACHE_FLAGS_ENABLED |
> CRAT_CACHE_FLAGS_INST_CACHE |
> CRAT_CACHE_FLAGS_SIMD_CACHE),
> @@ -104,8 +109,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
> },
> {
> /* Scalar L1 Data Cache (in SQC module) per bank. */
> -   .cache_size = 4,
> +   .cache_size = 16,
> .cache_level = 1,
> +   .cache_line_size = 64,
> .flags = (CRAT_CACHE_FLAGS_ENABLED |
> CRAT_CACHE_FLAGS_DATA_CACHE |
> CRAT_CACHE_FLAGS_SIMD_CACHE),
> @@ -135,6 +141,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
> /* TCP L1 Cache per CU */
> .cache_size = 16,
> .cache_level = 1,
> +   .cache_line_size = 64,
> .flags = (CRAT_CACHE_FLAGS_ENABLED |
> CRAT_CACHE_FLAGS_DATA_CACHE |
> CRAT_CACHE_FLAGS_SIMD_CACHE),
> @@ -144,6 +151,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
> /* Scalar L1 Instruction Cache per SQC */
> .cache_size = 32,
> .cache_level = 1,
> +   .cache_line_size = 64,
> .flags = (CRAT_CACHE_FLAGS_ENABLED |
> CRAT_CACHE_FLAGS_INST_CACHE |
> CRAT_CACHE_FLAGS_SIMD_CACHE),
> @@ -153,6 +161,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
> /* Scalar L1 Data Cache per SQC */
> .cache_size = 16,
> .cache_level = 1,
> +   .cache_line_size = 64,
> .flags = (CRAT_CACHE_FLAGS_ENABLED |
> CRAT_CACHE_FLAGS_DATA_CACHE |
> CRAT_CACHE_FLAGS_SIMD_CACHE),
> @@ -162,6 +171,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = {
> /* L2 

[PATCH AUTOSEL 4.19 22/23] drm/amdgpu: Let KFD sync with VM fences

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit ec9ba4821fa52b5efdbc4cdf0a77497990655231 ]

Change the rules for amdgpu_sync_resv to let KFD synchronize with VM
fences on page table reservations. This fixes intermittent memory
corruption after evictions when using amdgpu_vm_handle_moved to update
page tables for VM mappings managed through render nodes.

Signed-off-by: Felix Kuehling 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 2d6f5ec77a68..5eb8f93c7022 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -219,7 +219,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
 */
fence_owner = amdgpu_sync_get_owner(f);
if (fence_owner == AMDGPU_FENCE_OWNER_KFD &&
-   owner != AMDGPU_FENCE_OWNER_UNDEFINED)
+   owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
+   owner != AMDGPU_FENCE_OWNER_KFD)
continue;
 
if (amdgpu_sync_same_dev(adev, f)) {
-- 
2.43.0

[PATCH AUTOSEL 4.19 21/23] drm/amd/display: make flip_timestamp_in_us a 64-bit variable

[Sasha Levin]

From: Josip Pavic 

[ Upstream commit 6fb12518ca58412dc51054e2a7400afb41328d85 ]

[Why]
This variable currently overflows after about 71 minutes. This doesn't
cause any known functional issues but it does make debugging more
difficult.

[How]
Make it a 64-bit variable.

Reviewed-by: Aric Cyr 
Acked-by: Wayne Lin 
Signed-off-by: Josip Pavic 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index b789cb2b354b..c96ff10365d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -357,7 +357,7 @@ union dc_tiling_info {
} gfx8;
 
struct {
-   unsigned int num_pipes;
+   unsigned long long num_pipes;
unsigned int num_banks;
unsigned int pipe_interleave;
unsigned int num_shader_engines;
-- 
2.43.0

[PATCH AUTOSEL 4.19 23/23] drm/amdgpu: Drop 'fence' check in 'to_amdgpu_amdkfd_fence()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit bf2ad4fb8adca89374b54b225d494e0b1956dbea ]

Return value of container_of(...) can't be null, so null check is not
required for 'fence'. Hence drop its NULL check.

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c:93 to_amdgpu_amdkfd_fence() 
warn: can 'fence' even be NULL?

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
index 574c1181ae9a..75e4f1abb4c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
@@ -88,7 +88,7 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct 
dma_fence *f)
return NULL;
 
fence = container_of(f, struct amdgpu_amdkfd_fence, base);
-   if (fence && f->ops == &amdkfd_fence_ops)
+   if (f->ops == &amdkfd_fence_ops)
return fence;
 
return NULL;
-- 
2.43.0

[PATCH AUTOSEL 5.4 24/24] drm/amdgpu: Drop 'fence' check in 'to_amdgpu_amdkfd_fence()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit bf2ad4fb8adca89374b54b225d494e0b1956dbea ]

Return value of container_of(...) can't be null, so null check is not
required for 'fence'. Hence drop its NULL check.

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c:93 to_amdgpu_amdkfd_fence() 
warn: can 'fence' even be NULL?

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
index 3107b9575929..eef7517c9d24 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
@@ -88,7 +88,7 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct 
dma_fence *f)
return NULL;
 
fence = container_of(f, struct amdgpu_amdkfd_fence, base);
-   if (fence && f->ops == &amdkfd_fence_ops)
+   if (f->ops == &amdkfd_fence_ops)
return fence;
 
return NULL;
-- 
2.43.0

[PATCH AUTOSEL 5.4 23/24] drm/amdgpu: Let KFD sync with VM fences

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit ec9ba4821fa52b5efdbc4cdf0a77497990655231 ]

Change the rules for amdgpu_sync_resv to let KFD synchronize with VM
fences on page table reservations. This fixes intermittent memory
corruption after evictions when using amdgpu_vm_handle_moved to update
page tables for VM mappings managed through render nodes.

Signed-off-by: Felix Kuehling 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 95e5e93edd18..7e840e560513 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -218,7 +218,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
 */
fence_owner = amdgpu_sync_get_owner(f);
if (fence_owner == AMDGPU_FENCE_OWNER_KFD &&
-   owner != AMDGPU_FENCE_OWNER_UNDEFINED)
+   owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
+   owner != AMDGPU_FENCE_OWNER_KFD)
continue;
 
if (amdgpu_sync_same_dev(adev, f)) {
-- 
2.43.0

[PATCH AUTOSEL 5.4 22/24] drm/amd/display: make flip_timestamp_in_us a 64-bit variable

[Sasha Levin]

From: Josip Pavic 

[ Upstream commit 6fb12518ca58412dc51054e2a7400afb41328d85 ]

[Why]
This variable currently overflows after about 71 minutes. This doesn't
cause any known functional issues but it does make debugging more
difficult.

[How]
Make it a 64-bit variable.

Reviewed-by: Aric Cyr 
Acked-by: Wayne Lin 
Signed-off-by: Josip Pavic 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 0b8700a8a94a..c6281d4a18ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -423,7 +423,7 @@ struct dc_cursor_position {
 };
 
 struct dc_cursor_mi_param {
-   unsigned int pixel_clk_khz;
+   unsigned long long pixel_clk_khz;
unsigned int ref_clk_khz;
struct rect viewport;
struct fixed31_32 h_scale_ratio;
-- 
2.43.0

[PATCH AUTOSEL 5.4 06/24] drm/amd/display: Fix writeback_info never got updated

[Sasha Levin]

From: Alex Hung 

[ Upstream commit 8a30c36e15f38c9f23778babcd368144c7d8 ]

[WHY]
wb_enabled field is set to false before it is used, and the following
code will never be executed.

[HOW]
Setting wb_enable to false after all removal work is completed.

Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 71b10b45a9b9..6e2b7bb47f38 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -448,18 +448,13 @@ bool dc_stream_remove_writeback(struct dc *dc,
return false;
}
 
-// stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
-   for (i = 0; i < stream->num_wb_info; i++) {
-   /*dynamic update*/
-   if (stream->writeback_info[i].wb_enabled &&
-   stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst) {
-   stream->writeback_info[i].wb_enabled = false;
-   }
-   }
-
/* remove writeback info for disabled writeback pipes from stream */
for (i = 0, j = 0; i < stream->num_wb_info; i++) {
if (stream->writeback_info[i].wb_enabled) {
+
+   if (stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst)
+   stream->writeback_info[i].wb_enabled = false;
+
if (i != j)
/* trim the array */
stream->writeback_info[j] = 
stream->writeback_info[i];
-- 
2.43.0

[PATCH AUTOSEL 5.10 28/28] drm/amdgpu: Drop 'fence' check in 'to_amdgpu_amdkfd_fence()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit bf2ad4fb8adca89374b54b225d494e0b1956dbea ]

Return value of container_of(...) can't be null, so null check is not
required for 'fence'. Hence drop its NULL check.

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c:93 to_amdgpu_amdkfd_fence() 
warn: can 'fence' even be NULL?

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
index 3107b9575929..eef7517c9d24 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
@@ -88,7 +88,7 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct 
dma_fence *f)
return NULL;
 
fence = container_of(f, struct amdgpu_amdkfd_fence, base);
-   if (fence && f->ops == &amdkfd_fence_ops)
+   if (f->ops == &amdkfd_fence_ops)
return fence;
 
return NULL;
-- 
2.43.0

[PATCH AUTOSEL 5.10 27/28] drm/amdgpu: Let KFD sync with VM fences

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit ec9ba4821fa52b5efdbc4cdf0a77497990655231 ]

Change the rules for amdgpu_sync_resv to let KFD synchronize with VM
fences on page table reservations. This fixes intermittent memory
corruption after evictions when using amdgpu_vm_handle_moved to update
page tables for VM mappings managed through render nodes.

Signed-off-by: Felix Kuehling 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 8ea6c49529e7..6a22bc41c205 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -241,7 +241,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct 
amdgpu_sync *sync,
 
/* Never sync to VM updates either. */
if (fence_owner == AMDGPU_FENCE_OWNER_VM &&
-   owner != AMDGPU_FENCE_OWNER_UNDEFINED)
+   owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
+   owner != AMDGPU_FENCE_OWNER_KFD)
continue;
 
/* Ignore fences depending on the sync mode */
-- 
2.43.0

[PATCH AUTOSEL 5.10 26/28] drm/amd/display: make flip_timestamp_in_us a 64-bit variable

[Sasha Levin]

From: Josip Pavic 

[ Upstream commit 6fb12518ca58412dc51054e2a7400afb41328d85 ]

[Why]
This variable currently overflows after about 71 minutes. This doesn't
cause any known functional issues but it does make debugging more
difficult.

[How]
Make it a 64-bit variable.

Reviewed-by: Aric Cyr 
Acked-by: Wayne Lin 
Signed-off-by: Josip Pavic 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 1a87bc3da826..b36d4c5d0eca 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -426,7 +426,7 @@ struct dc_cursor_position {
 };
 
 struct dc_cursor_mi_param {
-   unsigned int pixel_clk_khz;
+   unsigned long long pixel_clk_khz;
unsigned int ref_clk_khz;
struct rect viewport;
struct fixed31_32 h_scale_ratio;
-- 
2.43.0

[PATCH AUTOSEL 5.10 09/28] drm/amd/display: Fix writeback_info never got updated

[Sasha Levin]

From: Alex Hung 

[ Upstream commit 8a30c36e15f38c9f23778babcd368144c7d8 ]

[WHY]
wb_enabled field is set to false before it is used, and the following
code will never be executed.

[HOW]
Setting wb_enable to false after all removal work is completed.

Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 8206c6edba74..c54691166871 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -481,18 +481,13 @@ bool dc_stream_remove_writeback(struct dc *dc,
return false;
}
 
-// stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
-   for (i = 0; i < stream->num_wb_info; i++) {
-   /*dynamic update*/
-   if (stream->writeback_info[i].wb_enabled &&
-   stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst) {
-   stream->writeback_info[i].wb_enabled = false;
-   }
-   }
-
/* remove writeback info for disabled writeback pipes from stream */
for (i = 0, j = 0; i < stream->num_wb_info; i++) {
if (stream->writeback_info[i].wb_enabled) {
+
+   if (stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst)
+   stream->writeback_info[i].wb_enabled = false;
+
if (i != j)
/* trim the array */
stream->writeback_info[j] = 
stream->writeback_info[i];
-- 
2.43.0

[PATCH AUTOSEL 5.10 07/28] drm/amd/display: Fix tiled display misalignment

[Sasha Levin]

From: Meenakshikumar Somasundaram 

[ Upstream commit c4b8394e76adba4f50a3c2696c75b214a291e24a ]

[Why]
When otg workaround is applied during clock update, otgs of
tiled display went out of sync.

[How]
To call dc_trigger_sync() after clock update to sync otgs again.

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Hamza Mahfooz 
Signed-off-by: Meenakshikumar Somasundaram 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 36a9e9c84ed4..272252cd0500 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1440,6 +1440,10 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
wait_for_no_pipes_pending(dc, context);
/* pplib is notified if disp_num changed */
dc->hwss.optimize_bandwidth(dc, context);
+   /* Need to do otg sync again as otg could be out of sync due to 
otg
+* workaround applied during clock update
+*/
+   dc_trigger_sync(dc, context);
}
 
context->stream_mask = get_stream_mask(dc, context);
-- 
2.43.0

[PATCH AUTOSEL 5.15 33/35] drm/amdgpu: Let KFD sync with VM fences

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit ec9ba4821fa52b5efdbc4cdf0a77497990655231 ]

Change the rules for amdgpu_sync_resv to let KFD synchronize with VM
fences on page table reservations. This fixes intermittent memory
corruption after evictions when using amdgpu_vm_handle_moved to update
page tables for VM mappings managed through render nodes.

Signed-off-by: Felix Kuehling 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 862eb3c1c4c5..494466893486 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -208,7 +208,8 @@ static bool amdgpu_sync_test_fence(struct amdgpu_device 
*adev,
 
/* Never sync to VM updates either. */
if (fence_owner == AMDGPU_FENCE_OWNER_VM &&
-   owner != AMDGPU_FENCE_OWNER_UNDEFINED)
+   owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
+   owner != AMDGPU_FENCE_OWNER_KFD)
return false;
 
/* Ignore fences depending on the sync mode */
-- 
2.43.0

[PATCH AUTOSEL 5.15 34/35] drm/amdgpu: Drop 'fence' check in 'to_amdgpu_amdkfd_fence()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit bf2ad4fb8adca89374b54b225d494e0b1956dbea ]

Return value of container_of(...) can't be null, so null check is not
required for 'fence'. Hence drop its NULL check.

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c:93 to_amdgpu_amdkfd_fence() 
warn: can 'fence' even be NULL?

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
index 1d0dbff87d3f..fb66e888ab3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
@@ -90,7 +90,7 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct 
dma_fence *f)
return NULL;
 
fence = container_of(f, struct amdgpu_amdkfd_fence, base);
-   if (fence && f->ops == &amdkfd_fence_ops)
+   if (f->ops == &amdkfd_fence_ops)
return fence;
 
return NULL;
-- 
2.43.0

[PATCH AUTOSEL 5.15 30/35] drm/amd/display: make flip_timestamp_in_us a 64-bit variable

[Sasha Levin]

From: Josip Pavic 

[ Upstream commit 6fb12518ca58412dc51054e2a7400afb41328d85 ]

[Why]
This variable currently overflows after about 71 minutes. This doesn't
cause any known functional issues but it does make debugging more
difficult.

[How]
Make it a 64-bit variable.

Reviewed-by: Aric Cyr 
Acked-by: Wayne Lin 
Signed-off-by: Josip Pavic 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 52355fe6994c..51df38a210e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -417,7 +417,7 @@ struct dc_cursor_position {
 };
 
 struct dc_cursor_mi_param {
-   unsigned int pixel_clk_khz;
+   unsigned long long pixel_clk_khz;
unsigned int ref_clk_khz;
struct rect viewport;
struct fixed31_32 h_scale_ratio;
-- 
2.43.0

[PATCH AUTOSEL 5.15 26/35] drm/amdgpu: fix ftrace event amdgpu_bo_move always move on same heap

[Sasha Levin]

From: "Wang, Beyond" 

[ Upstream commit 94aeb4117343d072e3a35b9595bcbfc0058ee724 ]

Issue: during evict or validate happened on amdgpu_bo, the 'from' and
'to' is always same in ftrace event of amdgpu_bo_move

where calling the 'trace_amdgpu_bo_move', the comment says move_notify
is called before move happens, but actually it is called after move
happens, here the new_mem is same as bo->resource

Fix: move trace_amdgpu_bo_move from move_notify to amdgpu_bo_move

Signed-off-by: Wang, Beyond 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 13 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  4 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  5 +++--
 3 files changed, 5 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 8a0b652da4f4..5d95594a1753 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1236,19 +1236,15 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void 
*buffer,
  * amdgpu_bo_move_notify - notification about a memory move
  * @bo: pointer to a buffer object
  * @evict: if this move is evicting the buffer from the graphics address space
- * @new_mem: new information of the bufer object
  *
  * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
  * bookkeeping.
  * TTM driver callback which is called when ttm moves a buffer.
  */
-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
-  bool evict,
-  struct ttm_resource *new_mem)
+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)
 {
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct amdgpu_bo *abo;
-   struct ttm_resource *old_mem = bo->resource;
 
if (!amdgpu_bo_is_amdgpu_bo(bo))
return;
@@ -1265,13 +1261,6 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
/* remember the eviction */
if (evict)
atomic64_inc(&adev->num_evictions);
-
-   /* update statistics */
-   if (!new_mem)
-   return;
-
-   /* move_notify is called before move happens */
-   trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 }
 
 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index dc5b889828d9..0969669f1d4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -313,9 +313,7 @@ int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void 
*metadata,
 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
   size_t buffer_size, uint32_t *metadata_size,
   uint64_t *flags);
-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
-  bool evict,
-  struct ttm_resource *new_mem);
+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict);
 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 51c76d6322c9..b06fb1fa411b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -554,10 +554,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, 
bool evict,
return r;
}
 
+   trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 out:
/* update statistics */
atomic64_add(bo->base.size, &adev->num_bytes_moved);
-   amdgpu_bo_move_notify(bo, evict, new_mem);
+   amdgpu_bo_move_notify(bo, evict);
return 0;
 }
 
@@ -1480,7 +1481,7 @@ static int amdgpu_ttm_access_memory(struct 
ttm_buffer_object *bo,
 static void
 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
 {
-   amdgpu_bo_move_notify(bo, false, NULL);
+   amdgpu_bo_move_notify(bo, false);
 }
 
 static struct ttm_device_funcs amdgpu_bo_driver = {
-- 
2.43.0

[PATCH AUTOSEL 5.15 09/35] drm/amd/display: Fix writeback_info never got updated

[Sasha Levin]

From: Alex Hung 

[ Upstream commit 8a30c36e15f38c9f23778babcd368144c7d8 ]

[WHY]
wb_enabled field is set to false before it is used, and the following
code will never be executed.

[HOW]
Setting wb_enable to false after all removal work is completed.

Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 5dd57cf170f5..b7b72fc2cb37 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -509,18 +509,13 @@ bool dc_stream_remove_writeback(struct dc *dc,
return false;
}
 
-// stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
-   for (i = 0; i < stream->num_wb_info; i++) {
-   /*dynamic update*/
-   if (stream->writeback_info[i].wb_enabled &&
-   stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst) {
-   stream->writeback_info[i].wb_enabled = false;
-   }
-   }
-
/* remove writeback info for disabled writeback pipes from stream */
for (i = 0, j = 0; i < stream->num_wb_info; i++) {
if (stream->writeback_info[i].wb_enabled) {
+
+   if (stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst)
+   stream->writeback_info[i].wb_enabled = false;
+
if (i != j)
/* trim the array */
stream->writeback_info[j] = 
stream->writeback_info[i];
-- 
2.43.0

[PATCH AUTOSEL 5.15 07/35] drm/amd/display: Fix tiled display misalignment

[Sasha Levin]

From: Meenakshikumar Somasundaram 

[ Upstream commit c4b8394e76adba4f50a3c2696c75b214a291e24a ]

[Why]
When otg workaround is applied during clock update, otgs of
tiled display went out of sync.

[How]
To call dc_trigger_sync() after clock update to sync otgs again.

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Hamza Mahfooz 
Signed-off-by: Meenakshikumar Somasundaram 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 3919e75fec16..ef151a1bc31c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1680,6 +1680,10 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
wait_for_no_pipes_pending(dc, context);
/* pplib is notified if disp_num changed */
dc->hwss.optimize_bandwidth(dc, context);
+   /* Need to do otg sync again as otg could be out of sync due to 
otg
+* workaround applied during clock update
+*/
+   dc_trigger_sync(dc, context);
}
 
if (dc->ctx->dce_version >= DCE_VERSION_MAX)
-- 
2.43.0

[PATCH AUTOSEL 6.1 48/53] drm/amdgpu: Drop 'fence' check in 'to_amdgpu_amdkfd_fence()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit bf2ad4fb8adca89374b54b225d494e0b1956dbea ]

Return value of container_of(...) can't be null, so null check is not
required for 'fence'. Hence drop its NULL check.

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c:93 to_amdgpu_amdkfd_fence() 
warn: can 'fence' even be NULL?

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
index 469785d33791..1ef758ac5076 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
@@ -90,7 +90,7 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct 
dma_fence *f)
return NULL;
 
fence = container_of(f, struct amdgpu_amdkfd_fence, base);
-   if (fence && f->ops == &amdkfd_fence_ops)
+   if (f->ops == &amdkfd_fence_ops)
return fence;
 
return NULL;
-- 
2.43.0

[PATCH AUTOSEL 6.1 49/53] drm/amdkfd: Fix iterator used outside loop in 'kfd_add_peer_prop()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit b1a428b45dc7e47c7acc2ad0d08d8a6dda910c4c ]

Fix the following about iterator use:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1456 kfd_add_peer_prop() 
warn: iterator used outside loop: 'iolink3'

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 24 ---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 713f893d2530..977e13cd36e8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1510,17 +1510,19 @@ static int kfd_add_peer_prop(struct kfd_topology_device 
*kdev,
/* CPU->CPU  link*/
cpu_dev = 
kfd_topology_device_by_proximity_domain(iolink1->node_to);
if (cpu_dev) {
-   list_for_each_entry(iolink3, &cpu_dev->io_link_props, 
list)
-   if (iolink3->node_to == iolink2->node_to)
-   break;
-
-   props->weight += iolink3->weight;
-   props->min_latency += iolink3->min_latency;
-   props->max_latency += iolink3->max_latency;
-   props->min_bandwidth = min(props->min_bandwidth,
-   iolink3->min_bandwidth);
-   props->max_bandwidth = min(props->max_bandwidth,
-   iolink3->max_bandwidth);
+   list_for_each_entry(iolink3, &cpu_dev->io_link_props, 
list) {
+   if (iolink3->node_to != iolink2->node_to)
+   continue;
+
+   props->weight += iolink3->weight;
+   props->min_latency += iolink3->min_latency;
+   props->max_latency += iolink3->max_latency;
+   props->min_bandwidth = min(props->min_bandwidth,
+  
iolink3->min_bandwidth);
+   props->max_bandwidth = min(props->max_bandwidth,
+  
iolink3->max_bandwidth);
+   break;
+   }
} else {
WARN(1, "CPU node not found");
}
-- 
2.43.0

[PATCH AUTOSEL 6.1 47/53] drm/amdgpu: Fix '*fw' from request_firmware() not released in 'amdgpu_ucode_request()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit 13a1851f923d9a7a78a477497295c2dfd16ad4a4 ]

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:1404 amdgpu_ucode_request() warn: 
'*fw' from request_firmware() not released on lines: 1404.

Cc: Mario Limonciello 
Cc: Lijo Lazar 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 6e7058a2d1c8..779707f19c88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -1110,9 +1110,13 @@ int amdgpu_ucode_request(struct amdgpu_device *adev, 
const struct firmware **fw,
 
if (err)
return -ENODEV;
+
err = amdgpu_ucode_validate(*fw);
-   if (err)
+   if (err) {
dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name);
+   release_firmware(*fw);
+   *fw = NULL;
+   }
 
return err;
 }
-- 
2.43.0

[PATCH AUTOSEL 6.1 42/53] drm/amd/display: make flip_timestamp_in_us a 64-bit variable

[Sasha Levin]

From: Josip Pavic 

[ Upstream commit 6fb12518ca58412dc51054e2a7400afb41328d85 ]

[Why]
This variable currently overflows after about 71 minutes. This doesn't
cause any known functional issues but it does make debugging more
difficult.

[How]
Make it a 64-bit variable.

Reviewed-by: Aric Cyr 
Acked-by: Wayne Lin 
Signed-off-by: Josip Pavic 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 46c2b991aa10..811c117665e7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -244,7 +244,7 @@ enum pixel_format {
 #define DC_MAX_DIRTY_RECTS 3
 struct dc_flip_addrs {
struct dc_plane_address address;
-   unsigned int flip_timestamp_in_us;
+   unsigned long long flip_timestamp_in_us;
bool flip_immediate;
/* TODO: add flip duration for FreeSync */
bool triplebuffer_flips;
-- 
2.43.0

[PATCH AUTOSEL 6.1 38/53] drm/amdgpu: fix ftrace event amdgpu_bo_move always move on same heap

[Sasha Levin]

From: "Wang, Beyond" 

[ Upstream commit 94aeb4117343d072e3a35b9595bcbfc0058ee724 ]

Issue: during evict or validate happened on amdgpu_bo, the 'from' and
'to' is always same in ftrace event of amdgpu_bo_move

where calling the 'trace_amdgpu_bo_move', the comment says move_notify
is called before move happens, but actually it is called after move
happens, here the new_mem is same as bo->resource

Fix: move trace_amdgpu_bo_move from move_notify to amdgpu_bo_move

Signed-off-by: Wang, Beyond 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 13 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  4 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  5 +++--
 3 files changed, 5 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0ee7c935fba1..cde2fd2f7117 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1222,19 +1222,15 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void 
*buffer,
  * amdgpu_bo_move_notify - notification about a memory move
  * @bo: pointer to a buffer object
  * @evict: if this move is evicting the buffer from the graphics address space
- * @new_mem: new information of the bufer object
  *
  * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
  * bookkeeping.
  * TTM driver callback which is called when ttm moves a buffer.
  */
-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
-  bool evict,
-  struct ttm_resource *new_mem)
+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)
 {
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct amdgpu_bo *abo;
-   struct ttm_resource *old_mem = bo->resource;
 
if (!amdgpu_bo_is_amdgpu_bo(bo))
return;
@@ -1251,13 +1247,6 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
/* remember the eviction */
if (evict)
atomic64_inc(&adev->num_evictions);
-
-   /* update statistics */
-   if (!new_mem)
-   return;
-
-   /* move_notify is called before move happens */
-   trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 }
 
 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 6dcd7bab42fb..2ada421e79e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -312,9 +312,7 @@ int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void 
*metadata,
 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
   size_t buffer_size, uint32_t *metadata_size,
   uint64_t *flags);
-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
-  bool evict,
-  struct ttm_resource *new_mem);
+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict);
 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 10469f20a10c..158b791883f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -555,10 +555,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, 
bool evict,
return r;
}
 
+   trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 out:
/* update statistics */
atomic64_add(bo->base.size, &adev->num_bytes_moved);
-   amdgpu_bo_move_notify(bo, evict, new_mem);
+   amdgpu_bo_move_notify(bo, evict);
return 0;
 }
 
@@ -1503,7 +1504,7 @@ static int amdgpu_ttm_access_memory(struct 
ttm_buffer_object *bo,
 static void
 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
 {
-   amdgpu_bo_move_notify(bo, false, NULL);
+   amdgpu_bo_move_notify(bo, false);
 }
 
 static struct ttm_device_funcs amdgpu_bo_driver = {
-- 
2.43.0

[PATCH AUTOSEL 6.1 46/53] drm/amd/display: Fixing stream allocation regression

[Sasha Levin]

From: Relja Vojvodic 

[ Upstream commit 292c2116b2ae84c7e799ae340981e60551b18f5e ]

For certain dual display configs that had one display using a 1080p
mode, the DPM level used to drive the configs regressed from DPM 0 to
DPM 3. This was caused by a missing check that should have only limited
the pipe segments on non-phantom pipes. This caused issues with detile
buffer allocation, which dissallow subvp from being used

Tested-by: Daniel Wheeler 
Reviewed-by: Dillon Varone 
Reviewed-by: Martin Leung 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Relja Vojvodic 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index fa3778849db1..5e0fcb80bf36 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -216,7 +216,7 @@ bool dcn32_subvp_in_use(struct dc *dc,
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 
-   if (pipe->stream && pipe->stream->mall_stream_config.type != 
SUBVP_NONE)
+   if (pipe->stream && pipe->stream->mall_stream_config.type != 
SUBVP_PHANTOM != SUBVP_NONE)
return true;
}
return false;
-- 
2.43.0

[PATCH AUTOSEL 6.1 45/53] drm/amdgpu: Let KFD sync with VM fences

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit ec9ba4821fa52b5efdbc4cdf0a77497990655231 ]

Change the rules for amdgpu_sync_resv to let KFD synchronize with VM
fences on page table reservations. This fixes intermittent memory
corruption after evictions when using amdgpu_vm_handle_moved to update
page tables for VM mappings managed through render nodes.

Signed-off-by: Felix Kuehling 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 090e66a1b284..54bdbd83a8cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -191,7 +191,8 @@ static bool amdgpu_sync_test_fence(struct amdgpu_device 
*adev,
 
/* Never sync to VM updates either. */
if (fence_owner == AMDGPU_FENCE_OWNER_VM &&
-   owner != AMDGPU_FENCE_OWNER_UNDEFINED)
+   owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
+   owner != AMDGPU_FENCE_OWNER_KFD)
return false;
 
/* Ignore fences depending on the sync mode */
-- 
2.43.0

[PATCH AUTOSEL 6.1 44/53] drm/amdgpu: Fix ecc irq enable/disable unpaired

[Sasha Levin]

From: "Stanley.Yang" 

[ Upstream commit a32c6f7f5737cc7e31cd7ad5133f0d96fca12ea6 ]

The ecc_irq is disabled while GPU mode2 reset suspending process,
but not be enabled during GPU mode2 reset resume process.

Changed from V1:
only do sdma/gfx ras_late_init in aldebaran_mode2_restore_ip
delete amdgpu_ras_late_resume function

Changed from V2:
check umc ras supported before put ecc_irq

Signed-off-by: Stanley.Yang 
Reviewed-by: Tao Zhou 
Reviewed-by: Hawking Zhang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/aldebaran.c | 26 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |  4 
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c |  5 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  4 
 4 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c 
b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
index 2b97b8a96fb4..fa6193535d48 100644
--- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
@@ -333,6 +333,7 @@ aldebaran_mode2_restore_hwcontext(struct 
amdgpu_reset_control *reset_ctl,
 {
struct list_head *reset_device_list = reset_context->reset_device_list;
struct amdgpu_device *tmp_adev = NULL;
+   struct amdgpu_ras *con;
int r;
 
if (reset_device_list == NULL)
@@ -358,7 +359,30 @@ aldebaran_mode2_restore_hwcontext(struct 
amdgpu_reset_control *reset_ctl,
 */
amdgpu_register_gpu_instance(tmp_adev);
 
-   /* Resume RAS */
+   /* Resume RAS, ecc_irq */
+   con = amdgpu_ras_get_context(tmp_adev);
+   if (!amdgpu_sriov_vf(tmp_adev) && con) {
+   if (tmp_adev->sdma.ras &&
+   tmp_adev->sdma.ras->ras_block.ras_late_init) {
+   r = 
tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev,
+   
&tmp_adev->sdma.ras->ras_block.ras_comm);
+   if (r) {
+   dev_err(tmp_adev->dev, "SDMA failed to 
execute ras_late_init! ret:%d\n", r);
+   goto end;
+   }
+   }
+
+   if (tmp_adev->gfx.ras &&
+   tmp_adev->gfx.ras->ras_block.ras_late_init) {
+   r = 
tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,
+   
&tmp_adev->gfx.ras->ras_block.ras_comm);
+   if (r) {
+   dev_err(tmp_adev->dev, "GFX failed to 
execute ras_late_init! ret:%d\n", r);
+   goto end;
+   }
+   }
+   }
+
amdgpu_ras_resume(tmp_adev);
 
/* Update PSP FW topology after reset */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index d96ee48e1706..35921b41fc27 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1144,6 +1144,10 @@ static int gmc_v10_0_hw_fini(void *handle)
 
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 
+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 7124347d2b6c..310a5607d83b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -951,6 +951,11 @@ static int gmc_v11_0_hw_fini(void *handle)
}
 
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
+
+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
+
gmc_v11_0_gart_disable(adev);
 
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 0d9e9d9dd4a1..409e3aa018f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1900,6 +1900,10 @@ static int gmc_v9_0_hw_fini(void *handle)
 
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 
+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
+
return 0;
 }
 
-- 
2.43.0

[PATCH AUTOSEL 6.1 35/53] drm/amd/display: For prefetch mode > 0, extend prefetch if possible

[Sasha Levin]

From: Alvin Lee 

[ Upstream commit dd4e4bb28843393065eed279e869fac248d03f0f ]

[Description]
For mode programming we want to extend the prefetch as much as possible
(up to oto, or as long as we can for equ) if we're not already applying
the 60us prefetch requirement. This is to avoid intermittent underflow
issues during prefetch.

The prefetch extension is applied under the following scenarios:
1. We're in prefetch mode 1 (i.e. we don't support MCLK switch in blank)
2. We're using subvp or drr methods of p-state switch, in which case we
   we don't care if prefetch takes up more of the blanking time

Mode programming typically chooses the smallest prefetch time possible
(i.e. highest bandwidth during prefetch) presumably to create margin between
p-states / c-states that happen in vblank and prefetch. Therefore we only
apply this prefetch extension when p-state in vblank is not required (UCLK
p-states take up the most vblank time).

Reviewed-by: Jun Lei 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alvin Lee 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../dc/dml/dcn32/display_mode_vba_32.c|  3 ++
 .../dc/dml/dcn32/display_mode_vba_util_32.c   | 33 +++
 .../dc/dml/dcn32/display_mode_vba_util_32.h   |  1 +
 3 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 19f55657272e..cc8c1a48c5c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -810,6 +810,8 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman

(v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||

v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= 
DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?

mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
+   
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
 > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false,
+
/* Output */
&v->DSTXAfterScaler[k],
&v->DSTYAfterScaler[k],
@@ -3291,6 +3293,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l

v->SwathHeightCThisState[k], v->TWait,

(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= 
DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?

mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
+   
mode_lib->vba.PrefetchModePerState[i][j] > 0 || 
mode_lib->vba.DRAMClockChangeRequirementFinal == false,
 
/* Output */

&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 23e4be2ad63f..7f4fc49be35c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -3418,6 +3418,7 @@ bool dml32_CalculatePrefetchSchedule(
unsigned int SwathHeightC,
double TWait,
double TPreReq,
+   bool ExtendPrefetchIfPossible,
/* Output */
double   *DSTXAfterScaler,
double   *DSTYAfterScaler,
@@ -3887,12 +3888,32 @@ bool dml32_CalculatePrefetchSchedule(
/* Clamp to oto for bandwidth calculation */
LinesForPrefetchBandwidth = dst_y_prefetch_oto;
} else {
-   *DestinationLinesForPrefetch = dst_y_prefetch_equ;
-   TimeForFetchingMetaPTE = Tvm_equ;
-   TimeForFetchingRowInVBlank = Tr0_equ;
-   *PrefetchBandwidth = prefetch_bw_equ;
-   /* Clamp to equ for bandwidth calculation */
-   LinesForPrefetchBandwidth = dst_y_prefetch_equ;
+   /* For mode programming we want to extend the prefetch 
as much as possible
+* (up to oto, or as long as we can for equ) if we're 
not already applying
+* the 60us prefetch requirement. This is to avoid 
intermittent underflow
+* issues during prefetch.
+  

[PATCH AUTOSEL 6.1 15/53] drm/amd/display: Fix writeback_info is not removed

[Sasha Levin]

From: Alex Hung 

[ Upstream commit 5b89d2ccc8466e0445a4994cb288fc009b565de5 ]

[WHY]
Counter j was not updated to present the num of writeback_info when
writeback pipes are removed.

[HOW]
update j (num of writeback info) under the correct condition.

Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 12b73b0ff19e..b59db6c95820 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -521,10 +521,11 @@ bool dc_stream_remove_writeback(struct dc *dc,
if (stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst)
stream->writeback_info[i].wb_enabled = false;
 
-   if (j < i)
-   /* trim the array */
+   /* trim the array */
+   if (j < i) {
stream->writeback_info[j] = 
stream->writeback_info[i];
-   j++;
+   j++;
+   }
}
}
stream->num_wb_info = j;
-- 
2.43.0

[PATCH AUTOSEL 6.1 14/53] drm/amd/display: Fix writeback_info never got updated

[Sasha Levin]

From: Alex Hung 

[ Upstream commit 8a30c36e15f38c9f23778babcd368144c7d8 ]

[WHY]
wb_enabled field is set to false before it is used, and the following
code will never be executed.

[HOW]
Setting wb_enable to false after all removal work is completed.

Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 556c57c390ff..12b73b0ff19e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -514,18 +514,13 @@ bool dc_stream_remove_writeback(struct dc *dc,
return false;
}
 
-// stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
-   for (i = 0; i < stream->num_wb_info; i++) {
-   /*dynamic update*/
-   if (stream->writeback_info[i].wb_enabled &&
-   stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst) {
-   stream->writeback_info[i].wb_enabled = false;
-   }
-   }
-
/* remove writeback info for disabled writeback pipes from stream */
for (i = 0, j = 0; i < stream->num_wb_info; i++) {
if (stream->writeback_info[i].wb_enabled) {
+
+   if (stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst)
+   stream->writeback_info[i].wb_enabled = false;
+
if (j < i)
/* trim the array */
stream->writeback_info[j] = 
stream->writeback_info[i];
-- 
2.43.0

[PATCH AUTOSEL 6.1 10/53] drm/amd/display: Fix tiled display misalignment

[Sasha Levin]

From: Meenakshikumar Somasundaram 

[ Upstream commit c4b8394e76adba4f50a3c2696c75b214a291e24a ]

[Why]
When otg workaround is applied during clock update, otgs of
tiled display went out of sync.

[How]
To call dc_trigger_sync() after clock update to sync otgs again.

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Hamza Mahfooz 
Signed-off-by: Meenakshikumar Somasundaram 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7a309547c2b3..f415733f1a97 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1903,6 +1903,10 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
wait_for_no_pipes_pending(dc, context);
/* pplib is notified if disp_num changed */
dc->hwss.optimize_bandwidth(dc, context);
+   /* Need to do otg sync again as otg could be out of sync due to 
otg
+* workaround applied during clock update
+*/
+   dc_trigger_sync(dc, context);
}
 
if (dc->hwss.update_dsc_pg)
-- 
2.43.0

[PATCH AUTOSEL 6.6 69/73] drm/amdgpu: apply the RV2 system aperture fix to RN/CZN as well

[Sasha Levin]

From: Alex Deucher 

[ Upstream commit 16783d8ef08448815e149e40c82fc1e1fc41ddbf ]

These chips needs the same fix.  This was previously not seen
on then since the AGP aperture expanded the system aperture,
but this showed up again when AGP was disabled.

Reviewed-and-tested-by: Jiadong Zhu 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c  | 4 +++-
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c  | 4 +++-
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c   | 4 +++-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++--
 4 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index cdc290a474a9..66c6bab75f8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -102,7 +102,9 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 
-   if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+   if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
+  AMD_APU_IS_RENOIR |
+  AMD_APU_IS_GREEN_SARDINE))
   /*
* Raven2 has a HW issue that it is unable to use the
* vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
index 0834af771549..b50f24f7ea5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
@@ -139,7 +139,9 @@ gfxhub_v1_2_xcc_init_system_aperture_regs(struct 
amdgpu_device *adev,
WREG32_SOC15_RLC(GC, GET_INST(GC, i), 
regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 
18);
 
-   if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+   if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
+  AMD_APU_IS_RENOIR |
+  AMD_APU_IS_GREEN_SARDINE))
   /*
* Raven2 has a HW issue that it is unable to 
use the
* vram which is out of 
MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index fb91b31056ca..d25f87fb1971 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -96,7 +96,9 @@ static void mmhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 
-   if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+   if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
+  AMD_APU_IS_RENOIR |
+  AMD_APU_IS_GREEN_SARDINE))
/*
 * Raven2 has a HW issue that it is unable to use the vram which
 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ca3aa9825eb8..56a410accf49 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1247,7 +1247,9 @@ static void mmhub_read_system_context(struct 
amdgpu_device *adev, struct dc_phy_
/* AGP aperture is disabled */
if (agp_bot == agp_top) {
logical_addr_low = adev->gmc.fb_start >> 18;
-   if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+   if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
+  AMD_APU_IS_RENOIR |
+  AMD_APU_IS_GREEN_SARDINE))
/*
 * Raven2 has a HW issue that it is unable to use the 
vram which
 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here 
is the
@@ -1259,7 +1261,9 @@ static void mmhub_read_system_context(struct 
amdgpu_device *adev, struct dc_phy_
logical_addr_high = adev->gmc.fb_end >> 18;
} else {
logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) 
>> 18;
-   if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+   if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
+  AMD_APU_IS_RENOIR |
+  AMD_APU_IS_GREEN_SARDINE))
/*
 * Raven2 has a HW issue that it is unable to use the 
vram which
   

[PATCH AUTOSEL 6.6 68/73] Revert "drm/amdkfd: Relocate TBA/TMA to opposite side of VM hole"

[Sasha Levin]

From: Kaibo Ma 

[ Upstream commit 0f35b0a7b8fa402adbffa2565047cdcc4c480153 ]

That commit causes NULL pointer dereferences in dmesgs when
running applications using ROCm, including clinfo, blender,
and PyTorch, since v6.6.1. Revert it to fix blender again.

This reverts commit 96c211f1f9ef82183493f4ceed4e347b52849149.

Closes: https://github.com/ROCm/ROCm/issues/2596
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2991
Reviewed-by: Jay Cornwall 
Signed-off-by: Kaibo Ma 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 26 ++--
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 62b205dac63a..6604a3f99c5e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -330,12 +330,6 @@ static void kfd_init_apertures_vi(struct 
kfd_process_device *pdd, uint8_t id)
pdd->gpuvm_limit =
pdd->dev->kfd->shared_resources.gpuvm_size - 1;
 
-   /* dGPUs: the reserved space for kernel
-* before SVM
-*/
-   pdd->qpd.cwsr_base = SVM_CWSR_BASE;
-   pdd->qpd.ib_base = SVM_IB_BASE;
-
pdd->scratch_base = MAKE_SCRATCH_APP_BASE_VI();
pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
 }
@@ -345,18 +339,18 @@ static void kfd_init_apertures_v9(struct 
kfd_process_device *pdd, uint8_t id)
pdd->lds_base = MAKE_LDS_APP_BASE_V9();
pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
 
-   pdd->gpuvm_base = PAGE_SIZE;
+/* Raven needs SVM to support graphic handle, etc. Leave the small
+ * reserved space before SVM on Raven as well, even though we don't
+ * have to.
+ * Set gpuvm_base and gpuvm_limit to CANONICAL addresses so that they
+ * are used in Thunk to reserve SVM.
+ */
+pdd->gpuvm_base = SVM_USER_BASE;
pdd->gpuvm_limit =
pdd->dev->kfd->shared_resources.gpuvm_size - 1;
 
pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9();
pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
-
-   /*
-* Place TBA/TMA on opposite side of VM hole to prevent
-* stray faults from triggering SVM on these pages.
-*/
-   pdd->qpd.cwsr_base = pdd->dev->kfd->shared_resources.gpuvm_size;
 }
 
 int kfd_init_apertures(struct kfd_process *process)
@@ -413,6 +407,12 @@ int kfd_init_apertures(struct kfd_process *process)
return -EINVAL;
}
}
+
+/* dGPUs: the reserved space for kernel
+ * before SVM
+ */
+pdd->qpd.cwsr_base = SVM_CWSR_BASE;
+pdd->qpd.ib_base = SVM_IB_BASE;
}
 
dev_dbg(kfd_device, "node id %u\n", id);
-- 
2.43.0

[PATCH AUTOSEL 6.6 64/73] Re-revert "drm/amd/display: Enable Replay for static screen use cases"

[Sasha Levin]

From: Ivan Lipski 

[ Upstream commit d6398866a6b47e92319ef6efdb0126a4fbb7796a ]

This reverts commit 44e60b14d5a72f91fd0bdeae8da59ae37a3ca8e5.

Since, it causes a regression in which eDP displays with PSR support,
but no Replay support (Sink support <= 0x03), fail to enable PSR and
consequently all IGT amd_psr tests fail. So, revert this until a more
suitable fix can be found.

This got brought back accidently with the backmerge.

Acked-by: Leo Li 
Signed-off-by: Ivan Lipski 
Signed-off-by: Hamza Mahfooz 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 ---
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c|  9 +---
 drivers/gpu/drm/amd/include/amd_shared.h  |  2 --
 3 files changed, 1 insertion(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5084833e3608..ca3aa9825eb8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -65,7 +65,6 @@
 #include "amdgpu_dm_debugfs.h"
 #endif
 #include "amdgpu_dm_psr.h"
-#include "amdgpu_dm_replay.h"
 
 #include "ivsrcid/ivsrcid_vislands30.h"
 
@@ -4338,7 +4337,6 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
enum dc_connection_type new_connection_type = dc_connection_none;
const struct dc_plane_cap *plane;
bool psr_feature_enabled = false;
-   bool replay_feature_enabled = false;
int max_overlay = dm->dc->caps.max_slave_planes;
 
dm->display_indexes_num = dm->dc->caps.max_streams;
@@ -4448,20 +4446,6 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
}
}
 
-   if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
-   switch (adev->ip_versions[DCE_HWIP][0]) {
-   case IP_VERSION(3, 1, 4):
-   case IP_VERSION(3, 1, 5):
-   case IP_VERSION(3, 1, 6):
-   case IP_VERSION(3, 2, 0):
-   case IP_VERSION(3, 2, 1):
-   replay_feature_enabled = true;
-   break;
-   default:
-   replay_feature_enabled = amdgpu_dc_feature_mask & 
DC_REPLAY_MASK;
-   break;
-   }
-   }
/* loops over all connectors on the board */
for (i = 0; i < link_cnt; i++) {
struct dc_link *link = NULL;
@@ -4510,12 +4494,6 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)

amdgpu_dm_update_connector_after_detect(aconnector);
setup_backlight_device(dm, aconnector);
 
-   /*
-* Disable psr if replay can be enabled
-*/
-   if (replay_feature_enabled && 
amdgpu_dm_setup_replay(link, aconnector))
-   psr_feature_enabled = false;
-
if (psr_feature_enabled)
amdgpu_dm_set_psr_caps(link);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 97b7a0b8a1c2..30d4c6fd95f5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -29,7 +29,6 @@
 #include "dc.h"
 #include "amdgpu.h"
 #include "amdgpu_dm_psr.h"
-#include "amdgpu_dm_replay.h"
 #include "amdgpu_dm_crtc.h"
 #include "amdgpu_dm_plane.h"
 #include "amdgpu_dm_trace.h"
@@ -124,12 +123,7 @@ static void vblank_control_worker(struct work_struct *work)
 * fill_dc_dirty_rects().
 */
if (vblank_work->stream && vblank_work->stream->link) {
-   /*
-* Prioritize replay, instead of psr
-*/
-   if 
(vblank_work->stream->link->replay_settings.replay_feature_enabled)
-   amdgpu_dm_replay_enable(vblank_work->stream, false);
-   else if (vblank_work->enable) {
+   if (vblank_work->enable) {
if (vblank_work->stream->link->psr_settings.psr_version 
< DC_PSR_VERSION_SU_1 &&

vblank_work->stream->link->psr_settings.psr_allow_active)
amdgpu_dm_psr_disable(vblank_work->stream);
@@ -138,7 +132,6 @@ static void vblank_control_worker(struct work_struct *work)
 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
   
!amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) &&
 #endif
-  
vblank_work->stream->link->panel_config.psr.disallow_replay &&
   vblank_work->acrtc->dm_irq_params.allow_psr_entry) {
amdgpu_dm_psr_enable(vblank_work->stream);
}
diff --git 

[PATCH AUTOSEL 6.6 65/73] drm/amdgpu: Fix '*fw' from request_firmware() not released in 'amdgpu_ucode_request()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit 13a1851f923d9a7a78a477497295c2dfd16ad4a4 ]

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:1404 amdgpu_ucode_request() warn: 
'*fw' from request_firmware() not released on lines: 1404.

Cc: Mario Limonciello 
Cc: Lijo Lazar 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 8beefc045e14..bef754177064 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -1326,9 +1326,13 @@ int amdgpu_ucode_request(struct amdgpu_device *adev, 
const struct firmware **fw,
 
if (err)
return -ENODEV;
+
err = amdgpu_ucode_validate(*fw);
-   if (err)
+   if (err) {
dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name);
+   release_firmware(*fw);
+   *fw = NULL;
+   }
 
return err;
 }
-- 
2.43.0

[PATCH AUTOSEL 6.6 63/73] drm/amd/display: Fixing stream allocation regression

[Sasha Levin]

From: Relja Vojvodic 

[ Upstream commit 292c2116b2ae84c7e799ae340981e60551b18f5e ]

For certain dual display configs that had one display using a 1080p
mode, the DPM level used to drive the configs regressed from DPM 0 to
DPM 3. This was caused by a missing check that should have only limited
the pipe segments on non-phantom pipes. This caused issues with detile
buffer allocation, which dissallow subvp from being used

Tested-by: Daniel Wheeler 
Reviewed-by: Dillon Varone 
Reviewed-by: Martin Leung 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Relja Vojvodic 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 3ad2b48954e0..03bd05596d21 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -190,7 +190,7 @@ bool dcn32_subvp_in_use(struct dc *dc,
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 
-   if (pipe->stream && pipe->stream->mall_stream_config.type != 
SUBVP_NONE)
+   if (pipe->stream && pipe->stream->mall_stream_config.type != 
SUBVP_PHANTOM != SUBVP_NONE)
return true;
}
return false;
-- 
2.43.0

[PATCH AUTOSEL 6.6 67/73] drm/amdkfd: Fix iterator used outside loop in 'kfd_add_peer_prop()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit b1a428b45dc7e47c7acc2ad0d08d8a6dda910c4c ]

Fix the following about iterator use:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1456 kfd_add_peer_prop() 
warn: iterator used outside loop: 'iolink3'

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 24 ---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index c8c75ff7cea8..b9988b4fe2f5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1449,17 +1449,19 @@ static int kfd_add_peer_prop(struct kfd_topology_device 
*kdev,
/* CPU->CPU  link*/
cpu_dev = 
kfd_topology_device_by_proximity_domain(iolink1->node_to);
if (cpu_dev) {
-   list_for_each_entry(iolink3, &cpu_dev->io_link_props, 
list)
-   if (iolink3->node_to == iolink2->node_to)
-   break;
-
-   props->weight += iolink3->weight;
-   props->min_latency += iolink3->min_latency;
-   props->max_latency += iolink3->max_latency;
-   props->min_bandwidth = min(props->min_bandwidth,
-   iolink3->min_bandwidth);
-   props->max_bandwidth = min(props->max_bandwidth,
-   iolink3->max_bandwidth);
+   list_for_each_entry(iolink3, &cpu_dev->io_link_props, 
list) {
+   if (iolink3->node_to != iolink2->node_to)
+   continue;
+
+   props->weight += iolink3->weight;
+   props->min_latency += iolink3->min_latency;
+   props->max_latency += iolink3->max_latency;
+   props->min_bandwidth = min(props->min_bandwidth,
+  
iolink3->min_bandwidth);
+   props->max_bandwidth = min(props->max_bandwidth,
+  
iolink3->max_bandwidth);
+   break;
+   }
} else {
WARN(1, "CPU node not found");
}
-- 
2.43.0

[PATCH AUTOSEL 6.6 66/73] drm/amdgpu: Drop 'fence' check in 'to_amdgpu_amdkfd_fence()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit bf2ad4fb8adca89374b54b225d494e0b1956dbea ]

Return value of container_of(...) can't be null, so null check is not
required for 'fence'. Hence drop its NULL check.

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c:93 to_amdgpu_amdkfd_fence() 
warn: can 'fence' even be NULL?

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
index 469785d33791..1ef758ac5076 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
@@ -90,7 +90,7 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct 
dma_fence *f)
return NULL;
 
fence = container_of(f, struct amdgpu_amdkfd_fence, base);
-   if (fence && f->ops == &amdkfd_fence_ops)
+   if (f->ops == &amdkfd_fence_ops)
return fence;
 
return NULL;
-- 
2.43.0

[PATCH AUTOSEL 6.6 61/73] drm/amd/display: Fix minor issues in BW Allocation Phase2

[Sasha Levin]

From: Meenakshikumar Somasundaram 

[ Upstream commit aa5dc05340eb97486a631ce6bccb8d020bf6b56b ]

[Why]
Fix minor issues in BW Allocation Phase2.

[How]
- In set_usb4_req_bw_req(), link->dpia_bw_alloc_config.response_ready
  flag should be reset before writing DPCD REQUEST_BW.
- Fix the granularity for value of 2 in get_bw_granularity().
- Removed bandwidth allocation support display fw boot option as
  the fw would read feature enable status from bios.
- Clean up DPIA_EST_BW_CHANGED and DPIA_BW_REQ_SUCCESS cases in
  dpia_handle_bw_alloc_response().
- Removed allocate_usb4_bw and deallocate_usb4_bw.
- Optimized loop in get_lowest_dpia_index().
- Updated link_dp_dpia_allocate_usb4_bandwidth_for_stream() and
  set_usb4_req_bw_req() to always issue request bw.

Tested-by: Daniel Wheeler 
Reviewed-by: PeiChen Huang 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Meenakshikumar Somasundaram 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../dc/link/protocols/link_dp_dpia_bw.c   | 221 --
 .../dc/link/protocols/link_dp_dpia_bw.h   |   4 +-
 2 files changed, 101 insertions(+), 124 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c 
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
index 7581023daa47..d6e1f969bfd5 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
@@ -50,6 +50,7 @@ static bool get_bw_alloc_proceed_flag(struct dc_link *tmp)
&& tmp->hpd_status
&& tmp->dpia_bw_alloc_config.bw_alloc_enabled);
 }
+
 static void reset_bw_alloc_struct(struct dc_link *link)
 {
link->dpia_bw_alloc_config.bw_alloc_enabled = false;
@@ -59,6 +60,11 @@ static void reset_bw_alloc_struct(struct dc_link *link)
link->dpia_bw_alloc_config.bw_granularity = 0;
link->dpia_bw_alloc_config.response_ready = false;
 }
+
+#define BW_GRANULARITY_0 4 // 0.25 Gbps
+#define BW_GRANULARITY_1 2 // 0.5 Gbps
+#define BW_GRANULARITY_2 1 // 1 Gbps
+
 static uint8_t get_bw_granularity(struct dc_link *link)
 {
uint8_t bw_granularity = 0;
@@ -71,16 +77,20 @@ static uint8_t get_bw_granularity(struct dc_link *link)
 
switch (bw_granularity & 0x3) {
case 0:
-   bw_granularity = 4;
+   bw_granularity = BW_GRANULARITY_0;
break;
case 1:
+   bw_granularity = BW_GRANULARITY_1;
+   break;
+   case 2:
default:
-   bw_granularity = 2;
+   bw_granularity = BW_GRANULARITY_2;
break;
}
 
return bw_granularity;
 }
+
 static int get_estimated_bw(struct dc_link *link)
 {
uint8_t bw_estimated_bw = 0;
@@ -93,31 +103,7 @@ static int get_estimated_bw(struct dc_link *link)
 
return bw_estimated_bw * (Kbps_TO_Gbps / 
link->dpia_bw_alloc_config.bw_granularity);
 }
-static bool allocate_usb4_bw(int *stream_allocated_bw, int bw_needed, struct 
dc_link *link)
-{
-   if (bw_needed > 0)
-   *stream_allocated_bw += bw_needed;
-
-   return true;
-}
-static bool deallocate_usb4_bw(int *stream_allocated_bw, int bw_to_dealloc, 
struct dc_link *link)
-{
-   bool ret = false;
-
-   if (*stream_allocated_bw > 0) {
-   *stream_allocated_bw -= bw_to_dealloc;
-   ret = true;
-   } else {
-   //Do nothing for now
-   ret = true;
-   }
 
-   // Unplug so reset values
-   if (!link->hpd_status)
-   reset_bw_alloc_struct(link);
-
-   return ret;
-}
 /*
  * Read all New BW alloc configuration ex: estimated_bw, allocated_bw,
  * granuality, Driver_ID, CM_Group, & populate the BW allocation structs
@@ -128,7 +114,12 @@ static void init_usb4_bw_struct(struct dc_link *link)
// Init the known values
link->dpia_bw_alloc_config.bw_granularity = get_bw_granularity(link);
link->dpia_bw_alloc_config.estimated_bw = get_estimated_bw(link);
+
+   DC_LOG_DEBUG("%s: bw_granularity(%d), estimated_bw(%d)\n",
+   __func__, link->dpia_bw_alloc_config.bw_granularity,
+   link->dpia_bw_alloc_config.estimated_bw);
 }
+
 static uint8_t get_lowest_dpia_index(struct dc_link *link)
 {
const struct dc *dc_struct = link->dc;
@@ -141,12 +132,15 @@ static uint8_t get_lowest_dpia_index(struct dc_link *link)
dc_struct->links[i]->ep_type != 
DISPLAY_ENDPOINT_USB4_DPIA)
continue;
 
-   if (idx > dc_struct->links[i]->link_index)
+   if (idx > dc_struct->links[i]->link_index) {
idx = dc_struct->links[i]->link_index;
+   break;
+   }
}
 
return idx;
 }
+
 /*
  * Get the Max Available BW or Max Estimated BW for each Host Router
  *
@@ -186,6 +180,7 @@ static int get_host_router_total_bw(st

[PATCH AUTOSEL 6.6 62/73] drm/amdgpu: Let KFD sync with VM fences

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit ec9ba4821fa52b5efdbc4cdf0a77497990655231 ]

Change the rules for amdgpu_sync_resv to let KFD synchronize with VM
fences on page table reservations. This fixes intermittent memory
corruption after evictions when using amdgpu_vm_handle_moved to update
page tables for VM mappings managed through render nodes.

Signed-off-by: Felix Kuehling 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index dcd8c066bc1f..1b013a44ca99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -191,7 +191,8 @@ static bool amdgpu_sync_test_fence(struct amdgpu_device 
*adev,
 
/* Never sync to VM updates either. */
if (fence_owner == AMDGPU_FENCE_OWNER_VM &&
-   owner != AMDGPU_FENCE_OWNER_UNDEFINED)
+   owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
+   owner != AMDGPU_FENCE_OWNER_KFD)
return false;
 
/* Ignore fences depending on the sync mode */
-- 
2.43.0

[PATCH AUTOSEL 6.6 60/73] drm/amdgpu: Fix ecc irq enable/disable unpaired

[Sasha Levin]

From: "Stanley.Yang" 

[ Upstream commit a32c6f7f5737cc7e31cd7ad5133f0d96fca12ea6 ]

The ecc_irq is disabled while GPU mode2 reset suspending process,
but not be enabled during GPU mode2 reset resume process.

Changed from V1:
only do sdma/gfx ras_late_init in aldebaran_mode2_restore_ip
delete amdgpu_ras_late_resume function

Changed from V2:
check umc ras supported before put ecc_irq

Signed-off-by: Stanley.Yang 
Reviewed-by: Tao Zhou 
Reviewed-by: Hawking Zhang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/aldebaran.c | 26 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |  4 
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c |  5 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  4 
 4 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c 
b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
index 2b97b8a96fb4..fa6193535d48 100644
--- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
@@ -333,6 +333,7 @@ aldebaran_mode2_restore_hwcontext(struct 
amdgpu_reset_control *reset_ctl,
 {
struct list_head *reset_device_list = reset_context->reset_device_list;
struct amdgpu_device *tmp_adev = NULL;
+   struct amdgpu_ras *con;
int r;
 
if (reset_device_list == NULL)
@@ -358,7 +359,30 @@ aldebaran_mode2_restore_hwcontext(struct 
amdgpu_reset_control *reset_ctl,
 */
amdgpu_register_gpu_instance(tmp_adev);
 
-   /* Resume RAS */
+   /* Resume RAS, ecc_irq */
+   con = amdgpu_ras_get_context(tmp_adev);
+   if (!amdgpu_sriov_vf(tmp_adev) && con) {
+   if (tmp_adev->sdma.ras &&
+   tmp_adev->sdma.ras->ras_block.ras_late_init) {
+   r = 
tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev,
+   
&tmp_adev->sdma.ras->ras_block.ras_comm);
+   if (r) {
+   dev_err(tmp_adev->dev, "SDMA failed to 
execute ras_late_init! ret:%d\n", r);
+   goto end;
+   }
+   }
+
+   if (tmp_adev->gfx.ras &&
+   tmp_adev->gfx.ras->ras_block.ras_late_init) {
+   r = 
tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,
+   
&tmp_adev->gfx.ras->ras_block.ras_comm);
+   if (r) {
+   dev_err(tmp_adev->dev, "GFX failed to 
execute ras_late_init! ret:%d\n", r);
+   goto end;
+   }
+   }
+   }
+
amdgpu_ras_resume(tmp_adev);
 
/* Update PSP FW topology after reset */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index fa87a85e1017..62ecf4d89cb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1141,6 +1141,10 @@ static int gmc_v10_0_hw_fini(void *handle)
 
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 
+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index e3b76fd28d15..3d797a1adef3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -974,6 +974,11 @@ static int gmc_v11_0_hw_fini(void *handle)
}
 
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
+
+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
+
gmc_v11_0_gart_disable(adev);
 
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 89550d3df68d..f9f43742e9ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -2413,6 +2413,10 @@ static int gmc_v9_0_hw_fini(void *handle)
 
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 
+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
+
return 0;
 }
 
-- 
2.43.0

[PATCH AUTOSEL 6.6 57/73] drm/amd/display: Only clear symclk otg flag for HDMI

[Sasha Levin]

From: Alvin Lee 

[ Upstream commit dff45f03f508c92cd8eb2050e27b726726b8ae0b ]

[Description]
There is a corner case where the symclk otg flag is cleared
when disabling the phantom pipe for subvp (because the phantom
and main pipe share the same link). This is undesired because
we need the maintain the correct symclk otg flag state for
the main pipe.

For now only clear the flag only for HDMI signal type, since
it's only set for HDMI signal type (phantom is virtual). The
ideal solution is to not clear it if the stream is phantom but
currently there's a bug that doesn't allow us to do this. Once
this issue is fixed the proper fix can be implemented.

Reviewed-by: Samson Tam 
Acked-by: Wayne Lin 
Signed-off-by: Alvin Lee 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c   | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c  | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c  | 3 ++-
 4 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 9c78e42418f3..93699176a7e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2124,7 +2124,8 @@ static void dce110_reset_hw_ctx_wrap(
BREAK_TO_DEBUGGER();
}

pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
-   
pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+   if 
(dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal))
+   
pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
pipe_ctx_old->plane_res.mi, 
dc->current_state->stream_count);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 13ccb57379c7..db1d7be7fda3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1054,7 +1054,8 @@ static void dcn10_reset_back_end_for_pipe(
if (pipe_ctx->stream_res.tg->funcs->set_drr)
pipe_ctx->stream_res.tg->funcs->set_drr(
pipe_ctx->stream_res.tg, NULL);
-   pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+   if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+   pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 
0;
}
 
for (i = 0; i < dc->res_pool->pipe_count; i++)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 2c4bcbca8bb8..1e3803739ae6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2533,7 +2533,8 @@ static void dcn20_reset_back_end_for_pipe(
 * the case where the same symclk is shared across multiple otg
 * instances
 */
-   link->phy_state.symclk_ref_cnts.otg = 0;
+   if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+   link->phy_state.symclk_ref_cnts.otg = 0;
if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
link_hwss->disable_link_output(link,
&pipe_ctx->link_res, 
pipe_ctx->stream->signal);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 2a7f47642a44..22da2007601e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -523,7 +523,8 @@ static void dcn31_reset_back_end_for_pipe(
if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
pipe_ctx->stream_res.tg, 
&pipe_ctx->stream->timing);
-   pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+   if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+   pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
 
if (pipe_ctx->stream_res.tg->funcs->set_drr)
pipe_ctx->stream_res.tg->funcs->set_drr(
-- 
2.43.0

[PATCH AUTOSEL 6.6 56/73] drm/amd/display: make flip_timestamp_in_us a 64-bit variable

[Sasha Levin]

From: Josip Pavic 

[ Upstream commit 6fb12518ca58412dc51054e2a7400afb41328d85 ]

[Why]
This variable currently overflows after about 71 minutes. This doesn't
cause any known functional issues but it does make debugging more
difficult.

[How]
Make it a 64-bit variable.

Reviewed-by: Aric Cyr 
Acked-by: Wayne Lin 
Signed-off-by: Josip Pavic 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 99880b08cda0..00de342e5290 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -244,7 +244,7 @@ enum pixel_format {
 #define DC_MAX_DIRTY_RECTS 3
 struct dc_flip_addrs {
struct dc_plane_address address;
-   unsigned int flip_timestamp_in_us;
+   unsigned long long flip_timestamp_in_us;
bool flip_immediate;
/* TODO: add flip duration for FreeSync */
bool triplebuffer_flips;
-- 
2.43.0

[PATCH AUTOSEL 6.6 50/73] drm/amdgpu: fix ftrace event amdgpu_bo_move always move on same heap

[Sasha Levin]

From: "Wang, Beyond" 

[ Upstream commit 94aeb4117343d072e3a35b9595bcbfc0058ee724 ]

Issue: during evict or validate happened on amdgpu_bo, the 'from' and
'to' is always same in ftrace event of amdgpu_bo_move

where calling the 'trace_amdgpu_bo_move', the comment says move_notify
is called before move happens, but actually it is called after move
happens, here the new_mem is same as bo->resource

Fix: move trace_amdgpu_bo_move from move_notify to amdgpu_bo_move

Signed-off-by: Wang, Beyond 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 13 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  4 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  5 +++--
 3 files changed, 5 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index ace837cfa0a6..173b43a5aa13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1250,19 +1250,15 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void 
*buffer,
  * amdgpu_bo_move_notify - notification about a memory move
  * @bo: pointer to a buffer object
  * @evict: if this move is evicting the buffer from the graphics address space
- * @new_mem: new information of the bufer object
  *
  * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
  * bookkeeping.
  * TTM driver callback which is called when ttm moves a buffer.
  */
-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
-  bool evict,
-  struct ttm_resource *new_mem)
+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)
 {
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct amdgpu_bo *abo;
-   struct ttm_resource *old_mem = bo->resource;
 
if (!amdgpu_bo_is_amdgpu_bo(bo))
return;
@@ -1279,13 +1275,6 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
/* remember the eviction */
if (evict)
atomic64_inc(&adev->num_evictions);
-
-   /* update statistics */
-   if (!new_mem)
-   return;
-
-   /* move_notify is called before move happens */
-   trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 }
 
 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index d28e21baef16..a3ea8a82db23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -344,9 +344,7 @@ int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void 
*metadata,
 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
   size_t buffer_size, uint32_t *metadata_size,
   uint64_t *flags);
-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
-  bool evict,
-  struct ttm_resource *new_mem);
+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict);
 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 4e51dce3aab5..f573909332c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -545,10 +545,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, 
bool evict,
return r;
}
 
+   trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 out:
/* update statistics */
atomic64_add(bo->base.size, &adev->num_bytes_moved);
-   amdgpu_bo_move_notify(bo, evict, new_mem);
+   amdgpu_bo_move_notify(bo, evict);
return 0;
 }
 
@@ -1555,7 +1556,7 @@ static int amdgpu_ttm_access_memory(struct 
ttm_buffer_object *bo,
 static void
 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
 {
-   amdgpu_bo_move_notify(bo, false, NULL);
+   amdgpu_bo_move_notify(bo, false);
 }
 
 static struct ttm_device_funcs amdgpu_bo_driver = {
-- 
2.43.0

[PATCH AUTOSEL 6.6 43/73] drm/amd/display: For prefetch mode > 0, extend prefetch if possible

[Sasha Levin]

From: Alvin Lee 

[ Upstream commit dd4e4bb28843393065eed279e869fac248d03f0f ]

[Description]
For mode programming we want to extend the prefetch as much as possible
(up to oto, or as long as we can for equ) if we're not already applying
the 60us prefetch requirement. This is to avoid intermittent underflow
issues during prefetch.

The prefetch extension is applied under the following scenarios:
1. We're in prefetch mode 1 (i.e. we don't support MCLK switch in blank)
2. We're using subvp or drr methods of p-state switch, in which case we
   we don't care if prefetch takes up more of the blanking time

Mode programming typically chooses the smallest prefetch time possible
(i.e. highest bandwidth during prefetch) presumably to create margin between
p-states / c-states that happen in vblank and prefetch. Therefore we only
apply this prefetch extension when p-state in vblank is not required (UCLK
p-states take up the most vblank time).

Reviewed-by: Jun Lei 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alvin Lee 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../dc/dml/dcn32/display_mode_vba_32.c|  3 ++
 .../dc/dml/dcn32/display_mode_vba_util_32.c   | 33 +++
 .../dc/dml/dcn32/display_mode_vba_util_32.h   |  1 +
 3 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index cbdfb762c10c..6c84b0fa40f4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -813,6 +813,8 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman

(v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||

v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= 
DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?

mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
+   
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
 > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false,
+
/* Output */
&v->DSTXAfterScaler[k],
&v->DSTYAfterScaler[k],
@@ -3317,6 +3319,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l

v->SwathHeightCThisState[k], v->TWait,

(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= 
DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?

mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
+   
mode_lib->vba.PrefetchModePerState[i][j] > 0 || 
mode_lib->vba.DRAMClockChangeRequirementFinal == false,
 
/* Output */

&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index ecea008f19d3..208b89d13d3f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -3423,6 +3423,7 @@ bool dml32_CalculatePrefetchSchedule(
unsigned int SwathHeightC,
double TWait,
double TPreReq,
+   bool ExtendPrefetchIfPossible,
/* Output */
double   *DSTXAfterScaler,
double   *DSTYAfterScaler,
@@ -3892,12 +3893,32 @@ bool dml32_CalculatePrefetchSchedule(
/* Clamp to oto for bandwidth calculation */
LinesForPrefetchBandwidth = dst_y_prefetch_oto;
} else {
-   *DestinationLinesForPrefetch = dst_y_prefetch_equ;
-   TimeForFetchingMetaPTE = Tvm_equ;
-   TimeForFetchingRowInVBlank = Tr0_equ;
-   *PrefetchBandwidth = prefetch_bw_equ;
-   /* Clamp to equ for bandwidth calculation */
-   LinesForPrefetchBandwidth = dst_y_prefetch_equ;
+   /* For mode programming we want to extend the prefetch 
as much as possible
+* (up to oto, or as long as we can for equ) if we're 
not already applying
+* the 60us prefetch requirement. This is to avoid 
intermittent underflow
+* issues during prefetch.
+  

[PATCH AUTOSEL 6.6 45/73] drm/amdkfd: fix mes set shader debugger process management

[Sasha Levin]

From: Jonathan Kim 

[ Upstream commit bd33bb1409b494558a2935f7bbc7842def957fcd ]

MES provides the driver a call to explicitly flush stale process memory
within the MES to avoid a race condition that results in a fatal
memory violation.

When SET_SHADER_DEBUGGER is called, the driver passes a memory address
that represents a process context address MES uses to keep track of
future per-process calls.

Normally, MES will purge its process context list when the last queue
has been removed.  The driver, however, can call SET_SHADER_DEBUGGER
regardless of whether a queue has been added or not.

If SET_SHADER_DEBUGGER has been called with no queues as the last call
prior to process termination, the passed process context address will
still reside within MES.

On a new process call to SET_SHADER_DEBUGGER, the driver may end up
passing an identical process context address value (based on per-process
gpu memory address) to MES but is now pointing to a new allocated buffer
object during KFD process creation.  Since the MES is unaware of this,
access of the passed address points to the stale object within MES and
triggers a fatal memory violation.

The solution is for KFD to explicitly flush the process context address
from MES on process termination.

Note that the flush call and the MES debugger calls use the same MES
interface but are separated as KFD calls to avoid conflicting with each
other.

Signed-off-by: Jonathan Kim 
Tested-by: Alice Wong 
Reviewed-by: Eric Huang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c   | 31 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h   | 10 +++---
 .../amd/amdkfd/kfd_process_queue_manager.c|  1 +
 drivers/gpu/drm/amd/include/mes_v11_api_def.h |  3 +-
 4 files changed, 40 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 6aa75052309f..15c67fa404ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -885,6 +885,11 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device 
*adev,
op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;
op_input.set_shader_debugger.process_context_addr = 
process_context_addr;
op_input.set_shader_debugger.flags.u32all = flags;
+
+   /* use amdgpu mes_flush_shader_debugger instead */
+   if (op_input.set_shader_debugger.flags.process_ctx_flush)
+   return -EINVAL;
+
op_input.set_shader_debugger.spi_gdbg_per_vmid_cntl = 
spi_gdbg_per_vmid_cntl;
memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,
sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
@@ -904,6 +909,32 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device 
*adev,
return r;
 }
 
+int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
+uint64_t process_context_addr)
+{
+   struct mes_misc_op_input op_input = {0};
+   int r;
+
+   if (!adev->mes.funcs->misc_op) {
+   DRM_ERROR("mes flush shader debugger is not supported!\n");
+   return -EINVAL;
+   }
+
+   op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;
+   op_input.set_shader_debugger.process_context_addr = 
process_context_addr;
+   op_input.set_shader_debugger.flags.process_ctx_flush = true;
+
+   amdgpu_mes_lock(&adev->mes);
+
+   r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+   if (r)
+   DRM_ERROR("failed to set_shader_debugger\n");
+
+   amdgpu_mes_unlock(&adev->mes);
+
+   return r;
+}
+
 static void
 amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,
   struct amdgpu_ring *ring,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index a27b424ffe00..c2c88b772361 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -291,9 +291,10 @@ struct mes_misc_op_input {
uint64_t process_context_addr;
union {
struct {
-   uint64_t single_memop : 1;
-   uint64_t single_alu_op : 1;
-   uint64_t reserved: 30;
+   uint32_t single_memop : 1;
+   uint32_t single_alu_op : 1;
+   uint32_t reserved: 29;
+   uint32_t process_ctx_flush: 1;
};
uint32_t u32all;
} flags;
@@ -369,7 +370,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device 
*adev,
const uint32_t *tcp_watch_cntl,
uint32_t flags,
   

[PATCH AUTOSEL 6.6 44/73] drm/amd/display: Force p-state disallow if leaving no plane config

[Sasha Levin]

From: Alvin Lee 

[ Upstream commit 9a902a9073c287353e25913c0761bfed49d75a88 ]

[Description]
- When we're in a no plane config, DCN is always asserting
  P-State allow
- This creates a scenario where the P-State blackout can start
  just as VUPDATE takes place and transitions the DCN config to
  a one where one or more HUBP's are active which can result in
  underflow
- To fix this issue, force p-state disallow and unforce after
  the transition from no planes case -> one or more planes active

Reviewed-by: Samson Tam 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alvin Lee 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 20 +++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index a2e1ca3b93e8..2c4bcbca8bb8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1792,6 +1792,8 @@ void dcn20_program_front_end_for_ctx(
int i;
struct dce_hwseq *hws = dc->hwseq;
DC_LOGGER_INIT(dc->ctx->logger);
+   unsigned int prev_hubp_count = 0;
+   unsigned int hubp_count = 0;
 
/* Carry over GSL groups in case the context is changing. */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1815,6 +1817,20 @@ void dcn20_program_front_end_for_ctx(
}
}
 
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
+   prev_hubp_count++;
+   if (context->res_ctx.pipe_ctx[i].plane_state)
+   hubp_count++;
+   }
+
+   if (prev_hubp_count == 0 && hubp_count > 0) {
+   if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+   
dc->res_pool->hubbub->funcs->force_pstate_change_control(
+   dc->res_pool->hubbub, true, false);
+   udelay(500);
+   }
+
/* Set pipe update flags and lock pipes */
for (i = 0; i < dc->res_pool->pipe_count; i++)

dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
@@ -1962,6 +1978,10 @@ void dcn20_post_unlock_program_front_end(
}
}
 
+   if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+   dc->res_pool->hubbub->funcs->force_pstate_change_control(
+   dc->res_pool->hubbub, false, false);
+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 
-- 
2.43.0

[PATCH AUTOSEL 6.6 17/73] drm/amd/display: Fix writeback_info is not removed

[Sasha Levin]

From: Alex Hung 

[ Upstream commit 5b89d2ccc8466e0445a4994cb288fc009b565de5 ]

[WHY]
Counter j was not updated to present the num of writeback_info when
writeback pipes are removed.

[HOW]
update j (num of writeback info) under the correct condition.

Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index c232d38e70ae..79f3d7648eb7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -546,11 +546,12 @@ bool dc_stream_remove_writeback(struct dc *dc,
if (stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst)
stream->writeback_info[i].wb_enabled = false;
 
-   if (j < i)
-   /* trim the array */
+   /* trim the array */
+   if (j < i) {
memcpy(&stream->writeback_info[j], 
&stream->writeback_info[i],
sizeof(struct 
dc_writeback_info));
-   j++;
+   j++;
+   }
}
}
stream->num_wb_info = j;
-- 
2.43.0

[PATCH AUTOSEL 6.6 15/73] drm/amd/display: Fix MST PBN/X.Y value calculations

[Sasha Levin]

From: Ilya Bakoulin 

[ Upstream commit 94bbf802efd0a8f13147d6664af6e653637340a8 ]

Changing PBN calculation to be more in line with spec. We don't need to
inflate PBN_NATIVE value by the 1.006 margin, since that is already
taken care of in the get_pbn_per_slot function.

Tested-by: Daniel Wheeler 
Reviewed-by: Wenjing Liu 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Ilya Bakoulin 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c 
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 35d087cf1980..c5f8ce6e30f3 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -1055,18 +1055,21 @@ static struct fixed31_32 
get_pbn_from_bw_in_kbps(uint64_t kbps)
uint32_t denominator = 1;
 
/*
-* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+* The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not
+* required when determining PBN/time slot utilization on the link 
between
+* us and the branch, since that overhead is already accounted for in
+* the get_pbn_per_slot function.
+*
 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
 * common multiplier to render an integer PBN for all link rate/lane
 * counts combinations
 * calculate
-* peak_kbps *= (1006/1000)
 * peak_kbps *= (64/54)
-* peak_kbps *= 8convert to bytes
+* peak_kbps /= (8 * 1000) convert to bytes
 */
 
-   numerator = 64 * PEAK_FACTOR_X1000;
-   denominator = 54 * 8 * 1000 * 1000;
+   numerator = 64;
+   denominator = 54 * 8 * 1000;
kbps *= numerator;
peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
 
-- 
2.43.0

[PATCH AUTOSEL 6.6 16/73] drm/amd/display: Fix writeback_info never got updated

[Sasha Levin]

From: Alex Hung 

[ Upstream commit 8a30c36e15f38c9f23778babcd368144c7d8 ]

[WHY]
wb_enabled field is set to false before it is used, and the following
code will never be executed.

[HOW]
Setting wb_enable to false after all removal work is completed.

Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index ebe571fcefe3..c232d38e70ae 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -539,18 +539,13 @@ bool dc_stream_remove_writeback(struct dc *dc,
return false;
}
 
-// stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
-   for (i = 0; i < stream->num_wb_info; i++) {
-   /*dynamic update*/
-   if (stream->writeback_info[i].wb_enabled &&
-   stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst) {
-   stream->writeback_info[i].wb_enabled = false;
-   }
-   }
-
/* remove writeback info for disabled writeback pipes from stream */
for (i = 0, j = 0; i < stream->num_wb_info; i++) {
if (stream->writeback_info[i].wb_enabled) {
+
+   if (stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst)
+   stream->writeback_info[i].wb_enabled = false;
+
if (j < i)
/* trim the array */
memcpy(&stream->writeback_info[j], 
&stream->writeback_info[i],
-- 
2.43.0

[PATCH AUTOSEL 6.6 11/73] drm/amd/display: Fix tiled display misalignment

[Sasha Levin]

From: Meenakshikumar Somasundaram 

[ Upstream commit c4b8394e76adba4f50a3c2696c75b214a291e24a ]

[Why]
When otg workaround is applied during clock update, otgs of
tiled display went out of sync.

[How]
To call dc_trigger_sync() after clock update to sync otgs again.

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Hamza Mahfooz 
Signed-off-by: Meenakshikumar Somasundaram 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a1be93f6385c..39b414774a1f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1948,6 +1948,10 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
wait_for_no_pipes_pending(dc, context);
/* pplib is notified if disp_num changed */
dc->hwss.optimize_bandwidth(dc, context);
+   /* Need to do otg sync again as otg could be out of sync due to 
otg
+* workaround applied during clock update
+*/
+   dc_trigger_sync(dc, context);
}
 
if (dc->hwss.update_dsc_pg)
-- 
2.43.0

[PATCH AUTOSEL 6.7 84/88] drm/amdgpu: apply the RV2 system aperture fix to RN/CZN as well

[Sasha Levin]

From: Alex Deucher 

[ Upstream commit 16783d8ef08448815e149e40c82fc1e1fc41ddbf ]

These chips needs the same fix.  This was previously not seen
on then since the AGP aperture expanded the system aperture,
but this showed up again when AGP was disabled.

Reviewed-and-tested-by: Jiadong Zhu 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c  | 4 +++-
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c  | 4 +++-
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c   | 4 +++-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++--
 4 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 53a2ba5fcf4b..22175da0e16a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -102,7 +102,9 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 
-   if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+   if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
+  AMD_APU_IS_RENOIR |
+  AMD_APU_IS_GREEN_SARDINE))
   /*
* Raven2 has a HW issue that it is unable to use the
* vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
index 55423ff1bb49..95d06da544e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
@@ -139,7 +139,9 @@ gfxhub_v1_2_xcc_init_system_aperture_regs(struct 
amdgpu_device *adev,
WREG32_SOC15_RLC(GC, GET_INST(GC, i), 
regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 
18);
 
-   if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+   if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
+  AMD_APU_IS_RENOIR |
+  AMD_APU_IS_GREEN_SARDINE))
   /*
* Raven2 has a HW issue that it is unable to 
use the
* vram which is out of 
MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 843219a91736..e3ddd22aa172 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -96,7 +96,9 @@ static void mmhub_v1_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 
-   if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+   if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
+  AMD_APU_IS_RENOIR |
+  AMD_APU_IS_GREEN_SARDINE))
/*
 * Raven2 has a HW issue that it is unable to use the vram which
 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index cf32502d669f..2ec5705596bf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1257,7 +1257,9 @@ static void mmhub_read_system_context(struct 
amdgpu_device *adev, struct dc_phy_
/* AGP aperture is disabled */
if (agp_bot > agp_top) {
logical_addr_low = adev->gmc.fb_start >> 18;
-   if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+   if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
+  AMD_APU_IS_RENOIR |
+  AMD_APU_IS_GREEN_SARDINE))
/*
 * Raven2 has a HW issue that it is unable to use the 
vram which
 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here 
is the
@@ -1269,7 +1271,9 @@ static void mmhub_read_system_context(struct 
amdgpu_device *adev, struct dc_phy_
logical_addr_high = adev->gmc.fb_end >> 18;
} else {
logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) 
>> 18;
-   if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+   if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
+  AMD_APU_IS_RENOIR |
+  AMD_APU_IS_GREEN_SARDINE))
/*
 * Raven2 has a HW issue that it is unable to use the 
vram which

[PATCH AUTOSEL 6.7 81/88] drm/amdgpu: Drop 'fence' check in 'to_amdgpu_amdkfd_fence()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit bf2ad4fb8adca89374b54b225d494e0b1956dbea ]

Return value of container_of(...) can't be null, so null check is not
required for 'fence'. Hence drop its NULL check.

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c:93 to_amdgpu_amdkfd_fence() 
warn: can 'fence' even be NULL?

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
index 469785d33791..1ef758ac5076 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
@@ -90,7 +90,7 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct 
dma_fence *f)
return NULL;
 
fence = container_of(f, struct amdgpu_amdkfd_fence, base);
-   if (fence && f->ops == &amdkfd_fence_ops)
+   if (f->ops == &amdkfd_fence_ops)
return fence;
 
return NULL;
-- 
2.43.0

[PATCH AUTOSEL 6.7 83/88] Revert "drm/amdkfd: Relocate TBA/TMA to opposite side of VM hole"

[Sasha Levin]

From: Kaibo Ma 

[ Upstream commit 0f35b0a7b8fa402adbffa2565047cdcc4c480153 ]

That commit causes NULL pointer dereferences in dmesgs when
running applications using ROCm, including clinfo, blender,
and PyTorch, since v6.6.1. Revert it to fix blender again.

This reverts commit 96c211f1f9ef82183493f4ceed4e347b52849149.

Closes: https://github.com/ROCm/ROCm/issues/2596
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2991
Reviewed-by: Jay Cornwall 
Signed-off-by: Kaibo Ma 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 26 ++--
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 62b205dac63a..6604a3f99c5e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -330,12 +330,6 @@ static void kfd_init_apertures_vi(struct 
kfd_process_device *pdd, uint8_t id)
pdd->gpuvm_limit =
pdd->dev->kfd->shared_resources.gpuvm_size - 1;
 
-   /* dGPUs: the reserved space for kernel
-* before SVM
-*/
-   pdd->qpd.cwsr_base = SVM_CWSR_BASE;
-   pdd->qpd.ib_base = SVM_IB_BASE;
-
pdd->scratch_base = MAKE_SCRATCH_APP_BASE_VI();
pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
 }
@@ -345,18 +339,18 @@ static void kfd_init_apertures_v9(struct 
kfd_process_device *pdd, uint8_t id)
pdd->lds_base = MAKE_LDS_APP_BASE_V9();
pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
 
-   pdd->gpuvm_base = PAGE_SIZE;
+/* Raven needs SVM to support graphic handle, etc. Leave the small
+ * reserved space before SVM on Raven as well, even though we don't
+ * have to.
+ * Set gpuvm_base and gpuvm_limit to CANONICAL addresses so that they
+ * are used in Thunk to reserve SVM.
+ */
+pdd->gpuvm_base = SVM_USER_BASE;
pdd->gpuvm_limit =
pdd->dev->kfd->shared_resources.gpuvm_size - 1;
 
pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9();
pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
-
-   /*
-* Place TBA/TMA on opposite side of VM hole to prevent
-* stray faults from triggering SVM on these pages.
-*/
-   pdd->qpd.cwsr_base = pdd->dev->kfd->shared_resources.gpuvm_size;
 }
 
 int kfd_init_apertures(struct kfd_process *process)
@@ -413,6 +407,12 @@ int kfd_init_apertures(struct kfd_process *process)
return -EINVAL;
}
}
+
+/* dGPUs: the reserved space for kernel
+ * before SVM
+ */
+pdd->qpd.cwsr_base = SVM_CWSR_BASE;
+pdd->qpd.ib_base = SVM_IB_BASE;
}
 
dev_dbg(kfd_device, "node id %u\n", id);
-- 
2.43.0

[PATCH AUTOSEL 6.7 82/88] drm/amdkfd: Fix iterator used outside loop in 'kfd_add_peer_prop()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit b1a428b45dc7e47c7acc2ad0d08d8a6dda910c4c ]

Fix the following about iterator use:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1456 kfd_add_peer_prop() 
warn: iterator used outside loop: 'iolink3'

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 24 ---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 057284bf50bb..d18dff7bb889 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1449,17 +1449,19 @@ static int kfd_add_peer_prop(struct kfd_topology_device 
*kdev,
/* CPU->CPU  link*/
cpu_dev = 
kfd_topology_device_by_proximity_domain(iolink1->node_to);
if (cpu_dev) {
-   list_for_each_entry(iolink3, &cpu_dev->io_link_props, 
list)
-   if (iolink3->node_to == iolink2->node_to)
-   break;
-
-   props->weight += iolink3->weight;
-   props->min_latency += iolink3->min_latency;
-   props->max_latency += iolink3->max_latency;
-   props->min_bandwidth = min(props->min_bandwidth,
-   iolink3->min_bandwidth);
-   props->max_bandwidth = min(props->max_bandwidth,
-   iolink3->max_bandwidth);
+   list_for_each_entry(iolink3, &cpu_dev->io_link_props, 
list) {
+   if (iolink3->node_to != iolink2->node_to)
+   continue;
+
+   props->weight += iolink3->weight;
+   props->min_latency += iolink3->min_latency;
+   props->max_latency += iolink3->max_latency;
+   props->min_bandwidth = min(props->min_bandwidth,
+  
iolink3->min_bandwidth);
+   props->max_bandwidth = min(props->max_bandwidth,
+  
iolink3->max_bandwidth);
+   break;
+   }
} else {
WARN(1, "CPU node not found");
}
-- 
2.43.0

[PATCH AUTOSEL 6.7 80/88] drm/amdgpu: Fix '*fw' from request_firmware() not released in 'amdgpu_ucode_request()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit 13a1851f923d9a7a78a477497295c2dfd16ad4a4 ]

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:1404 amdgpu_ucode_request() warn: 
'*fw' from request_firmware() not released on lines: 1404.

Cc: Mario Limonciello 
Cc: Lijo Lazar 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index b14127429f30..0efb2568cb65 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -1397,9 +1397,13 @@ int amdgpu_ucode_request(struct amdgpu_device *adev, 
const struct firmware **fw,
 
if (err)
return -ENODEV;
+
err = amdgpu_ucode_validate(*fw);
-   if (err)
+   if (err) {
dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name);
+   release_firmware(*fw);
+   *fw = NULL;
+   }
 
return err;
 }
-- 
2.43.0

[PATCH AUTOSEL 6.7 79/88] drm/amdgpu: Fix variable 'mca_funcs' dereferenced before NULL check in 'amdgpu_mca_smu_get_mca_entry()'

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit 4f32504a2f85a7b40fe149436881381f48e9c0c0 ]

Fixes the below:

drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c:377 amdgpu_mca_smu_get_mca_entry() 
warn: variable dereferenced before check 'mca_funcs' (see line 368)

357 int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev,
 enum amdgpu_mca_error_type type,
358  int idx, struct mca_bank_entry *entry)
359 {
360 const struct amdgpu_mca_smu_funcs *mca_funcs =
adev->mca.mca_funcs;
361 int count;
362
363 switch (type) {
364 case AMDGPU_MCA_ERROR_TYPE_UE:
365 count = mca_funcs->max_ue_count;

mca_funcs is dereferenced here.

366 break;
367 case AMDGPU_MCA_ERROR_TYPE_CE:
368 count = mca_funcs->max_ce_count;

mca_funcs is dereferenced here.

369 break;
370 default:
371 return -EINVAL;
372 }
373
374 if (idx >= count)
375 return -EINVAL;
376
377 if (mca_funcs && mca_funcs->mca_get_mca_entry)
^

Checked too late!

Cc: Yang Wang 
Cc: Hawking Zhang 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Yang Wang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
index cf33eb219e25..061d88f4480d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c
@@ -351,6 +351,9 @@ int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device 
*adev, enum amdgpu_mca_err
const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
int count;
 
+   if (!mca_funcs || !mca_funcs->mca_get_mca_entry)
+   return -EOPNOTSUPP;
+
switch (type) {
case AMDGPU_MCA_ERROR_TYPE_UE:
count = mca_funcs->max_ue_count;
@@ -365,10 +368,7 @@ int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device 
*adev, enum amdgpu_mca_err
if (idx >= count)
return -EINVAL;
 
-   if (mca_funcs && mca_funcs->mca_get_mca_entry)
-   return mca_funcs->mca_get_mca_entry(adev, type, idx, entry);
-
-   return -EOPNOTSUPP;
+   return mca_funcs->mca_get_mca_entry(adev, type, idx, entry);
 }
 
 #if defined(CONFIG_DEBUG_FS)
-- 
2.43.0

[PATCH AUTOSEL 6.7 73/88] drm/amdgpu: Fix ecc irq enable/disable unpaired

[Sasha Levin]

From: "Stanley.Yang" 

[ Upstream commit a32c6f7f5737cc7e31cd7ad5133f0d96fca12ea6 ]

The ecc_irq is disabled while GPU mode2 reset suspending process,
but not be enabled during GPU mode2 reset resume process.

Changed from V1:
only do sdma/gfx ras_late_init in aldebaran_mode2_restore_ip
delete amdgpu_ras_late_resume function

Changed from V2:
check umc ras supported before put ecc_irq

Signed-off-by: Stanley.Yang 
Reviewed-by: Tao Zhou 
Reviewed-by: Hawking Zhang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/aldebaran.c | 26 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |  4 
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c |  5 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  4 
 4 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c 
b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
index 02f4c6f9d4f6..576067d66bb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c
@@ -330,6 +330,7 @@ aldebaran_mode2_restore_hwcontext(struct 
amdgpu_reset_control *reset_ctl,
 {
struct list_head *reset_device_list = reset_context->reset_device_list;
struct amdgpu_device *tmp_adev = NULL;
+   struct amdgpu_ras *con;
int r;
 
if (reset_device_list == NULL)
@@ -355,7 +356,30 @@ aldebaran_mode2_restore_hwcontext(struct 
amdgpu_reset_control *reset_ctl,
 */
amdgpu_register_gpu_instance(tmp_adev);
 
-   /* Resume RAS */
+   /* Resume RAS, ecc_irq */
+   con = amdgpu_ras_get_context(tmp_adev);
+   if (!amdgpu_sriov_vf(tmp_adev) && con) {
+   if (tmp_adev->sdma.ras &&
+   tmp_adev->sdma.ras->ras_block.ras_late_init) {
+   r = 
tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev,
+   
&tmp_adev->sdma.ras->ras_block.ras_comm);
+   if (r) {
+   dev_err(tmp_adev->dev, "SDMA failed to 
execute ras_late_init! ret:%d\n", r);
+   goto end;
+   }
+   }
+
+   if (tmp_adev->gfx.ras &&
+   tmp_adev->gfx.ras->ras_block.ras_late_init) {
+   r = 
tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,
+   
&tmp_adev->gfx.ras->ras_block.ras_comm);
+   if (r) {
+   dev_err(tmp_adev->dev, "GFX failed to 
execute ras_late_init! ret:%d\n", r);
+   goto end;
+   }
+   }
+   }
+
amdgpu_ras_resume(tmp_adev);
 
/* Update PSP FW topology after reset */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index a5a05c16c10d..6c5185608854 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1041,6 +1041,10 @@ static int gmc_v10_0_hw_fini(void *handle)
 
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 
+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 23d7b548d13f..c9c653cfc765 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -941,6 +941,11 @@ static int gmc_v11_0_hw_fini(void *handle)
}
 
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
+
+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
+
gmc_v11_0_gart_disable(adev);
 
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 2ac5820e9c92..507d695bcc6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -2380,6 +2380,10 @@ static int gmc_v9_0_hw_fini(void *handle)
 
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 
+   if (adev->gmc.ecc_irq.funcs &&
+   amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
+   amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
+
return 0;
 }
 
-- 
2.43.0

[PATCH AUTOSEL 6.7 78/88] drm/amdgpu: Fix possible NULL dereference in amdgpu_ras_query_error_status_helper()

[Sasha Levin]

From: Srinivasan Shanmugam 

[ Upstream commit b8d55a90fd55b767c25687747e2b24abd1ef8680 ]

Return invalid error code -EINVAL for invalid block id.

Fixes the below:

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1183 
amdgpu_ras_query_error_status_helper() error: we previously assumed 'info' 
could be null (see line 1176)

Suggested-by: Hawking Zhang 
Cc: Tao Zhou 
Cc: Hawking Zhang 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
Reviewed-by: Hawking Zhang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 63fb4cd85e53..4a3726bb6da1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1174,6 +1174,9 @@ static int amdgpu_ras_query_error_status_helper(struct 
amdgpu_device *adev,
enum amdgpu_ras_block blk = info ? info->head.block : 
AMDGPU_RAS_BLOCK_COUNT;
struct amdgpu_ras_block_object *block_obj = NULL;
 
+   if (blk == AMDGPU_RAS_BLOCK_COUNT)
+   return -EINVAL;
+
if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)
return -EINVAL;
 
-- 
2.43.0

[PATCH AUTOSEL 6.7 77/88] Re-revert "drm/amd/display: Enable Replay for static screen use cases"

[Sasha Levin]

From: Ivan Lipski 

[ Upstream commit d6398866a6b47e92319ef6efdb0126a4fbb7796a ]

This reverts commit 44e60b14d5a72f91fd0bdeae8da59ae37a3ca8e5.

Since, it causes a regression in which eDP displays with PSR support,
but no Replay support (Sink support <= 0x03), fail to enable PSR and
consequently all IGT amd_psr tests fail. So, revert this until a more
suitable fix can be found.

This got brought back accidently with the backmerge.

Acked-by: Leo Li 
Signed-off-by: Ivan Lipski 
Signed-off-by: Hamza Mahfooz 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 ---
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c|  9 +---
 drivers/gpu/drm/amd/include/amd_shared.h  |  2 --
 3 files changed, 1 insertion(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4e82ee4d74ac..cf32502d669f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -65,7 +65,6 @@
 #include "amdgpu_dm_debugfs.h"
 #endif
 #include "amdgpu_dm_psr.h"
-#include "amdgpu_dm_replay.h"
 
 #include "ivsrcid/ivsrcid_vislands30.h"
 
@@ -4345,7 +4344,6 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
enum dc_connection_type new_connection_type = dc_connection_none;
const struct dc_plane_cap *plane;
bool psr_feature_enabled = false;
-   bool replay_feature_enabled = false;
int max_overlay = dm->dc->caps.max_slave_planes;
 
dm->display_indexes_num = dm->dc->caps.max_streams;
@@ -4457,20 +4455,6 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
}
}
 
-   if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
-   switch (adev->ip_versions[DCE_HWIP][0]) {
-   case IP_VERSION(3, 1, 4):
-   case IP_VERSION(3, 1, 5):
-   case IP_VERSION(3, 1, 6):
-   case IP_VERSION(3, 2, 0):
-   case IP_VERSION(3, 2, 1):
-   replay_feature_enabled = true;
-   break;
-   default:
-   replay_feature_enabled = amdgpu_dc_feature_mask & 
DC_REPLAY_MASK;
-   break;
-   }
-   }
/* loops over all connectors on the board */
for (i = 0; i < link_cnt; i++) {
struct dc_link *link = NULL;
@@ -4519,12 +4503,6 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)

amdgpu_dm_update_connector_after_detect(aconnector);
setup_backlight_device(dm, aconnector);
 
-   /*
-* Disable psr if replay can be enabled
-*/
-   if (replay_feature_enabled && 
amdgpu_dm_setup_replay(link, aconnector))
-   psr_feature_enabled = false;
-
if (psr_feature_enabled)
amdgpu_dm_set_psr_caps(link);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index cb0b48bb2a7d..d2834ad85a54 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -29,7 +29,6 @@
 #include "dc.h"
 #include "amdgpu.h"
 #include "amdgpu_dm_psr.h"
-#include "amdgpu_dm_replay.h"
 #include "amdgpu_dm_crtc.h"
 #include "amdgpu_dm_plane.h"
 #include "amdgpu_dm_trace.h"
@@ -124,12 +123,7 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct 
work_struct *work)
 * fill_dc_dirty_rects().
 */
if (vblank_work->stream && vblank_work->stream->link) {
-   /*
-* Prioritize replay, instead of psr
-*/
-   if 
(vblank_work->stream->link->replay_settings.replay_feature_enabled)
-   amdgpu_dm_replay_enable(vblank_work->stream, false);
-   else if (vblank_work->enable) {
+   if (vblank_work->enable) {
if (vblank_work->stream->link->psr_settings.psr_version 
< DC_PSR_VERSION_SU_1 &&

vblank_work->stream->link->psr_settings.psr_allow_active)
amdgpu_dm_psr_disable(vblank_work->stream);
@@ -138,7 +132,6 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct 
work_struct *work)
 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
   
!amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) &&
 #endif
-  
vblank_work->stream->link->panel_config.psr.disallow_replay &&
   vblank_work->acrtc->dm_irq_params.allow_psr_entry) {
amdgpu_dm_psr_enable(vblank_work->stream

[PATCH AUTOSEL 6.7 69/88] drm/amd/display: Only clear symclk otg flag for HDMI

[Sasha Levin]

From: Alvin Lee 

[ Upstream commit dff45f03f508c92cd8eb2050e27b726726b8ae0b ]

[Description]
There is a corner case where the symclk otg flag is cleared
when disabling the phantom pipe for subvp (because the phantom
and main pipe share the same link). This is undesired because
we need the maintain the correct symclk otg flag state for
the main pipe.

For now only clear the flag only for HDMI signal type, since
it's only set for HDMI signal type (phantom is virtual). The
ideal solution is to not clear it if the stream is phantom but
currently there's a bug that doesn't allow us to do this. Once
this issue is fixed the proper fix can be implemented.

Reviewed-by: Samson Tam 
Acked-by: Wayne Lin 
Signed-off-by: Alvin Lee 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c   | 3 ++-
 drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c   | 3 ++-
 drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c   | 3 ++-
 4 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 960a55e06375..c0d2e8454efc 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -2124,7 +2124,8 @@ static void dce110_reset_hw_ctx_wrap(
BREAK_TO_DEBUGGER();
}

pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
-   
pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+   if 
(dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal))
+   
pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
pipe_ctx_old->plane_res.mi, 
dc->current_state->stream_count);
 
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index cdb903116eb7..1fc8436c8130 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1057,7 +1057,8 @@ static void dcn10_reset_back_end_for_pipe(
if (pipe_ctx->stream_res.tg->funcs->set_drr)
pipe_ctx->stream_res.tg->funcs->set_drr(
pipe_ctx->stream_res.tg, NULL);
-   pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+   if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+   pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 
0;
}
 
for (i = 0; i < dc->res_pool->pipe_count; i++)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index c3c83178eb1e..da0181fef411 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2610,7 +2610,8 @@ static void dcn20_reset_back_end_for_pipe(
 * the case where the same symclk is shared across multiple otg
 * instances
 */
-   link->phy_state.symclk_ref_cnts.otg = 0;
+   if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+   link->phy_state.symclk_ref_cnts.otg = 0;
if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
link_hwss->disable_link_output(link,
&pipe_ctx->link_res, 
pipe_ctx->stream->signal);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 97798cee876e..3a40b7359a30 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -523,7 +523,8 @@ static void dcn31_reset_back_end_for_pipe(
if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
pipe_ctx->stream_res.tg, 
&pipe_ctx->stream->timing);
-   pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+   if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+   pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
 
if (pipe_ctx->stream_res.tg->funcs->set_drr)
pipe_ctx->stream_res.tg->funcs->set_drr(
-- 
2.43.0

[PATCH AUTOSEL 6.7 76/88] drm/amd/display: Fixing stream allocation regression

[Sasha Levin]

From: Relja Vojvodic 

[ Upstream commit 292c2116b2ae84c7e799ae340981e60551b18f5e ]

For certain dual display configs that had one display using a 1080p
mode, the DPM level used to drive the configs regressed from DPM 0 to
DPM 3. This was caused by a missing check that should have only limited
the pipe segments on non-phantom pipes. This caused issues with detile
buffer allocation, which dissallow subvp from being used

Tested-by: Daniel Wheeler 
Reviewed-by: Dillon Varone 
Reviewed-by: Martin Leung 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Relja Vojvodic 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index bc5f0db23d0c..a9c45174abed 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -290,7 +290,7 @@ static void override_det_for_subvp(struct dc *dc, struct 
dc_state *context, uint
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = 
&context->res_ctx.pipe_ctx[i];
 
-   if (pipe_ctx->stream && pipe_ctx->plane_state && 
pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
+   if (pipe_ctx->stream && pipe_ctx->plane_state && 
pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM != SUBVP_PHANTOM) {
if (pipe_ctx->stream->timing.v_addressable == 
1080 && pipe_ctx->stream->timing.h_addressable == 1920) {
if (pipe_segments[i] > 4)
pipe_segments[i] = 4;
-- 
2.43.0

[PATCH AUTOSEL 6.7 74/88] drm/amd/display: Fix minor issues in BW Allocation Phase2

[Sasha Levin]

From: Meenakshikumar Somasundaram 

[ Upstream commit aa5dc05340eb97486a631ce6bccb8d020bf6b56b ]

[Why]
Fix minor issues in BW Allocation Phase2.

[How]
- In set_usb4_req_bw_req(), link->dpia_bw_alloc_config.response_ready
  flag should be reset before writing DPCD REQUEST_BW.
- Fix the granularity for value of 2 in get_bw_granularity().
- Removed bandwidth allocation support display fw boot option as
  the fw would read feature enable status from bios.
- Clean up DPIA_EST_BW_CHANGED and DPIA_BW_REQ_SUCCESS cases in
  dpia_handle_bw_alloc_response().
- Removed allocate_usb4_bw and deallocate_usb4_bw.
- Optimized loop in get_lowest_dpia_index().
- Updated link_dp_dpia_allocate_usb4_bandwidth_for_stream() and
  set_usb4_req_bw_req() to always issue request bw.

Tested-by: Daniel Wheeler 
Reviewed-by: PeiChen Huang 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Meenakshikumar Somasundaram 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../dc/link/protocols/link_dp_dpia_bw.c   | 221 --
 .../dc/link/protocols/link_dp_dpia_bw.h   |   4 +-
 2 files changed, 101 insertions(+), 124 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c 
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
index 7581023daa47..d6e1f969bfd5 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
@@ -50,6 +50,7 @@ static bool get_bw_alloc_proceed_flag(struct dc_link *tmp)
&& tmp->hpd_status
&& tmp->dpia_bw_alloc_config.bw_alloc_enabled);
 }
+
 static void reset_bw_alloc_struct(struct dc_link *link)
 {
link->dpia_bw_alloc_config.bw_alloc_enabled = false;
@@ -59,6 +60,11 @@ static void reset_bw_alloc_struct(struct dc_link *link)
link->dpia_bw_alloc_config.bw_granularity = 0;
link->dpia_bw_alloc_config.response_ready = false;
 }
+
+#define BW_GRANULARITY_0 4 // 0.25 Gbps
+#define BW_GRANULARITY_1 2 // 0.5 Gbps
+#define BW_GRANULARITY_2 1 // 1 Gbps
+
 static uint8_t get_bw_granularity(struct dc_link *link)
 {
uint8_t bw_granularity = 0;
@@ -71,16 +77,20 @@ static uint8_t get_bw_granularity(struct dc_link *link)
 
switch (bw_granularity & 0x3) {
case 0:
-   bw_granularity = 4;
+   bw_granularity = BW_GRANULARITY_0;
break;
case 1:
+   bw_granularity = BW_GRANULARITY_1;
+   break;
+   case 2:
default:
-   bw_granularity = 2;
+   bw_granularity = BW_GRANULARITY_2;
break;
}
 
return bw_granularity;
 }
+
 static int get_estimated_bw(struct dc_link *link)
 {
uint8_t bw_estimated_bw = 0;
@@ -93,31 +103,7 @@ static int get_estimated_bw(struct dc_link *link)
 
return bw_estimated_bw * (Kbps_TO_Gbps / 
link->dpia_bw_alloc_config.bw_granularity);
 }
-static bool allocate_usb4_bw(int *stream_allocated_bw, int bw_needed, struct 
dc_link *link)
-{
-   if (bw_needed > 0)
-   *stream_allocated_bw += bw_needed;
-
-   return true;
-}
-static bool deallocate_usb4_bw(int *stream_allocated_bw, int bw_to_dealloc, 
struct dc_link *link)
-{
-   bool ret = false;
-
-   if (*stream_allocated_bw > 0) {
-   *stream_allocated_bw -= bw_to_dealloc;
-   ret = true;
-   } else {
-   //Do nothing for now
-   ret = true;
-   }
 
-   // Unplug so reset values
-   if (!link->hpd_status)
-   reset_bw_alloc_struct(link);
-
-   return ret;
-}
 /*
  * Read all New BW alloc configuration ex: estimated_bw, allocated_bw,
  * granuality, Driver_ID, CM_Group, & populate the BW allocation structs
@@ -128,7 +114,12 @@ static void init_usb4_bw_struct(struct dc_link *link)
// Init the known values
link->dpia_bw_alloc_config.bw_granularity = get_bw_granularity(link);
link->dpia_bw_alloc_config.estimated_bw = get_estimated_bw(link);
+
+   DC_LOG_DEBUG("%s: bw_granularity(%d), estimated_bw(%d)\n",
+   __func__, link->dpia_bw_alloc_config.bw_granularity,
+   link->dpia_bw_alloc_config.estimated_bw);
 }
+
 static uint8_t get_lowest_dpia_index(struct dc_link *link)
 {
const struct dc *dc_struct = link->dc;
@@ -141,12 +132,15 @@ static uint8_t get_lowest_dpia_index(struct dc_link *link)
dc_struct->links[i]->ep_type != 
DISPLAY_ENDPOINT_USB4_DPIA)
continue;
 
-   if (idx > dc_struct->links[i]->link_index)
+   if (idx > dc_struct->links[i]->link_index) {
idx = dc_struct->links[i]->link_index;
+   break;
+   }
}
 
return idx;
 }
+
 /*
  * Get the Max Available BW or Max Estimated BW for each Host Router
  *
@@ -186,6 +180,7 @@ static int get_host_router_total_bw(st

[PATCH AUTOSEL 6.7 75/88] drm/amdgpu: Let KFD sync with VM fences

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit ec9ba4821fa52b5efdbc4cdf0a77497990655231 ]

Change the rules for amdgpu_sync_resv to let KFD synchronize with VM
fences on page table reservations. This fixes intermittent memory
corruption after evictions when using amdgpu_vm_handle_moved to update
page tables for VM mappings managed through render nodes.

Signed-off-by: Felix Kuehling 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index dcd8c066bc1f..1b013a44ca99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -191,7 +191,8 @@ static bool amdgpu_sync_test_fence(struct amdgpu_device 
*adev,
 
/* Never sync to VM updates either. */
if (fence_owner == AMDGPU_FENCE_OWNER_VM &&
-   owner != AMDGPU_FENCE_OWNER_UNDEFINED)
+   owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
+   owner != AMDGPU_FENCE_OWNER_KFD)
return false;
 
/* Ignore fences depending on the sync mode */
-- 
2.43.0

[PATCH AUTOSEL 6.7 66/88] drm/amd/display: make flip_timestamp_in_us a 64-bit variable

[Sasha Levin]

From: Josip Pavic 

[ Upstream commit 6fb12518ca58412dc51054e2a7400afb41328d85 ]

[Why]
This variable currently overflows after about 71 minutes. This doesn't
cause any known functional issues but it does make debugging more
difficult.

[How]
Make it a 64-bit variable.

Reviewed-by: Aric Cyr 
Acked-by: Wayne Lin 
Signed-off-by: Josip Pavic 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index e2a3aa8812df..811474f4419b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -244,7 +244,7 @@ enum pixel_format {
 #define DC_MAX_DIRTY_RECTS 3
 struct dc_flip_addrs {
struct dc_plane_address address;
-   unsigned int flip_timestamp_in_us;
+   unsigned long long flip_timestamp_in_us;
bool flip_immediate;
/* TODO: add flip duration for FreeSync */
bool triplebuffer_flips;
-- 
2.43.0

[PATCH AUTOSEL 6.7 68/88] drm/amd/display: Fix lightup regression with DP2 single display configs

[Sasha Levin]

From: Michael Strauss 

[ Upstream commit 5a82b8d6c05f9b30828ede1b103b9ee5cb5c912e ]

[WHY]
Previous fix for multiple displays downstream of DP2 MST hub caused regression

[HOW]
Match sink IDs instead of sink struct addresses

Reviewed-by: Nicholas Kazlauskas 
Reviewed-by: Charlene Liu 
Acked-by: Wayne Lin 
Signed-off-by: Michael Strauss 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c
index 2498b8341199..d6a68484153c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c
@@ -157,6 +157,14 @@ bool is_dp2p0_output_encoder(const struct pipe_ctx 
*pipe_ctx)
 {
/* If this assert is hit then we have a link encoder dynamic management 
issue */
ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? 
pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
+   /* Count MST hubs once by treating only 1st remote sink in topology as 
an encoder */
+   if (pipe_ctx->stream->link && pipe_ctx->stream->link->remote_sinks[0]) {
+   return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
+   pipe_ctx->link_res.hpo_dp_link_enc &&
+   dc_is_dp_signal(pipe_ctx->stream->signal) &&
+   (pipe_ctx->stream->link->remote_sinks[0]->sink_id == 
pipe_ctx->stream->sink->sink_id));
+   }
+
return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
pipe_ctx->link_res.hpo_dp_link_enc &&
dc_is_dp_signal(pipe_ctx->stream->signal));
-- 
2.43.0

[PATCH AUTOSEL 6.7 67/88] drm/amd/display: fix usb-c connector_type

[Sasha Levin]

From: Allen Pan 

[ Upstream commit 0d26644bc57d8737c8e2fb3145366f7d0b941935 ]

[why]
BIOS switches to use USB-C connector type 0x18, but VBIOS's
objectInfo table not supported yet. driver needs to patch it
based on enc_cap from system integration info table.

Reviewed-by: Charlene Liu 
Acked-by: Wayne Lin 
Signed-off-by: Allen Pan 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c| 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c
index f91e08895275..da94e5309fba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c
@@ -256,6 +256,10 @@ void dcn35_link_encoder_construct(
enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = 
bp_cap_info.DP_UHBR10_EN;
enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = 
bp_cap_info.DP_UHBR13_5_EN;
enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = 
bp_cap_info.DP_UHBR20_EN;
+   if (bp_cap_info.DP_IS_USB_C) {
+   /*BIOS not switch to use CONNECTOR_ID_USBC = 24 yet*/
+   enc10->base.features.flags.bits.DP_IS_USB_C = 1;
+   }
 
} else {
DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS 
with error code %d!\n",
@@ -264,4 +268,5 @@ void dcn35_link_encoder_construct(
}
if (enc10->base.ctx->dc->debug.hdmi20_disable)
enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
+
 }
-- 
2.43.0

[PATCH AUTOSEL 6.7 58/88] drm/amdgpu: fix ftrace event amdgpu_bo_move always move on same heap

[Sasha Levin]

From: "Wang, Beyond" 

[ Upstream commit 94aeb4117343d072e3a35b9595bcbfc0058ee724 ]

Issue: during evict or validate happened on amdgpu_bo, the 'from' and
'to' is always same in ftrace event of amdgpu_bo_move

where calling the 'trace_amdgpu_bo_move', the comment says move_notify
is called before move happens, but actually it is called after move
happens, here the new_mem is same as bo->resource

Fix: move trace_amdgpu_bo_move from move_notify to amdgpu_bo_move

Signed-off-by: Wang, Beyond 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 13 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  4 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  5 +++--
 3 files changed, 5 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5ad03f2afdb4..425cebcc5cbf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1245,19 +1245,15 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void 
*buffer,
  * amdgpu_bo_move_notify - notification about a memory move
  * @bo: pointer to a buffer object
  * @evict: if this move is evicting the buffer from the graphics address space
- * @new_mem: new information of the bufer object
  *
  * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
  * bookkeeping.
  * TTM driver callback which is called when ttm moves a buffer.
  */
-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
-  bool evict,
-  struct ttm_resource *new_mem)
+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)
 {
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct amdgpu_bo *abo;
-   struct ttm_resource *old_mem = bo->resource;
 
if (!amdgpu_bo_is_amdgpu_bo(bo))
return;
@@ -1274,13 +1270,6 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
/* remember the eviction */
if (evict)
atomic64_inc(&adev->num_evictions);
-
-   /* update statistics */
-   if (!new_mem)
-   return;
-
-   /* move_notify is called before move happens */
-   trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 }
 
 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index d28e21baef16..a3ea8a82db23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -344,9 +344,7 @@ int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void 
*metadata,
 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
   size_t buffer_size, uint32_t *metadata_size,
   uint64_t *flags);
-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
-  bool evict,
-  struct ttm_resource *new_mem);
+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict);
 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index ab4a762aed5b..75c9fd2c6c2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -545,10 +545,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, 
bool evict,
return r;
}
 
+   trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 out:
/* update statistics */
atomic64_add(bo->base.size, &adev->num_bytes_moved);
-   amdgpu_bo_move_notify(bo, evict, new_mem);
+   amdgpu_bo_move_notify(bo, evict);
return 0;
 }
 
@@ -1553,7 +1554,7 @@ static int amdgpu_ttm_access_memory(struct 
ttm_buffer_object *bo,
 static void
 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
 {
-   amdgpu_bo_move_notify(bo, false, NULL);
+   amdgpu_bo_move_notify(bo, false);
 }
 
 static struct ttm_device_funcs amdgpu_bo_driver = {
-- 
2.43.0

[PATCH] drm/amdgpu: covert some variable sized arrays to [] style

[Alex Deucher]

Replace [1] with [].  Silences UBSAN warnings.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3107
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/include/pptable.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/pptable.h 
b/drivers/gpu/drm/amd/include/pptable.h
index 5aac8d545bdc..ef3feb0b6674 100644
--- a/drivers/gpu/drm/amd/include/pptable.h
+++ b/drivers/gpu/drm/amd/include/pptable.h
@@ -491,7 +491,7 @@ typedef struct _ClockInfoArray{
 //sizeof(ATOM_PPLIB_CLOCK_INFO)
 UCHAR ucEntrySize;
 
-UCHAR clockInfo[1];
+UCHAR clockInfo[];
 }ClockInfoArray;
 
 typedef struct _NonClockInfoArray{
@@ -501,7 +501,7 @@ typedef struct _NonClockInfoArray{
 //sizeof(ATOM_PPLIB_NONCLOCK_INFO)
 UCHAR ucEntrySize;
 
-ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
+ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[];
 }NonClockInfoArray;
 
 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
-- 
2.42.0

[PATCH AUTOSEL 6.7 51/88] drm/amd/display: Force p-state disallow if leaving no plane config

[Sasha Levin]

From: Alvin Lee 

[ Upstream commit 9a902a9073c287353e25913c0761bfed49d75a88 ]

[Description]
- When we're in a no plane config, DCN is always asserting
  P-State allow
- This creates a scenario where the P-State blackout can start
  just as VUPDATE takes place and transitions the DCN config to
  a one where one or more HUBP's are active which can result in
  underflow
- To fix this issue, force p-state disallow and unforce after
  the transition from no planes case -> one or more planes active

Reviewed-by: Samson Tam 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alvin Lee 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c   | 20 +++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 608221b0dd5d..c3c83178eb1e 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -1877,6 +1877,8 @@ void dcn20_program_front_end_for_ctx(
int i;
struct dce_hwseq *hws = dc->hwseq;
DC_LOGGER_INIT(dc->ctx->logger);
+   unsigned int prev_hubp_count = 0;
+   unsigned int hubp_count = 0;
 
if (resource_is_pipe_topology_changed(dc->current_state, context))
resource_log_pipe_topology_update(dc, context);
@@ -1894,6 +1896,20 @@ void dcn20_program_front_end_for_ctx(
}
}
 
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
+   prev_hubp_count++;
+   if (context->res_ctx.pipe_ctx[i].plane_state)
+   hubp_count++;
+   }
+
+   if (prev_hubp_count == 0 && hubp_count > 0) {
+   if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+   
dc->res_pool->hubbub->funcs->force_pstate_change_control(
+   dc->res_pool->hubbub, true, false);
+   udelay(500);
+   }
+
/* Set pipe update flags and lock pipes */
for (i = 0; i < dc->res_pool->pipe_count; i++)

dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
@@ -2039,6 +2055,10 @@ void dcn20_post_unlock_program_front_end(
}
}
 
+   if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+   dc->res_pool->hubbub->funcs->force_pstate_change_control(
+   dc->res_pool->hubbub, false, false);
+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 
-- 
2.43.0

[PATCH AUTOSEL 6.7 52/88] drm/amdkfd: fix mes set shader debugger process management

[Sasha Levin]

From: Jonathan Kim 

[ Upstream commit bd33bb1409b494558a2935f7bbc7842def957fcd ]

MES provides the driver a call to explicitly flush stale process memory
within the MES to avoid a race condition that results in a fatal
memory violation.

When SET_SHADER_DEBUGGER is called, the driver passes a memory address
that represents a process context address MES uses to keep track of
future per-process calls.

Normally, MES will purge its process context list when the last queue
has been removed.  The driver, however, can call SET_SHADER_DEBUGGER
regardless of whether a queue has been added or not.

If SET_SHADER_DEBUGGER has been called with no queues as the last call
prior to process termination, the passed process context address will
still reside within MES.

On a new process call to SET_SHADER_DEBUGGER, the driver may end up
passing an identical process context address value (based on per-process
gpu memory address) to MES but is now pointing to a new allocated buffer
object during KFD process creation.  Since the MES is unaware of this,
access of the passed address points to the stale object within MES and
triggers a fatal memory violation.

The solution is for KFD to explicitly flush the process context address
from MES on process termination.

Note that the flush call and the MES debugger calls use the same MES
interface but are separated as KFD calls to avoid conflicting with each
other.

Signed-off-by: Jonathan Kim 
Tested-by: Alice Wong 
Reviewed-by: Eric Huang 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c   | 31 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h   | 10 +++---
 .../amd/amdkfd/kfd_process_queue_manager.c|  1 +
 drivers/gpu/drm/amd/include/mes_v11_api_def.h |  3 +-
 4 files changed, 40 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 9ddbf1494326..30c010836658 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -886,6 +886,11 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device 
*adev,
op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;
op_input.set_shader_debugger.process_context_addr = 
process_context_addr;
op_input.set_shader_debugger.flags.u32all = flags;
+
+   /* use amdgpu mes_flush_shader_debugger instead */
+   if (op_input.set_shader_debugger.flags.process_ctx_flush)
+   return -EINVAL;
+
op_input.set_shader_debugger.spi_gdbg_per_vmid_cntl = 
spi_gdbg_per_vmid_cntl;
memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,
sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
@@ -905,6 +910,32 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device 
*adev,
return r;
 }
 
+int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
+uint64_t process_context_addr)
+{
+   struct mes_misc_op_input op_input = {0};
+   int r;
+
+   if (!adev->mes.funcs->misc_op) {
+   DRM_ERROR("mes flush shader debugger is not supported!\n");
+   return -EINVAL;
+   }
+
+   op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;
+   op_input.set_shader_debugger.process_context_addr = 
process_context_addr;
+   op_input.set_shader_debugger.flags.process_ctx_flush = true;
+
+   amdgpu_mes_lock(&adev->mes);
+
+   r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+   if (r)
+   DRM_ERROR("failed to set_shader_debugger\n");
+
+   amdgpu_mes_unlock(&adev->mes);
+
+   return r;
+}
+
 static void
 amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,
   struct amdgpu_ring *ring,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index a27b424ffe00..c2c88b772361 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -291,9 +291,10 @@ struct mes_misc_op_input {
uint64_t process_context_addr;
union {
struct {
-   uint64_t single_memop : 1;
-   uint64_t single_alu_op : 1;
-   uint64_t reserved: 30;
+   uint32_t single_memop : 1;
+   uint32_t single_alu_op : 1;
+   uint32_t reserved: 29;
+   uint32_t process_ctx_flush: 1;
};
uint32_t u32all;
} flags;
@@ -369,7 +370,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device 
*adev,
const uint32_t *tcp_watch_cntl,
uint32_t flags,
   

[PATCH AUTOSEL 6.7 50/88] drm/amd/display: For prefetch mode > 0, extend prefetch if possible

[Sasha Levin]

From: Alvin Lee 

[ Upstream commit dd4e4bb28843393065eed279e869fac248d03f0f ]

[Description]
For mode programming we want to extend the prefetch as much as possible
(up to oto, or as long as we can for equ) if we're not already applying
the 60us prefetch requirement. This is to avoid intermittent underflow
issues during prefetch.

The prefetch extension is applied under the following scenarios:
1. We're in prefetch mode 1 (i.e. we don't support MCLK switch in blank)
2. We're using subvp or drr methods of p-state switch, in which case we
   we don't care if prefetch takes up more of the blanking time

Mode programming typically chooses the smallest prefetch time possible
(i.e. highest bandwidth during prefetch) presumably to create margin between
p-states / c-states that happen in vblank and prefetch. Therefore we only
apply this prefetch extension when p-state in vblank is not required (UCLK
p-states take up the most vblank time).

Reviewed-by: Jun Lei 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alvin Lee 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../dc/dml/dcn32/display_mode_vba_32.c|  3 ++
 .../dc/dml/dcn32/display_mode_vba_util_32.c   | 33 +++
 .../dc/dml/dcn32/display_mode_vba_util_32.h   |  1 +
 3 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index cbdfb762c10c..6c84b0fa40f4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -813,6 +813,8 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman

(v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||

v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= 
DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?

mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
+   
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]
 > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false,
+
/* Output */
&v->DSTXAfterScaler[k],
&v->DSTYAfterScaler[k],
@@ -3317,6 +3319,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l

v->SwathHeightCThisState[k], v->TWait,

(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= 
DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?

mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
+   
mode_lib->vba.PrefetchModePerState[i][j] > 0 || 
mode_lib->vba.DRAMClockChangeRequirementFinal == false,
 
/* Output */

&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index d940dfa5ae43..80fccd4999a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -3423,6 +3423,7 @@ bool dml32_CalculatePrefetchSchedule(
unsigned int SwathHeightC,
double TWait,
double TPreReq,
+   bool ExtendPrefetchIfPossible,
/* Output */
double   *DSTXAfterScaler,
double   *DSTYAfterScaler,
@@ -3892,12 +3893,32 @@ bool dml32_CalculatePrefetchSchedule(
/* Clamp to oto for bandwidth calculation */
LinesForPrefetchBandwidth = dst_y_prefetch_oto;
} else {
-   *DestinationLinesForPrefetch = dst_y_prefetch_equ;
-   TimeForFetchingMetaPTE = Tvm_equ;
-   TimeForFetchingRowInVBlank = Tr0_equ;
-   *PrefetchBandwidth = prefetch_bw_equ;
-   /* Clamp to equ for bandwidth calculation */
-   LinesForPrefetchBandwidth = dst_y_prefetch_equ;
+   /* For mode programming we want to extend the prefetch 
as much as possible
+* (up to oto, or as long as we can for equ) if we're 
not already applying
+* the 60us prefetch requirement. This is to avoid 
intermittent underflow
+* issues during prefetch.
+  

[PATCH AUTOSEL 6.7 23/88] drm/amd/display: Fix writeback_info is not removed

[Sasha Levin]

From: Alex Hung 

[ Upstream commit ab37b88ed9de9de8d582683f7ea17059f1251a7f ]

[WHY]
Counter j was not updated to present the num of writeback_info when
writeback pipes are removed.

[HOW]
update j (num of writeback info) under the correct condition.

Tested-by: Daniel Wheeler 
Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 5055af147c20..37dc280e5566 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -497,11 +497,12 @@ bool dc_stream_remove_writeback(struct dc *dc,
if (stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst)
stream->writeback_info[i].wb_enabled = false;
 
-   if (j < i)
-   /* trim the array */
+   /* trim the array */
+   if (j < i) {
memcpy(&stream->writeback_info[j], 
&stream->writeback_info[i],
sizeof(struct 
dc_writeback_info));
-   j++;
+   j++;
+   }
}
}
stream->num_wb_info = j;
-- 
2.43.0

[PATCH AUTOSEL 6.7 22/88] drm/amd/display: Fix writeback_info never got updated

[Sasha Levin]

From: Alex Hung 

[ Upstream commit c09919e6ea5fefd49d8b7b54aa5b222937163108 ]

[WHY]
wb_enabled field is set to false before it is used, and the following
code will never be executed.

[HOW]
Setting wb_enable to false after all removal work is completed.

Tested-by: Daniel Wheeler 
Reviewed-by: Harry Wentland 
Signed-off-by: Alex Hung 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 13 -
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 4bdf105d1d71..5055af147c20 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -490,18 +490,13 @@ bool dc_stream_remove_writeback(struct dc *dc,
return false;
}
 
-// stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
-   for (i = 0; i < stream->num_wb_info; i++) {
-   /*dynamic update*/
-   if (stream->writeback_info[i].wb_enabled &&
-   stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst) {
-   stream->writeback_info[i].wb_enabled = false;
-   }
-   }
-
/* remove writeback info for disabled writeback pipes from stream */
for (i = 0, j = 0; i < stream->num_wb_info; i++) {
if (stream->writeback_info[i].wb_enabled) {
+
+   if (stream->writeback_info[i].dwb_pipe_inst == 
dwb_pipe_inst)
+   stream->writeback_info[i].wb_enabled = false;
+
if (j < i)
/* trim the array */
memcpy(&stream->writeback_info[j], 
&stream->writeback_info[i],
-- 
2.43.0

[PATCH AUTOSEL 6.7 21/88] drm/amd/display: add support for DTO genarated dscclk

[Sasha Levin]

From: Wenjing Liu 

[ Upstream commit 08a32addf17317b9fac55be9b31275cbf6e41fb7 ]

Current implementation will choose to use refclk as dscclk. This is not
recommended by hardware team as refclk is a fixed value which could
cause unnecessary power consumption or it could be not enough for large
DSC timings. So we are adding new interfaces so we could switch to use
dynamically generated DSCCLK by DTO. So DSCCLK is programmable based on
current pixel clock and dispclk.

Tested-by: Daniel Wheeler 
Reviewed-by: Chaitanya Dhere 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Wenjing Liu 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c   | 25 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |  4 +++
 .../gpu/drm/amd/display/dc/link/link_dpms.c   | 27 ++-
 3 files changed, 55 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index c1a9b746c43f..0f0972ad441a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -995,9 +995,22 @@ static int calc_mpc_flow_ctrl_cnt(const struct 
dc_stream_state *stream,
 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 {
struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+   struct dc *dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;
struct pipe_ctx *odm_pipe;
int opp_cnt = 1;
+   struct dccg *dccg = dc->res_pool->dccg;
+   /* It has been found that when DSCCLK is lower than 16Mhz, we will get 
DCN
+* register access hung. When DSCCLk is based on refclk, DSCCLk is 
always a
+* fixed value higher than 16Mhz so the issue doesn't occur. When 
DSCCLK is
+* generated by DTO, DSCCLK would be based on 1/3 dispclk. For small 
timings
+* with DSC such as 480p60Hz, the dispclk could be low enough to trigger
+* this problem. We are implementing a workaround here to keep using 
dscclk
+* based on fixed value refclk when timing is smaller than 3x16Mhz (i.e
+* 48Mhz) pixel clock to avoid hitting this problem.
+*/
+   bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&
+   stream->timing.pix_clk_100hz > 48;
 
ASSERT(dsc);
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = 
odm_pipe->next_odm_pipe)
@@ -1020,12 +1033,16 @@ static void update_dsc_on_stream(struct pipe_ctx 
*pipe_ctx, bool enable)
 
dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+   if (should_use_dto_dscclk)
+   dccg->funcs->set_dto_dscclk(dccg, dsc->inst);
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = 
odm_pipe->next_odm_pipe) {
struct display_stream_compressor *odm_dsc = 
odm_pipe->stream_res.dsc;
 
ASSERT(odm_dsc);
odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, 
&dsc_optc_cfg);
odm_dsc->funcs->dsc_enable(odm_dsc, 
odm_pipe->stream_res.opp->inst);
+   if (should_use_dto_dscclk)
+   dccg->funcs->set_dto_dscclk(dccg, 
odm_dsc->inst);
}
dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
dsc_cfg.pic_width *= opp_cnt;
@@ -1045,9 +1062,13 @@ static void update_dsc_on_stream(struct pipe_ctx 
*pipe_ctx, bool enable)
OPTC_DSC_DISABLED, 0, 0);
 
/* disable DSC block */
+   if (dccg->funcs->set_ref_dscclk)
+   dccg->funcs->set_ref_dscclk(dccg, 
pipe_ctx->stream_res.dsc->inst);
dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = 
odm_pipe->next_odm_pipe) {
ASSERT(odm_pipe->stream_res.dsc);
+   if (dccg->funcs->set_ref_dscclk)
+   dccg->funcs->set_ref_dscclk(dccg, 
odm_pipe->stream_res.dsc->inst);

odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
}
}
@@ -1130,6 +1151,10 @@ void dcn32_update_odm(struct dc *dc, struct dc_state 
*context, struct pipe_ctx *
if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe 
&&

current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
struct display_stream_compressor *dsc = 
current_pipe_ctx->next_odm_pipe->stream_res.dsc;
+   struct dccg *dccg = dc->res_pool->dccg;
+
+   if (dccg->funcs->set_ref_dscclk)
+  

[PATCH AUTOSEL 6.7 17/88] drm/amd/display: initialize all the dpm level's stutter latency

[Sasha Levin]

From: Charlene Liu 

[ Upstream commit 885c71ad791c1709f668a37f701d33e6872a902f ]

Fix issue when override level bigger than default. Levels 5, 6, and 7
had zero stutter latency, this is because override level being
initialized after stutter latency inits.

Tested-by: Daniel Wheeler 
Reviewed-by: Syed Hassan 
Reviewed-by: Allen Pan 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Charlene Liu 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index db06a5b749b4..279e7605a0a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -341,6 +341,9 @@ void dml2_init_soc_states(struct dml2_context *dml2, const 
struct dc *in_dc,
break;
}
 
+   if (dml2->config.bbox_overrides.clks_table.num_states)
+   p->in_states->num_states = 
dml2->config.bbox_overrides.clks_table.num_states;
+
/* Override from passed values, if available */
for (i = 0; i < p->in_states->num_states; i++) {
if (dml2->config.bbox_overrides.sr_exit_latency_us) {
@@ -397,7 +400,6 @@ void dml2_init_soc_states(struct dml2_context *dml2, const 
struct dc *in_dc,
}
/* Copy clocks tables entries, if available */
if (dml2->config.bbox_overrides.clks_table.num_states) {
-   p->in_states->num_states = 
dml2->config.bbox_overrides.clks_table.num_states;
 
for (i = 0; i < 
dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; 
i++) {
p->in_states->state_array[i].dcfclk_mhz = 
dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz;
-- 
2.43.0

[PATCH AUTOSEL 6.7 20/88] drm/amd/display: Fix Replay Desync Error IRQ handler

[Sasha Levin]

From: Dennis Chan 

[ Upstream commit dd5c6362ddcd8bdb07704faff8648593885ecfa1 ]

In previous case, Replay didn't identify the IRQ type, This commit fixes
the issues for the interrupt.

Tested-by: Daniel Wheeler 
Reviewed-by: Robin Chen 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Dennis Chan 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../display/dc/link/protocols/link_dp_irq_handler.c  | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c 
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
index 0c00e94e90b1..9eadc2c7f221 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
@@ -190,9 +190,6 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link)
/*AMD Replay version reuse DP_PSR_ERROR_STATUS for REPLAY_ERROR 
status.*/
union psr_error_status replay_error_status;
 
-   if (link->replay_settings.config.force_disable_desync_error_check)
-   return;
-
if (!link->replay_settings.replay_feature_enabled)
return;
 
@@ -210,9 +207,6 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link)
&replay_error_status.raw,
sizeof(replay_error_status.raw));
 
-   if (replay_configuration.bits.DESYNC_ERROR_STATUS)
-   link->replay_settings.config.received_desync_error_hpd = 1;
-
link->replay_settings.config.replay_error_status.bits.LINK_CRC_ERROR =
replay_error_status.bits.LINK_CRC_ERROR;
link->replay_settings.config.replay_error_status.bits.DESYNC_ERROR =
@@ -225,6 +219,12 @@ static void handle_hpd_irq_replay_sink(struct dc_link 
*link)

link->replay_settings.config.replay_error_status.bits.STATE_TRANSITION_ERROR) {
bool allow_active;
 
+   if 
(link->replay_settings.config.replay_error_status.bits.DESYNC_ERROR)
+   link->replay_settings.config.received_desync_error_hpd 
= 1;
+
+   if 
(link->replay_settings.config.force_disable_desync_error_check)
+   return;
+
/* Acknowledge and clear configuration bits */
dm_helpers_dp_write_dpcd(
link->ctx,
-- 
2.43.0