Re: [PATCH v2] drm/amgpu: Check return value of amdgpu_device_baco_enter/exit

[Lazar, Lijo]

On 2/29/2024 11:49 AM, Ma Jun wrote:
> Check return value of amdgpu_device_baco_enter/exit and print
> warning message because these errors may cause runtime resume failure
> 
> Signed-off-by: Ma Jun 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 --
>  1 file changed, 22 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index e68bd6f8a6a4..4928b588cd12 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -6000,15 +6000,24 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
>  {
>   struct amdgpu_device *adev = drm_to_adev(dev);
>   struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
> + int ret = 0;
>  
> - if (!amdgpu_device_supports_baco(dev))
> - return -ENOTSUPP;
> + if (!amdgpu_device_supports_baco(dev)) {
> + ret = -ENOTSUPP;
> + goto baco_error;
> + }
>  
>   if (ras && adev->ras_enabled &&
>   adev->nbio.funcs->enable_doorbell_interrupt)
>   adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
>  
> - return amdgpu_dpm_baco_enter(adev);
> + ret = amdgpu_dpm_baco_enter(adev);
> +
> +baco_error:
> + if (ret)
> + dev_warn(adev->dev, "warning: device fails to enter baco. 
> ret=%d\n", ret);
> +

This doesn't look like a real case, moreover the warning message is
misleading. If the device doesn't support baco, driver is not supposed
to call it for runpm purpose -
https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c#L2664

Thanks,
Lijo

> + return ret;
>  }
>  
>  int amdgpu_device_baco_exit(struct drm_device *dev)
> @@ -6017,12 +6026,14 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
>   struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
>   int ret = 0;
>  
> - if (!amdgpu_device_supports_baco(dev))
> - return -ENOTSUPP;
> + if (!amdgpu_device_supports_baco(dev)) {
> + ret = -ENOTSUPP;
> + goto baco_error;
> + }
>  
>   ret = amdgpu_dpm_baco_exit(adev);
>   if (ret)
> - return ret;
> + goto baco_error;
>  
>   if (ras && adev->ras_enabled &&
>   adev->nbio.funcs->enable_doorbell_interrupt)
> @@ -6032,7 +6043,11 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
>   adev->nbio.funcs->clear_doorbell_interrupt)
>   adev->nbio.funcs->clear_doorbell_interrupt(adev);
>  
> - return 0;
> +baco_error:
> + if (ret)
> + dev_warn(adev->dev, "warning: device fails to exit from baco. 
> ret=%d\n", ret);
> +
> + return ret;
>  }
>  
>  /**

[PATCH v2] drm/amgpu: Check return value of amdgpu_device_baco_enter/exit

[Ma Jun]

Check return value of amdgpu_device_baco_enter/exit and print
warning message because these errors may cause runtime resume failure

Signed-off-by: Ma Jun 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 --
 1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e68bd6f8a6a4..4928b588cd12 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -6000,15 +6000,24 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
 {
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+   int ret = 0;
 
-   if (!amdgpu_device_supports_baco(dev))
-   return -ENOTSUPP;
+   if (!amdgpu_device_supports_baco(dev)) {
+   ret = -ENOTSUPP;
+   goto baco_error;
+   }
 
if (ras && adev->ras_enabled &&
adev->nbio.funcs->enable_doorbell_interrupt)
adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 
-   return amdgpu_dpm_baco_enter(adev);
+   ret = amdgpu_dpm_baco_enter(adev);
+
+baco_error:
+   if (ret)
+   dev_warn(adev->dev, "warning: device fails to enter baco. 
ret=%d\n", ret);
+
+   return ret;
 }
 
 int amdgpu_device_baco_exit(struct drm_device *dev)
@@ -6017,12 +6026,14 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
int ret = 0;
 
-   if (!amdgpu_device_supports_baco(dev))
-   return -ENOTSUPP;
+   if (!amdgpu_device_supports_baco(dev)) {
+   ret = -ENOTSUPP;
+   goto baco_error;
+   }
 
ret = amdgpu_dpm_baco_exit(adev);
if (ret)
-   return ret;
+   goto baco_error;
 
if (ras && adev->ras_enabled &&
adev->nbio.funcs->enable_doorbell_interrupt)
@@ -6032,7 +6043,11 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
adev->nbio.funcs->clear_doorbell_interrupt)
adev->nbio.funcs->clear_doorbell_interrupt(adev);
 
-   return 0;
+baco_error:
+   if (ret)
+   dev_warn(adev->dev, "warning: device fails to exit from baco. 
ret=%d\n", ret);
+
+   return ret;
 }
 
 /**
-- 
2.34.1

[PATCH V3] Revert "drm/amdgpu: remove vm sanity check from amdgpu_vm_make_compute" for Raven

[Jesse . Zhang]

fix the issue:
"amdgpu: Failed to create process VM object".

[Why]when amdgpu initialized, seq64 do mampping and update bo mapping in vm 
page table.
But when clifo run. It also initializes a vm for a process device through the 
function kfd_process_device_init_vm and ensure the root PD is clean through the 
function amdgpu_vm_pt_is_root_clean.
So they have a conflict, and clinfo  always failed.

v1:
  - remove all the pte_supports_ats stuff from the amdgpu_vm code (Felix)

Signed-off-by: Jesse Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 23 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h|  3 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 56 +--
 3 files changed, 1 insertion(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index ed4a8c5d26d7..d004ace79536 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1385,10 +1385,6 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
struct amdgpu_bo_va_mapping, list);
list_del(>list);
 
-   if (vm->pte_support_ats &&
-   mapping->start < AMDGPU_GMC_HOLE_START)
-   init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
-
r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
   resv, mapping->start, mapping->last,
   init_pte_value, 0, 0, NULL, NULL,
@@ -2264,7 +2260,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
if (r)
return r;
 
-   vm->pte_support_ats = false;
vm->is_compute_context = false;
 
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
@@ -2350,30 +2345,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
  */
 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 {
-   bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
int r;
 
r = amdgpu_bo_reserve(vm->root.bo, true);
if (r)
return r;
 
-   /* Check if PD needs to be reinitialized and do it before
-* changing any other state, in case it fails.
-*/
-   if (pte_support_ats != vm->pte_support_ats) {
-   /* Sanity checks */
-   if (!amdgpu_vm_pt_is_root_clean(adev, vm)) {
-   r = -EINVAL;
-   goto unreserve_bo;
-   }
-
-   vm->pte_support_ats = pte_support_ats;
-   r = amdgpu_vm_pt_clear(adev, vm, to_amdgpu_bo_vm(vm->root.bo),
-  false);
-   if (r)
-   goto unreserve_bo;
-   }
-
/* Update VM state */
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
AMDGPU_VM_USE_CPU_FOR_COMPUTE);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 42f6ddec50c1..9f6b5e1ccf34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -357,9 +357,6 @@ struct amdgpu_vm {
/* Functions to use for VM table updates */
const struct amdgpu_vm_update_funcs *update_funcs;
 
-   /* Flag to indicate ATS support from PTE for GFX9 */
-   boolpte_support_ats;
-
/* Up to 128 pending retry page faults */
DECLARE_KFIFO(faults, u64, 128);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index a160265ddc07..2835cb3f76eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -89,22 +89,6 @@ static unsigned int amdgpu_vm_pt_num_entries(struct 
amdgpu_device *adev,
return AMDGPU_VM_PTE_COUNT(adev);
 }
 
-/**
- * amdgpu_vm_pt_num_ats_entries - return the number of ATS entries in the root 
PD
- *
- * @adev: amdgpu_device pointer
- *
- * Returns:
- * The number of entries in the root page directory which needs the ATS 
setting.
- */
-static unsigned int amdgpu_vm_pt_num_ats_entries(struct amdgpu_device *adev)
-{
-   unsigned int shift;
-
-   shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level);
-   return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
-}
-
 /**
  * amdgpu_vm_pt_entries_mask - the mask to get the entry number of a PD/PT
  *
@@ -379,7 +363,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
struct ttm_operation_ctx ctx = { true, false };
struct amdgpu_vm_update_params params;
struct amdgpu_bo *ancestor = >bo;
-   unsigned int entries, ats_entries;
+   unsigned int entries;
struct amdgpu_bo *bo = >bo;
uint64_t addr;
int r, idx;
@@ -394,27 +378,6 @@ int amdgpu_vm_pt_clear(struct amdgpu_device 

RE: [PATCH V3] Revert "drm/amdgpu: remove vm sanity check from amdgpu_vm_make_compute" for Raven

[Zhang, Jesse(Jie)]

[AMD Official Use Only - General]

Please ignore the patch and will send a new patch out soon.

-Original Message-
From: Jesse.Zhang 
Sent: Thursday, February 29, 2024 1:51 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kuehling, Felix 
; Paneer Selvam, Arunpravin 
; Zhang, Yifan ; Zhang, 
Jesse(Jie) 
Subject: [PATCH V3] Revert "drm/amdgpu: remove vm sanity check from 
amdgpu_vm_make_compute" for Raven

fix the issue:
"amdgpu: Failed to create process VM object".

[Why]when amdgpu initialized, seq64 do mampping and update bo mapping in vm 
page table.
But when clifo run. It also initializes a vm for a process device through the 
function kfd_process_device_init_vm and ensure the root PD is clean through the 
function amdgpu_vm_pt_is_root_clean.
So they have a conflict, and clinfo  always failed.

 v1:
- remove all the pte_supports_ats stuff from the amdgpu_vm code (Felix)

Signed-off-by: Jesse Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 23 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h|  3 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 55 +--
 3 files changed, 1 insertion(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index ed4a8c5d26d7..d004ace79536 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1385,10 +1385,6 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
struct amdgpu_bo_va_mapping, list);
list_del(>list);

-   if (vm->pte_support_ats &&
-   mapping->start < AMDGPU_GMC_HOLE_START)
-   init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
-
r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
   resv, mapping->start, mapping->last,
   init_pte_value, 0, 0, NULL, NULL, @@ 
-2264,7 +2260,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
if (r)
return r;

-   vm->pte_support_ats = false;
vm->is_compute_context = false;

vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & @@ 
-2350,30 +2345,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
  */
 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)  {
-   bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
int r;

r = amdgpu_bo_reserve(vm->root.bo, true);
if (r)
return r;

-   /* Check if PD needs to be reinitialized and do it before
-* changing any other state, in case it fails.
-*/
-   if (pte_support_ats != vm->pte_support_ats) {
-   /* Sanity checks */
-   if (!amdgpu_vm_pt_is_root_clean(adev, vm)) {
-   r = -EINVAL;
-   goto unreserve_bo;
-   }
-
-   vm->pte_support_ats = pte_support_ats;
-   r = amdgpu_vm_pt_clear(adev, vm, to_amdgpu_bo_vm(vm->root.bo),
-  false);
-   if (r)
-   goto unreserve_bo;
-   }
-
/* Update VM state */
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
AMDGPU_VM_USE_CPU_FOR_COMPUTE); diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 42f6ddec50c1..9f6b5e1ccf34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -357,9 +357,6 @@ struct amdgpu_vm {
/* Functions to use for VM table updates */
const struct amdgpu_vm_update_funcs *update_funcs;

-   /* Flag to indicate ATS support from PTE for GFX9 */
-   boolpte_support_ats;
-
/* Up to 128 pending retry page faults */
DECLARE_KFIFO(faults, u64, 128);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index a160265ddc07..f07255532aae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -89,22 +89,6 @@ static unsigned int amdgpu_vm_pt_num_entries(struct 
amdgpu_device *adev,
return AMDGPU_VM_PTE_COUNT(adev);
 }

-/**
- * amdgpu_vm_pt_num_ats_entries - return the number of ATS entries in the root 
PD
- *
- * @adev: amdgpu_device pointer
- *
- * Returns:
- * The number of entries in the root page directory which needs the ATS 
setting.
- */
-static unsigned int amdgpu_vm_pt_num_ats_entries(struct amdgpu_device *adev) -{
-   unsigned int shift;
-
-   shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level);
-   return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
-}
-
 /**
  * amdgpu_vm_pt_entries_mask - the mask to get the entry number of a PD/PT
  *
@@ -394,27 +378,7 @@ int 

[PATCH V3] Revert "drm/amdgpu: remove vm sanity check from amdgpu_vm_make_compute" for Raven

[Jesse . Zhang]

fix the issue:
"amdgpu: Failed to create process VM object".

[Why]when amdgpu initialized, seq64 do mampping and update bo mapping in vm 
page table.
But when clifo run. It also initializes a vm for a process device through the 
function kfd_process_device_init_vm and ensure the root PD is clean through the 
function amdgpu_vm_pt_is_root_clean.
So they have a conflict, and clinfo  always failed.

 v1:
- remove all the pte_supports_ats stuff from the amdgpu_vm code (Felix)

Signed-off-by: Jesse Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 23 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h|  3 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 55 +--
 3 files changed, 1 insertion(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index ed4a8c5d26d7..d004ace79536 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1385,10 +1385,6 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
struct amdgpu_bo_va_mapping, list);
list_del(>list);
 
-   if (vm->pte_support_ats &&
-   mapping->start < AMDGPU_GMC_HOLE_START)
-   init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
-
r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
   resv, mapping->start, mapping->last,
   init_pte_value, 0, 0, NULL, NULL,
@@ -2264,7 +2260,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
if (r)
return r;
 
-   vm->pte_support_ats = false;
vm->is_compute_context = false;
 
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
@@ -2350,30 +2345,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
  */
 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 {
-   bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
int r;
 
r = amdgpu_bo_reserve(vm->root.bo, true);
if (r)
return r;
 
-   /* Check if PD needs to be reinitialized and do it before
-* changing any other state, in case it fails.
-*/
-   if (pte_support_ats != vm->pte_support_ats) {
-   /* Sanity checks */
-   if (!amdgpu_vm_pt_is_root_clean(adev, vm)) {
-   r = -EINVAL;
-   goto unreserve_bo;
-   }
-
-   vm->pte_support_ats = pte_support_ats;
-   r = amdgpu_vm_pt_clear(adev, vm, to_amdgpu_bo_vm(vm->root.bo),
-  false);
-   if (r)
-   goto unreserve_bo;
-   }
-
/* Update VM state */
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
AMDGPU_VM_USE_CPU_FOR_COMPUTE);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 42f6ddec50c1..9f6b5e1ccf34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -357,9 +357,6 @@ struct amdgpu_vm {
/* Functions to use for VM table updates */
const struct amdgpu_vm_update_funcs *update_funcs;
 
-   /* Flag to indicate ATS support from PTE for GFX9 */
-   boolpte_support_ats;
-
/* Up to 128 pending retry page faults */
DECLARE_KFIFO(faults, u64, 128);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index a160265ddc07..f07255532aae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -89,22 +89,6 @@ static unsigned int amdgpu_vm_pt_num_entries(struct 
amdgpu_device *adev,
return AMDGPU_VM_PTE_COUNT(adev);
 }
 
-/**
- * amdgpu_vm_pt_num_ats_entries - return the number of ATS entries in the root 
PD
- *
- * @adev: amdgpu_device pointer
- *
- * Returns:
- * The number of entries in the root page directory which needs the ATS 
setting.
- */
-static unsigned int amdgpu_vm_pt_num_ats_entries(struct amdgpu_device *adev)
-{
-   unsigned int shift;
-
-   shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level);
-   return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
-}
-
 /**
  * amdgpu_vm_pt_entries_mask - the mask to get the entry number of a PD/PT
  *
@@ -394,27 +378,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
}
 
entries = amdgpu_bo_size(bo) / 8;
-   if (!vm->pte_support_ats) {
-   ats_entries = 0;
-
-   } else if (!bo->parent) {
-   ats_entries = amdgpu_vm_pt_num_ats_entries(adev);
-   ats_entries = min(ats_entries, entries);
-   entries -= ats_entries;
-
-   } else {
-   

Re: [PATCH] drm/amdgpu: add deferred error check for UMC v12 address query

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking

Get Outlook for iOS

From: amd-gfx  on behalf of Tao Zhou 

Sent: Thursday, February 29, 2024 11:45:47 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: add deferred error check for UMC v12 address query

Both RAS UE and deferred errors need page retirement.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index 14ef7a24be7b..77af4e25ff46 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -348,7 +348,8 @@ static int umc_v12_0_query_error_address(struct 
amdgpu_device *adev,
 }

 /* calculate error address if ue error is detected */
-   if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)) {
+   if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) ||
+   umc_v12_0_is_deferred_error(adev, mc_umc_status)) {
 mc_umc_addrt0 =
 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);

--
2.34.1

[PATCH] drm/amdgpu: add deferred error check for UMC v12 address query

[Tao Zhou]

Both RAS UE and deferred errors need page retirement.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index 14ef7a24be7b..77af4e25ff46 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -348,7 +348,8 @@ static int umc_v12_0_query_error_address(struct 
amdgpu_device *adev,
}
 
/* calculate error address if ue error is detected */
-   if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)) {
+   if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) ||
+   umc_v12_0_is_deferred_error(adev, mc_umc_status)) {
mc_umc_addrt0 =
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
 
-- 
2.34.1

Re: [PATCH 2/2] drm/amgpu: Check return value of amdgpu_device_baco_enter/exit

[Ma, Jun]

On 2/28/2024 7:58 PM, Lazar, Lijo wrote:
> 
> 
> On 2/28/2024 5:14 PM, Ma Jun wrote:
>> Check return value of amdgpu_device_baco_enter/exit and print
>> warning message because these errors may cause runtime resume failure
>>
>> Signed-off-by: Ma Jun 
>> ---
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++--
>>  1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index 8b83c26dc018..11e089cfb465 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -2705,7 +2705,9 @@ static int amdgpu_pmops_runtime_suspend(struct device 
>> *dev)
>>  } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
>>  /* nothing to do */
>>  } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
>> -amdgpu_device_baco_enter(drm_dev);
>> +ret = amdgpu_device_baco_enter(drm_dev);
>> +if (ret)
>> +dev_warn(>dev, "warning: device fails to enter 
>> baco. ret=%d\n", ret);
>>  }
> 
> If the intention is to print for any baco entry/exit failure, it's
> better to put the print inside enter/exit functions itself. Also, since
> these are triggered through PMFW, any PMFW fail will be printed. So this
> may not be that useful.
> 
Thanks, I will move it into enter/exit functions.
This check is mainly used for other error cases not for PMFW failure.

Regards,
Ma Jun

> Thanks,
> Lijo
> 
>>  
>>  dev_dbg(>dev, "asic/device is runtime suspended\n");
>> @@ -2745,7 +2747,9 @@ static int amdgpu_pmops_runtime_resume(struct device 
>> *dev)
>>   */
>>  pci_set_master(pdev);
>>  } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
>> -amdgpu_device_baco_exit(drm_dev);
>> +ret = amdgpu_device_baco_exit(drm_dev);
>> +if (ret)
>> +dev_warn(>dev, "warning: device fails to exit 
>> from baco. ret=%d\n", ret);
>>  }
>>  ret = amdgpu_device_resume(drm_dev, false);
>>  if (ret) {

RE: [PATCH] drm/amd/swsmu: modify the gfx activity scaling

[Zhang, Yifan]

[AMD Official Use Only - General]

Reviewed-by: Yifan Zhang 

-Original Message-
From: Alex Deucher 
Sent: Wednesday, February 28, 2024 10:25 PM
To: Ma, Li 
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Yifan ; Yu, Lang 

Subject: Re: [PATCH] drm/amd/swsmu: modify the gfx activity scaling

On Wed, Feb 28, 2024 at 6:39 AM Li Ma  wrote:
>
> Add an if condition for gfx activity because the scaling has been changed 
> after smu fw version 5d4600.
> And remove a warning log.
>
> Signed-off-by: Li Ma 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c   | 2 --
>  drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 5 -
>  2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> index 2aa7e9945a0b..7ac9bc0df8fd 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> @@ -229,8 +229,6 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)
> smu->smc_driver_if_version = 
> SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
> break;
> case IP_VERSION(14, 0, 0):
> -   if ((smu->smc_fw_version < 0x5d3a00))
> -   dev_warn(smu->adev->dev, "The PMFW version(%x) is 
> behind in this BIOS!\n", smu->smc_fw_version);
> smu->smc_driver_if_version = 
> SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
> break;
> default:
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 47fdbae4adfc..9310c4758e38 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -261,7 +261,10 @@ static int smu_v14_0_0_get_smu_metrics_data(struct 
> smu_context *smu,
> *value = metrics->MpipuclkFrequency;
> break;
> case METRICS_AVERAGE_GFXACTIVITY:
> -   *value = metrics->GfxActivity / 100;
> +   if ((smu->smc_fw_version > 0x5d4600))
> +   *value = metrics->GfxActivity;
> +   else
> +   *value = metrics->GfxActivity / 100;
> break;
> case METRICS_AVERAGE_VCNACTIVITY:
> *value = metrics->VcnActivity / 100;
> --
> 2.25.1
>

[PATCH 6/6] drm/amd/display: add amdgpu_dm support for DCN351

[Hamza Mahfooz]

Add Display Manager specific changes for DCN3.5.1.

Signed-off-by: Hamza Mahfooz 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 9 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5bbe7d1a53fb..bd8cd3a1325e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1219,6 +1219,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 4):
case IP_VERSION(3, 5, 0):
+   case IP_VERSION(3, 5, 1):
hw_params.dpia_supported = true;
hw_params.disable_dpia = 
adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
break;
@@ -2040,6 +2041,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
case IP_VERSION(3, 2, 0):
case IP_VERSION(3, 2, 1):
case IP_VERSION(3, 5, 0):
+   case IP_VERSION(3, 5, 1):
return 0;
default:
break;
@@ -2160,6 +2162,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
dmub_asic = DMUB_ASIC_DCN321;
break;
case IP_VERSION(3, 5, 0):
+   case IP_VERSION(3, 5, 1):
dmub_asic = DMUB_ASIC_DCN35;
break;
default:
@@ -4489,6 +4492,7 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
case IP_VERSION(3, 2, 1):
case IP_VERSION(2, 1, 0):
case IP_VERSION(3, 5, 0):
+   case IP_VERSION(3, 5, 1):
if (register_outbox_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail;
@@ -4510,6 +4514,7 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
case IP_VERSION(3, 2, 0):
case IP_VERSION(3, 2, 1):
case IP_VERSION(3, 5, 0):
+   case IP_VERSION(3, 5, 1):
psr_feature_enabled = true;
break;
default:
@@ -4527,6 +4532,7 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
case IP_VERSION(3, 2, 0):
case IP_VERSION(3, 2, 1):
case IP_VERSION(3, 5, 0):
+   case IP_VERSION(3, 5, 1):
replay_feature_enabled = true;
break;
default:
@@ -4679,6 +4685,7 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
case IP_VERSION(3, 2, 0):
case IP_VERSION(3, 2, 1):
case IP_VERSION(3, 5, 0):
+   case IP_VERSION(3, 5, 1):
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail;
@@ -4810,6 +4817,7 @@ static int dm_init_microcode(struct amdgpu_device *adev)
fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
break;
case IP_VERSION(3, 5, 0):
+   case IP_VERSION(3, 5, 1):
fw_name_dmub = FIRMWARE_DCN_35_DMUB;
break;
default:
@@ -4935,6 +4943,7 @@ static int dm_early_init(void *handle)
case IP_VERSION(3, 2, 0):
case IP_VERSION(3, 2, 1):
case IP_VERSION(3, 5, 0):
+   case IP_VERSION(3, 5, 1):
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index b54d646a7c73..e339c7a8d541 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -741,6 +741,7 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct 
amdgpu_device *adev,
dc->ctx->dce_version == DCN_VERSION_3_14 ||
dc->ctx->dce_version == DCN_VERSION_3_15 ||
dc->ctx->dce_version == DCN_VERSION_3_5 ||
+   dc->ctx->dce_version == DCN_VERSION_3_51 ||
dc->ctx->dce_version == DCN_VERSION_3_16)
hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, 
i);
-- 
2.43.0

[PATCH 5/6] drm/amd/display: add DC changes for DCN351

[Hamza Mahfooz]

Add DC support for DCN 3.5.1.

Signed-off-by: Hamza Mahfooz 
---
 .../display/dc/bios/command_table_helper2.c   |1 +
 .../gpu/drm/amd/display/dc/core/dc_resource.c |6 +
 .../dc/dcn35/dcn35_dio_stream_encoder.h   |1 +
 drivers/gpu/drm/amd/display/dc/dml/Makefile   |3 +
 .../amd/display/dc/dml/dcn351/dcn351_fpu.c|  574 +
 .../amd/display/dc/dml/dcn351/dcn351_fpu.h|   19 +
 .../gpu/drm/amd/display/dc/gpio/hw_factory.c  |1 +
 .../drm/amd/display/dc/gpio/hw_translate.c|1 +
 drivers/gpu/drm/amd/display/dc/hwss/Makefile  |8 +
 .../amd/display/dc/hwss/dcn351/CMakeLists.txt |4 -
 .../gpu/drm/amd/display/dc/resource/Makefile  |8 +
 .../dc/resource/dcn351/dcn351_resource.c  | 2156 +
 .../dc/resource/dcn351/dcn351_resource.h  |   23 +
 13 files changed, 2801 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h
 delete mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn351/CMakeLists.txt
 create mode 100644 
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.h

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 9d347960e2b0..117fc6d4c1de 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -81,6 +81,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
case DCN_VERSION_3_2:
case DCN_VERSION_3_21:
case DCN_VERSION_3_5:
+   case DCN_VERSION_3_51:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 1b7765bc5e5e..ec4bf9432bdb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -73,6 +73,7 @@
 #include "dcn32/dcn32_resource.h"
 #include "dcn321/dcn321_resource.h"
 #include "dcn35/dcn35_resource.h"
+#include "dcn351/dcn351_resource.h"
 
 #define VISUAL_CONFIRM_BASE_DEFAULT 3
 #define VISUAL_CONFIRM_BASE_MIN 1
@@ -195,6 +196,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id 
asic_id)
break;
case AMDGPU_FAMILY_GC_11_5_0:
dc_version = DCN_VERSION_3_5;
+   if (ASICREV_IS_GC_11_0_4(asic_id.hw_internal_rev))
+   dc_version = DCN_VERSION_3_51;
break;
default:
dc_version = DCE_VERSION_UNKNOWN;
@@ -303,6 +306,9 @@ struct resource_pool *dc_create_resource_pool(struct dc  
*dc,
case DCN_VERSION_3_5:
res_pool = dcn35_create_resource_pool(init_data, dc);
break;
+   case DCN_VERSION_3_51:
+   res_pool = dcn351_create_resource_pool(init_data, dc);
+   break;
 #endif /* CONFIG_DRM_AMD_DC_FP */
default:
break;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h
index 1212fcee38f2..499052329ebb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h
@@ -28,6 +28,7 @@
 #include "dcn30/dcn30_vpg.h"
 #include "dcn30/dcn30_afmt.h"
 #include "stream_encoder.h"
+#include "dcn10/dcn10_link_encoder.h"
 #include "dcn20/dcn20_stream_encoder.h"
 
 /* Register bit field name change */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile 
b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 59ade76ffb18..c4a5efd2dda5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -92,6 +92,7 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := 
$(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_ccflags) 
$(frame_warn_flag)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn321/dcn321_fpu.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn35/dcn35_fpu.o := $(dml_ccflags)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn351/dcn351_fpu.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn302/dcn302_fpu.o := $(dml_ccflags)
@@ -126,6 +127,7 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := 
$(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/dcn32_fpu.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn321/dcn321_fpu.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn35/dcn35_fpu.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn351/dcn351_fpu.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o 

[PATCH 4/6] drm/amd/display: add DCN351 IRQ changes

[Hamza Mahfooz]

Add DCN3.5.1 interrupt support.

Signed-off-by: Hamza Mahfooz 
---
 drivers/gpu/drm/amd/display/dc/irq/Makefile   |  11 +-
 .../dc/irq/dcn351/irq_service_dcn351.c| 409 ++
 .../dc/irq/dcn351/irq_service_dcn351.h|  12 +
 3 files changed, 431 insertions(+), 1 deletion(-)
 create mode 100644 
drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.h

diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile 
b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 076f667a82f6..2d4378780c1a 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -170,4 +170,13 @@ IRQ_DCN35 = irq_service_dcn35.o
 
 AMD_DAL_IRQ_DCN35= $(addprefix $(AMDDALPATH)/dc/irq/dcn35/,$(IRQ_DCN35))
 
-AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN35)
\ No newline at end of file
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN35)
+
+###
+# DCN 351
+###
+IRQ_DCN351 = irq_service_dcn351.o
+
+AMD_DAL_IRQ_DCN351= $(addprefix $(AMDDALPATH)/dc/irq/dcn351/,$(IRQ_DCN351))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN351)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c 
b/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
new file mode 100644
index ..7ec8e0de2f01
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
@@ -0,0 +1,409 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright 2024 Advanced Micro Devices, Inc. */
+
+#include "dm_services.h"
+#include "include/logger_interface.h"
+#include "../dce110/irq_service_dce110.h"
+
+
+#include "dcn/dcn_3_5_1_offset.h"
+#include "dcn/dcn_3_5_1_sh_mask.h"
+
+#include "irq_service_dcn351.h"
+
+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
+
+static enum dc_irq_source to_dal_irq_source_dcn351(
+   struct irq_service *irq_service,
+   uint32_t src_id,
+   uint32_t ext_id)
+{
+   switch (src_id) {
+   case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK1;
+   case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK2;
+   case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK3;
+   case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK4;
+   case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK5;
+   case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
+   return DC_IRQ_SOURCE_VBLANK6;
+   case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC1_VLINE0;
+   case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC2_VLINE0;
+   case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC3_VLINE0;
+   case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC4_VLINE0;
+   case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC5_VLINE0;
+   case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+   return DC_IRQ_SOURCE_DC6_VLINE0;
+   case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP1;
+   case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP2;
+   case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP3;
+   case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP4;
+   case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP5;
+   case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
+   return DC_IRQ_SOURCE_PFLIP6;
+   case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE1;
+   case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE2;
+   case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE3;
+   case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE4;
+   case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE5;
+   case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+   return DC_IRQ_SOURCE_VUPDATE6;
+   case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
+   return DC_IRQ_SOURCE_DMCUB_OUTBOX;
+   case DCN_1_0__SRCID__DC_HPD1_INT:
+   /* generic src_id for all HPD and HPDRX interrupts */
+   switch (ext_id) {
+   case DCN_1_0__CTXID__DC_HPD1_INT:
+   return 

[PATCH 3/6] drm/amd/display: add DMUB source files and changes for DCN351

[Hamza Mahfooz]

DMUB support is required to light-up displays.

Signed-off-by: Hamza Mahfooz 
---
 drivers/gpu/drm/amd/display/dmub/src/Makefile |  1 +
 .../drm/amd/display/dmub/src/dmub_dcn351.c| 34 +++
 .../drm/amd/display/dmub/src/dmub_dcn351.h| 13 +++
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |  4 +++
 4 files changed, 52 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c
 create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.h

diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile 
b/drivers/gpu/drm/amd/display/dmub/src/Makefile
index 08aaf84affaf..50a98448e2e8 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
+++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
@@ -25,6 +25,7 @@ DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o
 DMUB += dmub_dcn31.o dmub_dcn314.o dmub_dcn315.o dmub_dcn316.o
 DMUB += dmub_dcn32.o
 DMUB += dmub_dcn35.o
+DMUB += dmub_dcn351.o
 
 AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
 
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c
new file mode 100644
index ..8f40b9f6706c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright 2024 Advanced Micro Devices, Inc. */
+
+#include "../dmub_srv.h"
+#include "dmub_reg.h"
+#include "dmub_dcn351.h"
+
+#include "dcn/dcn_3_5_1_offset.h"
+#include "dcn/dcn_3_5_1_sh_mask.h"
+
+#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
+#define CTX dmub
+#define REGS dmub->regs_dcn35
+#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
+
+void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)
+{
+   struct dmub_srv_dcn35_regs *regs = dmub->regs_dcn35;
+#define REG_STRUCT regs
+
+#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
+   DMUB_DCN35_REGS()
+   DMCUB_INTERNAL_REGS()
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, 
field);
+   DMUB_DCN35_FIELDS()
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, 
field);
+   DMUB_DCN35_FIELDS()
+#undef DMUB_SF
+#undef REG_STRUCT
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.h 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.h
new file mode 100644
index ..4121fa1b301d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright 2024 Advanced Micro Devices, Inc. */
+
+#ifndef _DMUB_DCN351_H_
+#define _DMUB_DCN351_H_
+
+#include "dmub_dcn35.h"
+
+struct dmub_srv;
+
+void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
+
+#endif /* _DMUB_DCN351_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index cd97983cf759..90e878195d95 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -37,6 +37,7 @@
 #include "dmub_dcn316.h"
 #include "dmub_dcn32.h"
 #include "dmub_dcn35.h"
+#include "dmub_dcn351.h"
 #include "os_types.h"
 /*
  * Note: the DMUB service is standalone. No additional headers should be
@@ -315,6 +316,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum 
dmub_asic asic)
break;
 
case DMUB_ASIC_DCN35:
+   case DMUB_ASIC_DCN351:
dmub->regs_dcn35 = _srv_dcn35_regs;
funcs->configure_dmub_in_system_memory = 
dmub_dcn35_configure_dmub_in_system_memory;
funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd;
@@ -351,6 +353,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum 
dmub_asic asic)
funcs->get_diagnostic_data = 
dmub_dcn35_get_diagnostic_data;
 
funcs->init_reg_offsets = dmub_srv_dcn35_regs_init;
+   if (asic == DMUB_ASIC_DCN351)
+funcs->init_reg_offsets = 
dmub_srv_dcn351_regs_init;
 
funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up;
funcs->should_detect = dmub_dcn35_should_detect;
-- 
2.43.0

[PATCH 1/6] drm/amd/display: add DCN351 version identifiers

[Hamza Mahfooz]

Add DCN3.5.1 ASIC identifiers.

Signed-off-by: Hamza Mahfooz 
---
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   | 1 +
 drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h 
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ff2a65e67bd4..7785908a6676 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -112,6 +112,7 @@ enum dmub_asic {
DMUB_ASIC_DCN32,
DMUB_ASIC_DCN321,
DMUB_ASIC_DCN35,
+   DMUB_ASIC_DCN351,
DMUB_ASIC_MAX,
 };
 
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h 
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index e317089cf6ee..c9ec46c6b4c6 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -250,11 +250,13 @@ enum {
 #define GC_11_0_0_A0 0x1
 #define GC_11_0_2_A0 0x10
 #define GC_11_0_3_A0 0x20
+#define GC_11_0_4_A0 0xC0
 #define GC_11_UNKNOWN 0xFF
 
 #define ASICREV_IS_GC_11_0_0(eChipRev) (eChipRev < GC_11_0_2_A0)
 #define ASICREV_IS_GC_11_0_2(eChipRev) (eChipRev >= GC_11_0_2_A0 && eChipRev < 
GC_11_0_3_A0)
 #define ASICREV_IS_GC_11_0_3(eChipRev) (eChipRev >= GC_11_0_3_A0 && eChipRev < 
GC_11_UNKNOWN)
+#define ASICREV_IS_GC_11_0_4(eChipRev) (eChipRev >= GC_11_0_4_A0 && eChipRev < 
GC_11_UNKNOWN)
 
 /*
  * ASIC chip ID
-- 
2.43.0

[PATCH] drm/amd/display: handle range offsets in VRR ranges

[Alex Deucher]

Need to check the offset bits for values greater than 255.

v2: also update amdgpu_dm_connector values.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3203
Signed-off-by: Alex Deucher 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 ++-
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 32efce81a5a74..4e4cbf2e33dd2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -11292,14 +11292,23 @@ void amdgpu_dm_update_freesync_caps(struct 
drm_connector *connector,
if (range->flags != 1)
continue;
 
-   amdgpu_dm_connector->min_vfreq = 
range->min_vfreq;
-   amdgpu_dm_connector->max_vfreq = 
range->max_vfreq;
-   amdgpu_dm_connector->pixel_clock_mhz =
-   range->pixel_clock_mhz * 10;
-
connector->display_info.monitor_range.min_vfreq 
= range->min_vfreq;
connector->display_info.monitor_range.max_vfreq 
= range->max_vfreq;
 
+   if (edid->revision >= 4) {
+   if (data->pad2 & 
DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
+   
connector->display_info.monitor_range.min_vfreq += 255;
+   if (data->pad2 & 
DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
+   
connector->display_info.monitor_range.max_vfreq += 255;
+   }
+
+   amdgpu_dm_connector->min_vfreq =
+   
connector->display_info.monitor_range.min_vfreq;
+   amdgpu_dm_connector->max_vfreq =
+   
connector->display_info.monitor_range.max_vfreq;
+   amdgpu_dm_connector->pixel_clock_mhz =
+   range->pixel_clock_mhz * 10;
+
break;
}
 
-- 
2.44.0

[PATCH] drm/amd/display: handle range offsets in VRR ranges

[Alex Deucher]

Need to check the offset bits for values greater than 255.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3203
Signed-off-by: Alex Deucher 
---

Can we just drop this code (at least for DP)?  drm_edid.c already handles
this properly in get_monitor_range().

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 32efce81a5a74..c4fc65ba6b29b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -11300,6 +11300,13 @@ void amdgpu_dm_update_freesync_caps(struct 
drm_connector *connector,
connector->display_info.monitor_range.min_vfreq 
= range->min_vfreq;
connector->display_info.monitor_range.max_vfreq 
= range->max_vfreq;
 
+   if (edid->revision >= 4) {
+   if (data->pad2 & 
DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
+   
connector->display_info.monitor_range.min_vfreq += 255;
+   if (data->pad2 & 
DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
+   
connector->display_info.monitor_range.max_vfreq += 255;
+   }
+
break;
}
 
-- 
2.44.0

Re: [PATCH] Revert "drm/amdgpu: remove vm sanity check from amdgpu_vm_make_compute" for Raven

[Felix Kuehling]

On 2024-02-28 01:41, Christian König wrote:

Am 28.02.24 um 06:04 schrieb Jesse.Zhang:

fix the issue when run clinfo:
"amdgpu: Failed to create process VM object".

when amdgpu initialized, seq64 do mampping and update bo mapping in 
vm page table.
But when clifo run. It also initializes a vm for a process device 
through the function kfd_process_device_init_vm
and ensure the root PD is clean through the function 
amdgpu_vm_pt_is_root_clean.

So they have a conflict, and clinfo  always failed.


Big NAK for this, you removed the check but didn't solved the problem 
in any way.


When Raven still needs the ats feature than it is intentional that 
this fails.


I agree. I think we should just remove all the pte_supports_ats stuff 
from the amdgpu_vm code. We no longer use IOMMUv2. So there is no point 
setting invalid PTEs to fail over to ATS any more. As far as I can see, 
this will require changes in amdgpu_vm_clear_freed, amdgpu_vm_init, 
amdgpu_vm_make_compute. Then you can remove amdgpu_vm.pte_support_ats 
from the struct and remove amdgpu_vm_pt_is_root_clean.


Regards,
  Felix




Regards,
Christian.



Signed-off-by: Jesse Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 --
  1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index ed4a8c5d26d7..0bc0bc75be15 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2361,12 +2361,6 @@ int amdgpu_vm_make_compute(struct 
amdgpu_device *adev, struct amdgpu_vm *vm)

   * changing any other state, in case it fails.
   */
  if (pte_support_ats != vm->pte_support_ats) {
-    /* Sanity checks */
-    if (!amdgpu_vm_pt_is_root_clean(adev, vm)) {
-    r = -EINVAL;
-    goto unreserve_bo;
-    }
-
  vm->pte_support_ats = pte_support_ats;
  r = amdgpu_vm_pt_clear(adev, vm, to_amdgpu_bo_vm(vm->root.bo),
 false);

[PATCH 30/34] drm/amd/display: Backup and restore only on full updates

[Alex Hung]

From: Alvin Lee 

[WHY & HOW]
Since the backup and restore for plane and stream states has
a significant amount of data to copy, we will change the backup
and restore sequence to only take place during full updates.

We will also move the scratch memory to struct dc instead of dc_state
to avoid needing to allocate large amounts of memory every time
we create a new DC state.

Reviewed-by: Wenjing Liu 
Acked-by: Alex Hung 
Signed-off-by: Alvin Lee 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  10 +-
 .../gpu/drm/amd/display/dc/core/dc_state.c|   1 -
 drivers/gpu/drm/amd/display/dc/dc.h   | 164 ++
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  22 ---
 4 files changed, 100 insertions(+), 97 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d8967087335e..2105e4ba3384 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3162,9 +3162,10 @@ static bool update_planes_and_stream_state(struct dc *dc,
}
 
context = dc->current_state;
-   backup_planes_and_stream_state(>current_state->scratch, stream);
update_type = dc_check_update_surfaces_for_stream(
dc, srf_updates, surface_count, stream_update, 
stream_status);
+   if (update_type == UPDATE_TYPE_FULL)
+   backup_planes_and_stream_state(>scratch.current_state, 
stream);
 
/* update current stream with the new updates */
copy_stream_update_to_stream(dc, context, stream, stream_update);
@@ -3267,7 +3268,8 @@ static bool update_planes_and_stream_state(struct dc *dc,
 
*new_context = context;
*new_update_type = update_type;
-   backup_planes_and_stream_state(>scratch, stream);
+   if (update_type == UPDATE_TYPE_FULL)
+   backup_planes_and_stream_state(>scratch.new_state, stream);
 
return true;
 
@@ -4321,7 +4323,7 @@ static bool 
commit_minimal_transition_based_on_current_context(struct dc *dc,
 * This restores back the original stream and plane states associated
 * with the current state.
 */
-   restore_planes_and_stream_state(>current_state->scratch, stream);
+   restore_planes_and_stream_state(>scratch.current_state, stream);
intermediate_context = create_minimal_transition_state(dc,
dc->current_state, );
if (intermediate_context) {
@@ -4348,7 +4350,7 @@ static bool 
commit_minimal_transition_based_on_current_context(struct dc *dc,
 * Restore stream and plane states back to the values associated with
 * new context.
 */
-   restore_planes_and_stream_state(_context->scratch, stream);
+   restore_planes_and_stream_state(>scratch.new_state, stream);
return success;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index 5cc7f8da209c..cce4e1c465b6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -310,7 +310,6 @@ void dc_state_destruct(struct dc_state *state)
memset(state->dc_dmub_cmd, 0, sizeof(state->dc_dmub_cmd));
state->dmub_cmd_count = 0;
memset(>perf_params, 0, sizeof(state->perf_params));
-   memset(>scratch, 0, sizeof(state->scratch));
 }
 
 void dc_state_retain(struct dc_state *state)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 09c6a393642a..9629bd9252b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1004,76 +1004,6 @@ struct dc_current_properties {
unsigned int cursor_size_limit;
 };
 
-struct dc {
-   struct dc_debug_options debug;
-   struct dc_versions versions;
-   struct dc_caps caps;
-   struct dc_cap_funcs cap_funcs;
-   struct dc_config config;
-   struct dc_bounding_box_overrides bb_overrides;
-   struct dc_bug_wa work_arounds;
-   struct dc_context *ctx;
-   struct dc_phy_addr_space_config vm_pa_config;
-
-   uint8_t link_count;
-   struct dc_link *links[MAX_PIPES * 2];
-   struct link_service *link_srv;
-
-   struct dc_state *current_state;
-   struct resource_pool *res_pool;
-
-   struct clk_mgr *clk_mgr;
-
-   /* Display Engine Clock levels */
-   struct dm_pp_clock_levels sclk_lvls;
-
-   /* Inputs into BW and WM calculations. */
-   struct bw_calcs_dceip *bw_dceip;
-   struct bw_calcs_vbios *bw_vbios;
-   struct dcn_soc_bounding_box *dcn_soc;
-   struct dcn_ip_params *dcn_ip;
-   struct display_mode_lib dml;
-
-   /* HW functions */
-   struct hw_sequencer_funcs hwss;
-   struct dce_hwseq *hwseq;
-
-   /* Require to optimize clocks and bandwidth for added/removed planes */
-   bool optimized_required;
-   bool wm_optimized_required;
-   bool idle_optimizations_allowed;
- 

Re: [PATCH 25/34] drm/amd/display: Set the power_down_on_boot function pointer to null

[Mario Limonciello]

On 2/28/2024 12:39, Alex Hung wrote:

From: Muhammad Ahmed 

[WHY]
Blackscreen hang @ PC EF25 when trying to wake up from S0i3. DCN
gets powered off due to dc_power_down_on_boot() being called after
timeout.

[HOW]
Setting the power_down_on_boot function pointer to null since we don't
expect the function to be called for APU.


Perhaps, should we be making the same change for other APUs?

It seems a few others call dcn10_power_down_on_boot() for the callback.



Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Alex Hung 
Signed-off-by: Muhammad Ahmed 
---
  drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index dce620d359a6..d4e0abbef28e 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -39,7 +39,7 @@
  static const struct hw_sequencer_funcs dcn35_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
.init_hw = dcn35_init_hw,
-   .power_down_on_boot = dcn35_power_down_on_boot,
+   .power_down_on_boot = NULL,
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = NULL,
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,

[PATCH 34/34] drm/amd/display: 3.2.275

[Alex Hung]

From: Aric Cyr 

- Support long vblank feature
- Add monitor patch for specific eDP
- Init DPPCLK from SMU on dcn32
- Update odm when ODM combine is changed on an otg master pipe with
  no plane
- Fix idle check for shared firmware state
- Add guards for idle on reg read/write
- Guard cursor idle reallow by DC debug option
- Add debug counters to IPS exit prints
- Add left edge pixel for YCbCr422/420 + ODM pipe split
- Amend coasting vtotal for replay low hz
- Refactor DPP into a component directory
- Set the power_down_on_boot function pointer to null
- Implement update_planes_and_stream_v3 sequence
- Lock all enabled otg pipes even with no planes
- Implement wait_for_odm_update_pending_complete
- Add a dc_state NULL check in dc_state_release
- Backup and restore only on full updates
- Update DMUB flags and definitions
- Return the correct HDCP error code
- Add comments to v_total calculation and drop legacy TODO

Acked-by: Alex Hung 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 9629bd9252b4..e17ddda8ec38 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -51,7 +51,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.274"
+#define DC_VER "3.2.275"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.34.1

[PATCH 33/34] drm/amd/display: Add comments to v_total calculation and drop legacy TODO

[Alex Hung]

From: Rodrigo Siqueira 

[WHY & HOW]
This commit just adds some simple comments to help understand the
calculation of V total duration for Freesync. Also, remove a legacy TODO
comment from link service type.

Acked-by: Alex Hung 
Signed-off-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/include/link_service_types.h | 1 -
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c  | 4 ++--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h 
b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 92dbff22a7c6..1867aac57cf2 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -73,7 +73,6 @@ struct link_training_settings {
enum dc_pre_emphasis *pre_emphasis;
enum dc_post_cursor2 *post_cursor2;
bool should_set_fec_ready;
-   /* TODO - factor lane_settings out because it changes during LT */
union dc_dp_ffe_preset *ffe_preset;
 
uint16_t cr_pattern_time;
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index fbaa6effd0e3..b19ef58d1555 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -158,13 +158,13 @@ static unsigned int calc_v_total_from_duration(
if (duration_in_us > vrr->max_duration_in_us)
duration_in_us = vrr->max_duration_in_us;
 
-   if (dc_is_hdmi_signal(stream->signal)) {
+   if (dc_is_hdmi_signal(stream->signal)) { // change for HDMI to comply 
with spec
uint32_t h_total_up_scaled;
 
h_total_up_scaled = stream->timing.h_total * 1;
v_total = div_u64((unsigned long long)duration_in_us
* stream->timing.pix_clk_100hz + 
(h_total_up_scaled - 1),
-   h_total_up_scaled);
+   h_total_up_scaled); //ceiling for MMax 
and MMin for MVRR
} else {
v_total = div64_u64(div64_u64(((unsigned long long)(
duration_in_us) * 
(stream->timing.pix_clk_100hz / 10)),
-- 
2.34.1

[PATCH 32/34] drm/amd/display: Return the correct HDCP error code

[Alex Hung]

From: Rodrigo Siqueira 

[WHY & HOW]
If the display is null when creating an HDCP session, return a proper
error code.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung 
Signed-off-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index 8c137d7c032e..7c9805705fd3 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -513,6 +513,9 @@ enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct 
mod_hdcp *hdcp)
hdcp_cmd = (struct ta_hdcp_shared_memory 
*)psp->hdcp_context.context.mem_context.shared_buf;
memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
 
+   if (!display)
+   return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
+
hdcp_cmd->in_msg.hdcp2_create_session_v2.display_handle = 
display->index;
 
if (hdcp->connection.link.adjust.hdcp2.force_type == 
MOD_HDCP_FORCE_TYPE_0)
-- 
2.34.1

[PATCH 31/34] drm/amd/display: Update DMUB flags and definitions

[Alex Hung]

From: Anthony Koo 

[WHAT]
- Update replay residency tracing design to support more types
  including tracking PHY and ALPM residency types
- Add commands for Replay frame update count profiling
- Enhance HWFQ with additional flags to allow for more
  optimized IPS low power state residencies
- Add new flag to indicate if a new frame update needed for
  ABM to ramp up into steady state

Acked-by: Alex Hung 
Signed-off-by: Anthony Koo 
---
 .../gpu/drm/amd/display/dc/dce/dmub_replay.c  |  2 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 40 +--
 2 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index b010814706fe..4f559a025cf0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -244,7 +244,7 @@ static void dmub_replay_residency(struct dmub_replay *dmub, 
uint8_t panel_inst,
uint16_t param = (uint16_t)(panel_inst << 8);
 
if (is_alpm)
-   param |= REPLAY_RESIDENCY_MODE_ALPM;
+   param |= REPLAY_RESIDENCY_FIELD_MODE_ALPM;
 
if (is_start)
param |= REPLAY_RESIDENCY_ENABLE;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 4a650ac571d7..b81cd2649db3 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -194,6 +194,11 @@ union abm_flags {
 * of user backlight level.
 */
unsigned int abm_gradual_bl_change : 1;
+
+   /**
+* @abm_new_frame: Indicates if a new frame update needed for 
ABM to ramp up into steady
+*/
+   unsigned int abm_new_frame : 1;
} bitfields;
 
unsigned int u32All;
@@ -2937,18 +2942,47 @@ struct dmub_rb_cmd_psr_set_power_opt {
struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
 };
 
+/**
+ * Definition of Replay Residency GPINT command.
+ * Bit[0] - Residency mode for Revision 0
+ * Bit[1] - Enable/Disable state
+ * Bit[2-3] - Revision number
+ * Bit[4-7] - Residency mode for Revision 1
+ * Bit[8] - Panel instance
+ * Bit[9-15] - Reserved
+ */
+
+enum pr_residency_mode {
+   PR_RESIDENCY_MODE_PHY = 0x0,
+   PR_RESIDENCY_MODE_ALPM,
+   PR_RESIDENCY_MODE_IPS2,
+   PR_RESIDENCY_MODE_FRAME_CNT,
+};
+
 #define REPLAY_RESIDENCY_MODE_SHIFT(0)
 #define REPLAY_RESIDENCY_ENABLE_SHIFT  (1)
+#define REPLAY_RESIDENCY_REVISION_SHIFT(2)
+#define REPLAY_RESIDENCY_MODE2_SHIFT   (4)
 
 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << 
REPLAY_RESIDENCY_MODE_SHIFT)
-# define REPLAY_RESIDENCY_MODE_PHY (0x0 << 
REPLAY_RESIDENCY_MODE_SHIFT)
-# define REPLAY_RESIDENCY_MODE_ALPM(0x1 << 
REPLAY_RESIDENCY_MODE_SHIFT)
-# define REPLAY_RESIDENCY_MODE_IPS 0x10
+# define REPLAY_RESIDENCY_FIELD_MODE_PHY   (0x0 << 
REPLAY_RESIDENCY_MODE_SHIFT)
+# define REPLAY_RESIDENCY_FIELD_MODE_ALPM  (0x1 << 
REPLAY_RESIDENCY_MODE_SHIFT)
+
+#define REPLAY_RESIDENCY_MODE2_MASK(0xF << 
REPLAY_RESIDENCY_MODE2_SHIFT)
+# define REPLAY_RESIDENCY_FIELD_MODE2_IPS  (0x1 << 
REPLAY_RESIDENCY_MODE2_SHIFT)
+# define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT(0x2 << 
REPLAY_RESIDENCY_MODE2_SHIFT)
 
 #define REPLAY_RESIDENCY_ENABLE_MASK   (0x1 << 
REPLAY_RESIDENCY_ENABLE_SHIFT)
 # define REPLAY_RESIDENCY_DISABLE  (0x0 << 
REPLAY_RESIDENCY_ENABLE_SHIFT)
 # define REPLAY_RESIDENCY_ENABLE   (0x1 << 
REPLAY_RESIDENCY_ENABLE_SHIFT)
 
+#define REPLAY_RESIDENCY_REVISION_MASK (0x3 << 
REPLAY_RESIDENCY_REVISION_SHIFT)
+# define REPLAY_RESIDENCY_REVISION_0   (0x0 << 
REPLAY_RESIDENCY_REVISION_SHIFT)
+# define REPLAY_RESIDENCY_REVISION_1   (0x1 << 
REPLAY_RESIDENCY_REVISION_SHIFT)
+
+/**
+ * Definition of a replay_state.
+ */
 enum replay_state {
REPLAY_STATE_0  = 0x0,
REPLAY_STATE_1  = 0x10,
-- 
2.34.1

[PATCH 29/34] drm/amd/display: Add a dc_state NULL check in dc_state_release

[Alex Hung]

From: Allen Pan 

[How]
Check wheather state is NULL before releasing it.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu 
Acked-by: Alex Hung 
Signed-off-by: Allen Pan 
---
 drivers/gpu/drm/amd/display/dc/core/dc_state.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index 180ac47868c2..5cc7f8da209c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -334,7 +334,8 @@ static void dc_state_free(struct kref *kref)
 
 void dc_state_release(struct dc_state *state)
 {
-   kref_put(>refcount, dc_state_free);
+   if (state != NULL)
+   kref_put(>refcount, dc_state_free);
 }
 /*
  * dc_state_add_stream() - Add a new dc_stream_state to a dc_state.
-- 
2.34.1

[PATCH 28/34] drm/amd/display: Implement wait_for_odm_update_pending_complete

[Alex Hung]

From: Wenjing Liu 

[WHY]
Odm update is doubled buffered. We need to wait for ODM update to be
completed before optimizing bandwidth or programming new udpates.

[HOW]
implement wait_for_odm_update_pending_complete function to wait for:
1. odm configuration update is no longer pending in timing generator.
2. no pending dpg pattern update for each active OPP.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee 
Acked-by: Alex Hung 
Signed-off-by: Wenjing Liu 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 56 ++-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c  |  1 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c  | 14 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.h  |  2 +
 .../drm/amd/display/dc/dcn201/dcn201_opp.c|  1 +
 .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c   |  4 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h   |  3 +
 .../amd/display/dc/inc/hw/timing_generator.h  |  1 +
 .../amd/display/dc/optc/dcn10/dcn10_optc.h|  3 +-
 .../amd/display/dc/optc/dcn32/dcn32_optc.c|  8 +++
 .../amd/display/dc/optc/dcn32/dcn32_optc.h|  1 +
 11 files changed, 90 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e87aad983b40..d8967087335e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1335,6 +1335,54 @@ static void disable_vbios_mode_if_required(
}
 }
 
+/**
+ * wait_for_blank_complete - wait for all active OPPs to finish pending blank
+ * pattern updates
+ *
+ * @dc: [in] dc reference
+ * @context: [in] hardware context in use
+ */
+static void wait_for_blank_complete(struct dc *dc,
+   struct dc_state *context)
+{
+   struct pipe_ctx *opp_head;
+   struct dce_hwseq *hws = dc->hwseq;
+   int i;
+
+   if (!hws->funcs.wait_for_blank_complete)
+   return;
+
+   for (i = 0; i < MAX_PIPES; i++) {
+   opp_head = >res_ctx.pipe_ctx[i];
+
+   if (!resource_is_pipe_type(opp_head, OPP_HEAD) ||
+   dc_state_get_pipe_subvp_type(context, opp_head) 
== SUBVP_PHANTOM)
+   continue;
+
+   hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp);
+   }
+}
+
+static void wait_for_odm_update_pending_complete(struct dc *dc, struct 
dc_state *context)
+{
+   struct pipe_ctx *otg_master;
+   struct timing_generator *tg;
+   int i;
+
+   for (i = 0; i < MAX_PIPES; i++) {
+   otg_master = >res_ctx.pipe_ctx[i];
+   if (!resource_is_pipe_type(otg_master, OTG_MASTER) ||
+   dc_state_get_pipe_subvp_type(context, 
otg_master) == SUBVP_PHANTOM)
+   continue;
+   tg = otg_master->stream_res.tg;
+   if (tg->funcs->wait_odm_doublebuffer_pending_clear)
+   tg->funcs->wait_odm_doublebuffer_pending_clear(tg);
+   }
+
+   /* ODM update may require to reprogram blank pattern for each OPP */
+   wait_for_blank_complete(dc, context);
+}
+
 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 {
int i;
@@ -2026,6 +2074,11 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
context->stream_count == 0) {
/* Must wait for no flips to be pending before doing optimize 
bw */
wait_for_no_pipes_pending(dc, context);
+   /*
+* optimized dispclk depends on ODM setup. Need to wait for ODM
+* update pending complete before optimizing bandwidth.
+*/
+   wait_for_odm_update_pending_complete(dc, context);
/* pplib is notified if disp_num changed */
dc->hwss.optimize_bandwidth(dc, context);
/* Need to do otg sync again as otg could be out of sync due to 
otg
@@ -3591,7 +3644,7 @@ static void commit_planes_for_stream_fast(struct dc *dc,
top_pipe_to_program->stream->update_flags.raw = 0;
 }
 
-static void wait_for_outstanding_hw_updates(struct dc *dc, const struct 
dc_state *dc_context)
+static void wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state 
*dc_context)
 {
 /*
  * This function calls HWSS to wait for any potentially double buffered
@@ -3629,6 +3682,7 @@ static void wait_for_outstanding_hw_updates(struct dc 
*dc, const struct dc_state
}
}
}
+   wait_for_odm_update_pending_complete(dc, dc_context);
 }
 
 static void commit_planes_for_stream(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index 48a40dcc7050..5838a11efd00 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -384,6 +384,7 @@ static const struct 

[PATCH 27/34] drm/amd/display: Lock all enabled otg pipes even with no planes

[Alex Hung]

From: Wenjing Liu 

[WHY]
On DCN32 we support dynamic ODM even when OTG is blanked. When ODM
configuration is dynamically changed and the OTG is on blank pattern,
we will need to reprogram OPP's test pattern based on new ODM
configuration. Therefore we need to lock the OTG pipe to avoid temporary
corruption when we are reprogramming OPP blank patterns.

[HOW]
Add a new interdependent update lock implementation to lock all enabled
OTG pipes even when there is no plane on the OTG for DCN32.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee 
Acked-by: Alex Hung 
Signed-off-by: Wenjing Liu 
---
 .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c   | 23 +++
 .../amd/display/dc/hwss/dcn32/dcn32_hwseq.h   |  2 ++
 .../amd/display/dc/hwss/dcn32/dcn32_init.c|  2 +-
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index b890db0bfc46..c0b526cf1786 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1785,3 +1785,26 @@ void dcn32_prepare_bandwidth(struct dc *dc,
context->bw_ctx.bw.dcn.clk.p_state_change_support = 
p_state_change_support;
}
 }
+
+void dcn32_interdependent_update_lock(struct dc *dc,
+   struct dc_state *context, bool lock)
+{
+   unsigned int i;
+   struct pipe_ctx *pipe;
+   struct timing_generator *tg;
+
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   pipe = >res_ctx.pipe_ctx[i];
+   tg = pipe->stream_res.tg;
+
+   if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
+   !tg->funcs->is_tg_enabled(tg) ||
+   dc_state_get_pipe_subvp_type(context, pipe) == 
SUBVP_PHANTOM)
+   continue;
+
+   if (lock)
+   dc->hwss.pipe_control_lock(dc, pipe, true);
+   else
+   dc->hwss.pipe_control_lock(dc, pipe, false);
+   }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
index 069e20bc87c0..f55c11fc56ec 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
@@ -129,4 +129,6 @@ bool dcn32_is_pipe_topology_transition_seamless(struct dc 
*dc,
 void dcn32_prepare_bandwidth(struct dc *dc,
struct dc_state *context);
 
+void dcn32_interdependent_update_lock(struct dc *dc,
+   struct dc_state *context, bool lock);
 #endif /* __DC_HWSS_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
index 2b073123d3ed..67d661dbd5b7 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
@@ -58,7 +58,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
.disable_plane = dcn20_disable_plane,
.disable_pixel_data = dcn20_disable_pixel_data,
.pipe_control_lock = dcn20_pipe_control_lock,
-   .interdependent_update_lock = dcn10_lock_all_pipes,
+   .interdependent_update_lock = dcn32_interdependent_update_lock,
.cursor_lock = dcn10_cursor_lock,
.prepare_bandwidth = dcn32_prepare_bandwidth,
.optimize_bandwidth = dcn20_optimize_bandwidth,
-- 
2.34.1

[PATCH 26/34] drm/amd/display: Implement update_planes_and_stream_v3 sequence

[Alex Hung]

From: Wenjing Liu 

[WHY & HOW]
Update planes and stream version 3 separates FULL and FAST updates
to their own sequences. It aims to clean up frequent checks for
update type resulting unnecessary branching in logic flow. It also
adds a new commit minimal transition sequence, which detects the need
for minimal transition based on the actual comparison of current and
new states instead of "predicting" it based on per feature software
policy, i.e. could_mpcc_tree_change_for_active_pipes.

The new commit minimal transition sequence is made universal to any
power saving features that would use extra free pipes such as Dynamic
ODM/MPC Combine, MPO or SubVp. Therefore there is no longer a need to
specially handle compatibility problems with transitions among those
features as they are now transparent to the new sequence.

Reviewed-by: Wenjing Liu 
Acked-by: Alex Hung 
Signed-off-by: Wenjing Liu 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 700 +++
 1 file changed, 469 insertions(+), 231 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ed6579633a58..e87aad983b40 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2065,7 +2065,7 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
return result;
 }
 
-static bool commit_minimal_transition_state_legacy(struct dc *dc,
+static bool commit_minimal_transition_state(struct dc *dc,
struct dc_state *transition_base_context);
 
 /**
@@ -2131,7 +2131,7 @@ enum dc_status dc_commit_streams(struct dc *dc,
}
 
if (handle_exit_odm2to1)
-   res = commit_minimal_transition_state_legacy(dc, 
dc->current_state);
+   res = commit_minimal_transition_state(dc, dc->current_state);
 
context = dc_state_create_current_copy(dc);
if (!context)
@@ -3029,6 +3029,63 @@ static void restore_planes_and_stream_state(
*stream->out_transfer_func = scratch->out_transfer_func;
 }
 
+/**
+ * update_seamless_boot_flags() - Helper function for updating seamless boot 
flags
+ *
+ * @dc: Current DC state
+ * @context: New DC state to be programmed
+ * @surface_count: Number of surfaces that have an updated
+ * @stream: Corresponding stream to be updated in the current flip
+ *
+ * Updating seamless boot flags do not need to be part of the commit sequence. 
This
+ * helper function will update the seamless boot flags on each flip (if 
required)
+ * outside of the HW commit sequence (fast or slow).
+ *
+ * Return: void
+ */
+static void update_seamless_boot_flags(struct dc *dc,
+   struct dc_state *context,
+   int surface_count,
+   struct dc_stream_state *stream)
+{
+   if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
+   /* Optimize seamless boot flag keeps clocks and watermarks high 
until
+* first flip. After first flip, optimization is required to 
lower
+* bandwidth. Important to note that it is expected UEFI will
+* only light up a single display on POST, therefore we only 
expect
+* one stream with seamless boot flag set.
+*/
+   if (stream->apply_seamless_boot_optimization) {
+   stream->apply_seamless_boot_optimization = false;
+
+   if (get_seamless_boot_stream_count(context) == 0)
+   dc->optimized_required = true;
+   }
+   }
+}
+
+/**
+ * update_planes_and_stream_state() - The function takes planes and stream
+ * updates as inputs and determines the appropriate update type. If update type
+ * is FULL, the function allocates a new context, populates and validates it.
+ * Otherwise, it updates current dc context. The function will return both
+ * new_context and new_update_type back to the caller. The function also backs
+ * up both current and new contexts into corresponding dc state scratch memory.
+ * TODO: The function does too many things, and even conditionally allocates dc
+ * context memory implicitly. We should consider to break it down.
+ *
+ * @dc: Current DC state
+ * @srf_updates: an array of surface updates
+ * @surface_count: surface update count
+ * @stream: Corresponding stream to be updated
+ * @stream_update: stream update
+ * @new_update_type: [out] determined update type by the function
+ * @new_context: [out] new context allocated and validated if update type is
+ * FULL, reference to current context if update type is less than FULL.
+ *
+ * Return: true if a valid update is populated into new_context, false
+ * otherwise.
+ */
 static bool update_planes_and_stream_state(struct dc *dc,
struct dc_surface_update *srf_updates, int surface_count,
struct dc_stream_state *stream,
@@ -3153,6 +3210,7 @@ static bool 

[PATCH 25/34] drm/amd/display: Set the power_down_on_boot function pointer to null

[Alex Hung]

From: Muhammad Ahmed 

[WHY]
Blackscreen hang @ PC EF25 when trying to wake up from S0i3. DCN
gets powered off due to dc_power_down_on_boot() being called after
timeout.

[HOW]
Setting the power_down_on_boot function pointer to null since we don't
expect the function to be called for APU.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Alex Hung 
Signed-off-by: Muhammad Ahmed 
---
 drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index dce620d359a6..d4e0abbef28e 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -39,7 +39,7 @@
 static const struct hw_sequencer_funcs dcn35_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
.init_hw = dcn35_init_hw,
-   .power_down_on_boot = dcn35_power_down_on_boot,
+   .power_down_on_boot = NULL,
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = NULL,
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
-- 
2.34.1

[PATCH 24/34] drm/amd/display: Refactor DPP into a component directory

[Alex Hung]

From: Revalla Hari Krishna 

[WHY & HOW]
Move all dpp files to a new dpp directory.

Reviewed-by: Martin Leung 
Acked-by: Alex Hung 
Signed-off-by: Revalla Hari Krishna 
---
 drivers/gpu/drm/amd/display/Makefile  |  1 +
 drivers/gpu/drm/amd/display/dc/Makefile   |  2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/Makefile |  4 +-
 .../amd/display/dc/dcn10/dcn10_cm_common.c|  2 +-
 drivers/gpu/drm/amd/display/dc/dcn20/Makefile |  2 +-
 .../gpu/drm/amd/display/dc/dcn201/Makefile|  2 +-
 drivers/gpu/drm/amd/display/dc/dcn30/Makefile |  2 -
 .../amd/display/dc/dcn30/dcn30_cm_common.c|  2 +-
 drivers/gpu/drm/amd/display/dc/dcn32/Makefile |  2 +-
 drivers/gpu/drm/amd/display/dc/dcn35/Makefile |  2 +-
 drivers/gpu/drm/amd/display/dc/dpp/Makefile   | 77 +++
 .../amd/display/dc/dpp/dcn10/CMakeLists.txt   |  6 ++
 .../display/dc/{ => dpp}/dcn10/dcn10_dpp.c|  2 +-
 .../display/dc/{ => dpp}/dcn10/dcn10_dpp.h|  0
 .../display/dc/{ => dpp}/dcn10/dcn10_dpp_cm.c |  4 +-
 .../dc/{ => dpp}/dcn10/dcn10_dpp_dscl.c   |  2 +-
 .../amd/display/dc/dpp/dcn20/CMakeLists.txt   |  5 ++
 .../display/dc/{ => dpp}/dcn20/dcn20_dpp.c|  2 +-
 .../display/dc/{ => dpp}/dcn20/dcn20_dpp.h|  0
 .../display/dc/{ => dpp}/dcn20/dcn20_dpp_cm.c |  2 +-
 .../amd/display/dc/dpp/dcn201/CMakeLists.txt  |  4 +
 .../display/dc/{ => dpp}/dcn201/dcn201_dpp.c  |  2 +-
 .../display/dc/{ => dpp}/dcn201/dcn201_dpp.h  |  0
 .../amd/display/dc/dpp/dcn30/CMakeLists.txt   |  5 ++
 .../display/dc/{ => dpp}/dcn30/dcn30_dpp.c|  4 +-
 .../display/dc/{ => dpp}/dcn30/dcn30_dpp.h|  0
 .../display/dc/{ => dpp}/dcn30/dcn30_dpp_cm.c |  4 +-
 .../amd/display/dc/dpp/dcn32/CMakeLists.txt   |  4 +
 .../display/dc/{ => dpp}/dcn32/dcn32_dpp.c|  2 +-
 .../display/dc/{ => dpp}/dcn32/dcn32_dpp.h|  0
 .../amd/display/dc/dpp/dcn35/CMakeLists.txt   |  4 +
 .../display/dc/{ => dpp}/dcn35/dcn35_dpp.c|  2 +-
 .../display/dc/{ => dpp}/dcn35/dcn35_dpp.h|  0
 33 files changed, 128 insertions(+), 24 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn10/CMakeLists.txt
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn10/dcn10_dpp.c (99%)
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn10/dcn10_dpp.h (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn10/dcn10_dpp_cm.c (99%)
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn10/dcn10_dpp_dscl.c (99%)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn20/CMakeLists.txt
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn20/dcn20_dpp.c (99%)
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn20/dcn20_dpp.h (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn20/dcn20_dpp_cm.c (99%)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn201/CMakeLists.txt
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn201/dcn201_dpp.c (99%)
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn201/dcn201_dpp.h (100%)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn30/CMakeLists.txt
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn30/dcn30_dpp.c (99%)
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn30/dcn30_dpp.h (100%)
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn30/dcn30_dpp_cm.c (99%)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn32/CMakeLists.txt
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn32/dcn32_dpp.c (99%)
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn32/dcn32_dpp.h (100%)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn35/CMakeLists.txt
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn35/dcn35_dpp.c (98%)
 rename drivers/gpu/drm/amd/display/dc/{ => dpp}/dcn35/dcn35_dpp.h (100%)

diff --git a/drivers/gpu/drm/amd/display/Makefile 
b/drivers/gpu/drm/amd/display/Makefile
index 92a5c5efcf92..9a5bcafbf730 100644
--- a/drivers/gpu/drm/amd/display/Makefile
+++ b/drivers/gpu/drm/amd/display/Makefile
@@ -33,6 +33,7 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/hwss
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/resource
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dsc
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/optc
+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dpp
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/inc
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync
 subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
b/drivers/gpu/drm/amd/display/dc/Makefile
index 7991ae468f75..4e9fb1742877 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -22,7 +22,7 @@
 #
 # Makefile for Display Core (dc) component.
 
-DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource 
optc
+DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource 
optc dpp
 
 ifdef CONFIG_DRM_AMD_DC_FP
 
diff --git 

[PATCH 23/34] drm/amd/display: Amend coasting vtotal for replay low hz

[Alex Hung]

From: ChunTao Tso 

[WHY]
The original coasting vtotal is 2 bytes, and it need to
be amended to 4 bytes because low hz case.

[HOW]
Amend coasting vtotal from 2 bytes to 4 bytes.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee 
Acked-by: Alex Hung 
Signed-off-by: ChunTao Tso 
---
 drivers/gpu/drm/amd/display/dc/dc_types.h | 4 ++--
 drivers/gpu/drm/amd/display/dc/inc/link.h | 4 ++--
 .../display/dc/link/protocols/link_edp_panel_control.c| 4 ++--
 .../display/dc/link/protocols/link_edp_panel_control.h| 4 ++--
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 8 
 drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 2 +-
 drivers/gpu/drm/amd/display/modules/power/power_helpers.h | 2 +-
 7 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 9900dda2eef5..be2ac5c442a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1085,9 +1085,9 @@ struct replay_settings {
/* SMU optimization is enabled */
bool replay_smu_opt_enable;
/* Current Coasting vtotal */
-   uint16_t coasting_vtotal;
+   uint32_t coasting_vtotal;
/* Coasting vtotal table */
-   uint16_t coasting_vtotal_table[PR_COASTING_TYPE_NUM];
+   uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM];
/* Maximum link off frame count */
enum replay_link_off_frame_count_level link_off_frame_count_level;
/* Replay pseudo vtotal for abm + ips on full screen video which can 
improve ips residency */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h 
b/drivers/gpu/drm/amd/display/dc/inc/link.h
index 26fe81f213da..bf29fc58ea6a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link.h
@@ -285,12 +285,12 @@ struct link_service {
enum replay_FW_Message_type msg,
union dmub_replay_cmd_set *cmd_data);
bool (*edp_set_coasting_vtotal)(
-   struct dc_link *link, uint16_t coasting_vtotal);
+   struct dc_link *link, uint32_t coasting_vtotal);
bool (*edp_replay_residency)(const struct dc_link *link,
unsigned int *residency, const bool is_start,
const bool is_alpm);
bool (*edp_set_replay_power_opt_and_coasting_vtotal)(struct dc_link 
*link,
-   const unsigned int *power_opts, uint16_t 
coasting_vtotal);
+   const unsigned int *power_opts, uint32_t 
coasting_vtotal);
 
bool (*edp_wait_for_t12)(struct dc_link *link);
bool (*edp_is_ilr_optimization_required)(struct dc_link *link,
diff --git 
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c 
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index acfbbc638cc6..3baa2bdd6dd6 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -1034,7 +1034,7 @@ bool edp_send_replay_cmd(struct dc_link *link,
return true;
 }
 
-bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtotal)
+bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal)
 {
struct dc *dc = link->ctx->dc;
struct dmub_replay *replay = dc->res_pool->replay;
@@ -1073,7 +1073,7 @@ bool edp_replay_residency(const struct dc_link *link,
 }
 
 bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
-   const unsigned int *power_opts, uint16_t coasting_vtotal)
+   const unsigned int *power_opts, uint32_t coasting_vtotal)
 {
struct dc  *dc = link->ctx->dc;
struct dmub_replay *replay = dc->res_pool->replay;
diff --git 
a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h 
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
index 34e521af7bb4..a158c6234d42 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
@@ -59,12 +59,12 @@ bool edp_setup_replay(struct dc_link *link,
 bool edp_send_replay_cmd(struct dc_link *link,
enum replay_FW_Message_type msg,
union dmub_replay_cmd_set *cmd_data);
-bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtotal);
+bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal);
 bool edp_replay_residency(const struct dc_link *link,
unsigned int *residency, const bool is_start, const bool is_alpm);
 bool edp_get_replay_state(const struct dc_link *link, uint64_t *state);
 bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
-   const unsigned int 

[PATCH 22/34] drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split

[Alex Hung]

From: George Shen 

[WHY]
Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM
pipesplit is used, pixels on the left edge of ODM slices need one extra
pixel from the right edge of the previous slice to calculate the correct
chroma value.

Without this change, the chroma value is slightly different than
expected. This is usually imperceptible visually, but it impacts test
pattern CRCs for compliance test automation.

[HOW]
Update logic to use the register for adding extra left edge pixel for
YCbCr422/420 ODM cases.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee 
Acked-by: Alex Hung 
Signed-off-by: George Shen 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  4 ++
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 37 +++
 .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c   | 10 +
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  2 +
 drivers/gpu/drm/amd/display/dc/inc/resource.h |  4 ++
 5 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index acd8f1257ade..ed6579633a58 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3147,6 +3147,10 @@ static bool update_planes_and_stream_state(struct dc *dc,
 
if (otg_master && otg_master->stream->test_pattern.type 
!= DP_TEST_PATTERN_VIDEO_MODE)

resource_build_test_pattern_params(>res_ctx, otg_master);
+
+   if (otg_master && 
(otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422 ||
+   
otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420))
+   
resource_build_subsampling_params(>res_ctx, otg_master);
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 1b7765bc5e5e..96ea283bd169 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -822,6 +822,16 @@ static struct rect 
calculate_odm_slice_in_timing_active(struct pipe_ctx *pipe_ct
stream->timing.v_border_bottom +
stream->timing.v_border_top;
 
+   /* Recout for ODM slices after the first slice need one extra left edge 
pixel
+* for 3-tap chroma subsampling.
+*/
+   if (odm_slice_idx > 0 &&
+   (pipe_ctx->stream->timing.pixel_encoding == 
PIXEL_ENCODING_YCBCR422 ||
+   pipe_ctx->stream->timing.pixel_encoding == 
PIXEL_ENCODING_YCBCR420)) {
+   odm_rec.x -= 1;
+   odm_rec.width += 1;
+   }
+
return odm_rec;
 }
 
@@ -1438,6 +1448,7 @@ void resource_build_test_pattern_params(struct 
resource_context *res_ctx,
enum controller_dp_test_pattern controller_test_pattern;
enum controller_dp_color_space controller_color_space;
enum dc_color_depth color_depth = 
otg_master->stream->timing.display_color_depth;
+   enum dc_pixel_encoding pixel_encoding = 
otg_master->stream->timing.pixel_encoding;
int h_active = otg_master->stream->timing.h_addressable +
otg_master->stream->timing.h_border_left +
otg_master->stream->timing.h_border_right;
@@ -1469,10 +1480,36 @@ void resource_build_test_pattern_params(struct 
resource_context *res_ctx,
else
params->width = last_odm_slice_width;
 
+   /* Extra left edge pixel is required for 3-tap chroma 
subsampling. */
+   if (i != 0 && (pixel_encoding == PIXEL_ENCODING_YCBCR422 ||
+   pixel_encoding == PIXEL_ENCODING_YCBCR420)) {
+   params->offset -= 1;
+   params->width += 1;
+   }
+
offset += odm_slice_width;
}
 }
 
+void resource_build_subsampling_params(struct resource_context *res_ctx,
+   struct pipe_ctx *otg_master)
+{
+   struct pipe_ctx *opp_heads[MAX_PIPES];
+   int odm_cnt = 1;
+   int i;
+
+   odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, 
opp_heads);
+
+   /* For ODM slices after the first slice, extra left edge pixel is 
required
+* for 3-tap chroma subsampling.
+*/
+   if (otg_master->stream->timing.pixel_encoding == 
PIXEL_ENCODING_YCBCR422 ||
+   otg_master->stream->timing.pixel_encoding == 
PIXEL_ENCODING_YCBCR420) {
+   for (i = 0; i < odm_cnt; i++)
+   opp_heads[i]->stream_res.left_edge_extra_pixel = (i == 
0) ? false : true;
+   }
+}
+
 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 {
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
diff --git 

[PATCH 21/34] drm/amd/display: Add debug counters to IPS exit prints

[Alex Hung]

From: Nicholas Kazlauskas 

[WHY]
To have a log of the entry/exit counters in case the system hangs to
measure stability.

[HOW]
Read them from firmware state and pass them to the prints.

Reviewed-by: Duncan Ma 
Acked-by: Alex Hung 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 938e8cb2fec1..765a459d54eb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1279,6 +1279,7 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, 
bool allow_idle)
 static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
 {
struct dc_dmub_srv *dc_dmub_srv;
+   uint32_t rcg_exit_count, ips1_exit_count, ips2_exit_count;
 
if (dc->debug.dmcub_emulation)
return;
@@ -1295,15 +1296,22 @@ static void dc_dmub_srv_exit_low_power_state(const 
struct dc *dc)

_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver;
union dmub_shared_state_ips_driver_signals prev_driver_signals 
= ips_driver->signals;
 
+   rcg_exit_count = ips_fw->rcg_exit_count;
+   ips1_exit_count = ips_fw->ips1_exit_count;
+   ips2_exit_count = ips_fw->ips2_exit_count;
+
ips_driver->signals.all = 0;
 
DC_LOG_IPS(
-   "%s check (allow_ips1=%d allow_ips2=%d) (ips1_commit=%d 
ips2_commit=%d)",
+   "%s (allow ips1=%d ips2=%d) (commit ips1=%d ips2=%d) 
(count rcg=%d ips1=%d ips2=%d)",
__func__,
ips_driver->signals.bits.allow_ips1,
ips_driver->signals.bits.allow_ips2,
ips_fw->signals.bits.ips1_commit,
-   ips_fw->signals.bits.ips2_commit);
+   ips_fw->signals.bits.ips2_commit,
+   ips_fw->rcg_entry_count,
+   ips_fw->ips1_entry_count,
+   ips_fw->ips2_entry_count);
 
/* Note: register access has technically not resumed for DCN 
here, but we
 * need to be message PMFW through our standard register 
interface.
@@ -1387,7 +1395,11 @@ static void dc_dmub_srv_exit_low_power_state(const 
struct dc *dc)
if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
ASSERT(0);
 
-   DC_LOG_IPS("%s exited", __func__);
+   DC_LOG_IPS("%s exit (count rcg=%d ips1=%d ips2=%d)",
+   __func__,
+   rcg_exit_count,
+   ips1_exit_count,
+   ips2_exit_count);
 }
 
 void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum 
dc_acpi_cm_power_state powerState)
-- 
2.34.1

[PATCH 20/34] drm/amd/display: Guard cursor idle reallow by DC debug option

[Alex Hung]

From: Nicholas Kazlauskas 

[WHY]
To control whether idle optimizations reallowed after the first cursor
update.

[HOW]
Add checks to the conditions.

Reviewed-by: Duncan Ma 
Acked-by: Alex Hung 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 51a970fcb5d0..212e057ed9b0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -319,7 +319,7 @@ bool dc_stream_set_cursor_attributes(
program_cursor_attributes(dc, stream, attributes);
 
/* re-enable idle optimizations if necessary */
-   if (reset_idle_optimizations)
+   if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle)
dc_allow_idle_optimizations(dc, true);
 
return true;
@@ -394,7 +394,7 @@ bool dc_stream_set_cursor_position(
 
program_cursor_position(dc, stream, position);
/* re-enable idle optimizations if necessary */
-   if (reset_idle_optimizations)
+   if (reset_idle_optimizations && !dc->debug.disable_dmub_reallow_idle)
dc_allow_idle_optimizations(dc, true);
 
return true;
-- 
2.34.1

[PATCH 19/34] drm/amd/display: Add guards for idle on reg read/write

[Alex Hung]

From: Nicholas Kazlauskas 

[WHY]
If DCN is in idle then we should not be accessing DCN registers or
it can lead to hangs.

[HOW]
Log the error and return 0 or drop the write if it's in idle.

This is skipped in the exit sequence itself since the boolean flips
before it starts.

It also does not cover accesses from external clients outside of DM/DC
like firmware or the kernel mode driver.

Reviewed-by: Duncan Ma 
Acked-by: Alex Hung 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 9 +
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index b168dfc79381..938e8cb2fec1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1270,6 +1270,10 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, 
bool allow_idle)
/* NOTE: This does not use the "wake" interface since this is part of 
the wake path. */
/* We also do not perform a wait since DMCUB could enter idle after the 
notification. */
dm_execute_dmub_cmd(dc->ctx, , allow_idle ? 
DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT);
+
+   /* Register access should stop at this point. */
+   if (allow_idle)
+   dc_dmub_srv->needs_idle_wake = true;
 }
 
 static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
@@ -1301,6 +1305,11 @@ static void dc_dmub_srv_exit_low_power_state(const 
struct dc *dc)
ips_fw->signals.bits.ips1_commit,
ips_fw->signals.bits.ips2_commit);
 
+   /* Note: register access has technically not resumed for DCN 
here, but we
+* need to be message PMFW through our standard register 
interface.
+*/
+   dc_dmub_srv->needs_idle_wake = false;
+
if (prev_driver_signals.bits.allow_ips2) {
DC_LOG_IPS(
"wait IPS2 eval (ips1_commit=%d 
ips2_commit=%d)",
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 952bfb368886..60c93e9e3533 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -52,6 +52,7 @@ struct dc_dmub_srv {
void *dm;
 
bool idle_allowed;
+   bool needs_idle_wake;
 };
 
 void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);
-- 
2.34.1

[PATCH 18/34] drm/amd/display: Fix idle check for shared firmware state

[Alex Hung]

From: Nicholas Kazlauskas 

[WHY]
We still had an instance of get_idle_state checking the PMFW scratch
register instead of the actual idle allow signal.

[HOW]
Replace it with the SW state check for whether we had allowed idle
through notify_idle.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Duncan Ma 
Acked-by: Alex Hung 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index daf6c7fe0906..acd8f1257ade 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4884,22 +4884,16 @@ void dc_exit_ips_for_hw_access_internal(struct dc *dc, 
const char *caller_name)
 
 bool dc_dmub_is_ips_idle_state(struct dc *dc)
 {
-   uint32_t idle_state = 0;
-
if (dc->debug.disable_idle_power_optimizations)
return false;
 
if (!dc->caps.ips_support || (dc->config.disable_ips == 
DMUB_IPS_DISABLE_ALL))
return false;
 
-   if (dc->hwss.get_idle_state)
-   idle_state = dc->hwss.get_idle_state(dc);
-
-   if (!(idle_state & DMUB_IPS1_ALLOW_MASK) ||
-   !(idle_state & DMUB_IPS2_ALLOW_MASK))
-   return true;
+   if (!dc->ctx->dmub_srv)
+   return false;
 
-   return false;
+   return dc->ctx->dmub_srv->idle_allowed;
 }
 
 /* set min and max memory clock to lowest and highest DPM level, respectively 
*/
-- 
2.34.1

[PATCH 17/34] drm/amd/display: Update odm when ODM combine is changed on an otg master pipe with no plane

[Alex Hung]

From: Wenjing Liu 

[WHY]
When committing an update with ODM combine change when the plane is
removing or already removed, we fail to detect odm change in pipe
update flags. This has caused mismatch between new dc state and the
actual hardware state, because we missed odm programming.

[HOW]
- Detect odm change even for otg master pipe without a plane.
- Update odm config before calling program pipes for pipe with planes.

The commit also updates blank pattern programming when odm is changed
without plane. This is because number of OPP is changed when ODM
combine is changed. Blank pattern is per OPP so we will need to
reprogram OPP based on the new pipe topology.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Dillon Varone 
Acked-by: Alex Hung 
Signed-off-by: Wenjing Liu 
---
 .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c   | 41 ++-
 .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c   |  7 
 2 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index c55d5155ecb9..40098d9f70cb 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -1498,6 +1498,11 @@ static void dcn20_detect_pipe_changes(struct dc_state 
*old_state,
return;
}
 
+   if (resource_is_pipe_type(new_pipe, OTG_MASTER) &&
+   resource_is_odm_topology_changed(new_pipe, old_pipe))
+   /* Detect odm changes */
+   new_pipe->update_flags.bits.odm = 1;
+
/* Exit on unchanged, unused pipe */
if (!old_pipe->plane_state && !new_pipe->plane_state)
return;
@@ -1551,10 +1556,6 @@ static void dcn20_detect_pipe_changes(struct dc_state 
*old_state,
 
/* Detect top pipe only changes */
if (resource_is_pipe_type(new_pipe, OTG_MASTER)) {
-   /* Detect odm changes */
-   if (resource_is_odm_topology_changed(new_pipe, old_pipe))
-   new_pipe->update_flags.bits.odm = 1;
-
/* Detect global sync changes */
if (old_pipe->pipe_dlg_param.vready_offset != 
new_pipe->pipe_dlg_param.vready_offset
|| old_pipe->pipe_dlg_param.vstartup_start != 
new_pipe->pipe_dlg_param.vstartup_start
@@ -1999,19 +2000,20 @@ void dcn20_program_front_end_for_ctx(
DC_LOGGER_INIT(dc->ctx->logger);
unsigned int prev_hubp_count = 0;
unsigned int hubp_count = 0;
+   struct pipe_ctx *pipe;
 
if (resource_is_pipe_topology_changed(dc->current_state, context))
resource_log_pipe_topology_update(dc, context);
 
if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
-   struct pipe_ctx *pipe_ctx = 
>res_ctx.pipe_ctx[i];
+   pipe = >res_ctx.pipe_ctx[i];
 
-   if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && 
pipe_ctx->plane_state) {
-   
ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
+   if (!pipe->top_pipe && !pipe->prev_odm_pipe && 
pipe->plane_state) {
+   ASSERT(!pipe->plane_state->triplebuffer_flips);
/*turn off triple buffer for full update*/
dc->hwss.program_triplebuffer(
-   dc, pipe_ctx, 
pipe_ctx->plane_state->triplebuffer_flips);
+   dc, pipe, 
pipe->plane_state->triplebuffer_flips);
}
}
}
@@ -2085,12 +2087,22 @@ void dcn20_program_front_end_for_ctx(
DC_LOG_DC("Reset mpcc for pipe %d\n", 
dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
}
 
+   /* update ODM for blanked OTG master pipes */
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   pipe = >res_ctx.pipe_ctx[i];
+   if (resource_is_pipe_type(pipe, OTG_MASTER) &&
+   !resource_is_pipe_type(pipe, DPP_PIPE) &&
+   pipe->update_flags.bits.odm &&
+   hws->funcs.update_odm)
+   hws->funcs.update_odm(dc, context, pipe);
+   }
+
/*
 * Program all updated pipes, order matters for mpcc setup. Start with
 * top pipe and program all pipes that follow in order
 */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
-   struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
+   pipe = >res_ctx.pipe_ctx[i];
 
if (pipe->plane_state && !pipe->top_pipe) {
while (pipe) {
@@ -2129,17 +2141,6 @@ void dcn20_program_front_end_for_ctx(
   

[PATCH 16/34] drm/amd/display: Init DPPCLK from SMU on dcn32

[Alex Hung]

From: Dillon Varone 

[WHY & HOW]
DPPCLK ranges should be obtained from the SMU when available.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Chaitanya Dhere 
Acked-by: Alex Hung 
Signed-off-by: Dillon Varone 
---
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  | 14 ++
 .../drm/amd/display/dc/dml2/dml2_wrapper.c| 28 +--
 .../drm/amd/display/dc/dml2/dml2_wrapper.h|  3 ++
 .../dc/resource/dcn32/dcn32_resource.c|  2 ++
 .../dc/resource/dcn321/dcn321_resource.c  |  2 ++
 5 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 668f05c8654e..bec252e1dd27 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -216,6 +216,16 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950)
clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950;
 
+   /* DPPCLK */
+   dcn32_init_single_clock(clk_mgr, PPCLK_DPPCLK,
+   
_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
+   _entries_per_clk->num_dppclk_levels);
+   num_levels = num_entries_per_clk->num_dppclk_levels;
+   clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = 
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DPPCLK);
+   //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x
+   if (clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz > 1950)
+   clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = 1950;
+
if (num_entries_per_clk->num_dcfclk_levels &&
num_entries_per_clk->num_dtbclk_levels &&
num_entries_per_clk->num_dispclk_levels)
@@ -240,6 +250,10 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
= 
khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
}
 
+   for (i = 0; i < num_levels; i++)
+   if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz > 
1950)
+   
clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz = 1950;
+
/* Get UCLK, update bounding box */
clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index 2a58a7687bdb..72cca367062e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -703,13 +703,8 @@ static inline struct dml2_context 
*dml2_allocate_memory(void)
return (struct dml2_context *) kzalloc(sizeof(struct dml2_context), 
GFP_KERNEL);
 }
 
-bool dml2_create(const struct dc *in_dc, const struct 
dml2_configuration_options *config, struct dml2_context **dml2)
+static void dml2_init(const struct dc *in_dc, const struct 
dml2_configuration_options *config, struct dml2_context **dml2)
 {
-   // Allocate Mode Lib Ctx
-   *dml2 = dml2_allocate_memory();
-
-   if (!(*dml2))
-   return false;
 
// Store config options
(*dml2)->config = *config;
@@ -737,9 +732,18 @@ bool dml2_create(const struct dc *in_dc, const struct 
dml2_configuration_options
initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc);
 
initialize_dml2_soc_states(*dml2, in_dc, 
&(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states);
+}
+
+bool dml2_create(const struct dc *in_dc, const struct 
dml2_configuration_options *config, struct dml2_context **dml2)
+{
+   // Allocate Mode Lib Ctx
+   *dml2 = dml2_allocate_memory();
+
+   if (!(*dml2))
+   return false;
+
+   dml2_init(in_dc, config, dml2);
 
-   /*Initialize DML20 instance which calls dml2_core_create, and 
core_dcn3_populate_informative*/
-   //dml2_initialize_instance(&(*dml_ctx)->v20.dml_init);
return true;
 }
 
@@ -779,3 +783,11 @@ bool dml2_create_copy(struct dml2_context **dst_dml2,
 
return true;
 }
+
+void dml2_reinit(const struct dc *in_dc,
+const struct dml2_configuration_options 
*config,
+struct dml2_context **dml2)
+{
+
+   dml2_init(in_dc, config, dml2);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
index ee0eb184eb6d..cc662d682fd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
@@ -214,6 +214,9 @@ void dml2_copy(struct dml2_context *dst_dml2,
struct dml2_context *src_dml2);
 bool dml2_create_copy(struct dml2_context **dst_dml2,
struct dml2_context *src_dml2);
+void dml2_reinit(const 

[PATCH 15/34] drm/amd/display: Add monitor patch for specific eDP

[Alex Hung]

From: Ryan Lin 

[WHY]
Some eDP panels' ext caps don't write initial values. The value of
dpcd_addr (0x317) can be random and the backlight control interface
will be incorrect.

[HOW]
Add new panel patches to remove sink ext caps.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org # 6.5.x
Cc: Tsung-hua Lin 
Cc: Chris Chi 
Reviewed-by: Wayne Lin 
Acked-by: Alex Hung 
Signed-off-by: Ryan Lin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 85b7f58a7f35..c27063305a13 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -67,6 +67,8 @@ static void apply_edid_quirks(struct edid *edid, struct 
dc_edid_caps *edid_caps)
/* Workaround for some monitors that do not clear DPCD 0x317 if 
FreeSync is unsupported */
case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
+   case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A):
+   case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1):
DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id 
%X\n", panel_id);
edid_caps->panel_patch.remove_sink_ext_caps = true;
break;
@@ -120,6 +122,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
 
edid_caps->edid_hdmi = connector->display_info.is_hdmi;
 
+   apply_edid_quirks(edid_buf, edid_caps);
+
sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, );
if (sad_count <= 0)
return result;
@@ -146,8 +150,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
else
edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
 
-   apply_edid_quirks(edid_buf, edid_caps);
-
kfree(sads);
kfree(sadb);
 
-- 
2.34.1

[PATCH 14/34] drm/amd/display: Support long vblank feature

[Alex Hung]

From: Robin Chen 

[WHY]
We want to support low hz case, but the original
vtotal/vtotal_min/vtotal_max can't support more
than 0x7FFF.

[HOW]
We use the 2 HW reg to contorl long vblank case.
1. OTG_V_COUNT_STOP_CONTROL -> vcount_stop
2. OTG_V_COUNT_STOP_CONTROL2 -> vcount_stop_timer

vcount_stop define from which line we stop using vcount
and start using vcount2.
vcount_stop_timer define how long we use vcount2.

Ex:
Vtotal = 7
OTG_V_COUNT_STOP_CONTROL = 4
OTG_V_COUNT_STOP_CONTROL2 = 5

time: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
vcount  : 0, 1, 2, 3, -  -  -  -  -  4,  5,  6
vcount2 : 0, 1, 2, 3, 4,

Reviewed-by: Jun Lei 
Acked-by: Alex Hung 
Signed-off-by: ChunTao Tso 
Signed-off-by: Robin Chen
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  33 
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |   1 +
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   |  28 +++
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h   |   3 +
 .../amd/display/dc/hwss/dcn35/dcn35_init.c|   3 +-
 .../drm/amd/display/dc/hwss/hw_sequencer.h|   1 +
 .../amd/display/dc/inc/hw/timing_generator.h  |   7 +
 .../amd/display/dc/optc/dcn10/dcn10_optc.h|   6 +-
 .../amd/display/dc/optc/dcn35/dcn35_optc.c| 165 +-
 .../amd/display/dc/optc/dcn35/dcn35_optc.h|   6 +-
 .../dc/resource/dcn35/dcn35_resource.h|   2 +
 .../amd/display/modules/freesync/freesync.c   |   2 +
 12 files changed, 253 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 501e0298623a..daf6c7fe0906 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -386,6 +386,30 @@ static void dc_perf_trace_destroy(struct dc_perf_trace 
**perf_trace)
*perf_trace = NULL;
 }
 
+static bool set_long_vtotal(struct dc *dc, struct dc_stream_state *stream, 
struct dc_crtc_timing_adjust *adjust)
+{
+   if (!dc || !stream || !adjust)
+   return false;
+
+   if (!dc->current_state)
+   return false;
+
+   int i;
+
+   for (i = 0; i < MAX_PIPES; i++) {
+   struct pipe_ctx *pipe = >current_state->res_ctx.pipe_ctx[i];
+
+   if (pipe->stream == stream && pipe->stream_res.tg) {
+   if (dc->hwss.set_long_vtotal)
+   dc->hwss.set_long_vtotal(, 1, 
adjust->v_total_min, adjust->v_total_max);
+
+   return true;
+   }
+   }
+
+   return false;
+}
+
 /**
  *  dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR
  *  @dc: dc reference
@@ -420,6 +444,15 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
stream->adjust.v_total_mid = adjust->v_total_mid;
stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
stream->adjust.v_total_min = adjust->v_total_min;
+   stream->adjust.allow_otg_v_count_halt = adjust->allow_otg_v_count_halt;
+
+   if (dc->caps.max_v_total != 0 &&
+   (adjust->v_total_max > dc->caps.max_v_total || 
adjust->v_total_min > dc->caps.max_v_total)) {
+   if (adjust->allow_otg_v_count_halt)
+   return set_long_vtotal(dc, stream, adjust);
+   else
+   return false;
+   }
 
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe = >current_state->res_ctx.pipe_ctx[i];
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index aae2f3a2660d..465e15f57f93 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -974,6 +974,7 @@ struct dc_crtc_timing_adjust {
uint32_t v_total_max;
uint32_t v_total_mid;
uint32_t v_total_mid_frame_num;
+   uint32_t allow_otg_v_count_halt;
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 4b92df23ff0d..2e8ec58a16eb 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -1394,3 +1394,31 @@ void dcn35_set_static_screen_control(struct pipe_ctx 
**pipe_ctx,
set_static_screen_control(pipe_ctx[i]->stream_res.tg,
triggers, params->num_frames);
 }
+
+void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,
+   int num_pipes, uint32_t v_total_min, uint32_t v_total_max)
+{
+   int i = 0;
+   struct long_vtotal_params params = {0};
+
+   params.vertical_total_max = v_total_max;
+   params.vertical_total_min = v_total_min;
+
+   for (i = 0; i < num_pipes; i++) {
+   if (!pipe_ctx[i])
+   continue;
+
+   if (pipe_ctx[i]->stream) {
+   struct dc_crtc_timing *timing = 
_ctx[i]->stream->timing;
+
+  

[PATCH 13/34] drm/amd/display: 3.2.274

[Alex Hung]

From: Aric Cyr 

- Change default size for dummy plane in DML2
- Enable DML2 debug flags
- Add some forward declarations
- Add DML2 folder to include path
- Set DCN351 BB and IP the same as DCN35
- Override min required DCFCLK in dml1_validate
- Fix function banner for amdgpu_dm_psr_disable_all()
- Allow dirty rects to be sent to dmub when abm is active
- Add debug key to allow disabling dtbclk
- Add debug prints for IPS testing
- Exit idle optimizations before HDCP execution
- Add entry and exit counters

Acked-by: Alex Hung 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index c9485a7744d7..09c6a393642a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -51,7 +51,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.273"
+#define DC_VER "3.2.274"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.34.1

[PATCH 12/34] drm/amd/display: Add entry and exit counters

[Alex Hung]

From: Anthony Koo 

[WHY & HOW]
Add new counters in the shared IPS firmware state.

Acked-by: Alex Hung 
Signed-off-by: Anthony Koo 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index a529e369b2ac..02ad641bd8df 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -724,7 +724,13 @@ union dmub_shared_state_ips_driver_signals {
  */
 struct dmub_shared_state_ips_fw {
union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS 
signal bits */
-   uint32_t reserved[61]; /**< Reversed, to be updated when adding new 
fields. */
+   uint32_t rcg_entry_count; /**< Entry counter for RCG */
+   uint32_t rcg_exit_count; /**< Exit counter for RCG */
+   uint32_t ips1_entry_count; /**< Entry counter for IPS1 */
+   uint32_t ips1_exit_count; /**< Exit counter for IPS1 */
+   uint32_t ips2_entry_count; /**< Entry counter for IPS2 */
+   uint32_t ips2_exit_count; /**< Exit counter for IPS2 */
+   uint32_t reserved[55]; /**< Reversed, to be updated when adding new 
fields. */
 }; /* 248-bytes, fixed */
 
 /**
-- 
2.34.1

[PATCH 11/34] drm/amd/display: Exit idle optimizations before HDCP execution

[Alex Hung]

From: Nicholas Kazlauskas 

[WHY]
PSP can access DCN registers during command submission and we need
to ensure that DCN is not in PG before doing so.

[HOW]
Add a callback to DM to lock and notify DC for idle optimization exit.
It can't be DC directly because of a potential race condition with the
link protection thread and the rest of DM operation.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Charlene Liu 
Acked-by: Alex Hung 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c| 10 ++
 drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h |  8 
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index 5e01c6e24cbc..9a5a1726acaf 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -88,6 +88,14 @@ static uint8_t is_cp_desired_hdcp2(struct mod_hdcp *hdcp)
!hdcp->connection.is_hdcp2_revoked;
 }
 
+static void exit_idle_optimizations(struct mod_hdcp *hdcp)
+{
+   struct mod_hdcp_dm *dm = >config.dm;
+
+   if (dm->funcs.exit_idle_optimizations)
+   dm->funcs.exit_idle_optimizations(dm->handle);
+}
+
 static enum mod_hdcp_status execution(struct mod_hdcp *hdcp,
struct mod_hdcp_event_context *event_ctx,
union mod_hdcp_transition_input *input)
@@ -543,6 +551,8 @@ enum mod_hdcp_status mod_hdcp_process_event(struct mod_hdcp 
*hdcp,
memset(_ctx, 0, sizeof(struct mod_hdcp_event_context));
event_ctx.event = event;
 
+   exit_idle_optimizations(hdcp);
+
/* execute and transition */
exec_status = execution(hdcp, _ctx, >auth.trans_input);
trans_status = transition(
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h 
b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
index a4d344a4db9e..cdb17b093f2b 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
@@ -156,6 +156,13 @@ struct mod_hdcp_ddc {
} funcs;
 };
 
+struct mod_hdcp_dm {
+   void *handle;
+   struct {
+   void (*exit_idle_optimizations)(void *handle);
+   } funcs;
+};
+
 struct mod_hdcp_psp {
void *handle;
void *funcs;
@@ -272,6 +279,7 @@ struct mod_hdcp_display_query {
 struct mod_hdcp_config {
struct mod_hdcp_psp psp;
struct mod_hdcp_ddc ddc;
+   struct mod_hdcp_dm dm;
uint8_t index;
 };
 
-- 
2.34.1

[PATCH 10/34] drm/amd/display: Add debug prints for IPS testing

[Alex Hung]

From: Nicholas Kazlauskas 

[WHY]
To log commit states and when we transition in/out of allow and idle
states and the caller.

[HOW]
Add a new logging helper and wrap idle optimization calls to receive
the caller.

Reviewed-by: Duncan Ma 
Acked-by: Alex Hung 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 10 ++-
 drivers/gpu/drm/amd/display/dc/dc.h   |  7 +-
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  | 73 +++
 .../drm/amd/display/include/logger_types.h|  1 +
 4 files changed, 86 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 613d09c42f3b..501e0298623a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4820,11 +4820,15 @@ bool dc_set_replay_allow_active(struct dc *dc, bool 
active)
return true;
 }
 
-void dc_allow_idle_optimizations(struct dc *dc, bool allow)
+void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char 
const *caller_name)
 {
if (dc->debug.disable_idle_power_optimizations)
return;
 
+   if (allow != dc->idle_optimizations_allowed)
+   DC_LOG_IPS("%s: allow_idle old=%d new=%d (caller=%s)\n", 
__func__,
+  dc->idle_optimizations_allowed, allow, caller_name);
+
if (dc->caps.ips_support && (dc->config.disable_ips == 
DMUB_IPS_DISABLE_ALL))
return;
 
@@ -4839,10 +4843,10 @@ void dc_allow_idle_optimizations(struct dc *dc, bool 
allow)
dc->idle_optimizations_allowed = allow;
 }
 
-void dc_exit_ips_for_hw_access(struct dc *dc)
+void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name)
 {
if (dc->caps.ips_support)
-   dc_allow_idle_optimizations(dc, false);
+   dc_allow_idle_optimizations_internal(dc, false, caller_name);
 }
 
 bool dc_dmub_is_ips_idle_state(struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index c1d8288a08b3..c9485a7744d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -2339,8 +2339,11 @@ void dc_get_clock(struct dc *dc, enum dc_clock_type 
clock_type, struct dc_clock_
 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct 
dc_plane_state *plane,
struct dc_cursor_attributes *cursor_attr);
 
-void dc_allow_idle_optimizations(struct dc *dc, bool allow);
-void dc_exit_ips_for_hw_access(struct dc *dc);
+#define dc_allow_idle_optimizations(dc, allow) 
dc_allow_idle_optimizations_internal(dc, allow, __func__)
+#define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, 
__func__)
+
+void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const 
char *caller_name);
+void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char 
*caller_name);
 bool dc_dmub_is_ips_idle_state(struct dc *dc);
 
 /* set min and max memory clock to lowest and highest DPM level, respectively 
*/
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 6083b1dcf050..b168dfc79381 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -910,6 +910,8 @@ void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv 
*dc_dmub_srv)
return;
}
 
+   DC_LOG_ERROR("%s: DMCUB error - collecting diagnostic data\n", 
__func__);
+
if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, _data)) {
DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", 
__func__);
return;
@@ -1201,6 +1203,7 @@ bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv 
*dc_dmub_srv, bool wait)
 
 static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
 {
+   volatile const struct dmub_shared_state_ips_fw *ips_fw;
struct dc_dmub_srv *dc_dmub_srv;
union dmub_rb_cmd cmd = {0};
 
@@ -1211,6 +1214,7 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, 
bool allow_idle)
return;
 
dc_dmub_srv = dc->ctx->dmub_srv;
+   ips_fw = 
_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;
 
memset(, 0, sizeof(cmd));
cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT;
@@ -1226,6 +1230,12 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, 
bool allow_idle)

_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver;
union dmub_shared_state_ips_driver_signals new_signals;
 
+   DC_LOG_IPS(
+   "%s wait idle (ips1_commit=%d ips2_commit=%d)",
+   __func__,
+   ips_fw->signals.bits.ips1_commit,
+   ips_fw->signals.bits.ips2_commit);
+

[PATCH 09/34] drm/amd/display: Add debug key to allow disabling dtbclk

[Alex Hung]

From: Muhammad Ahmed 

[HOW]
Add debug key to allow disabling dtbclk

Reviewed-by: Charlene Liu 
Acked-by: Alex Hung 
Signed-off-by: Muhammad Ahmed 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/dc.h  | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index c378b879c76d..c6030bed95a0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -244,7 +244,8 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
}
 
if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
-   dcn35_smu_set_dtbclk(clk_mgr, false);
+   if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)
+   dcn35_smu_set_dtbclk(clk_mgr, false);
clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
}
/* check that we're not already in lower */
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index ee8453bf958f..c1d8288a08b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -435,6 +435,7 @@ struct dc_config {
unsigned int disable_ips;
unsigned int disable_ips_in_vpb;
bool usb4_bw_alloc_support;
+   bool allow_0_dtb_clk;
 };
 
 enum visual_confirm {
-- 
2.34.1

[PATCH 08/34] drm/amd/display: Allow dirty rects to be sent to dmub when abm is active

[Alex Hung]

From: Josip Pavic 

[WHY]
It's beneficial for ABM to know when new frame data are available.

[HOW]
Add new condition to allow dirty rects to be sent to DMUB when ABM is
active. ABM will use this as a signal that a new frame has arrived.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Anthony Koo 
Acked-by: Alex Hung 
Signed-off-by: Josip Pavic 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5211c1c0f3c0..613d09c42f3b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3270,6 +3270,9 @@ static bool dc_dmub_should_send_dirty_rect_cmd(struct dc 
*dc, struct dc_stream_s
if (stream->link->replay_settings.config.replay_supported)
return true;
 
+   if (stream->ctx->dce_version >= DCN_VERSION_3_5 && stream->abm_level)
+   return true;
+
return false;
 }
 
-- 
2.34.1

[PATCH 07/34] drm/amd/display: Fix function banner for amdgpu_dm_psr_disable_all()

[Alex Hung]

From: Roman Li 

[WHY]
Incorrect function name in function banner.

[HOW]
Correct name and brief description.

Reviewed-by: Hersen Wu 
Reviewed-by: Aurabindo Pillai 
Acked-by: Alex Hung 
Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 1f08c6564c3b..a48a79e84e82 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -210,7 +210,7 @@ bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
 }
 
 /*
- * amdgpu_dm_psr_disable() - disable psr f/w
+ * amdgpu_dm_psr_disable_all() - disable psr f/w for all streams
  * if psr is enabled on any stream
  *
  * Return: true if success
-- 
2.34.1

[PATCH 06/34] drm/amd/display: Override min required DCFCLK in dml1_validate

[Alex Hung]

From: Sohaib Nadeem 

[WHY]:
Increasing min DCFCLK addresses underflow issues that occur when phantom
pipe is turned on for some Sub-Viewport configs

[HOW]:
dcn32_override_min_req_dcfclk is added to override DCFCLK value in
dml1_validate when subviewport is being used.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Alvin Lee 
Acked-by: Alex Hung 
Signed-off-by: Sohaib Nadeem 
---
 .../gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c   | 6 ++
 .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c  | 1 +
 .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h  | 3 +++
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 87760600e154..f98def6c8c2d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -782,3 +782,9 @@ void 
dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc
pipe_cnt++;
}
 }
+
+void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context)
+{
+   if (dcn32_subvp_in_use(dc, context) && 
context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_KHZ)
+   context->bw_ctx.bw.dcn.clk.dcfclk_khz = MIN_SUBVP_DCFCLK_KHZ;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 3f3951f3ba98..f844f57ecc49 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -1771,6 +1771,7 @@ static bool dml1_validate(struct dc *dc, struct dc_state 
*context, bool fast_val
dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, 
vlevel);
 
dcn32_override_min_req_memclk(dc, context);
+   dcn32_override_min_req_dcfclk(dc, context);
 
BW_VAL_TRACE_END_WATERMARKS();
 
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h 
b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
index 0c87b0fabba7..2258c5c7212d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
@@ -42,6 +42,7 @@
 #define SUBVP_ACTIVE_MARGIN_LIST_LEN 2
 #define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800
 #define DCN3_2_VMIN_DISPCLK_HZ 71700
+#define MIN_SUBVP_DCFCLK_KHZ 40
 
 #define TO_DCN32_RES_POOL(pool)\
container_of(pool, struct dcn32_resource_pool, base)
@@ -181,6 +182,8 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct 
dc_state *context, int
 
 void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct 
dc_state *context, display_e2e_pipe_params_st *pipes);
 
+void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);
+
 /* definitions for run time init of reg offsets */
 
 /* CLK SRC */
-- 
2.34.1

[PATCH 05/34] drm/amd/display: Set DCN351 BB and IP the same as DCN35

[Alex Hung]

From: Xi Liu 

[WHY & HOW]
DCN351 and DCN35 should use the same bounding box and IP settings.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Jun Lei 
Acked-by: Alex Hung 
Signed-off-by: Xi Liu 
---
 .../gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c   | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 17a58f41fc6a..a20f28a5d2e7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -228,17 +228,13 @@ void dml2_init_socbb_params(struct dml2_context *dml2, 
const struct dc *in_dc, s
break;
 
case dml_project_dcn35:
+   case dml_project_dcn351:
out->num_chans = 4;
out->round_trip_ping_latency_dcfclk_cycles = 106;
out->smn_latency_us = 2;
out->dispclk_dppclk_vco_speed_mhz = 3600;
break;
 
-   case dml_project_dcn351:
-   out->num_chans = 16;
-   out->round_trip_ping_latency_dcfclk_cycles = 1100;
-   out->smn_latency_us = 2;
-   break;
}
/* ---Overrides if available--- */
if (dml2->config.bbox_overrides.dram_num_chan)
-- 
2.34.1

[PATCH 04/34] drm/amd/display: Add DML2 folder to include path

[Alex Hung]

From: Aurabindo Pillai 

Add DML2 compilation rule in the Makefile.

Reviewed-by: Chaitanya Dhere 
Acked-by: Alex Hung 
Signed-off-by: Aurabindo Pillai 
---
 drivers/gpu/drm/amd/display/dc/dml2/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/Makefile 
b/drivers/gpu/drm/amd/display/dc/dml2/Makefile
index acff3449b8d7..1c9498a72520 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml2/Makefile
@@ -67,6 +67,7 @@ frame_warn_flag := -Wframe-larger-than=2048
 endif
 endif
 
+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2
 CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_core.o := $(dml2_ccflags) 
$(frame_warn_flag)
 CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_util.o := $(dml2_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_wrapper.o := $(dml2_ccflags)
-- 
2.34.1

[PATCH 03/34] drm/amd/display: Add some forward declarations

[Alex Hung]

From: Aurabindo Pillai 

[WHAT]
Add DML2 pipe and config struct forward declaration as a
preparation for DML2.

Reviewed-by: Chaitanya Dhere 
Acked-by: Alex Hung 
Signed-off-by: Aurabindo Pillai 
---
 drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h
index 2f91244a7b01..1538b708d8be 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h
@@ -30,6 +30,8 @@
 #include "dml2_dc_types.h"
 
 struct dml2_context;
+struct dml2_dml_to_dc_pipe_mapping;
+struct dml_display_cfg_st;
 
 /*
  * dml2_map_dc_pipes - Creates a pipe linkage in dc_state based on current 
display config.
-- 
2.34.1

[PATCH 02/34] drm/amd/display: Enable DML2 debug flags

[Alex Hung]

From: Aurabindo Pillai 

[WHY & HOW]
Enable DML2 related debug config options in DM for testing purposes.

Reviewed-by: Chaitanya Dhere 
Acked-by: Alex Hung 
Signed-off-by: Aurabindo Pillai 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 32efce81a5a7..e12f56ca3b6a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1766,6 +1766,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
adev->dm.dc->debug.force_subvp_mclk_switch = true;
 
+   if (amdgpu_dc_debug_mask & DC_ENABLE_DML2)
+   adev->dm.dc->debug.using_dml2 = true;
+
adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
 
/* TODO: Remove after DP2 receiver gets proper support of Cable ID 
feature */
-- 
2.34.1

[PATCH 01/34] drm/amd/display: Change default size for dummy plane in DML2

[Alex Hung]

From: Swapnil Patel 

[WHY & HOW]
Currently, to map dc states into dml_display_cfg,
We create a dummy plane if the stream doesn't have any planes
attached to it. This dummy plane uses max addersable width height.
This results in certain mode validations failing when they shouldn't.

Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: sta...@vger.kernel.org
Reviewed-by: Chaitanya Dhere 
Acked-by: Alex Hung 
Signed-off-by: Swapnil Patel 
---
 .../display/dc/dml2/dml2_translation_helper.c  | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c 
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 1ba6933d2b36..17a58f41fc6a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -824,13 +824,25 @@ static struct scaler_data get_scaler_data_for_plane(const 
struct dc_plane_state
 
 static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, 
unsigned int location, const struct dc_stream_state *in)
 {
+   dml_uint_t width, height;
+
+   if (in->timing.h_addressable > 3840)
+   width = 3840;
+   else
+   width = in->timing.h_addressable;   // 4K max
+
+   if (in->timing.v_addressable > 2160)
+   height = 2160;
+   else
+   height = in->timing.v_addressable;  // 4K max
+
out->CursorBPP[location] = dml_cur_32bit;
out->CursorWidth[location] = 256;
 
out->GPUVMMinPageSizeKBytes[location] = 256;
 
-   out->ViewportWidth[location] = in->timing.h_addressable;
-   out->ViewportHeight[location] = in->timing.v_addressable;
+   out->ViewportWidth[location] = width;
+   out->ViewportHeight[location] = height;
out->ViewportStationary[location] = false;
out->ViewportWidthChroma[location] = 0;
out->ViewportHeightChroma[location] = 0;
@@ -849,7 +861,7 @@ static void populate_dummy_dml_plane_cfg(struct 
dml_plane_cfg_st *out, unsigned
out->HTapsChroma[location] = 0;
out->VTapsChroma[location] = 0;
out->SourceScan[location] = dml_rotation_0;
-   out->ScalerRecoutWidth[location] = in->timing.h_addressable;
+   out->ScalerRecoutWidth[location] = width;
 
out->LBBitPerPixel[location] = 57;
 
-- 
2.34.1

[PATCH 00/34] DC Patches Feb 28, 2020

[Alex Hung]

This DC patchset brings improvements in multiple areas. In summary, we 
highlight:

* Fixes on HDCP, eDP and FW idle check.
* Enhancement in debug messages
* Improvement on updates sequences
* DPP refactoring to a new directory
* Enhancements in DMUB

Cc: Daniel Wheeler 

Allen Pan (1):
  drm/amd/display: Add a dc_state NULL check in dc_state_release

Alvin Lee (1):
  drm/amd/display: Backup and restore only on full updates

Anthony Koo (2):
  drm/amd/display: Add entry and exit counters
  drm/amd/display: Update DMUB flags and definitions

Aric Cyr (2):
  drm/amd/display: 3.2.274
  drm/amd/display: 3.2.275

Aurabindo Pillai (3):
  drm/amd/display: Enable DML2 debug flags
  drm/amd/display: Add some forward declarations
  drm/amd/display: Add DML2 folder to include path

ChunTao Tso (1):
  drm/amd/display: Amend coasting vtotal for replay low hz

Dillon Varone (1):
  drm/amd/display: Init DPPCLK from SMU on dcn32

George Shen (1):
  drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split

Josip Pavic (1):
  drm/amd/display: Allow dirty rects to be sent to dmub when abm is
active

Muhammad Ahmed (2):
  drm/amd/display: Add debug key to allow disabling dtbclk
  drm/amd/display: Set the power_down_on_boot function pointer to null

Nicholas Kazlauskas (6):
  drm/amd/display: Add debug prints for IPS testing
  drm/amd/display: Exit idle optimizations before HDCP execution
  drm/amd/display: Fix idle check for shared firmware state
  drm/amd/display: Add guards for idle on reg read/write
  drm/amd/display: Guard cursor idle reallow by DC debug option
  drm/amd/display: Add debug counters to IPS exit prints

Revalla Hari Krishna (1):
  drm/amd/display: Refactor DPP into a component directory

Robin Chen (1):
  drm/amd/display: Support long vblank feature

Rodrigo Siqueira (2):
  drm/amd/display: Return the correct HDCP error code
  drm/amd/display: Add comments to v_total calculation and drop legacy
TODO

Roman Li (1):
  drm/amd/display: Fix function banner for amdgpu_dm_psr_disable_all()

Ryan Lin (1):
  drm/amd/display: Add monitor patch for specific eDP

Sohaib Nadeem (1):
  drm/amd/display: Override min required DCFCLK in dml1_validate

Swapnil Patel (1):
  drm/amd/display: Change default size for dummy plane in DML2

Wenjing Liu (4):
  drm/amd/display: Update odm when ODM combine is changed on an otg
master pipe with no plane
  drm/amd/display: Implement update_planes_and_stream_v3 sequence
  drm/amd/display: Lock all enabled otg pipes even with no planes
  drm/amd/display: Implement wait_for_odm_update_pending_complete

Xi Liu (1):
  drm/amd/display: Set DCN351 BB and IP the same as DCN35

 drivers/gpu/drm/amd/display/Makefile  |   1 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   3 +
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |   6 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |   2 +-
 drivers/gpu/drm/amd/display/dc/Makefile   |   2 +-
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  |  14 +
 .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c  |   3 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 824 --
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  37 +
 .../gpu/drm/amd/display/dc/core/dc_state.c|   4 +-
 .../gpu/drm/amd/display/dc/core/dc_stream.c   |   4 +-
 drivers/gpu/drm/amd/display/dc/dc.h   | 174 ++--
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  |  94 ++
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h  |   1 +
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |   1 +
 drivers/gpu/drm/amd/display/dc/dc_types.h |   4 +-
 .../gpu/drm/amd/display/dc/dce/dmub_replay.c  |   2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/Makefile |   4 +-
 .../amd/display/dc/dcn10/dcn10_cm_common.c|   2 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c  |   1 +
 drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   2 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c  |  14 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.h  |   2 +
 .../gpu/drm/amd/display/dc/dcn201/Makefile|   2 +-
 .../drm/amd/display/dc/dcn201/dcn201_opp.c|   1 +
 drivers/gpu/drm/amd/display/dc/dcn30/Makefile |   2 -
 .../amd/display/dc/dcn30/dcn30_cm_common.c|   2 +-
 drivers/gpu/drm/amd/display/dc/dcn32/Makefile |   2 +-
 .../display/dc/dcn32/dcn32_resource_helpers.c |   6 +
 drivers/gpu/drm/amd/display/dc/dcn35/Makefile |   2 +-
 drivers/gpu/drm/amd/display/dc/dml2/Makefile  |   1 +
 .../display/dc/dml2/dml2_dc_resource_mgmt.h   |   2 +
 .../display/dc/dml2/dml2_translation_helper.c |  24 +-
 .../drm/amd/display/dc/dml2/dml2_wrapper.c|  28 +-
 .../drm/amd/display/dc/dml2/dml2_wrapper.h|   3 +
 drivers/gpu/drm/amd/display/dc/dpp/Makefile   |  77 ++
 .../amd/display/dc/dpp/dcn10/CMakeLists.txt   |   6 +
 .../display/dc/{ => dpp}/dcn10/dcn10_dpp.c|   2 +-
 .../display/dc/{ => dpp}/dcn10/dcn10_dpp.h|   0
 .../display/dc/{ => dpp}/dcn10/dcn10_dpp_cm.c |   4 +-
 .../dc/{ => dpp}/dcn10/dcn10_dpp_dscl.c   |   2 +-
 

RE: [PATCH] amd/amdkfd: remove unused parameter

[Kasiviswanathan, Harish]

[AMD Official Use Only - General]

Reviewed-by: Harish Kasiviswanathan 

-Original Message-
From: amd-gfx  On Behalf Of Eric Huang
Sent: Wednesday, February 28, 2024 10:17 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, JinHuiEric 
Subject: [PATCH] amd/amdkfd: remove unused parameter

The adev can be found from bo by amdgpu_ttm_adev(bo->tbo.bdev),
and adev is also not used in the function
amdgpu_amdkfd_map_gtt_bo_to_gart().

Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h   | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +--
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 4fb32d86cd0e..0ef223c2affb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -320,7 +320,7 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem 
*mem,
 void **kptr, uint64_t *size);
 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);

-int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct 
amdgpu_bo *bo);
+int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo);

 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
struct dma_fence __rcu **ef);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index ef71b12062a1..bf8e6653341f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -2189,13 +2189,12 @@ int amdgpu_amdkfd_gpuvm_sync_memory(

 /**
  * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference 
count
- * @adev: Device to which allocated BO belongs
  * @bo: Buffer object to be mapped
  *
  * Before return, bo reference count is incremented. To release the reference 
and unpin/
  * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
  */
-int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct 
amdgpu_bo *bo)
+int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
 {
int ret;

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 824e660283b2..f030cafc5a0a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -371,7 +371,7 @@ static int kfd_ioctl_create_queue(struct file *filep, 
struct kfd_process *p,
goto err_wptr_map_gart;
}

-   err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo);
+   err = amdgpu_amdkfd_map_gtt_bo_to_gart(wptr_bo);
if (err) {
pr_err("Failed to map wptr bo to GART\n");
goto err_wptr_map_gart;
--
2.34.1

Re: [PATCH] drm/amd/display: Add monitor patch for specific eDP

[Hamza Mahfooz]

On 2/27/24 13:18, Rodrigo Siqueira wrote:

From: Ivan Lipski 

[WHY]
Some eDP panels's ext caps don't write initial value cause the value of
dpcd_addr(0x317) is random.  It means that sometimes the eDP will
clarify it is OLED, miniLED...etc cause the backlight control interface
is incorrect.

[HOW]
Add a new panel patch to remove sink ext caps(HDR,OLED...etc)


I wonder if it would make sense to turn this into a DPCD qurik (see
drivers/gpu/drm/display/drm_dp_helper.c). Since, it is rather unsettling
that we have so many panel quirks in our driver.



Cc: sta...@vger.kernel.org # 6.5.x
Cc: Hamza Mahfooz 
Cc: Tsung-hua Lin 
Cc: Chris Chi 
Cc: Harry Wentland 
Tested-by: Daniel Wheeler 
Reviewed-by: Sun peng Li 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Ivan Lipski 
---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index d9a482908380..764dc3ffd91b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -63,6 +63,12 @@ static void apply_edid_quirks(struct edid *edid, struct 
dc_edid_caps *edid_caps)
DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id 
%X\n", panel_id);
edid_caps->panel_patch.disable_fams = true;
break;
+   /* Workaround for some monitors that do not clear DPCD 0x317 if 
FreeSync is unsupported */
+   case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
+   case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
+   DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id 
%X\n", panel_id);
+   edid_caps->panel_patch.remove_sink_ext_caps = true;
+   break;
default:
return;
}

--
Hamza

Re: [PATCH] drm/amd/display: Add monitor patch for specific eDP

[Harry Wentland]

On 2024-02-27 13:18, Rodrigo Siqueira wrote:
> From: Ivan Lipski 
> 
> [WHY]
> Some eDP panels's ext caps don't write initial value cause the value of
> dpcd_addr(0x317) is random.  It means that sometimes the eDP will
> clarify it is OLED, miniLED...etc cause the backlight control interface
> is incorrect.
> 
> [HOW]
> Add a new panel patch to remove sink ext caps(HDR,OLED...etc)
> 
> Cc: sta...@vger.kernel.org # 6.5.x
> Cc: Hamza Mahfooz 
> Cc: Tsung-hua Lin 
> Cc: Chris Chi 
> Cc: Harry Wentland 
> Tested-by: Daniel Wheeler 
> Reviewed-by: Sun peng Li 
> Acked-by: Rodrigo Siqueira 
> Signed-off-by: Ivan Lipski 

Acked-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index d9a482908380..764dc3ffd91b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -63,6 +63,12 @@ static void apply_edid_quirks(struct edid *edid, struct 
> dc_edid_caps *edid_caps)
>   DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id 
> %X\n", panel_id);
>   edid_caps->panel_patch.disable_fams = true;
>   break;
> + /* Workaround for some monitors that do not clear DPCD 0x317 if 
> FreeSync is unsupported */
> + case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
> + case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
> + DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id 
> %X\n", panel_id);
> + edid_caps->panel_patch.remove_sink_ext_caps = true;
> + break;
>   default:
>   return;
>   }

[PATCH] amd/amdkfd: remove unused parameter

[Eric Huang]

The adev can be found from bo by amdgpu_ttm_adev(bo->tbo.bdev),
and adev is also not used in the function
amdgpu_amdkfd_map_gtt_bo_to_gart().

Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h   | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +--
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 4fb32d86cd0e..0ef223c2affb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -320,7 +320,7 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem 
*mem,
 void **kptr, uint64_t *size);
 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
 
-int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct 
amdgpu_bo *bo);
+int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo);
 
 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
struct dma_fence __rcu **ef);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index ef71b12062a1..bf8e6653341f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -2189,13 +2189,12 @@ int amdgpu_amdkfd_gpuvm_sync_memory(
 
 /**
  * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference 
count
- * @adev: Device to which allocated BO belongs
  * @bo: Buffer object to be mapped
  *
  * Before return, bo reference count is incremented. To release the reference 
and unpin/
  * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
  */
-int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct 
amdgpu_bo *bo)
+int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
 {
int ret;
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 824e660283b2..f030cafc5a0a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -371,7 +371,7 @@ static int kfd_ioctl_create_queue(struct file *filep, 
struct kfd_process *p,
goto err_wptr_map_gart;
}
 
-   err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo);
+   err = amdgpu_amdkfd_map_gtt_bo_to_gart(wptr_bo);
if (err) {
pr_err("Failed to map wptr bo to GART\n");
goto err_wptr_map_gart;
-- 
2.34.1

Re: [PATCH 1/2] Revert "drm/amd: Remove freesync video mode amdgpu parameter"

[Christian König]

Am 28.02.24 um 15:23 schrieb Alex Deucher:

On Wed, Feb 28, 2024 at 2:03 AM Christian König
 wrote:

Am 27.02.24 um 19:48 schrieb Alex Deucher:

This reverts commit e94e787e37b99645e7c02d20d0a1ba0f8a18a82a.

This conflicts with how compositors want to handle VRR.  Now
that compositors actually handle VRR, we probably don't need
freesync video.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2985

Scratching my head what actually happens here? Doesn't the problem then
just depend on a module parameter?

Yes.  The problem is that when freesync video is enabled, compositors
don't know which modes are actual modes and which are a VRR video
mode.  There are still customers that want the vrr video mode smooth
video playback, but compositors don't want this by default.  I guess
the alternative is to just drop this feature altogether now that
compositors and media players are starting to support this properly.


That's what I would suggest as well.

As far as I can see adding those modes is actually buggy behavior and we 
need to avoid it.


Christian.



Alex


Regards,
Christian.


Signed-off-by: Alex Deucher 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 27 +
   2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 0e365cadcc3fc..925026c183f41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -194,6 +194,7 @@ extern int amdgpu_emu_mode;
   extern uint amdgpu_smu_memory_pool_size;
   extern int amdgpu_smu_pptable_id;
   extern uint amdgpu_dc_feature_mask;
+extern uint amdgpu_freesync_vid_mode;
   extern uint amdgpu_dc_debug_mask;
   extern uint amdgpu_dc_visual_confirm;
   extern int amdgpu_dm_abm_level;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 15a8a64fc4e28..82b154b103f43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -199,6 +199,7 @@ int amdgpu_mes_kiq;
   int amdgpu_noretry = -1;
   int amdgpu_force_asic_type = -1;
   int amdgpu_tmz = -1; /* auto */
+uint amdgpu_freesync_vid_mode;
   int amdgpu_reset_method = -1; /* auto */
   int amdgpu_num_kcq = -1;
   int amdgpu_smartshift_bias;
@@ -883,6 +884,32 @@ module_param_named(damageclips, amdgpu_damage_clips, int, 
0444);
   MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = 
on)");
   module_param_named(tmz, amdgpu_tmz, int, 0444);

+/**
+ * DOC: freesync_video (uint)
+ * Enable the optimization to adjust front porch timing to achieve seamless
+ * mode change experience when setting a freesync supported mode for which full
+ * modeset is not needed.
+ *
+ * The Display Core will add a set of modes derived from the base FreeSync
+ * video mode into the corresponding connector's mode list based on commonly
+ * used refresh rates and VRR range of the connected display, when users enable
+ * this feature. From the userspace perspective, they can see a seamless mode
+ * change experience when the change between different refresh rates under the
+ * same resolution. Additionally, userspace applications such as Video playback
+ * can read this modeset list and change the refresh rate based on the video
+ * frame rate. Finally, the userspace can also derive an appropriate mode for a
+ * particular refresh rate based on the FreeSync Mode and add it to the
+ * connector's mode list.
+ *
+ * Note: This is an experimental feature.
+ *
+ * The default value: 0 (off).
+ */
+MODULE_PARM_DESC(
+ freesync_video,
+ "Enable freesync modesetting optimization feature (0 = off (default), 1 = 
on)");
+module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
+
   /**
* DOC: reset_method (int)
* GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 
3 = mode2, 4 = baco)

Re: [PATCH] drm/amdgpu: Removed used parameter

[Lazar, Lijo]

On 2/27/2024 9:23 PM, Harish Kasiviswanathan wrote:
> Also passing adev is misleading if BO is associated with different adev.
> In this case BO is mapped to a different device
> 
Looks like a typo in subject - unused?

Thanks,
Lijo

> Signed-off-by: Harish Kasiviswanathan 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h   | 2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++--
>  drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 4fb32d86cd0e..0ef223c2affb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -320,7 +320,7 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct 
> kgd_mem *mem,
>void **kptr, uint64_t *size);
>  void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
>  
> -int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct 
> amdgpu_bo *bo);
> +int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo);
>  
>  int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
>   struct dma_fence __rcu **ef);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index ef71b12062a1..d0819fa5fcd8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -2189,13 +2189,13 @@ int amdgpu_amdkfd_gpuvm_sync_memory(
>  
>  /**
>   * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference 
> count
> - * @adev: Device to which allocated BO belongs
>   * @bo: Buffer object to be mapped
>   *
> + * BO will be mapped to GART of adev to which it is previously associated 
> with
>   * Before return, bo reference count is incremented. To release the 
> reference and unpin/
>   * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
>   */
> -int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct 
> amdgpu_bo *bo)
> +int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
>  {
>   int ret;
>  
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> index 824e660283b2..f030cafc5a0a 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> @@ -371,7 +371,7 @@ static int kfd_ioctl_create_queue(struct file *filep, 
> struct kfd_process *p,
>   goto err_wptr_map_gart;
>   }
>  
> - err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo);
> + err = amdgpu_amdkfd_map_gtt_bo_to_gart(wptr_bo);
>   if (err) {
>   pr_err("Failed to map wptr bo to GART\n");
>   goto err_wptr_map_gart;

Re: [PATCH v5 7/8] drm/amd/display: Introduce KUnit tests to dc_dmub_srv library

[Rodrigo Siqueira Jordao]

On 2/26/24 04:12, Jani Nikula wrote:

On Thu, 22 Feb 2024, Rodrigo Siqueira  wrote:

diff --git a/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig 
b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
index eb6f81601757..4c5861ad58bd 100644
--- a/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
+++ b/drivers/gpu/drm/amd/display/test/kunit/.kunitconfig
@@ -4,5 +4,6 @@ CONFIG_DRM=y
  CONFIG_DRM_AMDGPU=y
  CONFIG_DRM_AMD_DC=y
  CONFIG_AMD_DC_BASICS_KUNIT_TEST=y
+CONFIG_AMD_DC_KUNIT_TEST=y
  CONFIG_DCE_KUNIT_TEST=y
  CONFIG_DML_KUNIT_TEST=y


A bit random patch to comment on, but this hunk demonstrates the point:

Should all the configs have DRM_AMD_ prefix to put them in a
"namespace"?



You are right! I'll fix this in the next version.

Thanks
Siqueira



BR,
Jani.

Re: [PATCH] drm/amdgpu: Removed used parameter

[Alex Deucher]

On Tue, Feb 27, 2024 at 11:13 AM Harish Kasiviswanathan
 wrote:
>
> Also passing adev is misleading if BO is associated with different adev.
> In this case BO is mapped to a different device
>
> Signed-off-by: Harish Kasiviswanathan 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h   | 2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++--
>  drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 4fb32d86cd0e..0ef223c2affb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -320,7 +320,7 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct 
> kgd_mem *mem,
>  void **kptr, uint64_t *size);
>  void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
>
> -int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct 
> amdgpu_bo *bo);
> +int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo);
>
>  int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
> struct dma_fence __rcu **ef);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index ef71b12062a1..d0819fa5fcd8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -2189,13 +2189,13 @@ int amdgpu_amdkfd_gpuvm_sync_memory(
>
>  /**
>   * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference 
> count
> - * @adev: Device to which allocated BO belongs
>   * @bo: Buffer object to be mapped
>   *
> + * BO will be mapped to GART of adev to which it is previously associated 
> with
>   * Before return, bo reference count is incremented. To release the 
> reference and unpin/
>   * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
>   */
> -int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct 
> amdgpu_bo *bo)
> +int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
>  {
> int ret;
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> index 824e660283b2..f030cafc5a0a 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> @@ -371,7 +371,7 @@ static int kfd_ioctl_create_queue(struct file *filep, 
> struct kfd_process *p,
> goto err_wptr_map_gart;
> }
>
> -   err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo);
> +   err = amdgpu_amdkfd_map_gtt_bo_to_gart(wptr_bo);
> if (err) {
> pr_err("Failed to map wptr bo to GART\n");
> goto err_wptr_map_gart;
> --
> 2.34.1
>

Re: [PATCH] drm/amd/swsmu: modify the gfx activity scaling

[Alex Deucher]

On Wed, Feb 28, 2024 at 6:39 AM Li Ma  wrote:
>
> Add an if condition for gfx activity because the scaling has been changed 
> after smu fw version 5d4600.
> And remove a warning log.
>
> Signed-off-by: Li Ma 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c   | 2 --
>  drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 5 -
>  2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> index 2aa7e9945a0b..7ac9bc0df8fd 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> @@ -229,8 +229,6 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)
> smu->smc_driver_if_version = 
> SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
> break;
> case IP_VERSION(14, 0, 0):
> -   if ((smu->smc_fw_version < 0x5d3a00))
> -   dev_warn(smu->adev->dev, "The PMFW version(%x) is 
> behind in this BIOS!\n", smu->smc_fw_version);
> smu->smc_driver_if_version = 
> SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
> break;
> default:
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 47fdbae4adfc..9310c4758e38 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -261,7 +261,10 @@ static int smu_v14_0_0_get_smu_metrics_data(struct 
> smu_context *smu,
> *value = metrics->MpipuclkFrequency;
> break;
> case METRICS_AVERAGE_GFXACTIVITY:
> -   *value = metrics->GfxActivity / 100;
> +   if ((smu->smc_fw_version > 0x5d4600))
> +   *value = metrics->GfxActivity;
> +   else
> +   *value = metrics->GfxActivity / 100;
> break;
> case METRICS_AVERAGE_VCNACTIVITY:
> *value = metrics->VcnActivity / 100;
> --
> 2.25.1
>

Re: [PATCH 1/2] Revert "drm/amd: Remove freesync video mode amdgpu parameter"

[Alex Deucher]

On Wed, Feb 28, 2024 at 2:03 AM Christian König
 wrote:
>
> Am 27.02.24 um 19:48 schrieb Alex Deucher:
> > This reverts commit e94e787e37b99645e7c02d20d0a1ba0f8a18a82a.
> >
> > This conflicts with how compositors want to handle VRR.  Now
> > that compositors actually handle VRR, we probably don't need
> > freesync video.
> >
> > Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2985
>
> Scratching my head what actually happens here? Doesn't the problem then
> just depend on a module parameter?

Yes.  The problem is that when freesync video is enabled, compositors
don't know which modes are actual modes and which are a VRR video
mode.  There are still customers that want the vrr video mode smooth
video playback, but compositors don't want this by default.  I guess
the alternative is to just drop this feature altogether now that
compositors and media players are starting to support this properly.

Alex

>
> Regards,
> Christian.
>
> > Signed-off-by: Alex Deucher 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 27 +
> >   2 files changed, 28 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 0e365cadcc3fc..925026c183f41 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -194,6 +194,7 @@ extern int amdgpu_emu_mode;
> >   extern uint amdgpu_smu_memory_pool_size;
> >   extern int amdgpu_smu_pptable_id;
> >   extern uint amdgpu_dc_feature_mask;
> > +extern uint amdgpu_freesync_vid_mode;
> >   extern uint amdgpu_dc_debug_mask;
> >   extern uint amdgpu_dc_visual_confirm;
> >   extern int amdgpu_dm_abm_level;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > index 15a8a64fc4e28..82b154b103f43 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > @@ -199,6 +199,7 @@ int amdgpu_mes_kiq;
> >   int amdgpu_noretry = -1;
> >   int amdgpu_force_asic_type = -1;
> >   int amdgpu_tmz = -1; /* auto */
> > +uint amdgpu_freesync_vid_mode;
> >   int amdgpu_reset_method = -1; /* auto */
> >   int amdgpu_num_kcq = -1;
> >   int amdgpu_smartshift_bias;
> > @@ -883,6 +884,32 @@ module_param_named(damageclips, amdgpu_damage_clips, 
> > int, 0444);
> >   MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 
> > 1 = on)");
> >   module_param_named(tmz, amdgpu_tmz, int, 0444);
> >
> > +/**
> > + * DOC: freesync_video (uint)
> > + * Enable the optimization to adjust front porch timing to achieve seamless
> > + * mode change experience when setting a freesync supported mode for which 
> > full
> > + * modeset is not needed.
> > + *
> > + * The Display Core will add a set of modes derived from the base FreeSync
> > + * video mode into the corresponding connector's mode list based on 
> > commonly
> > + * used refresh rates and VRR range of the connected display, when users 
> > enable
> > + * this feature. From the userspace perspective, they can see a seamless 
> > mode
> > + * change experience when the change between different refresh rates under 
> > the
> > + * same resolution. Additionally, userspace applications such as Video 
> > playback
> > + * can read this modeset list and change the refresh rate based on the 
> > video
> > + * frame rate. Finally, the userspace can also derive an appropriate mode 
> > for a
> > + * particular refresh rate based on the FreeSync Mode and add it to the
> > + * connector's mode list.
> > + *
> > + * Note: This is an experimental feature.
> > + *
> > + * The default value: 0 (off).
> > + */
> > +MODULE_PARM_DESC(
> > + freesync_video,
> > + "Enable freesync modesetting optimization feature (0 = off (default), 
> > 1 = on)");
> > +module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
> > +
> >   /**
> >* DOC: reset_method (int)
> >* GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = 
> > mode1, 3 = mode2, 4 = baco)
>

Re: [PATCH 1/2] drm/amdgpu: Use rpm_mode flag instead of checking it again for rpm

[Lazar, Lijo]

On 2/28/2024 5:14 PM, Ma Jun wrote:
> Because the rpm_mode flag is already set when the driver
> is initialized, we use it directly for runtime suspend/resume
> instead of checking it again
> 
> Signed-off-by: Ma Jun 

Reviewed-by: Lijo Lazar 

Thanks,
Lijo

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 24 
>  1 file changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index af7fae7907d7..8b83c26dc018 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -2666,7 +2666,7 @@ static int amdgpu_pmops_runtime_suspend(struct device 
> *dev)
>   }
>  
>   adev->in_runpm = true;
> - if (amdgpu_device_supports_px(drm_dev))
> + if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
>   drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
>  
>   /*
> @@ -2676,7 +2676,7 @@ static int amdgpu_pmops_runtime_suspend(struct device 
> *dev)
>* platforms.
>* TODO: this may be also needed for PX capable platform.
>*/
> - if (amdgpu_device_supports_boco(drm_dev))
> + if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
>   adev->mp1_state = PP_MP1_STATE_UNLOAD;
>  
>   ret = amdgpu_device_prepare(drm_dev);
> @@ -2685,15 +2685,15 @@ static int amdgpu_pmops_runtime_suspend(struct device 
> *dev)
>   ret = amdgpu_device_suspend(drm_dev, false);
>   if (ret) {
>   adev->in_runpm = false;
> - if (amdgpu_device_supports_boco(drm_dev))
> + if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
>   adev->mp1_state = PP_MP1_STATE_NONE;
>   return ret;
>   }
>  
> - if (amdgpu_device_supports_boco(drm_dev))
> + if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
>   adev->mp1_state = PP_MP1_STATE_NONE;
>  
> - if (amdgpu_device_supports_px(drm_dev)) {
> + if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
>   /* Only need to handle PCI state in the driver for ATPX
>* PCI core handles it for _PR3.
>*/
> @@ -2702,9 +2702,9 @@ static int amdgpu_pmops_runtime_suspend(struct device 
> *dev)
>   pci_ignore_hotplug(pdev);
>   pci_set_power_state(pdev, PCI_D3cold);
>   drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
> - } else if (amdgpu_device_supports_boco(drm_dev)) {
> + } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
>   /* nothing to do */
> - } else if (amdgpu_device_supports_baco(drm_dev)) {
> + } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
>   amdgpu_device_baco_enter(drm_dev);
>   }
>  
> @@ -2727,7 +2727,7 @@ static int amdgpu_pmops_runtime_resume(struct device 
> *dev)
>   if (!pci_device_is_present(adev->pdev))
>   adev->no_hw_access = true;
>  
> - if (amdgpu_device_supports_px(drm_dev)) {
> + if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
>   drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
>  
>   /* Only need to handle PCI state in the driver for ATPX
> @@ -2739,22 +2739,22 @@ static int amdgpu_pmops_runtime_resume(struct device 
> *dev)
>   if (ret)
>   return ret;
>   pci_set_master(pdev);
> - } else if (amdgpu_device_supports_boco(drm_dev)) {
> + } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
>   /* Only need to handle PCI state in the driver for ATPX
>* PCI core handles it for _PR3.
>*/
>   pci_set_master(pdev);
> - } else if (amdgpu_device_supports_baco(drm_dev)) {
> + } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
>   amdgpu_device_baco_exit(drm_dev);
>   }
>   ret = amdgpu_device_resume(drm_dev, false);
>   if (ret) {
> - if (amdgpu_device_supports_px(drm_dev))
> + if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
>   pci_disable_device(pdev);
>   return ret;
>   }
>  
> - if (amdgpu_device_supports_px(drm_dev))
> + if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
>   drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
>   adev->in_runpm = false;
>   return 0;

Re: [PATCH 2/2] drm/amgpu: Check return value of amdgpu_device_baco_enter/exit

[Lazar, Lijo]

On 2/28/2024 5:14 PM, Ma Jun wrote:
> Check return value of amdgpu_device_baco_enter/exit and print
> warning message because these errors may cause runtime resume failure
> 
> Signed-off-by: Ma Jun 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 8b83c26dc018..11e089cfb465 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -2705,7 +2705,9 @@ static int amdgpu_pmops_runtime_suspend(struct device 
> *dev)
>   } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
>   /* nothing to do */
>   } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
> - amdgpu_device_baco_enter(drm_dev);
> + ret = amdgpu_device_baco_enter(drm_dev);
> + if (ret)
> + dev_warn(>dev, "warning: device fails to enter 
> baco. ret=%d\n", ret);
>   }

If the intention is to print for any baco entry/exit failure, it's
better to put the print inside enter/exit functions itself. Also, since
these are triggered through PMFW, any PMFW fail will be printed. So this
may not be that useful.

Thanks,
Lijo

>  
>   dev_dbg(>dev, "asic/device is runtime suspended\n");
> @@ -2745,7 +2747,9 @@ static int amdgpu_pmops_runtime_resume(struct device 
> *dev)
>*/
>   pci_set_master(pdev);
>   } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
> - amdgpu_device_baco_exit(drm_dev);
> + ret = amdgpu_device_baco_exit(drm_dev);
> + if (ret)
> + dev_warn(>dev, "warning: device fails to exit 
> from baco. ret=%d\n", ret);
>   }
>   ret = amdgpu_device_resume(drm_dev, false);
>   if (ret) {

[PATCH 1/2] drm/amdgpu: Use rpm_mode flag instead of checking it again for rpm

[Ma Jun]

Because the rpm_mode flag is already set when the driver
is initialized, we use it directly for runtime suspend/resume
instead of checking it again

Signed-off-by: Ma Jun 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index af7fae7907d7..8b83c26dc018 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2666,7 +2666,7 @@ static int amdgpu_pmops_runtime_suspend(struct device 
*dev)
}
 
adev->in_runpm = true;
-   if (amdgpu_device_supports_px(drm_dev))
+   if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
/*
@@ -2676,7 +2676,7 @@ static int amdgpu_pmops_runtime_suspend(struct device 
*dev)
 * platforms.
 * TODO: this may be also needed for PX capable platform.
 */
-   if (amdgpu_device_supports_boco(drm_dev))
+   if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
adev->mp1_state = PP_MP1_STATE_UNLOAD;
 
ret = amdgpu_device_prepare(drm_dev);
@@ -2685,15 +2685,15 @@ static int amdgpu_pmops_runtime_suspend(struct device 
*dev)
ret = amdgpu_device_suspend(drm_dev, false);
if (ret) {
adev->in_runpm = false;
-   if (amdgpu_device_supports_boco(drm_dev))
+   if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
adev->mp1_state = PP_MP1_STATE_NONE;
return ret;
}
 
-   if (amdgpu_device_supports_boco(drm_dev))
+   if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
adev->mp1_state = PP_MP1_STATE_NONE;
 
-   if (amdgpu_device_supports_px(drm_dev)) {
+   if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
/* Only need to handle PCI state in the driver for ATPX
 * PCI core handles it for _PR3.
 */
@@ -2702,9 +2702,9 @@ static int amdgpu_pmops_runtime_suspend(struct device 
*dev)
pci_ignore_hotplug(pdev);
pci_set_power_state(pdev, PCI_D3cold);
drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
-   } else if (amdgpu_device_supports_boco(drm_dev)) {
+   } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
/* nothing to do */
-   } else if (amdgpu_device_supports_baco(drm_dev)) {
+   } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
amdgpu_device_baco_enter(drm_dev);
}
 
@@ -2727,7 +2727,7 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
if (!pci_device_is_present(adev->pdev))
adev->no_hw_access = true;
 
-   if (amdgpu_device_supports_px(drm_dev)) {
+   if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
/* Only need to handle PCI state in the driver for ATPX
@@ -2739,22 +2739,22 @@ static int amdgpu_pmops_runtime_resume(struct device 
*dev)
if (ret)
return ret;
pci_set_master(pdev);
-   } else if (amdgpu_device_supports_boco(drm_dev)) {
+   } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
/* Only need to handle PCI state in the driver for ATPX
 * PCI core handles it for _PR3.
 */
pci_set_master(pdev);
-   } else if (amdgpu_device_supports_baco(drm_dev)) {
+   } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
amdgpu_device_baco_exit(drm_dev);
}
ret = amdgpu_device_resume(drm_dev, false);
if (ret) {
-   if (amdgpu_device_supports_px(drm_dev))
+   if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
pci_disable_device(pdev);
return ret;
}
 
-   if (amdgpu_device_supports_px(drm_dev))
+   if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
adev->in_runpm = false;
return 0;
-- 
2.34.1

[PATCH 2/2] drm/amgpu: Check return value of amdgpu_device_baco_enter/exit

[Ma Jun]

Check return value of amdgpu_device_baco_enter/exit and print
warning message because these errors may cause runtime resume failure

Signed-off-by: Ma Jun 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8b83c26dc018..11e089cfb465 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2705,7 +2705,9 @@ static int amdgpu_pmops_runtime_suspend(struct device 
*dev)
} else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
/* nothing to do */
} else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
-   amdgpu_device_baco_enter(drm_dev);
+   ret = amdgpu_device_baco_enter(drm_dev);
+   if (ret)
+   dev_warn(>dev, "warning: device fails to enter 
baco. ret=%d\n", ret);
}
 
dev_dbg(>dev, "asic/device is runtime suspended\n");
@@ -2745,7 +2747,9 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
 */
pci_set_master(pdev);
} else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) {
-   amdgpu_device_baco_exit(drm_dev);
+   ret = amdgpu_device_baco_exit(drm_dev);
+   if (ret)
+   dev_warn(>dev, "warning: device fails to exit 
from baco. ret=%d\n", ret);
}
ret = amdgpu_device_resume(drm_dev, false);
if (ret) {
-- 
2.34.1

[PATCH] drm/amd/swsmu: modify the gfx activity scaling

[Li Ma]

Add an if condition for gfx activity because the scaling has been changed after 
smu fw version 5d4600.
And remove a warning log.

Signed-off-by: Li Ma 
---
 drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c   | 2 --
 drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 5 -
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 2aa7e9945a0b..7ac9bc0df8fd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -229,8 +229,6 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)
smu->smc_driver_if_version = 
SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
break;
case IP_VERSION(14, 0, 0):
-   if ((smu->smc_fw_version < 0x5d3a00))
-   dev_warn(smu->adev->dev, "The PMFW version(%x) is 
behind in this BIOS!\n", smu->smc_fw_version);
smu->smc_driver_if_version = 
SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
break;
default:
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 47fdbae4adfc..9310c4758e38 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -261,7 +261,10 @@ static int smu_v14_0_0_get_smu_metrics_data(struct 
smu_context *smu,
*value = metrics->MpipuclkFrequency;
break;
case METRICS_AVERAGE_GFXACTIVITY:
-   *value = metrics->GfxActivity / 100;
+   if ((smu->smc_fw_version > 0x5d4600))
+   *value = metrics->GfxActivity;
+   else
+   *value = metrics->GfxActivity / 100;
break;
case METRICS_AVERAGE_VCNACTIVITY:
*value = metrics->VcnActivity / 100;
-- 
2.25.1

Re: [PATCH V2] Revert "drm/amdgpu: remove vm sanity check from amdgpu_vm_make_compute" for Raven

[Christian König]

Hi Jesse,

Am 28.02.24 um 09:43 schrieb jesse.zh...@amd.com:

From: "Jesse.Zhang" 

fix the issue:
"amdgpu: Failed to create process VM object".

[Why]when amdgpu initialized, seq64 do mampping and update bo mapping in vm 
page table.
But when clifo run. It also initializes a vm for a process device through the 
function kfd_process_device_init_vm
and ensure the root PD is clean through the function amdgpu_vm_pt_is_root_clean.
So they have a conflict, and clinfo  always failed.

[HOW]
Skip the seq64 entry check in vm page table.

Signed-off-by: Jesse Zhang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 13 +
  1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index a160265ddc07..bdae5381887e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -746,8 +746,21 @@ bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev,
enum amdgpu_vm_level root = adev->vm_manager.root_level;
unsigned int entries = amdgpu_vm_pt_num_entries(adev, root);
unsigned int i = 0;
+   u64 seq64_addr = (adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT) - 
AMDGPU_VA_RESERVED_TOP;
+
+   seq64_addr /= AMDGPU_GPU_PAGE_SIZE;
+   mask = amdgpu_vm_pt_entries_mask(adev, adev->vm_manager.root_level);
+   shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level);
+   seq64_entry = (seq64_addr >> shift) & mask;
  
  	for (i = 0; i < entries; i++) {

+   /* seq64  reserve 2M memory from top of address space.
+* Then do the mapping and update the vm page table at amdgpu 
initialize.
+* So skip the know result.
+*/
+
+   if(i == seq64_entry)
+   continue;


Once more it is intentional that this fails!

Renoir shouldn't be using the ATS setting any more because that 
functionality was removed.


But it looks like the setting is somehow still active and because of 
this you run into this issue here.


Regards,
Christian.


if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo)
return false;
}

Re: [PATCH] drm/amdgpu: Fix multiple truncation issues in multiple driver files

[Lazar, Lijo]

On 2/27/2024 10:05 PM, Srinivasan Shanmugam wrote:
> Fixes snprintf function by writing more bytes into various buffers than
> they can hold.
> 
> In several files - smu_v13_0.c, gfx_v11_0.c, gfx_v10_0.c, gfx_v9_0.c,
> and amdgpu_mes.c. They were related to different directives, such as
> '%s', '_pfp.bin', '_me.bin', '_rlc.bin', '_mec.bin', '_mec2', and
> '_mes.bin'.
> 
> The buffers sizes have been adjusted to accommodate the maximum possible
> string size.
> 
> Fixes the below with gcc W=1:
> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.c:108:52: warning: 
> ‘%s’ directive output may be truncated writing up to 29 bytes into a region 
> of size 23 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:523:54: warning: ‘_pfp.bin’ directive 
> output may be truncated writing 8 bytes into a region of size between 4 and 
> 33 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:540:54: warning: ‘_me.bin’ directive 
> output may be truncated writing 7 bytes into a region of size between 4 and 
> 33 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:557:70: warning: ‘_rlc.bin’ directive 
> output may be truncated writing 8 bytes into a region of size between 4 and 
> 33 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:569:54: warning: ‘_mec.bin’ directive 
> output may be truncated writing 8 bytes into a region of size between 4 and 
> 33 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3979:58: warning: ‘%s’ directive 
> output may be truncated writing up to 4 bytes into a region of size between 0 
> and 29 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3985:57: warning: ‘%s’ directive 
> output may be truncated writing up to 4 bytes into a region of size between 1 
> and 30 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3991:57: warning: ‘%s’ directive 
> output may be truncated writing up to 4 bytes into a region of size between 1 
> and 30 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3998:62: warning: ‘_rlc.bin’ directive 
> output may be truncated writing 8 bytes into a region of size between 4 and 
> 33 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:4014:58: warning: ‘%s’ directive 
> output may be truncated writing up to 4 bytes into a region of size between 0 
> and 29 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:4021:54: warning: ‘_mec2’ directive 
> output may be truncated writing 5 bytes into a region of size between 4 and 
> 33 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1255:52: warning: ‘%s’ directive output 
> may be truncated writing up to 29 bytes into a region of size 23 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1261:52: warning: ‘%s’ directive output 
> may be truncated writing up to 29 bytes into a region of size 23 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1267:52: warning: ‘%s’ directive output 
> may be truncated writing up to 29 bytes into a region of size 23 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1303:60: warning: ‘%s’ directive output 
> may be truncated writing up to 29 bytes into a region of size 23 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1309:60: warning: ‘%s’ directive output 
> may be truncated writing up to 29 bytes into a region of size 23 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1311:60: warning: ‘%s’ directive output 
> may be truncated writing up to 29 bytes into a region of size 23 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1344:60: warning: ‘%s’ directive output 
> may be truncated writing up to 29 bytes into a region of size 23 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1346:60: warning: ‘%s’ directive output 
> may be truncated writing up to 29 bytes into a region of size 23 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1356:68: warning: ‘%s’ directive output 
> may be truncated writing up to 29 bytes into a region of size 23 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1358:68: warning: ‘%s’ directive output 
> may be truncated writing up to 29 bytes into a region of size 23 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c:1486:66: warning: ‘%s’ directive 
> output may be truncated writing up to 1 bytes into a region of size between 0 
> and 29 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c:1481:66: warning: ‘%s’ directive 
> output may be truncated writing 1 byte into a region of size between 0 and 29 
> [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c:1481:66: warning: ‘%s’ directive 
> output may be truncated writing 2 bytes into a region of size between 0 and 
> 29 [-Wformat-truncation=]
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c:1493:62: warning: ‘_mes.bin’ 
> directive output may be truncated writing 8 bytes into a region 

RE: [PATCH] drm/amd/pm: Fix esm reg mask use to get pcie speed

[Ma, Le]

[AMD Official Use Only - General]

Reviewed-by: Le Ma 

> -Original Message-
> From: Kamal, Asad 
> Sent: Wednesday, February 28, 2024 2:52 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Lazar, Lijo ; Zhang, Hawking
> ; Ma, Le ; Zhang, Morris
> ; Kamal, Asad 
> Subject: [PATCH] drm/amd/pm: Fix esm reg mask use to get pcie speed
>
> Fix mask used for esm ctrl register to get pcie link speed on smu_v11_0_3,
> smu_v13_0_2 & smu_v13_0_6
>
> Fixes: 511a95552ec8 ("drm/amd/pm: Add SMU 13.0.6 support")
> Fixes: c05d1c401572 ("drm/amd/swsmu: add aldebaran smu13 ip support (v3)")
> Fixes: f1c378593153 ("drm/amd/powerplay: add Arcturus support for gpu
> metrics export")
> Signed-off-by: Asad Kamal 
> Reviewed-by: Lijo Lazar 
> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c| 4 ++--
>  drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c   | 4 ++--
>  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 4 ++--
>  3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index bcad42534da4..1d96eb274d72 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -2272,8 +2272,8 @@ static uint16_t
> arcturus_get_current_pcie_link_speed(struct smu_context *smu)
>
>   /* TODO: confirm this on real target */
>   esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
> - if ((esm_ctrl >> 15) & 0x1)
> - return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128);
> + if ((esm_ctrl >> 15) & 0x1)
> + return (uint16_t)(((esm_ctrl >> 8) & 0x7F) + 128);
>
>   return smu_v11_0_get_current_pcie_link_speed(smu);
>  }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> index f122ef49106c..0467864a1aa8 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> @@ -1683,8 +1683,8 @@ static int
> aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
>
>   /* TODO: confirm this on real target */
>   esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
> - if ((esm_ctrl >> 15) & 0x1)
> - return (((esm_ctrl >> 8) & 0x3F) + 128);
> + if ((esm_ctrl >> 15) & 0x1)
> + return (((esm_ctrl >> 8) & 0x7F) + 128);
>
>   return smu_v13_0_get_current_pcie_link_speed(smu);
>  }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> index 69c64bc6e2dc..744c84f3029f 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> @@ -2148,8 +2148,8 @@ static int
> smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
>
>   /* TODO: confirm this on real target */
>   esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
> - if ((esm_ctrl >> 15) & 0x1)
> - return (((esm_ctrl >> 8) & 0x3F) + 128);
> + if ((esm_ctrl >> 15) & 0x1)
> + return (((esm_ctrl >> 8) & 0x7F) + 128);
>
>   speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
>   PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
> --
> 2.42.0

[PATCH] drm/amd/display: Fix potential index out of bounds in color transformation function

[Srinivasan Shanmugam]

Fixes index out of bounds issue in the color transformation function.
The issue could occur when the index 'i' exceeds the number of transfer
function points (TRANSFER_FUNC_POINTS).

The fix adds a check to ensure 'i' is within bounds before accessing the
transfer function points. If 'i' is out of bounds, an error message is
logged and the function returns false to indicate an error.

Reported by smatch:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_cm_common.c:405 
cm_helper_translate_curve_to_hw_format() error: buffer overflow 
'output_tf->tf_pts.red' 1025 <= s32max
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_cm_common.c:406 
cm_helper_translate_curve_to_hw_format() error: buffer overflow 
'output_tf->tf_pts.green' 1025 <= s32max
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_cm_common.c:407 
cm_helper_translate_curve_to_hw_format() error: buffer overflow 
'output_tf->tf_pts.blue' 1025 <= s32max

Fixes: b629596072e5 ("drm/amd/display: Build unity lut for shaper")
Cc: Vitaly Prosyak 
Cc: Charlene Liu 
Cc: Harry Wentland 
Cc: Rodrigo Siqueira 
Cc: Roman Li 
Cc: Aurabindo Pillai 
Cc: Tom Chung 
Signed-off-by: Srinivasan Shanmugam 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index b7e57aa27361..b0d192c6e63e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -402,6 +402,11 @@ bool cm_helper_translate_curve_to_hw_format(struct 
dc_context *ctx,
i += increment) {
if (j == hw_points - 1)
break;
+   if (i >= TRANSFER_FUNC_POINTS) {
+   DC_LOG_ERROR("Index out of bounds: i=%d, 
TRANSFER_FUNC_POINTS=%d\n",
+i, TRANSFER_FUNC_POINTS);
+   return false;
+   }
rgb_resulted[j].red = output_tf->tf_pts.red[i];
rgb_resulted[j].green = output_tf->tf_pts.green[i];
rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
-- 
2.34.1

[PATCH V2] Revert "drm/amdgpu: remove vm sanity check from amdgpu_vm_make_compute" for Raven

[jesse.zhang]

From: "Jesse.Zhang" 

fix the issue:
"amdgpu: Failed to create process VM object".

[Why]when amdgpu initialized, seq64 do mampping and update bo mapping in vm 
page table.
But when clifo run. It also initializes a vm for a process device through the 
function kfd_process_device_init_vm
and ensure the root PD is clean through the function amdgpu_vm_pt_is_root_clean.
So they have a conflict, and clinfo  always failed.

[HOW]
Skip the seq64 entry check in vm page table.

Signed-off-by: Jesse Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index a160265ddc07..bdae5381887e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -746,8 +746,21 @@ bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev,
enum amdgpu_vm_level root = adev->vm_manager.root_level;
unsigned int entries = amdgpu_vm_pt_num_entries(adev, root);
unsigned int i = 0;
+   u64 seq64_addr = (adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT) - 
AMDGPU_VA_RESERVED_TOP;
+
+   seq64_addr /= AMDGPU_GPU_PAGE_SIZE;
+   mask = amdgpu_vm_pt_entries_mask(adev, adev->vm_manager.root_level);
+   shift = amdgpu_vm_pt_level_shift(adev, adev->vm_manager.root_level);
+   seq64_entry = (seq64_addr >> shift) & mask;
 
for (i = 0; i < entries; i++) {
+   /* seq64  reserve 2M memory from top of address space.
+* Then do the mapping and update the vm page table at amdgpu 
initialize.
+* So skip the know result.
+*/
+
+   if(i == seq64_entry)
+   continue;
if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo)
return false;
}
-- 
2.34.1

Re: [PATCH 00/13] drm: Fix reservation locking for pin/unpin and console

[Thomas Zimmermann]

Hi

Am 27.02.24 um 19:14 schrieb Dmitry Osipenko:

Hello,

Thank you for the patches!

On 2/27/24 13:14, Thomas Zimmermann wrote:

Dma-buf locking semantics require the caller of pin and unpin to hold
the buffer's reservation lock. Fix DRM to adhere to the specs. This
enables to fix the locking in DRM's console emulation. Similar changes
for vmap and mmap have been posted at [1][2]

Most DRM drivers and memory managers acquire the buffer object's
reservation lock within their GEM pin and unpin callbacks. This
violates dma-buf locking semantics. We get away with it because PRIME
does not provide pin/unpin, but attach/detach, for which the locking
semantics is correct.

Patches 1 to 8 rework DRM GEM code in various implementations to
acquire the reservation lock when entering the pin and unpin callbacks.
This prepares them for the next patch. Drivers that are not affected
by these patches either don't acquire the reservation lock (amdgpu)
or don't need preparation (loongson).

Patch 9 moves reservation locking from the GEM pin/unpin callbacks
into drm_gem_pin() and drm_gem_unpin(). As PRIME uses these functions
internally it still gets the reservation lock.

With the updated GEM callbacks, the rest of the patchset fixes the
fbdev emulation's buffer locking. Fbdev emulation needs to keep its
GEM buffer object inplace while updating its content. This required
a implicit pinning and apparently amdgpu didn't do this at all.

Patch 10 introduces drm_client_buffer_vmap_local() and _vunmap_local().
The former function map a GEM buffer into the kernel's address space
with regular vmap operations, but keeps holding the reservation lock.
The _vunmap_local() helper undoes the vmap and releases the lock. The
updated GEM callbacks make this possible. Between the two calls, the
fbdev emulation can update the buffer content without have the buffer
moved or evicted. Update fbdev-generic to use vmap_local helpers,
which fix amdgpu. The idea of adding a "local vmap" has previously been
attempted at [3] in a different form.

Patch 11 adds implicit pinning to the DRM client's regular vmap
helper so that long-term vmap'ed buffers won't be evicted. This only
affects fbdev-dma, but GEM DMA helpers don't require pinning. So
there are no practical changes.

Patches 12 and 13 remove implicit pinning from the vmap and vunmap
operations in gem-vram and qxl. These pin operations are not supposed
to be part of vmap code, but were required to keep the buffers in place
for fbdev emulation. With the conversion o ffbdev-generic to to
vmap_local helpers, that code can finally be removed.

Isn't it a common behaviour for all DRM drivers to implicitly pin BO
while it's vmapped? I was sure it should be common /o\


That's what I originally thought as well, but the intention is for pin 
and vmap to be distinct operation. So far each driver has been 
different, as you probably know best from your vmap refactoring. :)




Why would you want to kmap BO that isn't pinned?


Pinning places the buffer object for the GPU. As a side effect, the 
buffer is then kept in place, which enables vmap. So pinning only makes 
sense for buffer objects that never move (shmem, dma). That's what patch 
11 is for.




Shouldn't TTM's vmap() be changed to do the pinning?


I don't think so. One problem is that pinning needs a memory area (vram, 
GTT, system ram, etc) specified, which vmap simply doesn't know about. 
That has been a problem for fbdev emulation at some point. Our fbdev 
code tried to pin as part of vmap, but chose the wrong area and suddenly 
the GPU could not see the buffer object any longer.  So the next best 
thing for vmap was to pin the buffer object where ever it is currently 
located. That is what gem-vram and qxl did so far. And of course, the 
fbdev code needs to unpin and vunmap the buffer object quickly, so that 
it can be relocated if the GPU needs it.  Hence, the vmap_local 
interface removes such short-term pinning in favor of holding the 
reservation lock.




I missed that TTM doesn't pin BO on vmap() and now surprised to see it.
It should be a rather serious problem requiring backporting of the
fixes, but I don't see the fixes tags on the patches (?)


No chance TBH. The old code has worked for years and backporting all 
this would require your vmap patches at a minimum.


Except maybe for amdgpu. It uses fbdev-generic, which requires pinning, 
but amdgpu doesn't pin. That looks fishy, but I'm not aware of any bug 
reports either. I guess, a quick workaround could fix older amdgpu if 
necessary.


Best regards
Thomas





--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)

Re: [PATCH 00/13] drm: Fix reservation locking for pin/unpin and console

[Dmitry Osipenko]

Hello,

Thank you for the patches!

On 2/27/24 13:14, Thomas Zimmermann wrote:
> Dma-buf locking semantics require the caller of pin and unpin to hold
> the buffer's reservation lock. Fix DRM to adhere to the specs. This
> enables to fix the locking in DRM's console emulation. Similar changes
> for vmap and mmap have been posted at [1][2]
> 
> Most DRM drivers and memory managers acquire the buffer object's
> reservation lock within their GEM pin and unpin callbacks. This
> violates dma-buf locking semantics. We get away with it because PRIME
> does not provide pin/unpin, but attach/detach, for which the locking
> semantics is correct.
> 
> Patches 1 to 8 rework DRM GEM code in various implementations to
> acquire the reservation lock when entering the pin and unpin callbacks.
> This prepares them for the next patch. Drivers that are not affected
> by these patches either don't acquire the reservation lock (amdgpu)
> or don't need preparation (loongson).
> 
> Patch 9 moves reservation locking from the GEM pin/unpin callbacks
> into drm_gem_pin() and drm_gem_unpin(). As PRIME uses these functions
> internally it still gets the reservation lock.
> 
> With the updated GEM callbacks, the rest of the patchset fixes the
> fbdev emulation's buffer locking. Fbdev emulation needs to keep its
> GEM buffer object inplace while updating its content. This required
> a implicit pinning and apparently amdgpu didn't do this at all.
> 
> Patch 10 introduces drm_client_buffer_vmap_local() and _vunmap_local().
> The former function map a GEM buffer into the kernel's address space
> with regular vmap operations, but keeps holding the reservation lock.
> The _vunmap_local() helper undoes the vmap and releases the lock. The
> updated GEM callbacks make this possible. Between the two calls, the
> fbdev emulation can update the buffer content without have the buffer
> moved or evicted. Update fbdev-generic to use vmap_local helpers,
> which fix amdgpu. The idea of adding a "local vmap" has previously been
> attempted at [3] in a different form.
> 
> Patch 11 adds implicit pinning to the DRM client's regular vmap
> helper so that long-term vmap'ed buffers won't be evicted. This only
> affects fbdev-dma, but GEM DMA helpers don't require pinning. So
> there are no practical changes.
> 
> Patches 12 and 13 remove implicit pinning from the vmap and vunmap
> operations in gem-vram and qxl. These pin operations are not supposed
> to be part of vmap code, but were required to keep the buffers in place
> for fbdev emulation. With the conversion o ffbdev-generic to to
> vmap_local helpers, that code can finally be removed.

Isn't it a common behaviour for all DRM drivers to implicitly pin BO
while it's vmapped? I was sure it should be common /o\

Why would you want to kmap BO that isn't pinned?

Shouldn't TTM's vmap() be changed to do the pinning?

I missed that TTM doesn't pin BO on vmap() and now surprised to see it.
It should be a rather serious problem requiring backporting of the
fixes, but I don't see the fixes tags on the patches (?)

-- 
Best regards,
Dmitry

amdgpu kmemleaks

[Borislav Petkov]

Hi folks,

anyone interested in a bunch of amdgpu kmemleak reports from latest Linus tree
+ tip?

GPU is:

[   11.317312] [drm] amdgpu kernel modesetting enabled.
[   11.363627] [drm] initializing kernel modesetting (CARRIZO 0x1002:0x9874 
0x103C:0x807E 0xC4).
[   11.364077] [drm] register mmio base: 0xD0C0
[   11.364547] [drm] register mmio size: 262144
[   11.365347] [drm] add ip block number 0 
[   11.365580] [drm] add ip block number 1 
[   11.365840] [drm] add ip block number 2 
[   11.366047] [drm] add ip block number 3 
[   11.366263] [drm] add ip block number 4 
[   11.366470] [drm] add ip block number 5 
[   11.32] [drm] add ip block number 6 
[   11.366835] [drm] add ip block number 7 
[   11.367022] [drm] add ip block number 8 
[   11.382774] [drm] BIOS signature incorrect 5b 7
[   11.383002] resource: resource sanity check: requesting [mem 
0x000c-0x000d], which spans more than PCI Bus :00 
[mem 0x000c-0x000cbfff window]
[   11.383655] caller pci_map_rom+0x68/0x1d0 mapping multiple BARs
[   11.384009] amdgpu :00:01.0: amdgpu: Fetched VBIOS from ROM BAR
[   11.384402] amdgpu: ATOM BIOS: SWBRT27354.001
[   11.385827] [drm] UVD is enabled in physical mode
[   11.386063] [drm] VCE enabled in physical mode
[   11.386886] amdgpu :00:01.0: vgaarb: deactivate vga console
[   11.389089] Console: switching to colour dummy device 80x25
[   11.389543] amdgpu :00:01.0: amdgpu: Trusted Memory Zone (TMZ) feature 
not supported
[   11.390482] [drm] vm size is 64 GB, 2 levels, block size is 10-bit, fragment 
size is 9-bit
[   11.390793] amdgpu :00:01.0: amdgpu: VRAM: 512M 0x00F4 - 
0x00F41FFF (512M used)
[   11.391129] amdgpu :00:01.0: amdgpu: GART: 1024M 0x00FF - 
0x00FF3FFF
[   11.391456] [drm] Detected VRAM RAM=512M, BAR=512M
[   11.391632] [drm] RAM width 128bits UNKNOWN
[   11.394546] [drm] amdgpu: 512M of VRAM memory ready
[   11.394751] [drm] amdgpu: 7622M of GTT memory ready.
[   11.395299] [drm] GART: num cpu pages 262144, num gpu pages 262144
[   11.395813] [drm] PCIE GART of 1024M enabled (table at 0x00F400A0).
[   11.404914] amdgpu: hwmgr_sw_init smu backed is smu8_smu
[   11.407177] [drm] Found UVD firmware Version: 1.91 Family ID: 11
[   11.407670] [drm] UVD ENC is disabled
[   11.409969] [drm] Found VCE firmware Version: 52.4 Binary ID: 3
[   11.412601] amdgpu: smu version 18.62.00
[   11.419275] [drm] DM_PPLIB: values for Engine clock
[   11.419480] [drm] DM_PPLIB:   30
[   11.419610] [drm] DM_PPLIB:   36
[   11.419740] [drm] DM_PPLIB:   423530
[   11.419869] [drm] DM_PPLIB:   514290
[   11.419998] [drm] DM_PPLIB:   626090
[   11.420127] [drm] DM_PPLIB:   72
[   11.420327] [drm] DM_PPLIB: Validation clocks:
[   11.420536] [drm] DM_PPLIB:engine_max_clock: 72000
[   11.420722] [drm] DM_PPLIB:memory_max_clock: 8
[   11.420907] [drm] DM_PPLIB:level   : 8
[   11.421083] [drm] DM_PPLIB: values for Display clock
[   11.421266] [drm] DM_PPLIB:   30
[   11.421395] [drm] DM_PPLIB:   40
[   11.421524] [drm] DM_PPLIB:   496560
[   11.421652] [drm] DM_PPLIB:   626090
[   11.421781] [drm] DM_PPLIB:   685720
[   11.421910] [drm] DM_PPLIB:   757900
[   11.422039] [drm] DM_PPLIB: Validation clocks:
[   11.422201] [drm] DM_PPLIB:engine_max_clock: 72000
[   11.422386] [drm] DM_PPLIB:memory_max_clock: 8
[   11.422572] [drm] DM_PPLIB:level   : 8
[   11.422746] [drm] DM_PPLIB: values for Memory clock
[   11.422923] [drm] DM_PPLIB:   333000
[   11.423052] [drm] DM_PPLIB:   80
[   11.423181] [drm] DM_PPLIB: Validation clocks:
[   11.423342] [drm] DM_PPLIB:engine_max_clock: 72000
[   11.423528] [drm] DM_PPLIB:memory_max_clock: 8
[   11.423713] [drm] DM_PPLIB:level   : 8
[   11.424561] [drm] Display Core v3.2.266 initialized on DCE 11.0
[   11.516117] [drm] UVD initialized successfully.
[   11.716119] [drm] VCE initialized successfully.


unreferenced object 0x88810e6faa80 (size 128):
  comm "systemd-udevd", pid 1219, jiffies 4294895080
  hex dump (first 32 bytes):
18 cb 03 00 00 0a 28 0a 48 0a c8 0a 00 00 a0 05  ..(.H...
aa 05 b4 05 dc 05 00 00 0a 00 00 00 00 00 00 00  
  backtrace (crc 5201319b):
[<6e1e4989>] kmalloc_trace+0x25a/0x300
[<7b61fcfc>] do_detailed_mode+0x323/0x670
[<79955120>] drm_for_each_detailed_block.part.0+0x34/0x180
[<9a087c6a>] _drm_edid_connector_add_modes.part.0+0x8f/0x10b0
[] drm_add_edid_modes+0x14e/0x160
[<0a49b747>] amdgpu_dm_connector_get_modes+0x13b/0x470 [amdgpu]
[<5f5da5a5>] amdgpu_dm_init.isra.0+0x12ed/0x1e50 [amdgpu]
[] dm_hw_init+0xe/0x20 [amdgpu]
[] amdgpu_device_init+0x1f17/0x2530 [amdgpu]
[<9c22ce56>] amdgpu_driver_load_kms+0x23/0x1a0 [amdgpu]
[<8bc75f74>] amdgpu_pci_probe+0x1b5/0x550 

[PATCH] drm/amdgpu: Fix assignment errors in 'si_common_early_init' functions

[Lu Yao]

uvd_ctx_rreg/uvd_ctx_wreg correct value requires function pointer.

Signed-off-by: Lu Yao 
---
 drivers/gpu/drm/amd/amdgpu/si.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index a757526153e5..455d49f7bd9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -2032,8 +2032,8 @@ static int si_common_early_init(void *handle)
adev->pcie_wreg = _pcie_wreg;
adev->pciep_rreg = _pciep_rreg;
adev->pciep_wreg = _pciep_wreg;
-   adev->uvd_ctx_rreg = si_uvd_ctx_rreg;
-   adev->uvd_ctx_wreg = si_uvd_ctx_wreg;
+   adev->uvd_ctx_rreg = _uvd_ctx_rreg;
+   adev->uvd_ctx_wreg = _uvd_ctx_wreg;
adev->didt_rreg = NULL;
adev->didt_wreg = NULL;
 
-- 
2.25.1