[PATCH] drm/amdgpu: init microcode chip name from ip versions

2024-04-21 Thread Le Ma 
To adapt to different gc versions in gfx_v9_4_3.c file.

Change-Id: Ib4465aade0dcbbcc43318c6dc865f813c5411097
Signed-off-by: Le Ma 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 835004187a58..ec4d3fa87e4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -431,16 +431,16 @@ static int gfx_v9_4_3_init_cp_compute_microcode(struct 
amdgpu_device *adev,
 
 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev)
 {
-   const char *chip_name;
+   char ucode_prefix[30];
int r;
 
-   chip_name = "gc_9_4_3";
+   amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, 
sizeof(ucode_prefix));
 
-   r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name);
+   r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix);
if (r)
return r;
 
-   r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name);
+   r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix);
if (r)
return r;
 
-- 
2.43.2

Re: [PATCH] drm/amdgpu: Update CGCG settings for GFXIP 9.4.3

2024-04-21 Thread Lazar, Lijo 



On 4/22/2024 6:42 AM, Rajneesh Bhardwaj wrote:
> Tune coarse grain clock gating idle threshold and rlc idle timeout to
> achieve better kernel launch latency.
> 
> Signed-off-by: Rajneesh Bhardwaj 

Reviewed-by: Lijo Lazar 

Thanks,
Lijo

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index 835004187a58..813528fb4f2a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -2404,10 +2404,10 @@ 
> gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
>   if (def != data)
>   WREG32_SOC15(GC, GET_INST(GC, xcc_id), 
> regRLC_CGTT_MGCG_OVERRIDE, data);
>  
> - /* enable cgcg FSM(0x363F) */
> + /* CGCG Hysteresis: 400us */
>   def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 
> regRLC_CGCG_CGLS_CTRL);
>  
> - data = (0x36
> + data = (0x2710
>   << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>  RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
>   if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
> @@ -2416,10 +2416,10 @@ 
> gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
>   if (def != data)
>   WREG32_SOC15(GC, GET_INST(GC, xcc_id), 
> regRLC_CGCG_CGLS_CTRL, data);
>  
> - /* set IDLE_POLL_COUNT(0x00900100) */
> + /* set IDLE_POLL_COUNT(0x33450100)*/
>   def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 
> regCP_RB_WPTR_POLL_CNTL);
>   data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
> - (0x0090 << 
> CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
> + (0x3345 << 
> CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
>   if (def != data)
>   WREG32_SOC15(GC, GET_INST(GC, xcc_id), 
> regCP_RB_WPTR_POLL_CNTL, data);
>   } else {

RE: [PATCH 15/15] drm/amdgpu: Use new interface to reserve bad page

2024-04-21 Thread Chai, Thomas 
[AMD Official Use Only - General]

Ping 


-
Best Regards,
Thomas

-Original Message-
From: Chai, Thomas 
Sent: Thursday, April 18, 2024 10:59 AM
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ; 
Zhou1, Tao ; Li, Candice ; Wang, 
Yang(Kevin) ; Yang, Stanley ; 
Chai, Thomas 
Subject: [PATCH 15/15] drm/amdgpu: Use new interface to reserve bad page

Use new interface to reserve bad page.

Signed-off-by: YiPeng Chai 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index d1a2ab944b7d..dee66db10fa2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2548,9 +2548,7 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
goto out;
}

-   amdgpu_vram_mgr_reserve_range(>mman.vram_mgr,
-   bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
-   AMDGPU_GPU_PAGE_SIZE);
+   amdgpu_ras_reserve_page(adev, bps[i].retired_page);

memcpy(>bps[data->count], [i], sizeof(*data->bps));
data->count++;
--
2.34.1

[PATCH] drm/amdgpu: Update CGCG settings for GFXIP 9.4.3

2024-04-21 Thread Rajneesh Bhardwaj 
Tune coarse grain clock gating idle threshold and rlc idle timeout to
achieve better kernel launch latency.

Signed-off-by: Rajneesh Bhardwaj 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 835004187a58..813528fb4f2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2404,10 +2404,10 @@ gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct 
amdgpu_device *adev,
if (def != data)
WREG32_SOC15(GC, GET_INST(GC, xcc_id), 
regRLC_CGTT_MGCG_OVERRIDE, data);
 
-   /* enable cgcg FSM(0x363F) */
+   /* CGCG Hysteresis: 400us */
def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 
regRLC_CGCG_CGLS_CTRL);
 
-   data = (0x36
+   data = (0x2710
<< RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
   RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
@@ -2416,10 +2416,10 @@ gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct 
amdgpu_device *adev,
if (def != data)
WREG32_SOC15(GC, GET_INST(GC, xcc_id), 
regRLC_CGCG_CGLS_CTRL, data);
 
-   /* set IDLE_POLL_COUNT(0x00900100) */
+   /* set IDLE_POLL_COUNT(0x33450100)*/
def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 
regCP_RB_WPTR_POLL_CNTL);
data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
-   (0x0090 << 
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
+   (0x3345 << 
CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
if (def != data)
WREG32_SOC15(GC, GET_INST(GC, xcc_id), 
regCP_RB_WPTR_POLL_CNTL, data);
} else {
-- 
2.34.1