Re: [PATCH] gpu: drm: radeon: Set DPM_FLAG_NEVER_SKIP when enabling PM-runtime
On Sat, Feb 16, 2019 at 1:01 AM Lukas Wunner wrote:
>
> On Fri, Feb 15, 2019 at 11:01:04AM -0500, Alex Deucher wrote:
> > On Fri, Feb 15, 2019 at 10:39 AM Rafael J. Wysocki
> > wrote:
> > > On HP ProBook 4540s, if PM-runtime is enabled in the radeon driver
> > > and the direct-complete optimization is used for the radeon device
> > > during system-wide suspend, the system doesn't resume.
> > >
> > > Preventing direct-complete from being used with the radeon device by
> > > setting the DPM_FLAG_NEVER_SKIP driver flag for it makes the problem
> > > go away, which indicates that direct-complete is not safe for the
> > > radeon driver in general and should not be used with it (at least
> > > for now).
> > >
> > > This fixes a regression introduced by commit c62ec4610c40
> > > ("PM / core: Fix direct_complete handling for devices with no
> > > callbacks") which allowed direct-complete to be applied to
> > > devices without PM callbacks (again) which in turn unlocked
> > > direct-complete for radeon on HP ProBook 4540s.
> >
> > Do other similar drivers like amdgpu and nouveau need the same fix?
> > I'm not too familiar with the direct_complete feature in general.
>
> direct_complete means that a discrete GPU which is in D3cold upon
> entering system sleep is left as is, i.e. it is not woken. It is
> also expected to still be in D3cold when resuming from system sleep
> from the PM core's point of view. (If it is in D0uninitialized, the
> GPU's driver needs to ensure it is transitioned to D3cold again.)
>
> I know for a fact that resuming the discrete GPU is not necessary
> on my MacBook Pro with Nvidia GPU. I'd expect those with AMD GPUs
> to behave the same. The apple-gmux driver takes care of putting
> the GPU into D3cold on resume from system sleep if it was in D3cold
> when entering system sleep (see drivers/platform/x86/apple-gmux.c,
> gmux_resume()).
>
> I think it is desirable to use direct_complete because it saves power
> (no need to gratuitously wake the GPU upon entering system sleep,
> only to immediately cut its power) and it also speeds up the suspend
> process by about half a second.
Thanks for the info. It sounds like we need a similar patch for
amdgpu. With dGPUs controlled by the ACPI ATPX method, I believe the
dGPU is powered by automatically on resume from S3/S4. I think there
may be a way to change that behavior in some revisions of ATPX (i.e.,
to keep the state across suspend cycles), but it's not the default.
I'm not sure about the newer _PR3 stuff in Hybrid Graphics laptops. I
think it retains state. In both radeon and amdgpu we probably need to
check if the system is using ATPX or _PR3 and disable direct complete
for ATPX at least.
Alex
>
> The root cause on the HP ProBook 4540s needs to be debugged, I'd
> suspect a BIOS issue which could be adressed by a quirk, either for
> this particular machine or for a certain class of devices (e.g. all
> machines which use PR3 to transition to D3cold) if that is necessary
> to behave identically to Windows. Or maybe the atpx vga_switcheroo
> handler needs to be amended to put the GPU into D3cold on resume from
> system sleep if it was runtime suspended before.
>
> Is this machine using s2idle or does it suspend to S3?
>
> Thanks,
>
> Lukas
>
> > > Fixes: c62ec4610c40 ("PM / core: Fix direct_complete handling for devices
> > > with no callbacks")
> > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=201519
> > > Reported-by: ??
> > > Tested-by: ??
> > > Signed-off-by: Rafael J. Wysocki
> > > ---
> > > drivers/gpu/drm/radeon/radeon_kms.c |1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > Index: linux-pm/drivers/gpu/drm/radeon/radeon_kms.c
> > > ===
> > > --- linux-pm.orig/drivers/gpu/drm/radeon/radeon_kms.c
> > > +++ linux-pm/drivers/gpu/drm/radeon/radeon_kms.c
> > > @@ -172,6 +172,7 @@ int radeon_driver_load_kms(struct drm_de
> > > }
> > >
> > > if (radeon_is_px(dev)) {
> > > + dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
> > > pm_runtime_use_autosuspend(dev->dev);
> > > pm_runtime_set_autosuspend_delay(dev->dev, 5000);
> > > pm_runtime_set_active(dev->dev);
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 6/6] drm/amdgpu: use BACO on vega12 if platform supports it
Use BACO for reset of the platform supports it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 99ebcf29dcb0..b2cbe4b42a3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -461,6 +461,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_VEGA10:
+ case CHIP_VEGA12:
case CHIP_VEGA20:
soc15_asic_get_baco_capability(adev, _reset);
break;
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/6] drm/amdgpu/powerplay: fix typo in BACO header guards
s/BOCO/BACO/g Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h | 4 ++-- drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h index a93b1e6d1c66..f7a3ffa744b3 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h @@ -20,8 +20,8 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#ifndef __VEGA10_BOCO_H__ -#define __VEGA10_BOCO_H__ +#ifndef __VEGA10_BACO_H__ +#define __VEGA10_BACO_H__ #include "hwmgr.h" #include "common_baco.h" diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h index c51988a9ed77..51c7f8392925 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h @@ -20,8 +20,8 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#ifndef __VEGA20_BOCO_H__ -#define __VEGA20_BOCO_H__ +#ifndef __VEGA20_BACO_H__ +#define __VEGA20_BACO_H__ #include "hwmgr.h" #include "common_baco.h" -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 5/6] drm/amdgpu/powerplay: split out common smu9 BACO code
Several of the BACO functions are common across smu9-based
asics. Split the common code out.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
.../gpu/drm/amd/powerplay/hwmgr/smu9_baco.c | 66 +++
.../gpu/drm/amd/powerplay/hwmgr/smu9_baco.h | 31 +
.../gpu/drm/amd/powerplay/hwmgr/vega10_baco.c | 39 +--
.../gpu/drm/amd/powerplay/hwmgr/vega10_baco.h | 5 +-
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 4 +-
.../gpu/drm/amd/powerplay/hwmgr/vega12_baco.c | 39 +--
.../gpu/drm/amd/powerplay/hwmgr/vega12_baco.h | 5 +-
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 4 +-
9 files changed, 106 insertions(+), 89 deletions(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.h
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index d1adf68f4c64..cc63705920dc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
pp_overdriver.o smu_helper.o \
vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \
- vega12_baco.o
+ vega12_baco.o smu9_baco.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c
new file mode 100644
index ..de0a37f7c632
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "soc15.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
+#include "soc15_common.h"
+#include "vega10_inc.h"
+#include "smu9_baco.h"
+
+int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+ uint32_t reg, data;
+
+ *cap = false;
+ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_BACO))
+ return 0;
+
+ WREG32(0x12074, 0xFFF0003B);
+ data = RREG32(0x12075);
+
+ if (data == 0x1) {
+ reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
+
+ if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
+ *cap = true;
+ }
+
+ return 0;
+}
+
+int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+ uint32_t reg;
+
+ reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
+
+ if (reg & BACO_CNTL__BACO_MODE_MASK)
+ /* gfx has already entered BACO state */
+ *state = BACO_STATE_IN;
+ else
+ *state = BACO_STATE_OUT;
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.h
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.h
new file mode 100644
index ..84e90f801ac3
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
[PATCH 4/6] drm/amdgpu/powerplay: add BACO support for vega12
This implements BACO (Bus Active, Chip Off) support
for vega12.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 3 +-
.../gpu/drm/amd/powerplay/hwmgr/vega12_baco.c | 156 ++
.../gpu/drm/amd/powerplay/hwmgr/vega12_baco.h | 32
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 5 +
.../gpu/drm/amd/powerplay/hwmgr/vega12_inc.h | 2 +
5 files changed, 197 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.h
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 0b3c6d1d52e4..d1adf68f4c64 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -35,7 +35,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
vega12_thermal.o \
pp_overdriver.o smu_helper.o \
vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
- vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o
+ vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \
+ vega12_baco.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c
new file mode 100644
index ..c2cc15385012
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "soc15.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
+#include "soc15_common.h"
+#include "vega12_inc.h"
+#include "vega12_ppsmc.h"
+#include "vega12_baco.h"
+
+static const struct soc15_baco_cmd_entry pre_baco_tbl[] =
+{
+ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmBIF_DOORBELL_CNTL_BASE_IDX,
mmBIF_DOORBELL_CNTL, BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK,
BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT, 0, 0 },
+ { CMD_WRITE, NBIF_HWID, 0, mmBIF_FB_EN_BASE_IDX, mmBIF_FB_EN, 0, 0, 0,
0 },
+ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX,
mmBACO_CNTL, BACO_CNTL__BACO_DSTATE_BYPASS_MASK,
BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT, 0, 1 },
+ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX,
mmBACO_CNTL, BACO_CNTL__BACO_RST_INTR_MASK_MASK,
BACO_CNTL__BACO_RST_INTR_MASK__SHIFT, 0, 1 }
+};
+
+static const struct soc15_baco_cmd_entry enter_baco_tbl[] =
+{
+ { CMD_WAITFOR, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX, mmTHM_BACO_CNTL,
THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK, THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT,
0x, 0x8000 },
+ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX,
mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 1 },
+ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX,
mmBACO_CNTL, BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK,
BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT, 0, 1 },
+ { CMD_READMODIFYWRITE, NBIF_HWID, 0, mmRCC_BACO_CNTL_MISC_BASE_IDX,
mmBACO_CNTL, BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_CNTL__BACO_DUMMY_EN__SHIFT, 0,
1 },
+ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX,
mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK,
THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 1 },
+ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX,
mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK,
THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT, 0, 1 },
+ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX,
mmTHM_BACO_CNTL, THM_BACO_CNTL__BACO_ISO_EN_MASK,
THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 1 },
+ { CMD_READMODIFYWRITE, THM_HWID, 0, mmTHM_BACO_CNTL_BASE_IDX,
mmTHM_BACO_CNTL,
[PATCH 1/6] drm/amdgpu: add missing license on baco files
Trivial. Signed-off-by: Alex Deucher --- .../gpu/drm/amd/powerplay/hwmgr/vega10_baco.c | 22 +++ .../gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 22 +++ 2 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c index f94dab27f486..d5232110ec84 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c @@ -1,3 +1,25 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ #include "amdgpu.h" #include "soc15.h" #include "soc15_hw_ip.h" diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c index 0d883b358df2..edf00da8424b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c @@ -1,3 +1,25 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ #include "amdgpu.h" #include "soc15.h" #include "soc15_hw_ip.h" -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/6] drm/amdgpu/powerplay: fix return codes in BACO code
Use a proper return code rather than -1.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c | 4 ++--
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c
index d5232110ec84..7337be5602e4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c
@@ -136,7 +136,7 @@ int vega10_baco_set_state(struct pp_hwmgr *hwmgr, enum
BACO_STATE state)
if (soc15_baco_program_registers(hwmgr, pre_baco_tbl,
ARRAY_SIZE(pre_baco_tbl))) {
if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnterBaco))
- return -1;
+ return -EINVAL;
if (soc15_baco_program_registers(hwmgr, enter_baco_tbl,
ARRAY_SIZE(enter_baco_tbl)))
@@ -154,5 +154,5 @@ int vega10_baco_set_state(struct pp_hwmgr *hwmgr, enum
BACO_STATE state)
}
}
- return -1;
+ return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
index edf00da8424b..5e8602a79b1c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
@@ -89,14 +89,14 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum
BACO_STATE state)
if(smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnterBaco, 0))
- return -1;
+ return -EINVAL;
} else if (state == BACO_STATE_OUT) {
if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco))
- return -1;
+ return -EINVAL;
if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
ARRAY_SIZE(clean_baco_tbl)))
- return -1;
+ return -EINVAL;
}
return 0;
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm: Mark expected switch fall-throughs
On Fri, Feb 15, 2019 at 11:08 AM Gustavo A. R. Silva wrote: > > In preparation to enabling -Wimplicit-fallthrough, mark switch > cases where we are expecting to fall through. > > Warning level 3 was used: -Wimplicit-fallthrough=3 > > Notice that, in some cases, the code comment is modified > in accordance with what GCC is expecting to find. > > This patch is part of the ongoing efforts to enable > -Wimplicit-fallthrough. > > Signed-off-by: Gustavo A. R. Silva Can you please split this up per driver? A comment below as well. > --- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 + > drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 ++ > drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 ++ > drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 2 +- > drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c| 2 ++ > drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 1 + > drivers/gpu/drm/drm_vm.c| 4 ++-- > drivers/gpu/drm/nouveau/nouveau_bo.c| 2 +- > drivers/gpu/drm/radeon/ci_dpm.c | 2 ++ > drivers/gpu/drm/radeon/evergreen_cs.c | 1 + > drivers/gpu/drm/radeon/si_dpm.c | 2 ++ > 11 files changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index b8e50a34bdb3..02955e6e9dd9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -3236,6 +3236,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct > amdgpu_device *adev) > dev_warn(adev->dev, > "Unknown chip type (%d) in function > gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n", > adev->asic_type); > + /* fall through */ > > case CHIP_CARRIZO: > modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c > b/drivers/gpu/drm/amd/amdgpu/si_dpm.c > index da58040fdbdc..41e01a7f57a4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c > +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c > @@ -6216,10 +6216,12 @@ static void > si_request_link_speed_change_before_state_change(struct amdgpu_devic > si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2; > if (current_link_speed == AMDGPU_PCIE_GEN2) > break; > + /* fall through */ > case AMDGPU_PCIE_GEN2: > if (amdgpu_acpi_pcie_performance_request(adev, > PCIE_PERF_REQ_PECI_GEN2, false) == 0) > break; > #endif > + /* fall through */ > default: > si_pi->force_pcie_gen = > si_get_current_pcie_speed(adev); > break; > diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c > b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c > index a1c56f29cfeb..fd5266a58297 100644 > --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c > +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c > @@ -265,6 +265,7 @@ static struct atom_display_object_path_v2 > *get_bios_object( > && id.enum_id == obj_id.enum_id) > return > >object_info_tbl.v1_4->display_path[i]; > } > + /* fall through */ > case OBJECT_TYPE_CONNECTOR: > case OBJECT_TYPE_GENERIC: > /* Both Generic and Connector Object ID > @@ -277,6 +278,7 @@ static struct atom_display_object_path_v2 > *get_bios_object( > && id.enum_id == obj_id.enum_id) > return > >object_info_tbl.v1_4->display_path[i]; > } > + /* fall through */ > default: > return NULL; > } > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c > b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c > index 85686d917636..a24a2bda8656 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c > @@ -479,7 +479,7 @@ static void program_grph_pixel_format( > case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: > sign = 1; > floating = 1; > - /* no break */ > + /* fall through */ > case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: /* shouldn't this get > float too? */ > case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: > grph_depth = 3; > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > index c8f5c00dd1e7..48187acac59e 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c > +++
Re: [PATCH] gpu: drm: radeon: Set DPM_FLAG_NEVER_SKIP when enabling PM-runtime
On Fri, Feb 15, 2019 at 10:39 AM Rafael J. Wysocki wrote:
>
> From: Rafael J. Wysocki
>
> On HP ProBook 4540s, if PM-runtime is enabled in the radeon driver
> and the direct-complete optimization is used for the radeon device
> during system-wide suspend, the system doesn't resume.
>
> Preventing direct-complete from being used with the radeon device by
> setting the DPM_FLAG_NEVER_SKIP driver flag for it makes the problem
> go away, which indicates that direct-complete is not safe for the
> radeon driver in general and should not be used with it (at least
> for now).
>
> This fixes a regression introduced by commit c62ec4610c40
> ("PM / core: Fix direct_complete handling for devices with no
> callbacks") which allowed direct-complete to be applied to
> devices without PM callbacks (again) which in turn unlocked
> direct-complete for radeon on HP ProBook 4540s.
Do other similar drivers like amdgpu and nouveau need the same fix?
I'm not too familiar with the direct_complete feature in general.
Alex
>
> Fixes: c62ec4610c40 ("PM / core: Fix direct_complete handling for devices
> with no callbacks")
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=201519
> Reported-by: Ярослав Семченко
> Tested-by: Ярослав Семченко
> Signed-off-by: Rafael J. Wysocki
> ---
> drivers/gpu/drm/radeon/radeon_kms.c |1 +
> 1 file changed, 1 insertion(+)
>
> Index: linux-pm/drivers/gpu/drm/radeon/radeon_kms.c
> ===
> --- linux-pm.orig/drivers/gpu/drm/radeon/radeon_kms.c
> +++ linux-pm/drivers/gpu/drm/radeon/radeon_kms.c
> @@ -172,6 +172,7 @@ int radeon_driver_load_kms(struct drm_de
> }
>
> if (radeon_is_px(dev)) {
> + dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
> pm_runtime_use_autosuspend(dev->dev);
> pm_runtime_set_autosuspend_delay(dev->dev, 5000);
> pm_runtime_set_active(dev->dev);
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH libdrm] libdrm: Fix issue about differrent domainID but same BDF
Adding dri-devel.
On Thu, Feb 14, 2019 at 2:53 AM Emily Deng wrote:
>
> For multiple GPUs which has the same BDF, but has different domain ID,
> the drmOpenByBusid will return the wrong fd when startx.
>
> The reproduce sequence as below:
> 1. Call drmOpenByBusid to open Card0, then will return the right fd0, and the
> fd0 is master privilege;
> 2. Call drmOpenByBusid to open Card1. In function drmOpenByBusid, it will
> open Card0 first, this time, the fd1 for opening Card0 is not master
> privilege, and will call drmSetInterfaceVersion to identify the
> domain ID feature, as the fd1 is not master privilege, then
> drmSetInterfaceVersion
> will fail, and then won't compare domain ID, then return the wrong fd for
> Card1.
>
> Solution:
> First loop search the best match fd about drm 1.4.
>
> Signed-off-by: Emily Deng
> ---
> xf86drm.c | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/xf86drm.c b/xf86drm.c
> index 336d64d..b60e029 100644
> --- a/xf86drm.c
> +++ b/xf86drm.c
> @@ -584,11 +584,34 @@ static int drmOpenByBusid(const char *busid, int type)
> if (base < 0)
> return -1;
>
> +/* We need to try for 1.4 first for proper PCI domain support */
> drmMsg("drmOpenByBusid: Searching for BusID %s\n", busid);
> for (i = base; i < base + DRM_MAX_MINOR; i++) {
> fd = drmOpenMinor(i, 1, type);
> drmMsg("drmOpenByBusid: drmOpenMinor returns %d\n", fd);
> if (fd >= 0) {
> +sv.drm_di_major = 1;
> +sv.drm_di_minor = 4;
> +sv.drm_dd_major = -1;/* Don't care */
> +sv.drm_dd_minor = -1;/* Don't care */
> +if (!drmSetInterfaceVersion(fd, )) {
> +buf = drmGetBusid(fd);
> +drmMsg("drmOpenByBusid: drmGetBusid reports %s\n", buf);
> +if (buf && drmMatchBusID(buf, busid, 1)) {
> +drmFreeBusid(buf);
> +return fd;
> +}
> +if (buf)
> +drmFreeBusid(buf);
> +}
> +close(fd);
> +}
> +}
> +
> + for (i = base; i < base + DRM_MAX_MINOR; i++) {
> +fd = drmOpenMinor(i, 1, type);
> +drmMsg("drmOpenByBusid: drmOpenMinor returns %d\n", fd);
> +if (fd >= 0) {
> /* We need to try for 1.4 first for proper PCI domain support
> * and if that fails, we know the kernel is busted
> */
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: remove some old unused dpm helpers
Carried over from radeon, but no longer used.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 88 -
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 9 ---
2 files changed, 97 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 1c4595562f8f..344967df3137 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -184,61 +184,6 @@ u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev)
return vrefresh;
}
-void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
- u32 *p, u32 *u)
-{
- u32 b_c = 0;
- u32 i_c;
- u32 tmp;
-
- i_c = (i * r_c) / 100;
- tmp = i_c >> p_b;
-
- while (tmp) {
- b_c++;
- tmp >>= 1;
- }
-
- *u = (b_c + 1) / 2;
- *p = i_c / (1 << (2 * (*u)));
-}
-
-int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
-{
- u32 k, a, ah, al;
- u32 t1;
-
- if ((fl == 0) || (fh == 0) || (fl > fh))
- return -EINVAL;
-
- k = (100 * fh) / fl;
- t1 = (t * (k - 100));
- a = (1000 * (100 * h + t1)) / (1 + (t1 / 100));
- a = (a + 5) / 10;
- ah = ((a * t) + 5000) / 1;
- al = a - ah;
-
- *th = t - ah;
- *tl = t + al;
-
- return 0;
-}
-
-bool amdgpu_is_uvd_state(u32 class, u32 class2)
-{
- if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
- return true;
- if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
- return true;
- if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
- return true;
- if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
- return true;
- if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
- return true;
- return false;
-}
-
bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor)
{
switch (sensor) {
@@ -949,39 +894,6 @@ enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct
amdgpu_device *adev,
return AMDGPU_PCIE_GEN1;
}
-u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
-u16 asic_lanes,
-u16 default_lanes)
-{
- switch (asic_lanes) {
- case 0:
- default:
- return default_lanes;
- case 1:
- return 1;
- case 2:
- return 2;
- case 4:
- return 4;
- case 8:
- return 8;
- case 12:
- return 12;
- case 16:
- return 16;
- }
-}
-
-u8 amdgpu_encode_pci_lane_width(u32 lanes)
-{
- u8 encoded_lanes[] = { 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0,
6 };
-
- if (lanes > 16)
- return 0;
-
- return encoded_lanes[lanes];
-}
-
struct amd_vce_state*
amdgpu_get_vce_clock_state(void *handle, u32 idx)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 2f61e9edb1c1..e871e022c129 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -486,10 +486,6 @@ void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev);
-bool amdgpu_is_uvd_state(u32 class, u32 class2);
-void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
- u32 *p, u32 *u);
-int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
@@ -505,11 +501,6 @@ enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct
amdgpu_device *adev,
enum amdgpu_pcie_gen asic_gen,
enum amdgpu_pcie_gen
default_gen);
-u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
-u16 asic_lanes,
-u16 default_lanes);
-u8 amdgpu_encode_pci_lane_width(u32 lanes);
-
struct amd_vce_state*
amdgpu_get_vce_clock_state(void *handle, u32 idx);
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2 1/4] drm/sched: Fix entities with 0 rqs.
On Wed, Jan 30, 2019 at 5:43 AM Christian König
wrote:
>
> Am 30.01.19 um 02:53 schrieb Bas Nieuwenhuizen:
> > Some blocks in amdgpu can have 0 rqs.
> >
> > Job creation already fails with -ENOENT when entity->rq is NULL,
> > so jobs cannot be pushed. Without a rq there is no scheduler to
> > pop jobs, and rq selection already does the right thing with a
> > list of length 0.
> >
> > So the operations we need to fix are:
> >- Creation, do not set rq to rq_list[0] if the list can have length 0.
> >- Do not flush any jobs when there is no rq.
> >- On entity destruction handle the rq = NULL case.
> >- on set_priority, do not try to change the rq if it is NULL.
> >
> > Signed-off-by: Bas Nieuwenhuizen
>
> One minor comment on patch #2, apart from that the series is
> Reviewed-by: Christian König .
>
> I'm going to make the change on #2 and pick them up for inclusion in
> amd-staging-drm-next.
Hi Christian,
I haven't seen these land yet. Just want to make sure they don't fall
through the cracks.
Alex
>
> Thanks for the help,
> Christian.
>
> > ---
> > drivers/gpu/drm/scheduler/sched_entity.c | 39
> > 1 file changed, 26 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
> > b/drivers/gpu/drm/scheduler/sched_entity.c
> > index 4463d3826ecb..8e31b6628d09 100644
> > --- a/drivers/gpu/drm/scheduler/sched_entity.c
> > +++ b/drivers/gpu/drm/scheduler/sched_entity.c
> > @@ -52,12 +52,12 @@ int drm_sched_entity_init(struct drm_sched_entity
> > *entity,
> > {
> > int i;
> >
> > - if (!(entity && rq_list && num_rq_list > 0 && rq_list[0]))
> > + if (!(entity && rq_list && (num_rq_list == 0 || rq_list[0])))
> > return -EINVAL;
> >
> > memset(entity, 0, sizeof(struct drm_sched_entity));
> > INIT_LIST_HEAD(>list);
> > - entity->rq = rq_list[0];
> > + entity->rq = NULL;
> > entity->guilty = guilty;
> > entity->num_rq_list = num_rq_list;
> > entity->rq_list = kcalloc(num_rq_list, sizeof(struct drm_sched_rq *),
> > @@ -67,6 +67,10 @@ int drm_sched_entity_init(struct drm_sched_entity
> > *entity,
> >
> > for (i = 0; i < num_rq_list; ++i)
> > entity->rq_list[i] = rq_list[i];
> > +
> > + if (num_rq_list)
> > + entity->rq = rq_list[0];
> > +
> > entity->last_scheduled = NULL;
> >
> > spin_lock_init(>rq_lock);
> > @@ -165,6 +169,9 @@ long drm_sched_entity_flush(struct drm_sched_entity
> > *entity, long timeout)
> > struct task_struct *last_user;
> > long ret = timeout;
> >
> > + if (!entity->rq)
> > + return 0;
> > +
> > sched = entity->rq->sched;
> > /**
> >* The client will not queue more IBs during this fini, consume
> > existing
> > @@ -264,20 +271,24 @@ static void drm_sched_entity_kill_jobs(struct
> > drm_sched_entity *entity)
> >*/
> > void drm_sched_entity_fini(struct drm_sched_entity *entity)
> > {
> > - struct drm_gpu_scheduler *sched;
> > + struct drm_gpu_scheduler *sched = NULL;
> >
> > - sched = entity->rq->sched;
> > - drm_sched_rq_remove_entity(entity->rq, entity);
> > + if (entity->rq) {
> > + sched = entity->rq->sched;
> > + drm_sched_rq_remove_entity(entity->rq, entity);
> > + }
> >
> > /* Consumption of existing IBs wasn't completed. Forcefully
> >* remove them here.
> >*/
> > if (spsc_queue_peek(>job_queue)) {
> > - /* Park the kernel for a moment to make sure it isn't
> > processing
> > - * our enity.
> > - */
> > - kthread_park(sched->thread);
> > - kthread_unpark(sched->thread);
> > + if (sched) {
> > + /* Park the kernel for a moment to make sure it isn't
> > processing
> > + * our enity.
> > + */
> > + kthread_park(sched->thread);
> > + kthread_unpark(sched->thread);
> > + }
> > if (entity->dependency) {
> > dma_fence_remove_callback(entity->dependency,
> > >cb);
> > @@ -362,9 +373,11 @@ void drm_sched_entity_set_priority(struct
> > drm_sched_entity *entity,
> > for (i = 0; i < entity->num_rq_list; ++i)
> > drm_sched_entity_set_rq_priority(>rq_list[i],
> > priority);
> >
> > - drm_sched_rq_remove_entity(entity->rq, entity);
> > - drm_sched_entity_set_rq_priority(>rq, priority);
> > - drm_sched_rq_add_entity(entity->rq, entity);
> > + if (entity->rq) {
> > + drm_sched_rq_remove_entity(entity->rq, entity);
> > + drm_sched_entity_set_rq_priority(>rq, priority);
> > + drm_sched_rq_add_entity(entity->rq, entity);
> > + }
> >
> > spin_unlock(>rq_lock);
> > }
>
> ___
> amd-gfx
Re: [PATCH] drm/amd/display: Fix reference counting for struct dc_sink.
Add amd-gfx and some DC people. Alex On Sun, Feb 10, 2019 at 5:13 AM wrote: > > From: Mathias Fröhlich > > Reference counting in amdgpu_dm_connector for amdgpu_dm_connector::dc_sink > and amdgpu_dm_connector::dc_em_sink as well as in dc_link::local_sink seems > to be out of shape. Thus make reference counting consistent for these > members and just plain increment the reference count when the variable > gets assigned and decrement when the pointer is set to zero or replaced. > Also simplify reference counting in selected function sopes to be sure the > reference is released in any case. In some cases add NULL pointer check > before dereferencing. > At a hand full of places a comment is placed to stat that the reference > increment happened already somewhere else. > > This actually fixes the following kernel bug on my system when enabling > display core in amdgpu. There are some more similar bug reports around, > so it probably helps at more places. > >kernel BUG at mm/slub.c:294! >invalid opcode: [#1] SMP PTI >CPU: 9 PID: 1180 Comm: Xorg Not tainted 5.0.0-rc1+ #2 >Hardware name: Supermicro X10DAi/X10DAI, BIOS 3.0a 02/05/2018 >RIP: 0010:__slab_free+0x1e2/0x3d0 >Code: 8b 54 24 30 48 89 4c 24 28 e8 da fb ff ff 4c 8b 54 24 28 85 c0 0f 85 > 67 fe ff ff 48 8d 65 d8 5b 41 5c 41 5d 41 5e 41 5f 5d c3 <0f> 0b 49 3b 5c 24 > 28 75 ab 48 8b 44 24 30 49 89 4c 24 28 49 89 44 >RSP: 0018:b0978589fa90 EFLAGS: 00010246 >RAX: 92f12806c400 RBX: 80200019 RCX: 92f12806c400 >RDX: 92f12806c400 RSI: dd6421a01a00 RDI: 92ed2f406e80 >RBP: b0978589fb40 R08: 0001 R09: c0ee4748 >R10: 92f12806c400 R11: 0001 R12: dd6421a01a00 >R13: 92f12806c400 R14: 92ed2f406e80 R15: dd6421a01a20 >FS: 7f4170be0ac0() GS:92ed2fb4() > knlGS: >CS: 0010 DS: ES: CR0: 80050033 >CR2: 562818aaa000 CR3: 00045745a002 CR4: 003606e0 >DR0: DR1: DR2: >DR3: DR6: fffe0ff0 DR7: 0400 >Call Trace: > ? drm_dbg+0x87/0x90 [drm] > dc_stream_release+0x28/0x50 [amdgpu] > amdgpu_dm_connector_mode_valid+0xb4/0x1f0 [amdgpu] > drm_helper_probe_single_connector_modes+0x492/0x6b0 [drm_kms_helper] > drm_mode_getconnector+0x457/0x490 [drm] > ? drm_connector_property_set_ioctl+0x60/0x60 [drm] > drm_ioctl_kernel+0xa9/0xf0 [drm] > drm_ioctl+0x201/0x3a0 [drm] > ? drm_connector_property_set_ioctl+0x60/0x60 [drm] > amdgpu_drm_ioctl+0x49/0x80 [amdgpu] > do_vfs_ioctl+0xa4/0x630 > ? __sys_recvmsg+0x83/0xa0 > ksys_ioctl+0x60/0x90 > __x64_sys_ioctl+0x16/0x20 > do_syscall_64+0x5b/0x160 > entry_SYSCALL_64_after_hwframe+0x44/0xa9 >RIP: 0033:0x7f417110809b >Code: 0f 1e fa 48 8b 05 ed bd 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff > ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff > 73 01 c3 48 8b 0d bd bd 0c 00 f7 d8 64 89 01 48 >RSP: 002b:7ffdd8d1c268 EFLAGS: 0246 ORIG_RAX: 0010 >RAX: ffda RBX: 562818a8ebc0 RCX: 7f417110809b >RDX: 7ffdd8d1c2a0 RSI: c05064a7 RDI: 0012 >RBP: 7ffdd8d1c2a0 R08: 562819012280 R09: 0007 >R10: R11: 0246 R12: c05064a7 >R13: 0012 R14: 0012 R15: 7ffdd8d1c2a0 >Modules linked in: nfsv4 dns_resolver nfs lockd grace fscache fuse vfat > fat amdgpu intel_rapl sb_edac x86_pkg_temp_thermal intel_powerclamp coretemp > kvm_intel kvm irqbypass crct10dif_pclmul chash gpu_sched crc32_pclmul > snd_hda_codec_realtek ghash_clmulni_intel amd_iommu_v2 iTCO_wdt > iTCO_vendor_support ttm snd_hda_codec_generic snd_hda_codec_hdmi > ledtrig_audio snd_hda_intel drm_kms_helper snd_hda_codec intel_cstate > snd_hda_core drm snd_hwdep snd_seq snd_seq_device intel_uncore snd_pcm > intel_rapl_perf snd_timer snd soundcore ioatdma pcspkr intel_wmi_thunderbolt > mxm_wmi i2c_i801 lpc_ich pcc_cpufreq auth_rpcgss sunrpc igb crc32c_intel > i2c_algo_bit dca wmi hid_cherry analog gameport joydev > > This patch is based on agd5f/drm-next-5.1-wip. This patch does not require > all of that, but agd5f/drm-next-5.1-wip contains at least one more dc_sink > counting fix that I could spot. > > Signed-off-by: Mathias Fröhlich > --- > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 43 +++ > .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 + > drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 + > 3 files changed, 37 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 3a6f595f295e..20fa01bff685 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++
[pull] amdgpu, sched drm-fixes-5.0
Hi Dave, Daniel, A few small fixes for 5.0. amdgpu: - Vega20 psp fix - Add vrr range to debugfs for freesync debugging sched: - Scheduler race fix The following changes since commit 78eb1ca47589f0cd9db2ceb28b60434e8d512131: Merge branch 'vmwgfx-fixes-5.0-2' of git://people.freedesktop.org/~thomash/linux into drm-fixes (2019-02-07 10:36:47 +1000) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux drm-fixes-5.0 for you to fetch changes up to 1d69511e49b0107c0a60ff5ef488f5a2512a50ae: drm/amdgpu/psp11: TA firmware is optional (v3) (2019-02-13 09:44:05 -0500) Alex Deucher (1): drm/amdgpu/psp11: TA firmware is optional (v3) Eric Anholt (1): drm/sched: Always trace the dependencies we wait on, to fix a race. Nicholas Kazlauskas (1): drm/amd/display: Expose connector VRR range via debugfs drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 9 +-- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 28 -- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 22 - drivers/gpu/drm/scheduler/sched_entity.c | 7 ++ 4 files changed, 46 insertions(+), 20 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/powerplay: declare firmware for CI cards
Missing firmware declaration caused firmware requirement to
not be noted by the module and may cause firmware to not
be available in initrd.
Fixes: bc4b539e385088 "drm/amdgpu: remove old CI DPM implementation"
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index a6edd5df33b0..4240aeec9000 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -29,6 +29,10 @@
#include
#include "smumgr.h"
+MODULE_FIRMWARE("amdgpu/bonaire_smc.bin");
+MODULE_FIRMWARE("amdgpu/bonaire_k_smc.bin");
+MODULE_FIRMWARE("amdgpu/hawaii_smc.bin");
+MODULE_FIRMWARE("amdgpu/hawaii_k_smc.bin");
MODULE_FIRMWARE("amdgpu/topaz_smc.bin");
MODULE_FIRMWARE("amdgpu/topaz_k_smc.bin");
MODULE_FIRMWARE("amdgpu/tonga_smc.bin");
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/psp11: TA firmware is optional (v3)
Don't warn or fail if it's missing.
v2: handle xgmi case more gracefully.
v3: handle older kernels properly
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 ++--
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 28 ++---
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8fab0d637ee5..3a9b48b227ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -90,8 +90,10 @@ static int psp_sw_fini(void *handle)
adev->psp.sos_fw = NULL;
release_firmware(adev->psp.asd_fw);
adev->psp.asd_fw = NULL;
- release_firmware(adev->psp.ta_fw);
- adev->psp.ta_fw = NULL;
+ if (adev->psp.ta_fw) {
+ release_firmware(adev->psp.ta_fw);
+ adev->psp.ta_fw = NULL;
+ }
return 0;
}
@@ -435,6 +437,9 @@ static int psp_xgmi_initialize(struct psp_context *psp)
struct ta_xgmi_shared_memory *xgmi_cmd;
int ret;
+ if (!psp->adev->psp.ta_fw)
+ return -ENOENT;
+
if (!psp->xgmi_context.initialized) {
ret = psp_xgmi_init_shared_buf(psp);
if (ret)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 0c6e7f9b143f..189fcb004579 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -152,18 +152,22 @@ static int psp_v11_0_init_microcode(struct psp_context
*psp)
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
err = request_firmware(>psp.ta_fw, fw_name, adev->dev);
- if (err)
- goto out2;
-
- err = amdgpu_ucode_validate(adev->psp.ta_fw);
- if (err)
- goto out2;
-
- ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
- adev->psp.ta_xgmi_ucode_version =
le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
- adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
- adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
- le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+ if (err) {
+ release_firmware(adev->psp.ta_fw);
+ adev->psp.ta_fw = NULL;
+ dev_info(adev->dev,
+"psp v11.0: Failed to load firmware \"%s\"\n",
fw_name);
+ } else {
+ err = amdgpu_ucode_validate(adev->psp.ta_fw);
+ if (err)
+ goto out2;
+
+ ta_hdr = (const struct ta_firmware_header_v1_0
*)adev->psp.ta_fw->data;
+ adev->psp.ta_xgmi_ucode_version =
le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
+ adev->psp.ta_xgmi_ucode_size =
le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
+ adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
+ le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+ }
return 0;
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/psp11: TA firmware is optional (v2)
Don't warn or fail if it's missing.
v2: handle xgmi case more gracefully.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 ++--
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 28 ++---
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index d87f165e3a23..5df74131678e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -84,8 +84,10 @@ static int psp_sw_fini(void *handle)
adev->psp.sos_fw = NULL;
release_firmware(adev->psp.asd_fw);
adev->psp.asd_fw = NULL;
- release_firmware(adev->psp.ta_fw);
- adev->psp.ta_fw = NULL;
+ if (adev->psp.ta_fw) {
+ release_firmware(adev->psp.ta_fw);
+ adev->psp.ta_fw = NULL;
+ }
return 0;
}
@@ -440,6 +442,9 @@ static int psp_xgmi_initialize(struct psp_context *psp)
struct ta_xgmi_shared_memory *xgmi_cmd;
int ret;
+ if (!adev->psp.ta_fw)
+ return -ENOENT;
+
if (!psp->xgmi_context.initialized) {
ret = psp_xgmi_init_shared_buf(psp);
if (ret)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index f71384be1f97..860b70d80d3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -98,18 +98,22 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
err = request_firmware(>psp.ta_fw, fw_name, adev->dev);
- if (err)
- goto out2;
-
- err = amdgpu_ucode_validate(adev->psp.ta_fw);
- if (err)
- goto out2;
-
- ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
- adev->psp.ta_xgmi_ucode_version =
le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
- adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
- adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
- le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+ if (err) {
+ release_firmware(adev->psp.ta_fw);
+ adev->psp.ta_fw = NULL;
+ dev_info(adev->dev,
+"psp v11.0: Failed to load firmware \"%s\"\n",
fw_name);
+ } else {
+ err = amdgpu_ucode_validate(adev->psp.ta_fw);
+ if (err)
+ goto out2;
+
+ ta_hdr = (const struct ta_firmware_header_v1_0
*)adev->psp.ta_fw->data;
+ adev->psp.ta_xgmi_ucode_version =
le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
+ adev->psp.ta_xgmi_ucode_size =
le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
+ adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
+ le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+ }
return 0;
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/psp11: TA firmware is optional
Don't warn or fail if it's missing.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 --
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 28 ++---
2 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index d87f165e3a23..d5fad352e9eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -84,8 +84,10 @@ static int psp_sw_fini(void *handle)
adev->psp.sos_fw = NULL;
release_firmware(adev->psp.asd_fw);
adev->psp.asd_fw = NULL;
- release_firmware(adev->psp.ta_fw);
- adev->psp.ta_fw = NULL;
+ if (adev->psp.ta_fw) {
+ release_firmware(adev->psp.ta_fw);
+ adev->psp.ta_fw = NULL;
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index f71384be1f97..860b70d80d3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -98,18 +98,22 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
err = request_firmware(>psp.ta_fw, fw_name, adev->dev);
- if (err)
- goto out2;
-
- err = amdgpu_ucode_validate(adev->psp.ta_fw);
- if (err)
- goto out2;
-
- ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
- adev->psp.ta_xgmi_ucode_version =
le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
- adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
- adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
- le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+ if (err) {
+ release_firmware(adev->psp.ta_fw);
+ adev->psp.ta_fw = NULL;
+ dev_info(adev->dev,
+"psp v11.0: Failed to load firmware \"%s\"\n",
fw_name);
+ } else {
+ err = amdgpu_ucode_validate(adev->psp.ta_fw);
+ if (err)
+ goto out2;
+
+ ta_hdr = (const struct ta_firmware_header_v1_0
*)adev->psp.ta_fw->data;
+ adev->psp.ta_xgmi_ucode_version =
le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
+ adev->psp.ta_xgmi_ucode_size =
le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
+ adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
+ le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+ }
return 0;
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/psp11: TA firmware is optional (v2)
Don't warn or fail if it's missing.
v2: handle xgmi case more gracefully.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 ++--
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 28 ++---
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index d87f165e3a23..5df74131678e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -84,8 +84,10 @@ static int psp_sw_fini(void *handle)
adev->psp.sos_fw = NULL;
release_firmware(adev->psp.asd_fw);
adev->psp.asd_fw = NULL;
- release_firmware(adev->psp.ta_fw);
- adev->psp.ta_fw = NULL;
+ if (adev->psp.ta_fw) {
+ release_firmware(adev->psp.ta_fw);
+ adev->psp.ta_fw = NULL;
+ }
return 0;
}
@@ -440,6 +442,9 @@ static int psp_xgmi_initialize(struct psp_context *psp)
struct ta_xgmi_shared_memory *xgmi_cmd;
int ret;
+ if (!adev->psp.ta_fw)
+ return -ENOENT;
+
if (!psp->xgmi_context.initialized) {
ret = psp_xgmi_init_shared_buf(psp);
if (ret)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index f71384be1f97..860b70d80d3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -98,18 +98,22 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
err = request_firmware(>psp.ta_fw, fw_name, adev->dev);
- if (err)
- goto out2;
-
- err = amdgpu_ucode_validate(adev->psp.ta_fw);
- if (err)
- goto out2;
-
- ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
- adev->psp.ta_xgmi_ucode_version =
le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
- adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
- adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
- le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+ if (err) {
+ release_firmware(adev->psp.ta_fw);
+ adev->psp.ta_fw = NULL;
+ dev_info(adev->dev,
+"psp v11.0: Failed to load firmware \"%s\"\n",
fw_name);
+ } else {
+ err = amdgpu_ucode_validate(adev->psp.ta_fw);
+ if (err)
+ goto out2;
+
+ ta_hdr = (const struct ta_firmware_header_v1_0
*)adev->psp.ta_fw->data;
+ adev->psp.ta_xgmi_ucode_version =
le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
+ adev->psp.ta_xgmi_ucode_size =
le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
+ adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
+ le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+ }
return 0;
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: don't clamp debugfs register access to the BAR size
This prevents us from accessing extended registers in tools like
umr. The register access functions already check if the offset
is beyond the BAR size and use the indirect accessors with locking
so this is safe.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index dd9a4fb9ce39..4ae3ff9a1d4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -158,9 +158,6 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct
file *f,
while (size) {
uint32_t value;
- if (*pos > adev->rmmio_size)
- goto end;
-
if (read) {
value = RREG32(*pos >> 2);
r = put_user(value, (uint32_t *)buf);
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
