from:"Chen, Jiansong \(Simon\)"

RE: [PATCH] drm/amdgpu: fix the doorbell missing when in CGPG issue for renoir.

2021-07-28 Thread Chen, Jiansong (Simon)

[AMD Official Use Only]

A coding style issue, "Do not unnecessarily use braces where a single statement 
will do."

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Yifan Zhang
Sent: Wednesday, July 28, 2021 11:40 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Yifan 
Subject: [PATCH] drm/amdgpu: fix the doorbell missing when in CGPG issue for 
renoir.

If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC.
Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue.

Signed-off-by: Yifan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 03acc777adf7..61a8583f02a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3675,8 +3675,17 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring 
*ring)
if (ring->use_doorbell) {
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
(adev->doorbell_index.kiq * 2) << 2);
-   WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+   /* In renoir, if GC has entered CGPG, ringing doorbell > first 
page
+* doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to
+* workaround this issue.
+*/
+   if (adev->asic_type == CHIP_RENOIR) {
+   WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+   (adev->doorbell.size - 4));
+   } else {
+   WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
(adev->doorbell_index.userqueue_end * 
2) << 2);
+   }
}

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
--
2.25.1

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RE: [PATCH 2/3] drm/amdgpu: Fix a printing message

2021-07-15 Thread Chen, Jiansong (Simon)

[Public]

Ok, I see. Thanks!

Regards,
Jiansong
From: Deucher, Alexander 
Sent: Thursday, July 15, 2021 10:55 AM
To: Chen, Jiansong (Simon) ; Alex Deucher 
; Zeng, Oak 
Cc: Xu, Feifei ; Kuehling, Felix ; 
Liu, Leo ; amd-gfx list ; 
Zhang, Hawking 
Subject: Re: [PATCH 2/3] drm/amdgpu: Fix a printing message


[Public]

I think it's more consistent to use dev_info since we already use that pretty 
extensively in the driver.

Alex


From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Chen, Jiansong (Simon) 
mailto:jiansong.c...@amd.com>>
Sent: Wednesday, July 14, 2021 10:51 PM
To: Alex Deucher mailto:alexdeuc...@gmail.com>>; Zeng, 
Oak mailto:oak.z...@amd.com>>
Cc: Xu, Feifei mailto:feifei...@amd.com>>; Kuehling, Felix 
mailto:felix.kuehl...@amd.com>>; Liu, Leo 
mailto:leo@amd.com>>; amd-gfx list 
mailto:amd-gfx@lists.freedesktop.org>>; Zhang, 
Hawking mailto:hawking.zh...@amd.com>>
Subject: RE: [PATCH 2/3] drm/amdgpu: Fix a printing message

[Public]

[Public]

Hi Alex,
Is DRM_DEV_INFO more suitable than dev_info as far as DRM subsystem is 
concerned? Thanks!

Regards,
Jiansong
-Original Message-
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Alex Deucher
Sent: Wednesday, July 14, 2021 11:48 PM
To: Zeng, Oak mailto:oak.z...@amd.com>>
Cc: Xu, Feifei mailto:feifei...@amd.com>>; Kuehling, Felix 
mailto:felix.kuehl...@amd.com>>; Liu, Leo 
mailto:leo@amd.com>>; amd-gfx list 
mailto:amd-gfx@lists.freedesktop.org>>; Zhang, 
Hawking mailto:hawking.zh...@amd.com>>
Subject: Re: [PATCH 2/3] drm/amdgpu: Fix a printing message

On Wed, Jul 14, 2021 at 11:25 AM Oak Zeng 
mailto:oak.z...@amd.com>> wrote:
>
> The printing message "PSP loading VCN firmware" is mis-leading because
> people might think driver is loading VCN firmware. Actually when this
> message is printed, driver is just preparing some VCN ucode, not
> loading VCN firmware yet. The actual VCN firmware loading will be in
> the PSP block hw_init. Fix the printing message
>
> Signed-off-by: Oak Zeng mailto:oak.z...@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 284bb42..1f8e902 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -119,7 +119,7 @@ static int vcn_v1_0_sw_init(void *handle)
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 1.0: Will use PSP to load VCN
> + firmware\n");
> }
>
> r = amdgpu_vcn_resume(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 8af567c..ebe4f2b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -122,7 +122,7 @@ static int vcn_v2_0_sw_init(void *handle)
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 2.0: Will use PSP to load VCN
> + firmware\n");

While you are here, switch to dev_info() so we get the device information in 
the output (in case we have multiple GPUs in a system).

Alex

> }
>
> r = amdgpu_vcn_resume(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 888b17d..5741504 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -152,7 +152,7 @@ static int vcn_v2_5_sw_init(void *handle)
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), 
> PAGE_SIZE);
> }
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 2.5: Will use PSP to load VCN
> + firmware\n");
> }
>
> r = amdgpu_vcn_resume(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> ind

RE: [PATCH 2/3] drm/amdgpu: Fix a printing message

2021-07-15 Thread Chen, Jiansong (Simon)

[Public]

Hi Alex,
Is DRM_DEV_INFO more suitable than dev_info as far as DRM subsystem is 
concerned? Thanks!

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Wednesday, July 14, 2021 11:48 PM
To: Zeng, Oak 
Cc: Xu, Feifei ; Kuehling, Felix ; 
Liu, Leo ; amd-gfx list ; 
Zhang, Hawking 
Subject: Re: [PATCH 2/3] drm/amdgpu: Fix a printing message

On Wed, Jul 14, 2021 at 11:25 AM Oak Zeng  wrote:
>
> The printing message "PSP loading VCN firmware" is mis-leading because
> people might think driver is loading VCN firmware. Actually when this
> message is printed, driver is just preparing some VCN ucode, not
> loading VCN firmware yet. The actual VCN firmware loading will be in
> the PSP block hw_init. Fix the printing message
>
> Signed-off-by: Oak Zeng 
> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 284bb42..1f8e902 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -119,7 +119,7 @@ static int vcn_v1_0_sw_init(void *handle)
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 1.0: Will use PSP to load VCN
> + firmware\n");
> }
>
> r = amdgpu_vcn_resume(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 8af567c..ebe4f2b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -122,7 +122,7 @@ static int vcn_v2_0_sw_init(void *handle)
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 2.0: Will use PSP to load VCN
> + firmware\n");

While you are here, switch to dev_info() so we get the device information in 
the output (in case we have multiple GPUs in a system).

Alex

> }
>
> r = amdgpu_vcn_resume(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 888b17d..5741504 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -152,7 +152,7 @@ static int vcn_v2_5_sw_init(void *handle)
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), 
> PAGE_SIZE);
> }
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 2.5: Will use PSP to load VCN
> + firmware\n");
> }
>
> r = amdgpu_vcn_resume(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index c3580de..b81eae3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -158,7 +158,7 @@ static int vcn_v3_0_sw_init(void *handle)
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), 
> PAGE_SIZE);
> }
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 3.0: Will use PSP to load VCN
> + firmware\n");
> }
>
> r = amdgpu_vcn_resume(adev);
> --
> 2.7.4
>
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RE: [PATCH] drm/amd/display: avoid printing ERROR for unknown CEA parse

2021-07-13 Thread Chen, Jiansong (Simon)

[AMD Official Use Only]

Is DRM_WARN more suitable for the case?

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Guchun Chen
Sent: Tuesday, July 13, 2021 1:56 PM
To: amd-gfx@lists.freedesktop.org; Wang, Chao-kai (Stylon) 
; Kazlauskas, Nicholas ; 
Siqueira, Rodrigo ; Yin, Tianci (Rico) 

Cc: Chen, Guchun 
Subject: [PATCH] drm/amd/display: avoid printing ERROR for unknown CEA parse

For the unknown CEA parse case on DMUB-enabled ASICs, dmesg will print an error 
message like below, this will be captured by automation tools as it has the 
word like ERROR during boot up and treated as a false error, as it does not 
break bootup process.
So use DRM_INFO printing for this.

[drm:amdgpu_dm_update_freesync_caps [amdgpu]] *ERROR* Unknown EDID CEA parser 
results

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 03db86bfaec8..613540b0766e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -10700,7 +10700,7 @@ static bool dm_edid_parser_send_cea(struct 
amdgpu_display_manager *dm,
vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
} else {
-   DRM_ERROR("Unknown EDID CEA parser results\n");
+   DRM_INFO("Unknown EDID CEA parser results\n");
return false;
}

--
2.17.1

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RE: [PATCH] drm/amd/pm: Fix BACO state setting for Beige_Goby

2021-07-09 Thread Chen, Jiansong (Simon)

[AMD Official Use Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Chengming Gui 
Sent: Friday, July 9, 2021 4:29 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Chen, Jiansong (Simon) 
; Chen, Guchun ; Feng, Kenneth 
; Zhang, Hawking ; Gui, Jack 

Subject: [PATCH] drm/amd/pm: Fix BACO state setting for Beige_Goby

Correct BACO state setting for Beige_Goby

Signed-off-by: Chengming Gui 
Change-Id: I28b9a526f1b353c3986225f075c613ba88b6ae2b
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 388c5cb5c647..0a5d46ac9ccd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1528,6 +1528,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, 
enum smu_baco_state state)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
+   case CHIP_BEIGE_GOBY:
if (amdgpu_runtime_pm == 2)
ret = smu_cmn_send_smc_msg_with_param(smu,
  
SMU_MSG_EnterBaco,
--
2.17.1

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RE: [PATCH] SWDEV-291099 - Use a percise function name

2021-07-06 Thread Chen, Jiansong (Simon)

[AMD Official Use Only]

Internal ticket number is not appropriate to appear in upstream patch, and 
percise->precise in the subject?

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Roy Sun
Sent: Monday, July 5, 2021 6:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Sun, Roy 
Subject: [PATCH] SWDEV-291099 - Use a percise function name

The callback functions are used for SRIOV read/write instead of just for rlcg 
read/write

Signed-off-by: Roy Sun 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h| 4 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/soc15_common.h  | 8 
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index eb1f3f42e00b..aa94ad0e9973 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -508,7 +508,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
adev->gfx.rlc.funcs &&
adev->gfx.rlc.funcs->is_rlcg_access_range) {
if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
-   return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0, 
0);
+   return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v, 0, 
0);
} else {
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index 7a4775ab6804..00afd0dcae86 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs {
void (*reset)(struct amdgpu_device *adev);
void (*start)(struct amdgpu_device *adev);
void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
-   void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 
acc_flags, u32 hwip);
-   u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 acc_flags, 
u32 hwip);
+   void (*sriov_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 
acc_flags, u32 hwip);
+   u32 (*sriov_rreg)(struct amdgpu_device *adev, u32 offset, u32
+acc_flags, u32 hwip);
bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg); 
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 705fa3027199..c9b68a8611d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -8269,8 +8269,8 @@ static const struct amdgpu_rlc_funcs 
gfx_v10_0_rlc_funcs_sriov = {
.reset = gfx_v10_0_rlc_reset,
.start = gfx_v10_0_rlc_start,
.update_spm_vmid = gfx_v10_0_update_spm_vmid,
-   .rlcg_wreg = gfx_v10_rlcg_wreg,
-   .rlcg_rreg = gfx_v10_rlcg_rreg,
+   .sriov_wreg = gfx_v10_rlcg_wreg,
+   .sriov_rreg = gfx_v10_rlcg_rreg,
.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,  };

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 044076ec1d03..1c9b8b37fd3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5131,7 +5131,7 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = 
{
.reset = gfx_v9_0_rlc_reset,
.start = gfx_v9_0_rlc_start,
.update_spm_vmid = gfx_v9_0_update_spm_vmid,
-   .rlcg_wreg = gfx_v9_0_rlcg_wreg,
+   .sriov_wreg = gfx_v9_0_rlcg_wreg,
.is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,  };

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h 
b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index 0eeb5e073be8..8a9ca87d8663 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -28,13 +28,13 @@
 #define SOC15_REG_OFFSET(ip, inst, reg)
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)

 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
-   ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && 
adev->gfx.rlc.funcs->rlcg_wreg) ? \
-adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
+   ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && 
adev->gfx.rlc.funcs->sriov_wreg) ? \
+adev->gfx.rlc.funcs->sriov_wreg(adev, reg, value, flag, hwip) : \
 WREG32(reg, value))

 #define __RREG32_SOC15_RLC__(reg, flag, hwip) \
-   ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && 
adev->gfx.rlc.funcs->rlcg_rreg) ? \
-adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
+   ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && 
adev->gfx.rlc.funcs->sriov_rreg) ? \
+adev->gfx.rlc.funcs->sriov_rreg(adev, reg, flag, hwip) : \
 RREG32(reg))

 #define WREG32_FIELD15(ip, idx, reg, field, val)   \
--
2.32.0

RE: [PATCH 2/2] drm/amdkfd: Walk thorugh list with dqm lock hold

2021-06-16 Thread Chen, Jiansong (Simon)

[AMD Official Use Only]

BTW, there is an obvious typo in the subject, Walk thorugh => Walk through.

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Felix 
Kuehling
Sent: Thursday, June 17, 2021 7:09 AM
To: Pan, Xinhui ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian 

Subject: Re: [PATCH 2/2] drm/amdkfd: Walk thorugh list with dqm lock hold

On 2021-06-16 4:35 a.m., xinhui pan wrote:
> To avoid any list corruption.
>
> Signed-off-by: xinhui pan 
> ---
>   .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c| 12 
>   1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index c24ab8f17eb6..1f84de861ec6 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -1704,7 +1704,7 @@ static int process_termination_cpsch(struct 
> device_queue_manager *dqm,
>   struct qcm_process_device *qpd)
>   {
>   int retval;
> - struct queue *q, *next;
> + struct queue *q;
>   struct kernel_queue *kq, *kq_next;
>   struct mqd_manager *mqd_mgr;
>   struct device_process_node *cur, *next_dpn; @@ -1739,8 +1739,6 @@
> static int process_termination_cpsch(struct device_queue_manager *dqm,
>   qpd->mapped_gws_queue = false;
>   }
>   }
> -
> - dqm->total_queue_count--;

I think this should stay here. This is only used to check the maximum user 
queue limit per-device, which is a HW limitation. As far as the HW is 
concerned, the queues are destroyed after the call to execute_queues_cpsch. So 
there is no need to delay this update.


>   }
>
>   /* Unregister process */
> @@ -1772,13 +1770,19 @@ static int process_termination_cpsch(struct 
> device_queue_manager *dqm,
>   /* Lastly, free mqd resources.
>* Do free_mqd() after dqm_unlock to avoid circular locking.
>*/
> - list_for_each_entry_safe(q, next, >queues_list, list) {
> + dqm_lock(dqm);

Instead of taking the dqm lock again, just move this up a couple of lines 
before the dqm_unlock call.

Regards,
   Felix


> + while (!list_empty(>queues_list)) {
> + q = list_first_entry(>queues_list, struct queue, list);
>   mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
>   q->properties.type)];
>   list_del(>list);
>   qpd->queue_count--;
> + dqm->total_queue_count--;
> + dqm_unlock(dqm);
>   mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
> + dqm_lock(dqm);
>   }
> + dqm_unlock(dqm);
>
>   return retval;
>   }
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RE: [PATCH] drm/amdgpu: refine amdgpu_fru_get_product_info

2021-05-25 Thread Chen, Jiansong (Simon)

I think we still could keep them to be more informative for the moment.

Regards,
Jiansong
-Original Message-
From: Chen, Guchun  
Sent: Tuesday, May 25, 2021 3:47 PM
To: Chen, Jiansong (Simon) ; 
amd-gfx@lists.freedesktop.org
Cc: Chen, Jiansong (Simon) 
Subject: RE: [PATCH] drm/amdgpu: refine amdgpu_fru_get_product_info

[AMD Public Use]

+   len = size;
/* Serial number should only be 16 characters. Any more,
 * and something could be wrong. Cap it at 16 to be safe
 */
-   if (size > 16) {
+   if (len >= sizeof(adev->serial)) {
DRM_WARN("FRU Serial Number is larger than 16 characters. This 
is likely a mistake");
-   size = 16;
+   len = sizeof(adev->serial) - 1;
}

The hardcoded '16' in comment/warning printing needs to be dropped as well?

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Jiansong Chen
Sent: Tuesday, May 25, 2021 2:42 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Jiansong (Simon) 
Subject: [PATCH] drm/amdgpu: refine amdgpu_fru_get_product_info

1. eliminate potential array index out of bounds.
2. return meaningful value for failure.

Signed-off-by: Jiansong Chen 
Change-Id: I9be36eb2e42ee46cd00464b0f2c35a4e4ea213e3
---
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 42 ++-
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 8f4a8f8d8146..39b6c6bfab45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -101,7 +101,8 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device 
*adev, uint32_t addrptr,  int amdgpu_fru_get_product_info(struct amdgpu_device 
*adev)  {
unsigned char buff[34];
-   int addrptr = 0, size = 0;
+   int addrptr, size;
+   int len;
 
if (!is_fru_eeprom_supported(adev))
return 0;
@@ -109,7 +110,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
/* If algo exists, it means that the i2c_adapter's initialized */
if (!adev->pm.smu_i2c.algo) {
DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
-   return 0;
+   return -ENODEV;
}
 
/* There's a lot of repetition here. This is due to the FRU having @@ 
-128,7 +129,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
/* Increment the addrptr by the size of the field, and 1 due to the @@ 
-138,43 +139,45 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU product name, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Product name should only be 32 characters. Any more,
 * and something could be wrong. Cap it at 32 to be safe
 */
-   if (size > 32) {
+   if (len >= sizeof(adev->product_name)) {
DRM_WARN("FRU Product Number is larger than 32 characters. This 
is likely a mistake");
-   size = 32;
+   len = sizeof(adev->product_name) - 1;
}
/* Start at 2 due to buff using fields 0 and 1 for the address */
-   memcpy(adev->product_name, [2], size);
-   adev->product_name[size] = '\0';
+   memcpy(adev->product_name, [2], len);
+   adev->product_name[len] = '\0';
 
addrptr += size + 1;
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU product number, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Product number should only be 16 characters. Any more,
 * and something could be wrong. Cap it at 16 to be safe
 */
-   if (size > 16) {
+   if (len >= sizeof(adev->product_number)) {
DRM_WARN("FRU Product Number is larger than 16 characters. This 
is likely a mistake");
-   size = 16;
+   len = sizeof(adev->product_number) - 1;
}
-   memcpy(adev->product_number, [2], size);
-   adev->product_number[size] = '\0';
+   memcpy(adev->product_number, [2], len);
+   adev->product_number[len] = '\0';
 
addrptr += size + 1;
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
 
if (size < 1) {
DRM_ERROR("Failed to read

RE: [PATCH] drm/amdgpu: refine amdgpu_fru_get_product_info

2021-05-25 Thread Chen, Jiansong (Simon)

[AMD Official Use Only]

Please ignore the patch, will resend after removing multiple assignments.

-Original Message-
From: Jiansong Chen 
Sent: Tuesday, May 25, 2021 2:17 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Jiansong (Simon) 
Subject: [PATCH] drm/amdgpu: refine amdgpu_fru_get_product_info

1. eliminate potential array index out of bounds.
2. return meaningful value for failure.

Signed-off-by: Jiansong Chen 
Change-Id: I9be36eb2e42ee46cd00464b0f2c35a4e4ea213e3
---
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 69 ++-
 1 file changed, 35 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 8f4a8f8d8146..5c2b4403a5b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -101,7 +101,8 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device 
*adev, uint32_t addrptr,  int amdgpu_fru_get_product_info(struct amdgpu_device 
*adev)  {
unsigned char buff[34];
-   int addrptr = 0, size = 0;
+   int addrptr, size;
+   int len;

if (!is_fru_eeprom_supported(adev))
return 0;
@@ -109,7 +110,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
/* If algo exists, it means that the i2c_adapter's initialized */
if (!adev->pm.smu_i2c.algo) {
DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
-   return 0;
+   return -ENODEV;
}

/* There's a lot of repetition here. This is due to the FRU having @@ 
-125,75 +126,75 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
 * and the language field, so just start from 0xb, manufacturer size
 */
addrptr = 0xb;
-   size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
-   if (size < 1) {
-   DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", size);
-   return size;
+   len = size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
+   if (len < 1) {
+   DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", len);
+   return -EINVAL;
}

/* Increment the addrptr by the size of the field, and 1 due to the
 * size field being 1 byte. This pattern continues below.
 */
addrptr += size + 1;
-   size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
-   if (size < 1) {
-   DRM_ERROR("Failed to read FRU product name, ret:%d", size);
-   return size;
+   len = size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
+   if (len < 1) {
+   DRM_ERROR("Failed to read FRU product name, ret:%d", len);
+   return -EINVAL;
}

/* Product name should only be 32 characters. Any more,
 * and something could be wrong. Cap it at 32 to be safe
 */
-   if (size > 32) {
+   if (len >= sizeof(adev->product_name)) {
DRM_WARN("FRU Product Number is larger than 32 characters. This 
is likely a mistake");
-   size = 32;
+   len = sizeof(adev->product_name) - 1;
}
/* Start at 2 due to buff using fields 0 and 1 for the address */
-   memcpy(adev->product_name, [2], size);
-   adev->product_name[size] = '\0';
+   memcpy(adev->product_name, [2], len);
+   adev->product_name[len] = '\0';

addrptr += size + 1;
-   size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
-   if (size < 1) {
-   DRM_ERROR("Failed to read FRU product number, ret:%d", size);
-   return size;
+   len = size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
+   if (len < 1) {
+   DRM_ERROR("Failed to read FRU product number, ret:%d", len);
+   return -EINVAL;
}

/* Product number should only be 16 characters. Any more,
 * and something could be wrong. Cap it at 16 to be safe
 */
-   if (size > 16) {
+   if (len >= sizeof(adev->product_number)) {
DRM_WARN("FRU Product Number is larger than 16 characters. This 
is likely a mistake");
-   size = 16;
+   len = sizeof(adev->product_number) - 1;
}
-   memcpy(adev->product_number, [2], size);
-   adev->product_number[size] = '\0';
+   memcpy(adev->product_number, [2], len);
+   adev->product_number[len] = '\0';

addrptr += size + 1;
-   size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
+   len = size = amdgpu_fru_read_eeprom(adev, addrptr, buff);

-   if (size < 1) {
-   DRM_ERROR("Failed to read FRU product version, ret:%d", size);
-   return size;
+   if (len < 1) {
+   D

RE: [PATCH] drm/amd/pm: Update PPTable struct for beige_goby

2021-05-20 Thread Chen, Jiansong (Simon)

[AMD Official Use Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Chengming Gui 
Sent: Thursday, May 20, 2021 3:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Gui, Jack ; Zhou1, Tao ; Chen, 
Jiansong (Simon) ; Zhang, Hawking 
; Feng, Kenneth 
Subject: [PATCH] drm/amd/pm: Update PPTable struct for beige_goby

Update PPTable structure since SMC#73.9/IFWI-XXX.013

Signed-off-by: Chengming Gui 
Reviewed-by: Tao Zhou 
Change-Id: I7f6a2dd85b367eb4ecbcfcd5141b1960a395ec24
---
 drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index 7a6d049e65e3..a1079256d318 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -1176,7 +1176,7 @@ typedef struct {
   uint16_t LedGpio;//GeneriA GPIO flag used to control the 
radeon LEDs
   uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control 
gfx power stages

-  uint32_t SkuReserved[16];
+  uint32_t SkuReserved[55];



--
2.17.1

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RE: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

2021-05-17 Thread Chen, Jiansong (Simon)

[AMD Official Use Only]

Does't the below code in gfx_v8_ring_emit_cntxcntl do almost the same thing as 
dropping the preamble ib. I cannot understand why bother to duplicate the 
optimization and cause a mess
In the common code.
/* set load_ce_ram if preamble presented */
if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
dw2 |= 0x1000;
} else {
/* still load_ce_ram if this is the first time preamble 
presented
 * although there is no context switch happens.
 */
if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
dw2 |= 0x1000;
}

-Original Message-
From: Christian König 
Sent: Monday, May 17, 2021 2:56 PM
To: Chen, Jiansong (Simon) ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

Am 17.05.21 um 08:51 schrieb Chen, Jiansong (Simon):
> [AMD Official Use Only]
>
> Doesn't  current solution always enable the optimization in a safe and more 
> clear way?

No, we also need this for gfx8 where gfxoff is currently not implemented.

Additional to that we mix common frontend handling into the backend with this 
approach.

But you could clean up the code in amdgpu_ib_schedule() quite a bit.

Regards,
Christian.

> 1. for gfx8/9/10 we use load_ce_ram in context_control to control the 
> optimization.
> 2. for gfx6/7, we directly drop the preamble ib.
>
> Regards,
> Jiansong
> -Original Message-
> From: Koenig, Christian 
> Sent: Monday, May 17, 2021 2:42 PM
> To: Chen, Jiansong (Simon) ;
> amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old
> GPUs
>
> Well NAK, as discussed checking the global flag is more flexible since it 
> will still enable the preamble drop when gfxoff is disabled.
>
> Christian.
>
> Am 17.05.21 um 06:39 schrieb Jiansong Chen:
>> The optimization is safe for old GPUs and can help performance.
>>
>> Signed-off-by: Jiansong Chen 
>> Change-Id: Id3b1250f1fe46dddbe8498894fb97e9753b7cafe
>> ---
>>drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++
>>drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++
>>2 files changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> index 3a8d52a54873..c915cc439484 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> @@ -1873,6 +1873,12 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring 
>> *ring,
>>amdgpu_ring_write(ring, 0);
>>}
>>
>> + /* drop the CE preamble IB for the same context */
>> + if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
>> + !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
>> + !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
>> + return;
>> +
>>if (ib->flags & AMDGPU_IB_FLAG_CE)
>>header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
>>else
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> index c35fdd2ef2d4..6d9ccae48024 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> @@ -2269,6 +2269,12 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct 
>> amdgpu_ring *ring,
>>amdgpu_ring_write(ring, 0);
>>}
>>
>> + /* drop the CE preamble IB for the same context */
>> + if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
>> + !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
>> + !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
>> + return;
>> +
>>if (ib->flags & AMDGPU_IB_FLAG_CE)
>>header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
>>else
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RE: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

2021-05-17 Thread Chen, Jiansong (Simon)

[AMD Official Use Only]

Doesn't  current solution always enable the optimization in a safe and more 
clear way?
1. for gfx8/9/10 we use load_ce_ram in context_control to control the 
optimization.
2. for gfx6/7, we directly drop the preamble ib.

Regards,
Jiansong
-Original Message-
From: Koenig, Christian 
Sent: Monday, May 17, 2021 2:42 PM
To: Chen, Jiansong (Simon) ; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

Well NAK, as discussed checking the global flag is more flexible since it will 
still enable the preamble drop when gfxoff is disabled.

Christian.

Am 17.05.21 um 06:39 schrieb Jiansong Chen:
> The optimization is safe for old GPUs and can help performance.
>
> Signed-off-by: Jiansong Chen 
> Change-Id: Id3b1250f1fe46dddbe8498894fb97e9753b7cafe
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++
>   2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 3a8d52a54873..c915cc439484 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1873,6 +1873,12 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring 
> *ring,
>   amdgpu_ring_write(ring, 0);
>   }
>
> + /* drop the CE preamble IB for the same context */
> + if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
> + !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
> + !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
> + return;
> +
>   if (ib->flags & AMDGPU_IB_FLAG_CE)
>   header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
>   else
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index c35fdd2ef2d4..6d9ccae48024 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -2269,6 +2269,12 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct 
> amdgpu_ring *ring,
>   amdgpu_ring_write(ring, 0);
>   }
>
> + /* drop the CE preamble IB for the same context */
> + if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
> + !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
> + !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
> + return;
> +
>   if (ib->flags & AMDGPU_IB_FLAG_CE)
>   header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
>   else

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RE: [PATCH] drm/amd/pm: enable ASPM by default

2021-05-11 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Better to make the commit msg more specific, eg. Change predicate accordingly 
since aspm is enabled by default.
Either way,  Reviewed-by: Jiansong Chen 

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Kenneth Feng
Sent: Tuesday, May 11, 2021 11:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth 
Subject: [PATCH] drm/amd/pm: enable ASPM by default

enable ASPM by default

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c 
index 82a380be8368..2fcfd893edc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -598,7 +598,7 @@ static void nv_pcie_gen3_enable(struct amdgpu_device *adev)

 static void nv_program_aspm(struct amdgpu_device *adev)  {
-   if (amdgpu_aspm != 1)
+   if (!amdgpu_aspm)
return;

if (!(adev->flags & AMD_IS_APU) &&
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 49ece2a7f9f0..4b660b2d1c22 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -817,7 +817,7 @@ static void soc15_pcie_gen3_enable(struct amdgpu_device 
*adev)

 static void soc15_program_aspm(struct amdgpu_device *adev)  {
-   if (amdgpu_aspm != 1)
+   if (!amdgpu_aspm)
return;

if (!(adev->flags & AMD_IS_APU) &&
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c 
index 735ebbd1148f..3d21c0799037 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1136,7 +1136,7 @@ static void vi_program_aspm(struct amdgpu_device *adev)
bool bL1SS = false;
bool bClkReqSupport = true;

-   if (amdgpu_aspm != 1)
+   if (!amdgpu_aspm)
return;

if (adev->flags & AMD_IS_APU ||
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index d2fd44b903ca..270b2b0b8e8a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -302,7 +302,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
if (smu->dc_controlled_by_gpio)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);

-   if (amdgpu_aspm == 1)
+   if (amdgpu_aspm)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);

return 0;
--
2.17.1

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RE: [PATCH] drm/amdgpu: Add graphics cache rinse packet for sdma 5.0

2021-04-29 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
I notice there is already similar logic in sdma_v5_0_ring_emit_ib, do we need 
remove it?

Regards,
Jiansong

@@ -410,6 +410,18 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring 
*ring,
unsigned vmid = AMDGPU_JOB_GET_VMID(job);
uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);

+   /* Invalidate L2, because if we don't do it, we might get stale cache
+* lines from previous IBs.
+*/
+   amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
+   amdgpu_ring_write(ring, 0);
+   amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
+SDMA_GCR_GL2_WB |
+SDMA_GCR_GLM_INV |
+SDMA_GCR_GLM_WB) << 16);
+   amdgpu_ring_write(ring, 0xff80);
+   amdgpu_ring_write(ring, 0x);
+

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, April 29, 2021 11:41 AM
To: Deucher, Alexander 
Cc: amd-gfx list 
Subject: Re: [PATCH] drm/amdgpu: Add graphics cache rinse packet for sdma 5.0

Ping?

On Tue, Apr 20, 2021 at 3:28 PM Alex Deucher  wrote:
>
> Add emit mem sync callback for sdma_v5_0
>
> In amdgpu sync object test, three threads created jobs to send GFX IB
> and SDMA IB in sequence. After the first GFX thread joined, sometimes
> the third thread will reuse the same physical page to store the SDMA
> IB. There will be a risk that SDMA will read GFX IB in the previous
> physical page. So it's better to flush the cache before commit sdma
> IB.
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 28
> ++
>  1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index 920fc6d4a127..d294ef6a625a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -437,6 +437,33 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring 
> *ring,
> amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));  }
>
> +/**
> + * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache
> +rinse
> + *
> + * @ring: amdgpu ring pointer
> + * @job: job to retrieve vmid from
> + * @ib: IB object to schedule
> + *
> + * flush the IB by graphics cache rinse.
> + */
> +static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring) {
> +uint32_t gcr_cntl =
> +   SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> +   SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | 
> SDMA_GCR_GLK_INV |
> +   SDMA_GCR_GLI_INV(1);
> +
> +   /* flush entire cache L0/L1/L2, this can be optimized by performance 
> requirement */
> +   amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
> +   amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
> +   amdgpu_ring_write(ring, 
> SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
> +   SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> +   amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
> +   SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl 
> >> 16));
> +   amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
> +   SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> +}
> +
>  /**
>   * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
>   *
> @@ -1643,6 +1670,7 @@ static const struct amdgpu_ring_funcs 
> sdma_v5_0_ring_funcs = {
> 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, 
> vm fence */
> .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
> .emit_ib = sdma_v5_0_ring_emit_ib,
> +   .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
> .emit_fence = sdma_v5_0_ring_emit_fence,
> .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
> .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
> --
> 2.30.2
>
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RE: [PATCH 6/6] drm/amdgpu: Fix driver unload issue

2021-03-30 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

I still wonder how the issue takes place? According to my humble knowledge in 
driver model, the reference count of the kobject
for the device will not reach zero when there is still some device mem access, 
and shutdown should not happen.

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Emily Deng
Sent: Tuesday, March 30, 2021 12:42 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily 
Subject: [PATCH 6/6] drm/amdgpu: Fix driver unload issue

During driver unloading, don't need to copy mem, or it will introduce some call 
trace, such as when sa_manager is freed, it will introduce warn call trace in 
amdgpu_sa_bo_new.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e00263bcc88b..f0546a489e0d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -317,6 +317,9 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 struct dma_fence *fence = NULL;
 int r = 0;

+if (adev->shutdown)
+return 0;
+
 if (!adev->mman.buffer_funcs_enabled) {
 DRM_ERROR("Trying to move memory with ring turned off.\n");
 return -EINVAL;
--
2.25.1

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RE: [PATCH] drm/amd/pm: fix Navi1x runtime resume failure V2

2021-03-18 Thread Chen, Jiansong (Simon)

We still need reserve "return 0", otherwise may trigger warning "not all 
control paths return a value".

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Chen, Guchun
Sent: Thursday, March 18, 2021 5:28 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Lazar, Lijo ; Quan, Evan 
Subject: RE: [PATCH] drm/amd/pm: fix Navi1x runtime resume failure V2

[AMD Public Use]

One comment inline. Other than this, the patch is:

Reviewed-by: Guchun Chen 

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Thursday, March 18, 2021 5:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Lazar, Lijo ; Quan, Evan 
Subject: [PATCH] drm/amd/pm: fix Navi1x runtime resume failure V2

The RLC was put into a wrong state on runtime suspend. Thus the RLC autoload 
will fail on the succeeding runtime resume. By adding an intermediate 
PPSMC_MSG_PrepareMp1ForUnload(some GC hard reset involved, designed for PnP), 
we can bring RLC back into the desired state.

V2: integrate INTERRUPTS_ENABLED flag clearing into current
mp1 state set routines

Change-Id: I4eb3d5d76068412a6ab228af7fe7f794e53c1eaa
Signed-off-by: Evan Quan 
Reviewed-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   |  9 --
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  7 +
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 28 +++
 .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c |  1 +
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 25 +
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 14 ++
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 14 ++
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 28 +++
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h|  3 ++
 9 files changed, 102 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 809f4cb738f4..ab6f4059630c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2160,9 +2160,12 @@ static int psp_load_smu_fw(struct psp_context *psp)
if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
return 0;
 
-
-   if (amdgpu_in_reset(adev) && ras && ras->supported &&
-   adev->asic_type == CHIP_ARCTURUS) {
+   if ((amdgpu_in_reset(adev) &&
+ras && ras->supported &&
+adev->asic_type == CHIP_ARCTURUS) ||
+(adev->in_runpm &&
+ adev->asic_type >= CHIP_NAVI10 &&
+ adev->asic_type <= CHIP_NAVI12)) {
ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
if (ret) {
DRM_WARN("Failed to set MP1 state prepare for 
reload\n"); diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 629a988b069d..21c3c149614c 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -836,6 +836,13 @@ struct pptable_funcs {
 */
int (*check_fw_status)(struct smu_context *smu);
 
+   /**
+* @set_mp1_state: put SMU into a correct state for comming
+* resume from runpm or gpu reset.
+*/
+   int (*set_mp1_state)(struct smu_context *smu,
+enum pp_mp1_state mp1_state);
+
/**
 * @setup_pptable: Initialize the power play table and populate it with
 * default values.
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index bae9016fedea..470ca4e5d4d7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1927,36 +1927,16 @@ int smu_set_mp1_state(void *handle,
  enum pp_mp1_state mp1_state)
 {
struct smu_context *smu = handle;
-   uint16_t msg;
-   int ret;
+   int ret = 0;
 
if (!smu->pm_enabled)
return -EOPNOTSUPP;
 
mutex_lock(>mutex);
 
-   switch (mp1_state) {
-   case PP_MP1_STATE_SHUTDOWN:
-   msg = SMU_MSG_PrepareMp1ForShutdown;
-   break;
-   case PP_MP1_STATE_UNLOAD:
-   msg = SMU_MSG_PrepareMp1ForUnload;
-   break;
-   case PP_MP1_STATE_RESET:
-   msg = SMU_MSG_PrepareMp1ForReset;
-   break;
-   case PP_MP1_STATE_NONE:
-   default:
-   mutex_unlock(>mutex);
-   return 0;
-   }
-
-   ret = smu_send_smc_msg(smu, msg, NULL);
-   /* some asics may not support those messages */
-   if (ret == -EINVAL)
-   ret = 0;
-   if (ret)
-   dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
+   if (smu->ppt_funcs &&
+   smu->ppt_funcs->set_mp1_state)
+   ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
 
mutex_unlock(>mutex);
 
diff --git

RE: [PATCH] drm/amdgpu: block hardware accessed by other threads when doing gpu recovery

2021-03-01 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

For all the "locked = likely(!amdgpu_in_recovery_thread(adev)) & !in_irq();",  
logical operator "&&" should be used,

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Dennis Li
Sent: Monday, March 1, 2021 7:12 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Kuehling, Felix ; Zhang, 
Hawking ; Koenig, Christian 
Cc: Li, Dennis 
Subject: [PATCH] drm/amdgpu: block hardware accessed by other threads when 
doing gpu recovery

When GPU recovery thread is doing GPU reset, it is unsafe that other threads 
access hardware concurrently, which could cause GPU reset randomly hang.

Signed-off-by: Dennis Li 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1624c2bc8285..c71d3bba5f69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1033,6 +1033,7 @@ struct amdgpu_device {
 atomic_t in_gpu_reset;
 enum pp_mp1_state   mp1_state;
 struct rw_semaphore reset_sem;
+struct thread_info *recovery_thread;
 struct amdgpu_doorbell_index doorbell_index;

 struct mutexnotifier_lock;
@@ -1385,4 +1386,13 @@ static inline int amdgpu_in_reset(struct amdgpu_device 
*adev)  {
 return atomic_read(>in_gpu_reset);  }
+
+static inline bool amdgpu_in_recovery_thread(struct amdgpu_device
+*adev) {
+if (unlikely(adev->recovery_thread != NULL) &&
+adev->recovery_thread == current_thread_info())
+return true;
+
+return false;
+}
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 71805dfd9e25..7c17a5468d43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -401,13 +401,22 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, 
uint32_t offset)
  */
 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t 
value)  {
+bool locked;
+
 if (adev->in_pci_err_recovery)
 return;

+locked = likely(!amdgpu_in_recovery_thread(adev)) & !in_irq();
+if (locked)
+down_read(>reset_sem);
+
 if (offset < adev->rmmio_size)
 writeb(value, adev->rmmio + offset);
 else
 BUG();
+
+if (locked)
+up_read(>reset_sem);
 }

 /**
@@ -424,15 +433,19 @@ void amdgpu_device_wreg(struct amdgpu_device *adev,
 uint32_t reg, uint32_t v,
 uint32_t acc_flags)
 {
+bool locked;
+
 if (adev->in_pci_err_recovery)
 return;

+locked = likely(!amdgpu_in_recovery_thread(adev)) & !in_irq();
+if (locked)
+down_read(>reset_sem);
+
 if ((reg * 4) < adev->rmmio_size) {
 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
-amdgpu_sriov_runtime(adev) &&
-down_read_trylock(>reset_sem)) {
+amdgpu_sriov_runtime(adev)) {
 amdgpu_kiq_wreg(adev, reg, v);
-up_read(>reset_sem);
 } else {
 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 }
@@ -440,6 +453,9 @@ void amdgpu_device_wreg(struct amdgpu_device *adev,
 adev->pcie_wreg(adev, reg * 4, v);
 }

+if (locked)
+up_read(>reset_sem);
+
 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);  }

@@ -451,9 +467,15 @@ void amdgpu_device_wreg(struct amdgpu_device *adev,  void 
amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
  uint32_t reg, uint32_t v)
 {
+bool locked;
+
 if (adev->in_pci_err_recovery)
 return;

+locked = likely(!amdgpu_in_recovery_thread(adev)) & !in_irq();
+if (locked)
+down_read(>reset_sem);
+
 if (amdgpu_sriov_fullaccess(adev) &&
 adev->gfx.rlc.funcs &&
 adev->gfx.rlc.funcs->is_rlcg_access_range) { @@ -462,6 +484,9 @@ void 
amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
 } else {
 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 }
+
+if (locked)
+up_read(>reset_sem);
 }

 /**
@@ -496,15 +521,24 @@ u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
  */
 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  {
+bool locked;
+
 if (adev->in_pci_err_recovery)
 return;

+locked = likely(!amdgpu_in_recovery_thread(adev)) & !in_irq();
+if (locked)
+down_read(>reset_sem);
+
 if ((reg * 4) < adev->rio_mem_size)
 iowrite32(v, adev->rio_mem + (reg * 4));
 else {
 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 }
+
+if (locked)
+up_read(>reset_sem);
 }

 /**
@@ -679,6 +713,11 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device 
*adev,
 unsigned long flags;
 void __iomem *pcie_index_offset;
 void __iomem *pcie_data_offset;
+bool locked;
+
+locked = likely(!amdgpu_in_recovery_thread(adev)) & !in_irq();
+if (locked)
+down_read(>reset_sem);

 spin_lock_irqsave(>pcie_idx_lock, flags);
 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; @@ -689,6 
+728,9 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
 writel(reg_data, pcie_data_offset);
 readl(pcie_data_offset);
 spin_unlock_irqrestore(>pcie_idx_lock, flags);
+
+if (locked)
+up_read(>reset_sem);
 }

 /**
@@ -708,6 +750,11 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device 
*adev,
 unsigned long flags;
 void __iomem *pcie_index_offset;

RE: [PATCH] drm/amdgpu: enable gpu recovery for dimgrey_cavefish

2021-02-07 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Sunday, February 7, 2021 4:52 PM
To: Chen, Jiansong (Simon) ; Gui, Jack 
; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: enable gpu recovery for dimgrey_cavefish

As dimgrey_cavefish driver is stable enough, set gpu recovery as default in HW 
hang for dimgrey_cavefish.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fbd57482bce5..4a7f6c9bcd0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4209,6 +4209,7 @@ bool amdgpu_device_should_recover_gpu(struct 
amdgpu_device *adev)
 case CHIP_NAVI12:
 case CHIP_SIENNA_CICHLID:
 case CHIP_NAVY_FLOUNDER:
+case CHIP_DIMGREY_CAVEFISH:
 break;
 default:
 goto disabled;
--
2.17.1

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RE: [PATCH 1/2] drm/amd/pm: fulfill the API for navi1x gfxoff state retrieving(V2)

2021-01-18 Thread Chen, Jiansong (Simon)

If it's just for dev usage, why don't use UMR tool instead?
~/tools$ sudo ./umr -r *.mp*.mmMP1_SMN_EXT_SCRATCH0
0x0040

-Original Message-
From: amd-gfx  On Behalf Of Quan, Evan
Sent: Monday, January 18, 2021 2:06 PM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Chen, Guchun 

Subject: RE: [PATCH 1/2] drm/amd/pm: fulfill the API for navi1x gfxoff state 
retrieving(V2)

Considering the gfxoff status is always in dynamic switch, it's absolutely 
right we will never have a reliable way to know the exact current gfxoff status.
The status we can see is always the one of last moment.
However, the case we want to cover(also the one we see mostly) is we know the 
asic/gfx is totally idle and we want to know whether the gfxoff kicks in as 
expected.
Under this scenario, this approach(gfxoff state reporting) will be greatly 
helpful and reliable(asic unlikely transit out of gfxoff state without stress 
in short period).
I believe that must be the reason why APU team decide to introduce this 
routine. And we dgpu team should follow up.

BR
Evan
-Original Message-
From: Lazar, Lijo  
Sent: Monday, January 18, 2021 12:31 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan 
; Chen, Guchun 
Subject: RE: [PATCH 1/2] drm/amd/pm: fulfill the API for navi1x gfxoff state 
retrieving(V2)

[AMD Public Use]

This is not guaranteed to work reliably. By the time driver fetches and reports 
say status 0 (in GFXOFF), there could be a doorbell interrupt which changes the 
status to 1 (Transition out of GFX State).

If there is no requirement to report the instantaneous status, better to avoid 
it.

Thanks,
Lijo

-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Monday, January 18, 2021 7:25 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan 
; Chen, Guchun 
Subject: [PATCH 1/2] drm/amd/pm: fulfill the API for navi1x gfxoff state 
retrieving(V2)

Support Navi1x gfxoff state retrieving.

V2: some cosmetic fixes

Change-Id: I57aa506b82dc122bbead708c580a4720e536cfce
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  2 ++
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  1 +
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 22 +++
 3 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 102a0cf12d7a..4d346f289ed8 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -287,5 +287,7 @@ int smu_v11_0_deep_sleep_control(struct smu_context *smu,
 
 void smu_v11_0_interrupt_work(struct smu_context *smu);
 
+uint32_t smu_v11_0_get_gfxoff_status(struct smu_context *smu);
+
 #endif
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 7ebf9588983f..93a3b6b60c8f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2482,6 +2482,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_fan_parameters = navi10_get_fan_parameters,
.post_init = navi10_post_smu_init,
.interrupt_work = smu_v11_0_interrupt_work,
+   .get_gfx_off_status = smu_v11_0_get_gfxoff_status,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu) diff --git 
a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 147efe12973c..730a4880af08 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -2127,3 +2127,25 @@ int smu_v11_0_deep_sleep_control(struct smu_context *smu,
 
return ret;
 }
+
+/**
+ * smu_v11_0_get_gfxoff_status - get gfxoff status
+ *
+ * @smu: smu_context pointer
+ *
+ * This function will be used to get gfxoff status
+ *
+ * Returns 0=GFXOFF(default).
+ * Returns 1=Transition out of GFX State.
+ * Returns 2=Not in GFXOFF.
+ * Returns 3=Transition into GFXOFF.
+ */
+uint32_t smu_v11_0_get_gfxoff_status(struct smu_context *smu) {
+   struct amdgpu_device *adev = smu->adev;
+   uint32_t reg;
+
+   reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
+
+   return reg & 0x3;
+}
--
2.29.0

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RE: [PATCH 1/2] drm/amd/pm: fulfill the API for navi1x gfxoff state retrieving

2021-01-15 Thread Chen, Jiansong (Simon)

[AMD Public Use]

Can you help explain why we need introduce such a callback?  Seems it has 
presupposed pmfw's internal
Implementation.

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Friday, January 15, 2021 5:34 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan 

Subject: [PATCH 1/2] drm/amd/pm: fulfill the API for navi1x gfxoff state 
retrieving

Support Navi1x gfxoff state retrieving.

Change-Id: I57aa506b82dc122bbead708c580a4720e536cfce
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  2 ++
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  1 +
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 24 +++
 3 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 13de692a4213..2857f1bf4e9a 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -287,5 +287,7 @@ int smu_v11_0_deep_sleep_control(struct smu_context *smu,

 void smu_v11_0_interrupt_work(struct smu_context *smu);

+uint32_t smu_v11_0_get_gfxoff_status(struct smu_context *smu);
+
 #endif
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 7ebf9588983f..93a3b6b60c8f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2482,6 +2482,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
 .get_fan_parameters = navi10_get_fan_parameters,
 .post_init = navi10_post_smu_init,
 .interrupt_work = smu_v11_0_interrupt_work,
+.get_gfx_off_status = smu_v11_0_get_gfxoff_status,
 };

 void navi10_set_ppt_funcs(struct smu_context *smu) diff --git 
a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 147efe12973c..50566c613971 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -2127,3 +2127,27 @@ int smu_v11_0_deep_sleep_control(struct smu_context *smu,

 return ret;
 }
+
+/**
+ * smu_v11_0_get_gfxoff_status - get gfxoff status
+ *
+ * @smu: amdgpu_device pointer
+ *
+ * This function will be used to get gfxoff status
+ *
+ * Returns 0=GFXOFF(default).
+ * Returns 1=Transition out of GFX State.
+ * Returns 2=Not in GFXOFF.
+ * Returns 3=Transition into GFXOFF.
+ */
+uint32_t smu_v11_0_get_gfxoff_status(struct smu_context *smu) {
+struct amdgpu_device *adev = smu->adev;
+uint32_t gfxOff_Status = 0;
+uint32_t reg;
+
+reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0);
+gfxOff_Status = reg & 0x3;
+
+return gfxOff_Status;
+}
--
2.29.0

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RE: [PATCH] drm/amd/display: fix the system memory page fault because of copy overflow

2021-01-15 Thread Chen, Jiansong (Simon)

[AMD Public Use]

Hi Rui,
Seems the change has violated the kernel coding style, please help check.
https://www.kernel.org/doc/html/latest/process/coding-style.html

Allocating memory
..
The preferred form for passing a size of a struct is the following:

p = kmalloc(sizeof(*p), ...);
The alternative form where struct name is spelled out hurts readability and 
introduces an opportunity for a bug when the pointer variable type is changed 
but the corresponding sizeof that is passed to a memory allocator is not.

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Huang Rui
Sent: Saturday, January 16, 2021 2:47 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Su, Jinzhou (Joe) 
; Huang, Ray ; Lee Jones 
; Zhu, Changfeng 
Subject: [PATCH] drm/amd/display: fix the system memory page fault because of 
copy overflow

The buffer is allocated with the size of pointer and copy with the size of data 
structure. Then trigger the system memory page fault. Use the orignal data 
structure to get the object size.

Fixes: a8e30005b drm/amd/display/dc/core/dc_link: Move some local data from the 
stack to the heap

Signed-off-by: Huang Rui 
Cc: Lee Jones 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 69573d67056d..73178978ae74 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1380,7 +1380,7 @@ static bool dc_link_construct(struct dc_link *link,

 DC_LOGGER_INIT(dc_ctx->logger);

-info = kzalloc(sizeof(info), GFP_KERNEL);
+info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
 if (!info)
 goto create_fail;

@@ -1545,7 +1545,7 @@ static bool dc_link_construct(struct dc_link *link,
 }

 if (bios->integrated_info)
-memcpy(info, bios->integrated_info, sizeof(*info));
+memcpy(info, bios->integrated_info, sizeof(struct integrated_info));

 /* Look for channel mapping corresponding to connector and device tag */
 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
--
2.25.1

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RE: [PATCH] drm/amdgpu: enable gpu recovery for navy_flounder

2021-01-11 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Hi Paul,
We just enable gpu recovery when the feature is stable enough for 
navy_flounder.  And you can use debugfs interface to perform
a manual GPU reset. Here is more detail 
https://github.com/RadeonOpenCompute/ROCm/issues/616. Thanks!

Regards,
Jiansong
-Original Message-
From: Paul Menzel 
Sent: Monday, January 11, 2021 7:58 PM
To: Chen, Jiansong (Simon) 
Cc: Zhou1, Tao ; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: enable gpu recovery for navy_flounder

Dear Jiansong,


Am 11.01.21 um 10:49 schrieb Jiansong Chen:
> Enable gpu recovery for navy_flounder by default to trigger reset once
> needed.

[…]

Why was it disabled before? Were some bugs fixed, that it works now?

How did you test this? Is there a command to “crash“ the GPU, so it can be 
recovered?

Please extend the commit message accordingly.


Kind regards,

Paul
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RE: [PATCH] drm/amdgpu: correct releasing the same sdma fw repeatedly

2020-12-30 Thread Chen, Jiansong (Simon)

Ok, I will send another patch.

Regards,
Jiansong
-Original Message-
From: Zhang, Hawking  
Sent: Wednesday, December 30, 2020 6:02 PM
To: Chen, Jiansong (Simon) ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Chen, Jiansong (Simon) 

Subject: RE: [PATCH] drm/amdgpu: correct releasing the same sdma fw repeatedly

[AMD Public Use]

Shall we ignore this patch and wait for your latest fixes that remove the asic 
type check for sdma_v5_2.

I agree with you that should be more reasonable approach.

Regards,
Hawking

-Original Message-
From: Jiansong Chen  
Sent: Wednesday, December 30, 2020 17:23
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Zhang, Hawking ; 
Chen, Jiansong (Simon) 
Subject: [PATCH] drm/amdgpu: correct releasing the same sdma fw repeatedly

Same as sienna_cichlid, dimgrey_cavefish and navy_flounder reuse sdma0 fw for 
other instances, so free it only once.

Signed-off-by: Jiansong Chen 
Change-Id: I9dda4a9b73e20243ee48f54d8f0c7593d7e7354b
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index f1ba36a094da..6ac314c8be32 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -125,7 +125,8 @@ static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device 
*adev)
release_firmware(adev->sdma.instance[i].fw);
adev->sdma.instance[i].fw = NULL;
 
-   if (adev->asic_type == CHIP_SIENNA_CICHLID)
+   if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
+   adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
break;
}
 
--
2.25.1
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RE: [PATCH] drm/amdgpu: fix a memory protection fault when remove amdgpu device

2020-12-29 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

-Original Message-
From: amd-gfx  On Behalf Of Dennis Li
Sent: Wednesday, December 30, 2020 2:46 PM
To: amd-gfx@lists.freedesktop.org; Clements, John ; 
Zhang, Hawking ; Koenig, Christian 

Cc: Li, Dennis 
Subject: [PATCH] drm/amdgpu: fix a memory protection fault when remove amdgpu 
device

ASD and TA share the same firmware in SIENNA_CICHLID and only TA firmware is 
requested during boot, so only need release TA firmware when remove device.

[   83.877150] general protection fault, probably for non-canonical address 
0x1269f97e6ed04095:  [#1] SMP PTI
[   83.888076] CPU: 0 PID: 1312 Comm: modprobe Tainted: GW  OE 
5.9.0-rc5-deli-amd-vangogh-0.0.6.6-114-gdd99d5669a96-dirty #2
[   83.901160] Hardware name: System manufacturer System Product Name/TUF 
Z370-PLUS GAMING II, BIOS 0411 09/21/2018
[   83.912353] RIP: 0010:free_fw_priv+0xc/0x120
[   83.917531] Code: e8 99 cd b0 ff b8 a1 ff ff ff eb 9f 4c 89 f7 e8 8a cd b0 
ff b8 f4 ff ff ff eb 90 0f 1f 00 0f 1f 44 00 00 55 48 89 e5 41 54 53 <4c> 8b 67 
18 48 89 fb 4c 89 e7 e8 45 94 41 00 b8 ff ff ff ff f0 0f
[   83.937576] RSP: 0018:bc34c13a3ce0 EFLAGS: 00010206
[   83.943699] RAX: bb681850 RBX: a047f117eb60 RCX: 80800055
[   83.951879] RDX: bc34c1d5f000 RSI: 80800055 RDI: 1269f97e6ed04095
[   83.959955] RBP: bc34c13a3cf0 R08:  R09: 0001
[   83.968107] R10: bc34c13a3cc8 R11: ff00 R12: a047d6b23378
[   83.976166] R13: a047d6b23338 R14: a047d6b240c8 R15: 
[   83.984295] FS:  7f74f6712540() GS:a047fbe0() 
knlGS:
[   83.993323] CS:  0010 DS:  ES:  CR0: 80050033
[   84.56] CR2: 556a1cca4e18 CR3: 00021faa8004 CR4: 003706f0
[   84.008128] DR0:  DR1:  DR2: 
[   84.016155] DR3:  DR6: fffe0ff0 DR7: 0400
[   84.024174] Call Trace:
[   84.027514]  release_firmware.part.11+0x4b/0x70
[   84.033017]  release_firmware+0x13/0x20
[   84.037803]  psp_sw_fini+0x77/0xb0 [amdgpu]
[   84.042857]  amdgpu_device_fini+0x38c/0x5d0 [amdgpu]
[   84.048815]  amdgpu_driver_unload_kms+0x43/0x70 [amdgpu]
[   84.055055]  drm_dev_unregister+0x73/0xb0 [drm]
[   84.060499]  drm_dev_unplug+0x28/0x30 [drm]
[   84.065598]  amdgpu_dev_uninit+0x1b/0x40 [amdgpu]
[   84.071223]  amdgpu_pci_remove+0x4e/0x70 [amdgpu]
[   84.076835]  pci_device_remove+0x3e/0xc0
[   84.081609]  device_release_driver_internal+0xfb/0x1c0
[   84.087558]  driver_detach+0x4d/0xa0
[   84.092041]  bus_remove_driver+0x5f/0xe0
[   84.096854]  driver_unregister+0x2f/0x50
[   84.101594]  pci_unregister_driver+0x22/0xa0
[   84.106806]  amdgpu_exit+0x15/0x2b [amdgpu]

Signed-off-by: Dennis Li 
Change-Id: Icc981a421499dff844855d5a662e91d1730c2754

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index eb19ae734396..b44b46dd60f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -564,7 +564,7 @@ static int psp_asd_load(struct psp_context *psp)
  * add workaround to bypass it for sriov now.
  * TODO: add version check to make it common
  */
-if (amdgpu_sriov_vf(psp->adev) || !psp->asd_fw)
+if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size)
 return 0;

 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); @@ -2779,11 
+2779,10 @@ static int parse_ta_bin_descriptor(struct psp_context *psp,
switch (desc->fw_type) {
 case TA_FW_TYPE_PSP_ASD:
-psp->asd_fw_version   = le32_to_cpu(desc->fw_version);
+psp->asd_fw_version= le32_to_cpu(desc->fw_version);
 psp->asd_feature_version   = le32_to_cpu(desc->fw_version);
-psp->asd_ucode_size   = le32_to_cpu(desc->size_bytes);
+psp->asd_ucode_size= le32_to_cpu(desc->size_bytes);

Seems the above 2 changes are irrelevant.

 psp->asd_start_addr= ucode_start_addr;
-psp->asd_fw= psp->ta_fw;
 break;
 case TA_FW_TYPE_PSP_XGMI:
 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
--
2.17.1

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RE: [PATCH] drm/amdgpu: print mmhub client name for dimgrey_cavefish

2020-12-15 Thread Chen, Jiansong (Simon)

[AMD Public Use]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Wednesday, December 16, 2020 11:40 AM
To: Chen, Jiansong (Simon) ; Gui, Jack 
; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: print mmhub client name for dimgrey_cavefish

This makes it easier to debug what block is causing the fault, same as 
sienna_cichlid.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 092ff2c43658..f107385faba2 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -136,6 +136,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct 
amdgpu_device *adev,
 break;
 case CHIP_SIENNA_CICHLID:
 case CHIP_NAVY_FLOUNDER:
+case CHIP_DIMGREY_CAVEFISH:
 mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];
 break;
 default:
--
2.17.1

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RE: [PATCH] drm/amdgpu: set mode1 reset as default for dimgrey_cavefish

2020-12-15 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Tuesday, December 15, 2020 6:23 PM
To: Chen, Jiansong (Simon) ; Gui, Jack 
; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: set mode1 reset as default for dimgrey_cavefish

Use mode1 reset for dimgrey_cavefish by default.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c 
index ac02dd707c44..6bee3677394a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -362,6 +362,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
 switch (adev->asic_type) {
 case CHIP_SIENNA_CICHLID:
 case CHIP_NAVY_FLOUNDER:
+case CHIP_DIMGREY_CAVEFISH:
 return AMD_RESET_METHOD_MODE1;
 default:
 if (smu_baco_is_support(smu))
--
2.17.1

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Recall: [PATCH 5/5] drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port workaround

2020-12-09 Thread Chen, Jiansong (Simon)

Chen, Jiansong (Simon) would like to recall the message, "[PATCH 5/5] 
drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port workaround".
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RE: [PATCH 5/5] drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port workaround

2020-12-09 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Hi Evan,
Besides Navi21, other Navi2x Asics reuse sienna_cichlid_ppt.c and the 
callbacks, have you taken their user cases into consideration?
Thanks!

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Wednesday, December 9, 2020 12:19 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo 
; Quan, Evan 
Subject: [PATCH 5/5] drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port 
workaround

Fulfill the 2nd usb2.0 port workaround for sienna cichlid.

Change-Id: Id5a89a468787846ed0050b56cd318a9574185567
Signed-off-by: Evan Quan 
---
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 38 ++-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 47d4f92d5ead..74cf027e4a41 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -3247,6 +3247,42 @@ static int sienna_cichlid_gpo_control(struct smu_context 
*smu,

 return ret;
 }
+
+static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context
+*smu) {
+uint32_t smu_version;
+int ret = 0;
+
+ret = smu_cmn_get_smc_version(smu, NULL, _version);
+if (ret)
+return ret;
+
+/*
+ * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
+ * onwards PMFWs.
+ */
+if (smu_version < 0x003A2D00)
+return 0;
+
+return smu_cmn_send_smc_msg_with_param(smu,
+   SMU_MSG_Enable2ndUSB20Port,
+   smu->smu_table.boot_values.firmware_caps & 
ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
+   1 : 0,
+   NULL);
+}
+
+static int sienna_cichlid_system_features_control(struct smu_context *smu,
+  bool en)
+{
+int ret = 0;
+
+ret = sienna_cichlid_notify_2nd_usb20_port(smu);
+if (ret)
+return ret;
+
+return smu_v11_0_system_features_control(smu, en); }
+
 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
@@ -3287,7 +3323,7 @@ static const struct pptable_funcs 
sienna_cichlid_ppt_funcs = {
 .set_driver_table_location = smu_v11_0_set_driver_table_location,
 .set_tool_table_location = smu_v11_0_set_tool_table_location,
 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
-.system_features_control = smu_v11_0_system_features_control,
+.system_features_control = sienna_cichlid_system_features_control,
 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
 .send_smc_msg = smu_cmn_send_smc_msg,
 .init_display_count = NULL,
--
2.29.0

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RE: [PATCH] drm/amd/pm: update driver if version for dimgrey_cavefish

2020-12-07 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Monday, December 7, 2020 2:06 PM
To: Chen, Jiansong (Simon) ; Gui, Jack 
; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amd/pm: update driver if version for dimgrey_cavefish

Per PMFW 59.16.0.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index c1cb472f8f0f..e5aa0725147c 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -33,7 +33,7 @@
 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3B  #define 
SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xC  #define 
SMU11_DRIVER_IF_VERSION_VANGOGH 0x02 -#define 
SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xD
+#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF

 /* MP Apertures */
 #define MP0_Public0x0380
--
2.17.1

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RE: [PATCH] drm/amdgpu: update GC golden setting for dimgrey_cavefish

2020-11-26 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Friday, November 27, 2020 12:28 PM
To: Chen, Jiansong (Simon) ; Gui, Jack 
; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: update GC golden setting for dimgrey_cavefish

Update GC golden setting for dimgrey_cavefish.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 841d39eb62d9..ffbda6680a68 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3266,6 +3266,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_vangogh[] =

 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =  {
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x7800,
+0x78000100),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x3000, 0x3100),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e00, 0x7e000100),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007, 0xc000),
--
2.17.1

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RE: [PATCH] drm/amd/pm: support runtime PPTable update for dimgrey_cavefish

2020-11-17 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Tuesday, November 17, 2020 3:33 PM
To: Chen, Jiansong (Simon) ; Gui, Jack 
; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amd/pm: support runtime PPTable update for dimgrey_cavefish

There is no need to reset DPM for PPTable uploading on dimgrey_cavefish and 
PMFW can handle it, same as navy_flounder.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 1904df5a3e20..8e3e7a5bbffe 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1183,7 +1183,7 @@ static int smu_disable_dpms(struct smu_context *smu)
  */
 if (smu->uploading_custom_pp_table &&
 (adev->asic_type >= CHIP_NAVI10) &&
-(adev->asic_type <= CHIP_NAVY_FLOUNDER))
+(adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
 return 0;

 /*
--
2.17.1

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RE: [PATCH] drm/amd/pm: retire dimgrey_cavefish hardcode for the use of soft PTable

2020-11-16 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

In the subject Ptable->pptable, except that,
Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Tuesday, November 17, 2020 11:32 AM
To: Chen, Jiansong (Simon) ; Gui, Jack 
; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amd/pm: retire dimgrey_cavefish hardcode for the use of 
soft PTable

The PPTable provided by VBIOS can be used.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index b23311096467..d5fa0d9dd7eb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -339,8 +339,7 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 version_major = le16_to_cpu(hdr->header.header_version_major);
 version_minor = le16_to_cpu(hdr->header.header_version_minor);
-if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||
-adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
+if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 dev_info(adev->dev, "use driver provided pptable %d\n", 
smu->smu_table.boot_values.pp_table_id);
 switch (version_minor) {
 case 0:
--
2.17.1

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RE: [PATCH] drm/amd/pm: update driver if version for dimgrey_cavefish

2020-11-13 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Friday, November 13, 2020 4:51 PM
To: Chen, Jiansong (Simon) ; Gui, Jack 
; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amd/pm: update driver if version for dimgrey_cavefish

Per PMFW 59.13.0.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 5ad693312187..41bc919dc9f4 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -33,7 +33,7 @@
 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A  #define 
SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5  #define 
SMU11_DRIVER_IF_VERSION_VANGOGH 0x02 -#define 
SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xB
+#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xD

 /* MP Apertures */
 #define MP0_Public0x0380
--
2.17.1

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RE: [PATCH] drm/amdgpu: update gfx golden setting for dimgrey_cavefish

2020-11-09 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Tuesday, November 10, 2020 2:30 PM
To: Chen, Jiansong (Simon) ; Gui, Jack 
; Zhang, Hawking ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: update gfx golden setting for dimgrey_cavefish

Set LDS_CONFIG to 0x20 on dimgrey_cavefish to fix GPU hang.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8c3bad3dfc01..e068133aec71 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3286,7 +3286,8 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_4[] =
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 
0x),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 
0x),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x0103, 0x0103),
-SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a0, 0x00a0)
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a0, 0x00a0),
+SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x0020, 0x0020)
 };

 #define DEFAULT_SH_MEM_CONFIG \
--
2.17.1

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RE: [PATCH v2] drm/amdgpu: disable gfxoff if VCN is busy

2020-10-30 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Please ignore the change.

-Original Message-
From: Jiansong Chen 
Sent: Friday, October 30, 2020 10:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhu, James ; 
Liu, Leo ; Zhou1, Tao ; Chen, Jiansong 
(Simon) 
Subject: [PATCH v2] drm/amdgpu: disable gfxoff if VCN is busy

Toggle on/off gfxoff during video playback to fix gpu hang.

v2: change sequence to be more compatible with original code.

Signed-off-by: Jiansong Chen 
Change-Id: I5b938c446884268c2cda0801121a53da980e603a
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 277a8435dd06..ef0878e848de 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -358,6 +358,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work)
 }

 if (!fences && !atomic_read(>vcn.total_submission_cnt)) {
+amdgpu_gfx_off_ctrl(adev, true);
 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
 } else {
@@ -370,7 +371,9 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 struct amdgpu_device *adev = ring->adev;

 atomic_inc(>vcn.total_submission_cnt);
-cancel_delayed_work_sync(>vcn.idle_work);
+
+if (!cancel_delayed_work_sync(>vcn.idle_work);)
+amdgpu_gfx_off_ctrl(adev, false);

 mutex_lock(>vcn.vcn_pg_lock);
 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
--
2.25.1

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RE: [PATCH] drm/amdgpu: disable gfxoff if VCN is busy

2020-10-30 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Hi James,
Thanks for your input, v2 patch is sent out.

Regards,
Jiansong
-Original Message-
From: Zhu, James 
Sent: Friday, October 30, 2020 9:06 PM
To: Chen, Jiansong (Simon) ; 
amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhu, James ; 
Liu, Leo ; Zhou1, Tao 
Subject: Re: [PATCH] drm/amdgpu: disable gfxoff if VCN is busy

Hi Jiansong

Pls check inline.

thanks!

James

On 2020-10-30 7:37 a.m., Jiansong Chen wrote:
> Toggle on/off gfxoff during video playback to fix gpu hang.
[JZ] It is a workaround, not a fix. Also Arcturus needn't this WA.
> Signed-off-by: Jiansong Chen 
> Change-Id: I5b938c446884268c2cda0801121a53da980e603a
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 10 +++---
>   1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 277a8435dd06..444b89413232 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -358,6 +358,7 @@ static void amdgpu_vcn_idle_work_handler(struct 
> work_struct *work)
>   }
>
>   if (!fences && !atomic_read(>vcn.total_submission_cnt)) {
> +amdgpu_gfx_off_ctrl(adev, true);
>   amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
>  AMD_PG_STATE_GATE);
>   } else {
> @@ -368,13 +369,16 @@ static void amdgpu_vcn_idle_work_handler(struct 
> work_struct *work)
>   void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
>   {
>   struct amdgpu_device *adev = ring->adev;
> +bool set_clocks = !cancel_delayed_work_sync(>vcn.idle_work);
>
>   atomic_inc(>vcn.total_submission_cnt);
> -cancel_delayed_work_sync(>vcn.idle_work);
>
>   mutex_lock(>vcn.vcn_pg_lock);
> -amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
> -   AMD_PG_STATE_UNGATE);
> +if (set_clocks) {
> +amdgpu_gfx_off_ctrl(adev, false);

[JZ] Move the above two lines before mutex_lock(>vcn.vcn_pg_lock);

Since it may cause S3 test failure.

> +amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
> +AMD_PG_STATE_UNGATE);
> +}
>
>   if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){
>   struct dpg_pause_state new_state;
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RE: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

2020-09-21 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: amd-gfx  On Behalf Of Likun Gao
Sent: Tuesday, September 22, 2020 11:17 AM
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun ; Feng, Kenneth ; 
Zhang, Hawking 
Subject: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

From: Likun Gao 

Update driver if file for sienna cichlid.

Signed-off-by: Likun Gao 
Change-Id: I295edda90d156c4cea742e62fab696afb6cd1366
---
 drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h | 4 ++--
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index 11a6cf96fe0c..1275246769d9 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x37
+#define SMU11_DRIVER_IF_VERSION 0x39

 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 6

@@ -962,7 +962,7 @@ typedef struct {
   uint8_tFanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
   uint8_tFanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
   uint16_t   MaxOpTemp;// Degree Celcius
-  uint16_t   Padding_16[1];
+  int16_tVddGfxOffset; // in mV
   uint8_tFanZeroRpmEnable;
   uint8_tFanZeroRpmStopTemp;
   uint8_tFanMode;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 7ae83df83edb..03198d214bba 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36  #define 
SMU11_DRIVER_IF_VERSION_NV12 0x36  #define SMU11_DRIVER_IF_VERSION_NV14 0x36 
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x37
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5

 /* MP Apertures */
--
2.25.1

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RE: [PATCH] drm/amd/pm: support runtime pptable update for sienna_cichlid etc.

2020-09-14 Thread Chen, Jiansong (Simon)

It makes nonsense to call gfxoff  when smu failure has happened.

Regards,
Jiansong
-Original Message-
From: Chen, Guchun  
Sent: Monday, September 14, 2020 4:14 PM
To: Chen, Jiansong (Simon) ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Feng, Kenneth ; Quan, 
Evan ; Chen, Jiansong (Simon) 
Subject: RE: [PATCH] drm/amd/pm: support runtime pptable update for 
sienna_cichlid etc.

[AMD Public Use]

ret = smu_late_init(adev);
+   if (ret)
+   return ret;

One counter leak happens? It needs to call amdgpu_gfx_off_ctrl(smu->adev, true) 
before returning?

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Jiansong Chen
Sent: Monday, September 14, 2020 4:10 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Feng, Kenneth ; Quan, 
Evan ; Chen, Jiansong (Simon) 
Subject: [PATCH] drm/amd/pm: support runtime pptable update for sienna_cichlid 
etc.

This avoids smu issue when enabling runtime pptable update for sienna_cichlid 
and so on. Runtime pptable udpate is needed for test and debug purpose.

Signed-off-by: Jiansong Chen 
Change-Id: I70b704ab4d6efd169f579c392e5dbc2737dc1fb2
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7a55ece1f124..7618f9972b8c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1129,7 +1129,7 @@ static int smu_disable_dpms(struct smu_context *smu)
 */
if (smu->uploading_custom_pp_table &&
(adev->asic_type >= CHIP_NAVI10) &&
-   (adev->asic_type <= CHIP_NAVI12))
+   (adev->asic_type <= CHIP_NAVY_FLOUNDER))
return 0;
 
/*
@@ -1214,7 +1214,9 @@ static int smu_hw_fini(void *handle)  int 
smu_reset(struct smu_context *smu)  {
struct amdgpu_device *adev = smu->adev;
-   int ret = 0;
+   int ret;
+
+   amdgpu_gfx_off_ctrl(smu->adev, false);
 
ret = smu_hw_fini(adev);
if (ret)
@@ -1225,8 +1227,12 @@ int smu_reset(struct smu_context *smu)
return ret;
 
ret = smu_late_init(adev);
+   if (ret)
+   return ret;
 
-   return ret;
+   amdgpu_gfx_off_ctrl(smu->adev, true);
+
+   return 0;
 }
 
 static int smu_suspend(void *handle)
--
2.25.1

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RE: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

2020-09-10 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Gao, Likun 
Sent: Thursday, September 10, 2020 4:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Chen, Jiansong (Simon) ; Gao, 
Likun 
Subject: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

From: Likun Gao 

Update drive if file for sienna_cichlid.

Signed-off-by: Likun Gao 
Change-Id: I53e5210acb760901622cd50aaf81193e9699feba
---
 .../pm/inc/smu11_driver_if_sienna_cichlid.h   | 20 ++-
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  2 +-
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  5 -
 3 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index 5ef9c92f57c4..11a6cf96fe0c 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x35
+#define SMU11_DRIVER_IF_VERSION 0x37

-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 6

 #define NUM_GFXCLK_DPM_LEVELS  16
 #define NUM_SMNCLK_DPM_LEVELS  2
@@ -169,7 +169,7 @@ typedef enum {
 #define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN   0x0200
 #define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x0400
 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK   0x0800
-#define DPM_OVERRIDE_ENABLE_FAST_FCLK_TIMER  0x1000
+#define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x1000
 #define DPM_OVERRIDE_DISABLE_VCN_PG  0x2000
 #define DPM_OVERRIDE_DISABLE_FMAX_VMAX   0x4000

@@ -793,8 +793,18 @@ typedef struct {

   // SECTION: Sku Reserved
   uint8_t  CustomerVariant;
-  uint8_t  Spare[3];
-  uint32_t SkuReserved[14];
+
+  //VC BTC parameters are only applicable to VDD_GFX domain
+  uint8_t  VcBtcEnabled;
+  uint16_t VcBtcVminT0; // T0_VMIN
+  uint16_t VcBtcFixedVminAgingOffset;   // FIXED_VMIN_AGING_OFFSET
+  uint16_t VcBtcVmin2PsmDegrationGb;// VMIN_TO_PSM_DEGRADATION_GB
+  uint32_t VcBtcPsmA;   // A_PSM
+  uint32_t VcBtcPsmB;   // B_PSM
+  uint32_t VcBtcVminA;  // A_VMIN
+  uint32_t VcBtcVminB;  // B_VMIN
+
+  uint32_t SkuReserved[9];


   // MAJOR SECTION: BOARD PARAMETERS
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 2a3f1ee4a50b..9dfc1c87b6dd 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36  #define 
SMU11_DRIVER_IF_VERSION_NV12 0x36  #define SMU11_DRIVER_IF_VERSION_NV14 0x36 
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x35
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x37
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x4

 /* MP Apertures */
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index b67931fd64b4..194abaca6948 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2295,11 +2295,6 @@ static void sienna_cichlid_dump_pptable(struct 
smu_context *smu)
 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
 dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
-dev_info(smu->adev->dev, "SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
-dev_info(smu->adev->dev, "SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
-dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
-dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
-dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);

 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
--
2.25.1

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RE: [PATCH] drm/amdgpu: add asd fw check before loading asd

2020-08-24 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Zhou1, Tao 
Sent: Tuesday, August 25, 2020 11:20 AM
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; 
Chen, Jiansong (Simon) ; Gui, Jack 
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: add asd fw check before loading asd

asd is not ready for some ASICs in early stage, and psp->asd_fw is more generic 
than ASIC name in the check

Signed-off-by: Tao Zhou 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c22fb0194df7..d6c38e24f130 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -522,8 +522,7 @@ static int psp_asd_load(struct psp_context *psp)
  * add workaround to bypass it for sriov now.
  * TODO: add version check to make it common
  */
-if (amdgpu_sriov_vf(psp->adev) ||
-(psp->adev->asic_type == CHIP_NAVY_FLOUNDER))
+if (amdgpu_sriov_vf(psp->adev) || !psp->asd_fw)
 return 0;

 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
--
2.17.1

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RE: [PATCH v2] drm/amd/pm: fix is_dpm_running() run error on 32bit system

2020-08-24 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen 

-Original Message-
From: Wang, Kevin(Yang) 
Sent: Monday, August 24, 2020 8:41 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Deucher, Alexander 
; Chen, Jiansong (Simon) ; 
Wang, Kevin(Yang) ; Chen, Jiansong (Simon) 

Subject: [PATCH v2] drm/amd/pm: fix is_dpm_running() run error on 32bit system

From: Kevin Wang 

v1:
the C type "unsigned long" size is 32bit on 32bit system, it will cause code 
logic error, so replace it with "uint64_t".

v2:
remove duplicate cast operation.

Signed-off-by: Kevin 
Suggest-by: Jiansong Chen 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c  | 10 +++---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c| 10 +++---
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 10 +++---
 3 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 8347b1f2509f..59b245c6c4d7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1844,10 +1844,14 @@ static bool arcturus_is_dpm_running(struct smu_context 
*smu)  {
 int ret = 0;
 uint32_t feature_mask[2];
-unsigned long feature_enabled;
+uint64_t feature_enabled;
+
 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
-feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
-   ((uint64_t)feature_mask[1] << 32));
+if (ret)
+return false;
+
+feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
+
 return !!(feature_enabled & SMC_DPM_FEATURE);  }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 72f3d68691d8..cc67d5c60f3d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1345,10 +1345,14 @@ static bool navi10_is_dpm_running(struct smu_context 
*smu)  {
 int ret = 0;
 uint32_t feature_mask[2];
-unsigned long feature_enabled;
+uint64_t feature_enabled;
+
 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
-feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
-   ((uint64_t)feature_mask[1] << 32));
+if (ret)
+return false;
+
+feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
+
 return !!(feature_enabled & SMC_DPM_FEATURE);  }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 66d655958a78..b48ac591db8b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1150,10 +1150,14 @@ static bool sienna_cichlid_is_dpm_running(struct 
smu_context *smu)  {
 int ret = 0;
 uint32_t feature_mask[2];
-unsigned long feature_enabled;
+uint64_t feature_enabled;
+
 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
-feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
-   ((uint64_t)feature_mask[1] << 32));
+if (ret)
+return false;
+
+feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
+
 return !!(feature_enabled & SMC_DPM_FEATURE);  }

--
2.27.0

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RE: [PATCH] drm/amd/pm: fix is_dpm_running() run error on 32bit system

2020-08-24 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Good point, but  I wonder whether the outmost uint64_t cast is necessary?

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Kevin
Sent: Monday, August 24, 2020 4:59 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray 
; Wang, Kevin(Yang) 
Subject: [PATCH] drm/amd/pm: fix is_dpm_running() run error on 32bit system

From: Kevin Wang 

the C type "unsigned long" size is 32bit on 32bit system, it will cause code 
logic error, so replace it with "uint64_t".

Signed-off-by: Kevin 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c   | 9 +++--
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 9 +++--
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 9 +++--
 3 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 8347b1f2509f..e619315b0f5c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1844,10 +1844,15 @@ static bool arcturus_is_dpm_running(struct smu_context 
*smu)  {
 int ret = 0;
 uint32_t feature_mask[2];
-unsigned long feature_enabled;
+uint64_t feature_enabled;
+
 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
-feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+if (ret)
+return false;
+
+feature_enabled = (uint64_t)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
+
 return !!(feature_enabled & SMC_DPM_FEATURE);  }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 72f3d68691d8..d95b370adaf4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1345,10 +1345,15 @@ static bool navi10_is_dpm_running(struct smu_context 
*smu)  {
 int ret = 0;
 uint32_t feature_mask[2];
-unsigned long feature_enabled;
+uint64_t feature_enabled;
+
 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
-feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+if (ret)
+return false;
+
+feature_enabled = (uint64_t)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
+
 return !!(feature_enabled & SMC_DPM_FEATURE);  }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 66d655958a78..f8df6448ab4d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1150,10 +1150,15 @@ static bool sienna_cichlid_is_dpm_running(struct 
smu_context *smu)  {
 int ret = 0;
 uint32_t feature_mask[2];
-unsigned long feature_enabled;
+uint64_t feature_enabled;
+
 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
-feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+if (ret)
+return false;
+
+feature_enabled = (uint64_t)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
+
 return !!(feature_enabled & SMC_DPM_FEATURE);  }

--
2.27.0

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RE: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid

2020-07-24 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

See my comments below.

-Original Message-
From: Gao, Likun 
Sent: Friday, July 24, 2020 5:39 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Chen, Jiansong (Simon) ; Gao, 
Likun 
Subject: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid

From: Likun Gao 

Update sienna_cichlid driver if header and related files.
Support new smu metrics for pre & postDS frequency.

Signed-off-by: Likun Gao 
Change-Id: I5446256fd7082a1d51df4ade3828bf5fa1ea3e7f
---
 .../inc/smu11_driver_if_sienna_cichlid.h  | 21 +--
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  2 +-
 .../drm/amd/powerplay/sienna_cichlid_ppt.c| 11 +++---
 3 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index b2232e24d82f..aa2708fccb6d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x33
+#define SMU11_DRIVER_IF_VERSION 0x34

 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 5

@@ -968,9 +968,15 @@ typedef struct {

 typedef struct {
   uint32_t CurrClock[PPCLK_COUNT];
-  uint16_t AverageGfxclkFrequency;
-  uint16_t AverageFclkFrequency;
-  uint16_t AverageUclkFrequency  ;
+
+  uint16_t AverageGfxclkFrequencyPreDs;  uint16_t
+ AverageGfxclkFrequencyPostDs;  uint16_t AverageFclkFrequencyPreDs;
+ uint16_t AverageFclkFrequencyPostDs;  uint16_t
+ AverageUclkFrequencyPreDs  ;  uint16_t AverageUclkFrequencyPostDs  ;
+
+
   uint16_t AverageGfxActivity;
   uint16_t AverageUclkActivity   ;
   uint8_t  CurrSocVoltageOffset  ;
@@ -988,6 +994,7 @@ typedef struct {
   uint16_t TemperatureLiquid0;
   uint16_t TemperatureLiquid1;
   uint16_t TemperaturePlx;
+  uint16_t Padding16 ;
   uint32_t ThrottlerStatus   ;

   uint8_t  LinkDpmLevel;
@@ -1006,8 +1013,10 @@ typedef struct {
   uint16_t AverageDclk0Frequency  ;
   uint16_t AverageVclk1Frequency  ;
   uint16_t AverageDclk1Frequency  ;
-  uint16_t VcnActivityPercentage ; //place holder, David N. to provide full 
sequence
-  uint16_t padding16_2;
+  uint16_t VcnActivityPercentage  ; //place holder, David N. to provide full 
sequence
+  uint8_t  PcieRate   ;
+  uint8_t  PcieWidth  ;
+
 } SmuMetrics_t;

 typedef struct {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 429f5aa8924a..9504f9954fd3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36  #define 
SMU11_DRIVER_IF_VERSION_NV12 0x33  #define SMU11_DRIVER_IF_VERSION_NV14 0x36 
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2

 /* MP Apertures */
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dcc5d25a7894..f64a1be94cb8 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -70,6 +70,8 @@
 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))

+#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
+
 static struct cmn2asic_msg_mapping 
sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
 MSG_MAP(TestMessage,PPSMC_MSG_TestMessage, 1),
 MSG_MAP(GetSmuVersion,PPSMC_MSG_GetSmuVersion,   1),
@@ -443,13 +445,16 @@ static int sienna_cichlid_get_smu_metrics_data(struct 
smu_context *smu,
 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 break;
 case METRICS_AVERAGE_GFXCLK:
-*value = metrics->AverageGfxclkFrequency;
+if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
+*value = metrics->AverageGfxclkFrequencyPostDs;
+else
+*value = metrics->AverageGfxclkFrequencyPreDs;

break;
[Jiansong] why fclk and uclk don't follow similar change as gfxclk, since all 
will enter DS when in idle state.
 case METRICS_AVERAGE_FCLK:
-*value = metrics->AverageFclkFrequency;
+*value = metrics->AverageFclkFrequencyPostDs;
 break;
 case METRICS_AVERAGE_UCLK:
-*value = metrics->AverageUclkFrequency;
+*value = metrics->AverageUclkFrequencyPostDs;
 break;
 case METRICS_AVERAGE_GFXACTIVITY:
 *value = metrics->AverageGfxActivity;
--
2.25.1

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RE: [PATCH] drm/amd/powerplay: skip invalid msg when smu set mp1 state

2020-07-21 Thread Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

Then why we don't handle it directly in smu_cmn_send_smc_msg_with_param where 
is more near to the source of the problem.
And there is similar logic already.
if (index < 0)
return index == -EACCES ? 0 : index;

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Likun Gao
Sent: Tuesday, July 21, 2020 2:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun ; Quan, Evan ; Sheng, 
Wenhui ; Zhang, Hawking 
Subject: [PATCH] drm/amd/powerplay: skip invalid msg when smu set mp1 state

From: Likun Gao 

Some asic may not support for some message of set mp1 state.
If the return value of smu_send_smc_msg is -EINVAL, that means it failed to 
send msg to smc as it can not map an valid message for the ASIC. And with that 
case, smu_set_mp1_state should be skipped as those ASIC was in fact do not 
support for that.

Signed-off-by: Likun Gao 
Change-Id: I31b40b87532a1d7549b26155d4ec8145b5e3f101
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index b197dcaed064..237d8ab8b40d 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1590,6 +1590,9 @@ int smu_set_mp1_state(struct smu_context *smu,
 }

 ret = smu_send_smc_msg(smu, msg, NULL);
+/* some asics may not support those messages */
+if (ret == -EINVAL)
+ret = 0;
 if (ret)
 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");

--
2.25.1

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