Re: Screen flicckering due to "drm/amdgpu: enable gfxoff again on raven series"

[Deucher, Alexander]

Make sure you have this patch as well:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-5.2-wip&id=083d022913f2f8c3bc1183a13874ad777b9f5bdd

Alex

From: Pinky 
Sent: Friday, April 5, 2019 2:38 PM
To: Deucher, Alexander
Cc: Huang, Ray; amd-gfx@lists.freedesktop.org
Subject: Re: Screen flicckering due to "drm/amdgpu: enable gfxoff again on 
raven series"


cat /sys/kernel/debug/dri/0/amdgpu_firmware_info
VCE feature version: 0, firmware version: 0x
UVD feature version: 0, firmware version: 0x
MC feature version: 0, firmware version: 0x
ME feature version: 40, firmware version: 0x0099
PFP feature version: 40, firmware version: 0x00ae
CE feature version: 40, firmware version: 0x004d
RLC feature version: 1, firmware version: 0xd237
RLC SRLC feature version: 1, firmware version: 0x0001
RLC SRLG feature version: 1, firmware version: 0x0001
RLC SRLS feature version: 1, firmware version: 0x0001
MEC feature version: 40, firmware version: 0x018b
MEC2 feature version: 40, firmware version: 0x018b
SOS feature version: 0, firmware version: 0x
ASD feature version: 0, firmware version: 0x0017ba78
TA XGMI feature version: 0, firmware version: 0x
TA RAS feature version: 0, firmware version: 0x
SMC feature version: 0, firmware version: 0x1e44
SDMA0 feature version: 41, firmware version: 0x00a9
VCN feature version: 0, firmware version: 0x01004912
DMCU feature version: 0, firmware version: 0x0001
VBIOS version: 113-RAVEN-110



* Deucher, Alexander  [2019-04-05 18:33:23 +]:

>+ Ray
>
>Ray, any ideas?
>
>Pinkava,
>
>can you provide the output of:
>sudo cat /sys/kernel/debug/dri/0/amdgpu_firmware_info
>
>Thanks,
>
>Alex
>
>From: Pinky 
>Sent: Friday, April 5, 2019 1:53 PM
>To: Deucher, Alexander
>Cc: amd-gfx@lists.freedesktop.org
>Subject: Re: Screen flicckering due to "drm/amdgpu: enable gfxoff again on 
>raven series"
>
>No, this does no do anything, the bug is still present.
>
>
>* Deucher, Alexander  [2019-04-05 17:07:21 +]:
>
>>This may be related to stutter mode rather than gfxoff.  If so, there is a 
>>fix in the pipeline for that.  Does setting appending 
>>amdgpu.ppfeaturemask=0xfffdbfff on the kernel command line fix it?
>>
>>Alex
>>
>>From: amd-gfx  on behalf of Pinky 
>>
>>Sent: Friday, April 5, 2019 12:24 PM
>>To: amd-gfx@lists.freedesktop.org
>>Subject: Screen flicckering due to "drm/amdgpu: enable gfxoff again on raven 
>>series"
>>
>>Hello,
>>
>>I have today compiled the drm-next kernel from (1) and find out the screen is
>>flickering and shows various artifacts. By bissecting I found the cause
>>is commit 005440066f929ba0dca8f4e0aebfbf8daac592cc. By reverting it the
>>problem went out.
>>
>>I does not have idea about what to do next. Sorry if this should be posted to
>>some bugzilla instead, I have got a bit lost. If so, would You please
>>point my out what to do?
>>
>>With best regards,
>>Pinkava J.
>>
>>
>>lspci (partial)
>>
>>00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 IOMMU
>>00:01.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 
>>00h-0fh) PCIe Dummy Host Bridge
>>06:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] 
>>Raven Ridge [Radeon Vega Series / Radeon Vega Mobile Series] (rev d1)
>>06:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] 
>>Raven/Raven2/Fenghuang HDMI/DP Audio Controller
>>
>>
>>
>>
>>(1) git://people.freedesktop.org/~agd5f/linux
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>>https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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Re: Screen flicckering due to "drm/amdgpu: enable gfxoff again on raven series"

[Deucher, Alexander]

+ Ray

Ray, any ideas?

Pinkava,

can you provide the output of:
sudo cat /sys/kernel/debug/dri/0/amdgpu_firmware_info

Thanks,

Alex

From: Pinky 
Sent: Friday, April 5, 2019 1:53 PM
To: Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: Screen flicckering due to "drm/amdgpu: enable gfxoff again on 
raven series"

No, this does no do anything, the bug is still present.


* Deucher, Alexander  [2019-04-05 17:07:21 +]:

>This may be related to stutter mode rather than gfxoff.  If so, there is a fix 
>in the pipeline for that.  Does setting appending 
>amdgpu.ppfeaturemask=0xfffdbfff on the kernel command line fix it?
>
>Alex
>
>From: amd-gfx  on behalf of Pinky 
>
>Sent: Friday, April 5, 2019 12:24 PM
>To: amd-gfx@lists.freedesktop.org
>Subject: Screen flicckering due to "drm/amdgpu: enable gfxoff again on raven 
>series"
>
>Hello,
>
>I have today compiled the drm-next kernel from (1) and find out the screen is
>flickering and shows various artifacts. By bissecting I found the cause
>is commit 005440066f929ba0dca8f4e0aebfbf8daac592cc. By reverting it the
>problem went out.
>
>I does not have idea about what to do next. Sorry if this should be posted to
>some bugzilla instead, I have got a bit lost. If so, would You please
>point my out what to do?
>
>With best regards,
>Pinkava J.
>
>
>lspci (partial)
>
>00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 IOMMU
>00:01.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 
>00h-0fh) PCIe Dummy Host Bridge
>06:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] 
>Raven Ridge [Radeon Vega Series / Radeon Vega Mobile Series] (rev d1)
>06:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] 
>Raven/Raven2/Fenghuang HDMI/DP Audio Controller
>
>
>
>
>(1) git://people.freedesktop.org/~agd5f/linux
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Re: Screen flicckering due to "drm/amdgpu: enable gfxoff again on raven series"

[Deucher, Alexander]

Kernel command line in grub.

From: amd-gfx  on behalf of Deucher, 
Alexander 
Sent: Friday, April 5, 2019 1:07 PM
To: Pinky; amd-gfx@lists.freedesktop.org
Subject: Re: Screen flicckering due to "drm/amdgpu: enable gfxoff again on 
raven series"

This may be related to stutter mode rather than gfxoff.  If so, there is a fix 
in the pipeline for that.  Does setting appending 
amdgpu.ppfeaturemask=0xfffdbfff on the kernel command line fix it?

Alex

From: amd-gfx  on behalf of Pinky 

Sent: Friday, April 5, 2019 12:24 PM
To: amd-gfx@lists.freedesktop.org
Subject: Screen flicckering due to "drm/amdgpu: enable gfxoff again on raven 
series"

Hello,

I have today compiled the drm-next kernel from (1) and find out the screen is
flickering and shows various artifacts. By bissecting I found the cause
is commit 005440066f929ba0dca8f4e0aebfbf8daac592cc. By reverting it the
problem went out.

I does not have idea about what to do next. Sorry if this should be posted to
some bugzilla instead, I have got a bit lost. If so, would You please
point my out what to do?

With best regards,
Pinkava J.


lspci (partial)

00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 IOMMU
00:01.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 
00h-0fh) PCIe Dummy Host Bridge
06:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Raven 
Ridge [Radeon Vega Series / Radeon Vega Mobile Series] (rev d1)
06:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] 
Raven/Raven2/Fenghuang HDMI/DP Audio Controller




(1) git://people.freedesktop.org/~agd5f/linux
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Re: Screen flicckering due to "drm/amdgpu: enable gfxoff again on raven series"

[Deucher, Alexander]

This may be related to stutter mode rather than gfxoff.  If so, there is a fix 
in the pipeline for that.  Does setting appending 
amdgpu.ppfeaturemask=0xfffdbfff on the kernel command line fix it?

Alex

From: amd-gfx  on behalf of Pinky 

Sent: Friday, April 5, 2019 12:24 PM
To: amd-gfx@lists.freedesktop.org
Subject: Screen flicckering due to "drm/amdgpu: enable gfxoff again on raven 
series"

Hello,

I have today compiled the drm-next kernel from (1) and find out the screen is
flickering and shows various artifacts. By bissecting I found the cause
is commit 005440066f929ba0dca8f4e0aebfbf8daac592cc. By reverting it the
problem went out.

I does not have idea about what to do next. Sorry if this should be posted to
some bugzilla instead, I have got a bit lost. If so, would You please
point my out what to do?

With best regards,
Pinkava J.


lspci (partial)

00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Raven/Raven2 IOMMU
00:01.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 
00h-0fh) PCIe Dummy Host Bridge
06:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Raven 
Ridge [Radeon Vega Series / Radeon Vega Mobile Series] (rev d1)
06:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] 
Raven/Raven2/Fenghuang HDMI/DP Audio Controller




(1) git://people.freedesktop.org/~agd5f/linux
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Re: [PATCH 1/2] drm/amdgpu: Allow switching to CUSTOM profile on Vega10/20 v2

[Deucher, Alexander]

Only vega and newer have the concept of profiles in the SMU.  Vegas has a set 
of profiles that the SMU tracks directly.  SMU7 parts don't really have 
profiles per se; there just one "state" and the driver loads all the params 
into that state when you request a profile (custom or hardcoded).

Alex


From: amd-gfx  on behalf of Russell, 
Kent 
Sent: Friday, March 29, 2019 7:07 AM
To: Quan, Evan; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 1/2] drm/amdgpu: Allow switching to CUSTOM profile on 
Vega10/20 v2


Sorry for all of the questions, Evan. I see that we store the CUSTOM profile 
for Vega10/Fiji, but is that a limitation of the HW not being able to store it 
via the SMU? It seems like a lot of extra work to store a local copy, when we 
can just get the copy from the GPU itself, especially if we don’t need to do 
that on future ASICs. I would assume that the CUSTOM profile that is kept on 
the GPU is valid, but would it be simpler to just initialize the CUSTOM profile 
to the same values as the BOOTUP values when we initialize the ASIC, then 
submit that to the GPU, thus ensuring that the CUSTOM profile always has some 
valid values? Or conversely, zeroing out the CUSTOM profile on initialization, 
so that the check is still valid.



I have no problem doing the work, I just want to make sure that it makes the 
most sense and that we’re not having to redo it later if the SMU standardizes 
things and actually allows all future ASICs to store the CUSTOM profile on the 
GPU. Thanks!



Kent

From: Quan, Evan
Sent: Thursday, March 28, 2019 10:47 AM
To: Russell, Kent ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 1/2] drm/amdgpu: Allow switching to CUSTOM profile on 
Vega10/20 v2



OK, I see. Yep, the new settings will be stored in SMU.

But as I know, the SMU comes with some default settings for CUSTOM profile.

I suspect “activity_monitor.Soc_BoosterFreqType != 0” will be also true even 
without your first CUSTOM profile settings(with input parameters).

So, I would prefer to have a local copy of previous custom settigns(as what we 
do on vega10 and smu7).



Evan

From: Russell, Kent mailto:kent.russ...@amd.com>>
Sent: Thursday, March 28, 2019 5:29 PM
To: Quan, Evan mailto:evan.q...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/amdgpu: Allow switching to CUSTOM profile on 
Vega10/20 v2



Am I mistaken in thinking that activity monitor gets the existing CUSTOM 
profile from the SMU? When I tested it, the CUSTOM profile was saved and could 
be retrieved through this method. I specifically set the profile to something 
ridiculous (1 2 3 4 5 6 7 8 9 10) and these values were retained when switching 
to VR and back to CUSTOM, so I was under the impression that it was saved to 
the SMU when we submit it to the SMU.

Kent

KENT RUSSELL
Sr. Software Engineer | Linux Compute Kernel
1 Commerce Valley Drive East
Markham, ON L3T 7X6
O +(1) 289-695-2122 | Ext 72122



From: Quan, Evan
Sent: Wednesday, March 27, 2019 9:36:02 PM
To: Russell, Kent; 
amd-gfx@lists.freedesktop.org
Cc: Russell, Kent
Subject: RE: [PATCH 1/2] drm/amdgpu: Allow switching to CUSTOM profile on 
Vega10/20 v2



For vega20, activity_monitor is also a temporary structure and you should not 
rely on that for judging existence of custom profile.

Regards
Evan
> -Original Message-
> From: amd-gfx 
> mailto:amd-gfx-boun...@lists.freedesktop.org>>
>  On Behalf Of
> Russell, Kent
> Sent: Wednesday, March 27, 2019 9:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Russell, Kent mailto:kent.russ...@amd.com>>
> Subject: [PATCH 1/2] drm/amdgpu: Allow switching to CUSTOM profile on
> Vega10/20 v2
>
> Don't return an error if the CUSTOM profile is selected, just apply it with 
> the
> values saved to the GPU
>
> v2: Remove reference to fixed bug, check that CUSTOM profile was set
>
> Change-Id: I114cc9783226ee9ebb146863897e951527a85e20
> Signed-off-by: Kent Russell 
> mailto:kent.russ...@amd.com>>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 14
> +-
> drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 14
> +-
>  2 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 85a536924571..7e9e7e254a0d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4910,9 +4910,20 @@ static int vega10_set_power_profile_mode(struct
> pp_hwmgr *hwmgr, long *input, ui
>1 << power_profile_mode);
>
>if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
> - if (size == 0 || size > 4)
> + if (size != 0 && size != 4)
>ret

Re: [PATCH] drm/amd/powerplay: check for invalid profile mode before switching

[Deucher, Alexander]

Sure no problem.

Acked-by: Alex Deucher 

From: Quan, Evan
Sent: Wednesday, March 27, 2019 9:55 PM
To: Quan, Evan; amd-gfx@lists.freedesktop.org; Deucher, Alexander
Cc: Russell, Kent
Subject: RE: [PATCH] drm/amd/powerplay: check for invalid profile mode before 
switching

It's kind of an improvement of the previous commit
drm/amd/powerplay: update current profile mode only when it's really applied

No need to update current profile mode if the new profile mode
does not take effect in fact.

Maybe @Deucher, Alexander can help to combine them as one.

Regards,
Evan
> -Original Message-
> From: Evan Quan 
> Sent: Thursday, March 28, 2019 9:51 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Russell, Kent ; Quan, Evan
> 
> Subject: [PATCH] drm/amd/powerplay: check for invalid profile mode before
> switching
>
> Need to check for invalid profile mode settings before determining to switch
> to that.
>
> Change-Id: Ie47cd75a73a8369c349410ea74d322df1d3d38d1
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 85a536924571..973a8896fa9d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4906,9 +4906,6 @@ static int vega10_set_power_profile_mode(struct
> pp_hwmgr *hwmgr, long *input, ui
>uint8_t min_active_level;
>uint32_t power_profile_mode = input[size];
>
> - smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetWorkloadMask,
> - 1 << power_profile_mode);
> -
>if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
>if (size == 0 || size > 4)
>return -EINVAL;
> @@ -4923,6 +4920,8 @@ static int vega10_set_power_profile_mode(struct
> pp_hwmgr *hwmgr, long *input, ui
>use_rlc_busy << 16 |
> min_active_level<<24);
>}
>
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetWorkloadMask,
> + 1 << power_profile_mode);
>hwmgr->power_profile_mode = power_profile_mode;
>
>return 0;
> --
> 2.21.0

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Re: [PATCH 2/2] drm/amd/powerplay: correct data type to avoid overflow

[Deucher, Alexander]

Series is:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Quan, Evan 

Sent: Tuesday, March 26, 2019 6:15 AM
To: Quan, Evan; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/2] drm/amd/powerplay: correct data type to avoid overflow

Ping..

> -Original Message-
> From: Evan Quan 
> Sent: 2019年3月23日 2:07
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan 
> Subject: [PATCH 2/2] drm/amd/powerplay: correct data type to avoid
> overflow
>
> Avoid left shift overflow.
>
> Change-Id: If03f4f4d440b6d742d8eaa23d0bae6ddd21c01ea
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
> index b90089a4fb6a..195c4ae67058 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
> @@ -165,7 +165,7 @@
>  #define FEATURE_DS_FCLK_MASK(1 << FEATURE_DS_FCLK_BIT
> )
>  #define FEATURE_DS_MP1CLK_MASK  (1 <<
> FEATURE_DS_MP1CLK_BIT  )
>  #define FEATURE_DS_MP0CLK_MASK  (1 <<
> FEATURE_DS_MP0CLK_BIT  )
> -#define FEATURE_XGMI_MASK   (1 << FEATURE_XGMI_BIT   
> )
> +#define FEATURE_XGMI_MASK   (1ULL <<
> FEATURE_XGMI_BIT   )
>  #define FEATURE_ECC_MASK(1ULL << FEATURE_ECC_BIT 
>)
>
>  #define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x0001
> --
> 2.21.0

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Re: [PATCH] drm/amd/powerplay: fix possible hang with 3+ 4K monitors

[Deucher, Alexander]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Evan Quan 

Sent: Tuesday, March 26, 2019 6:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: fix possible hang with 3+ 4K monitors

If DAL requires to force MCLK high, the FCLK will be
forced to high also.

Change-Id: Iaff8956ca1faafaf904f0bec108f566e8bbf6a64
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 3f349ada8de0..38dbec3caa01 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -3471,6 +3471,7 @@ static int vega20_apply_clocks_adjust_rules(struct 
pp_hwmgr *hwmgr)
 struct vega20_single_dpm_table *dpm_table;
 bool vblank_too_short = false;
 bool disable_mclk_switching;
+   bool disable_fclk_switching;
 uint32_t i, latency;

 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
@@ -3546,13 +3547,20 @@ static int vega20_apply_clocks_adjust_rules(struct 
pp_hwmgr *hwmgr)
 if (hwmgr->display_config->nb_pstate_switch_disable)
 dpm_table->dpm_state.hard_min_level = 
dpm_table->dpm_levels[dpm_table->count - 1].value;

+   if ((disable_mclk_switching &&
+   (dpm_table->dpm_state.hard_min_level == 
dpm_table->dpm_levels[dpm_table->count - 1].value)) ||
+hwmgr->display_config->min_mem_set_clock / 100 >= 
dpm_table->dpm_levels[dpm_table->count - 1].value)
+   disable_fclk_switching = true;
+   else
+   disable_fclk_switching = false;
+
 /* fclk */
 dpm_table = &(data->dpm_table.fclk_table);
 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
-   if (hwmgr->display_config->nb_pstate_switch_disable)
+   if (hwmgr->display_config->nb_pstate_switch_disable || 
disable_fclk_switching)
 dpm_table->dpm_state.soft_min_level = 
dpm_table->dpm_levels[dpm_table->count - 1].value;

 /* vclk */
--
2.21.0

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Re: [PATCH] drm/amdgpu: Adjust TMR address alignment as per HW requirement

[Deucher, Alexander]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Liu, Shaoyun 

Sent: Monday, March 25, 2019 4:14 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH] drm/amdgpu: Adjust TMR address alignment as per HW requirement

According to HW engineer, they prefer the TMR address be "naturally aligned", 
e.g. the start address
must be an integer divide of TME size.

Change-Id: Ie01b3d41e564fc8f416048e001d75edb64c045e3
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2206bb4..905cce1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -187,13 +187,13 @@ static int psp_tmr_init(struct psp_context *psp)
 int ret;

 /*
-* Allocate 3M memory aligned to 1M from Frame Buffer (local
-* physical).
+* According to HW engineer, they prefer the TMR address be "naturally
+* aligned" , e.g. the start address be an integer divide of TMR size.
  *
  * Note: this memory need be reserved till the driver
  * uninitializes.
  */
-   ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x10,
+   ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, PSP_TMR_SIZE,
   AMDGPU_GEM_DOMAIN_VRAM,
   &psp->tmr_bo, &psp->tmr_mc_addr, 
&psp->tmr_buf);

--
2.7.4

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Re: [PATCH] drm/amd/display: Fix "dc has no member named dml" compile error

[Deucher, Alexander]

Thanks!

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of 
sunpeng...@amd.com 
Sent: Thursday, March 21, 2019 10:44 AM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Sun peng (Leo); Alex Deucher; Wentland, Harry; Kazlauskas, Nicholas
Subject: [PATCH] drm/amd/display: Fix "dc has no member named dml" compile error

From: Leo Li 

For DCN disabled builds, dc->dml is stripped out. Therefore, guard usage
in dc_create_state() with CONFIG_DRM_AMD_DC_DCN1_0.

It fixes the following error:

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c: In function 
'dc_create_state':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:1237:34: error: 'struct 
>> dc' has no member named 'dml'
 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
 ^~

Signed-off-by: Leo Li 
CC: Alex Deucher 
CC: Harry Wentland 
CC: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index cebd083..589cd95 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1245,7 +1245,9 @@ struct dc_state *dc_create_state(struct dc *dc)
  * initialize and obtain IP and SOC the base DML instance from DC is
  * initially copied into every context
  */
+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct 
display_mode_lib));
+#endif

 kref_init(&context->refcount);

--
2.7.4

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Re: [PATCH xf86-video-ati] modesetting: add tile property support

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Thursday, March 14, 2019 6:19 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH xf86-video-ati] modesetting: add tile property support

From: Dave Airlie 

This adds tiling support to the driver, it retrieves the tile info from
the kernel and translates it into the server format and exposes the
property.

(Ported from xserver commits 8fb8bbb3062f1a06621ab7030a9e89d5e8367b35
 and 6abdb54a11dac4e8854ff94ecdcb90a14321ab31)
(Ported from amdgpu commit 6ee857726166f495abcd68e4ff60e3a09593d079)

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 54 +--
 src/drmmode_display.h |  3 +++
 2 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 002513f1a..0e9e24749 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1576,6 +1576,51 @@ drmmode_output_mode_valid(xf86OutputPtr output, 
DisplayModePtr pModes)
 return MODE_OK;
 }

+static void
+drmmode_output_attach_tile(xf86OutputPtr output)
+{
+#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1, 17, 99, 901, 0)
+   drmmode_output_private_ptr drmmode_output = output->driver_private;
+   drmModeConnectorPtr koutput = drmmode_output->mode_output;
+   RADEONEntPtr pRADEONEnt = RADEONEntPriv(output->scrn);
+   struct xf86CrtcTileInfo tile_info, *set = NULL;
+   int i;
+
+   if (!koutput) {
+   xf86OutputSetTile(output, NULL);
+   return;
+   }
+
+   /* look for a TILE property */
+   for (i = 0; i < koutput->count_props; i++) {
+   drmModePropertyPtr props;
+   props = drmModeGetProperty(pRADEONEnt->fd, koutput->props[i]);
+   if (!props)
+   continue;
+
+   if (!(props->flags & DRM_MODE_PROP_BLOB)) {
+   drmModeFreeProperty(props);
+   continue;
+   }
+
+   if (!strcmp(props->name, "TILE")) {
+   drmModeFreePropertyBlob(drmmode_output->tile_blob);
+   drmmode_output->tile_blob =
+   drmModeGetPropertyBlob(pRADEONEnt->fd,
+  koutput->prop_values[i]);
+   }
+   drmModeFreeProperty(props);
+   }
+   if (drmmode_output->tile_blob) {
+   if (xf86OutputParseKMSTile(drmmode_output->tile_blob->data,
+  drmmode_output->tile_blob->length,
+  &tile_info) == TRUE)
+   set = &tile_info;
+   }
+   xf86OutputSetTile(output, set);
+#endif
+}
+
 static int
 koutput_get_prop_idx(int fd, drmModeConnectorPtr koutput,
 int type, const char *name)
@@ -1648,6 +1693,8 @@ drmmode_output_get_modes(xf86OutputPtr output)
 }
 xf86OutputSetEDID(output, mon);

+   drmmode_output_attach_tile(output);
+
 /* modes should already be available */
 for (i = 0; i < koutput->count_modes; i++) {
 Mode = xnfalloc(sizeof(DisplayModeRec));
@@ -1665,8 +1712,11 @@ drmmode_output_destroy(xf86OutputPtr output)
 drmmode_output_private_ptr drmmode_output = output->driver_private;
 int i;

-   if (drmmode_output->edid_blob)
-   drmModeFreePropertyBlob(drmmode_output->edid_blob);
+   drmModeFreePropertyBlob(drmmode_output->edid_blob);
+#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1, 17, 99, 901, 0)
+   drmModeFreePropertyBlob(drmmode_output->tile_blob);
+#endif
+
 for (i = 0; i < drmmode_output->num_props; i++) {
 drmModeFreeProperty(drmmode_output->props[i].mode_prop);
 free(drmmode_output->props[i].atoms);
diff --git a/src/drmmode_display.h b/src/drmmode_display.h
index 2c2c3d57f..96eaef0aa 100644
--- a/src/drmmode_display.h
+++ b/src/drmmode_display.h
@@ -142,6 +142,9 @@ typedef struct {
 drmModeConnectorPtr mode_output;
 drmModeEncoderPtr *mode_encoders;
 drmModePropertyBlobPtr edid_blob;
+#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1, 17, 99, 901, 0)
+drmModePropertyBlobPtr tile_blob;
+#endif
 int dpms_enum_id;
 int num_props;
 drmmode_prop_ptr props;
--
2.20.1

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Re: [PATCH xf86-video-ati] Use radeon_finish in drmmode_crtc_scanout_update

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Thursday, March 14, 2019 6:15 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH xf86-video-ati] Use radeon_finish in drmmode_crtc_scanout_update

From: Michel Dänzer 

radeon_glamor_finish only works if we're using glamor, otherwise it'll
crash.

Fixes: ce7db51020d3 "Cancel pending scanout update in 
drmmode_crtc_scanout_update"
Bug: https://bugs.debian.org/924540
Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index c5fccd2aa..002513f1a 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -785,7 +785,7 @@ drmmode_crtc_scanout_update(xf86CrtcPtr crtc, 
DisplayModePtr mode,
  
screen->GetWindowPixmap(screen->root),
  extents)) {
 
RegionEmpty(DamageRegion(drmmode_crtc->scanout_damage));
-   radeon_glamor_finish(scrn);
+   radeon_finish(scrn, 
drmmode_crtc->scanout[scanout_id].bo);

 if (!drmmode_crtc->flip_pending) {
 radeon_drm_abort_entry(drmmode_crtc->
--
2.20.1

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Re: [PATCH] drm/amdgpu: enable gfxoff again on raven series

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Huang Rui 

Sent: Wednesday, March 13, 2019 8:27 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray
Subject: [PATCH] drm/amdgpu: enable gfxoff again on raven series

This patch enables gfxoff and stutter mode again, since we take more testing on
raven series. For raven2 and picasso, we can enable it directly. And for raven,
we need check the RLC ucode version cannot be less than #531.

Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 21 +
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 13 -
 4 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 95cd3b7..02c1125 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1508,6 +1508,8 @@ static int amdgpu_device_ip_early_init(struct 
amdgpu_device *adev)
 }

 adev->pm.pp_feature = amdgpu_pp_feature_mask;
+   if (amdgpu_sriov_vf(adev))
+   adev->pm.pp_feature &= ~PP_GFXOFF_MASK;

 for (i = 0; i < adev->num_ip_blocks; i++) {
 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 4a8c422..5681a41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -118,8 +118,8 @@ uint amdgpu_pg_mask = 0x;
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-/* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/
-uint amdgpu_pp_feature_mask = 0xfffd3fff;
+/* OverDrive(bit 14) disabled by default*/
+uint amdgpu_pp_feature_mask = 0xbfff;
 int amdgpu_ngg = 0;
 int amdgpu_prim_buf_per_se = 0;
 int amdgpu_pos_buf_per_se = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 60c582c..6b48d4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -578,6 +578,26 @@ static void gfx_v9_0_check_fw_write_wait(struct 
amdgpu_device *adev)
 }
 }

+static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
+{
+   switch (adev->asic_type) {
+   case CHIP_VEGA10:
+   case CHIP_VEGA12:
+   case CHIP_VEGA20:
+   break;
+   case CHIP_RAVEN:
+   if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
+   break;
+   if ((adev->gfx.rlc_fw_version < 531) ||
+   (adev->gfx.rlc_feature_version < 1) ||
+   !adev->gfx.rlc.is_rlc_v2_1)
+   adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+   break;
+   default:
+   break;
+   }
+}
+
 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 {
 const char *chip_name;
@@ -830,6 +850,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device 
*adev)
 }

 out:
+   gfx_v9_0_check_if_need_gfxoff(adev);
 gfx_v9_0_check_fw_write_wait(adev);
 if (err) {
 dev_err(adev->dev,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 0ad8fe4..f32e3d0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -114,11 +114,6 @@ static int smu10_initialize_dpm_defaults(struct pp_hwmgr 
*hwmgr)
 smu10_data->num_active_display = 0;
 smu10_data->deep_sleep_dcefclk = 0;

-   if (hwmgr->feature_mask & PP_GFXOFF_MASK)
-   smu10_data->gfx_off_controled_by_driver = true;
-   else
-   smu10_data->gfx_off_controled_by_driver = false;
-
 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 PHM_PlatformCaps_SclkDeepSleep);

@@ -330,9 +325,9 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)

 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 {
-   struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+   struct amdgpu_device *adev = hwmgr->adev;

-   if (smu10_data->gfx_off_controled_by_driver) {
+   if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff);

 /* confirm gfx is back to "on" state */
@@ -350,9 +345,9 @@ static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)

 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
 {
-   struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+   struct amdgpu_device *adev = hwmgr->adev;

-   if (smu10_data->gfx_off_controled_by_dri

Re: Slow memory access when using OpenCL without X11

[Deucher, Alexander]

Forcing the sclk and mclk high may impact the CPU frequency since they share 
TDP.

Alex

From: amd-gfx  on behalf of Lauri 
Ehrenpreis 
Sent: Tuesday, March 12, 2019 5:31 PM
To: Kuehling, Felix
Cc: Tom St Denis; amd-gfx@lists.freedesktop.org
Subject: Re: Slow memory access when using OpenCL without X11

However it's not only related to mclk and sclk. I tried this:
rocm-smi  --setsclk 2
rocm-smi  --setmclk 3
rocm-smi
ROCm System Management Interface


GPU   Temp   AvgPwr   SCLKMCLKPCLK   Fan PerfPwrCap   
SCLK OD   MCLK OD  GPU%
GPU[0] : WARNING: Empty SysFS value: pclk
GPU[0] : WARNING: Unable to read /sys/class/drm/card0/device/gpu_busy_percent
0 34.0c  N/A  1240Mhz 1333Mhz N/A0%  manual  N/A  
0%0%   N/A

   End of ROCm SMI Log  


./cl_slow_test 1
got 1 platforms 1 devices
speed 3919.777100 avg 3919.777100 mbytes/s
speed 3809.373291 avg 3864.575195 mbytes/s
speed 585.796814 avg 2771.649170 mbytes/s
speed 188.721848 avg 2125.917236 mbytes/s
speed 188.916367 avg 1738.517090 mbytes/s

So despite forcing max sclk and mclk the memory speed is still slow..

--
Lauri


On Tue, Mar 12, 2019 at 11:21 PM Lauri Ehrenpreis 
mailto:lauri...@gmail.com>> wrote:
IN the case when memory is slow, the rocm-smi outputs this:
ROCm System Management Interface


GPU   Temp   AvgPwr   SCLKMCLKPCLK   Fan PerfPwrCap   
SCLK OD   MCLK OD  GPU%
GPU[0] : WARNING: Empty SysFS value: pclk
GPU[0] : WARNING: Unable to read /sys/class/drm/card0/device/gpu_busy_percent
0 30.0c  N/A  400Mhz  933Mhz  N/A0%  autoN/A  
0%0%   N/A

   End of ROCm SMI Log  


normal memory speed case gives following:
ROCm System Management Interface


GPU   Temp   AvgPwr   SCLKMCLKPCLK   Fan PerfPwrCap   
SCLK OD   MCLK OD  GPU%
GPU[0] : WARNING: Empty SysFS value: pclk
GPU[0] : WARNING: Unable to read /sys/class/drm/card0/device/gpu_busy_percent
0 35.0c  N/A  400Mhz  1200Mhz N/A0%  autoN/A  
0%0%   N/A

   End of ROCm SMI Log  


So there is a difference in MCLK - can this cause such a huge slowdown?

--
Lauri

On Tue, Mar 12, 2019 at 6:39 PM Kuehling, Felix 
mailto:felix.kuehl...@amd.com>> wrote:
[adding the list back]

I'd suspect a problem related to memory clock. This is an APU where
system memory is shared with the CPU, so if the SMU changes memory
clocks that would affect CPU memory access performance. If the problem
only occurs when OpenCL is running, then the compute power profile could
have an effect here.

Laurie, can you monitor the clocks during your tests using rocm-smi?

Regards,
   Felix

On 2019-03-11 1:15 p.m., Tom St Denis wrote:
> Hi Lauri,
>
> I don't have ROCm installed locally (not on that team at AMD) but I
> can rope in some of the KFD folk and see what they say :-).
>
> (in the mean time I should look into installing the ROCm stack on my
> Ubuntu disk for experimentation...).
>
> Only other thing that comes to mind is some sort of stutter due to
> power/clock gating (or gfx off/etc).  But that typically affects the
> display/gpu side not the CPU side.
>
> Felix:  Any known issues with Raven and ROCm interacting over memory
> bus performance?
>
> Tom
>
> On Mon, Mar 11, 2019 at 12:56 PM Lauri Ehrenpreis 
> mailto:lauri...@gmail.com>
> >> wrote:
>
> Hi!
>
> The 100x memory slowdown is hard to belive indeed. I attached the
> test program with my first e-mail which depends only on
> rocm-opencl-dev package. Would you mind compiling it and checking
> if it slows down memory for you as well?
>
> steps:
> 1) g++ cl_slow_test.cpp -o cl_slow_test -I
> /opt/rocm/opencl/include/ -L /opt/rocm/opencl/lib/x86_64/  -lOpenCL
> 2) logout from desktop env and disconnect hdmi/diplayport etc
> 3) log in over ssh
> 4) run the program ./cl_slow_test 1
>
> For me i

Re: [PATCH 2/3] drm/amdgpu: free up the first paging queue

[Deucher, Alexander]

I don't think Raven has a paging queue in the first place.

Alex

From: amd-gfx  on behalf of Kuehling, 
Felix 
Sent: Tuesday, March 12, 2019 11:29 AM
To: Christian König; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/3] drm/amdgpu: free up the first paging queue

I think this would break Raven, which only has one SDMA engine.

Regards,
  Felix

-Original Message-
From: amd-gfx  On Behalf Of Christian 
König
Sent: Tuesday, March 12, 2019 8:38 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 2/3] drm/amdgpu: free up the first paging queue

We need the first paging queue to handle page faults.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3ac5abe937f4..bed18e7bbc36 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2266,7 +2266,7 @@ static void sdma_v4_0_set_buffer_funcs(struct 
amdgpu_device *adev)  {
 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
 if (adev->sdma.has_page_queue)
-   adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
+   adev->mman.buffer_funcs_ring = &adev->sdma.instance[1].page;
 else
 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  
} @@ -2285,15 +2285,19 @@ static void sdma_v4_0_set_vm_pte_funcs(struct 
amdgpu_device *adev)
 unsigned i;

 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
-   for (i = 0; i < adev->sdma.num_instances; i++) {
-   if (adev->sdma.has_page_queue)
-   sched = &adev->sdma.instance[i].page.sched;
-   else
-   sched = &adev->sdma.instance[i].ring.sched;
-   adev->vm_manager.vm_pte_rqs[i] =
+   if (adev->sdma.has_page_queue) {
+   sched = &adev->sdma.instance[1].page.sched;
+   adev->vm_manager.vm_pte_rqs[0] =
 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+   adev->vm_manager.vm_pte_num_rqs = 1;
+   } else {
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   sched = &adev->sdma.instance[i].ring.sched;
+   adev->vm_manager.vm_pte_rqs[i] =
+   &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+   }
+   adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
 }
-   adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
 }

 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
--
2.17.1

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RE: [PATCH 2/2] drm/amdgpu: add new ras workflow control flags

[Deucher, Alexander]

> -Original Message-
> From: Pan, Xinhui 
> Sent: Tuesday, March 12, 2019 6:14 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Quan, Evan
> ; Zhang, Hawking 
> Subject: [PATCH 2/2] drm/amdgpu: add new ras workflow control flags
> 
> add ras post init function.
> Do some initialization after all IP have finished their late init.
> 
> Add new member flags which will control the ras work flow.
> For now, vbios enable ras for us on boot. That might change in the future.
> So there should be a flag from vbios to tell us if ras is enabled or not on 
> boot.
> Looks like there is no such info now.
> 
> Other bits of the flags are reserved to control other parts of ras.
> 
> Signed-off-by: xinhui pan 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  3 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 34
> +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h|  3 ++
>  3 files changed, 39 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 29c44a2eabcf..95cd3b7886ff 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2707,6 +2707,9 @@ int amdgpu_device_init(struct amdgpu_device
> *adev,
>   goto failed;
>   }
> 
> + /* must succeed. */
> + amdgpu_ras_post_init(adev);
> +
>   return 0;
> 
>  failed:
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index 10ce40d2c040..238b46c304cc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -118,6 +118,11 @@ const char *ras_block_string[] = {  #define
> ras_err_str(i) (ras_error_string[ffs(i)])  #define ras_block_str(i)
> (ras_block_string[i])
> 
> +enum amdgpu_ras_flags {
> + AMDGPU_RAS_FLAG_INIT_BY_VBIOS = 1,
> +};
> +#define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
> +

Move this enum to amdgpu_ras.h?  Although if you are going to be using this as 
flags, maybe defines would be better.

>  static void amdgpu_ras_self_test(struct amdgpu_device *adev)  {
>   /* TODO */
> @@ -1387,13 +1392,16 @@ int amdgpu_ras_init(struct amdgpu_device
> *adev)
>   &con->supported);
>   con->features = 0;
>   INIT_LIST_HEAD(&con->head);
> + /* Might need get this flag from vbios. */
> + con->flags = RAS_DEFAULT_FLAGS;
> 
>   if (amdgpu_ras_recovery_init(adev))
>   goto recovery_out;
> 
>   amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
> 
> - amdgpu_ras_enable_all_features(adev, 1);
> + if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
> + amdgpu_ras_enable_all_features(adev, 1);
> 
>   if (amdgpu_ras_fs_init(adev))
>   goto fs_out;
> @@ -1413,6 +1421,30 @@ int amdgpu_ras_init(struct amdgpu_device
> *adev)
>   return -EINVAL;
>  }
> 
> +/* do some init work after IP late init as dependence */ void
> +amdgpu_ras_post_init(struct amdgpu_device *adev) {
> + struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
> + struct ras_manager *obj, *tmp;
> +
> + if (!con)
> + return;
> +
> + /* We enable ras on all hw_supported block, but as boot parameter
> might
> +  * disable some of them and one or more IP has not implemented
> yet.
> +  * So we disable them on behalf.
> +  */
> + if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
> + list_for_each_entry_safe(obj, tmp, &con->head, node) {
> + if (!amdgpu_ras_is_supported(adev, obj-
> >head.block)) {
> + amdgpu_ras_feature_enable(adev, &obj-
> >head, 0);
> + /* there should be no any reference. */
> + WARN_ON(alive_obj(obj));
> + }
> + };
> + }
> +}
> +
>  /* do some fini work before IP fini as dependence */  int
> amdgpu_ras_pre_fini(struct amdgpu_device *adev)  { diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> index 2b6077762b91..7a35316baab0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> @@ -103,6 +103,8 @@ struct amdgpu_ras {
>   /* error handler data */
>   struct ras_err_handler_data *eh_data;
>   struct mutex recovery_lock;
> +
> + uint32_t flags;
>  };
> 
>  /* interfaces for IP */
> @@ -197,6 +199,7 @@ static inline int amdgpu_ras_reset_gpu(struct
> amdgp

Re: [PATCH 1/2] drm/amdgpu: let ras initialization a little noticeable

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: Pan, Xinhui
Sent: Tuesday, March 12, 2019 6:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Quan, Evan; Zhang, Hawking
Subject: [PATCH 1/2] drm/amdgpu: let ras initialization a little noticeable

add drm info output if ras initialized successfully.
add ras atomfirmware sanity check.

Signed-off-by: xinhui pan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 1f47974b1184..10ce40d2c040 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1357,8 +1357,9 @@ static void amdgpu_ras_check_supported(struct 
amdgpu_device *adev,
 adev->asic_type != CHIP_VEGA20)
 return;

-   if (amdgpu_atomfirmware_mem_ecc_supported(adev) ||
-   amdgpu_atomfirmware_sram_ecc_supported(adev))
+   if (adev->is_atom_fw &&
+   (amdgpu_atomfirmware_mem_ecc_supported(adev) ||
+amdgpu_atomfirmware_sram_ecc_supported(adev)))
 *hw_supported = AMDGPU_RAS_BLOCK_MASK;

 *supported = amdgpu_ras_enable == 0 ?
@@ -1398,6 +1399,10 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
 goto fs_out;

 amdgpu_ras_self_test(adev);
+
+   DRM_INFO("RAS INFO: ras initialized successfully, "
+   "hardware ability[%x] ras_mask[%x]\n",
+   con->hw_supported, con->supported);
 return 0;
 fs_out:
 amdgpu_ras_recovery_fini(adev);
--
2.17.1

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Re: [PATCH xf86-video-ati] Revert "glamor: Avoid glamor_create_pixmap for pixmaps backing windows"

[Deucher, Alexander]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Friday, March 8, 2019 5:51 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH xf86-video-ati] Revert "glamor: Avoid glamor_create_pixmap for 
pixmaps backing windows"

From: Michel Dänzer 

This reverts commit 274703087f80342f51fa69c935bb9a1cb0c4ae47.

Reports of visual corruption were bisected to this, e.g.
https://bugs.archlinux.org/task/61941 . I can reproduce this with Turks,
but not with Bonaire. I assume it's a Mesa/glamor bug, but let's revert
for now.

Signed-off-by: Michel Dänzer 
---
 src/radeon_glamor.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/radeon_glamor.c b/src/radeon_glamor.c
index 3e676f2dc..f1098381e 100644
--- a/src/radeon_glamor.c
+++ b/src/radeon_glamor.c
@@ -238,7 +238,7 @@ radeon_glamor_create_pixmap(ScreenPtr screen, int w, int h, 
int depth,
 if (info->shadow_primary) {
 if (usage != CREATE_PIXMAP_USAGE_BACKING_PIXMAP)
 return fbCreatePixmap(screen, w, h, depth, 
usage);
-   } else if (usage != CREATE_PIXMAP_USAGE_BACKING_PIXMAP) {
+   } else {
 pixmap = glamor_create_pixmap(screen, w, h, depth, 
usage);
 if (pixmap)
 return pixmap;
--
2.20.1

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Re: [PATCH] drm/amd/display: avoid passing enum as NULL pointer

[Deucher, Alexander]

Thanks for the patch.  We already have the fix queued:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-5.2-wip&id=672e78cab819ebe31e3b9b8abac367be8a110472

Alex

From: Arnd Bergmann 
Sent: Thursday, March 7, 2019 5:34 AM
To: Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; 
Zhou, David(ChunMing)
Cc: Nick Desaulniers; Arnd Bergmann; David Airlie; Daniel Vetter; Koo, Anthony; 
Cyr, Aric; Tatla, Harmanprit; Chalmers, Kenneth; Kumarasamy, Sivapiriyan; Kees 
Cook; Bayan Zabihiyan; Cheng, Tony; amd-gfx@lists.freedesktop.org; 
dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org
Subject: [PATCH] drm/amd/display: avoid passing enum as NULL pointer

The mod_freesync_build_vrr_infopacket() function uses rather obscure
calling conventions, where an enum is passed in through a pointer,
and a NULL pointer is expected to behave the same way as the zero-value
(TRANSFER_FUNC_UNKNOWN).

Trying to build this with clang results in a warning:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4601:3: error: 
expression which evaluates to zero treated
  as a null pointer constant of type 'const enum color_transfer_func *' 
[-Werror,-Wnon-literal-null-conversion]

Passing it by value instead of by reference makes the code simpler
and more conventional but should not change the behavior at all.

Fixes: c2791297013e ("drm/amd/display: Add color bit info to freesync 
infoframe")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 7 +++
 drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h  | 2 +-
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 94a84bc57c7a..6f32fe129880 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -724,7 +724,7 @@ static void build_vrr_infopacket_v1(enum signal_type signal,

 static void build_vrr_infopacket_v2(enum signal_type signal,
 const struct mod_vrr_params *vrr,
-   const enum color_transfer_func *app_tf,
+   const enum color_transfer_func app_tf,
 struct dc_info_packet *infopacket)
 {
 unsigned int payload_size = 0;
@@ -732,8 +732,7 @@ static void build_vrr_infopacket_v2(enum signal_type signal,
 build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);
 build_vrr_infopacket_data(vrr, infopacket);

-   if (app_tf != NULL)
-   build_vrr_infopacket_fs2_data(*app_tf, infopacket);
+   build_vrr_infopacket_fs2_data(app_tf, infopacket);

 build_vrr_infopacket_checksum(&payload_size, infopacket);

@@ -757,7 +756,7 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync 
*mod_freesync,
 const struct dc_stream_state *stream,
 const struct mod_vrr_params *vrr,
 enum vrr_packet_type packet_type,
-   const enum color_transfer_func *app_tf,
+   const enum color_transfer_func app_tf,
 struct dc_info_packet *infopacket)
 {
 /* SPD info packet for FreeSync
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h 
b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index 4222e403b151..645793b924cf 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -145,7 +145,7 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync 
*mod_freesync,
 const struct dc_stream_state *stream,
 const struct mod_vrr_params *vrr,
 enum vrr_packet_type packet_type,
-   const enum color_transfer_func *app_tf,
+   const enum color_transfer_func app_tf,
 struct dc_info_packet *infopacket);

 void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
--
2.20.0

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Re: [PATCH] drm/amdgpu: fix ras parameter descriptions

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Evan Quan 

Sent: Thursday, March 7, 2019 2:00 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Pan, Xinhui; Quan, Evan; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: fix ras parameter descriptions

The descriptions of modinfo wrongly show two parameters
for each feature(see below). This patch can fix this
incorrect outputs.

parm:   amdgpu_ras_enable:Enable RAS features on the GPU (0 = disable, 
1 = enable, -1 = auto (default))
parm:   ras_enable:int
parm:   amdgpu_ras_mask:Mask of RAS features to enable (default 
0x), only valid when ras_enable == 1
parm:   ras_mask:uint

Change-Id: I04f7e505cecca991f196802befd2006dc49b3dcf
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 38dbf6115c15..e0a7712d5d7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -512,18 +512,18 @@ MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 
0 = disable)");
 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);

 /*
- * DOC: amdgpu_ras_enable (int)
+ * DOC: ras_enable (int)
  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto 
(default))
  */
-MODULE_PARM_DESC(amdgpu_ras_enable, "Enable RAS features on the GPU (0 = 
disable, 1 = enable, -1 = auto (default))");
+MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = 
enable, -1 = auto (default))");
 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);

 /**
- * DOC: amdgpu_ras_mask (uint)
+ * DOC: ras_mask (uint)
  * Mask of RAS features to enable (default 0x), only valid when 
ras_enable == 1
  * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
  */
-MODULE_PARM_DESC(amdgpu_ras_mask, "Mask of RAS features to enable (default 
0x), only valid when ras_enable == 1");
+MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 
0x), only valid when ras_enable == 1");
 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);


--
2.21.0

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Re: [PATCH] drm/amdgpu: XGMI pstate switch initial support

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Liu, Shaoyun 

Sent: Wednesday, March 6, 2019 11:03 AM
To: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: XGMI pstate switch initial support

Ping

-Original Message-
From: Liu, Shaoyun 
Sent: Tuesday, March 5, 2019 11:25 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun 
Subject: [PATCH] drm/amdgpu: XGMI pstate switch initial support

Driver vote low to high pstate switch whenever there is an outstanding XGMI 
mapping request. Driver vote high to low pstate when all the outstanding XGMI 
mapping is terminated.

Change-Id: I499fb1c389077632fe9cfce4b6dc9a33deff6875
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  3 +++  
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 29 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c   | 15 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h   |  2 ++
 6 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f0dada9..c3c8392 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -930,6 +930,10 @@ struct amdgpu_device {

 int asic_reset_res;
 struct work_struct  xgmi_reset_work;
+
+   /* counter of mapped memory through xgmi */
+   atomic_txgmi_map_counter;
+
 };

 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device 
*bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 00def57..f28abb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2008,6 +2008,9 @@ static void 
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
 r = amdgpu_device_enable_mgpu_fan_boost();
 if (r)
 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
+
+   /*set to low pstate by default */
+   amdgpu_xgmi_set_pstate(adev, 0);
 }

 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) diff 
--git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 220a6a7..6f176bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -54,6 +54,7 @@ struct amdgpu_bo_va_mapping {
 uint64_t__subtree_last;
 uint64_toffset;
 uint64_tflags;
+   boolis_xgmi;
 };

 /* User space allocated BO in a VM */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index c0f315b..5765761 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -34,6 +34,7 @@
 #include "amdgpu_trace.h"
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_gmc.h"
+#include "amdgpu_xgmi.h"

 /**
  * DOC: GPUVM
@@ -2013,8 +2014,9 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 struct ttm_mem_reg *mem;
 struct drm_mm_node *nodes;
 struct dma_fence *exclusive, **last_update;
-   uint64_t flags;
 struct amdgpu_device *bo_adev = adev;
+   bool is_xgmi = false;
+   uint64_t flags;
 int r;

 if (clear || !bo) {
@@ -2036,6 +2038,10 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 if (bo) {
 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   if (adev != bo_adev &&
+   adev->gmc.xgmi.hive_id &&
+   adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id)
+   is_xgmi = true;
 } else {
 flags = 0x0;
 }
@@ -2054,6 +2060,19 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 }

 list_for_each_entry(mapping, &bo_va->invalids, list) {
+   if (mapping->is_xgmi != is_xgmi) {
+   if (is_xgmi) {
+   /* Adding an XGMI mapping to the PT */
+   if (atomic_inc_return(&adev->xgmi_map_counter) 
== 1)
+   amdgpu_xgmi_set_pstate(adev, 1);
+   } else {
+   /* Removing an XGMI mapping from the PT */
+   if (atomic_dec_return(&adev->xgmi_map_counter) 
== 0)
+   amdgpu_xgmi_set_pstate(adev, 0);
+   }
+   mapping->is_xgmi = is_xgmi;
+   }
+
 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
mapping,

Re: [PATCH] drm/amdkfd: fix a compiling error when CONFIG_HSA_AMD disalbed

[Deucher, Alexander]

Add a line like:

Fixes: 9032ea09e2d2ef ("drm/amdkfd: add RAS ECC event support")

With that added:
Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Huang, 
JinHuiEric 
Sent: Wednesday, March 6, 2019 10:59 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, JinHuiEric
Subject: [PATCH] drm/amdkfd: fix a compiling error when CONFIG_HSA_AMD disalbed

It fixes a commpiling error on commit
9032ea09e2d2ef0d10e5cd793713bf2eb21643c5
drm/amdkfd: add RAS ECC event support

Change-Id: I8792767726e28eed3a3fcf9072f608701be13c79
Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index fe1d736..acf8ae0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -640,4 +640,8 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
 {
 }
+
+void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
+{
+}
 #endif
--
2.7.4

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Re: [PATCH] drm/amdkfd: Add curly braces around idr_for_each_entry_continue loop

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Tuesday, March 5, 2019 6:20 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdkfd: Add curly braces around 
idr_for_each_entry_continue loop

From: Michel Dänzer 

The compiler pointed out that one if block unintentionally wasn't part
of the loop:

In file included from ./include/linux/kernfs.h:14,
 from ./include/linux/sysfs.h:16,
 from ./include/linux/kobject.h:20,
 from ./include/linux/device.h:16,
 from ./include/linux/node.h:18,
 from ./include/linux/memory.h:19,
 from drivers/gpu/drm//amd/amdgpu/../amdkfd/kfd_events.c:30:
drivers/gpu/drm//amd/amdgpu/../amdkfd/kfd_events.c: In function 
‘kfd_signal_reset_event’:
./include/linux/idr.h:212:2: warning: this ‘for’ clause does not guard... 
[-Wmisleading-indentation]
  for ((entry) = idr_get_next((idr), &(id));   \
  ^~~
drivers/gpu/drm//amd/amdgpu/../amdkfd/kfd_events.c:1038:3: note: in expansion 
of macro ‘idr_for_each_entry_continue’
   idr_for_each_entry_continue(&p->event_idr, ev, id)
   ^~~
drivers/gpu/drm//amd/amdgpu/../amdkfd/kfd_events.c:1043:4: note: ...this 
statement, but the latter is misleadingly indented as if it were guarded by the 
‘for’
if (ev->type == KFD_EVENT_TYPE_MEMORY &&
^~

Fixes: "drm/amdkfd: add RAS ECC event support"
Signed-off-by: Michel Dänzer 
---

This is one reason why I think it's better to always use curly braces
around multiple lines, even if it happens to be a single statement.

 drivers/gpu/drm/amd/amdkfd/kfd_events.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 97c984684973..6e1d41c5bf86 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -1035,7 +1035,7 @@ void kfd_signal_reset_event(struct kfd_dev *dev)
 hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
 mutex_lock(&p->event_mutex);
 id = KFD_FIRST_NONSIGNAL_EVENT_ID;
-   idr_for_each_entry_continue(&p->event_idr, ev, id)
+   idr_for_each_entry_continue(&p->event_idr, ev, id) {
 if (ev->type == KFD_EVENT_TYPE_HW_EXCEPTION) {
 ev->hw_exception_data = hw_exception_data;
 set_event(ev);
@@ -1045,6 +1045,7 @@ void kfd_signal_reset_event(struct kfd_dev *dev)
 ev->memory_exception_data = 
memory_exception_data;
 set_event(ev);
 }
+   }
 mutex_unlock(&p->event_mutex);
 }
 srcu_read_unlock(&kfd_processes_srcu, idx);
--
2.20.1

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Re: [PATCH] drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Tom St Denis 

Sent: Tuesday, March 5, 2019 10:17 AM
To: amd-gfx mailing list
Subject: Re: [PATCH] drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers

Hi,

Alex can I get an RB on this :-)

Thanks,
Tom

On Mon, Mar 4, 2019 at 10:59 AM StDenis, Tom 
mailto:tom.stde...@amd.com>> wrote:
Signed-off-by: Tom St Denis mailto:tom.stde...@amd.com>>
---
 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h  | 2 ++
 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 5 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
index 442ca7c471a5..6109f5ad25ad 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
@@ -141,6 +141,8 @@
 #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX
1
 #define mmUVD_GPCOM_VCPU_DATA1 
0x03c5
 #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX
1
+#define mmUVD_ENGINE_CNTL  
0x03c6
+#define mmUVD_ENGINE_CNTL_BASE_IDX 
1
 #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG  
0x03d2
 #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX 
1
 #define mmUVD_UDEC_ADDR_CONFIG 
0x03d3
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
index 63457f9df4c5..f84bed6eecb9 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
@@ -312,6 +312,11 @@
 //UVD_GPCOM_VCPU_DATA1
 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 
   0x0
 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK   
   0xL
+//UVD_ENGINE_CNTL
+#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
+#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
 //UVD_UDEC_DBW_UV_ADDR_CONFIG
 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT  
   0x0
 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT   
   0x3
--
2.17.2

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Re: [PATCH] drm/amdgpu: also reroute VMC and UMD to IH ring 1 on Vega 20

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Christian 
König 
Sent: Monday, March 4, 2019 1:36 PM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: also reroute VMC and UMD to IH ring 1 on Vega 20

Same patch we alredy did for Vega10. Just re-route page faults to a separate
ring to avoid drowning in interrupts.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 36 ++
 1 file changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 3f59a4477a7b..2b3429d90690 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -33,6 +33,9 @@
 #include "sdma0/sdma0_4_0_offset.h"
 #include "nbio/nbio_7_4_offset.h"

+#include "oss/osssys_4_0_offset.h"
+#include "oss/osssys_4_0_sh_mask.h"
+
 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
@@ -224,6 +227,37 @@ static int psp_v11_0_bootloader_load_sos(struct 
psp_context *psp)
 return ret;
 }

+static void psp_v11_0_reroute_ih(struct psp_context *psp)
+{
+   struct amdgpu_device *adev = psp->adev;
+   uint32_t tmp;
+
+   /* Change IH ring for VMC */
+   tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+   mdelay(20);
+   psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+
+   /* Change IH ring for UMC */
+   tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+   mdelay(20);
+   psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+}
+
 static int psp_v11_0_ring_init(struct psp_context *psp,
   enum psp_ring_type ring_type)
 {
@@ -231,6 +265,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
 struct psp_ring *ring;
 struct amdgpu_device *adev = psp->adev;

+   psp_v11_0_reroute_ih(psp);
+
 ring = &psp->km_ring;

 ring->ring_type = ring_type;
--
2.17.1

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Re: [PATCH] drm/amdgpu: reroute VMC and UMD to IH ring 1

[Deucher, Alexander]

Would be good to verify this across all vega parts (10/12/20).  Other than that:
Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Christian 
König 
Sent: Monday, March 4, 2019 8:15 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: reroute VMC and UMD to IH ring 1

Page faults can easily overwhelm the interrupt handler.

So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h |  1 +
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 36 +
 2 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h 
b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index f3a7d207af07..2f79765b4bdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -43,6 +43,7 @@ enum psp_gfx_crtl_cmd_id
 GFX_CTRL_CMD_ID_ENABLE_INT  = 0x0005,   /* enable PSP-to-Gfx 
interrupt */
 GFX_CTRL_CMD_ID_DISABLE_INT = 0x0006,   /* disable PSP-to-Gfx 
interrupt */
 GFX_CTRL_CMD_ID_MODE1_RST   = 0x0007,   /* trigger the Mode 1 
reset */
+GFX_CTRL_CMD_ID_GBR_IH_SET  = 0x0008,   /* set Gbr IH_RB_CNTL 
registers */
 GFX_CTRL_CMD_ID_CONSUME_CMD = 0x000A,   /* send interrupt to psp 
for updating write pointer of vf */
 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C, /* destroy GPCOM ring */

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 0487e3a4e9e7..143f0fae69d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -37,6 +37,9 @@
 #include "sdma0/sdma0_4_0_offset.h"
 #include "nbio/nbio_6_1_offset.h"

+#include "oss/osssys_4_0_offset.h"
+#include "oss/osssys_4_0_sh_mask.h"
+
 MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
 MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
 MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
@@ -252,6 +255,37 @@ static int psp_v3_1_ring_init(struct psp_context *psp,
 return 0;
 }

+static void psp_v3_1_reroute_ih(struct psp_context *psp)
+{
+   struct amdgpu_device *adev = psp->adev;
+   uint32_t tmp;
+
+   /* Change IH ring for VMC */
+   tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+   mdelay(20);
+   psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+
+   /* Change IH ring for UMC */
+   tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
+   tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+   mdelay(20);
+   psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+}
+
 static int psp_v3_1_ring_create(struct psp_context *psp,
 enum psp_ring_type ring_type)
 {
@@ -260,6 +294,8 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
 struct psp_ring *ring = &psp->km_ring;
 struct amdgpu_device *adev = psp->adev;

+   psp_v3_1_reroute_ih(psp);
+
 /* Write low address of the ring to C2PMSG_69 */
 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
--
2.17.1

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Re: [PATCH xf86-video-ati 2/2] dri2: Call drm_queue_handle_deferred in dri2_deferred_event

[Deucher, Alexander]

Series is:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Friday, March 1, 2019 12:35 PM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH xf86-video-ati 2/2] dri2: Call drm_queue_handle_deferred in 
dri2_deferred_event

From: Michel Dänzer 

drm_queue_handler just puts the event on the signalled list; without
calling drm_queue_handle_deferred, actual processing of the event may be
delayed indefinitely, e.g. until another event arrives from the kernel.

This could result in DRI2 clients hanging during DPMS off.

Fixes: ba83a866af5a "Add radeon_drm_handle_event wrapper for
 drmHandleEvent"
(Ported from amdgpu commit 09be74a3d1dd9604336d9a27f98d132b262dcbaf)

Signed-off-by: Michel Dänzer 
---
 src/radeon_dri2.c | 19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index b5d6835c9..a9f14e8d8 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -979,12 +979,18 @@ CARD32 radeon_dri2_deferred_event(OsTimerPtr timer, 
CARD32 now, pointer data)
 if (ret) {
 xf86DrvMsg(scrn->scrnIndex, X_ERROR,
"%s cannot get current time\n", __func__);
-   if (event_info->drm_queue_seq)
+
+   if (event_info->drm_queue_seq) {
 drmmode_crtc->drmmode->event_context.
 vblank_handler(pRADEONEnt->fd, 0, 0, 0,
(void*)event_info->drm_queue_seq);
-   else
+   drmmode_crtc->wait_flip_nesting_level++;
+   radeon_drm_queue_handle_deferred(crtc);
+
+   } else {
 radeon_dri2_frame_event_handler(crtc, 0, 0, data);
+   }
+
 return 0;
 }
 /*
@@ -995,13 +1001,18 @@ CARD32 radeon_dri2_deferred_event(OsTimerPtr timer, 
CARD32 now, pointer data)
 delta_seq = delta_t * drmmode_crtc->dpms_last_fps;
 delta_seq /= 100;
 frame = (CARD64)drmmode_crtc->dpms_last_seq + delta_seq;
-if (event_info->drm_queue_seq)
+
+if (event_info->drm_queue_seq) {
 drmmode_crtc->drmmode->event_context.
 vblank_handler(pRADEONEnt->fd, frame, drm_now / 100,
drm_now % 100,
(void*)event_info->drm_queue_seq);
-else
+   drmmode_crtc->wait_flip_nesting_level++;
+   radeon_drm_queue_handle_deferred(crtc);
+} else {
 radeon_dri2_frame_event_handler(crtc, frame, drm_now, data);
+}
+
 return 0;
 }

--
2.20.1

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RE: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT info

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Kuehling, Felix
> Sent: Thursday, February 28, 2019 11:09 AM
> To: Koenig, Christian ; Russell, Kent
> ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT
> info
> 
> On 2/28/2019 9:56 AM, Christian König wrote:
> > Am 28.02.19 um 16:32 schrieb Russell, Kent:
> >> Add 3 files that return:
> >> The total amount of VRAM and the current total used VRAM The total
> >> amount of VRAM and the current total used visible VRAM The total GTT
> >> size and the current total of used GTT
> >>
> >> Each returns 2 integers, total and used, in bytes
> >
> > Well that is a good start, but unfortunately violates the rules for
> > sysfs. You need to return one value per file.
> 
> Is this rule written down anywhere. I see that space-separated lists of things
> are common. E.g. scaling_available_governors in the cpufreq directories.
> 
> In Documentation/admin-guide/sysfs-rules.rst I don't see any rule about
> single value per file. Maybe that's because these rules are more from user
> mode usage of sysfs rather than for kernel implementations.

This (two values) is also more consistent with the pcie bw file IIRC.

Alex

> 
> Regards,
>    Felix
> 
> 
> >
> > So you should create 6 files in total.
> >
> > Regards,
> > Christian.
> >
> >>
> >> Change-Id: I0bd702b166b4253887ef76fb1bba8b9aadc7e2c5
> >> Signed-off-by: Kent Russell 
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c  | 36 +++
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 67
> >> 
> >>   2 files changed, 103 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> >> index da7b1b92d9cf..adfa211c5152 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> >> @@ -36,6 +36,30 @@ struct amdgpu_gtt_node {
> >>   struct ttm_buffer_object *tbo;
> >>   };
> >>   +/**
> >> + * DOC: mem_info_gtt
> >> + *
> >> + * The amdgpu driver provides a sysfs API for reporting current GTT
> >> information
> >> + * The file mem_info_gtt is used for this.
> >> + * The file returns the total size of the GTT block and the current
> >> amount of
> >> + * used GTT as 2 separate integers, in bytes  */ static ssize_t
> >> +amdgpu_mem_info_gtt_show(struct device *dev,
> >> +    struct device_attribute *attr, char *buf) {
> >> +    struct drm_device *ddev = dev_get_drvdata(dev);
> >> +    struct amdgpu_device *adev = ddev->dev_private;
> >> +    uint64_t used_gtt, total_gtt;
> >> +
> >> +    used_gtt =
> >> +amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
> >> +    total_gtt = (adev->mman.bdev.man[TTM_PL_TT].size) * PAGE_SIZE;
> >> +
> >> +    return snprintf(buf, PAGE_SIZE, "%llu %llu\n",
> >> +  total_gtt, used_gtt); }
> >> +
> >> +static DEVICE_ATTR(mem_info_gtt, S_IRUGO,
> amdgpu_mem_info_gtt_show,
> >> NULL);
> >> +
> >>   /**
> >>    * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
> >>    *
> >> @@ -50,6 +74,7 @@ static int amdgpu_gtt_mgr_init(struct
> >> ttm_mem_type_manager *man,
> >>   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
> >>   struct amdgpu_gtt_mgr *mgr;
> >>   uint64_t start, size;
> >> +    int ret;
> >>     mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
> >>   if (!mgr)
> >> @@ -61,6 +86,13 @@ static int amdgpu_gtt_mgr_init(struct
> >> ttm_mem_type_manager *man,
> >>   spin_lock_init(&mgr->lock);
> >>   atomic64_set(&mgr->available, p_size);
> >>   man->priv = mgr;
> >> +
> >> +    ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt);
> >> +    if (ret) {
> >> +    DRM_ERROR("Failed to create device file mem_info_gtt\n");
> >> +    return ret;
> >> +    }
> >> +
> >>   return 0;
> >>   }
> >>   @@ -74,12 +106,16 @@ static int amdgpu_gtt_mgr_init(struct
> >> ttm_mem_type_manager *man,
> >>    */
> >>   static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
> >>   {
> >> +    struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
> >>   struct amdgpu_gtt_mgr *mgr = man->priv;
> >>   spin_lock(&mgr->lock);
> >>   drm_mm_takedown(&mgr->mm);
> >>   spin_unlock(&mgr->lock);
> >>   kfree(mgr);
> >>   man->priv = NULL;
> >> +
> >> +    device_remove_file(adev->dev, &dev_attr_mem_info_gtt);
> >> +
> >>   return 0;
> >>   }
> >>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> >> index 3f9d5d00c9b3..d0bada997cba 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> >> @@ -32,6 +32,55 @@ struct amdgpu_vram_mgr {
> >>   atomic64_t vis_usage;
> >>   };
> >>   +/**
> >> + * DOC: mem_info_vram
> >> + *
> >> + * The amdgpu driver provides a sysfs API for reporting current VRAM
> >> information
> >> + * The file mem_info_vram is used 

RE: [PATCH] drm/amdgpu: Bump amdgpu version for per-flip plane tiling updates

[Deucher, Alexander]

Acked-by: Alex Deucher 

> -Original Message-
> From: amd-gfx  On Behalf Of
> Nicholas Kazlauskas
> Sent: Thursday, February 28, 2019 10:00 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Michel Dänzer ; Kazlauskas, Nicholas
> ; Marek Olšák 
> Subject: [PATCH] drm/amdgpu: Bump amdgpu version for per-flip plane tiling
> updates
> 
> To help xf86-video-amdgpu and mesa know DC supports updating the tiling
> attributes for a framebuffer per-flip.
> 
> Cc: Michel Dänzer 
> Cc: Marek Olšák 
> Signed-off-by: Nicholas Kazlauskas 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 223013ef8466..ae4e3eeb4ae2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -74,9 +74,10 @@
>   * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
>   * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
>   * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
> + * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
>   */
>  #define KMS_DRIVER_MAJOR 3
> -#define KMS_DRIVER_MINOR 30
> +#define KMS_DRIVER_MINOR 31
>  #define KMS_DRIVER_PATCHLEVEL0
> 
>  int amdgpu_vram_limit = 0;
> --
> 2.17.1
> 
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RE: [PATCH 2/2] drm/amd/powerplay: override duty cycle on Vega20

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx  On Behalf Of Evan
> Quan
> Sent: Thursday, February 28, 2019 5:32 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan 
> Subject: [PATCH 2/2] drm/amd/powerplay: override duty cycle on Vega20
> 
> This is needed for the new SMC firmwares only.
> 
> Change-Id: I5934e5161ec53c1dd73cb1542ef6b738ad2e620c
> Signed-off-by: Evan Quan 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c   | 16
> 
>  drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h |  3 ++-
>  2 files changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index 9aa7bec1b5fe..d35f60ab3404 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -828,6 +828,17 @@ static int vega20_override_pcie_parameters(struct
> pp_hwmgr *hwmgr)
>   return 0;
>  }
> 
> +static int vega20_override_duty_cycle(struct pp_hwmgr *hwmgr) {
> + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr-
> >adev);
> + int ret = 0;
> +
> + if (adev->pm.fw_version >= 0x00282700)
> + ret = smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_OverrideDutyCycle);
> +
> + return ret;
> +}
> +
>  static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)  {
>   struct vega20_hwmgr *data =
> @@ -1644,6 +1655,11 @@ static int vega20_enable_dpm_tasks(struct
> pp_hwmgr *hwmgr)
>   "[EnableDPMTasks] Failed to enable all smu
> features!",
>   return result);
> 
> + result = vega20_override_duty_cycle(hwmgr);
> + PP_ASSERT_WITH_CODE(!result,
> + "[EnableDPMTasks] Failed to override duty cycle!",
> + return result);
> +
>   result = vega20_override_pcie_parameters(hwmgr);
>   PP_ASSERT_WITH_CODE(!result,
>   "[EnableDPMTasks] Failed to override pcie
> parameters!", diff --git
> a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> index 4f63a736ea0e..4a1e01f04cf5 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> @@ -119,7 +119,8 @@
>  #define PPSMC_MSG_PrepareMp1ForShutdown  0x5A
>  #define PPSMC_MSG_SetMGpuFanBoostLimitRpm0x5D
>  #define PPSMC_MSG_GetAVFSVoltageByDpm0x5F
> -#define PPSMC_Message_Count  0x60
> +#define PPSMC_MSG_OverrideDutyCycle  0x64
> +#define PPSMC_Message_Count  0x65
> 
>  typedef uint32_t PPSMC_Result;
>  typedef uint32_t PPSMC_Msg;
> --
> 2.21.0
> 
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Re: KASAN caught amdgpu / HMM use-after-free

[Deucher, Alexander]

Go ahead an apply it to amd-staging-drm-next.  It'll naturally fall out when I 
rebase it.

Alex

From: amd-gfx  on behalf of Yang, Philip 

Sent: Wednesday, February 27, 2019 1:05 PM
To: Michel Dänzer; Jérôme Glisse
Cc: linux...@kvack.org; amd-gfx@lists.freedesktop.org
Subject: Re: KASAN caught amdgpu / HMM use-after-free

amd-staging-drm-next will rebase to kernel 5.1 to pickup this fix
automatically. As a short-term workaround, please cherry-pick this fix
into your local repository.

Regards,
Philip

On 2019-02-27 12:33 p.m., Michel Dänzer wrote:
> On 2019-02-27 6:14 p.m., Yang, Philip wrote:
>> Hi Michel,
>>
>> Yes, I found the same issue and the bug has been fixed by Jerome:
>>
>> 876b462120aa mm/hmm: use reference counting for HMM struct
>>
>> The fix is on hmm-for-5.1 branch, I cherry-pick it into my local branch
>> to workaround the issue.
>
> Please push it to amd-staging-drm-next, so that others don't run into
> the issue as well.
>
>
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RE: [PATCH libdrm] libdrm: Fix issue about differrent domainID but same BDF

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx  On Behalf Of Emil
> Velikov
> Sent: Monday, February 25, 2019 8:09 AM
> To: Alex Deucher 
> Cc: Deng, Emily ; Maling list - DRI developers  de...@lists.freedesktop.org>; amd-gfx list 
> Subject: Re: [PATCH libdrm] libdrm: Fix issue about differrent domainID but
> same BDF
> 
> Hi all,
> 
> This patch causes unnecessary round trip by openning the nodes. As
> mentioned previously this could be trivially fixed [1].
> 
> Even Emily acknowledged that [1], yet the sub-par fix was merged. Can we
> revert+fixup this properly?
> 

Sorry, I totally missed your reply.  I'm having Internet issues at the moment 
so if you want to revert for now, I'll work with Emily to address your 
suggestions later in the week or next.  Emily, can you take a look at 
addressing Emil's concerns with an updated patch?

Alex

> Thanks
> Emil
> 
> [1] https://lists.freedesktop.org/archives/amd-gfx/2019-
> February/031573.html
> 
> On Fri, 22 Feb 2019 at 21:05, Alex Deucher  wrote:
> >
> > Pushed.  Thanks!
> >
> > Alex
> >
> > On Thu, Feb 21, 2019 at 9:36 PM Deng, Emily 
> wrote:
> > >
> > > Hi Alex,
> > > Please help, thanks.
> > >
> > > Best wishes
> > > Emily Deng
> > >
> > >
> > >
> > > >-Original Message-
> > > >From: Alex Deucher 
> > > >Sent: Friday, February 22, 2019 12:13 AM
> > > >To: Deng, Emily ; Maling list - DRI developers
> > > >
> > > >Cc: amd-gfx list 
> > > >Subject: Re: [PATCH libdrm] libdrm: Fix issue about differrent
> > > >domainID but same BDF
> > > >
> > > >On Thu, Feb 14, 2019 at 2:53 AM Emily Deng 
> wrote:
> > > >>
> > > >> For multiple GPUs which has the same BDF, but has different
> > > >> domain ID, the drmOpenByBusid will return the wrong fd when startx.
> > > >>
> > > >> The reproduce sequence as below:
> > > >> 1. Call drmOpenByBusid to open Card0, then will return the right
> > > >> fd0, and the
> > > >> fd0 is master privilege;
> > > >> 2. Call drmOpenByBusid to open Card1. In function drmOpenByBusid,
> > > >> it will open Card0 first, this time, the fd1 for opening Card0 is
> > > >> not master privilege, and will call drmSetInterfaceVersion to
> > > >> identify the domain ID feature, as the fd1 is not master
> > > >> privilege, then drmSetInterfaceVersion will fail, and then won't
> > > >> compare domain ID, then
> > > >return the wrong fd for Card1.
> > > >>
> > > >> Solution:
> > > >> First loop search the best match fd about drm 1.4.
> > > >>
> > > >> Signed-off-by: Emily Deng 
> > > >
> > > >Reviewed-by: Alex Deucher 
> > > >
> > > >Do you need someone to commit this for you?
> > > >
> > > >Alex
> > > >
> > > >> ---
> > > >>  xf86drm.c | 23 +++
> > > >>  1 file changed, 23 insertions(+)
> > > >>
> > > >> diff --git a/xf86drm.c b/xf86drm.c index 336d64d..b60e029 100644
> > > >> --- a/xf86drm.c
> > > >> +++ b/xf86drm.c
> > > >> @@ -584,11 +584,34 @@ static int drmOpenByBusid(const char
> > > >> *busid, int
> > > >type)
> > > >>  if (base < 0)
> > > >>  return -1;
> > > >>
> > > >> +/* We need to try for 1.4 first for proper PCI domain
> > > >> + support */
> > > >>  drmMsg("drmOpenByBusid: Searching for BusID %s\n", busid);
> > > >>  for (i = base; i < base + DRM_MAX_MINOR; i++) {
> > > >>  fd = drmOpenMinor(i, 1, type);
> > > >>  drmMsg("drmOpenByBusid: drmOpenMinor returns %d\n", fd);
> > > >>  if (fd >= 0) {
> > > >> +sv.drm_di_major = 1;
> > > >> +sv.drm_di_minor = 4;
> > > >> +sv.drm_dd_major = -1;/* Don't care */
> > > >> +sv.drm_dd_minor = -1;/* Don't care */
> > > >> +if (!drmSetInterfaceVersion(fd, &sv)) {
> > > >> +buf = drmGetBusid(fd);
> > > >> +drmMsg("drmOpenByBusid: drmGetBusid reports %s\n",
> buf);
> > > >> +if (buf && drmMatchBusID(buf, busid, 1)) {
> > > >> +drmFreeBusid(buf);
> > > >> +return fd;
> > > >> +}
> > > >> +if (buf)
> > > >> +drmFreeBusid(buf);
> > > >> +}
> > > >> +close(fd);
> > > >> +}
> > > >> +}
> > > >> +
> > > >> +   for (i = base; i < base + DRM_MAX_MINOR; i++) {
> > > >> +fd = drmOpenMinor(i, 1, type);
> > > >> +drmMsg("drmOpenByBusid: drmOpenMinor returns %d\n", fd);
> > > >> +if (fd >= 0) {
> > > >>  /* We need to try for 1.4 first for proper PCI domain 
> > > >> support
> > > >>   * and if that fails, we know the kernel is busted
> > > >>   */
> > > >> --
> > > >> 2.7.4
> > > >>
> > > >> ___
> > > >> amd-gfx mailing list
> > > >> amd-gfx@lists.freedesktop.org
> > > >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> > ___
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> > https://lists.freedesktop.org/mailman/listinfo/d

RE: [PATCH 2/2] drm/amdgpu: use REG32_PCIE wrapper instead for psp

[Deucher, Alexander]

Series is:
Reviewed-by: Alex Deucher 

> -Original Message-
> From: amd-gfx  On Behalf Of
> Huang Rui
> Sent: Monday, February 25, 2019 2:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Zhang, Hawking
> 
> Subject: [PATCH 2/2] drm/amdgpu: use REG32_PCIE wrapper instead for psp
> 
> This patch uses REG32_PCIE wrapper instead of writting pci_index2 and
> reading
> pci_data2 for psp. This sequence should be protected by pcie_idx_lock.
> 
> Suggested-by: Hawking Zhang 
> Signed-off-by: Huang Rui 
> ---
>  drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index 38deb57..54926a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -500,9 +500,7 @@ static bool psp_v3_1_smu_reload_quirk(struct
> psp_context *psp)
>   struct amdgpu_device *adev = psp->adev;
>   uint32_t reg;
> 
> - reg = smnMP1_FIRMWARE_FLAGS | 0x03b0;
> - WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg);
> - reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2);
> + reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b0);
>   return (reg &
> MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;  }
> 
> --
> 2.7.4
> 
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RE: [PATCH] drm/amd/powerplay: set max fan target temperature as 105C

[Deucher, Alexander]

Acked-by: Alex Deucher 

> -Original Message-
> From: amd-gfx  On Behalf Of Evan
> Quan
> Sent: Monday, February 25, 2019 2:07 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan 
> Subject: [PATCH] drm/amd/powerplay: set max fan target temperature as
> 105C
> 
> A workaround to override the fan target temperature in SMC table.
> 
> Change-Id: I67845c2fe5f51abde1ac483a979bde43ce2f26d3
> Signed-off-by: Evan Quan 
> ---
>  .../powerplay/hwmgr/vega20_processpptables.c| 17
> +
>  1 file changed, 17 insertions(+)
> 
> diff --git
> a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
> index 97f8a1a970c3..7a7f15d0c53a 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
> @@ -32,6 +32,8 @@
>  #include "cgs_common.h"
>  #include "vega20_pptable.h"
> 
> +#define VEGA20_FAN_TARGET_TEMPERATURE_OVERRIDE 105
> +
>  static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
>   enum phm_platform_caps cap)
>  {
> @@ -798,6 +800,17 @@ static int append_vbios_pptable(struct pp_hwmgr
> *hwmgr, PPTable_t *ppsmc_pptable
>   return 0;
>  }
> 
> +static int override_powerplay_table_fantargettemperature(struct
> +pp_hwmgr *hwmgr) {
> + struct phm_ppt_v3_information *pptable_information =
> + (struct phm_ppt_v3_information *)hwmgr->pptable;
> + PPTable_t *ppsmc_pptable = (PPTable_t
> +*)(pptable_information->smc_pptable);
> +
> + ppsmc_pptable->FanTargetTemperature =
> +VEGA20_FAN_TARGET_TEMPERATURE_OVERRIDE;
> +
> + return 0;
> +}
> +
>  #define VEGA20_ENGINECLOCK_HARDMAX 198000  static int
> init_powerplay_table_information(
>   struct pp_hwmgr *hwmgr,
> @@ -887,6 +900,10 @@ static int init_powerplay_table_information(
> 
> 
>   result = append_vbios_pptable(hwmgr, (pptable_information-
> >smc_pptable));
> + if (result)
> + return result;
> +
> + result = override_powerplay_table_fantargettemperature(hwmgr);
> 
>   return result;
>  }
> --
> 2.20.1
> 
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Re: [PATCH] drm/amd/display: don't call dm_pp_ function from an fpu block

[Deucher, Alexander]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Harry 
Wentland 
Sent: Friday, February 22, 2019 10:39 AM
To: amd-gfx@lists.freedesktop.org
Cc: robdcl...@gmail.com; Wentland, Harry; sta...@vger.kernel.org
Subject: [PATCH] drm/amd/display: don't call dm_pp_ function from an fpu block

Powerplay functions called from dm_pp_* functions tend to do a
mutex_lock which isn't safe to do inside a kernel_fpu_begin/end block as
those will disable/enable preemption.

Rearrange the dm_pp_get_clock_levels_by_type_with_voltage calls to make
sure they happen outside of kernel_fpu_begin/end.

Cc: sta...@vger.kernel.org
Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 2a807b9f77f7..5955634f6e27 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1348,12 +1348,12 @@ void dcn_bw_update_from_pplib(struct dc *dc)
 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
 bool res;

-   kernel_fpu_begin();
-
 /* TODO: This is not the proper way to obtain 
fabric_and_dram_bandwidth, should be min(fclk, memclk) */
 res = dm_pp_get_clock_levels_by_type_with_voltage(
 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);

+   kernel_fpu_begin();
+
 if (res)
 res = verify_clock_values(&fclks);

@@ -1372,9 +1372,13 @@ void dcn_bw_update_from_pplib(struct dc *dc)
 } else
 BREAK_TO_DEBUGGER();

+   kernel_fpu_end();
+
 res = dm_pp_get_clock_levels_by_type_with_voltage(
 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);

+   kernel_fpu_begin();
+
 if (res)
 res = verify_clock_values(&dcfclks);

--
2.19.1

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Re: [PATCH] drm/amdgpu: disable userptr if swiotlb is active

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Christian 
König 
Sent: Wednesday, February 20, 2019 8:46 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: disable userptr if swiotlb is active

Otherwise we can't be sure that we won't end up with a bounce buffer.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index d21dd2f369da..abc65633119b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -289,6 +289,10 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void 
*data,
 if (offset_in_page(args->addr | args->size))
 return -EINVAL;

+   /* We can't do this when swiotlb is active */
+   if (adev->needs_swiotlb)
+   return -ENXIO;
+
 /* reject unknown flag values */
 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
--
2.17.1

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Re: [PATCH] drm/amdgpu: disable bulk moves for now

[Deucher, Alexander]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Christian 
König 
Sent: Wednesday, February 20, 2019 9:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: sta...@vger.kernel.org
Subject: [PATCH] drm/amdgpu: disable bulk moves for now

The changes to fix those are two invasive for backporting.

Just disable the feature in 4.20 and 5.0.

Signed-off-by: Christian König 
Cc: [4.20+]
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 0877ff9a9594..c3643dde3e9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -637,12 +637,14 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device 
*adev,
 struct ttm_bo_global *glob = adev->mman.bdev.glob;
 struct amdgpu_vm_bo_base *bo_base;

+#if 0
 if (vm->bulk_moveable) {
 spin_lock(&glob->lru_lock);
 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
 spin_unlock(&glob->lru_lock);
 return;
 }
+#endif

 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));

--
2.14.1

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Re: [PATCH 000/138] The new SW SMU driver of amdgpu

[Deucher, Alexander]

Series is:
Acked-by: Alex Deucher 

From: Huang, Ray
Sent: Wednesday, February 20, 2019 7:51 AM
To: Huang, Ray; amd-gfx@lists.freedesktop.org; Deucher, Alexander
Cc: Gao, Likun; Wang, Kevin(Yang); Gui, Jack
Subject: RE: [PATCH 000/138] The new SW SMU driver of amdgpu

Ping.
May I have your comments?

Thanks,
Ray

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Friday, January 25, 2019 6:23 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Gao, Likun ; Wang, Kevin(Yang)
> ; Huang, Ray ; Gui, Jack
> 
> Subject: [PATCH 000/138] The new SW SMU driver of amdgpu
>
> Hi all,
>
> The series of patches are to implement a new SW SMU driver for future asics.
>
> Background:
> The powerplay driver will be retired. The final version is for vega20 with
> SMU11. However, the future asic will use the new swSMU framework to
> implement as
> well. Here is the first version of new sw smu driver that is basing on vega20.
>
> Purpose:
> We would like to do re-arch for linux power codes to use a new sw SMU ip
> block
> for future asics. We hope to write a simple and readable framework for Linux.
>
> Currently, the default path is still with powerplay on vega20. So far we don’t
> plan to switch default path to new swSMU design for vega20. And we can
> use the
> module parameter amdgpu_dpm to switch it to new SW SMU design
> (modprobe amdgpu
> dpm=1).
>
> Development Items:
> - Setup new SMU IP block skeleton.
> - Implement SMC firmware loading function.
> - Implement SMC table data structure.
> - Implement SMU v11 indirect register (MP1) read/write and SMC message
> sending
>   helpers.
> - Implement SMU v11 SMC table initialization (read from vbios, parse,
> populate,
>   and write back to smc).
> - Implement SMU v11 memory pool location function.
> - Enable DPM feature for SMU v11 and implement DPM control callback
> function.
> - Enable interfaces for starting tools.
> - Implement SMU v11 power control and power containment functions.
> - Implement and enable SMU v11 thermal/fan control function.
> - Implement SMU interfaces placeholder for DC, VCN, and KFD driver.
> - Enable and align sys interface in the amdgpu_pm.c.
>
> So far, Kevin, Likun, Jack, and I have enabled features such as dpm, od,
> thermal, and etc. with new sw smu driver. (Thanks to Kevin, Likun and Jack's
> great effort!)
>
> Any comments are warm for us.
>
> Thanks & Best Regards!
> Ray
>
>
> Chengming Gui (14):
>   drm/amd/powerplay: implement power_dpm_state sys interface for
> SMU11
>   drm/amd/powerplay: add watermarks related data structs and function
> for SMU11.
>   drm/amd/powerplay: implement pp_power_profile_mode sys inerface for
> SMU11
>   drm/amd/powerplay: add display_config to handle display config for
> SMU11.
>   drm/amd/powerplay: add mclk_latency_table struct and smu_clocks struct
> for SMU11
>   drm/amd/powerplay: add enable_umd_pstate functions for SMU11
>   drm/amd/powerplay: add get_profiling_clk_mask functions for SMU11
>   drm/amd/powerplay: add set_uclk_to_highest_level for SMU11
>   drm/amd/powerplay: add display_config_changed for SMU11.
>   drm/amd/powerplay: add apply_clock_adjust_rules for SMU11.
>   drm/amd/powerplay: add vega20_notify_smc_display_config functions for
> SMU11
>   drm/amd/powerplay: add vega20_find/force_higest/lowest_dpm for
> SMU11
>   drm/amd/powerplay: add vega20_unforce_dpm_levels for SMU11.
>   drm/amd/powerplay: implement power_dpm_force_performance_level
> for
> SMU11
>
> Huang Rui (53):
>   drm/amd/powerplay: add new smu ip block
>   drm/amd/powerplay: add smu11 sub block for SMU IP
>   drm/amd/powerplay: add firmware loading interface
>   drm/amd/powerplay: add fw load checking interface
>   drm/amd/powerplay: add interface to read pptable from vbios
>   drm/amd/powerplay: add placeholder of smu_initialize_pptable
>   drm/amd/powerplay: add interface to init smc tables (v2)
>   drm/amd/powerplay: add interface to init power (v2)
>   drm/amd/powerplay: add interface to get vbios bootup values (v2)
>   drm/amd/powerplay: add interface to check pptable (v2)
>   drm/amd/powerplay: add interface to init fb allocations (v2)
>   drm/amd/powerplay: add interface to parse pptable (v2)
>   drm/amd/powerplay: add interface to populate smc pptable (v2)
>   drm/amd/powerplay: add interface to check fw version (v2)
>   drm/amd/powerplay: add interface to write pptable (v2)
>   drm/amd/powerplay: add interface to set min dcef deep sleep (v2)
>   drm/amd/powerplay: add interface to set tool table location (v2)
>   drm/amd/powerplay: add interface to allocate memory pool 

Re: [PATCH] drm/amdgpu: fix dma mask check in gmc_v6_0.c

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Christian 
König 
Sent: Wednesday, February 20, 2019 7:47 AM
To: michael.d.labri...@gmail.com; amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: fix dma mask check in gmc_v6_0.c

This got messed up by "drm: change func to better detect wether swiotlb
is needed".

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 9fc3296592fe..98fd9208877f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -886,7 +886,7 @@ static int gmc_v6_0_sw_init(void *handle)
 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
 }
-   adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
+   adev->need_swiotlb = drm_need_swiotlb(dma_bits);

 r = gmc_v6_0_init_microcode(adev);
 if (r) {
--
2.17.1

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Re: [PATCH] drm/amdgpu: Update sdma golden setting for vega20

[Deucher, Alexander]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Liu, Shaoyun 

Sent: Friday, February 15, 2019 11:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH] drm/amdgpu: Update sdma golden setting for vega20

According to hardware engineer, WTITE_BUST_LENGTH [9:8] in register
SDMA0_CHICKEN_BITS need to change to 3 for better performance

Change-Id: I32121ac19a62c0794b43755078e89d447724bf07
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 127b859..c816e55 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -128,7 +128,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma0_4_2_init[] = {

 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 {
-   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 
0x02831d07),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0x, 
0x3f000100),
 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x773f, 
0x4002),
 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
@@ -158,7 +158,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma0_4_2[] =
 };

 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
-   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831d07),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0x, 
0x3f000100),
 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x773f, 
0x4002),
 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
--
2.7.4

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RE: [PATCH] drm/amd/display: Attach VRR properties for eDP connectors

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Nicholas Kazlauskas
> Sent: Thursday, January 31, 2019 1:58 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Li, Sun peng (Leo) ; Wentland, Harry
> ; Kazlauskas, Nicholas
> 
> Subject: [PATCH] drm/amd/display: Attach VRR properties for eDP
> connectors
> 
> [Why]
> eDP was missing in the checks for supported VRR connectors.
> 
> [How]
> Attach the properties for eDP connectors too.
> 
> Cc: Leo Li 
> Cc: Harry Wentland 
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=202449
> Signed-off-by: Nicholas Kazlauskas 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index cdda68aba70e..4c7c34cae882 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4249,7 +4249,8 @@ void amdgpu_dm_connector_init_helper(struct
> amdgpu_display_manager *dm,
>   }
> 
>   if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> - connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
> + connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> + connector_type == DRM_MODE_CONNECTOR_eDP) {
>   drm_connector_attach_vrr_capable_property(
>   &aconnector->base);
>   drm_object_attach_property(&aconnector->base.base,
> --
> 2.17.1
> 
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RE: Bug#921004: downgrade to firmware-amd-graphics_20180825-1_all.deb

[Deucher, Alexander]

Is there a big report?  I haven't heard of any other issues and these updates 
have been upstream in linux-firmware for over a month now.

Alex

> -Original Message-
> From: amd-gfx  On Behalf Of
> Michel Dänzer
> Sent: Thursday, January 31, 2019 11:03 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: Fwd: Bug#921004: downgrade to firmware-amd-graphics_20180825-
> 1_all.deb
> 
> 
> Bad news I'm afraid, looks like the latest firmware (based on linux-firmware
> commit bc656509a3cfb60fcdfc905d7e23c18873e4e7b9 from
> 2019-01-14) broke some RX 580 cards.
> 
> 
> --
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer
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Re: [PATCH] drm/amd/powerplay: Remove duplicate header

[Deucher, Alexander]

It was already fixed a while ago:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7e07834c12b96214e95a473f7b14fc03b20e2e7a


Alex


From: Brajeswar Ghosh 
Sent: Wednesday, January 30, 2019 8:58:52 AM
To: Souptick Joarder
Cc: Zhu, Rex; Quan, Evan; Deucher, Alexander; Koenig, Christian; Zhou, 
David(ChunMing); airl...@linux.ie; Zhang, Hawking; Huang, Ray; 
amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; 
linux-ker...@vger.kernel.org; Sabyasachi Gupta
Subject: Re: [PATCH] drm/amd/powerplay: Remove duplicate header

On Fri, Dec 21, 2018 at 6:06 PM Souptick Joarder  wrote:
>
> On Fri, Dec 21, 2018 at 2:49 PM Brajeswar Ghosh
>  wrote:
> >
> > Remove hwmgr_ppt.h which is included more than once
> >
> > Signed-off-by: Brajeswar Ghosh 
> > ---
> Acked-by: Souptick Joarder 

If no further comment, can we get this patch in queue for 5.1 ?

>
> >  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
> >  1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
> > b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > index e5a60aa44b5d..07d180ce4d18 100644
> > --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > @@ -28,7 +28,6 @@
> >  #include "hardwaremanager.h"
> >  #include "hwmgr_ppt.h"
> >  #include "ppatomctrl.h"
> > -#include "hwmgr_ppt.h"
> >  #include "power_state.h"
> >  #include "smu_helper.h"
> >
> > --
> > 2.17.1
> >
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Re: [PATCH] drm/amd/display: Fix fclk idle state

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of 
roman...@amd.com 
Sent: Tuesday, January 29, 2019 3:16:53 PM
To: amd-gfx@lists.freedesktop.org; Xu, Feifei; Quan, Evan
Cc: Chan, Carl; Wentland, Harry; Li, Roman
Subject: [PATCH] drm/amd/display: Fix fclk idle state

From: Roman Li 

[Why]
The earlier change 'Fix 6x4K displays' led to fclk value
idling at higher DPM level.

[How]
Apply the fix only to respective multi-display configuration.

Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
index 3c52a4fc921d..bbe051736a18 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
@@ -627,7 +627,15 @@ static void dce11_pplib_apply_display_requirements(
 dc,
 context->bw.dce.sclk_khz);

-   pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz;
+   /*
+* As workaround for >4x4K lightup set dcfclock to min_engine_clock 
value.
+* This is not required for less than 5 displays,
+* thus don't request decfclk in dc to avoid impact
+* on power saving.
+*
+*/
+   pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4)?
+   pp_display_cfg->min_engine_clock_khz : 0;

 pp_display_cfg->min_engine_clock_deep_sleep_khz
 = context->bw.dce.sclk_deep_sleep_khz;
--
2.17.1

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Re: regression in dcn linked to -msse2

[Deucher, Alexander]

See:

https://bugs.freedesktop.org/show_bug.cgi?id=109487



From: amd-gfx  on behalf of StDenis, Tom 

Sent: Tuesday, January 29, 2019 8:44:03 AM
To: Wentland, Harry; amd-gfx mailing list
Cc: Deucher, Alexander
Subject: regression in dcn linked to -msse2

Testing with the new 5.0.0-rc1 amd-staging-drm-next branch results in
this commit causing the attached lockup on init with my Raven + Polaris
system:

10117450735c7a7c0858095fb46a860e7037cb9a is the first bad commit
commit 10117450735c7a7c0858095fb46a860e7037cb9a
Author: ndesaulni...@google.com 
Date:   Thu Jan 24 16:52:59 2019 -0800

 drm/amd/display: add -msse2 to prevent Clang from emitting libcalls
to undefined SW FP routines

 arch/x86/Makefile disables SSE and SSE2 for the whole kernel.  The
 AMDGPU drivers modified in this patch re-enable SSE but not SSE2.  Turn
 on SSE2 to support emitting double precision floating point
instructions
 rather than calls to non-existent (usually available from gcc_s or
 compiler_rt) floating point helper routines.

 Link:
https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html
 Link: https://github.com/ClangBuiltLinux/linux/issues/327
 Cc: sta...@vger.kernel.org # 4.19
 Reported-by: S, Shirish 
 Reported-by: Matthias Kaehlcke 
 Suggested-by: James Y Knight 
 Suggested-by: Nathan Chancellor 
 Signed-off-by: Nick Desaulniers 
 Tested-by: Guenter Roeck 
 Tested-by:  Matthias Kaehlcke 
 Tested-by: Nathan Chancellor 
 Reviewed-by: Harry Wentland 
 Signed-off-by: Harry Wentland 
 Signed-off-by: Alex Deucher 

:04 04 39f89ea177b8a69a3a2aa098aef8b1a7e58056b9
71edb262be0608ffae0996253f47492b2e714b5c M  drivers


Cheers,
Tom
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Re: [PATCH] drm/amd/powerplay: add override pcie parameters for Vega20

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Huang, 
JinHuiEric 
Sent: Friday, January 25, 2019 5:24:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, JinHuiEric
Subject: [PATCH] drm/amd/powerplay: add override pcie parameters for Vega20

It is to solve RDMA performance issue.

Change-Id: I441d2943e504e2ef7d33de0e8773a0f9b8fdb2ca
Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 46 ++
 1 file changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 5085b36..7e59bc8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -771,6 +771,47 @@ static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
 return 0;
 }

+static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   uint32_t pcie_speed = 0, pcie_width = 0, pcie_arg;
+   int ret;
+
+   if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
+   pcie_speed = 16;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+   pcie_speed = 8;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
+   pcie_speed = 5;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
+   pcie_speed = 2;
+
+   if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32)
+   pcie_width = 32;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+   pcie_width = 16;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
+   pcie_width = 12;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
+   pcie_width = 8;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
+   pcie_width = 4;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
+   pcie_width = 2;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
+   pcie_width = 1;
+
+   pcie_arg = pcie_width | (pcie_speed << 8);
+
+   ret = smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_OverridePcieParameters, pcie_arg);
+   PP_ASSERT_WITH_CODE(!ret,
+   "[OverridePcieParameters] Attempt to override pcie params 
failed!",
+   return ret);
+
+   return 0;
+}
+
 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 {
 struct vega20_hwmgr *data =
@@ -1570,6 +1611,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr 
*hwmgr)
 "[EnableDPMTasks] Failed to initialize SMC table!",
 return result);

+   result = vega20_override_pcie_parameters(hwmgr);
+   PP_ASSERT_WITH_CODE(!result,
+   "[EnableDPMTasks] Failed to override pcie parameters!",
+   return result);
+
 result = vega20_run_btc(hwmgr);
 PP_ASSERT_WITH_CODE(!result,
 "[EnableDPMTasks] Failed to run btc!",
--
2.7.4

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Re: [PATCH 4/4] drm/amd/powerplay: support Vega12 retrieving and setting ppfeatures

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 



From: amd-gfx  on behalf of Evan Quan 

Sent: Thursday, January 24, 2019 2:48:05 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH 4/4] drm/amd/powerplay: support Vega12 retrieving and setting 
ppfeatures

Enable retrieving and setting ppfeatures on Vega12.

Change-Id: Idad5eaadbb9e7ea73edd9e9d4fe4e1a5b17fb7a6
Signed-off-by: Evan Quan 
---
 .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 100 ++
 1 file changed, 100 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 45a45669d2ec..342f8b81ca82 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1933,6 +1933,104 @@ static int vega12_force_clock_level(struct pp_hwmgr 
*hwmgr,
 return 0;
 }

+static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
+{
+   static const char *ppfeature_name[] = {
+   "DPM_PREFETCHER",
+   "GFXCLK_DPM",
+   "UCLK_DPM",
+   "SOCCLK_DPM",
+   "UVD_DPM",
+   "VCE_DPM",
+   "ULV",
+   "MP0CLK_DPM",
+   "LINK_DPM",
+   "DCEFCLK_DPM",
+   "GFXCLK_DS",
+   "SOCCLK_DS",
+   "LCLK_DS",
+   "PPT",
+   "TDC",
+   "THERMAL",
+   "GFX_PER_CU_CG",
+   "RM",
+   "DCEFCLK_DS",
+   "ACDC",
+   "VR0HOT",
+   "VR1HOT",
+   "FW_CTF",
+   "LED_DISPLAY",
+   "FAN_CONTROL",
+   "DIDT",
+   "GFXOFF",
+   "CG",
+   "ACG"};
+   static const char *output_title[] = {
+   "FEATURES",
+   "BITMASK",
+   "ENABLEMENT"};
+   uint64_t features_enabled;
+   int i;
+   int ret = 0;
+   int size = 0;
+
+   ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
+   PP_ASSERT_WITH_CODE(!ret,
+   "[EnableAllSmuFeatures] Failed to get enabled smc 
features!",
+   return ret);
+
+   size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", 
features_enabled);
+   size += sprintf(buf + size, "%-19s %-22s %s\n",
+   output_title[0],
+   output_title[1],
+   output_title[2]);
+   for (i = 0; i < GNLD_FEATURES_MAX; i++) {
+   size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
+   ppfeature_name[i],
+   1ULL << i,
+   (features_enabled & (1ULL << i)) ? "Y" 
: "N");
+   }
+
+   return size;
+}
+
+static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t 
new_ppfeature_masks)
+{
+   uint64_t features_enabled;
+   uint64_t features_to_enable;
+   uint64_t features_to_disable;
+   int ret = 0;
+
+   if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
+   return -EINVAL;
+
+   ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
+   if (ret)
+   return ret;
+
+   features_to_disable =
+   (features_enabled ^ new_ppfeature_masks) & features_enabled;
+   features_to_enable =
+   (features_enabled ^ new_ppfeature_masks) ^ features_to_disable;
+
+   pr_debug("features_to_disable 0x%llx\n", features_to_disable);
+   pr_debug("features_to_enable 0x%llx\n", features_to_enable);
+
+   if (features_to_disable) {
+   ret = vega12_enable_smc_features(hwmgr, false, 
features_to_disable);
+   if (ret)
+   return ret;
+   }
+
+   if (features_to_enable) {
+   ret = vega12_enable_smc_features(hwmgr, true, 
features_to_enable);
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+}
+
 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
 enum pp_clock_type type, char *buf)
 {
@@ -2528,6 +2626,8 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
 .start_thermal_controller = vega12_start_thermal_controller,
 .powergate_gfx = vega12_gfx_off_control,

Re: [PATCH 2/2] drm/amd/powerplay: avoid frequent metrics table export

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Evan Quan 

Sent: Thursday, January 24, 2019 5:59:18 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH 2/2] drm/amd/powerplay: avoid frequent metrics table export

That's unnecessary. Also it makes more sense to show all the clocks
on one metrics table export.

Change-Id: I6350911934dbd85dc701de17ccc0e9cbddda4648
Signed-off-by: Evan Quan 
---
 .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 43 +--
 .../drm/amd/powerplay/hwmgr/vega20_hwmgr.h|  3 ++
 2 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 13f124125f5a..7b49a9a13a4a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -1958,16 +1958,36 @@ static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr 
*hwmgr, bool low)
 return (mem_clk * 100);
 }

+static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t 
*metrics_table)
+{
+   struct vega20_hwmgr *data =
+   (struct vega20_hwmgr *)(hwmgr->backend);
+   int ret = 0;
+
+   if (!data->metrics_time || time_after(jiffies, data->metrics_time + HZ 
/ 2)) {
+   ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
+   TABLE_SMU_METRICS, true);
+   if (ret) {
+   pr_info("Failed to export SMU metrics table!\n");
+   return ret;
+   }
+   memcpy(&data->metrics_table, metrics_table, 
sizeof(SmuMetrics_t));
+   data->metrics_time = jiffies;
+   } else
+   memcpy(metrics_table, &data->metrics_table, 
sizeof(SmuMetrics_t));
+
+   return ret;
+}
+
 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
 uint32_t *query)
 {
 int ret = 0;
 SmuMetrics_t metrics_table;

-   ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, 
TABLE_SMU_METRICS, true);
-   PP_ASSERT_WITH_CODE(!ret,
-   "Failed to export SMU METRICS table!",
-   return ret);
+   ret = vega20_get_metrics_table(hwmgr, &metrics_table);
+   if (ret)
+   return ret;

 *query = metrics_table.CurrSocketPower << 8;

@@ -1998,10 +2018,9 @@ static int vega20_get_current_activity_percent(struct 
pp_hwmgr *hwmgr,
 int ret = 0;
 SmuMetrics_t metrics_table;

-   ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, 
TABLE_SMU_METRICS, true);
-   PP_ASSERT_WITH_CODE(!ret,
-   "Failed to export SMU METRICS table!",
-   return ret);
+   ret = vega20_get_metrics_table(hwmgr, &metrics_table);
+   if (ret)
+   return ret;

 *activity_percent = metrics_table.AverageGfxActivity;

@@ -2019,11 +2038,9 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, 
int idx,

 switch (idx) {
 case AMDGPU_PP_SENSOR_GFX_SCLK:
-   ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table,
-   TABLE_SMU_METRICS, true);
-   PP_ASSERT_WITH_CODE(!ret,
-   "Failed to export SMU METRICS table!",
-   return ret);
+   ret = vega20_get_metrics_table(hwmgr, &metrics_table);
+   if (ret)
+   return ret;

 *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 
100;
 *size = 4;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
index 25faaa5c5b10..37f5f5e657da 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
@@ -520,6 +520,9 @@ struct vega20_hwmgr {
 /*  Gfxoff  */
 bool   gfxoff_allowed;
 uint32_t   counter_gfxoff;
+
+   unsigned long  metrics_time;
+   SmuMetrics_t   metrics_table;
 };

 #define VEGA20_DPM2_NEAR_TDP_DEC  10
--
2.20.1

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Re: [PATCH 2/2] drm/amd/powerplay: run btc before enabling all SMU features

[Deucher, Alexander]

Series is:

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Evan Quan 

Sent: Monday, January 21, 2019 4:46:07 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH 2/2] drm/amd/powerplay: run btc before enabling all SMU features

BTC is needed before enabling all SMU features.

Change-Id: Ic717226528f4d09a58264524b2d8e67150a35da7
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 60a22d8da7f0..5085b3636f8e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -804,6 +804,11 @@ static int vega20_set_allowed_featuresmask(struct pp_hwmgr 
*hwmgr)
 return 0;
 }

+static int vega20_run_btc(struct pp_hwmgr *hwmgr)
+{
+   return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc);
+}
+
 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
 {
 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
@@ -1565,6 +1570,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr 
*hwmgr)
 "[EnableDPMTasks] Failed to initialize SMC table!",
 return result);

+   result = vega20_run_btc(hwmgr);
+   PP_ASSERT_WITH_CODE(!result,
+   "[EnableDPMTasks] Failed to run btc!",
+   return result);
+
 result = vega20_run_btc_afll(hwmgr);
 PP_ASSERT_WITH_CODE(!result,
 "[EnableDPMTasks] Failed to run btc afll!",
--
2.20.1

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Re: [PATCH 2/2] drm/amdgpu: fix wrong APU judgement

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Evan Quan 

Sent: Wednesday, January 16, 2019 1:16:15 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH 2/2] drm/amdgpu: fix wrong APU judgement

Fix the APU judgement to make it really work as expected.

Change-Id: Iedc7d280e2bb68dd1b3732adb3b36ff9b05d84af
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 42078607168f..931cfd947958 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2483,7 +2483,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 return ret;
 }
 /* PCIe Perf counters won't work on APU nodes */
-   if (adev->flags & !AMD_IS_APU) {
+   if (!(adev->flags & AMD_IS_APU)) {
 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
 if (ret) {
 DRM_ERROR("failed to create device file pcie_bw\n");
@@ -2546,7 +2546,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 device_remove_file(adev->dev,
 &dev_attr_pp_od_clk_voltage);
 device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
-   if (adev->flags & !AMD_IS_APU)
+   if (!(adev->flags & AMD_IS_APU))
 device_remove_file(adev->dev, &dev_attr_pcie_bw);
 if ((adev->asic_type >= CHIP_VEGA10) &&
 !(adev->flags & AMD_IS_APU))
--
2.20.1

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Re: [PATCH] drm/amd/display: eDP fast bootup does not work for pre-raven asic

[Deucher, Alexander]

So 95f05a3a2e6895ecfd8b4f64b5d6c6 is still valid even with your patch and we 
should keep it?  Thanks


Alex


From: Wu, Hersen
Sent: Tuesday, January 15, 2019 12:04:30 PM
To: Alex Deucher
Cc: Deucher, Alexander; Li, Sun peng (Leo); amd-gfx@lists.freedesktop.org; 
Wentland, Harry
Subject: RE: [PATCH] drm/amd/display: eDP fast bootup does not work for 
pre-raven asic

My change will NOT revert 95f05a3a2e6895ecfd8b4f64b5d6c6.

Thanks
Hersen



-Original Message-
From: Alex Deucher 
Sent: Tuesday, January 15, 2019 12:01 PM
To: Wu, Hersen 
Cc: Deucher, Alexander ; Li, Sun peng (Leo) 
; amd-gfx@lists.freedesktop.org; Wentland, Harry 

Subject: Re: [PATCH] drm/amd/display: eDP fast bootup does not work for 
pre-raven asic

I'm not sure I understand.  If we were to apply your proposed patch, could we 
revert 95f05a3a2e6895ecfd8b4f64b5d6c6 ?

Thanks,

Alex

On Tue, Jan 15, 2019 at 11:57 AM Wu, Hersen  wrote:
>
> Hi, Alex,
>
>
>
> Hersen’s change is for older version of eDP fast boot up ( 
> bios_get_vga_enabled_displays  is called).
>
> Chrome tree source still use bios_get_vga_enabled_displays for fast boot up.
>
>
>
>
>
> Harry’s change is new implementation of eDP fast boot up.
>
>
>
> Hersen’s change will not revert Harry’s change.
>
>
>
> Thanks,
>
> Hersen
>
>
>
>
>
> From: Deucher, Alexander 
> Sent: Tuesday, January 15, 2019 10:43 AM
> To: Li, Sun peng (Leo) ;
> amd-gfx@lists.freedesktop.org
> Cc: Wentland, Harry ; Wu, Hersen
> 
> Subject: Re: [PATCH] drm/amd/display: eDP fast bootup does not work
> for pre-raven asic
>
>
>
> Can this patch be reverted with this change?
>
>
>
> commit 95f05a3a2e6895ecfd8b4f64b5d6c6cf0b6a3f4a
> Author: Alex Deucher 
> Date:   Thu Aug 16 15:35:21 2018 -0500
>
> drm/amdgpu/display: disable eDP fast boot optimization on DCE8
>
> Seems to cause blank screens.
>
> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106940
> Reviewed-by: Harry Wentland 
> Signed-off-by: Alex Deucher 
>
> Other than that, it looks good to me.
>
> Reviewed-by: Alex Deucher 
>
> 
>
> From: amd-gfx  on behalf of
> sunpeng...@amd.com 
> Sent: Monday, January 14, 2019 5:36:15 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wentland, Harry; Wu, Hersen
> Subject: [PATCH] drm/amd/display: eDP fast bootup does not work for
> pre-raven asic
>
>
>
> From: hersen wu 
>
> [Why] bios will light up eDP before sw driver loaded. sw driver will
> check if eDP lighted up by bios by reading BIOS_SCRATCH_3. If yes, sw
> driver will not power down eDP power, phy to save time.
> definition of BIOS_SCRATCH_3 are missed for pre-raven asic. this cuase
> eDP fast boot up not work. for some eDP panel, even AMD dp tx send
> NoVideoStream_flag =1 and dpcd 0x600=2, eDP rx may not handle
> properly. this may cause short period flash on screen.
>
> [How] add definition of BIOS_SCRATCH_3 for all asic
>
> CC: Harry Wentland 
> Signed-off-by: hersen wu 
> Reviewed-by: Charlene Liu 
> Acked-by: Yongqiang Sun 
> Acked-by: Leo Li 
> ---
>  drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c | 3 +--
> drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c  | 2 ++
> drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c  | 2 ++
> drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c  | 2 ++
> drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c  | 1 +
>  drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c| 2 ++
>  6 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
> b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
> index fdda8aa..d8275ceb 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
> @@ -83,8 +83,7 @@ uint32_t bios_get_vga_enabled_displays(  {
>  uint32_t active_disp = 1;
>
> -   if (bios->regs->BIOS_SCRATCH_3) /*follow up with other asic, todo*/
> -   active_disp = REG_READ(BIOS_SCRATCH_3) & 0X;
> +   active_disp = REG_READ(BIOS_SCRATCH_3) & 0X;
>  return active_disp;
>  }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> index c3f616a..23044e6 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
> @@ -76,6 +76,7 @@
>
>  #ifndef mmBIOS_SCRATCH_2
>  #define mmBIOS_SCRATCH_2 0x05CB
> +   #define mmBIOS_SCRATCH_3 0x05CC
>  #define mmBIOS_SCRATCH_6 0x

Re: [PATCH] drm/amd/display: eDP fast bootup does not work for pre-raven asic

[Deucher, Alexander]

Can this patch be reverted with this change?


commit 95f05a3a2e6895ecfd8b4f64b5d6c6cf0b6a3f4a
Author: Alex Deucher 
Date:   Thu Aug 16 15:35:21 2018 -0500

drm/amdgpu/display: disable eDP fast boot optimization on DCE8

Seems to cause blank screens.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106940
Reviewed-by: Harry Wentland 
Signed-off-by: Alex Deucher 

Other than that, it looks good to me.

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of 
sunpeng...@amd.com 
Sent: Monday, January 14, 2019 5:36:15 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry; Wu, Hersen
Subject: [PATCH] drm/amd/display: eDP fast bootup does not work for pre-raven 
asic

From: hersen wu 

[Why] bios will light up eDP before sw driver loaded. sw driver will
check if eDP lighted up by bios by reading BIOS_SCRATCH_3. If yes,
sw driver will not power down eDP power, phy to save time.
definition of BIOS_SCRATCH_3 are missed for pre-raven asic. this
cuase eDP fast boot up not work. for some eDP panel, even AMD dp tx
send NoVideoStream_flag =1 and dpcd 0x600=2, eDP rx may not handle
properly. this may cause short period flash on screen.

[How] add definition of BIOS_SCRATCH_3 for all asic

CC: Harry Wentland 
Signed-off-by: hersen wu 
Reviewed-by: Charlene Liu 
Acked-by: Yongqiang Sun 
Acked-by: Leo Li 
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c | 3 +--
 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c  | 2 ++
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c  | 2 ++
 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c  | 2 ++
 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c  | 1 +
 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c| 2 ++
 6 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
index fdda8aa..d8275ceb 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
@@ -83,8 +83,7 @@ uint32_t bios_get_vga_enabled_displays(
 {
 uint32_t active_disp = 1;

-   if (bios->regs->BIOS_SCRATCH_3) /*follow up with other asic, todo*/
-   active_disp = REG_READ(BIOS_SCRATCH_3) & 0X;
+   active_disp = REG_READ(BIOS_SCRATCH_3) & 0X;
 return active_disp;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index c3f616a..23044e6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -76,6 +76,7 @@

 #ifndef mmBIOS_SCRATCH_2
 #define mmBIOS_SCRATCH_2 0x05CB
+   #define mmBIOS_SCRATCH_3 0x05CC
 #define mmBIOS_SCRATCH_6 0x05CF
 #endif

@@ -365,6 +366,7 @@ static const struct dce_abm_mask abm_mask = {
 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03

 static const struct bios_registers bios_regs = {
+   .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 };

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 7d46eb7..7549ada 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -84,6 +84,7 @@

 #ifndef mmBIOS_SCRATCH_2
 #define mmBIOS_SCRATCH_2 0x05CB
+   #define mmBIOS_SCRATCH_3 0x05CC
 #define mmBIOS_SCRATCH_6 0x05CF
 #endif

@@ -369,6 +370,7 @@ static const struct dce110_clk_src_mask cs_mask = {
 };

 static const struct bios_registers bios_regs = {
+   .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 };

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index d930e09..ea3065d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -76,6 +76,7 @@

 #ifndef mmBIOS_SCRATCH_2
 #define mmBIOS_SCRATCH_2 0x05CB
+   #define mmBIOS_SCRATCH_3 0x05CC
 #define mmBIOS_SCRATCH_6 0x05CF
 #endif

@@ -376,6 +377,7 @@ static const struct dce110_clk_src_mask cs_mask = {
 };

 static const struct bios_registers bios_regs = {
+   .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 };

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 23d7d4d..312a0ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -442,6 +442,7 @@ struct dce_i2c_hw *dce120_i2c_hw_create(
 return dce_i2c_hw;
 }
 static const struct bios_registers bios_regs = {
+   .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + 
NBIO_BASE(mmBIOS_SCRATCH_3_BASE_

Re: [PATCH 4/4] drm/amd/powerplay: support retrieving and adjusting dcefclock power levels

[Deucher, Alexander]

Seems reasonable to me.  With those changes,

Reviewed-by: Alex Deucher 


From: Quan, Evan
Sent: Tuesday, January 15, 2019 1:59:42 AM
To: Alex Deucher
Cc: amd-gfx list; Deucher, Alexander
Subject: RE: [PATCH 4/4] drm/amd/powerplay: support retrieving and adjusting 
dcefclock power levels

For ppfeatures, it will be seen only if (adev->asic_type >= CHIP_VEGA10 && 
!APU).

Regards,
Evan
> -Original Message-
> From: Quan, Evan
> Sent: Tuesday, January 15, 2019 2:44 PM
> To: Alex Deucher 
> Cc: amd-gfx list ; Deucher, Alexander
> 
> Subject: RE: [PATCH 4/4] drm/amd/powerplay: support retrieving and
> adjusting dcefclock power levels
>
> I think we can use asic_type to determine whether to expose these new
> interfaces.
> If (adev->asic_type >= CHIP_VEGA10), socclk and dcefclk are OK to expose If
> (adev->asic_type >= CHIP_VEGA20), fclk is OK to expose
>
> Regards,
> Evan
> > -Original Message-
> > From: Alex Deucher 
> > Sent: Tuesday, January 15, 2019 1:00 AM
> > To: Quan, Evan 
> > Cc: amd-gfx list ; Deucher, Alexander
> > 
> > Subject: Re: [PATCH 4/4] drm/amd/powerplay: support retrieving and
> > adjusting dcefclock power levels
> >
> > On Mon, Jan 14, 2019 at 5:02 AM Evan Quan  wrote:
> > >
> > > User can use "pp_dpm_dcefclk" to retrieve and adjust dcefclock power
> > > levels.
> > >
> > > Change-Id: Ia3f61558ca96104c88d129ba5194103b2fe702ec
> > > Signed-off-by: Evan Quan 
> >
> > We should probably find a way to hide these new files on asics which
> > don't support them.  Other than that, the series looks good to me.
> >
> > Alex
> >
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 53
> > ++-
> > >  .../gpu/drm/amd/include/kgd_pp_interface.h|  1 +
> > >  .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 52
> > +-
> > >  3 files changed, 103 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > index f6646a522c06..b7b70f590236 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > @@ -731,11 +731,13 @@ static ssize_t
> > > amdgpu_get_ppfeature_status(struct device *dev,  }
> > >
> > >  /**
> > > - * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk
> > pp_dpm_pcie
> > > + * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk
> > > + pp_dpm_dcefclk
> > > + * pp_dpm_pcie
> > >   *
> > >   * The amdgpu driver provides a sysfs API for adjusting what power
> levels
> > >   * are enabled for a given power state.  The files pp_dpm_sclk,
> > > pp_dpm_mclk,
> > > - * pp_dpm_socclk, pp_dpm_fclk and pp_dpm_pcie are used for this.
> > > + * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie
> are
> > > + used for
> > > + * this.
> > >   *
> > >   * Reading back the files will show you the available power levels within
> > >   * the power state and the clock information for those levels.
> > > @@ -745,6 +747,8 @@ static ssize_t
> > > amdgpu_get_ppfeature_status(struct
> > device *dev,
> > >   * Secondly,Enter a new value for each level by inputing a string that
> > >   * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
> > >   * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
> > > + *
> > > + * NOTE: change to the dcefclk max dpm level is not supported now
> > >   */
> > >
> > >  static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, @@ -927,6
> > > +931,42 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
> > > return count;
> > >  }
> > >
> > > +static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
> > > +   struct device_attribute *attr,
> > > +   char *buf)
> > > +{
> > > +   struct drm_device *ddev = dev_get_drvdata(dev);
> > > +   struct amdgpu_device *adev = ddev->dev_private;
> > > +
> > > +   if (adev->powerplay.pp_funcs->print_clock_levels)
> > > +   return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK,
> buf);
> > > +   else
> > > +   return snprintf(buf, PAGE_SIZE, "\n"); }
> > > +
> > > +static ssize_t amdgpu_set_

Re: [PATCH] drm/amdgpu: Setting doorbell range registers earlier

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Zeng, Oak 

Sent: Monday, January 14, 2019 5:39:41 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zeng, Oak
Subject: [PATCH] drm/amdgpu: Setting doorbell range registers earlier

HW doorbell writing routing policy: writing to doorbell
not in SDMA/IH/MM/ACV doorbell range will be routed to CP.
So CP doorbell routing depends on doorbell range setting
of above blocks. Setting doorbell range of above blocks
earlier (soc15_common_hw_init) to make sure CP doorbell
writing be routed to CP block.

Change-Id: I3f8edd582fb7cc20a83f48f7a1ff789036b3550e
Signed-off-by: Oak Zeng 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  2 --
 drivers/gpu/drm/amd/amdgpu/soc15.c | 21 +
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c |  2 --
 3 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 59638b8..48a166b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -834,8 +834,6 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device 
*adev, unsigned int i)
 OFFSET, ring->doorbell_index);
 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
-   adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
- ring->doorbell_index);

 sdma_v4_0_ring_set_wptr(ring);

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 5248b03..4cae547 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -966,6 +966,21 @@ static int soc15_common_sw_fini(void *handle)
 return 0;
 }

+static void soc15_doorbell_range_init(struct amdgpu_device *adev)
+{
+   int i;
+   struct amdgpu_ring *ring;
+
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   ring = &adev->sdma.instance[i].ring;
+   adev->nbio_funcs->sdma_doorbell_range(adev, i,
+   ring->use_doorbell, ring->doorbell_index);
+   }
+
+   adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
+   adev->irq.ih.doorbell_index);
+}
+
 static int soc15_common_hw_init(void *handle)
 {
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -978,6 +993,12 @@ static int soc15_common_hw_init(void *handle)
 adev->nbio_funcs->init_registers(adev);
 /* enable the doorbell aperture */
 soc15_enable_doorbell_aperture(adev, true);
+   /* HW doorbell routing policy: doorbell writing not
+* in SDMA/IH/MM/ACV range will be routed to CP. So
+* we need to init SDMA/IH/MM/ACV doorbell range prior
+* to CP ip block init and ring test.
+*/
+   soc15_doorbell_range_init(adev);

 return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 5627019..877b4a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -140,8 +140,6 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
  ENABLE, 0);
 }
 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
-   adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
-   adev->irq.ih.doorbell_index);

 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
--
2.7.4

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Re: [PATCH] Revert "drm/amdgpu: validate user pitch alignment"

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Friday, January 11, 2019 10:22:07 AM
To: amd-gfx@lists.freedesktop.org
Cc: Yu Zhao
Subject: [PATCH] Revert "drm/amdgpu: validate user pitch alignment"

From: Michel Dänzer 

The check turned out to be too strict in some cases.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 70a816dd8b4d..4e944737b708 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -531,16 +531,6 @@ amdgpu_display_user_framebuffer_create(struct drm_device 
*dev,
 struct drm_gem_object *obj;
 struct amdgpu_framebuffer *amdgpu_fb;
 int ret;
-   struct amdgpu_device *adev = dev->dev_private;
-   int cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
-   int pitch = mode_cmd->pitches[0] / cpp;
-
-   pitch = amdgpu_align_pitch(adev, pitch, cpp, false);
-   if (mode_cmd->pitches[0] != pitch) {
-   DRM_DEBUG_KMS("Invalid pitch: expecting %d but got %d\n",
- pitch, mode_cmd->pitches[0]);
-   return ERR_PTR(-EINVAL);
-   }

 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
 if (obj ==  NULL) {
--
2.20.1

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Re: [PATCH 1/2] drm/amdgpu: Add NBIO SMN headers v2

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Russell, 
Kent 
Sent: Wednesday, January 9, 2019 9:43:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent
Subject: [PATCH 1/2] drm/amdgpu: Add NBIO SMN headers v2

We need these offsets for PCIE perf counters, so include them as well as
the the previously-used defines from the nbio_*.c files

v2: Return NBIF definitions back to previous files

Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  6 +--
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  4 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  5 +-
 .../drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h   | 58 ++
 .../drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h   | 54 
 .../drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h | 53 
 6 files changed, 168 insertions(+), 12 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index accdedd..1965756 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -27,13 +27,9 @@
 #include "nbio/nbio_6_1_default.h"
 #include "nbio/nbio_6_1_offset.h"
 #include "nbio/nbio_6_1_sh_mask.h"
+#include "nbio/nbio_6_1_smn.h"
 #include "vega10_enum.h"

-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-#define smnPCIE_CONFIG_CNTL
 0x11180044
-#define smnPCIE_CI_CNTL
 0x11180080
-
 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index df34dc7..38291c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -27,13 +27,11 @@
 #include "nbio/nbio_7_0_default.h"
 #include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
+#include "nbio/nbio_7_0_smn.h"
 #include "vega10_enum.h"

 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a05c

-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-
 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 4cd31a2..0a61309 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -26,13 +26,10 @@

 #include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
+#include "nbio/nbio_7_4_0_smn.h"

 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a21c

-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-#define smnPCIE_CI_CNTL
 0x11180080
-
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h 
b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
new file mode 100644
index 000..8c75669
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRI

Re: [PATCH xf86-video-ati 1/2] Only call drmmode_uevent_init if RandR is enabled

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Wednesday, January 9, 2019 5:43:22 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH xf86-video-ati 1/2] Only call drmmode_uevent_init if RandR is 
enabled

From: Michel Dänzer 

There's no point in listening for hotplug events if RandR is disabled,
as there's no other mechanism for them to be propagated. We were already
mostly ignoring them in that case.

Inspired by
https://gitlab.freedesktop.org/xorg/driver/xf86-video-intel/commit/1a489142c8e6a4828348cc9afbd0f430d3b1e2d8
(via https://bugs.freedesktop.org/109230#c11).

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 2 +-
 src/radeon_kms.c  | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index d433e0611..e04a17d5e 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -3273,7 +3273,7 @@ restart_destroy:
 /* Check to see if a lessee has disappeared */
 drmmode_validate_leases(scrn);

-   if (changed && dixPrivateKeyRegistered(rrPrivKey)) {
+   if (changed) {
 #if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,14,99,2,0)
 RRSetChanged(xf86ScrnToScreen(scrn));
 #else
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index bb6885fb9..67f42e0fe 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -349,13 +349,13 @@ static Bool RADEONCreateScreenResources_KMS(ScreenPtr 
pScreen)
 RROutputChanged(rrScrPriv->primaryOutput, FALSE);
 rrScrPriv->layoutChanged = TRUE;
 }
+
+   drmmode_uevent_init(pScrn, &info->drmmode);
 }

 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, pScreen->isGPU))
 return FALSE;

-drmmode_uevent_init(pScrn, &info->drmmode);
-
 if (info->r600_shadow_fb) {
 pixmap = pScreen->GetScreenPixmap(pScreen);

--
2.20.1

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Re: [PATCH 0/6] kexec fixes

[Deucher, Alexander]

Yes, the checks are taken from the existing SMU and PSP code.


Alex


From: Kuehling, Felix
Sent: Tuesday, January 8, 2019 6:22:48 PM
To: Alex Deucher; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH 0/6] kexec fixes

Thanks for this. I trust that your method for detecting that SMU or PSP
are running is correct. With that caveat the series is Reviewed-by:
Felix Kuehling 

Regards,
  Felix

On 2019-01-08 5:11 p.m., Alex Deucher wrote:
> Fixes for kexec.  The GPU needs to be reset before the driver
> can be loaded again reliably.  Needed for kexec for booting some
> ppc platforms.  See:
> https://bugs.freedesktop.org/show_bug.cgi?id=108585
>
> Alex Deucher (6):
>   drm/amdgpu: add need_reset_on_init asic callback (v2)
>   drm/amdgpu/si: add need_reset_on_init asic callback for SI (v2)
>   drm/amdgpu/cik: add need_reset_on_init asic callback for CIK (v2)
>   drm/amdgpu/vi: add need_reset_on_init asic callback for VI (v2)
>   drm/amdgpu/soc15: add need_reset_on_init asic callback for SOC15 (v2)
>   drm/amdgpu: check if we need to reset at init time (v2)
>
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  3 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 +++
>  drivers/gpu/drm/amd/amdgpu/cik.c   | 18 ++
>  drivers/gpu/drm/amd/amdgpu/si.c|  6 ++
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 20 
>  drivers/gpu/drm/amd/amdgpu/vi.c| 18 ++
>  6 files changed, 76 insertions(+)
>
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Re: [PATCH] drm/amdgpu: expose sclk and mclk via hwmon

[Deucher, Alexander]

Ping?  Useful for rocm-smi?


From: Alex Deucher 
Sent: Monday, December 10, 2018 4:17:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: expose sclk and mclk via hwmon

Expose sclk (gfx clock) and mclk (memory clock) via
hwmon compatible interface.  hwmon does not actually
formally specify a frequency type attribute, but these
are compatible with the format of the other attributes
exposed via hwmon.  Units are hertz.

freq1_input - GPU gfx/compute clock in hertz
freq2_input - GPU memory clock in hertz (dGPU only)

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 93 ++
 1 file changed, 93 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 1f61ed95727c..6d52428fc45b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1516,6 +1516,75 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device 
*dev,
 return count;
 }

+static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+   struct amdgpu_device *adev = dev_get_drvdata(dev);
+   struct drm_device *ddev = adev->ddev;
+   uint32_t sclk;
+   int r, size = sizeof(sclk);
+
+   /* Can't get voltage when the card is off */
+   if  ((adev->flags & AMD_IS_PX) &&
+(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+   return -EINVAL;
+
+   /* sanity check PP is enabled */
+   if (!(adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->read_sensor))
+ return -EINVAL;
+
+   /* get the sclk */
+   r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
+  (void *)&sclk, &size);
+   if (r)
+   return r;
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
+}
+
+static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
+   struct device_attribute *attr,
+   char *buf)
+{
+   return snprintf(buf, PAGE_SIZE, "sclk\n");
+}
+
+static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+   struct amdgpu_device *adev = dev_get_drvdata(dev);
+   struct drm_device *ddev = adev->ddev;
+   uint32_t mclk;
+   int r, size = sizeof(mclk);
+
+   /* Can't get voltage when the card is off */
+   if  ((adev->flags & AMD_IS_PX) &&
+(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+   return -EINVAL;
+
+   /* sanity check PP is enabled */
+   if (!(adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->read_sensor))
+ return -EINVAL;
+
+   /* get the sclk */
+   r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
+  (void *)&mclk, &size);
+   if (r)
+   return r;
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
+}
+
+static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
+   struct device_attribute *attr,
+   char *buf)
+{
+   return snprintf(buf, PAGE_SIZE, "mclk\n");
+}

 /**
  * DOC: hwmon
@@ -1532,6 +1601,10 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device 
*dev,
  *
  * - GPU fan
  *
+ * - GPU gfx/compute engine clock
+ *
+ * - GPU memory clock (dGPU only)
+ *
  * hwmon interfaces for GPU temperature:
  *
  * - temp1_input: the on die GPU temperature in millidegrees Celsius
@@ -1576,6 +1649,12 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device 
*dev,
  *
  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
  *
+ * hwmon interfaces for GPU clocks:
+ *
+ * - freq1_input: the gfx/compute clock in hertz
+ *
+ * - freq2_input: the memory clock in hertz
+ *
  * You can use hwmon tools like sensors to view this information on your 
system.
  *
  */
@@ -1600,6 +1679,10 @@ static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, 
amdgpu_hwmon_show_power_avg,
 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, 
amdgpu_hwmon_show_power_cap_max, NULL, 0);
 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, 
amdgpu_hwmon_show_power_cap_min, NULL, 0);
 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, 
amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
+static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 
0);
+static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, 

Re: [PATCH] drm/amdgpu: Add message print when unable to get valid hive

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Liu, Shaoyun 

Sent: Monday, January 7, 2019 11:01:51 AM
To: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: Add message print when unable to get valid hive

Ping ...

-Original Message-
From: Liu, Shaoyun 
Sent: Friday, January 4, 2019 1:29 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun 
Subject: [PATCH] drm/amdgpu: Add message print when unable to get valid hive

Add message print out and return -EINVAL when driver can not get valid hive 
from hive  arrary on xgmi configuration

Change-Id: Ic03927904edf0e384b8c4651e19274bb3f2a7d9a
Signed-off-by: shaoyunl 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 8a8bc60..b226631 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -113,8 +113,13 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)

 mutex_lock(&xgmi_mutex);
 hive = amdgpu_get_xgmi_hive(adev);
-   if (!hive)
+   if (!hive) {
+   ret = -EINVAL;
+   dev_err(adev->dev,
+   "XGMI: Can not matech hive 0xllx in the hive list.\n",
+   adev->gmc.xgmi.hive_id);
 goto exit;
+   }

 hive_topology = &hive->topology_info;

--
2.7.4

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Re: [PATCH 2/2] drm/amd/powerplay: create pp_od_clk_voltage device file under OD support

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Evan Quan 

Sent: Monday, January 7, 2019 7:05:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Quan, Evan; Freehill, Chris
Subject: [PATCH 2/2] drm/amd/powerplay: create pp_od_clk_voltage device file 
under OD support

Since pp_od_clk_voltage device file is for OD related sysfs operations.

Change-Id: I13e95b4bd2ffb93b1cd5d272dd27171ab38dbe57
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 22 ++
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 32aa4d09e12d..d8f3f006f5c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2061,6 +2061,7 @@ void amdgpu_pm_print_power_states(struct amdgpu_device 
*adev)

 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 {
+   struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
 int ret;

 if (adev->pm.sysfs_initialized)
@@ -2144,12 +2145,14 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 "pp_power_profile_mode\n");
 return ret;
 }
-   ret = device_create_file(adev->dev,
-   &dev_attr_pp_od_clk_voltage);
-   if (ret) {
-   DRM_ERROR("failed to create device file "
-   "pp_od_clk_voltage\n");
-   return ret;
+   if (hwmgr->od_enabled) {
+   ret = device_create_file(adev->dev,
+   &dev_attr_pp_od_clk_voltage);
+   if (ret) {
+   DRM_ERROR("failed to create device file "
+   "pp_od_clk_voltage\n");
+   return ret;
+   }
 }
 ret = device_create_file(adev->dev,
 &dev_attr_gpu_busy_percent);
@@ -2171,6 +2174,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)

 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 {
+   struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
+
 if (adev->pm.dpm_enabled == 0)
 return;

@@ -2191,8 +2196,9 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
 device_remove_file(adev->dev,
 &dev_attr_pp_power_profile_mode);
-   device_remove_file(adev->dev,
-   &dev_attr_pp_od_clk_voltage);
+   if (hwmgr->od_enabled)
+   device_remove_file(adev->dev,
+   &dev_attr_pp_od_clk_voltage);
 device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
 }

--
2.20.1

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Re: [PATCH 2/2] drm/amdgpu/psp: Fix can't detect psp INVOKE command failed

[Deucher, Alexander]

This bug may also be related:

https://bugs.freedesktop.org/show_bug.cgi?id=109206


Alex


From: Koenig, Christian
Sent: Thursday, January 3, 2019 10:57:50 AM
To: Yu, Xiangliang; Xu, Feifei; amd-gfx@lists.freedesktop.org; Deucher, 
Alexander
Subject: Re: [PATCH 2/2] drm/amdgpu/psp: Fix can't detect psp INVOKE command 
failed

> For Vega10, could you explain why it block older version fw?
I'm not very familiar with the PSP, so I don't know what exactly is
going wrong here.

Symptoms are that we get the following in dmesg:
> Jan 03 15:55:17 abel kernel: [drm] PSP loading VCE firmware
> Jan 03 15:55:17 abel kernel: [drm] reserve 0x40 from 0xf400c0
> for PSP TMR SIZE
> Jan 03 15:55:17 abel kernel: [drm:psp_cmd_submit_buf [amdgpu]] *ERROR*
> psp command failed and response status is (1)
> Jan 03 15:55:17 abel kernel: [drm:psp_hw_init [amdgpu]] *ERROR* PSP
> firmware loading failed
> Jan 03 15:55:17 abel kernel: [drm:amdgpu_device_fw_loading [amdgpu]]
> *ERROR* hw_init of IP block  failed -22
> Jan 03 15:55:17 abel kernel: amdgpu :43:00.0:
> amdgpu_device_ip_init failed
> Jan 03 15:55:17 abel kernel: amdgpu :43:00.0: Fatal error during
> GPU init

I think the code was purposely ignoring some return status because the
command wasn't available on older fw generations.

Now that we bail out on every non zero return code that fails when you
try to use the older PSP firmware on Vega10.

Anyway breaking older fw versions is not something we can do, so we need
to either fix or revert that ASAP or end users will start to complain.

Any idea how to investigate further?

Christian.

Am 03.01.19 um 16:21 schrieb Yu, Xiangliang:
> XGMI command will not load ucode, so it can't find the command failed if 
> check ucode at first.
> For code logic, should check response status to see if command complete 
> successfully at first.
> For Vega10, could you explain why it block older version fw?
>
>
> -Original Message-
> From: Christian König 
> Sent: Thursday, January 03, 2019 11:00 PM
> To: Xu, Feifei ; Yu, Xiangliang ; 
> amd-gfx@lists.freedesktop.org; Deucher, Alexander 
> Subject: Re: [PATCH 2/2] drm/amdgpu/psp: Fix can't detect psp INVOKE command 
> failed
>
> Hi guys,
>
> this patch broke loading older versions of PSP firmware on Vega10.
>
> What exactly is the background here? E.g. why do we need it? And can we 
> revert it ASAP?
>
> Thanks,
> Christian.
>
> Am 18.12.18 um 03:45 schrieb Xu, Feifei:
>> Reviewed-by: Feifei Xu 
>>
>> -Original Message-
>> From: amd-gfx  On Behalf Of
>> Xiangliang Yu
>> Sent: Thursday, December 13, 2018 3:42 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Yu, Xiangliang 
>> Subject: [PATCH 2/2] drm/amdgpu/psp: Fix can't detect psp INVOKE
>> command failed
>>
>> There isn't ucode when executing INVOKE command, so current code can't check 
>> the failure of INVOKE command.
>>
>> Remove the ucode check.
>>
>> Signed-off-by: Xiangliang Yu 
>> ---
>>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 11 +++
>>1 file changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> index 2f126ea7..7f5ce37 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> @@ -140,10 +140,13 @@ psp_cmd_submit_buf(struct psp_context *psp,
>>   while (*((unsigned int *)psp->fence_buf) != index)
>>   msleep(1);
>>
>> -/* the status field must be 0 after FW is loaded */
>> -if (ucode && psp->cmd_buf_mem->resp.status) {
>> -DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n",
>> -  psp->cmd_buf_mem->resp.status, ucode->ucode_id);
>> +/* the status field must be 0 after psp command completion */
>> +if (psp->cmd_buf_mem->resp.status) {
>> +if (ucode)
>> +DRM_ERROR("failed to load ucode id (%d) ",
>> +  ucode->ucode_id);
>> +DRM_ERROR("psp command failed and response status is (%d)\n",
>> +  psp->cmd_buf_mem->resp.status);
>>   return -EINVAL;
>>   }
>>
>> --
>> 2.7.4
>>
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Re: [PATCH 2/2] drm/amdgpu/psp: make get_fw_type and prep_cmd_buf to be common interfaces

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Hawking 
Zhang 
Sent: Thursday, January 3, 2019 9:00:44 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking
Subject: [PATCH 2/2] drm/amdgpu/psp: make get_fw_type and prep_cmd_buf to be 
common interfaces

get_fw_type and prep_cmd_buf should be common interface
instead of IP specific ones

Change-Id: I115a8d3fafdbe143008b3698ad3a5f3bd4b87481
Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 94 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h |  3 --
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 90 ---
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 75 --
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 72 -
 5 files changed, 93 insertions(+), 241 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8189a90..53c2d60 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -501,6 +501,98 @@ static int psp_hw_start(struct psp_context *psp)
 return 0;
 }

+static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
+  enum psp_gfx_fw_type *type)
+{
+   switch (ucode->ucode_id) {
+   case AMDGPU_UCODE_ID_SDMA0:
+   *type = GFX_FW_TYPE_SDMA0;
+   break;
+   case AMDGPU_UCODE_ID_SDMA1:
+   *type = GFX_FW_TYPE_SDMA1;
+   break;
+   case AMDGPU_UCODE_ID_CP_CE:
+   *type = GFX_FW_TYPE_CP_CE;
+   break;
+   case AMDGPU_UCODE_ID_CP_PFP:
+   *type = GFX_FW_TYPE_CP_PFP;
+   break;
+   case AMDGPU_UCODE_ID_CP_ME:
+   *type = GFX_FW_TYPE_CP_ME;
+   break;
+   case AMDGPU_UCODE_ID_CP_MEC1:
+   *type = GFX_FW_TYPE_CP_MEC;
+   break;
+   case AMDGPU_UCODE_ID_CP_MEC1_JT:
+   *type = GFX_FW_TYPE_CP_MEC_ME1;
+   break;
+   case AMDGPU_UCODE_ID_CP_MEC2:
+   *type = GFX_FW_TYPE_CP_MEC;
+   break;
+   case AMDGPU_UCODE_ID_CP_MEC2_JT:
+   *type = GFX_FW_TYPE_CP_MEC_ME2;
+   break;
+   case AMDGPU_UCODE_ID_RLC_G:
+   *type = GFX_FW_TYPE_RLC_G;
+   break;
+   case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
+   *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
+   break;
+   case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
+   *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
+   break;
+   case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
+   *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
+   break;
+   case AMDGPU_UCODE_ID_SMC:
+   *type = GFX_FW_TYPE_SMU;
+   break;
+   case AMDGPU_UCODE_ID_UVD:
+   *type = GFX_FW_TYPE_UVD;
+   break;
+   case AMDGPU_UCODE_ID_UVD1:
+   *type = GFX_FW_TYPE_UVD1;
+   break;
+   case AMDGPU_UCODE_ID_VCE:
+   *type = GFX_FW_TYPE_VCE;
+   break;
+   case AMDGPU_UCODE_ID_VCN:
+   *type = GFX_FW_TYPE_VCN;
+   break;
+   case AMDGPU_UCODE_ID_DMCU_ERAM:
+   *type = GFX_FW_TYPE_DMCU_ERAM;
+   break;
+   case AMDGPU_UCODE_ID_DMCU_INTV:
+   *type = GFX_FW_TYPE_DMCU_ISR;
+   break;
+   case AMDGPU_UCODE_ID_MAXIMUM:
+   default:
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
+  struct psp_gfx_cmd_resp *cmd)
+{
+   int ret;
+   uint64_t fw_mem_mc_addr = ucode->mc_addr;
+
+   memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
+
+   cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
+   cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
+   cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
+   cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
+
+   ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
+   if (ret)
+   DRM_ERROR("Unknown firmware type\n");
+
+   return ret;
+}
+
 static int psp_np_fw_load(struct psp_context *psp)
 {
 int i, ret;
@@ -522,7 +614,7 @@ static int psp_np_fw_load(struct psp_context *psp)
 /*skip ucode loading in SRIOV VF */
 continue;

-   ret = psp_prep_cmd_buf(ucode, psp->cmd);
+   ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
 if (ret)
 return ret;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 3ee573b..2ef98cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd

Re: [PATCH] drm/amd/powerplay: hint and error out when prerequisite not meet

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Evan Quan 

Sent: Thursday, January 3, 2019 1:06:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: hint and error out when prerequisite not 
meet

Do not ignore the error silently. Otherwise user may thought it
was executed successfully.

Change-Id: I4ac0cff5918d53d1d737f1c2fb1a4f81917dbf56
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 14 ++
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |  4 +++-
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 5e071917594f..e0a9f02d68d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -756,8 +756,11 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 if (ret)
 return ret;

-   if (adev->powerplay.pp_funcs->force_clock_level)
-   amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+   if (adev->powerplay.pp_funcs->force_clock_level) {
+   ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+   if (ret)
+   return ret;
+   }

 return count;
 }
@@ -789,8 +792,11 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 if (ret)
 return ret;

-   if (adev->powerplay.pp_funcs->force_clock_level)
-   amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+   if (adev->powerplay.pp_funcs->force_clock_level) {
+   ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+   if (ret)
+   return ret;
+   }

 return count;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 27215e4b488b..285375b96ea4 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -727,8 +727,10 @@ static int pp_dpm_force_clock_level(void *handle,
 mutex_lock(&hwmgr->smu_lock);
 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
 ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
-   else
+   else {
+   pr_info_ratelimited("Force clock level setting is for manual 
dpm mode only.\n");
 ret = -EINVAL;
+   }
 mutex_unlock(&hwmgr->smu_lock);
 return ret;
 }
--
2.20.1

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Re: [PATCH] drm/amdgpu/sriov: For finishing routine send rel event after init failed

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Emily Deng 

Sent: Wednesday, January 2, 2019 10:58:37 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu/sriov: For finishing routine send rel event after 
init failed

When init fail, sendsend rel init, req_fini and rel_fini to host for the
finishing routine.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 +++---
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3c57ffc..ccd2e83 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1652,7 +1652,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
 if (r) {
 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
   adev->ip_blocks[i].version->funcs->name, r);
-   return r;
+   goto init_failed;
 }
 adev->ip_blocks[i].status.sw = true;

@@ -1661,17 +1661,17 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
 r = amdgpu_device_vram_scratch_init(adev);
 if (r) {
 DRM_ERROR("amdgpu_vram_scratch_init failed 
%d\n", r);
-   return r;
+   goto init_failed;
 }
 r = adev->ip_blocks[i].version->funcs->hw_init((void 
*)adev);
 if (r) {
 DRM_ERROR("hw_init %d failed %d\n", i, r);
-   return r;
+   goto init_failed;
 }
 r = amdgpu_device_wb_init(adev);
 if (r) {
 DRM_ERROR("amdgpu_device_wb_init failed %d\n", 
r);
-   return r;
+   goto init_failed;
 }
 adev->ip_blocks[i].status.hw = true;

@@ -1682,7 +1682,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
 
AMDGPU_CSA_SIZE);
 if (r) {
 DRM_ERROR("allocate CSA failed %d\n", 
r);
-   return r;
+   goto init_failed;
 }
 }
 }
@@ -1690,30 +1690,32 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)

 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init 
complete*/
 if (r)
-   return r;
+   goto init_failed;

 r = amdgpu_device_ip_hw_init_phase1(adev);
 if (r)
-   return r;
+   goto init_failed;

 r = amdgpu_device_fw_loading(adev);
 if (r)
-   return r;
+   goto init_failed;

 r = amdgpu_device_ip_hw_init_phase2(adev);
 if (r)
-   return r;
+   goto init_failed;

 if (adev->gmc.xgmi.num_physical_nodes > 1)
 amdgpu_xgmi_add_device(adev);
 amdgpu_amdkfd_device_init(adev);

+init_failed:
 if (amdgpu_sriov_vf(adev)) {
-   amdgpu_virt_init_data_exchange(adev);
+   if (!r)
+   amdgpu_virt_init_data_exchange(adev);
 amdgpu_virt_release_full_gpu(adev, true);
 }

-   return 0;
+   return r;
 }

 /**
@@ -2621,6 +2623,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 }
 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 
0);
+   if (amdgpu_virt_request_full_gpu(adev, false))
+   amdgpu_virt_release_full_gpu(adev, false);
 goto failed;
 }

--
2.7.4

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Re: [PATCH 2/2] drm/amdgpu: set the executable flag on unused Vega10 PTEs

[Deucher, Alexander]

Series is:

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Christian 
König 
Sent: Wednesday, January 2, 2019 8:35:06 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 2/2] drm/amdgpu: set the executable flag on unused Vega10 PTEs

Otherwise we run into a non-retry fault on access.

It seems to be a hardware bug that the executable bit has
higher priority than the valid bit.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index e73d152659a2..01a68f4e17d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -799,9 +799,15 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 addr += ats_entries * 8;
 }

-   if (entries)
+   if (entries) {
+   uint64_t value = 0;
+
+   if (level == AMDGPU_VM_PTB && adev->asic_type >= CHIP_VEGA10)
+   value = AMDGPU_PTE_EXECUTABLE;
+
 amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
- entries, 0, 0);
+ entries, 0, value);
+   }

 amdgpu_ring_pad_ib(ring, &job->ibs[0]);

--
2.17.1

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Re: [PATCH] drm/amdgpu: distinguish early and late re-init log in sriov

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of wentalou 

Sent: Wednesday, January 2, 2019 3:03:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: Lou, Wentao
Subject: [PATCH] drm/amdgpu: distinguish early and late re-init log in sriov

distinguish ip_reinit_early_sriov and ip_reinit_late_sriov
by different log RE-INIT-early and RE-INIT-late

Change-Id: If4dd78cb807790e9f8daffb04d893cc7fd2b0e60
Signed-off-by: Wentao Lou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7ff3a28..03b73c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2133,7 +2133,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct 
amdgpu_device *adev)
 continue;

 r = block->version->funcs->hw_init(adev);
-   DRM_INFO("RE-INIT: %s %s\n", 
block->version->funcs->name, r?"failed":"succeeded");
+   DRM_INFO("RE-INIT-early: %s %s\n", 
block->version->funcs->name, r?"failed":"succeeded");
 if (r)
 return r;
 }
@@ -2167,7 +2167,7 @@ static int amdgpu_device_ip_reinit_late_sriov(struct 
amdgpu_device *adev)
 continue;

 r = block->version->funcs->hw_init(adev);
-   DRM_INFO("RE-INIT: %s %s\n", 
block->version->funcs->name, r?"failed":"succeeded");
+   DRM_INFO("RE-INIT-late: %s %s\n", 
block->version->funcs->name, r?"failed":"succeeded");
 if (r)
 return r;
 }
--
2.7.4

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Re: [PATCH] drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test sequence

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Zhou, 
Tiecheng 
Sent: Friday, December 28, 2018 12:36:17 AM
To: Zhou, Tiecheng; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings 
test sequence

Ping...

-Original Message-
From: amd-gfx  On Behalf Of Tiecheng Zhou
Sent: Thursday, December 27, 2018 4:15 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, Tiecheng 
Subject: [PATCH] drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test 
sequence

The kiq ring and the very first compute ring may fail occasionally if they are 
tested directly following kiq_kcq_enable.

Insert the gfx ring test before kiq ring test to delay the kiq and kcq ring 
tests will fix the issue.

Signed-off-by: Tiecheng Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 48 +--
 1 file changed, 35 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 381f593b..164ffc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4278,9 +4278,8 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device 
*adev)
 amdgpu_ring_clear_ring(ring);
 gfx_v8_0_cp_gfx_start(adev);
 ring->sched.ready = true;
-   r = amdgpu_ring_test_helper(ring);

-   return r;
+   return 0;
 }

 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool 
enable) @@ -4369,10 +4368,9 @@ static int gfx_v8_0_kiq_kcq_enable(struct 
amdgpu_device *adev)
 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 }

-   r = amdgpu_ring_test_helper(kiq_ring);
-   if (r)
-   DRM_ERROR("KCQ enable failed\n");
-   return r;
+   amdgpu_ring_commit(kiq_ring);
+
+   return 0;
 }

 static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req) @@ 
-4709,16 +4707,32 @@ static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
 if (r)
 goto done;

-   /* Test KCQs - reversing the order of rings seems to fix ring test 
failure
-* after GPU reset
-*/
-   for (i = adev->gfx.num_compute_rings - 1; i >= 0; i--) {
+done:
+   return r;
+}
+
+static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev) {
+   int r, i;
+   struct amdgpu_ring *ring;
+
+   /* collect all the ring_tests here, gfx, kiq, compute */
+   ring = &adev->gfx.gfx_ring[0];
+   r = amdgpu_ring_test_helper(ring);
+   if (r)
+   return r;
+
+   ring = &adev->gfx.kiq.ring;
+   r = amdgpu_ring_test_helper(ring);
+   if (r)
+   return r;
+
+   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 ring = &adev->gfx.compute_ring[i];
-   r = amdgpu_ring_test_helper(ring);
+   amdgpu_ring_test_helper(ring);
 }

-done:
-   return r;
+   return 0;
 }

 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) @@ -4739,6 +4753,11 
@@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
 r = gfx_v8_0_kcq_resume(adev);
 if (r)
 return r;
+
+   r = gfx_v8_0_cp_test_all_rings(adev);
+   if (r)
+   return r;
+
 gfx_v8_0_enable_gui_idle_interrupt(adev, true);

 return 0;
@@ -5056,6 +5075,7 @@ static int gfx_v8_0_post_soft_reset(void *handle)  {
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 u32 grbm_soft_reset = 0;
+   struct amdgpu_ring *ring;

 if ((!adev->gfx.grbm_soft_reset) &&
 (!adev->gfx.srbm_soft_reset))
@@ -5086,6 +5106,8 @@ static int gfx_v8_0_post_soft_reset(void *handle)
 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
 gfx_v8_0_cp_gfx_resume(adev);

+   gfx_v8_0_cp_test_all_rings(adev);
+
 adev->gfx.rlc.funcs->start(adev);

 return 0;
--
2.7.4

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Re: [PATCH] drm/amd/powerplay: support BOOTUP_DEFAULT power profile mode

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Evan Quan 

Sent: Thursday, December 27, 2018 2:50:38 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: support BOOTUP_DEFAULT power profile mode

This can avoid unexpected profile mode change after running
compute workload.

Change-Id: I138e8747e4f588a6fb38b9c68f765bb653556dc0
Signed-off-by: Evan Quan 
---
 .../gpu/drm/amd/include/kgd_pp_interface.h| 13 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   | 24 ++-
 .../gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c  |  8 ---
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 12 ++
 .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 10 +---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |  2 +-
 6 files changed, 40 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 1479ea1dc3e7..789c4f288485 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -127,12 +127,13 @@ enum amd_pp_task {
 };

 enum PP_SMC_POWER_PROFILE {
-   PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x0,
-   PP_SMC_POWER_PROFILE_POWERSAVING  = 0x1,
-   PP_SMC_POWER_PROFILE_VIDEO= 0x2,
-   PP_SMC_POWER_PROFILE_VR   = 0x3,
-   PP_SMC_POWER_PROFILE_COMPUTE  = 0x4,
-   PP_SMC_POWER_PROFILE_CUSTOM   = 0x5,
+   PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
+   PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
+   PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
+   PP_SMC_POWER_PROFILE_VIDEO= 0x3,
+   PP_SMC_POWER_PROFILE_VR   = 0x4,
+   PP_SMC_POWER_PROFILE_COMPUTE  = 0x5,
+   PP_SMC_POWER_PROFILE_CUSTOM   = 0x6,
 };

 enum {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 0173d0480024..310b102a9292 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -64,17 +64,19 @@ static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);

 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
 {
-   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2;
-   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0;
-   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1;
-   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
-   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;
-
-   hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
-   hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
-   hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
-   hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
-   hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
+   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
+   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
+   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
+   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
+   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
+   hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
+
+   hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+   hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+   hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
+   hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
+   hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
+   hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 }

 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index d91390459326..c8f5c00dd1e7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -77,8 +77,9 @@
 #define PCIE_BUS_CLK1
 #define TCLK(PCIE_BUS_CLK / 10)

-static const struct profile_mode_setting smu7_profiling[6] =
-   {{1, 0, 100, 30, 1, 0, 100, 10},
+static const struct profile_mode_setting smu7_profiling[7] =
+   {{0, 0, 0, 0, 0, 0, 0, 0},
+{1, 0, 100, 30, 1, 0, 100, 10},
  {1, 10, 0, 30, 0, 0, 0, 0},
  {0, 0, 0, 0, 1, 10, 16, 31},
  {1, 0, 11, 50, 1, 0, 100, 10},
@@ -4889,7 +4890,8 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr 
*hwmgr, char *buf)
 uint32_t i, size = 0;
 uint32_t len;

-   static const char *profile_name[6] = {"3D_FULL_SCREEN",
+   static const char *profile_name[7] = {"BOOTUP_DEFAULT"

Re: [PATCH] drm/amdgpu/gmc: fix compiler errors [-Werror,-Wmissing-braces]

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of S, Shirish 

Sent: Thursday, December 20, 2018 9:01:33 AM
To: Li, Sun peng (Leo); Wentland, Harry; Deucher, Alexander; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org; S, Shirish
Subject: [PATCH] drm/amdgpu/gmc: fix compiler errors [-Werror,-Wmissing-braces]

Initializing structures with { } is known to be problematic since
it doesn't necessararily initializes all bytes, in case of padding,
causing random failures when structures are memcmp().

This patch fixes the structure initialisation compiler error by memsetting
the entire structure elements instead of only the first one.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 1ad7e6b..3444067 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1471,8 +1471,9 @@ static int gmc_v8_0_process_interrupt(struct 
amdgpu_device *adev,
 gmc_v8_0_set_fault_enable_default(adev, false);

 if (printk_ratelimit()) {
-   struct amdgpu_task_info task_info = { 0 };
+   struct amdgpu_task_info task_info;

+   memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);

 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process 
%s pid %d thread %s pid %d\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index bacdaef..2bfddce 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -320,8 +320,9 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device 
*adev,
 }

 if (printk_ratelimit()) {
-   struct amdgpu_task_info task_info = { 0 };
+   struct amdgpu_task_info task_info;

+   memset(&task_info, 0, sizeof(amdgpu_task_info));
 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);

 dev_err(adev->dev,
--
2.7.4

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Re: [PATCH] drm/amd/display: fix compliler errors [-Werror,-Wmissing-braces]

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of S, Shirish 

Sent: Thursday, December 20, 2018 9:01:04 AM
To: Li, Sun peng (Leo); Wentland, Harry; Deucher, Alexander; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org; S, Shirish
Subject: [PATCH] drm/amd/display: fix compliler errors 
[-Werror,-Wmissing-braces]

Initializing structures with { } is known to be problematic since
it doesn't necessararily initializes all bytes, in case of padding,
causing random failures when structures are memcmp().

This patch fixes the structure initialisation compiler error by memsetting
the entire structure elements instead of only the first one.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c   | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0bd33a7..1b5630f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -92,9 +92,10 @@ static void log_mpc_crc(struct dc *dc,
 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
 {
 struct dc_context *dc_ctx = dc->ctx;
-   struct dcn_hubbub_wm wm = {0};
+   struct dcn_hubbub_wm wm;
 int i;

+   memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
 hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);

 DTN_INFO("HUBBUB WM:  data_urgent  pte_meta_urgent"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index cd46901..3fccec2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -72,7 +72,7 @@ static unsigned int snprintf_count(char *pBuf, unsigned int 
bufSize, char *fmt,
 static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned 
int bufSize)
 {
 struct dc_context *dc_ctx = dc->ctx;
-   struct dcn_hubbub_wm wm = {0};
+   struct dcn_hubbub_wm wm;
 int i;

 unsigned int chars_printed = 0;
@@ -81,6 +81,7 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, 
char *pBuf, unsigned i
 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 
1000;
 static const unsigned int frac = 1000;

+   memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
 hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);

 chars_printed = snprintf_count(pBuf, remaining_buffer, 
"wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_chanage\n");
--
2.7.4

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Re: [PATCH] drm/amd/display: Fix MST dp_blank REG_WAIT timeout

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Harry 
Wentland 
Sent: Wednesday, December 19, 2018 2:14:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zuo, Jerry
Subject: [PATCH] drm/amd/display: Fix MST dp_blank REG_WAIT timeout

From: "Jerry (Fangzhi) Zuo" 

Need to blank stream before deallocate MST payload.

[drm:generic_reg_wait [amdgpu]] *ERROR* REG_WAIT timeout 10us * 3000 tries - 
dce110_stream_encoder_dp_blank line:944
[ cut here ]
WARNING: CPU: 0 PID: 2201 at 
/var/lib/dkms/amdgpu/18.50-690240/build/amd/amdgpu/../display/dc/dc_helper.c:249
 generic_reg_wait+0xe7/0x160 [amdgpu]
Call Trace:
 dce110_stream_encoder_dp_blank+0x11c/0x180 [amdgpu]
 core_link_disable_stream+0x40/0x230 [amdgpu]
 ? generic_reg_update_ex+0xdb/0x130 [amdgpu]
 dce110_reset_hw_ctx_wrap+0xb7/0x1f0 [amdgpu]
 dce110_apply_ctx_to_hw+0x30/0x430 [amdgpu]
 ? dce110_apply_ctx_for_surface+0x206/0x260 [amdgpu]
 dc_commit_state+0x2ba/0x4d0 [amdgpu]
 amdgpu_dm_atomic_commit_tail+0x297/0xd70 [amdgpu]
 ? amdgpu_bo_pin_restricted+0x58/0x260 [amdgpu]
 ? wait_for_completion_timeout+0x1f/0x120
 ? wait_for_completion_interruptible+0x1c/0x160
 commit_tail+0x3d/0x60 [drm_kms_helper]
 drm_atomic_helper_commit+0xf6/0x100 [drm_kms_helper]
 drm_atomic_connector_commit_dpms+0xe5/0xf0 [drm]
 drm_mode_obj_set_property_ioctl+0x14f/0x250 [drm]
 drm_mode_connector_property_set_ioctl+0x2e/0x40 [drm]
 drm_ioctl+0x1e0/0x430 [drm]
 ? drm_mode_connector_set_obj_prop+0x70/0x70 [drm]
 ? ep_read_events_proc+0xb0/0xb0
 ? ep_scan_ready_list.constprop.18+0x1e6/0x1f0
 ? timerqueue_add+0x52/0x80
 amdgpu_drm_ioctl+0x49/0x80 [amdgpu]
 do_vfs_ioctl+0x90/0x5f0
 SyS_ioctl+0x74/0x80
 do_syscall_64+0x74/0x140
 entry_SYSCALL_64_after_hwframe+0x3d/0xa2
---[ end trace 3ed7b77a97d60f72 ]---

Signed-off-by: Jerry (Fangzhi) Zuo 
Reviewed-by: Hersen Wu 
Acked-by: Harry Wentland 
Tested-by: Lyude Paul 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a87db7ac2e46..3dd5f2717b53 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2636,11 +2636,11 @@ void core_link_disable_stream(struct pipe_ctx 
*pipe_ctx, int option)
 {
 struct dc  *core_dc = pipe_ctx->stream->ctx->dc;

+   core_dc->hwss.blank_stream(pipe_ctx);
+
 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
 deallocate_mst_payload(pipe_ctx);

-   core_dc->hwss.blank_stream(pipe_ctx);
-
 core_dc->hwss.disable_stream(pipe_ctx, option);

 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
--
2.19.1

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Re: Powerplay clock information missing on Polaris 12 (msi RX550 LP OC) on armhf

[Deucher, Alexander]

Those messages are harmless and can be ignored.  I think they have been removed 
in newer kernels.


Alex


From: amd-gfx  on behalf of Luís Mendes 

Sent: Wednesday, December 19, 2018 12:31:44 PM
To: Koenig, Christian; amd-gfx list
Subject: Powerplay clock information missing on Polaris 12 (msi RX550 LP OC) on 
armhf

Hi,

Just want to report this issue for the Polaris 12, RX550, with kernel 4.19.9
[   20.272719] amdgpu: [powerplay] Failed to retrieve minimum clocks.
[   20.272723] amdgpu: [powerplay] Error in phm_get_clock_info


dmesg excerpt of relevant amdgpu initialization follows below.

Regards,
Luís Mendes, Researcher, Instituto Superior Técnico
Hardware and Software engineer
https://tecnico.ulisboa.pt/en/



[   18.679841] [drm] initializing kernel modesetting (POLARIS12
0x1002:0x699F 0x1462:0x8A90 0xC7).
[   18.679854] [drm] register mmio base: 0xE020
[   18.679856] [drm] register mmio size: 262144
[   18.679898] [drm] add ip block number 0 
[   18.679900] [drm] add ip block number 1 
[   18.679902] [drm] add ip block number 2 
[   18.679903] [drm] add ip block number 3 
[   18.679906] [drm] add ip block number 4 
[   18.679907] [drm] add ip block number 5 
[   18.679909] [drm] add ip block number 6 
[   18.679911] [drm] add ip block number 7 
[   18.679913] [drm] add ip block number 8 
[   18.679937] [drm] UVD is enabled in VM mode
[   18.679938] [drm] UVD ENC is enabled in VM mode
[   18.679942] [drm] VCE enabled in VM mode
[   18.890422] ATOM BIOS: 113-D090LP-M11
[   18.890467] [drm] GPU posting now...
[   18.945707] snd_hda_intel :01:00.1: enabling device (0140 -> 0142)
[   18.945718] snd_hda_intel :01:00.1: Force to snoop mode by module option
[   19.027723] [drm] vm size is 64 GB, 2 levels, block size is 10-bit,
fragment size is 9-bit
[   19.052235] input: HDA ATI HDMI HDMI/DP,pcm=3 as
/devices/platform/soc/soc:pcie/pci:00/:00:01.0/:01:00.1/sound/card0/input2
[   19.491128] amdgpu :01:00.0: VRAM: 4096M 0x00F4 -
0x00F4 (4096M used)
[   19.491136] amdgpu :01:00.0: GART: 256M 0x -
0x0FFF
[   19.491141] [drm] Detected VRAM RAM=4096M, BAR=256M
[   19.491143] [drm] RAM width 128bits GDDR5
[   19.491286] [TTM] Zone  kernel: Available graphics memory: 375104 kiB
[   19.491289] [TTM] Zone highmem: Available graphics memory: 1030464 kiB
[   19.491291] [TTM] Initializing pool allocator
[   19.491311] [drm] amdgpu: 4096M of VRAM memory ready
[   19.491314] [drm] amdgpu: 1509M of GTT memory ready.
[   19.491352] [drm] GART: num cpu pages 65536, num gpu pages 65536
[   19.492115] [drm] PCIE GART of 256M enabled (table at 0x00F4).
[   19.633585] [drm] Chained IB support enabled!
[   20.075528] [drm] Found UVD firmware Version: 1.130 Family ID: 16
[   20.135798] [drm] Found VCE firmware Version: 53.26 Binary ID: 3
[   20.272719] amdgpu: [powerplay] Failed to retrieve minimum clocks.
[   20.272723] amdgpu: [powerplay] Error in phm_get_clock_info
[   20.272854] [drm] DM_PPLIB: values for Engine clock
[   20.272858] [drm] DM_PPLIB: 214000
[   20.272859] [drm] DM_PPLIB: 551000
[   20.272860] [drm] DM_PPLIB: 746000
[   20.272862] [drm] DM_PPLIB: 995000
[   20.272863] [drm] DM_PPLIB: 1063000
[   20.272864] [drm] DM_PPLIB: 1116000
[   20.272866] [drm] DM_PPLIB: 1142000
[   20.272867] [drm] DM_PPLIB: 1203000
[   20.272869] [drm] DM_PPLIB: Validation clocks:
[   20.272871] [drm] DM_PPLIB:engine_max_clock: 120300
[   20.272873] [drm] DM_PPLIB:memory_max_clock: 175000
[   20.272874] [drm] DM_PPLIB:level   : 8
[   20.272879] [drm] DM_PPLIB: values for Memory clock
[   20.272880] [drm] DM_PPLIB: 30
[   20.272881] [drm] DM_PPLIB: 625000
[   20.272883] [drm] DM_PPLIB: 175
[   20.272884] [drm] DM_PPLIB: Validation clocks:
[   20.272886] [drm] DM_PPLIB:engine_max_clock: 120300
[   20.272887] [drm] DM_PPLIB:memory_max_clock: 175000
[   20.272888] [drm] DM_PPLIB:level   : 8
[   20.276533] [drm] Display Core initialized with v3.1.59!
[   20.291991] [drm] SADs count is: -2, don't need to read it
[   20.292825] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[   20.292827] [drm] Driver supports precise vblank timestamp query.
[   20.340483] [drm] UVD and UVD ENC initialized successfully.
[   20.420775] Adding 19450708k swap on /dev/sda3.  Priority:-2
extents:1 across:19450708k FS
[   20.441642] [drm] VCE initialized successfully.
[   20.447024] [drm] fb mappable at 0xD0528000
[   20.447028] [drm] vram apper at 0xD000
[   20.447030] [drm] size 5242880
[   20.447032] [drm] fb depth is 24
[   20.447033] [drm]pitch is 5120
[   20.474428] Console: switching to colour frame buffer device 160x64
[   20.620688] amdgpu :01:00.0: fb0: amdgpudrmfb frame buffer device
[   20.663591] [drm] Initialized amdgpu 3.27.0 20150101 for
:01:00.0 on minor 0
___
a

Re: [PATCH] drm/amd/display: Use div_u64 for flip timestamp ns to ms

[Deucher, Alexander]

Could also use do_div.  Either way:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Nicholas 
Kazlauskas 
Sent: Wednesday, December 19, 2018 9:12:09 AM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Sun peng (Leo); Wentland, Harry; Kazlauskas, Nicholas
Subject: [PATCH] drm/amd/display: Use div_u64 for flip timestamp ns to ms

Resolves __udivdi3 missing errors when building for i386.

Fixes: 6378ef012ddc ("drm/amd/display: Add below the range support for 
FreeSync")

Change-Id: I4ded5790160054e6908367f20a63257225517714
Cc: Leo Li 
Cc: Harry Wentland 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e16e62139ec3..920649332055 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4550,6 +4550,7 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
   struct dc_state *state)
 {
 unsigned long flags;
+   uint64_t timestamp_ns;
 uint32_t target_vblank;
 int r, vpos, hpos;
 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
@@ -4612,7 +4613,9 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
 addr.flip_immediate = async_flip;
-   addr.flip_timestamp_in_us = ktime_get_ns() / 1000;
+
+   timestamp_ns = ktime_get_ns();
+   addr.flip_timestamp_in_us = div_u64(timestamp_ns, 1000);


 if (acrtc->base.state->event)
--
2.17.1

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Re: [PATCH] drm/amdgpu/uvd:Change uvd ring name convention

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Zhu, James 

Sent: Tuesday, December 18, 2018 4:07:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: jzh...@gmail.com
Subject: [PATCH] drm/amdgpu/uvd:Change uvd ring name convention

Since umr tool can't handle bracket, change uvd ring name convention.

Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 089645e..aef9240 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -435,7 +435,7 @@ static int uvd_v7_0_sw_init(void *handle)
 continue;
 if (!amdgpu_sriov_vf(adev)) {
 ring = &adev->uvd.inst[j].ring;
-   sprintf(ring->name, "uvd<%d>", j);
+   sprintf(ring->name, "uvd_%d", ring->me);
 r = amdgpu_ring_init(adev, ring, 512, 
&adev->uvd.inst[j].irq, 0);
 if (r)
 return r;
@@ -443,7 +443,7 @@ static int uvd_v7_0_sw_init(void *handle)

 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 ring = &adev->uvd.inst[j].ring_enc[i];
-   sprintf(ring->name, "uvd_enc%d<%d>", i, j);
+   sprintf(ring->name, "uvd_enc_%d.%d", ring->me, i);
 if (amdgpu_sriov_vf(adev)) {
 ring->use_doorbell = true;

--
2.7.4

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Re: [PATCH] drm/amdgpu: correct the return value for error case

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Evan Quan 

Sent: Monday, December 17, 2018 4:59:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amdgpu: correct the return value for error case

It should not return 0 for error case as '0' is actually
a special value for index.

Change-Id: Iced8b4427d4403f86826a7c8e3c9d1da3394246c
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h  | 12 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 15 +--
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c   | 20 
 3 files changed, 31 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 24dea17b4161..ee26181222ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -83,8 +83,8 @@ struct psp_funcs
   enum AMDGPU_UCODE_ID ucode_type);
 bool (*smu_reload_quirk)(struct psp_context *psp);
 int (*mode1_reset)(struct psp_context *psp);
-   uint64_t (*xgmi_get_node_id)(struct psp_context *psp);
-   uint64_t (*xgmi_get_hive_id)(struct psp_context *psp);
+   int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id);
+   int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id);
 int (*xgmi_get_topology_info)(struct psp_context *psp, int 
number_devices,
   struct psp_xgmi_topology_info *topology);
 int (*xgmi_set_topology_info)(struct psp_context *psp, int 
number_devices,
@@ -216,10 +216,10 @@ struct tmz_clear_vpr {
 ((psp)->funcs->support_vmr_ring ? 
(psp)->funcs->support_vmr_ring((psp)) : false)
 #define psp_mode1_reset(psp) \
 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) 
: false)
-#define psp_xgmi_get_node_id(psp) \
-   ((psp)->funcs->xgmi_get_node_id ? 
(psp)->funcs->xgmi_get_node_id((psp)) : 0)
-#define psp_xgmi_get_hive_id(psp) \
-   ((psp)->funcs->xgmi_get_hive_id ? 
(psp)->funcs->xgmi_get_hive_id((psp)) : 0)
+#define psp_xgmi_get_node_id(psp, node_id) \
+   ((psp)->funcs->xgmi_get_node_id ? 
(psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
+#define psp_xgmi_get_hive_id(psp, hive_id) \
+   ((psp)->funcs->xgmi_get_hive_id ? 
(psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL)
 #define psp_xgmi_get_topology_info(psp, num_device, topology) \
 ((psp)->funcs->xgmi_get_topology_info ? \
 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), 
(topology)) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 0b263a9857c6..8a8bc60cb6b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -97,8 +97,19 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
 if (!adev->gmc.xgmi.supported)
 return 0;

-   adev->gmc.xgmi.node_id = psp_xgmi_get_node_id(&adev->psp);
-   adev->gmc.xgmi.hive_id = psp_xgmi_get_hive_id(&adev->psp);
+   ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
+   if (ret) {
+   dev_err(adev->dev,
+   "XGMI: Failed to get node id\n");
+   return ret;
+   }
+
+   ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
+   if (ret) {
+   dev_err(adev->dev,
+   "XGMI: Failed to get hive id\n");
+   return ret;
+   }

 mutex_lock(&xgmi_mutex);
 hive = amdgpu_get_xgmi_hive(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 0a390a9544b5..d9b4a3aca3be 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -704,7 +704,7 @@ static int psp_v11_0_xgmi_set_topology_info(struct 
psp_context *psp,
 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
 }

-static u64 psp_v11_0_xgmi_get_hive_id(struct psp_context *psp)
+static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t 
*hive_id)
 {
 struct ta_xgmi_shared_memory *xgmi_cmd;
 int ret;
@@ -717,12 +717,14 @@ static u64 psp_v11_0_xgmi_get_hive_id(struct psp_context 
*psp)
 /* Invoke xgmi ta to get hive id */
 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 if (ret)
-   return 0;
-   else
-   return xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
+   return ret;
+
+   *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
+
+   return 0;
 }

-static u64 psp_v11_0_xgmi_get_node_id(struct psp_context *psp)
+static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t 
*node_id)
 {
 struct ta_xgmi_shared_memory *xgmi_cmd;
   

Re: [PATCH 1/1] drm/amdkfd: Fix handling of return code of dma_buf_get

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Kuehling, 
Felix 
Sent: Friday, December 14, 2018 2:05:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix
Subject: [PATCH 1/1] drm/amdkfd: Fix handling of return code of dma_buf_get

On errors, dma_buf_get returns a negative error code, rather than NULL.

Reported-by: Dan Carpenter 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 3623538..db6f27f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1629,8 +1629,8 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,
 return -EINVAL;

 dmabuf = dma_buf_get(args->dmabuf_fd);
-   if (!dmabuf)
-   return -EINVAL;
+   if (IS_ERR(dmabuf))
+   return PTR_ERR(dmabuf);

 mutex_lock(&p->mutex);

--
2.7.4

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Re: [PATCH] drm/amdgpu: fix IH overflow on Vega10

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: Christian König 
Sent: Friday, December 14, 2018 9:37:23 AM
To: Deucher, Alexander; alexdeuc...@gmail.com; amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: fix IH overflow on Vega10

When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR doesn't trigger another memory writeback.

So what can happen is that we end up processing the buffer overflow over and
over again because the bit is never cleared. Resulting in a random system
lockup because of an infinite loop in an interrupt handler.

This is 100% reproducible on Vega10, but it's most likely an issue we have
in the driver over all generations all the way back to radeon.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 68 --
 1 file changed, 43 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 992c8a8b8f77..0ab7785079c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -276,31 +276,49 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,

 wptr = le32_to_cpu(*ih->wptr_cpu);

-   if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
-   wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
-
-   /* When a ring buffer overflow happen start parsing interrupt
-* from the last not overwritten vector (wptr + 32). Hopefully
-* this should allow us to catchup.
-*/
-   tmp = (wptr + 32) & ih->ptr_mask;
-   dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 
0x%08X)\n",
-wptr, ih->rptr, tmp);
-   ih->rptr = tmp;
-
-   if (ih == &adev->irq.ih)
-   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
-   else if (ih == &adev->irq.ih1)
-   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
-   else if (ih == &adev->irq.ih2)
-   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
-   else
-   BUG();
-
-   tmp = RREG32_NO_KIQ(reg);
-   tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
-   WREG32_NO_KIQ(reg, tmp);
-   }
+   if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
+   goto out;
+
+   /* Double check that the overflow wasn't already cleared. */
+   if (ih == &adev->irq.ih)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
+   else if (ih == &adev->irq.ih1)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
+   else if (ih == &adev->irq.ih2)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
+   else
+   BUG();
+
+   wptr = RREG32_NO_KIQ(reg);
+   if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
+   goto out;
+
+   wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
+
+   /* When a ring buffer overflow happen start parsing interrupt
+* from the last not overwritten vector (wptr + 32). Hopefully
+* this should allow us to catchup.
+*/
+   tmp = (wptr + 32) & ih->ptr_mask;
+   dev_warn(adev->dev, "IH ring buffer overflow "
+"(0x%08X, 0x%08X, 0x%08X)\n",
+wptr, ih->rptr, tmp);
+   ih->rptr = tmp;
+
+   if (ih == &adev->irq.ih)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
+   else if (ih == &adev->irq.ih1)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+   else if (ih == &adev->irq.ih2)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+   else
+   BUG();
+
+   tmp = RREG32_NO_KIQ(reg);
+   tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
+   WREG32_NO_KIQ(reg, tmp);
+
+out:
 return (wptr & ih->ptr_mask);
 }

--
2.17.1

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Re: [PATCH] drm/amdgpu: WARN once if amdgpu_bo_unpin is called for an unpinned BO

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Thursday, December 13, 2018 11:06:35 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: WARN once if amdgpu_bo_unpin is called for an 
unpinned BO

From: Michel Dänzer 

It indicates a pin/unpin imbalance bug somewhere. While the bug isn't
necessarily in the call chain hitting this, it's at least one part
involved.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index fd271f9746a2..728e15e5d68a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -912,7 +912,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 struct ttm_operation_ctx ctx = { false, false };
 int r, i;

-   if (!bo->pin_count) {
+   if (WARN_ON_ONCE(!bo->pin_count)) {
 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 return 0;
 }
--
2.20.0.rc2

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Re: [PATCH] drm/amdgpu: unify Vega20 PSP SOS firmwares for A0 and A1

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Evan Quan 

Sent: Thursday, December 13, 2018 1:14:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amdgpu: unify Vega20 PSP SOS firmwares for A0 and A1

The new PSP SOS firmware can support both A0 and A1.

Change-Id: I9bf85eb77b183a4403667c77e291e32689aed0af
---
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 12 +---
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 61cf2f6954e7..f3f5d4dd4631 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -34,14 +34,11 @@
 #include "nbio/nbio_7_4_offset.h"

 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
-MODULE_FIRMWARE("amdgpu/vega20_sos_old.bin");
 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");

 /* address block */
 #define smnMP1_FIRMWARE_FLAGS   0x3010024

-#define VEGA20_BL_VERSION_VAR_NEW 0xA1
-
 static int
 psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type 
*type)
 {
@@ -104,7 +101,6 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
 int err = 0;
 const struct psp_firmware_header_v1_0 *sos_hdr;
 const struct ta_firmware_header_v1_0 *ta_hdr;
-   uint32_t bl_version;

 DRM_DEBUG("\n");

@@ -116,13 +112,7 @@ static int psp_v11_0_init_microcode(struct psp_context 
*psp)
 BUG();
 }

-   bl_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_100);
-   bl_version = (bl_version & 0xFF) >> 16;
-
-   if (bl_version == VEGA20_BL_VERSION_VAR_NEW)
-   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", 
chip_name);
-   else
-   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos_old.bin", 
chip_name);
+   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
 if (err)
 goto out;
--
2.19.2

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Re: [PATCH libdrm] tests/amdgpu/vcn: fix the nop command in IBs

[Deucher, Alexander]

Reviewed-by: Alex Deucher 



From: amd-gfx  on behalf of Liu, Leo 

Sent: Tuesday, December 11, 2018 4:03 PM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Liu, Leo
Subject: [PATCH libdrm] tests/amdgpu/vcn: fix the nop command in IBs

Just make them properly i.e. put 0 to the Nop reg

Signed-off-by: Leo Liu 
---
 tests/amdgpu/vcn_tests.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index d9f05af8..859ec496 100644
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -268,8 +268,10 @@ static void amdgpu_cs_vcn_dec_create(void)
 ib_cpu[len++] = msg_buf.addr >> 32;
 ib_cpu[len++] = 0x81C3;
 ib_cpu[len++] = 0;
-   for (; len % 16; ++len)
-   ib_cpu[len] = 0x81ff;
+   for (; len % 16; ) {
+   ib_cpu[len++] = 0x81ff;
+   ib_cpu[len++] = 0;
+   }

 r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 CU_ASSERT_EQUAL(r, 0);
@@ -336,8 +338,10 @@ static void amdgpu_cs_vcn_dec_decode(void)

 ib_cpu[len++] = 0x81C6;
 ib_cpu[len++] = 0x1;
-   for (; len % 16; ++len)
-   ib_cpu[len] = 0x8000;
+   for (; len % 16; ) {
+   ib_cpu[len++] = 0x81ff;
+   ib_cpu[len++] = 0;
+   }

 r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 CU_ASSERT_EQUAL(r, 0);
@@ -373,8 +377,10 @@ static void amdgpu_cs_vcn_dec_destroy(void)
 ib_cpu[len++] = msg_buf.addr >> 32;
 ib_cpu[len++] = 0x81C3;
 ib_cpu[len++] = 0;
-   for (; len % 16; ++len)
-   ib_cpu[len] = 0x8000;
+   for (; len % 16; ) {
+   ib_cpu[len++] = 0x81ff;
+   ib_cpu[len++] = 0;
+   }

 r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 CU_ASSERT_EQUAL(r, 0);
--
2.17.1

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Re: [PATCH] drm/amdgpu: Enable GPU recovery by default for CI

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Andrey 
Grodzovsky 
Sent: Tuesday, December 11, 2018 3:35:16 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Grodzovsky, Andrey
Subject: [PATCH] drm/amdgpu: Enable GPU recovery by default for CI

I retested Bonaire (gfx7 dGPU) and it works fine.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 42111d5..71a9e18 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3258,6 +3258,8 @@ bool amdgpu_device_should_recover_gpu(struct 
amdgpu_device *adev)

 if (amdgpu_gpu_recovery == -1) {
 switch (adev->asic_type) {
+   case CHIP_BONAIRE:
+   case CHIP_HAWAII:
 case CHIP_TOPAZ:
 case CHIP_TONGA:
 case CHIP_FIJI:
--
2.7.4

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Re: [PATCH] drm/amdgpu:skip ASIC_INIT when posting card on vg20

[Deucher, Alexander]

vbios asic init will still work.  It will wait on the psp init so I'd suggest 
we just drop this patch to keep the code consistent.  There are also possibly 
some registers that are handled by vbios asic init rather than psp.


Alex


From: amd-gfx  on behalf of Feifei Xu 

Sent: Sunday, December 9, 2018 11:45:52 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei
Subject: [PATCH] drm/amdgpu:skip ASIC_INIT when posting card on vg20

On vega20, the job of executing the ASIC_INIT table when posting card
is moved to psp. Skip the atombios's ASIC_INIT on vega20 when posting
card.

Change-Id: Id1d3c0a0d19296d5ed804de7edf5b09b8d38c0a5
Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f2bda76c8e05..310d4eb0536b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2513,8 +2513,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 /* detect if we are with an SRIOV vbios */
 amdgpu_device_detect_sriov_bios(adev);

+DRM_INFO("skip posting card using ASIC INIT table in vbios on vega20\n");
 /* Post card if necessary */
-   if (amdgpu_device_need_post(adev)) {
+   if ((adev->asic_type != CHIP_VEGA20) && amdgpu_device_need_post(adev)) {
 if (!adev->bios) {
 dev_err(adev->dev, "no vBIOS found\n");
 r = -EINVAL;
--
2.17.1

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Re: [PATCH 1/2] drm/amdkfd: add new vega10 pci ids

[Deucher, Alexander]

Care to review the amdgpu series as well?


From: amd-gfx  on behalf of Kuehling, 
Felix 
Sent: Friday, December 7, 2018 4:38:20 PM
To: Alex Deucher; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; sta...@vger.kernel.org
Subject: Re: [PATCH 1/2] drm/amdkfd: add new vega10 pci ids

On 2018-12-07 4:26 p.m., Alex Deucher wrote:
> New vega10 ids.
>
> Signed-off-by: Alex Deucher 

The series is Reviewed-by: Felix Kuehling 


> Cc: sta...@vger.kernel.org
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_device.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index 9ed14a11afa2..b78b3c2fa9d8 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -378,7 +378,13 @@ static const struct kfd_deviceid supported_devices[] = {
>{ 0x6864, &vega10_device_info },/* Vega10 */
>{ 0x6867, &vega10_device_info },/* Vega10 */
>{ 0x6868, &vega10_device_info },/* Vega10 */
> + { 0x6869, &vega10_device_info },/* Vega10 */
> + { 0x686A, &vega10_device_info },/* Vega10 */
> + { 0x686B, &vega10_device_info },/* Vega10 */
>{ 0x686C, &vega10_vf_device_info }, /* Vega10  vf*/
> + { 0x686D, &vega10_device_info },/* Vega10 */
> + { 0x686E, &vega10_device_info },/* Vega10 */
> + { 0x686F, &vega10_device_info },/* Vega10 */
>{ 0x687F, &vega10_device_info },/* Vega10 */
>{ 0x69A0, &vega12_device_info },/* Vega12 */
>{ 0x69A1, &vega12_device_info },/* Vega12 */
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Re: [PATCH] drm/amdgpu: Workaround build failure due to trace conflict

[Deucher, Alexander]

Acked-by: Alex Deucher 



From: amd-gfx  on behalf of Kuehling, 
Felix 
Sent: Friday, December 7, 2018 5:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix
Subject: [PATCH] drm/amdgpu: Workaround build failure due to trace conflict

Avoid including mmu_context.h in amdgpu_amdkfd.h since that may be
included in other header files that define traces. This leads to
conflicts due to traces defined in other headers included via
mmu_context.h.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 1 +
 4 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index bcf587b..86cf1a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -27,7 +27,6 @@

 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 72a357d..ff7fac7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 0e2a56b..56ea929 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 03b604c..5c51d491 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
--
2.7.4

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Re: [PATCH 1/2] drm/amdgpu: add some additional vega10 pci ids

[Deucher, Alexander]

Will do.


Alex


From: Kuehling, Felix
Sent: Friday, December 7, 2018 4:14:39 PM
To: Alex Deucher; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; sta...@vger.kernel.org
Subject: Re: [PATCH 1/2] drm/amdgpu: add some additional vega10 pci ids

Can you add them amdkfd/kfd_device.c as well while you're at it.

Thanks,
  Felix

On 2018-12-07 4:03 p.m., Alex Deucher wrote:
> New vega ids.
>
> Signed-off-by: Alex Deucher 
> Cc: sta...@vger.kernel.org
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 90f474f98b6e..e32f6f43a46b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -873,7 +873,13 @@ static const struct pci_device_id pciidlist[] = {
>{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
>{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
>{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
> + {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
> + {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
> + {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
>{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
> + {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
> + {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
> + {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
>{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
>/* Vega 12 */
>{0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
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Re: [PATCH] Revert "drm/amd/display: Set RMX_ASPECT as default"

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Nicholas 
Kazlauskas 
Sent: Friday, December 7, 2018 12:15:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Sun peng (Leo); Wentland, Harry; Lakha, Bhawanpreet; Kazlauskas, 
Nicholas
Subject: [PATCH] Revert "drm/amd/display: Set RMX_ASPECT as default"

This reverts commit 91b66c47ba3468f7882ea4a84d5e0e0c186b638f.

Forcing RMX_ASPECT as default uses the preferred/native mode's timings
for any mode the user selects and scales the image. This provides a
a consistently nicer result in the case where the selected mode's
refresh rate matches the native mode's refresh but this isn't always
the case.

For example, if the monitor is 1080p@144Hz and the preferred mode is
60Hz then even if the user selects 1080p@144Hz as their selected mode
they'll get 1080p@60Hz.

Cc: Bhawanpreet Lakha 
Cc: Leo Li 
Cc: Harry Wentland 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 23d61570df17..fa2b00ad1713 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3100,10 +3100,8 @@ int amdgpu_dm_connector_atomic_set_property(struct 
drm_connector *connector,
 rmx_type = RMX_FULL;
 break;
 case DRM_MODE_SCALE_NONE:
-   rmx_type = RMX_OFF;
-   break;
 default:
-   rmx_type = RMX_ASPECT;
+   rmx_type = RMX_OFF;
 break;
 }

@@ -3216,7 +3214,7 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector 
*connector)
 state = kzalloc(sizeof(*state), GFP_KERNEL);

 if (state) {
-   state->scaling = RMX_ASPECT;
+   state->scaling = RMX_OFF;
 state->underscan_enable = false;
 state->underscan_hborder = 0;
 state->underscan_vborder = 0;
--
2.17.1

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Re: [PATCH 1/2] drm/amdgpu: update SMC firmware image for polaris10 variants

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Junwei Zhang 

Sent: Friday, December 7, 2018 2:19:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jerry
Subject: [PATCH 1/2] drm/amdgpu: update SMC firmware image for polaris10 
variants

Some new variants require different firmwares.

Signed-off-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index ceadeeadfa56..387f1cf1dc20 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -381,7 +381,8 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device 
*cgs_device,
   (adev->pdev->revision == 0xe7) ||
   (adev->pdev->revision == 0xef))) 
||
 ((adev->pdev->device == 0x6fdf) &&
-(adev->pdev->revision == 0xef))) {
+((adev->pdev->revision == 0xef) ||
+ (adev->pdev->revision == 0xff 
{
 info->is_kicker = true;
 strcpy(fw_name, 
"amdgpu/polaris10_k_smc.bin");
 } else if ((adev->pdev->device == 
0x67df) &&
--
2.17.1

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Re: [PATCH v2] drm/amdgpu/powerplay: Apply avfs cks-off voltages on VI

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Kenneth Feng 

Sent: Friday, December 7, 2018 1:13:20 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth
Subject: [PATCH v2] drm/amdgpu/powerplay: Apply avfs cks-off voltages on VI

Instead of EVV cks-off voltages, avfs cks-off voltages can avoid
the overshoot voltages when switching sclk.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h  | 2 ++
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 6 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h
index 62f36ba..c1a99df 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu7_ppsmc.h
@@ -386,6 +386,8 @@ typedef uint16_t PPSMC_Result;
 #define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403)
 #define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404)

+#define PPSMC_MSG_ApplyAvfsCksOffVoltage  ((uint16_t) 0x415)
+
 #define PPSMC_MSG_GFX_CU_PG_ENABLE((uint16_t) 0x280)
 #define PPSMC_MSG_GFX_CU_PG_DISABLE   ((uint16_t) 0x281)
 #define PPSMC_MSG_GetCurrPkgPwr   ((uint16_t) 0x282)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 94898b2..d2b97aa 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -1997,6 +1997,12 @@ int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)

 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);

+   /* Apply avfs cks-off voltages to avoid the overshoot
+* when switching to the highest sclk frequency
+*/
+   if (data->apply_avfs_cks_off_voltage)
+   smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage);
+
 return 0;
 }

--
2.7.4

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Re: [PATCH] drm/amdgpu: bypass RLC init under sriov for Tonga

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Tiecheng 
Zhou 
Sent: Thursday, December 6, 2018 9:11:49 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, Tiecheng
Subject: [PATCH] drm/amdgpu: bypass RLC init under sriov for Tonga

SWDEV-173384: vm-mix reboot (4 VMs) fail on Tonga under sriov

Phenomena: there is compute_1.3.1 ring test fail on one VM
   when it starts to do hw_init after it is rebooted

Root cause: RLC will go wrong in soft_reset under sriov

Workaround: init RLC csb, and skip RLC stop, reset, start
this is because GIM has already done
full initialization on RLC

refer to 'commit cfee05bc9057 ("drm/amdgpu:bypass RLC init for SRIOV")'
 and 'commit f840cc5f8447 ("drm/amdgpu/sriov:init csb for gfxv9")'

Signed-off-by: Tiecehng Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 1454fc3..a9c853a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4068,6 +4068,11 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device 
*adev)

 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
 {
+   if (amdgpu_sriov(adev)) {
+   gfx_v8_0_init_csb(adev);
+   return 0;
+   }
+
 adev->gfx.rlc.funcs->stop(adev);
 adev->gfx.rlc.funcs->reset(adev);
 gfx_v8_0_init_pg(adev);
--
2.7.4

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Re: [PATCH] drm/amdgpu: both support PCO FP5/AM4 rlc fw

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Aaron Liu 

Sent: Wednesday, December 5, 2018 8:26:52 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Aaron
Subject: [PATCH] drm/amdgpu: both support PCO FP5/AM4 rlc fw

For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
For Picasso && FP5 SOCKET board, we use picasso_rlc.bin

Judgment method:
PCO AM4: revision >= 0xC8 && revision <= 0xCF
 or revision >= 0xD8 && revision <= 0xDF
otherwise is PCO FP5

Change-Id: I359f0a3d1bc7d4d49c871cb3fb82797c7b91b259
Signed-off-by: Aaron Liu 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 94740ea..7556716 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -86,6 +86,7 @@ MODULE_FIRMWARE("amdgpu/picasso_me.bin");
 MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
+MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin");

 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
@@ -645,7 +646,20 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device 
*adev)
 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 adev->gfx.ce_feature_version = 
le32_to_cpu(cp_hdr->ucode_feature_version);

-   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
+   /*
+* For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
+* instead of picasso_rlc.bin.
+* Judgment method:
+* PCO AM4: revision >= 0xC8 && revision <= 0xCF
+*  or revision >= 0xD8 && revision <= 0xDF
+* otherwise is PCO FP5
+*/
+   if (!strcmp(chip_name, "picasso") &&
+   (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 
0xCF)) ||
+   ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 
0xDF
+   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", 
chip_name);
+   else
+   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", 
chip_name);
 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 if (err)
 goto out;
--
2.7.4

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Re: [PATCH] drm/amd/powerplay: rv dal-pplib interface refactor powerplay part

[Deucher, Alexander]

Looks reasonable to me.

Acked-by: Alex Deucher 


From: Wu, Hersen
Sent: Wednesday, December 5, 2018 1:03:57 PM
To: amd-gfx@lists.freedesktop.org; Zhu, Rex; Deucher, Alexander
Subject: RE: [PATCH] drm/amd/powerplay: rv dal-pplib interface refactor 
powerplay part

Hello, Alex, Rex,

Would you please help review the change?

Thanks,
Hersen





[WHY] clarify dal input parameters to pplib interface, remove un-used 
parameters. dal knows exactly which parameters needed and their effects at 
pplib and smu sides.

current dal sequence for dcn1_update_clock to pplib:

1.smu10_display_clock_voltage_request for dcefclk 
2.smu10_display_clock_voltage_request for fclk 
3.phm_store_dal_configuration_data {
  set_min_deep_sleep_dcfclk
  set_active_display_count
  store_cc6_data --- this data never be referenced

new sequence will be:

1. set_display_count  --- need add new pplib interface 2. 
set_min_deep_sleep_dcfclk -- new pplib interface 3. set_hard_min_dcfclk_by_freq 
4. set_hard_min_fclk_by_freq

after this code refactor, smu10_display_clock_voltage_request,
phm_store_dal_configuration_data will not be needed for rv.

[HOW] step 1: add new functions at pplib interface
  step 2: add new functions at amdgpu dm and dc

Signed-off-by: hersen wu 
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h |  4 ++
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 76 ++
 .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  | 45 -  
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  | 36 +-
 .../gpu/drm/amd/powerplay/inc/hardwaremanager.h|  3 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  4 +-
 6 files changed, 162 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 980e696..1479ea1 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -276,6 +276,10 @@ struct amd_pm_funcs {
 struct amd_pp_simple_clock_info *clocks);
 int (*notify_smu_enable_pwe)(void *handle);
 int (*enable_mgpu_fan_boost)(void *handle);
+   int (*set_active_display_count)(void *handle, uint32_t count);
+   int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
+   int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
+   int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
 };

 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index d6aa1d4..53dde16 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1332,6 +1332,78 @@ static int pp_enable_mgpu_fan_boost(void *handle)
 return 0;
 }

+static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock)
+{
+   struct pp_hwmgr *hwmgr = handle;
+
+   if (!hwmgr || !hwmgr->pm_en)
+   return -EINVAL;
+
+   if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) {
+   pr_info("%s was not implemented.\n", __func__);
+   return -EINVAL;;
+   }
+
+   mutex_lock(&hwmgr->smu_lock);
+   hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
+   mutex_unlock(&hwmgr->smu_lock);
+
+   return 0;
+}
+
+static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t
+clock) {
+   struct pp_hwmgr *hwmgr = handle;
+
+   if (!hwmgr || !hwmgr->pm_en)
+   return -EINVAL;
+
+   if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) {
+   pr_info("%s was not implemented.\n", __func__);
+   return -EINVAL;;
+   }
+
+   mutex_lock(&hwmgr->smu_lock);
+   hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
+   mutex_unlock(&hwmgr->smu_lock);
+
+   return 0;
+}
+
+static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock) {
+   struct pp_hwmgr *hwmgr = handle;
+
+   if (!hwmgr || !hwmgr->pm_en)
+   return -EINVAL;
+
+   if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) {
+   pr_info("%s was not implemented.\n", __func__);
+   return -EINVAL;;
+   }
+
+   mutex_lock(&hwmgr->smu_lock);
+   hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
+   mutex_unlock(&hwmgr->smu_lock);
+
+   return 0;
+}
+
+static int pp_set_active_display_count(void *handle, uint32_t count) {
+   struct pp_hwmgr *hwmgr = handle;
+   int ret = 0;
+
+   if (!hwmgr || !hwmgr->pm_en)
+   return -EINVAL;
+
+   mutex_lock(&hwmgr->smu_lock);
+   ret = phm_set_active_display_count(hwmgr, count);
+   mutex_unlock(&hwmgr->smu_lock);
+
+   return ret;
+}
+
 static const struct amd_p

Re: [PATCH 3/3] drm/amdgpu/psp: Destroy psp ring when doing gpu reset

[Deucher, Alexander]

Series is:

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Xiangliang 
Yu 
Sent: Wednesday, December 5, 2018 1:46:31 AM
To: amd-gfx@lists.freedesktop.org
Cc: Min, Frank; Yu, Xiangliang
Subject: [PATCH 3/3] drm/amdgpu/psp: Destroy psp ring when doing gpu reset

PSP ring need to be destroy before starting reinit for vf.
This patche move it from hypervisor driver into guest.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Frank Min 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 3142f84..6759d89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -548,8 +548,10 @@ static int psp_load_fw(struct amdgpu_device *adev)
 int ret;
 struct psp_context *psp = &adev->psp;

-   if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0)
+   if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
+   psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 goto skip_memalloc;
+   }

 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 if (!psp->cmd)
--
2.7.4

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Re: [PATCH] drm/amdgpu: Update XGMI node print

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Andrey 
Grodzovsky 
Sent: Monday, December 3, 2018 3:03:41 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Grodzovsky, Andrey
Subject: [PATCH] drm/amdgpu: Update XGMI node print

amdgpu_xgmi_update_topology is called both on device registration
and reset. Fix misleading print since the device is added only once to
the hive on registration and not on reset.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 1b15ff3..0b263a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -78,7 +78,7 @@ int amdgpu_xgmi_update_topology(struct amdgpu_hive_info 
*hive, struct amdgpu_dev
 adev->gmc.xgmi.node_id,
 adev->gmc.xgmi.hive_id, ret);
 else
-   dev_info(adev->dev, "XGMI: Add node %d to hive 0x%llx.\n",
+   dev_info(adev->dev, "XGMI: Set topology for node %d, hive 
0x%llx.\n",
  adev->gmc.xgmi.physical_node_id,
  adev->gmc.xgmi.hive_id);

--
2.7.4

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Re: [PATCH v3 3/3] drm/amdgpu: Implement concurrent asic reset for XGMI.

[Deucher, Alexander]

Patches 1, 2:

Reviewed-by: Alex Deucher 


Patch 3:

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Andrey 
Grodzovsky 
Sent: Friday, November 30, 2018 4:41:10 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Wang, Ken; 
ckoenig.leichtzumer...@gmail.com; Xu, Feifei
Cc: Grodzovsky, Andrey
Subject: [PATCH v3 3/3] drm/amdgpu: Implement concurrent asic reset for XGMI.

Use per hive wq to concurrently send reset commands to all nodes
in the hive.

v2:
Switch to system_highpri_wq after dropping dedicated queue.
Fix non XGMI code path KASAN error.
Stop  the hive reset for each node loop if there
is a reset failure on any of the nodes.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++
 2 files changed, 41 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c8ad6bf..6fc023b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -910,7 +910,9 @@ struct amdgpu_device {
 boolin_gpu_reset;
 struct mutex  lock_reset;
 struct amdgpu_doorbell_index doorbell_index;
+
 int asic_reset_res;
+   struct work_struct  xgmi_reset_work;
 };

 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index bfd286c..9fd9f63 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2356,6 +2356,19 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device 
*adev)
 return amdgpu_device_asic_has_dc_support(adev->asic_type);
 }

+
+static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
+{
+   struct amdgpu_device *adev =
+   container_of(__work, struct amdgpu_device, xgmi_reset_work);
+
+   adev->asic_reset_res =  amdgpu_asic_reset(adev);
+   if (adev->asic_reset_res)
+   DRM_WARN("ASIC reset failed with err r, %d for drm dev, %s",
+adev->asic_reset_res, adev->ddev->unique);
+}
+
+
 /**
  * amdgpu_device_init - initialize the driver
  *
@@ -2454,6 +2467,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
   amdgpu_device_delay_enable_gfx_off);

+   INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
+
 adev->gfx.gfx_off_req_count = 1;
 adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : 
false;

@@ -3331,10 +3346,31 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info 
*hive,
  */
 if (need_full_reset) {
 list_for_each_entry(tmp_adev, device_list_handle, 
gmc.xgmi.head) {
-   r = amdgpu_asic_reset(tmp_adev);
-   if (r)
-   DRM_WARN("ASIC reset failed with err r, %d for 
drm dev, %s",
+   /* For XGMI run all resets in parallel to speed up the 
process */
+   if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
+   if (!queue_work(system_highpri_wq, 
&tmp_adev->xgmi_reset_work))
+   r = -EALREADY;
+   } else
+   r = amdgpu_asic_reset(tmp_adev);
+
+   if (r) {
+   DRM_ERROR("ASIC reset failed with err r, %d for 
drm dev, %s",
  r, tmp_adev->ddev->unique);
+   break;
+   }
+   }
+
+   /* For XGMI wait for all PSP resets to complete before proceed 
*/
+   if (!r) {
+   list_for_each_entry(tmp_adev, device_list_handle,
+   gmc.xgmi.head) {
+   if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
+   flush_work(&tmp_adev->xgmi_reset_work);
+   r = tmp_adev->asic_reset_res;
+   if (r)
+   break;
+   }
+   }
 }
 }

@@ -3521,8 +3557,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 if (tmp_adev == adev)
 continue;

-   dev_info(tmp_adev->dev, "GPU reset begin for drm dev %s!\n", 
adev->ddev->unique);
-
 amdgpu_device_lock_adev(tmp_adev);

Re: [PATCH] drm/amdgpu: Fix num_doorbell calculation issue

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Oak Zeng 

Sent: Friday, November 30, 2018 10:39:21 AM
To: amd-gfx@lists.freedesktop.org
Cc: Yang, Philip; Zeng, Oak; Yin, Tianci (Rico)
Subject: [PATCH] drm/amdgpu: Fix num_doorbell calculation issue

When paging queue is enabled, it use the second page of doorbell.
The AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
kernel doorbells are in the first page. So with paging queue enabled,
the total kernel doorbell range should be original num_doorbell plus
one page (0x400 in dword), not *2.

Change-Id: I62023bb91da33ca5532b22b263771b587b796d59
Signed-off-by: Oak Zeng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8eaa40e..c75badf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -539,10 +539,13 @@ static int amdgpu_device_doorbell_init(struct 
amdgpu_device *adev)
 return -EINVAL;

 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
-* paging queue doorbell use the second page
+* paging queue doorbell use the second page. The
+* AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
+* doorbells are in the first page. So with paging queue enabled,
+* the max num_doorbells should + 1 page (0x400 in dword)
  */
 if (adev->asic_type >= CHIP_VEGA10)
-   adev->doorbell.num_doorbells *= 2;
+   adev->doorbell.num_doorbells += 0x400;

 adev->doorbell.ptr = ioremap(adev->doorbell.base,
  adev->doorbell.num_doorbells *
--
2.7.4

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Re: [PATCH] drm/amd/display: Fix NULL ptr deref for commit_planes_to_stream

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Nicholas 
Kazlauskas 
Sent: Friday, November 30, 2018 10:09:28 AM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Sun peng (Leo); Wentland, Harry; Kazlauskas, Nicholas
Subject: [PATCH] drm/amd/display: Fix NULL ptr deref for commit_planes_to_stream

[Why]
With scaling, underscan and abm changes we can end up calling
commit_planes_to_stream in commit_tail. This call uses dm_state->context
which can be NULL if the commit was a fast update.

[How]
Use dc_state instead since that can't be NULL unless the system ran
out of memory.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108912
Fixes: e64abff2f133 ("drm/amd/display: Use private obj helpers for 
dm_atomic_state")

Cc: Leo Li 
Cc: Harry Wentland 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 76b1aebdca0c..8ecd78657d43 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5011,7 +5011,7 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
 status->plane_count,
 dm_new_crtc_state,
 to_dm_crtc_state(old_crtc_state),
-   dm_state->context))
+   dc_state))
 dm_error("%s: Failed to update stream scaling!\n", 
__func__);
 }

--
2.17.1

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Re: [PATCH] drm/amdgpu: remove amdgpu_bo_backup_to_shadow

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Christian 
König 
Sent: Friday, November 30, 2018 7:45:17 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: remove amdgpu_bo_backup_to_shadow

It is unused.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 47 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  5 ---
 2 files changed, 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index cf768acb51dc..cc50cb65c212 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -607,53 +607,6 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 return r;
 }

-/**
- * amdgpu_bo_backup_to_shadow - Backs up an &amdgpu_bo buffer object
- * @adev: amdgpu device object
- * @ring: amdgpu_ring for the engine handling the buffer operations
- * @bo: &amdgpu_bo buffer to be backed up
- * @resv: reservation object with embedded fence
- * @fence: dma_fence associated with the operation
- * @direct: whether to submit the job directly
- *
- * Copies an &amdgpu_bo buffer object to its shadow object.
- * Not used for now.
- *
- * Returns:
- * 0 for success or a negative error code on failure.
- */
-int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
-  struct amdgpu_ring *ring,
-  struct amdgpu_bo *bo,
-  struct reservation_object *resv,
-  struct dma_fence **fence,
-  bool direct)
-
-{
-   struct amdgpu_bo *shadow = bo->shadow;
-   uint64_t bo_addr, shadow_addr;
-   int r;
-
-   if (!shadow)
-   return -EINVAL;
-
-   bo_addr = amdgpu_bo_gpu_offset(bo);
-   shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
-
-   r = reservation_object_reserve_shared(bo->tbo.resv, 1);
-   if (r)
-   goto err;
-
-   r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
-  amdgpu_bo_size(bo), resv, fence,
-  direct, false);
-   if (!r)
-   amdgpu_bo_fence(bo, *fence, true);
-
-err:
-   return r;
-}
-
 /**
  * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
  * @bo: pointer to the buffer object
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 7d3312d0da11..9291c2f837e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -267,11 +267,6 @@ int amdgpu_bo_fault_reserve_notify(struct 
ttm_buffer_object *bo);
 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
  bool shared);
 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
-int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
-  struct amdgpu_ring *ring,
-  struct amdgpu_bo *bo,
-  struct reservation_object *resv,
-  struct dma_fence **fence, bool direct);
 int amdgpu_bo_validate(struct amdgpu_bo *bo);
 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
  struct dma_fence **fence);
--
2.17.1

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Re: [PATCH 09/16] drm/amd/display: fbc state could not reach while enable fbc

[Deucher, Alexander]

Do you think this will fix this bug?

https://bugs.freedesktop.org/show_bug.cgi?id=108577

If so, we can re-enable fbc.


Alex


From: amd-gfx  on behalf of 
sunpeng...@amd.com 
Sent: Thursday, November 29, 2018 10:52:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wu, Hersen
Subject: [PATCH 09/16] drm/amd/display: fbc state could not reach while enable 
fbc

From: hersen wu 

   [WHY] fbc is within the data path from memory to dce. while
   re-configure mc dmif, fbc should be enabled. otherwise, fbc
   may not be enabled properly.

   [HOW] before re-configure mc dmif, disable fbc, only after
   dmif re-configuration fully done, enable fbc again.

Signed-off-by: hersen wu 
Reviewed-by: Roman Li 
Acked-by: Leo Li 
---
 .../drm/amd/display/dc/dce110/dce110_compressor.c  | 91 --
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 57 --
 drivers/gpu/drm/amd/display/dc/inc/compressor.h|  1 +
 3 files changed, 66 insertions(+), 83 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 1f7f250..52d50e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -64,65 +64,37 @@ static const struct dce110_compressor_reg_offsets 
reg_offsets[] = {

 static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;

-enum fbc_idle_force {
-   /* Bit 0 - Display registers updated */
-   FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x0001,
-
-   /* Bit 2 - FBC_GRPH_COMP_EN register updated */
-   FBC_IDLE_FORCE_GRPH_COMP_EN = 0x0002,
-   /* Bit 3 - FBC_SRC_SEL register updated */
-   FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x0004,
-   /* Bit 4 - FBC_MIN_COMPRESSION register updated */
-   FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x0008,
-   /* Bit 5 - FBC_ALPHA_COMP_EN register updated */
-   FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x0010,
-   /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
-   FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x0020,
-   /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
-   FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x0040,
-
-   /* Bit 24 - Memory write to region 0 defined by MC registers. */
-   FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x0100,
-   /* Bit 25 - Memory write to region 1 defined by MC registers */
-   FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x0200,
-   /* Bit 26 - Memory write to region 2 defined by MC registers */
-   FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x0400,
-   /* Bit 27 - Memory write to region 3 defined by MC registers. */
-   FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x0800,
-
-   /* Bit 28 - Memory write from any client other than MCIF */
-   FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x1000,
-   /* Bit 29 - CG statics screen signal is inactive */
-   FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x2000,
-};
-
-
 static uint32_t align_to_chunks_number_per_line(uint32_t pixels)
 {
 return 256 * ((pixels + 255) / 256);
 }

-static void reset_lb_on_vblank(struct dc_context *ctx)
+static void reset_lb_on_vblank(struct compressor *compressor, uint32_t 
crtc_inst)
 {
-   uint32_t value, frame_count;
+   uint32_t value;
+   uint32_t frame_count;
+   uint32_t status_pos;
 uint32_t retry = 0;
-   uint32_t status_pos =
-   dm_read_reg(ctx, mmCRTC_STATUS_POSITION);
+   struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
+
+   cp110->offsets = reg_offsets[crtc_inst];
+
+   status_pos = dm_read_reg(compressor->ctx, 
DCP_REG(mmCRTC_STATUS_POSITION));


 /* Only if CRTC is enabled and counter is moving we wait for one 
frame. */
-   if (status_pos != dm_read_reg(ctx, mmCRTC_STATUS_POSITION)) {
+   if (status_pos != dm_read_reg(compressor->ctx, 
DCP_REG(mmCRTC_STATUS_POSITION))) {
 /* Resetting LB on VBlank */
-   value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL);
+   value = dm_read_reg(compressor->ctx, 
DCP_REG(mmLB_SYNC_RESET_SEL));
 set_reg_field_value(value, 3, LB_SYNC_RESET_SEL, 
LB_SYNC_RESET_SEL);
 set_reg_field_value(value, 1, LB_SYNC_RESET_SEL, 
LB_SYNC_RESET_SEL2);
-   dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value);
+   dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), 
value);

-   frame_count = dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT);
+   frame_count = dm_read_reg(compressor->ctx, 
DCP_REG(mmCRTC_STATUS_FRAME_COUNT));


 for (retry = 1; retry > 0; retry--) {
-   if (frame_count != dm_read_reg(ctx, 
mmCRTC_STATUS_FRAME_COUNT))
+   if (frame_count != dm_read_reg(compressor->ctx, 
DCP_REG(

Re: [PATCH] drm/ttm: fix LRU handling in ttm_buffer_object_transfer

[Deucher, Alexander]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Christian 
König 
Sent: Thursday, November 29, 2018 11:20:12 AM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: mar...@gmail.com
Subject: [PATCH] drm/ttm: fix LRU handling in ttm_buffer_object_transfer

We need to set the NO_EVICT flag on the ghost object or otherwise we are
adding it to the LRU.

When it is added to the LRU we can run into a race between destroying
and evicting it again.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/ttm/ttm_bo_util.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c 
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index ba80150d1052..895d77d799e4 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -492,8 +492,10 @@ static int ttm_buffer_object_transfer(struct 
ttm_buffer_object *bo,
 if (!fbo)
 return -ENOMEM;

-   ttm_bo_get(bo);
 fbo->base = *bo;
+   fbo->base.mem.placement |= TTM_PL_FLAG_NO_EVICT;
+
+   ttm_bo_get(bo);
 fbo->bo = bo;

 /**
--
2.14.1

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