RE: [PATCH 2/3] drm/amdgpu: sdma support for sriov cpx mode
[AMD Official Use Only - General]
> -Original Message-
> From: Kuehling, Felix
> Sent: Monday, March 4, 2024 6:47 PM
> To: Dhume, Samir ; amd-gfx@lists.freedesktop.org
> Cc: Lazar, Lijo ; Wan, Gavin ;
> Liu, Leo ; Deucher, Alexander
>
> Subject: Re: [PATCH 2/3] drm/amdgpu: sdma support for sriov cpx mode
>
>
> On 2024-03-04 10:19, Samir Dhume wrote:
> > Signed-off-by: Samir Dhume
>
> Please add a meaningful commit description to all the patches in the series.
> See one more comment below.
Right!
>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 34
> +++-
> > 1 file changed, 27 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > index fec5a3d1c4bc..f666ececbe7d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > @@ -82,17 +82,37 @@ static unsigned sdma_v4_4_2_seq_to_irq_id(int
> seq_num)
> > }
> > }
> >
> > -static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id)
> > +static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev,
> unsigned client_id)
> > {
> > +
> > + struct amdgpu_xcp_mgr *xcp_mgr = adev->xcp_mgr;
> > + bool sriov_cpx_odd = false;
> > + int mode;
> > +
> > + if (amdgpu_sriov_vf(adev)) {
> > + mode = xcp_mgr->funcs->query_partition_mode(xcp_mgr);
>
> This queries an MMIO register for the current mode. Is that really
> necessary to do in the interrupt handler? Could we use the partition
> mode stored in xcp_mgr->mode instead?
The design appears to be that even when the host sets the mode to DPX/QPX/CPX,
each guest sets itself to be in the SPX mode and xcp_mgr->mode is set to SPX.
But I can use a new field in xcp_mgr to reflect the system mode set by the host
and remove the MMIO access from the interrupt handler.
Thanks,
samir
>
> Regards,
>Felix
>
>
> > +
> > + if (mode == AMDGPU_CPX_PARTITION_MODE) {
> > + if (adev->gfx.funcs->get_xcc_id(adev, 0) & 0x1)
> > + sriov_cpx_odd = true;
> > + }
> > + }
> > +
> > switch (client_id) {
> > case SOC15_IH_CLIENTID_SDMA0:
> > return 0;
> > case SOC15_IH_CLIENTID_SDMA1:
> > return 1;
> > case SOC15_IH_CLIENTID_SDMA2:
> > - return 2;
> > + if (sriov_cpx_odd)
> > + return 0;
> > + else
> > + return 2;
> > case SOC15_IH_CLIENTID_SDMA3:
> > - return 3;
> > + if (sriov_cpx_odd)
> > + return 1;
> > + else
> > + return 3;
> > default:
> > return -EINVAL;
> > }
> > @@ -1541,7 +1561,7 @@ static int sdma_v4_4_2_process_trap_irq(struct
> amdgpu_device *adev,
> > uint32_t instance, i;
> >
> > DRM_DEBUG("IH: SDMA trap\n");
> > - instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
> > + instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
> >
> > /* Client id gives the SDMA instance in AID. To know the exact SDMA
> > * instance, interrupt entry gives the node id which corresponds to the
> AID instance.
> > @@ -1584,7 +1604,7 @@ static int
> sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
> > if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))
> > goto out;
> >
> > - instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
> > + instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
> > if (instance < 0)
> > goto out;
> >
> > @@ -1603,7 +1623,7 @@ static int
> sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
> >
> > DRM_ERROR("Illegal instruction in SDMA command stream\n");
> >
> > - instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
> > + instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
> > if (instance < 0)
> > return 0;
> >
> > @@ -1647,7 +1667,7 @@ static int sdma_v4_4_2_print_iv_entry(struct
> amdgpu_device *adev,
> > struct amdgpu_task_info task_info;
> > u64 addr;
> >
> > - instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
> > + instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
> > if (instance < 0 || instance >= adev->sdma.num_instances) {
> > dev_err(adev->dev, "sdma instance invalid %d\n", instance);
> > return -EINVAL;
RE: [PATCH 4/4] drm/amdgpu: Do not program VM_L2_CNTL under SRIOV
[AMD Official Use Only - General]
Reviewed-by: Samir Dhume
-Original Message-
From: amd-gfx On Behalf Of Victor Lu
Sent: Tuesday, January 2, 2024 12:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chander, Vignesh ; Lu, Victor Cheng Chi (Victor)
Subject: [PATCH 4/4] drm/amdgpu: Do not program VM_L2_CNTL under SRIOV
VM_L2_CNTL* should not be programmed on driver unload under SRIOV.
These regs are skipped during SRIOV driver init.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
index 55423ff1bb49..20e800bc0b68 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
@@ -454,10 +454,12 @@ static void gfxhub_v1_2_xcc_gart_disable(struct
amdgpu_device *adev,
WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL,
tmp);
/* Setup L2 cache */
- tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
- WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);
- WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);
+ if (!amdgpu_sriov_vf(adev)) {
+ tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE,
0);
+ WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);
+ WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);
+ }
}
}
--
2.34.1
RE: [PATCH 2/4] drm/amdgpu: Do not program SQ_TIMEOUT_CONFIG in SRIOV
[AMD Official Use Only - General] Reviewed-by: Samir Dhume -Original Message- From: amd-gfx On Behalf Of Victor Lu Sent: Tuesday, January 2, 2024 12:30 PM To: amd-gfx@lists.freedesktop.org Cc: Chander, Vignesh ; Lu, Victor Cheng Chi (Victor) Subject: [PATCH 2/4] drm/amdgpu: Do not program SQ_TIMEOUT_CONFIG in SRIOV VF should not program this register. Signed-off-by: Victor Lu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 00b21ece081f..30cc155f20d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3888,6 +3888,9 @@ static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, uint32_t i; uint32_t data; + if (amdgpu_sriov_vf(adev)) + return; + data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); -- 2.34.1
RE: [PATCH v2] drm/amdgpu: Do not program VF copy regs in mmhub v1.8 under SRIOV (v2)
[AMD Official Use Only - General]
Reviewed-by: Samir Dhume
-Original Message-
From: Lu, Victor Cheng Chi (Victor)
Sent: Friday, November 10, 2023 5:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Dhume, Samir ; Lu, Victor Cheng Chi (Victor)
Subject: [PATCH v2] drm/amdgpu: Do not program VF copy regs in mmhub v1.8 under
SRIOV (v2)
MC_VM_AGP_* registers should not be programmed by guest driver.
v2: move early return outside of loop
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
index ea142611be1c..9b0146732e13 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
@@ -130,6 +130,9 @@ static void mmhub_v1_8_init_system_aperture_regs(struct
amdgpu_device *adev)
uint64_t value;
int i;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
inst_mask = adev->aid_mask;
for_each_inst(i, inst_mask) {
/* Program the AGP BAR */
@@ -139,9 +142,6 @@ static void mmhub_v1_8_init_system_aperture_regs(struct
amdgpu_device *adev)
WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP,
adev->gmc.agp_end >> 24);
- if (amdgpu_sriov_vf(adev))
- return;
-
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
--
2.34.1
RE: [PATCH] drm/amdgpu: Do not program VF copy regs in mmhub v1.8 under SRIOV
[AMD Official Use Only - General]
It makes more sense to put the check for sriov in the beginning of the function
rather than inside the for-loop.
Thanks,
Samir
-Original Message-
From: amd-gfx On Behalf Of Victor Lu
Sent: Tuesday, November 7, 2023 2:31 PM
To: amd-gfx@lists.freedesktop.org
Cc: Dhume, Samir ; Lu, Victor Cheng Chi (Victor)
Subject: [PATCH] drm/amdgpu: Do not program VF copy regs in mmhub v1.8 under
SRIOV
MC_VM_AGP_* registers should not be programmed by guest driver.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
index ea142611be1c..125917c3cba1 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
@@ -132,6 +132,9 @@ static void mmhub_v1_8_init_system_aperture_regs(struct
amdgpu_device *adev)
inst_mask = adev->aid_mask;
for_each_inst(i, inst_mask) {
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Program the AGP BAR */
WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BASE, 0);
WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT, @@ -139,9 +142,6 @@
static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)
WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP,
adev->gmc.agp_end >> 24);
- if (amdgpu_sriov_vf(adev))
- return;
-
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
--
2.34.1
RE: [PATCH v2] drm/amdgpu: Do not program PF-only regs in hdp_v4_0.c under SRIOV (v2)
[AMD Official Use Only - General]
Reviewed-by: Samir Dhume
-Original Message-
From: Lu, Victor Cheng Chi (Victor)
Sent: Wednesday, November 8, 2023 10:25 AM
To: amd-gfx@lists.freedesktop.org
Cc: Dhume, Samir ; Lu, Victor Cheng Chi (Victor)
Subject: [PATCH v2] drm/amdgpu: Do not program PF-only regs in hdp_v4_0.c under
SRIOV (v2)
The following regs can only be programmed by the PF:
HDP_MISC_CNTL
HDP_NONSURFACE_BASE
HDP_NONSURFACE_BASE_HI
v2: update commit message
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index 3f3a6445c006..bf3bdf67abb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -145,6 +145,11 @@ static void hdp_v4_0_init_registers(struct amdgpu_device
*adev)
break;
}
+ /* Do not program registers if VF */
+ if (amdgpu_sriov_vf(adev)) {
+ return;
+ }
+
WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0))
--
2.34.1
RE: [PATCH] drm/amdgpu: Skip PCTL0_MMHUB_DEEPSLEEP_IB write in jpegv4.0.3 under SRIOV
[AMD Official Use Only - General]
Reviewed-by: Samir Dhume
-Original Message-
From: Lu, Victor Cheng Chi (Victor)
Sent: Tuesday, November 7, 2023 2:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Dhume, Samir ; Lu, Victor Cheng Chi (Victor)
Subject: [PATCH] drm/amdgpu: Skip PCTL0_MMHUB_DEEPSLEEP_IB write in jpegv4.0.3
under SRIOV
PCTL0_MMHUB_DEEPSLEEP_IB is blocked for VF access
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 355d25fd6169..165448bed6c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -652,9 +652,11 @@ static void jpeg_v4_0_3_dec_ring_set_wptr(struct
amdgpu_ring *ring)
*/
static void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) {
- amdgpu_ring_write(ring,
PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
- 0, 0, PACKETJ_TYPE0));
- amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
+ if (!amdgpu_sriov_vf(ring->adev)) {
+ amdgpu_ring_write(ring,
PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+ 0, 0, PACKETJ_TYPE0));
+ amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
+ }
amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
0, 0, PACKETJ_TYPE0));
@@ -670,9 +672,11 @@ static void jpeg_v4_0_3_dec_ring_insert_start(struct
amdgpu_ring *ring)
*/
static void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) {
- amdgpu_ring_write(ring,
PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
- 0, 0, PACKETJ_TYPE0));
- amdgpu_ring_write(ring, 0x62a04);
+ if (!amdgpu_sriov_vf(ring->adev)) {
+ amdgpu_ring_write(ring,
PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+ 0, 0, PACKETJ_TYPE0));
+ amdgpu_ring_write(ring, 0x62a04);
+ }
amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
0, 0, PACKETJ_TYPE0));
--
2.34.1
RE: [PATCH] drm/amdgpu: Do not program HDP_MISC_CNTL in hdp_v4_0.c under SRIOV
[AMD Official Use Only - General]
Do you also need to skip programming of mmHDP_NONSURFACE_BASE and
mmHDP_NONSURFACE_BASE_HI?
-Original Message-
From: Lu, Victor Cheng Chi (Victor)
Sent: Tuesday, November 7, 2023 2:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Dhume, Samir ; Lu, Victor Cheng Chi (Victor)
Subject: [PATCH] drm/amdgpu: Do not program HDP_MISC_CNTL in hdp_v4_0.c under
SRIOV
This register is blocked for VF access.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index 3f3a6445c006..bf3bdf67abb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -145,6 +145,11 @@ static void hdp_v4_0_init_registers(struct amdgpu_device
*adev)
break;
}
+ /* Do not program registers if VF */
+ if (amdgpu_sriov_vf(adev)) {
+ return;
+ }
+
WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0))
--
2.34.1
RE: [PATCH v3 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
[AMD Official Use Only - General]
Thanks Leo. I'll restore the check for sriov before calling
amdgpu_virt_alloc_mm_table(). That will make it consistent with other vcn ip
versions. I'll retain the check for sriov inside amdgpu_virt_alloc_mm_table()
as well, as a conservative check.
Thanks,
Samir
-Original Message-
From: Liu, Leo
Sent: Tuesday, August 8, 2023 8:29 AM
To: Dhume, Samir ; amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang ; Chen, Guchun ;
Wan, Gavin ; Lazar, Lijo ; Min, Frank
; Zhang, Hawking
Subject: Re: [PATCH v3 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
On 2023-07-28 15:15, Samir Dhume wrote:
> initialization table handshake with mmsch
>
> Signed-off-by: Samir Dhume
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 257 +---
> 1 file changed, 233 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 411c1d802823..b978265b2d77 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -31,6 +31,7 @@
> #include "soc15d.h"
> #include "soc15_hw_ip.h"
> #include "vcn_v2_0.h"
> +#include "mmsch_v4_0_3.h"
>
> #include "vcn/vcn_4_0_3_offset.h"
> #include "vcn/vcn_4_0_3_sh_mask.h"
> @@ -44,6 +45,7 @@
> #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
> #define VCN1_VID_SOC_ADDRESS_3_00x48300
>
> +static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
> static int vcn_v4_0_3_set_powergating_state(void *handle, @@ -130,6
> +132,10 @@ static int vcn_v4_0_3_sw_init(void *handle)
> amdgpu_vcn_fwlog_init(>vcn.inst[i]);
> }
>
> + r = amdgpu_virt_alloc_mm_table(adev);
Since this function is not for bare-metal, please move amdgpu_sriov_vf() check
from inside of the function to here, to avoid confusion.
> + if (r)
> + return r;
> +
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
>
> @@ -167,6 +173,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
> drm_dev_exit(idx);
> }
>
> + amdgpu_virt_free_mm_table(adev);
Same as above.
Regards,
Leo
> +
> r = amdgpu_vcn_suspend(adev);
> if (r)
> return r;
> @@ -189,33 +197,47 @@ static int vcn_v4_0_3_hw_init(void *handle)
> struct amdgpu_ring *ring;
> int i, r, vcn_inst;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - vcn_inst = GET_INST(VCN, i);
> - ring = >vcn.inst[i].ring_enc[0];
> + if (amdgpu_sriov_vf(adev)) {
> + r = vcn_v4_0_3_start_sriov(adev);
> + if (r)
> + goto done;
>
> - if (ring->use_doorbell) {
> - adev->nbio.funcs->vcn_doorbell_range(
> - adev, ring->use_doorbell,
> - (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
> - 9 * vcn_inst,
> - adev->vcn.inst[i].aid_id);
> -
> - WREG32_SOC15(
> - VCN, GET_INST(VCN, ring->me),
> - regVCN_RB1_DB_CTRL,
> - ring->doorbell_index
> - <<
> VCN_RB1_DB_CTRL__OFFSET__SHIFT |
> - VCN_RB1_DB_CTRL__EN_MASK);
> -
> - /* Read DB_CTRL to flush the write DB_CTRL command. */
> - RREG32_SOC15(
> - VCN, GET_INST(VCN, ring->me),
> - regVCN_RB1_DB_CTRL);
> + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + ring = >vcn.inst[i].ring_enc[0];
> + ring->wptr = 0;
> + ring->wptr_old = 0;
> + vcn_v4_0_3_unified_ring_set_wptr(ring);
> + ring->sched.ready = true;
> }
> + } else {
> + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + vcn_inst = GET_INST(VCN, i);
> + ring = >vcn.inst[i].ring_enc[0];
> +
> + if (ring->use_doorbell) {
> + adev->nbio.funcs->vcn_doorbell_range(
> +
RE: [PATCH 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
[Public]
Fair point. I'll follow up with another patch.
Thanks,
Samir
-Original Message-
From: Chen, Guchun
Sent: Tuesday, July 18, 2023 1:54 AM
To: Dhume, Samir ; amd-gfx@lists.freedesktop.org
Cc: Dhume, Samir
Subject: RE: [PATCH 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Samir Dhume
> Sent: Monday, July 17, 2023 11:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Dhume, Samir
> Subject: [PATCH 3/7] drm/amdgpu/vcn: sriov support for vcn_v4_0_3
>
> initialization table handshake with mmsch
>
> Signed-off-by: Samir Dhume
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 264
> +---
> 1 file changed, 240 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 411c1d802823..ac405dfcfaf1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -31,6 +31,7 @@
> #include "soc15d.h"
> #include "soc15_hw_ip.h"
> #include "vcn_v2_0.h"
> +#include "mmsch_v4_0_3.h"
>
> #include "vcn/vcn_4_0_3_offset.h"
> #include "vcn/vcn_4_0_3_sh_mask.h"
> @@ -44,6 +45,7 @@
> #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
> #define VCN1_VID_SOC_ADDRESS_3_0 0x48300
>
> +static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device
> *adev); static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device
> *adev); static int vcn_v4_0_3_set_powergating_state(void *handle, @@
> -130,6 +132,12 @@ static int vcn_v4_0_3_sw_init(void *handle)
> amdgpu_vcn_fwlog_init(>vcn.inst[i]);
> }
>
> + if (amdgpu_sriov_vf(adev)) {
> + r = amdgpu_virt_alloc_mm_table(adev);
amdgpu_virt_alloc_mm_table has an early check of amdgpu_sriov_vf(adev), so from
coding style's perspective, I think you can drop this superfluous check here
and directly call amdgpu_virt_alloc_mm_table.
> + if (r)
> + return r;
> + }
> +
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
>
> @@ -167,6 +175,9 @@ static int vcn_v4_0_3_sw_fini(void *handle)
> drm_dev_exit(idx);
> }
>
> + if (amdgpu_sriov_vf(adev))
> + amdgpu_virt_free_mm_table(adev);
Same as above.
Regards,
Guchun
> r = amdgpu_vcn_suspend(adev);
> if (r)
> return r;
> @@ -189,33 +200,50 @@ static int vcn_v4_0_3_hw_init(void *handle)
> struct amdgpu_ring *ring;
> int i, r, vcn_inst;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> - vcn_inst = GET_INST(VCN, i);
> - ring = >vcn.inst[i].ring_enc[0];
> + if (amdgpu_sriov_vf(adev)) {
> + r = vcn_v4_0_3_start_sriov(adev);
> + if (r)
> + goto done;
>
> - if (ring->use_doorbell) {
> - adev->nbio.funcs->vcn_doorbell_range(
> - adev, ring->use_doorbell,
> - (adev->doorbell_index.vcn.vcn_ring0_1 << 1)
> +
> - 9 * vcn_inst,
> - adev->vcn.inst[i].aid_id);
> -
> - WREG32_SOC15(
> - VCN, GET_INST(VCN, ring->me),
> - regVCN_RB1_DB_CTRL,
> - ring->doorbell_index
> - <<
> VCN_RB1_DB_CTRL__OFFSET__SHIFT |
> - VCN_RB1_DB_CTRL__EN_MASK);
> -
> - /* Read DB_CTRL to flush the write DB_CTRL
> command. */
> - RREG32_SOC15(
> - VCN, GET_INST(VCN, ring->me),
> - regVCN_RB1_DB_CTRL);
> + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + if (adev->vcn.harvest_config & (1 << i))
> + continue;
> +
> + ring = >vcn.inst[i].ring_enc[0];
> + ring->wptr = 0;
> + ring->wptr_old = 0;
> + vcn_v4_0_3_unified_ring_set_wptr(ring);
> + ring->sched.ready = true;
> }
> + } else {
> + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + vcn_inst = GET_INS
drm/amdgpu: Rearm IRQ in Navi10 SR-IOV if IRQ lost
[AMD Official Use Only - Internal Distribution Only]
Ported from Vega10. SDMA stress tests sometimes see IRQ lost.
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 36 ++
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index cf557a428298..e08245a446fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -32,6 +32,7 @@
#include "soc15_common.h"
#include "navi10_ih.h"
+#define MAX_REARM_RETRY 10
static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
@@ -283,6 +284,38 @@ static void navi10_ih_decode_iv(struct amdgpu_device *adev,
ih->rptr += 32;
}
+/**
+ * navi10_ih_irq_rearm - rearm IRQ if lost
+ *
+ * @adev: amdgpu_device pointer
+ *
+ */
+static void navi10_ih_irq_rearm(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
+{
+ uint32_t reg_rptr = 0;
+ uint32_t v = 0;
+ uint32_t i = 0;
+
+ if (ih == >irq.ih)
+ reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
+ else if (ih == >irq.ih1)
+ reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
+ else if (ih == >irq.ih2)
+ reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
+ else
+ return;
+
+ /* Rearm IRQ / re-write doorbell if doorbell write is lost */
+ for (i = 0; i < MAX_REARM_RETRY; i++) {
+ v = RREG32_NO_KIQ(reg_rptr);
+ if ((v < ih->ring_size) && (v != ih->rptr))
+ WDOORBELL32(ih->doorbell_index, ih->rptr);
+ else
+ break;
+ }
+}
+
/**
* navi10_ih_set_rptr - set the IH ring buffer rptr
*
@@ -297,6 +330,9 @@ static void navi10_ih_set_rptr(struct amdgpu_device *adev,
/* XXX check if swapping is necessary on BE */
*ih->rptr_cpu = ih->rptr;
WDOORBELL32(ih->doorbell_index, ih->rptr);
+
+ if (amdgpu_sriov_vf(adev))
+ navi10_ih_irq_rearm(adev, ih);
} else
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); }
--
2.20.1
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