RE: [PATCH 1/2] drm/amdgpu: allow secure submission on VCN4 ring
Hi Leo,
There are two issues here.
This change fixing the Crash while secure playback and we see below error:
2023-07-14T15:51:24.837592Z ERR kernel: [ 129.255823] amdgpu :c2:00.0:
amdgpu: secure submissions not supported on ring
2023-07-14T15:51:24.837601Z ERR kernel: [ 129.255827] [drm:amdgpu_job_run]
*ERROR* Error scheduling IBs (-22)
2023-07-14T15:51:24.837603Z INFO kernel: [ 129.255834] [drm] Skip scheduling
IBs!
The second one : https://patchwork.freedesktop.org/patch/547587/
Fixing the garbage/corruption.
With both patches playback working fine.
Thanks,
Suresh G
-Original Message-
From: Liu, Leo
Sent: Friday, July 14, 2023 7:08 PM
To: Guttula, Suresh ; Deucher, Alexander
; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/amdgpu: allow secure submission on VCN4 ring
On 2023-07-14 05:44, sguttula wrote:
> This patch will enable secure decode playback on VCN4
>
> Signed-off-by: sguttula
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index e8c02ae10163..d199f87febd1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -1804,6 +1804,7 @@ static int vcn_v4_0_ring_patch_cs_in_place(struct
> amdgpu_cs_parser *p,
> static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
> .type = AMDGPU_RING_TYPE_VCN_ENC,
> .align_mask = 0x3f,
> + .secure_submission_supported = true,
We should set it to true with VCN4_0_4 only for now, and check either this
boolean or VCN4_0_4 with your implementation from patch 2
Regards,
Leo
> .nop = VCN_ENC_CMD_NO_OP,
> .get_rptr = vcn_v4_0_unified_ring_get_rptr,
> .get_wptr = vcn_v4_0_unified_ring_get_wptr,
[PATCH 1/3] Revert "drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVD"
From: Shirish S
This reverts commit dbd8299c32f6f413f6cfe322fe0308f3cfc577e8.
Reason for revert:
This patch sends msg PPSMC_MSG_DisableLowMemoryPstate(0x002e)
in wrong of sequence to SMU which is before PPSMC_MSG_UVDPowerON (0x0008).
This leads to SMU failing to service the request as it is
dependent on UVD to be powered ON, since it accesses UVD
registers.
This msg should ideally be sent only when the UVD is about to decode
a 4k video.
Signed-off-by: Shirish S
Signed-off-by: suresh guttula
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index fef111d..53cf787 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1228,17 +1228,14 @@ static int smu8_dpm_force_dpm_level(struct pp_hwmgr
*hwmgr,
static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
- if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
- smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);
+ if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
- }
return 0;
}
static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
{
if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
- smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);
return smum_send_msg_to_smc_with_parameter(
hwmgr,
PPSMC_MSG_UVDPowerON,
--
2.7.4
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[PATCH v3 3/3] drm/amd:Enable/Disable NBPSTATE on On/OFF of UVD
We observe black lines (underflow) on display when playing a
4K video with UVD. On Disabling Low memory P state this issue is
not seen.
In this patch,disabling low memory P state only when video
size >= 4k.
Multiple runs of power measurement shows no impact
Signed-off-by: suresh guttula
---
v2: Enable/disable low memory pstate logic added to
amdgpu_dpm_enable_uvd() instead of parser function
v3: Fix compilation error of struct pp_instance
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 2 ++
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 7235cd0..7431943 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -33,6 +33,8 @@
#include
#include
#include
+#include "hwmgr.h"
+#define WIDTH_4K 3840
static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
@@ -1956,6 +1958,17 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev,
bool enable)
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD,
!enable);
mutex_unlock(>pm.mutex);
}
+ /* enable/disable Low Memory PState for UVD (4k videos) */
+ if (adev->asic_type == CHIP_STONEY &&
+ adev->uvd.decode_image_width >= WIDTH_4K) {
+ struct pp_hwmgr *hwmgr =
+ adev->powerplay.pp_handle;
+ if (hwmgr && hwmgr->hwmgr_func &&
+ hwmgr->hwmgr_func->update_nbdpm_pstate)
+ hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
+ !enable,
+ true);
+ }
}
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 69896f4..4e5d13e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -692,6 +692,8 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device
*adev, uint32_t *msg,
buf_sizes[0x1] = dpb_size;
buf_sizes[0x2] = image_size;
buf_sizes[0x4] = min_ctx_size;
+ /* store image width to adjust nb memory pstate */
+ adev->uvd.decode_image_width = width;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index a3ab1a4..5eb6328 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -65,6 +65,8 @@ struct amdgpu_uvd {
struct drm_sched_entity entity;
struct delayed_work idle_work;
unsignedharvest_config;
+ /* store image width to adjust nb memory state */
+ unsigneddecode_image_width;
};
int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
--
2.7.4
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[PATCH v2 2/3] drm/amd/powerplay:add hwmgr callback to update nbpstate on Carrizo
Add hwmgr callback "update_nbdpm_pstate".This will use to access
"cz_nbdpm_pstate_enable_disable" function to enable/disable low
memory pstate.
Signed-off-by: suresh guttula
---
v2: commit message edited to explain more details
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 1 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h| 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index 53cf787..553a203 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1992,6 +1992,7 @@ static const struct pp_hwmgr_func smu8_hwmgr_funcs = {
.power_state_set = smu8_set_power_state_tasks,
.dynamic_state_management_disable = smu8_disable_dpm_tasks,
.notify_cac_buffer_info = smu8_notify_cac_buffer_info,
+ .update_nbdpm_pstate = smu8_nbdpm_pstate_enable_disable,
.get_thermal_temperature_range = smu8_get_thermal_temperature_range,
};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 07d180ce..fb0f96f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -317,6 +317,9 @@ struct pp_hwmgr_func {
uint32_t mc_addr_low,
uint32_t mc_addr_hi,
uint32_t size);
+ int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
+ bool enable,
+ bool lock);
int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
struct PP_TemperatureRange *range);
int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
--
2.7.4
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[PATCH v2 2/3] drm/amd/powerplay:add hwmgr callback to update nbpstate on Carrizo
Add hwmgr callback "update_nbdpm_pstate".This will use to access
"cz_nbdpm_pstate_enable_disable" function to enable/disable low
memory pstate.
Signed-off-by: suresh guttula
---
v2: commit message edited to explain more details
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 1 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h| 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index 53cf787..553a203 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1992,6 +1992,7 @@ static const struct pp_hwmgr_func smu8_hwmgr_funcs = {
.power_state_set = smu8_set_power_state_tasks,
.dynamic_state_management_disable = smu8_disable_dpm_tasks,
.notify_cac_buffer_info = smu8_notify_cac_buffer_info,
+ .update_nbdpm_pstate = smu8_nbdpm_pstate_enable_disable,
.get_thermal_temperature_range = smu8_get_thermal_temperature_range,
};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 07d180ce..fb0f96f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -317,6 +317,9 @@ struct pp_hwmgr_func {
uint32_t mc_addr_low,
uint32_t mc_addr_hi,
uint32_t size);
+ int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
+ bool enable,
+ bool lock);
int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
struct PP_TemperatureRange *range);
int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
--
2.7.4
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[PATCH v2 3/3] drm/amd:Enable/Disable NBPSTATE on On/OFF of UVD
We observe black lines (underflow) on display when playing a
4K video with UVD. On Disabling Low memory P state this issue is
not seen.
In this patch ,disabling low memory P state only when video
size >= 4k.
Multiple runs of power measurement shows no imapct
Signed-off-by: suresh guttula
---
v2: Enable/disable low memory pstate logic added to
amdgpu_dpm_enable_uvd() instead of parser function
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 17 +
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 2 ++
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 7235cd0..66c0dbd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -33,6 +33,8 @@
#include
#include
#include
+#include "hwmgr.h"
+#define WIDTH_4K 3840
static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
@@ -1956,6 +1958,21 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev,
bool enable)
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD,
!enable);
mutex_unlock(>pm.mutex);
}
+ /* enable/disable Low Memory PState for UVD (4k videos) */
+ if (adev->asic_type == CHIP_STONEY &&
+ adev->uvd.decode_image_width >= WIDTH_4K) {
+ struct pp_hwmgr *hwmgr;
+ struct pp_instance *pp_handle =
+ (struct pp_instance *)adev->powerplay.pp_handle;
+ if (pp_handle) {
+ hwmgr = pp_handle->hwmgr;
+ if (hwmgr && hwmgr->hwmgr_func &&
+ hwmgr->hwmgr_func->update_nbdpm_pstate)
+ hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
+ !enable,
+ true);
+ }
+ }
}
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 69896f4..4e5d13e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -692,6 +692,8 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device
*adev, uint32_t *msg,
buf_sizes[0x1] = dpb_size;
buf_sizes[0x2] = image_size;
buf_sizes[0x4] = min_ctx_size;
+ /* store image width to adjust nb memory pstate */
+ adev->uvd.decode_image_width = width;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index a3ab1a4..5eb6328 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -65,6 +65,8 @@ struct amdgpu_uvd {
struct drm_sched_entity entity;
struct delayed_work idle_work;
unsignedharvest_config;
+ /* store image width to adjust nb memory state */
+ unsigneddecode_image_width;
};
int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
--
2.7.4
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[PATCH 1/3] Revert "drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVD"
From: "S, Shirish"
This reverts commit dbd8299c32f6f413f6cfe322fe0308f3cfc577e8.
Reason for revert:
This patch sends msg PPSMC_MSG_DisableLowMemoryPstate(0x002e)
in wrong of sequence to SMU which is before PPSMC_MSG_UVDPowerON (0x0008).
This leads to SMU failing to service the request as it is
dependent on UVD to be powered ON, since it accesses UVD
registers.
This msg should ideally be sent only when the UVD is about to decode
a 4k video.
Signed-off-by: Shirish S
Signed-off-by: suresh guttula
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index fef111d..53cf787 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1228,17 +1228,14 @@ static int smu8_dpm_force_dpm_level(struct pp_hwmgr
*hwmgr,
static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
- if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
- smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);
+ if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
- }
return 0;
}
static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
{
if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
- smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);
return smum_send_msg_to_smc_with_parameter(
hwmgr,
PPSMC_MSG_UVDPowerON,
--
2.7.4
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[PATCH v2] drm/amd/display: set backlight level limit to 1
From: "Guttula, Suresh"
This patch will work as workaround for silicon limitation
related to PWM dutycycle when the backlight level goes to 0.
Actually PWM value is 16 bit value and valid range from 1-65535.
when ever user requested to set this PWM value to 0 which is not
fall in the range, in VBIOS taken care this by limiting to 1.
This patch here will do the same. Either driver or VBIOS can not
pass 0 value as it is not a valid range for PWM and it will
give a high PWM pulse which is not the intended behaviour as
per HW constraints.
Signed-off-by: suresh guttula
Reviewed-by: Harry Wentland
---
v2 : comment edited to represent general usecase
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 492230c..be261ef 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1518,6 +1518,13 @@ static int amdgpu_dm_backlight_update_status(struct
backlight_device *bd)
{
struct amdgpu_display_manager *dm = bl_get_data(bd);
+ /*
+* PWM interperts 0 as 100% rather than 0% because of HW
+* limitation for level 0.So limiting minimum brightness level
+* to 1.
+*/
+ if (bd->props.brightness < 1)
+ return 1;
if (dc_link_set_backlight_level(dm->backlight_link,
bd->props.brightness, 0, 0))
return 0;
--
2.7.4
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[PATCH 1/3] Revert "drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVD"
From: "S, Shirish"
This reverts commit dbd8299c32f6f413f6cfe322fe0308f3cfc577e8.
Reason for revert:
This patch sends msg PPSMC_MSG_DisableLowMemoryPstate(0x002e)
in wrong of sequence to SMU which is before PPSMC_MSG_UVDPowerON (0x0008).
This leads to SMU failing to service the request as it is
dependent on UVD to be powered ON, since it accesses UVD
registers.
This msg should ideally be sent only when the UVD is about to decode
a 4k video.
Signed-off-by: Shirish S
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index fef111d..53cf787 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1228,17 +1228,14 @@ static int smu8_dpm_force_dpm_level(struct pp_hwmgr
*hwmgr,
static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
- if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
- smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);
+ if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
- }
return 0;
}
static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
{
if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
- smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);
return smum_send_msg_to_smc_with_parameter(
hwmgr,
PPSMC_MSG_UVDPowerON,
--
2.7.4
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[PATCH 2/3] drm/amd/powerplay:add hwmgr callback to update nbpstate on Carrizo
This callback is used to access hwmgr function named as
cz_nbdpm_pstate_enable_disable.
Signed-off-by: suresh guttula
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 1 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h| 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index 53cf787..553a203 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1992,6 +1992,7 @@ static const struct pp_hwmgr_func smu8_hwmgr_funcs = {
.power_state_set = smu8_set_power_state_tasks,
.dynamic_state_management_disable = smu8_disable_dpm_tasks,
.notify_cac_buffer_info = smu8_notify_cac_buffer_info,
+ .update_nbdpm_pstate = smu8_nbdpm_pstate_enable_disable,
.get_thermal_temperature_range = smu8_get_thermal_temperature_range,
};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 07d180ce..fb0f96f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -317,6 +317,9 @@ struct pp_hwmgr_func {
uint32_t mc_addr_low,
uint32_t mc_addr_hi,
uint32_t size);
+ int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
+ bool enable,
+ bool lock);
int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
struct PP_TemperatureRange *range);
int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
--
2.7.4
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[PATCH 3/3] drm/amd:Enable/Disable NBPSTATE on On/OFF of UVD
We observe black lines (underflow) on display when playing a
4K video with UVD. On Disabling Low memory P state this issue is
not seen.
In this patch ,disabling low memory P state only when video
size >= 4k.
Multiple runs of power measurement shows no imapct
Signed-off-by: suresh guttula
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 17 +
drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 4 +++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index e5a6db6..6902719 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -38,6 +38,7 @@
#include "amdgpu_uvd.h"
#include "cikd.h"
#include "uvd/uvd_4_2_d.h"
+#include "hwmgr.h"
/* 1 second timeout */
#define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
@@ -78,6 +79,7 @@
#define UVD_GPCOM_VCPU_DATA1 0x03c5
#define UVD_NO_OP 0x03ff
#define UVD_BASE_SI0x3800
+#define WIDTH_4K3840
/**
* amdgpu_uvd_cs_ctx - Command submission parser context
@@ -528,6 +530,21 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device
*adev, uint32_t *msg,
unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
unsigned min_ctx_size = ~0;
+//disable Low Memory PState for UVD(4k videos)
+ if (adev->asic_type == CHIP_STONEY && width >= WIDTH_4K) {
+ struct pp_hwmgr *hwmgr;
+ struct pp_instance *pp_handle =
+ (struct pp_instance *)adev->powerplay.pp_handle;
+ if (pp_handle) {
+ hwmgr = pp_handle->hwmgr;
+ if (hwmgr && hwmgr->hwmgr_func &&
+ hwmgr->hwmgr_func->update_nbdpm_pstate)
+ hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
+ false,
+ true);
+ }
+ }
+
image_size = width * height;
image_size += image_size / 2;
image_size = ALIGN(image_size, 1024);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
index 553a203..0bf56f7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
@@ -1228,8 +1228,10 @@ static int smu8_dpm_force_dpm_level(struct pp_hwmgr
*hwmgr,
static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
- if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
+ if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
+ smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);
return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
+ }
return 0;
}
--
2.7.4
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Re: [PATCH] drm/amd/display: set backlight level limit to 1
On 10/26/2018 12:04 AM, Wentland, Harry wrote:
> On 2018-10-25 2:58 a.m., Guttula, Suresh wrote:
>> This patch will work as workaround for silicon limitation
>> related to PWM dutycycle when the backlight level goes to 0.
>>
>> Actually PWM value is 16 bit value and valid range from 1-65535.
>> when ever user requested to set this PWM value to 0 which is not
>> fall in the range, in VBIOS taken care this by limiting to 1.
>> This patch here will do the same. Either driver or VBIOS can not
>> pass 0 value as it is not a valid range for PWM and it will
>> give a high PWM pulse which is not the intented behaviour as
>> per HW constraints.
>>
>
>
> Comments from Windows dev, Anthony, CCed here as well:
>> In Windows, we typically never set backlight PWM value to 0.
>> Windows brightness slider is from 0 - 100% brightness.
>> 0% brightness maps to some non-zero value. So user never gets the chance to
>> set value to 0.
>>
>> I'm not 100% sure what kind of flashing they are seeing.
>> I thought 0 PWM works, and just means PWM signal always low, I think it
>> would equate to panel backlight completely being off.
>> I do know of a flashing issue caused by fractional PWM at low PWM values,
>> but this would not even be at 0. The flashing problem would be anywhere from
>> 1 - 300 for example. (out of 65535)
>
> Do you see flickering when value is at 0 or in the 1 > 0 transition? 1 would
> be 65535/256 = 256 and put us right in the 1-300 range that has a flashing
> problem.
>
> Harry
>
We can not make out if flicker is at transition from 1 to 0 or exactly
at 0, because the flickering is very instantaneous.But, I am not able to
see the issue @1 , only seen the issue after going down from 1.
Thanks,
Suresh G
>> Signed-off-by: suresh guttula
>> ---
>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 492230c..38f84b2 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -1518,6 +1518,14 @@ static int amdgpu_dm_backlight_update_status(struct
>> backlight_device *bd)
>> {
>> struct amdgpu_display_manager *dm = bl_get_data(bd);
>>
>> +/*
>> + * When we use brightness low key to reduce the brightness,
>> + * brightness level reaching to 0, with which we can see flash
>> + * screen on ui beacuse of HW limitation.To avoid that we are
>> + * limiting level to 1
>> + */
>> +if (bd->props.brightness < 1)
>> +return 1;
>> if (dc_link_set_backlight_level(dm->backlight_link,
>> bd->props.brightness, 0, 0))
>> return 0;
>>
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[PATCH] drm/amd/display: set backlight level limit to 1
This patch will work as workaround for silicon limitation
related to PWM dutycycle when the backlight level goes to 0.
Actually PWM value is 16 bit value and valid range from 1-65535.
when ever user requested to set this PWM value to 0 which is not
fall in the range, in VBIOS taken care this by limiting to 1.
This patch here will do the same. Either driver or VBIOS can not
pass 0 value as it is not a valid range for PWM and it will
give a high PWM pulse which is not the intented behaviour as
per HW constraints.
Signed-off-by: suresh guttula
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 492230c..38f84b2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1518,6 +1518,14 @@ static int amdgpu_dm_backlight_update_status(struct
backlight_device *bd)
{
struct amdgpu_display_manager *dm = bl_get_data(bd);
+ /*
+* When we use brightness low key to reduce the brightness,
+* brightness level reaching to 0, with which we can see flash
+* screen on ui beacuse of HW limitation.To avoid that we are
+* limiting level to 1
+*/
+ if (bd->props.brightness < 1)
+ return 1;
if (dc_link_set_backlight_level(dm->backlight_link,
bd->props.brightness, 0, 0))
return 0;
--
2.7.4
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