Re: [PATCH] iommu/amd: flush IOTLB for specific domains only
Hi I am getting "AMD-Vi: Completion-Wait loop timed out" error approximately once per several days with R9 390. Is there a reason why this patch isn't in the mainstream linux-git yet? -Jan [18107.021297] AMD-Vi: Completion-Wait loop timed out [18107.168770] AMD-Vi: Completion-Wait loop timed out [18107.444225] AMD-Vi: Completion-Wait loop timed out [18107.714855] AMD-Vi: Completion-Wait loop timed out [18107.846366] AMD-Vi: Completion-Wait loop timed out [18108.047749] AMD-Vi: Event logged [ [18108.047752] IOTLB_INV_TIMEOUT device=23:00.0 address=0x00042bb129e0] [18108.179774] AMD-Vi: Completion-Wait loop timed out [18108.580262] AMD-Vi: Completion-Wait loop timed out [18108.710005] AMD-Vi: Completion-Wait loop timed out [18108.911565] AMD-Vi: Event logged [ [18108.911567] IOTLB_INV_TIMEOUT device=23:00.0 address=0x00042bb12a80] [18109.041945] AMD-Vi: Completion-Wait loop timed out [18109.243115] AMD-Vi: Completion-Wait loop timed out [18109.646030] AMD-Vi: Completion-Wait loop timed out [18109.847087] AMD-Vi: Completion-Wait loop timed out [18109.918406] clocksource: timekeeping watchdog on CPU5: Marking clocksource 'tsc' as unstable because the skew is too large: [18109.918408] clocksource: 'hpet' wd_now: 5f6204a6 wd_last: 5e860c6b mask: [18109.918408] clocksource: 'tsc' cs_now: 34ca9e6f0220 cs_last: 34c9ebff5f00 mask: [18109.918410] sched_clock: Marking unstable (18109972341058, -53936107)<-(18110036284612, -117879661) [18109.918411] tsc: Marking TSC unstable due to clocksource watchdog [18109.918421] AMD-Vi: Event logged [ [18109.918423] IOTLB_INV_TIMEOUT device=23:00.0 address=0x00042bb12b20] [18110.119761] sched: RT throttling activated [18110.249804] AMD-Vi: Completion-Wait loop timed out [18110.453355] AMD-Vi: Completion-Wait loop timed out [18110.652707] AMD-Vi: Completion-Wait loop timed out [18110.854045] AMD-Vi: Completion-Wait loop timed out [18111.055387] AMD-Vi: Completion-Wait loop timed out [18111.126714] AMD-Vi: Event logged [ [18111.126717] IOTLB_INV_TIMEOUT device=23:00.0 address=0x00042bb12bc0] [18111.127250] clocksource: Switched to clocksource hpet [18111.144384] AMD-Vi: Completion-Wait loop timed out [18111.274097] AMD-Vi: Completion-Wait loop timed out [18111.427604] AMD-Vi: Completion-Wait loop timed out [18111.533317] AMD-Vi: Completion-Wait loop timed out [18111.663103] AMD-Vi: Completion-Wait loop timed out [18111.891058] AMD-Vi: Event logged [ [18111.891061] IOTLB_INV_TIMEOUT device=23:00.0 address=0x00042bb12c60] [18111.894334] AMD-Vi: Completion-Wait loop timed out [18112.024375] AMD-Vi: Completion-Wait loop timed out [18112.167603] AMD-Vi: Completion-Wait loop timed out [18112.297630] AMD-Vi: Completion-Wait loop timed out [18112.427562] AMD-Vi: Completion-Wait loop timed out [18112.557171] AMD-Vi: Completion-Wait loop timed out [18112.689019] AMD-Vi: Completion-Wait loop timed out [18112.891054] AMD-Vi: Event logged [ [18112.891056] IOTLB_INV_TIMEOUT device=23:00.0 address=0x00042bb12d00] [18112.927055] AMD-Vi: Completion-Wait loop timed out [18113.039385] AMD-Vi: Completion-Wait loop timed out [18113.187600] AMD-Vi: Completion-Wait loop timed out [18113.315955] AMD-Vi: Completion-Wait loop timed out [18113.445461] AMD-Vi: Completion-Wait loop timed out [18113.600945] AMD-Vi: Completion-Wait loop timed out [18113.724978] AMD-Vi: Completion-Wait loop timed out [18113.891067] AMD-Vi: Event logged [ [18113.891069] IOTLB_INV_TIMEOUT device=23:00.0 address=0x00042bb12da0] [18113.854379] AMD-Vi: Completion-Wait loop timed out [18114.024385] AMD-Vi: Completion-Wait loop timed out [18114.173507] AMD-Vi: Completion-Wait loop timed out [18114.310944] AMD-Vi: Completion-Wait loop timed out [18114.573226] AMD-Vi: Completion-Wait loop timed out [18114.621895] AMD-Vi: Completion-Wait loop timed out [18114.734704] AMD-Vi: Completion-Wait loop timed out [18114.891088] AMD-Vi: Event logged [ [18114.891090] IOTLB_INV_TIMEOUT device=23:00.0 address=0x00042bb12e40] [18114.910947] AMD-Vi: Completion-Wait loop timed out [18115.039803] AMD-Vi: Completion-Wait loop timed out [18115.184277] AMD-Vi: Completion-Wait loop timed out [18115.324281] AMD-Vi: Completion-Wait loop timed out [18115.464271] AMD-Vi: Completion-Wait loop timed out [18115.677841] AMD-Vi: Completion-Wait loop timed out [18115.747713] AMD-Vi: Completion-Wait loop timed out [18115.891107] AMD-Vi: Event logged [ [18115.891109] IOTLB_INV_TIMEOUT device=23:00.0 address=0x00042bb12ee0] [18115.884118] AMD-Vi: Completion-Wait loop timed out [18116.020404] AMD-Vi: Completion-Wait loop timed out [18116.157621] AMD-Vi: Completion-Wait loop timed out [18116.291560] AMD-Vi: Completion-Wait loop timed out [18116.420952] AMD-Vi: Completion-Wait loop timed out [18116.420952] [ cut here ] [18116.420952] WARNING: CPU: 4 PID: 0 at drivers/iommu/amd_iommu.c:1256 __domain_flush_pages+0x1d0/0x1f0 [18116.420952]
Re: [PATCH 000/100] Add Vega10 Support
On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher <alexdeuc...@gmail.com> wrote: > On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0...@gmail.com> > wrote: > > Hi > > > > https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/ > drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask. > h?h=amd-staging-4.9=9555ef0ba926df25d9a637d0ea21bc0d231c21d2 > > > > The file nbio_6_1_sh_mask.h is uncompressed. It consists from 133884 > lines. > > Only generated C/C++ code will be able to utilize the content of such a > file > > efficiently. All hand-written codes combined will be able to utilize > about > > 1% of the file. > > > > Is there a reason why nbio_6_1_sh_mask.h is huge? > > That IP block contains a lot of registers. The idea is to open source > as much IP as possible to facilitate debugging, new features, etc. > > Alex > [This email contains long/wide lines and should be viewed on a sufficiently wide screen] For example if I open the file in vim and go to line 66952: #define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 Then abstracting away some of the digits used in the defined identifier and using egrep: $ egrep "\<DWC_E12MP_PHY_X._NS_X._._LANE._DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_.__DTB_SEL__SHIFT\>" nbio_6_1_sh_mask.h #define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 #define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 0x9 The egrep command produced 20 lines. Instead of the many #define directives, it is a possibility to define functions such as: int DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_e__DTB_SEL__SHIFT(int a, int b, int c, int d, int e) __attribute__((pure)); I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a generated file). It is an option to modify the tool to output C functions with proper input guards instead of #define directives. Jan ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 000/100] Add Vega10 Support
Hi https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9=9555ef0ba926df25d9a637d0ea21bc0d231c21d2 The file nbio_6_1_sh_mask.h is uncompressed. It consists from 133884 lines. Only generated C/C++ code will be able to utilize the content of such a file efficiently. All hand-written codes combined will be able to utilize about 1% of the file. Is there a reason why nbio_6_1_sh_mask.h is huge? Jan ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
