[PATCH] drm/amdgpu: refine amdgpu_fru_get_product_info

[Jiansong Chen]

1. eliminate potential array index out of bounds.
2. return meaningful value for failure.

Signed-off-by: Jiansong Chen 
Change-Id: I9be36eb2e42ee46cd00464b0f2c35a4e4ea213e3
---
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 42 ++-
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 8f4a8f8d8146..39b6c6bfab45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -101,7 +101,8 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device 
*adev, uint32_t addrptr,
 int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
 {
unsigned char buff[34];
-   int addrptr = 0, size = 0;
+   int addrptr, size;
+   int len;
 
if (!is_fru_eeprom_supported(adev))
return 0;
@@ -109,7 +110,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
/* If algo exists, it means that the i2c_adapter's initialized */
if (!adev->pm.smu_i2c.algo) {
DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
-   return 0;
+   return -ENODEV;
}
 
/* There's a lot of repetition here. This is due to the FRU having
@@ -128,7 +129,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
/* Increment the addrptr by the size of the field, and 1 due to the
@@ -138,43 +139,45 @@ int amdgpu_fru_get_product_info(struct amdgpu_device 
*adev)
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU product name, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Product name should only be 32 characters. Any more,
 * and something could be wrong. Cap it at 32 to be safe
 */
-   if (size > 32) {
+   if (len >= sizeof(adev->product_name)) {
DRM_WARN("FRU Product Number is larger than 32 characters. This 
is likely a mistake");
-   size = 32;
+   len = sizeof(adev->product_name) - 1;
}
/* Start at 2 due to buff using fields 0 and 1 for the address */
-   memcpy(adev->product_name, [2], size);
-   adev->product_name[size] = '\0';
+   memcpy(adev->product_name, [2], len);
+   adev->product_name[len] = '\0';
 
addrptr += size + 1;
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU product number, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Product number should only be 16 characters. Any more,
 * and something could be wrong. Cap it at 16 to be safe
 */
-   if (size > 16) {
+   if (len >= sizeof(adev->product_number)) {
DRM_WARN("FRU Product Number is larger than 16 characters. This 
is likely a mistake");
-   size = 16;
+   len = sizeof(adev->product_number) - 1;
}
-   memcpy(adev->product_number, [2], size);
-   adev->product_number[size] = '\0';
+   memcpy(adev->product_number, [2], len);
+   adev->product_number[len] = '\0';
 
addrptr += size + 1;
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
 
if (size < 1) {
DRM_ERROR("Failed to read FRU product version, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
addrptr += size + 1;
@@ -182,18 +185,19 @@ int amdgpu_fru_get_product_info(struct amdgpu_device 
*adev)
 
if (size < 1) {
DRM_ERROR("Failed to read FRU serial number, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Serial number should only be 16 characters. Any more,
 * and something could be wrong. Cap it at 16 to be safe
 */
-   if (size > 16) {
+   if (len >= sizeof(adev->serial)) {
DRM_WARN("FRU Serial Number is larger than 16 characters. This 
is likely a mistake");
-   size = 16;
+   len = sizeof(adev->serial) - 1;
}
-   memcpy(adev->serial, [2], size);
-   adev->serial[size] = '\0';
+   memcpy(adev->serial, [2], len);
+   adev->serial[len] = '\0';
 
return 0;
 }
-- 
2.25.1

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[PATCH] drm/amdgpu: refine amdgpu_fru_get_product_info

[Jiansong Chen]

1. eliminate potential array index out of bounds.
2. return meaningful value for failure.

Signed-off-by: Jiansong Chen 
Change-Id: I9be36eb2e42ee46cd00464b0f2c35a4e4ea213e3
---
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 69 ++-
 1 file changed, 35 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 8f4a8f8d8146..5c2b4403a5b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -101,7 +101,8 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device 
*adev, uint32_t addrptr,
 int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
 {
unsigned char buff[34];
-   int addrptr = 0, size = 0;
+   int addrptr, size;
+   int len;
 
if (!is_fru_eeprom_supported(adev))
return 0;
@@ -109,7 +110,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
/* If algo exists, it means that the i2c_adapter's initialized */
if (!adev->pm.smu_i2c.algo) {
DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
-   return 0;
+   return -ENODEV;
}
 
/* There's a lot of repetition here. This is due to the FRU having
@@ -125,75 +126,75 @@ int amdgpu_fru_get_product_info(struct amdgpu_device 
*adev)
 * and the language field, so just start from 0xb, manufacturer size
 */
addrptr = 0xb;
-   size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
-   if (size < 1) {
-   DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", size);
-   return size;
+   len = size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
+   if (len < 1) {
+   DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", len);
+   return -EINVAL;
}
 
/* Increment the addrptr by the size of the field, and 1 due to the
 * size field being 1 byte. This pattern continues below.
 */
addrptr += size + 1;
-   size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
-   if (size < 1) {
-   DRM_ERROR("Failed to read FRU product name, ret:%d", size);
-   return size;
+   len = size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
+   if (len < 1) {
+   DRM_ERROR("Failed to read FRU product name, ret:%d", len);
+   return -EINVAL;
}
 
/* Product name should only be 32 characters. Any more,
 * and something could be wrong. Cap it at 32 to be safe
 */
-   if (size > 32) {
+   if (len >= sizeof(adev->product_name)) {
DRM_WARN("FRU Product Number is larger than 32 characters. This 
is likely a mistake");
-   size = 32;
+   len = sizeof(adev->product_name) - 1;
}
/* Start at 2 due to buff using fields 0 and 1 for the address */
-   memcpy(adev->product_name, [2], size);
-   adev->product_name[size] = '\0';
+   memcpy(adev->product_name, [2], len);
+   adev->product_name[len] = '\0';
 
addrptr += size + 1;
-   size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
-   if (size < 1) {
-   DRM_ERROR("Failed to read FRU product number, ret:%d", size);
-   return size;
+   len = size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
+   if (len < 1) {
+   DRM_ERROR("Failed to read FRU product number, ret:%d", len);
+   return -EINVAL;
}
 
/* Product number should only be 16 characters. Any more,
 * and something could be wrong. Cap it at 16 to be safe
 */
-   if (size > 16) {
+   if (len >= sizeof(adev->product_number)) {
DRM_WARN("FRU Product Number is larger than 16 characters. This 
is likely a mistake");
-   size = 16;
+   len = sizeof(adev->product_number) - 1;
}
-   memcpy(adev->product_number, [2], size);
-   adev->product_number[size] = '\0';
+   memcpy(adev->product_number, [2], len);
+   adev->product_number[len] = '\0';
 
addrptr += size + 1;
-   size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
+   len = size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
 
-   if (size < 1) {
-   DRM_ERROR("Failed to read FRU product version, ret:%d", size);
-   return size;
+   if (len < 1) {
+   DRM_ERROR("Failed to read FRU product version, ret:%d", len);
+   return -EINVAL;
}
 
addrptr += size + 1;
-   size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
+   len = size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
 
-   if (size < 1) {
-   

[PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

[Jiansong Chen]

The optimization is safe for old GPUs and can help performance.

Signed-off-by: Jiansong Chen 
Change-Id: Id3b1250f1fe46dddbe8498894fb97e9753b7cafe
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 3a8d52a54873..c915cc439484 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1873,6 +1873,12 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring 
*ring,
amdgpu_ring_write(ring, 0);
}
 
+   /* drop the CE preamble IB for the same context */
+   if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
+   !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
+   !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
+   return;
+
if (ib->flags & AMDGPU_IB_FLAG_CE)
header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index c35fdd2ef2d4..6d9ccae48024 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2269,6 +2269,12 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring 
*ring,
amdgpu_ring_write(ring, 0);
}
 
+   /* drop the CE preamble IB for the same context */
+   if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
+   !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
+   !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
+   return;
+
if (ib->flags & AMDGPU_IB_FLAG_CE)
header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
else
-- 
2.25.1

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[PATCH] drm/amdgpu: remove unsafe optimization to drop preamble ib

[Jiansong Chen]

Take the situation with gfxoff, the optimization may cause
corrupt CE ram contents. In addition emit_cntxcntl callback
has similar optimization which firmware can handle properly
even for power feature.

Signed-off-by: Jiansong Chen 
Change-Id: I962946557108bb0575f8b2afc25b18a6dcf0d838
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 11 +--
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 2e6789a7dc46..77baf9b48d67 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -130,7 +130,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
struct amdgpu_device *adev = ring->adev;
struct amdgpu_ib *ib = [0];
struct dma_fence *tmp = NULL;
-   bool skip_preamble, need_ctx_switch;
+   bool need_ctx_switch;
unsigned patch_offset = ~0;
struct amdgpu_vm *vm;
uint64_t fence_ctx;
@@ -227,7 +227,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
if (need_ctx_switch)
status |= AMDGPU_HAVE_CTX_SWITCH;
 
-   skip_preamble = ring->current_ctx == fence_ctx;
if (job && ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
@@ -245,14 +244,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
for (i = 0; i < num_ibs; ++i) {
ib = [i];
 
-   /* drop preamble IBs if we don't have a context switch */
-   if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
-   skip_preamble &&
-   !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
-   !amdgpu_mcbp &&
-   !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble 
CE ib must be inserted anyway */
-   continue;
-
if (job && ring->funcs->emit_frame_cntl) {
if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) {
amdgpu_ring_emit_frame_cntl(ring, false, 
secure);
-- 
2.25.1

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[PATCH] drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish

[Jiansong Chen]

dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid,
so follow its registers offset setting.

Signed-off-by: Jiansong Chen 
Change-Id: I2c8f1022c0b4c5baf70d09ec99b7b2ca8da36bba
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 85a6a10e048f..49fd10a15707 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3377,7 +3377,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_4[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007, 0xc000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x0280, 0x0280),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x0780, 0x0080),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1d00, 
0x0500),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 
0x1d00, 0x0500),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c, 0x00280400),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0x, 
0xffcf),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0x, 
0xffcf),
-- 
2.25.1

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[PATCH] drm/amd/pm: update driver if version for navy_flounder

[Jiansong Chen]

It's in accordance with pmfw 65.22.0 for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: I85fcf7a238b5a7d1da76709ef7963140702048ab
---
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 13de692a4213..102a0cf12d7a 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -31,7 +31,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3D
-#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xC
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
 
-- 
2.25.1

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[PATCH] drm/amdgpu: enable gpu recovery for navy_flounder

[Jiansong Chen]

Enable gpu recovery for navy_flounder by default to trigger
reset once needed.

Signed-off-by: Jiansong Chen 
Change-Id: If213b4c7a5444872ec51869da53a374bf40db7fe
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 087afab67e22..dd67b589b4ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4206,6 +4206,7 @@ bool amdgpu_device_should_recover_gpu(struct 
amdgpu_device *adev)
case CHIP_NAVI14:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
break;
default:
goto disabled;
-- 
2.25.1

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[PATCH] drm/amdgpu: remove unnecessary asic check for sdma5.2

[Jiansong Chen]

For sdma5.2, all sdma instances will share the same fw,
remove unnecessary asic check to be more generic.

Signed-off-by: Jiansong Chen 
Change-Id: I8b67dd588de9e7d54618404092a77b768bf0ddbd
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 31 +-
 1 file changed, 5 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index f1ba36a094da..690a5090475a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -119,15 +119,7 @@ static int sdma_v5_2_init_inst_ctx(struct 
amdgpu_sdma_instance *sdma_inst)
 
 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 {
-   int i;
-
-   for (i = 0; i < adev->sdma.num_instances; i++) {
-   release_firmware(adev->sdma.instance[i].fw);
-   adev->sdma.instance[i].fw = NULL;
-
-   if (adev->asic_type == CHIP_SIENNA_CICHLID)
-   break;
-   }
+   release_firmware(adev->sdma.instance[0].fw);
 
memset((void *)adev->sdma.instance, 0,
   sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
@@ -185,23 +177,10 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device 
*adev)
if (err)
goto out;
 
-   for (i = 1; i < adev->sdma.num_instances; i++) {
-   if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
-   adev->asic_type <= CHIP_DIMGREY_CAVEFISH) {
-   memcpy((void *)>sdma.instance[i],
-  (void *)>sdma.instance[0],
-  sizeof(struct amdgpu_sdma_instance));
-   } else {
-   snprintf(fw_name, sizeof(fw_name), 
"amdgpu/%s_sdma%d.bin", chip_name, i);
-   err = request_firmware(>sdma.instance[i].fw, 
fw_name, adev->dev);
-   if (err)
-   goto out;
-
-   err = sdma_v5_2_init_inst_ctx(>sdma.instance[i]);
-   if (err)
-   goto out;
-   }
-   }
+   for (i = 1; i < adev->sdma.num_instances; i++)
+   memcpy((void *)>sdma.instance[i],
+  (void *)>sdma.instance[0],
+  sizeof(struct amdgpu_sdma_instance));
 
DRM_DEBUG("psp_load == '%s'\n",
  adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : 
"false");
-- 
2.25.1

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[PATCH] drm/amdgpu: correct releasing the same sdma fw repeatedly

[Jiansong Chen]

Same as sienna_cichlid, dimgrey_cavefish and navy_flounder
reuse sdma0 fw for other instances, so free it only once.

Signed-off-by: Jiansong Chen 
Change-Id: I9dda4a9b73e20243ee48f54d8f0c7593d7e7354b
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index f1ba36a094da..6ac314c8be32 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -125,7 +125,8 @@ static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device 
*adev)
release_firmware(adev->sdma.instance[i].fw);
adev->sdma.instance[i].fw = NULL;
 
-   if (adev->asic_type == CHIP_SIENNA_CICHLID)
+   if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
+   adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
break;
}
 
-- 
2.25.1

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[PATCH] drm/amdkfd: correct pipe offset calculation

[Jiansong Chen]

Correct pipe offset calculation in is_pipe_enabled function,
it should be done in queues.

Signed-off-by: Jiansong Chen 
Change-Id: I826aa532ca1e5073e3329212a8096f8f5a0be057
---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index c579615451ba..c37e9c4b1fb4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -72,8 +72,8 @@ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum 
kfd_queue_type type)
 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int 
pipe)
 {
int i;
-   int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
-   + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
+   int pipe_offset = (mec * dqm->dev->shared_resources.num_pipe_per_mec
+   + pipe) * dqm->dev->shared_resources.num_queue_per_pipe;
 
/* queue is available for KFD usage if bit is 1 */
for (i = 0; i <  dqm->dev->shared_resources.num_queue_per_pipe; ++i)
-- 
2.25.1

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[PATCH] drm/amd/pm: update driver if version for navy_flounder

[Jiansong Chen]

It's in accordance with pmfw 65.18.0 for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: Ia96b6bf276f4a99a931a1203e3314a2ff407e924
---
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index eff396c7a281..78eb99962bab 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -31,7 +31,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3B
-#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xC
 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xD
 
-- 
2.25.1

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[PATCH] drm/amdgpu: update GC golden setting for navy_flounder

[Jiansong Chen]

Update GC golden setting for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: I25d5afb46ef9667a65bc897dcddf54390891e90f
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index eb05d1bc194e..841d39eb62d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3191,6 +3191,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_sienna_cichlid[] =
 
 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
 {
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 
0x78000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 
0x78000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 
0x3100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 
0x7e000100),
@@ -3199,6 +3200,8 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 
0x00b8),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 
0x1ff1, 0x0500),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 
0x, 0xff008080),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 
0x8fff, 0xff008080),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003f, 0x00280400),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0x, 
0xffcf),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0x, 
0xffcf),
-- 
2.25.1

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[PATCH v2] drm/amdgpu: disable gfxoff if VCN is busy

[Jiansong Chen]

Toggle on/off gfxoff during video playback to fix gpu hang.

v2: change sequence to be more compatible with original code.

Signed-off-by: Jiansong Chen 
Change-Id: I5b938c446884268c2cda0801121a53da980e603a
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 277a8435dd06..62d4614d48eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -358,6 +358,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work)
}
 
if (!fences && !atomic_read(>vcn.total_submission_cnt)) {
+   amdgpu_gfx_off_ctrl(adev, true);
amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,
   AMD_PG_STATE_GATE);
} else {
@@ -370,7 +371,9 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
struct amdgpu_device *adev = ring->adev;
 
atomic_inc(>vcn.total_submission_cnt);
-   cancel_delayed_work_sync(>vcn.idle_work);
+
+   if (!cancel_delayed_work_sync(>vcn.idle_work))
+   amdgpu_gfx_off_ctrl(adev, false);
 
mutex_lock(>vcn.vcn_pg_lock);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
-- 
2.25.1

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[PATCH v2] drm/amdgpu: disable gfxoff if VCN is busy

[Jiansong Chen]

Toggle on/off gfxoff during video playback to fix gpu hang.

v2: change sequence to be more compatible with original code.

Signed-off-by: Jiansong Chen 
Change-Id: I5b938c446884268c2cda0801121a53da980e603a
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 277a8435dd06..ef0878e848de 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -358,6 +358,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work)
}
 
if (!fences && !atomic_read(>vcn.total_submission_cnt)) {
+   amdgpu_gfx_off_ctrl(adev, true);
amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,
   AMD_PG_STATE_GATE);
} else {
@@ -370,7 +371,9 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
struct amdgpu_device *adev = ring->adev;
 
atomic_inc(>vcn.total_submission_cnt);
-   cancel_delayed_work_sync(>vcn.idle_work);
+
+   if (!cancel_delayed_work_sync(>vcn.idle_work);)
+   amdgpu_gfx_off_ctrl(adev, false);
 
mutex_lock(>vcn.vcn_pg_lock);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
-- 
2.25.1

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[PATCH] drm/amdgpu: disable gfxoff if VCN is busy

[Jiansong Chen]

Toggle on/off gfxoff during video playback to fix
gpu hang.

Signed-off-by: Jiansong Chen 
Change-Id: I5b938c446884268c2cda0801121a53da980e603a
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 277a8435dd06..444b89413232 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -358,6 +358,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work)
}
 
if (!fences && !atomic_read(>vcn.total_submission_cnt)) {
+   amdgpu_gfx_off_ctrl(adev, true);
amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,
   AMD_PG_STATE_GATE);
} else {
@@ -368,13 +369,16 @@ static void amdgpu_vcn_idle_work_handler(struct 
work_struct *work)
 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 {
struct amdgpu_device *adev = ring->adev;
+   bool set_clocks = !cancel_delayed_work_sync(>vcn.idle_work);
 
atomic_inc(>vcn.total_submission_cnt);
-   cancel_delayed_work_sync(>vcn.idle_work);
 
mutex_lock(>vcn.vcn_pg_lock);
-   amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
-  AMD_PG_STATE_UNGATE);
+   if (set_clocks) {
+   amdgpu_gfx_off_ctrl(adev, false);
+   amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,
+   AMD_PG_STATE_UNGATE);
+   }
 
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){
struct dpg_pause_state new_state;
-- 
2.25.1

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[PATCH] drm/amd/pm: drop navy_flounder hardcode of using soft pptable

[Jiansong Chen]

Drop navy_flounder hardcode of using soft pptable, so that it
can use pptable from vbios when available.

Signed-off-by: Jiansong Chen 
Change-Id: I33436b023d03ae77a1b92da5a8062e8466e80110
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index c2a6eb93d93c..fff1d2522463 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -337,7 +337,6 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
if ((version_major == 2 && 
smu->smu_table.boot_values.pp_table_id > 0) ||
-   adev->asic_type == CHIP_NAVY_FLOUNDER ||
adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
dev_info(adev->dev, "use driver provided pptable %d\n", 
smu->smu_table.boot_values.pp_table_id);
switch (version_minor) {
-- 
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[PATCH] Revert "drm/amdgpu: disable gfxoff temporarily for navy_flounder"

[Jiansong Chen]

This reverts commit 7e59138e97574e8dbecd1f259581277fff555d00.
TDR issue has been resovled by pmfw update.

Change-Id: Ia04709c4ba13835abfdec56558738bf6fbfac20d
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8fc69c208adb..be13495b97f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3723,7 +3723,6 @@ static void gfx_v10_0_check_gfxoff_flag(struct 
amdgpu_device *adev)
if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
break;
-   case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH:
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
break;
-- 
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[PATCH] drm/amdgpu: disable gfxoff temporarily for navy_flounder

[Jiansong Chen]

gfxoff is temporarily disabled for navy_flounder, since
at present the feature caused some tdr when performing
display operation.

Signed-off-by: Jiansong Chen 
Change-Id: Ib2be4041f82a3f5e12c657541c516815c8eb3670
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 17fb2efdadd3..9792ec737029 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3610,6 +3610,9 @@ static void gfx_v10_0_check_gfxoff_flag(struct 
amdgpu_device *adev)
if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
break;
+   case CHIP_NAVY_FLOUNDER:
+   adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+   break;
default:
break;
}
-- 
2.25.1

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[PATCH] drm/amdgpu: remove gpu_info fw support for sienna_cichlid etc.

[Jiansong Chen]

Remove gpu_info fw support for sienna_cichlid etc., since the
information can be retrieved from discovery binary.

Signed-off-by: Jiansong Chen 
Change-Id: I4cb42aae5d680f28209122bb37962a2291ef785f
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5c2eb46e9b71..a174431268b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -80,8 +80,6 @@ MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
-MODULE_FIRMWARE("amdgpu/sienna_cichlid_gpu_info.bin");
-MODULE_FIRMWARE("amdgpu/navy_flounder_gpu_info.bin");
 
 #define AMDGPU_RESUME_MS   2000
 
@@ -1669,6 +1667,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
amdgpu_device *adev)
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_VEGA20:
+   case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
default:
return 0;
case CHIP_VEGA10:
@@ -1700,12 +1700,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct 
amdgpu_device *adev)
case CHIP_NAVI12:
chip_name = "navi12";
break;
-   case CHIP_SIENNA_CICHLID:
-   chip_name = "sienna_cichlid";
-   break;
-   case CHIP_NAVY_FLOUNDER:
-   chip_name = "navy_flounder";
-   break;
}
 
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
-- 
2.25.1

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[PATCH] drm/amdgpu: declare ta firmware for navy_flounder

[Jiansong Chen]

The information provided via MODULE_FIRMWARE appears in
the module information. External tools(eg. dracut) may use the
list of fw files to include them as appropriate in an initramfs,
thus missing declaration will lead to request firmware failure
in boot time.

Signed-off-by: Jiansong Chen 
Change-Id: I0eb0231d0e4672ee00ebdbe0bd8e75245a8c1698
---
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index e16874f30d5d..6c5d9612abcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -58,7 +58,7 @@ MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
-MODULE_FIRMWARE("amdgpu/navy_flounder_asd.bin");
+MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
 
 /* address block */
 #define smnMP1_FIRMWARE_FLAGS  0x3010024
-- 
2.25.1

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[PATCH] drm/amd/pm: support runtime pptable update for sienna_cichlid etc.

[Jiansong Chen]

This avoids smu issue when enabling runtime pptable update for
sienna_cichlid and so on. Runtime pptable udpate is needed for test
and debug purpose.

Signed-off-by: Jiansong Chen 
Change-Id: I70b704ab4d6efd169f579c392e5dbc2737dc1fb2
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7a55ece1f124..7618f9972b8c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1129,7 +1129,7 @@ static int smu_disable_dpms(struct smu_context *smu)
 */
if (smu->uploading_custom_pp_table &&
(adev->asic_type >= CHIP_NAVI10) &&
-   (adev->asic_type <= CHIP_NAVI12))
+   (adev->asic_type <= CHIP_NAVY_FLOUNDER))
return 0;
 
/*
@@ -1214,7 +1214,9 @@ static int smu_hw_fini(void *handle)
 int smu_reset(struct smu_context *smu)
 {
struct amdgpu_device *adev = smu->adev;
-   int ret = 0;
+   int ret;
+
+   amdgpu_gfx_off_ctrl(smu->adev, false);
 
ret = smu_hw_fini(adev);
if (ret)
@@ -1225,8 +1227,12 @@ int smu_reset(struct smu_context *smu)
return ret;
 
ret = smu_late_init(adev);
+   if (ret)
+   return ret;
 
-   return ret;
+   amdgpu_gfx_off_ctrl(smu->adev, true);
+
+   return 0;
 }
 
 static int smu_suspend(void *handle)
-- 
2.25.1

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[PATCH] drm/amd/pm: update driver if version for navy_flounder

[Jiansong Chen]

It's in accordance with pmfw 65.8.0 for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: Iddb07c2123c0fd5dedff68f9a3a2f43685600117
---
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 1f9575a4dfe7..21d65d20e569 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -31,7 +31,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x35
-#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x4
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
 
 /* MP Apertures */
 #define MP0_Public 0x0380
-- 
2.25.1

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[PATCH] drm/amd/pm: enable MP0 DPM for sienna_cichlid

[Jiansong Chen]

Enable MP0 clock DPM for sienna_cichlid.

Signed-off-by: Jiansong Chen 
Change-Id: Iee6a05a634c200f9bbb895b963365bb001a451bc
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index b48ac591db8b..b67931fd64b4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -68,7 +68,8 @@
FEATURE_MASK(FEATURE_DPM_LINK_BIT)   | \
FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
FEATURE_MASK(FEATURE_DPM_FCLK_BIT)   | \
-   FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
+   FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)| \
+   FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
 
 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
 
@@ -230,6 +231,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
 
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
+   | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
| FEATURE_MASK(FEATURE_DS_FCLK_BIT)
-- 
2.25.1

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[PATCH] drm/amdgpu: disable runtime pm for navy_flounder

[Jiansong Chen]

Disable runtime pm for navy_flounder temporarily.

Signed-off-by: Jiansong Chen 
Change-Id: Ie1b03f09ab70e79b6dd67ede5547afa23c063eee
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 9f80eaeaf0ae..caed73d72d3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -170,6 +170,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, 
unsigned long flags)
case CHIP_VEGA20:
case CHIP_ARCTURUS:
case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
/* enable runpm if runpm=1 */
if (amdgpu_runtime_pm > 0)
adev->runpm = true;
-- 
2.25.1

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[PATCH] drm/amdgpu: use MODE1 reset for navy_flounder by default

[Jiansong Chen]

Switch default gpu reset method to MODE1 for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: I99b2d3ac04352142e288877f3b6c3138d0efd4bc
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 33a6d2d5fc16..4d1402356262 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -364,6 +364,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
 
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
return AMD_RESET_METHOD_MODE1;
default:
if (smu_baco_is_support(smu))
-- 
2.25.1

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[PATCH] drm/amdgpu/gfx10: refine mgcg setting

[Jiansong Chen]

1. enable ENABLE_CGTS_LEGACY to fix specviewperf11 random hang.
2. remove obsolete RLC_CGTT_SCLK_OVERRIDE workaround.

Signed-off-by: Jiansong Chen 
Change-Id: Id52d45ba48159c5e1c9ecf658c5b52f7fc72eb65
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d851fe80eaf4..2db195ec8d0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7285,10 +7285,8 @@ static void 
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
-
-   /* only for Vega10 & Raven1 */
-   data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
+ RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
+ RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
 
if (def != data)
WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
-- 
2.25.1

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[PATCH] drm/amd/pm: set VCN pg per instances

[Jiansong Chen]

When deciding whether to set pg for vcn1, instances
number is more generic than chip name.

Signed-off-by: Jiansong Chen 
Change-Id: I5bf3f024ac499c347e3ea72563ae75e4a540f321
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index d2320ce7ef0d..66d655958a78 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -783,7 +783,7 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct 
smu_context *smu, bool enabl
ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_PowerUpVcn, 0, NULL);
if (ret)
return ret;
-   if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+   if (adev->vcn.num_vcn_inst > 1) {
ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_PowerUpVcn,
  0x1, 
NULL);
if (ret)
@@ -795,7 +795,7 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct 
smu_context *smu, bool enabl
ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_PowerDownVcn, 0, NULL);
if (ret)
return ret;
-   if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+   if (adev->vcn.num_vcn_inst > 1) {
ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_PowerDownVcn,
  0x1, 
NULL);
if (ret)
-- 
2.25.1

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[PATCH] drm/amd/pm: enable run_btc callback for sienna_cichlid

[Jiansong Chen]

DC BTC support for sienna_cichlid is added, it provides
the DC tolerance and aging measurements.

Signed-off-by: Jiansong Chen 
Change-Id: I93b439b99c1bf365194d61385eb0fe0251f27041
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 8ffa8b71b75f..d2320ce7ef0d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -95,6 +95,7 @@ static struct cmn2asic_msg_mapping 
sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(TransferTableSmu2Dram,  
PPSMC_MSG_TransferTableSmu2Dram,   0),
MSG_MAP(TransferTableDram2Smu,  
PPSMC_MSG_TransferTableDram2Smu,   0),
MSG_MAP(UseDefaultPPTable,  PPSMC_MSG_UseDefaultPPTable,
   0),
+   MSG_MAP(RunDcBtc,   PPSMC_MSG_RunDcBtc, 
   0),
MSG_MAP(EnterBaco,  PPSMC_MSG_EnterBaco,
   0),
MSG_MAP(SetSoftMinByFreq,   PPSMC_MSG_SetSoftMinByFreq, 
   0),
MSG_MAP(SetSoftMaxByFreq,   PPSMC_MSG_SetSoftMaxByFreq, 
   0),
@@ -1735,6 +1736,11 @@ static int sienna_cichlid_get_dpm_ultimate_freq(struct 
smu_context *smu,
return ret;
 }
 
+static int sienna_cichlid_run_btc(struct smu_context *smu)
+{
+   return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
+}
+
 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
 {
struct amdgpu_device *adev = smu->adev;
@@ -2792,6 +2798,7 @@ static const struct pptable_funcs 
sienna_cichlid_ppt_funcs = {
.mode1_reset = smu_v11_0_mode1_reset,
.get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+   .run_btc = sienna_cichlid_run_btc,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
-- 
2.25.1

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[PATCH] drm/amd/pm: update driver if version for navy_flounder

[Jiansong Chen]

It's in accordance with pmfw 65.7.0 for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: Iaac4c591f92c9a00891a29757d142c0109dcd676
---
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 65363d56e3cc..77d0996f4ec2 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -31,7 +31,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x35
-#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x4
 
 /* MP Apertures */
 #define MP0_Public 0x0380
-- 
2.25.1

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[PATCH] Revert "drm/amdgpu: disable gfxoff for navy_flounder"

[Jiansong Chen]

This reverts commit 6a72ad7e387c6fec821c230fda3460f79fc0f877.
Newly released sdma fw (51.52) provides a fix for the issue.
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index e87d43537013..e527be22a3d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3610,9 +3610,6 @@ static void gfx_v10_0_check_gfxoff_flag(struct 
amdgpu_device *adev)
if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
break;
-   case CHIP_NAVY_FLOUNDER:
-   adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
-   break;
default:
break;
}
-- 
2.25.1

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[PATCH] drm/amdgpu: disable gfxoff for navy_flounder

[Jiansong Chen]

gfxoff is temporarily disabled for navy_flounder,
since at present the feature has broken some basic
amdgpu test.

Signed-off-by: Jiansong Chen 
Change-Id: Icc030370997a66fb9f01cdd4b1c45816e3c88584
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d851fe80eaf4..de6e6de41867 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3610,6 +3610,9 @@ static void gfx_v10_0_check_gfxoff_flag(struct 
amdgpu_device *adev)
if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
break;
+   case CHIP_NAVY_FLOUNDER:
+   adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+   break;
default:
break;
}
-- 
2.25.1

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[PATCH] drm/amdgpu: enable GFXOFF for navy_flounder

[Jiansong Chen]

Enable GFXOFF for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: Ia49c1ad70e3521447b9db101f5c0eae70b1df665
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 +
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ca16f01956d3..fe8ccc9be682 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7529,6 +7529,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
case CHIP_NAVI14:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
amdgpu_gfx_off_ctrl(adev, enable);
break;
default:
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index a9453ec01619..7d7de854a826 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1029,6 +1029,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, 
bool enable)
case CHIP_NAVI14:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
if (enable)
-- 
2.17.1

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[PATCH] drm/amdgpu: update GC golden setting for navy_flounder

[Jiansong Chen]

Update GC golden setting for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: Ia7e82616b0be48f397c73b015823ac10ef907f08
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index db9f1e89a0f8..ca16f01956d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3127,7 +3127,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 
0x3100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 
0x7e000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007, 0xc000),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0200),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0280),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 
0x00b8),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 
0x1ff1, 0x0500),
@@ -3158,7 +3158,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 
0x),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x, 0x010b),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbf, 0x00a0),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, 
0x03ff)
 };
-- 
2.17.1

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[PATCH] drm/amd/powerplay: update driver if version for navy_flounder

[Jiansong Chen]

It's in accordance with pmfw 65.5.0 for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: I984a1147030264adbc02230e2e1dd416d4ad63b0
---
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 9504f9954fd3..6a42331aba8a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -31,7 +31,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV12 0x33
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
-#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3
 
 /* MP Apertures */
 #define MP0_Public 0x0380
-- 
2.17.1

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[PATCH] drm/amd/powerplay: retrieve VCN dpm table per instances

[Jiansong Chen]

To accommodate VCN instances variance, otherwise it may trigger
smu response error for configuration with less instances.

Signed-off-by: Jiansong Chen 
Change-Id: I0bfe31f1f5638d539ac6ded3bffee8f57574bafa
---
 .../drm/amd/powerplay/sienna_cichlid_ppt.c| 68 +++
 1 file changed, 38 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 87eedd7c28ec..c8b59a891f5d 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -525,6 +525,7 @@ static int sienna_cichlid_set_default_dpm_table(struct 
smu_context *smu)
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
struct smu_11_0_dpm_table *dpm_table;
+   struct amdgpu_device *adev = smu->adev;
int ret = 0;
 
/* socclk dpm table setup */
@@ -617,22 +618,26 @@ static int sienna_cichlid_set_default_dpm_table(struct 
smu_context *smu)
dpm_table->max = dpm_table->dpm_levels[0].value;
}
 
+
/* vclk1 dpm table setup */
-   dpm_table = _context->dpm_tables.vclk1_table;
-   if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
-   ret = smu_v11_0_set_single_dpm_table(smu,
-SMU_VCLK1,
-dpm_table);
-   if (ret)
-   return ret;
-   dpm_table->is_fine_grained =
-   !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
-   } else {
-   dpm_table->count = 1;
-   dpm_table->dpm_levels[0].value = 
smu->smu_table.boot_values.vclk / 100;
-   dpm_table->dpm_levels[0].enabled = true;
-   dpm_table->min = dpm_table->dpm_levels[0].value;
-   dpm_table->max = dpm_table->dpm_levels[0].value;
+   if (adev->vcn.num_vcn_inst > 1) {
+   dpm_table = _context->dpm_tables.vclk1_table;
+   if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) 
{
+   ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_VCLK1,
+dpm_table);
+   if (ret)
+   return ret;
+   dpm_table->is_fine_grained =
+   
!driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
+   } else {
+   dpm_table->count = 1;
+   dpm_table->dpm_levels[0].value =
+   smu->smu_table.boot_values.vclk / 100;
+   dpm_table->dpm_levels[0].enabled = true;
+   dpm_table->min = dpm_table->dpm_levels[0].value;
+   dpm_table->max = dpm_table->dpm_levels[0].value;
+   }
}
 
/* dclk0 dpm table setup */
@@ -654,21 +659,24 @@ static int sienna_cichlid_set_default_dpm_table(struct 
smu_context *smu)
}
 
/* dclk1 dpm table setup */
-   dpm_table = _context->dpm_tables.dclk1_table;
-   if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
-   ret = smu_v11_0_set_single_dpm_table(smu,
-SMU_DCLK1,
-dpm_table);
-   if (ret)
-   return ret;
-   dpm_table->is_fine_grained =
-   !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
-   } else {
-   dpm_table->count = 1;
-   dpm_table->dpm_levels[0].value = 
smu->smu_table.boot_values.dclk / 100;
-   dpm_table->dpm_levels[0].enabled = true;
-   dpm_table->min = dpm_table->dpm_levels[0].value;
-   dpm_table->max = dpm_table->dpm_levels[0].value;
+   if (adev->vcn.num_vcn_inst > 1) {
+   dpm_table = _context->dpm_tables.dclk1_table;
+   if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) 
{
+   ret = smu_v11_0_set_single_dpm_table(smu,
+SMU_DCLK1,
+dpm_table);
+   if (ret)
+   return ret;
+   dpm_table->is_fine_grained =
+   
!driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
+   } else {
+   dpm_table->count = 1;
+   dpm_table->dpm_levels[0].v

[PATCH] drm/amd/powerplay: update driver if version for navy_flounder

[Jiansong Chen]

It's in accordance with pmfw 65.3.0 for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: I97b0a28e280c3ac5c63f9c17a47c08b2c9b7d65e
---
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index b18ee5837f50..429f5aa8924a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -31,7 +31,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV12 0x33
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
-#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2B
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2
 
 /* MP Apertures */
 #define MP0_Public 0x0380
-- 
2.17.1

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[PATCH] drm/amd/powerplay: fix typos for clk map

[Jiansong Chen]

It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0.

Signed-off-by: Jiansong Chen 
Change-Id: Ib2239b35840d3774a0e1aa3114d2f965e6d88e7c
---
 drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index cae8e776fafe..87eedd7c28ec 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -128,8 +128,8 @@ static struct cmn2asic_mapping 
sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(UCLK,   PPCLK_UCLK),
CLK_MAP(MCLK,   PPCLK_UCLK),
CLK_MAP(DCLK,   PPCLK_DCLK_0),
-   CLK_MAP(DCLK1,  PPCLK_DCLK_0),
-   CLK_MAP(VCLK,   PPCLK_VCLK_1),
+   CLK_MAP(DCLK1,  PPCLK_DCLK_1),
+   CLK_MAP(VCLK,   PPCLK_VCLK_0),
CLK_MAP(VCLK1,  PPCLK_VCLK_1),
CLK_MAP(DCEFCLK,PPCLK_DCEFCLK),
CLK_MAP(DISPCLK,PPCLK_DISPCLK),
-- 
2.17.1

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[PATCH] drm/amd/powerplay: limit smu support to Arcturus for onevf

[Jiansong Chen]

Under onevf mode the smu support to other chips is not well
verified yet.

Change-Id: Idbc166bea203cabba7615a255541eb283f18e1a0
Signed-off-by: Jiansong Chen 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index d4599fa6dc0b..88b4e5642302 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -571,7 +571,10 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
if (adev->asic_type == CHIP_VEGA20)
return (amdgpu_dpm == 2) ? true : false;
else if (adev->asic_type >= CHIP_ARCTURUS) {
-   if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
+   if (amdgpu_sriov_vf(adev) &&
+   !(adev->asic_type == CHIP_ARCTURUS &&
+ amdgpu_sriov_is_pp_one_vf(adev)))
+
return false;
else
return true;
-- 
2.17.1

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