[PATCH 2/2] drm/amd/pm: enable thermal alert on smu 14.0.2/3

[Kenneth Feng]

enable thermal alert on smu 14.0.2/3

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h  |  8 +++
 .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c| 68 ++-
 .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c  | 35 +-
 3 files changed, 108 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
index 3d34b3869df6..9b97a4e95c0f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
@@ -48,6 +48,10 @@
 
 #define SMU14_TOOL_SIZE0x19000
 
+#define CTF_OFFSET_EDGE5
+#define CTF_OFFSET_HOTSPOT 5
+#define CTF_OFFSET_MEM 5
+
 extern const int decoded_link_speed[5];
 extern const int decoded_link_width[7];
 
@@ -236,5 +240,9 @@ int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
 
 void smu_v14_0_set_smu_mailbox_registers(struct smu_context *smu);
 
+int smu_v14_0_enable_thermal_alert(struct smu_context *smu);
+
+int smu_v14_0_disable_thermal_alert(struct smu_context *smu);
+
 #endif
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index fbfe9cae0e05..8cce17d1f230 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -38,6 +38,8 @@
 #include "amdgpu_ras.h"
 #include "smu_cmn.h"
 
+#include "asic_reg/thm/thm_14_0_2_offset.h"
+#include "asic_reg/thm/thm_14_0_2_sh_mask.h"
 #include "asic_reg/mp/mp_14_0_2_offset.h"
 #include "asic_reg/mp/mp_14_0_2_sh_mask.h"
 
@@ -853,12 +855,19 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device 
*adev,
   unsigned tyep,
   enum amdgpu_interrupt_state state)
 {
+   struct smu_context *smu = adev->powerplay.pp_handle;
+   uint32_t low, high;
uint32_t val = 0;
 
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
/* For THM irqs */
-   // TODO
+   val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 
1);
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 
1);
+   WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
+
+   WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
 
/* For MP1 SW irqs */
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 
0) ||
@@ -875,7 +884,24 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device 
*adev,
break;
case AMDGPU_IRQ_STATE_ENABLE:
/* For THM irqs */
-   // TODO
+   low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
+ smu->thermal_range.min / 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
+  smu->thermal_range.software_shutdown_temp);
+   val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 
5);
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 
1);
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 
0);
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 
0);
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, 
(high & 0xff));
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, 
(low & 0xff));
+   val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
+   WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
+
+   val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
+   val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
+   val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
+   WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
 
/* For MP1 SW irqs */
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 
0) ||
@@ -1849,3 +1875,41 @@ int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
return ret;
 }
 
+static int smu_v14_0_allow_ih_interrupt(struct smu_context *smu)
+{
+   return smu_cmn_send_smc_msg(smu,
+   SMU_MSG_AllowIHHostInterrupt,
+   NULL);
+}
+
+static int smu_v14_0_process_pending_interrupt(struct smu_context *smu)
+{
+   int ret = 0;
+
+   if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
+   ret = smu_v14_0_allow_ih_interrupt(smu);
+
+   return ret;
+}
+
+int smu_v14_0_enable_thermal_alert(struct smu_conte

[PATCH 1/2] drm/amd/amdgpu: add thm 14.0.2 header file

[Kenneth Feng]

add thm 14.0.2 header file

v2: add license, update to latest changes (Alex)

Signed-off-by: Kenneth Feng 
Signed-off-by: Alex Deucher 
---
 .../include/asic_reg/thm/thm_14_0_2_offset.h  | 228 +
 .../include/asic_reg/thm/thm_14_0_2_sh_mask.h | 940 ++
 2 files changed, 1168 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h
new file mode 100644
index ..78a71b124d22
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright 2024 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _thm_14_0_2_OFFSET_HEADER
+#define _thm_14_0_2_OFFSET_HEADER
+
+
+
+// addressBlock: thm_thm_SmuThmDec
+// base address: 0x59800
+#define regTHM_TCON_CUR_TMP
 0x
+#define regTHM_TCON_CUR_TMP_BASE_IDX   
 0
+#define regTHM_TCON_HTC
 0x0001
+#define regTHM_TCON_HTC_BASE_IDX   
 0
+#define regTHM_TCON_THERM_TRIP 
 0x0002
+#define regTHM_TCON_THERM_TRIP_BASE_IDX
 0
+#define regTHM_CTF_DELAY   
 0x0003
+#define regTHM_CTF_DELAY_BASE_IDX  
 0
+#define regTHM_GPIO_PROCHOT_CTRL   
 0x0004
+#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX  
 0
+#define regTHM_GPIO_THERMTRIP_CTRL 
 0x0005
+#define regTHM_GPIO_THERMTRIP_CTRL_BASE_IDX
 0
+#define regTHM_GPIO_PWM_CTRL   
 0x0006
+#define regTHM_GPIO_PWM_CTRL_BASE_IDX  
 0
+#define regTHM_GPIO_TACHIN_CTRL
 0x0007
+#define regTHM_GPIO_TACHIN_CTRL_BASE_IDX   
 0
+#define regTHM_GPIO_PUMPOUT_CTRL   
 0x0008
+#define regTHM_GPIO_PUMPOUT_CTRL_BASE_IDX  
 0
+#define regTHM_GPIO_PUMPIN_CTRL
 0x0009
+#define regTHM_GPIO_PUMPIN_CTRL_BASE_IDX   
 0
+#define regTHM_THERMAL_INT_ENA 
 0x000a
+#define regTHM_THERMAL_INT_ENA_BASE_IDX
 0
+#define regTHM_THERMAL_INT_CTRL
 0x000b
+#define regTHM_THERMAL_INT_CTRL_BASE_IDX   
 0
+#define regTHM_THERMAL_INT_STATUS  
 0x000c
+#define regTHM_THERMAL_INT_STATUS_BASE_IDX 
 0
+#d

[PATCH 2/2] drm/amd/amdgpu: use the default reset for ras recovery

[Kenneth Feng]

use the default reset for ras recovery

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index a037e8fba29f..f92b2c4f0d5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2437,6 +2437,7 @@ static void amdgpu_ras_do_recovery(struct work_struct 
*work)
struct amdgpu_device *adev = ras->adev;
struct list_head device_list, *device_list_handle =  NULL;
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
+   int save_reset_method = amdgpu_reset_method;
 
if (hive) {
atomic_set(>ras_recovery, 1);
@@ -2501,7 +2502,13 @@ static void amdgpu_ras_do_recovery(struct work_struct 
*work)
}
}
 
+   if (amdgpu_gpu_recovery == 2)
+   amdgpu_reset_method = -1;
+
amdgpu_device_gpu_recover(ras->adev, NULL, _context);
+
+   if (amdgpu_gpu_recovery == 2)
+   amdgpu_reset_method = save_reset_method;
}
atomic_set(>in_recovery, 0);
if (hive) {
-- 
2.34.1

[PATCH 1/2] drm/amd/amdgpu: customized the reset to skip soft recovery

[Kenneth Feng]

customized the reset to skip soft recovery

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index ea14f1c8f430..65c3a387fec7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -548,7 +548,7 @@ module_param_named(compute_multipipe, 
amdgpu_compute_multipipe, int, 0444);
  * DOC: gpu_recovery (int)
  * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default 
is -1 (auto, disabled except SRIOV).
  */
-MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 
= disable, -1 = auto)");
+MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 
= disable, -1 = auto, 2 = customized)");
 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index e4742b65032d..5c75993698a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -51,7 +51,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
drm_sched_job *s_job)
 
adev->job_hang = true;
 
-   if (amdgpu_gpu_recovery &&
+   if (amdgpu_gpu_recovery && amdgpu_gpu_recovery != 2 &&
amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) 
{
DRM_ERROR("ring %s timeout, but soft recovered\n",
  s_job->sched->name);
-- 
2.34.1

[PATCH] drm/amd/pm: fix the high voltage issue after unload

[Kenneth Feng]

fix the high voltage issue after unload on smu 13.0.10

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 26 ++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 27 +--
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  8 +-
 4 files changed, 48 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 12dc71a6b5db..1b9136bb7f62 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4138,18 +4138,22 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->ip_blocks[i].status.hw = true;
}
}
+   } else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == 
IP_VERSION(13, 0, 10) &&
+  !amdgpu_device_has_display_hardware(adev)) {
+   r = psp_gpu_reset(adev);
} else {
-   tmp = amdgpu_reset_method;
-   /* It should do a default reset when loading or 
reloading the driver,
-* regardless of the module parameter reset_method.
-*/
-   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
-   r = amdgpu_asic_reset(adev);
-   amdgpu_reset_method = tmp;
-   if (r) {
-   dev_err(adev->dev, "asic reset on init 
failed\n");
-   goto failed;
-   }
+   tmp = amdgpu_reset_method;
+   /* It should do a default reset when loading or 
reloading the driver,
+* regardless of the module parameter 
reset_method.
+*/
+   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
+   r = amdgpu_asic_reset(adev);
+   amdgpu_reset_method = tmp;
+   }
+
+   if (r) {
+ dev_err(adev->dev, "asic reset on init failed\n");
+ goto failed;
}
}
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 246b211b1e85..65333141b1c1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -735,7 +735,7 @@ static int smu_early_init(void *handle)
smu->adev = adev;
smu->pm_enabled = !!amdgpu_dpm;
smu->is_apu = false;
-   smu->smu_baco.state = SMU_BACO_STATE_EXIT;
+   smu->smu_baco.state = SMU_BACO_STATE_NONE;
smu->smu_baco.platform_support = false;
smu->user_dpm_profile.fan_mode = -1;
 
@@ -1966,10 +1966,25 @@ static int smu_smc_hw_cleanup(struct smu_context *smu)
return 0;
 }
 
+static int smu_reset_mp1_state(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+   int ret = 0;
+
+   if ((!adev->in_runpm) && (!adev->in_suspend) &&
+   (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 
0) ==
+   
IP_VERSION(13, 0, 10) &&
+   !amdgpu_device_has_display_hardware(adev))
+   ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
+
+   return ret;
+}
+
 static int smu_hw_fini(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = adev->powerplay.pp_handle;
+   int ret;
 
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
@@ -1987,7 +2002,15 @@ static int smu_hw_fini(void *handle)
 
adev->pm.dpm_enabled = false;
 
-   return smu_smc_hw_cleanup(smu);
+   ret = smu_smc_hw_cleanup(smu);
+   if (ret)
+   return ret;
+
+   ret = smu_reset_mp1_state(smu);
+   if (ret)
+   return ret;
+
+   return 0;
 }
 
 static void smu_late_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index a870bdd49a4e..1fa81575788c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -424,6 +424,7 @@ enum smu_reset_mode {
 enum smu_baco_state {
SMU_BACO_STATE_ENTER = 0,
SMU_BACO_STATE_EXIT,
+   SMU_BACO_STATE_NONE,
 };
 
 struct smu_baco_context {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 5a857cb999f5..f4df4cceb06f 100644
--- a/drivers/g

[PATCH] drm/amd/pm: denote S to the deep sleep clock

[Kenneth Feng]

denote S to the deep sleep clock for the clock output on smu 
v13.0.0/v13.0.7/v13.0.10

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 27 +--
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 27 +--
 2 files changed, 38 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 2e7518f4ae1a..fd33646970a4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -109,6 +109,7 @@
 #define PP_OD_FEATURE_FAN_MINIMUM_PWM  10
 
 #define LINK_SPEED_MAX 3
+#define SMU_13_0_0_DSCLK_THRESHOLD 100
 
 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] 
= {
MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,  
   1),
@@ -1269,20 +1270,30 @@ static int smu_v13_0_0_print_clk_levels(struct 
smu_context *smu,
 *   - level 0 -> min clock freq
 *   - level 1 -> max clock freq
 * And the current clock frequency can be any value 
between them.
-* So, if the current clock frequency is not at level 0 
or level 1,
-* we will fake it as three dpm levels:
+* So, if the current clock frequency is lower than 
level 0,
+* we will denote it to S:
+*   - level S -> current actual clock freq
 *   - level 0 -> min clock freq
-*   - level 1 -> current actual clock freq
-*   - level 2 -> max clock freq
+*   - level 1 -> max clock freq
 */
if ((single_dpm_table->dpm_levels[0].value != 
curr_freq) &&
-(single_dpm_table->dpm_levels[1].value != 
curr_freq)) {
+(single_dpm_table->dpm_levels[1].value != 
curr_freq) &&
+(curr_freq < SMU_13_0_0_DSCLK_THRESHOLD)) {
+   size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
+   curr_freq);
size += sysfs_emit_at(buf, size, "0: %uMhz\n",

single_dpm_table->dpm_levels[0].value);
-   size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
-   curr_freq);
-   size += sysfs_emit_at(buf, size, "2: %uMhz\n",
+   size += sysfs_emit_at(buf, size, "1: %uMhz\n",

single_dpm_table->dpm_levels[1].value);
+   } else if ((single_dpm_table->dpm_levels[0].value != 
curr_freq) &&
+   
(single_dpm_table->dpm_levels[1].value != curr_freq)) {
+   size += sysfs_emit_at(buf, size, "0: %uMhz 
%s\n",
+   
single_dpm_table->dpm_levels[0].value,
+   
single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
+   size += sysfs_emit_at(buf, size, "1: %uMhz 
*\n", curr_freq);
+   size += sysfs_emit_at(buf, size, "2: %uMhz 
%s\n",
+   
single_dpm_table->dpm_levels[1].value,
+   
single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
} else {
size += sysfs_emit_at(buf, size, "0: %uMhz 
%s\n",

single_dpm_table->dpm_levels[0].value,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 0ffdb58af74e..2ecebad7a9cb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -85,6 +85,7 @@
 #define PP_OD_FEATURE_FAN_MINIMUM_PWM  10
 
 #define LINK_SPEED_MAX 3
+#define SMU_13_0_7_DSCLK_THRESHOLD 100
 
 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] 
= {
MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,  
   1),
@@ -1258,20 +1259,30 @@ static int smu_v13_0_7_print_clk_levels(struct 
smu_context *smu,
 *   - level 0 -> min clock freq
  

[PATCH] drm/amd/pm: denote S to the actual clock

[Kenneth Feng]

denote S to the actual clock in smu v13.0.0/v13.0.7/v13.0.10

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 12 ++--
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 12 ++--
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 2e7518f4ae1a..63a930c4da01 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1270,18 +1270,18 @@ static int smu_v13_0_0_print_clk_levels(struct 
smu_context *smu,
 *   - level 1 -> max clock freq
 * And the current clock frequency can be any value 
between them.
 * So, if the current clock frequency is not at level 0 
or level 1,
-* we will fake it as three dpm levels:
+* we will denote it to S:
+*   - level S -> current actual clock freq
 *   - level 0 -> min clock freq
-*   - level 1 -> current actual clock freq
-*   - level 2 -> max clock freq
+*   - level 1 -> max clock freq
 */
if ((single_dpm_table->dpm_levels[0].value != 
curr_freq) &&
 (single_dpm_table->dpm_levels[1].value != 
curr_freq)) {
+   size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
+   curr_freq);
size += sysfs_emit_at(buf, size, "0: %uMhz\n",

single_dpm_table->dpm_levels[0].value);
-   size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
-   curr_freq);
-   size += sysfs_emit_at(buf, size, "2: %uMhz\n",
+   size += sysfs_emit_at(buf, size, "1: %uMhz\n",

single_dpm_table->dpm_levels[1].value);
} else {
size += sysfs_emit_at(buf, size, "0: %uMhz 
%s\n",
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 0ffdb58af74e..dbdb50173de7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1259,18 +1259,18 @@ static int smu_v13_0_7_print_clk_levels(struct 
smu_context *smu,
 *   - level 1 -> max clock freq
 * And the current clock frequency can be any value 
between them.
 * So, if the current clock frequency is not at level 0 
or level 1,
-* we will fake it as three dpm levels:
+* we will denote it to S:
+*   - level S -> current actual clock freq
 *   - level 0 -> min clock freq
-*   - level 1 -> current actual clock freq
-*   - level 2 -> max clock freq
+*   - level 1 -> max clock freq
 */
if ((single_dpm_table->dpm_levels[0].value != 
curr_freq) &&
 (single_dpm_table->dpm_levels[1].value != 
curr_freq)) {
+   size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
+   curr_freq);
size += sysfs_emit_at(buf, size, "0: %uMhz\n",

single_dpm_table->dpm_levels[0].value);
-   size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
-   curr_freq);
-   size += sysfs_emit_at(buf, size, "2: %uMhz\n",
+   size += sysfs_emit_at(buf, size, "1: %uMhz\n",

single_dpm_table->dpm_levels[1].value);
} else {
size += sysfs_emit_at(buf, size, "0: %uMhz 
%s\n",
-- 
2.34.1

[PATCH] drm/amd/pm: update the power cap setting

[Kenneth Feng]

update the power cap setting for smu_v13.0.0/smu_v13.0.7

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 54 ++-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 54 ++-
 2 files changed, 104 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 231122622a9c..e769adb8da2c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -2357,6 +2357,7 @@ static int smu_v13_0_0_get_power_limit(struct smu_context 
*smu,
PPTable_t *pptable = table_context->driver_pptable;
SkuTable_t *skutable = >SkuTable;
uint32_t power_limit, od_percent_upper, od_percent_lower;
+   uint32_t msg_limit = 
skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
 
if (smu_v13_0_get_current_power_limit(smu, _limit))
power_limit = smu->adev->pm.ac_power ?
@@ -2380,7 +2381,7 @@ static int smu_v13_0_0_get_power_limit(struct smu_context 
*smu,
od_percent_upper, od_percent_lower, 
power_limit);
 
if (max_power_limit) {
-   *max_power_limit = power_limit * (100 + od_percent_upper);
+   *max_power_limit = msg_limit * (100 + od_percent_upper);
*max_power_limit /= 100;
}
 
@@ -2960,6 +2961,55 @@ static bool smu_v13_0_0_wbrf_support_check(struct 
smu_context *smu)
}
 }
 
+static int smu_v13_0_0_set_power_limit(struct smu_context *smu,
+  enum smu_ppt_limit_type limit_type,
+  uint32_t limit)
+{
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
+   SkuTable_t *skutable = >SkuTable;
+   uint32_t msg_limit = 
skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
+   struct smu_table_context *table_context = >smu_table;
+   OverDriveTableExternal_t *od_table =
+   (OverDriveTableExternal_t *)table_context->overdrive_table;
+   int ret = 0;
+
+   if (limit_type != SMU_DEFAULT_PPT_LIMIT)
+   return -EINVAL;
+
+   if (limit <= msg_limit) {
+   if (smu->current_power_limit > msg_limit) {
+   od_table->OverDriveTable.Ppt = 0;
+   od_table->OverDriveTable.FeatureCtrlMask |= 1U << 
PP_OD_FEATURE_PPT_BIT;
+
+   ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
+   if (ret) {
+   dev_err(smu->adev->dev, "Failed to upload 
overdrive table!\n");
+   return ret;
+   }
+   }
+   return smu_v13_0_set_power_limit(smu, limit_type, limit);
+   } else if (smu->od_enabled) {
+   ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
+   if (ret)
+   return ret;
+
+   od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
+   od_table->OverDriveTable.FeatureCtrlMask |= 1U << 
PP_OD_FEATURE_PPT_BIT;
+
+   ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
+   if (ret) {
+ dev_err(smu->adev->dev, "Failed to upload overdrive 
table!\n");
+ return ret;
+   }
+
+   smu->current_power_limit = limit;
+   } else {
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
@@ -3014,7 +3064,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = 
{
.set_fan_control_mode = smu_v13_0_set_fan_control_mode,
.enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
.get_power_limit = smu_v13_0_0_get_power_limit,
-   .set_power_limit = smu_v13_0_set_power_limit,
+   .set_power_limit = smu_v13_0_0_set_power_limit,
.set_power_source = smu_v13_0_set_power_source,
.get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
.set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 59606a19e3d2..7c3e162e2d81 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -2321,6 +2321,7 @@ static int smu_v13_0_7_get_power_limit(struct smu_context 
*smu,
PPTable_t *pptable = table_context->driver_pptable;
SkuTable_t *skutable = >SkuTable;
uint32_t power_limit, od_percent_upper, od

[PATCH] drm/amd/pm: add power save mode workload for smu 13.0.10

[Kenneth Feng]

add power save mode workload for smu 13.0.10, so that in compute mode,
pmfw will add 35mv voltage margin since some applications requres higher
voltages.

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 23 +++
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index a24aa886c636..231122622a9c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -2545,16 +2545,19 @@ static int smu_v13_0_0_set_power_profile_mode(struct 
smu_context *smu,
 
workload_mask = 1 << workload_type;
 
-   /* Add optimizations for SMU13.0.0.  Reuse the power saving profile */
-   if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE &&
-   (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0)) 
&&
-   ((smu->adev->pm.fw_version == 0x004e6601) ||
-(smu->adev->pm.fw_version >= 0x004e7400))) {
-   workload_type = smu_cmn_to_asic_specific_index(smu,
-  
CMN2ASIC_MAPPING_WORKLOAD,
-  
PP_SMC_POWER_PROFILE_POWERSAVING);
-   if (workload_type >= 0)
-   workload_mask |= 1 << workload_type;
+   /* Add optimizations for SMU13.0.0/10.  Reuse the power saving profile 
*/
+   if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
+   if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == 
IP_VERSION(13, 0, 0) &&
+   ((smu->adev->pm.fw_version == 0x004e6601) ||
+   (smu->adev->pm.fw_version >= 0x004e7300))) ||
+   (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == 
IP_VERSION(13, 0, 10) &&
+smu->adev->pm.fw_version >= 0x00504500)) {
+   workload_type = smu_cmn_to_asic_specific_index(smu,
+   
   CMN2ASIC_MAPPING_WORKLOAD,
+   
   PP_SMC_POWER_PROFILE_POWERSAVING);
+   if (workload_type >= 0)
+   workload_mask |= 1 << workload_type;
+   }
}
 
return smu_cmn_send_smc_msg_with_param(smu,
-- 
2.34.1

[PATCH v2] drm/amd/pm: fix the high voltage and temperature issue

[Kenneth Feng]

fix the high voltage and temperature issue after the driver is unloaded on smu 
13.0.0,
smu 13.0.7 and smu 13.0.10
v2 - fix the code format and make sure it is used on the unload case only.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 25 ++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 33 +--
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  2 ++
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 13 
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 18 --
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 19 +--
 7 files changed, 96 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 31f8c3ead161..1ad0fc3f3861 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3986,13 +3986,23 @@ int amdgpu_device_init(struct amdgpu_device *adev,
}
}
} else {
-   tmp = amdgpu_reset_method;
-   /* It should do a default reset when loading or 
reloading the driver,
-* regardless of the module parameter reset_method.
-*/
-   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
-   r = amdgpu_asic_reset(adev);
-   amdgpu_reset_method = tmp;
+   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+   case IP_VERSION(13, 0, 0):
+   case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
+   r = psp_gpu_reset(adev);
+   break;
+   default:
+   tmp = amdgpu_reset_method;
+   /* It should do a default reset when loading or 
reloading the driver,
+* regardless of the module parameter 
reset_method.
+*/
+   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
+   r = amdgpu_asic_reset(adev);
+   amdgpu_reset_method = tmp;
+   break;
+   }
+
if (r) {
dev_err(adev->dev, "asic reset on init 
failed\n");
goto failed;
@@ -5945,6 +5955,7 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
return -ENOTSUPP;
 
ret = amdgpu_dpm_baco_exit(adev);
+
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7c3356d6da5e..2e82172ba250 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -733,7 +733,7 @@ static int smu_early_init(void *handle)
smu->adev = adev;
smu->pm_enabled = !!amdgpu_dpm;
smu->is_apu = false;
-   smu->smu_baco.state = SMU_BACO_STATE_EXIT;
+   smu->smu_baco.state = SMU_BACO_STATE_NONE;
smu->smu_baco.platform_support = false;
smu->user_dpm_profile.fan_mode = -1;
 
@@ -1740,10 +1740,31 @@ static int smu_smc_hw_cleanup(struct smu_context *smu)
return 0;
 }
 
+static int smu_reset_mp1_state(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+   int ret = 0;
+
+   if ((!adev->in_runpm) && (!adev->in_suspend) &&
+   (!amdgpu_in_reset(adev)))
+   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+ case IP_VERSION(13, 0, 0):
+ case IP_VERSION(13, 0, 7):
+ case IP_VERSION(13, 0, 10):
+   ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
+   break;
+ default:
+   break;
+   }
+
+   return ret;
+}
+
 static int smu_hw_fini(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = adev->powerplay.pp_handle;
+   int ret;
 
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
@@ -1761,7 +1782,15 @@ static int smu_hw_fini(void *handle)
 
adev->pm.dpm_enabled = false;
 
-   return smu_smc_hw_cleanup(smu);
+   ret = smu_smc_hw_cleanup(smu);
+   if (ret)
+   return ret;
+
+   ret = smu_reset_mp1_state(smu);
+   if (ret)
+   return ret;
+
+   return 0;
 }
 
 static void smu_late_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 1454eed76604

[PATCH v2] drm/amd/pm: fix the high voltage and temperature issue

[Kenneth Feng]

fix the high voltage and temperature issue after the driver is unloaded on smu 
13.0.0,
smu 13.0.7 and smu 13.0.10
v2 - fix the code format and make sure it is used on the unload case only.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 36 +++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 33 +++--
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  2 ++
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 13 +++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  8 -
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  |  8 -
 7 files changed, 90 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 31f8c3ead161..c5c892a8b3f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3986,13 +3986,23 @@ int amdgpu_device_init(struct amdgpu_device *adev,
}
}
} else {
-   tmp = amdgpu_reset_method;
-   /* It should do a default reset when loading or 
reloading the driver,
-* regardless of the module parameter reset_method.
-*/
-   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
-   r = amdgpu_asic_reset(adev);
-   amdgpu_reset_method = tmp;
+   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+   case IP_VERSION(13, 0, 0):
+   case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
+   r = psp_gpu_reset(adev);
+   break;
+   default:
+   tmp = amdgpu_reset_method;
+   /* It should do a default reset when loading or 
reloading the driver,
+* regardless of the module parameter 
reset_method.
+*/
+   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
+   r = amdgpu_asic_reset(adev);
+   amdgpu_reset_method = tmp;
+   break;
+   }
+
if (r) {
dev_err(adev->dev, "asic reset on init 
failed\n");
goto failed;
@@ -5945,6 +5955,18 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
return -ENOTSUPP;
 
ret = amdgpu_dpm_baco_exit(adev);
+
+   if (!ret)
+   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+   case IP_VERSION(13, 0, 0):
+   case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
+   adev->gfx.is_poweron = false;
+   break;
+   default:
+   break;
+   }
+
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7c3356d6da5e..2e82172ba250 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -733,7 +733,7 @@ static int smu_early_init(void *handle)
smu->adev = adev;
smu->pm_enabled = !!amdgpu_dpm;
smu->is_apu = false;
-   smu->smu_baco.state = SMU_BACO_STATE_EXIT;
+   smu->smu_baco.state = SMU_BACO_STATE_NONE;
smu->smu_baco.platform_support = false;
smu->user_dpm_profile.fan_mode = -1;
 
@@ -1740,10 +1740,31 @@ static int smu_smc_hw_cleanup(struct smu_context *smu)
return 0;
 }
 
+static int smu_reset_mp1_state(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+   int ret = 0;
+
+   if ((!adev->in_runpm) && (!adev->in_suspend) &&
+   (!amdgpu_in_reset(adev)))
+   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+ case IP_VERSION(13, 0, 0):
+ case IP_VERSION(13, 0, 7):
+ case IP_VERSION(13, 0, 10):
+   ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
+   break;
+ default:
+   break;
+   }
+
+   return ret;
+}
+
 static int smu_hw_fini(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = adev->powerplay.pp_handle;
+   int ret;
 
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
@@ -1761,7 +1782,15 @@ static int smu_hw_fini(void *handle)
 
adev->pm.dpm_enabled = false;
 
-   return smu

[PATCH] drm/amd/amdgpu: avoid to disable gfxhub interrupt when driver is unloaded

[Kenneth Feng]

avoid to disable gfxhub interrupt when driver is unloaded on gmc 11

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 80ca2c05b0b8..8e36a8395464 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -73,7 +73,8 @@ gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 * fini/suspend, so the overall state doesn't
 * change over the course of suspend/resume.
 */
-   if (!adev->in_s0ix)
+   if (!adev->in_s0ix && (adev->in_runpm || adev->in_suspend ||
+  
amdgpu_in_reset(adev)))
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), 
false);
break;
case AMDGPU_IRQ_STATE_ENABLE:
-- 
2.34.1

[PATCH] drm/amd/pm: fix the high voltage and temperature issue on smu 13

[Kenneth Feng]

fix the high voltage and temperature issue after the driver is unloaded on smu 
13.0.0,
smu 13.0.7 and smu 13.0.10

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 36 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c|  4 +--
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 27 --
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  2 ++
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 13 +++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  8 -
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  |  8 -
 8 files changed, 86 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 31f8c3ead161..c5c892a8b3f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3986,13 +3986,23 @@ int amdgpu_device_init(struct amdgpu_device *adev,
}
}
} else {
-   tmp = amdgpu_reset_method;
-   /* It should do a default reset when loading or 
reloading the driver,
-* regardless of the module parameter reset_method.
-*/
-   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
-   r = amdgpu_asic_reset(adev);
-   amdgpu_reset_method = tmp;
+   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+   case IP_VERSION(13, 0, 0):
+   case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
+   r = psp_gpu_reset(adev);
+   break;
+   default:
+   tmp = amdgpu_reset_method;
+   /* It should do a default reset when loading or 
reloading the driver,
+* regardless of the module parameter 
reset_method.
+*/
+   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
+   r = amdgpu_asic_reset(adev);
+   amdgpu_reset_method = tmp;
+   break;
+   }
+
if (r) {
dev_err(adev->dev, "asic reset on init 
failed\n");
goto failed;
@@ -5945,6 +5955,18 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
return -ENOTSUPP;
 
ret = amdgpu_dpm_baco_exit(adev);
+
+   if (!ret)
+   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+   case IP_VERSION(13, 0, 0):
+   case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
+   adev->gfx.is_poweron = false;
+   break;
+   default:
+   break;
+   }
+
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 80ca2c05b0b8..3ad38e42773b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -73,7 +73,7 @@ gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 * fini/suspend, so the overall state doesn't
 * change over the course of suspend/resume.
 */
-   if (!adev->in_s0ix)
+   if (!adev->in_s0ix && adev->gfx.is_poweron)
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), 
false);
break;
case AMDGPU_IRQ_STATE_ENABLE:
@@ -85,7 +85,7 @@ gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 * fini/suspend, so the overall state doesn't
 * change over the course of suspend/resume.
 */
-   if (!adev->in_s0ix)
+   if (!adev->in_s0ix && adev->gfx.is_poweron)
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), 
true);
break;
default:
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7c3356d6da5e..30e5f7161737 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -733,7 +733,7 @@ static int smu_early_init(void *handle)
smu->adev = adev;
smu->pm_enabled = !!amdgpu_dpm;
smu->is_apu = false;
-   smu->smu_baco.state = SMU_BACO_STATE_EXIT;
+   smu->smu_baco.state = SMU_BACO_STATE_NONE;
smu->smu_baco.platform_support = false;
smu->user_dpm_profile.fan_mode = -1;
 
@@ -1740,10 +1740,25 @@ static int smu_smc

[PATCH] drm/amd/pm: workaround for the wrong ac power detection on smu 13.0.0

[Kenneth Feng]

workaround for the wrong ac power detection on smu 13.0.0

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c   | 3 +--
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 0232adb95df3..fd1798fd716e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1021,8 +1021,7 @@ static int smu_v13_0_process_pending_interrupt(struct 
smu_context *smu)
 {
int ret = 0;
 
-   if (smu->dc_controlled_by_gpio &&
-   smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
+   if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
ret = smu_v13_0_allow_ih_interrupt(smu);
 
return ret;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 3903a47669e4..128468355375 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -2664,7 +2664,6 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = 
{
.enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
.get_power_limit = smu_v13_0_0_get_power_limit,
.set_power_limit = smu_v13_0_set_power_limit,
-   .set_power_source = smu_v13_0_set_power_source,
.get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
.set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
.run_btc = smu_v13_0_run_btc,
-- 
2.34.1

[PATCH] drm/amd/pm: allow the user to force BACO on smu v13.0.0/7

[Kenneth Feng]

allow the user to force BACO on smu v13.0.0/7

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c   | 2 +-
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 ++-
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 3 ++-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 895cda8e6934..52e9c7611013 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2263,7 +2263,7 @@ int smu_v13_0_baco_set_state(struct smu_context *smu,
if (state == SMU_BACO_STATE_ENTER) {
ret = smu_cmn_send_smc_msg_with_param(smu,
  SMU_MSG_EnterBaco,
- smu_baco->maco_support ?
+ (smu_baco->maco_support 
&& amdgpu_runtime_pm != 1) ?
  BACO_SEQ_BAMACO : 
BACO_SEQ_BACO,
  NULL);
} else {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index a5857acee641..12ccc12657d7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -2211,7 +2211,8 @@ static int smu_v13_0_0_baco_enter(struct smu_context *smu)
 
if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
return smu_v13_0_baco_set_armd3_sequence(smu,
-   smu_baco->maco_support ? BACO_SEQ_BAMACO : 
BACO_SEQ_BACO);
+   (smu_baco->maco_support && amdgpu_runtime_pm != 
1) ?
+   BACO_SEQ_BAMACO : BACO_SEQ_BACO);
else
return smu_v13_0_baco_enter(smu);
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 93b3e8fa8238..f0bcc7995983 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -2139,7 +2139,8 @@ static int smu_v13_0_7_baco_enter(struct smu_context *smu)
 
if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
return smu_v13_0_baco_set_armd3_sequence(smu,
-   smu_baco->maco_support ? BACO_SEQ_BAMACO : 
BACO_SEQ_BACO);
+   (smu_baco->maco_support && amdgpu_runtime_pm != 
1) ?
+   BACO_SEQ_BAMACO : BACO_SEQ_BACO);
else
return smu_v13_0_baco_enter(smu);
 }
-- 
2.34.1

[PATCH] drm/amd/pm: add unique_id for gc 11.0.3

[Kenneth Feng]

drm/amd/pm: add unique_id for gc 11.0.3

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 5aed023f7402..c69701da94ea 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2076,6 +2076,7 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
+   case IP_VERSION(11, 0, 3):
*states = ATTR_STATE_SUPPORTED;
break;
default:
-- 
2.34.1

[PATCH v2] drm/amd/pm: disallow the fan setting if there is no fan on smu 13.0.0

[Kenneth Feng]

drm/amd/pm: disallow the fan setting if there is no fan on smu 13.0.0
V2: depend on pm.no_fan to check

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index fddcd834bcec..0fb6be11a0cc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -331,6 +331,7 @@ static int smu_v13_0_0_check_powerplay_table(struct 
smu_context *smu)
struct smu_13_0_0_powerplay_table *powerplay_table =
table_context->power_play_table;
struct smu_baco_context *smu_baco = >smu_baco;
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
 #if 0
PPTable_t *pptable = smu->smu_table.driver_pptable;
const OverDriveLimits_t * const overdrive_upperlimits =
@@ -371,6 +372,9 @@ static int smu_v13_0_0_check_powerplay_table(struct 
smu_context *smu)
table_context->thermal_controller_type =
powerplay_table->thermal_controller_type;
 
+   smu->adev->pm.no_fan =
+   !(pptable->SkuTable.FeaturesToRun[0] & (1 << 
FEATURE_FAN_CONTROL_BIT));
+
return 0;
 }
 
-- 
2.34.1

[PATCH] drm/amd/pm: disallow the fan setting if there is no fan on smu13

[Kenneth Feng]

disallow the fan setting if there is no fan on smu13

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 9b62b45ebb7f..09ef0a7e7679 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1131,7 +1131,9 @@ smu_v13_0_display_clock_voltage_request(struct 
smu_context *smu,
 
 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
 {
-   if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+   if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+   return AMD_FAN_CTRL_NONE;
+   else if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
return AMD_FAN_CTRL_MANUAL;
else
return AMD_FAN_CTRL_AUTO;
@@ -1143,7 +1145,7 @@ smu_v13_0_auto_fan_control(struct smu_context *smu, bool 
auto_fan_control)
int ret = 0;
 
if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
-   return 0;
+   return -EINVAL;
 
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, 
auto_fan_control);
if (ret)
@@ -1204,7 +1206,8 @@ smu_v13_0_set_fan_control_mode(struct smu_context *smu,
 
switch (mode) {
case AMD_FAN_CTRL_NONE:
-   ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
+   if (smu_cmn_feature_is_supported(smu, 
SMU_FEATURE_FAN_CONTROL_BIT))
+   ret = -EINVAL;
break;
case AMD_FAN_CTRL_MANUAL:
ret = smu_v13_0_auto_fan_control(smu, 0);
-- 
2.34.1

[PATCH] drm/amd/pm: correct the pcie width for smu 13.0.0

[Kenneth Feng]

correct the pcie width value in pp_dpm_pcie for smu 13.0.0

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 232274423f9e..4bdbd3910e1f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1140,7 +1140,6 @@ static int smu_v13_0_0_print_clk_levels(struct 
smu_context *smu,
(OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
struct smu_13_0_dpm_table *single_dpm_table;
struct smu_13_0_pcie_table *pcie_table;
-   const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
uint32_t gen_speed, lane_width;
int i, curr_freq, size = 0;
int32_t min_value, max_value;
@@ -1256,7 +1255,7 @@ static int smu_v13_0_0_print_clk_levels(struct 
smu_context *smu,
(pcie_table->pcie_lane[i] == 6) ? "x16" 
: "",
pcie_table->clk_freq[i],
(gen_speed == 
DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
-   (lane_width == 
DECODE_LANE_WIDTH(link_width[pcie_table->pcie_lane[i]])) ?
+   (lane_width == 
DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
"*" : "");
break;
 
-- 
2.34.1

[PATCH] drm/amd/pm: add abnormal fan detection for smu 13.0.0

[Kenneth Feng]

add abnormal fan detection for smu 13.0.0

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index a6083957ae51..124287cbbff8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1710,6 +1710,7 @@ static int 
smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
range->mem_emergency_max = 
(pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
+   range->software_shutdown_temp_offset = 
pptable->SkuTable.FanAbnormalTempLimitOffset;
 
return 0;
 }
-- 
2.34.1

[PATCH v2] drm/amd/pm: workaround for compute workload type on some skus

[Kenneth Feng]

On smu 13.0.0, the compute workload type cannot be set on all the skus
due to some other problems. This workaround is to make sure compute workload 
type
can also run on some specific skus.

v2: keep the variable consistent

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 33 +--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index e2265f50bacc..5e9e507a710e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -2179,10 +2179,39 @@ static int smu_v13_0_0_set_power_profile_mode(struct 
smu_context *smu,
}
}
 
-   /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
-   workload_type = smu_cmn_to_asic_specific_index(smu,
+   if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE &&
+   (((smu->adev->pdev->device == 0x744C) && 
(smu->adev->pdev->revision == 0xC8)) ||
+   ((smu->adev->pdev->device == 0x744C) && 
(smu->adev->pdev->revision == 0xCC {
+   ret = smu_cmn_update_table(smu,
+  SMU_TABLE_ACTIVITY_MONITOR_COEFF,
+  WORKLOAD_PPLIB_COMPUTE_BIT,
+  (void *)(_monitor_external),
+  false);
+   if (ret) {
+   dev_err(smu->adev->dev, "[%s] Failed to get activity 
monitor!", __func__);
+   return ret;
+   }
+
+   ret = smu_cmn_update_table(smu,
+  SMU_TABLE_ACTIVITY_MONITOR_COEFF,
+  WORKLOAD_PPLIB_CUSTOM_BIT,
+  (void *)(_monitor_external),
+  true);
+   if (ret) {
+   dev_err(smu->adev->dev, "[%s] Failed to set activity 
monitor!", __func__);
+   return ret;
+   }
+
+   workload_type = smu_cmn_to_asic_specific_index(smu,
+  
CMN2ASIC_MAPPING_WORKLOAD,
+  
PP_SMC_POWER_PROFILE_CUSTOM);
+   } else {
+   /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+   workload_type = smu_cmn_to_asic_specific_index(smu,
   
CMN2ASIC_MAPPING_WORKLOAD,
   smu->power_profile_mode);
+   }
+
if (workload_type < 0)
return -EINVAL;
 
-- 
2.34.1

[PATCH] drm/amd/pm: workaround for compute workload type on some skus

[Kenneth Feng]

On smu 13.0.0, the compute workload type cannot be set on all the skus
due to some other problems. This workaround is to make sure compute workload 
type
can also run on some specific skus.

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 26 +++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index e2265f50bacc..6e8acd021ee6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -2179,6 +2179,32 @@ static int smu_v13_0_0_set_power_profile_mode(struct 
smu_context *smu,
}
}
 
+   if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE &&
+   (((smu->adev->pdev->device == 0x744C) && 
(smu->adev->pdev->revision == 0xC8)) ||
+   ((smu->adev->pdev->device == 0x744C) && 
(smu->adev->pdev->revision == 0xCC {
+   ret = smu_cmn_update_table(smu,
+  SMU_TABLE_ACTIVITY_MONITOR_COEFF,
+  WORKLOAD_PPLIB_COMPUTE_BIT,
+  (void *)(_monitor_external),
+  false);
+   if (ret) {
+   dev_err(smu->adev->dev, "[%s] Failed to get activity 
monitor!", __func__);
+   return ret;
+   }
+
+   ret = smu_cmn_update_table(smu,
+  SMU_TABLE_ACTIVITY_MONITOR_COEFF,
+  WORKLOAD_PPLIB_CUSTOM_BIT,
+  (void *)(_monitor_external),
+  true);
+   if (ret) {
+   dev_err(smu->adev->dev, "[%s] Failed to set activity 
monitor!", __func__);
+   return ret;
+   }
+
+   smu->power_profile_mode = PP_SMC_POWER_PROFILE_CUSTOM;
+   }
+
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
workload_type = smu_cmn_to_asic_specific_index(smu,
   
CMN2ASIC_MAPPING_WORKLOAD,
-- 
2.34.1

[PATCH] drm/amd/pm: update smu-driver if header for smu 13.0.0 and smu 13.0.10

[Kenneth Feng]

update smu-driver if header for smu 13.0.0 and smu 13.0.10

Signed-off-by: Kenneth Feng 
Change-Id: I540aaa99fac2216f2d1a28fd79c68dd77a495f8b
---
 .../inc/pmfw_if/smu13_driver_if_v13_0_0.h | 33 ++-
 1 file changed, 25 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
index fe995651c6f5..ba56bc676310 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
@@ -24,10 +24,10 @@
 #ifndef SMU13_DRIVER_IF_V13_0_0_H
 #define SMU13_DRIVER_IF_V13_0_0_H
 
-#define SMU13_0_0_DRIVER_IF_VERSION 0x32
+#define SMU13_0_0_DRIVER_IF_VERSION 0x3D
 
 //Increment this version if SkuTable_t or BoardTable_t change
-#define PPTABLE_VERSION 0x26
+#define PPTABLE_VERSION 0x2B
 
 #define NUM_GFXCLK_DPM_LEVELS16
 #define NUM_SOCCLK_DPM_LEVELS8
@@ -96,7 +96,7 @@
 #define FEATURE_ATHUB_MMHUB_PG_BIT48
 #define FEATURE_SOC_PCC_BIT   49
 #define FEATURE_EDC_PWRBRK_BIT50
-#define FEATURE_SPARE_51_BIT  51
+#define FEATURE_BOMXCO_SVI3_PROG_BIT  51
 #define FEATURE_SPARE_52_BIT  52
 #define FEATURE_SPARE_53_BIT  53
 #define FEATURE_SPARE_54_BIT  54
@@ -312,6 +312,7 @@ typedef enum {
I2C_CONTROLLER_PROTOCOL_VR_IR35217,
I2C_CONTROLLER_PROTOCOL_TMP_MAX31875,
I2C_CONTROLLER_PROTOCOL_INA3221,
+   I2C_CONTROLLER_PROTOCOL_TMP_MAX6604,
I2C_CONTROLLER_PROTOCOL_COUNT,
 } I2cControllerProtocol_e;
 
@@ -570,6 +571,7 @@ typedef enum {
 } POWER_SOURCE_e;
 
 typedef enum {
+  MEM_VENDOR_PLACEHOLDER0,
   MEM_VENDOR_SAMSUNG,
   MEM_VENDOR_INFINEON,
   MEM_VENDOR_ELPIDA,
@@ -579,7 +581,6 @@ typedef enum {
   MEM_VENDOR_MOSEL,
   MEM_VENDOR_WINBOND,
   MEM_VENDOR_ESMT,
-  MEM_VENDOR_PLACEHOLDER0,
   MEM_VENDOR_PLACEHOLDER1,
   MEM_VENDOR_PLACEHOLDER2,
   MEM_VENDOR_PLACEHOLDER3,
@@ -808,6 +809,9 @@ typedef enum {
 
 #define INVALID_BOARD_GPIO 0xFF
 
+#define MARKETING_BASE_CLOCKS 0
+#define MARKETING_GAME_CLOCKS 1
+#define MARKETING_BOOST_CLOCKS2
 
 typedef struct {
   //PLL 0
@@ -1098,10 +1102,15 @@ typedef struct {
   uint16_tDcsExitHysteresis;//The min amount of time power credit 
accumulator should have a value > 0 before SMU exits the DCS throttling phase.
   uint16_tDcsTimeout;   //This is the amount of time SMU FW 
waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism 
of throttling GFXCLK to Fmin.
 
+  uint8_t FoptEnabled;
+  uint8_t DcsSpare2[3];
+  uint32_tDcsFoptM; //Tuning paramters to shift Fopt 
calculation, used in T19 and Navi32
+  uint32_tDcsFoptB; //Tuning paramters to shift Fopt 
calculation, used in T19 and Navi32
 
-  uint32_tDcsSpare[16];
+  uint32_tDcsSpare[11];
 
   // UCLK section
+  uint16_t ShadowFreqTableUclk [NUM_UCLK_DPM_LEVELS]; // In MHz
   uint8_t  UseStrobeModeOptimizations; //Set to indicate that FW should 
use strobe mode optimizations
   uint8_t  PaddingMem[3];
 
@@ -1247,8 +1256,13 @@ typedef struct {
   QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT];
   QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT];
 
+  uint16_t TemperatureLimit_Hynix; // In degrees Celsius. Memory temperature 
limit associated with Hynix
+  uint16_t TemperatureLimit_Micron; // In degrees Celsius. Memory temperature 
limit associated with Micron
+  uint16_t TemperatureFwCtfLimit_Hynix;
+  uint16_t TemperatureFwCtfLimit_Micron;
+
   // SECTION: Sku Reserved
-  uint32_t Spare[43];
+  uint32_t Spare[41];
 
   // Padding for MMHUB - do not modify this
   uint32_t MmHubPadding[8];
@@ -1320,8 +1334,9 @@ typedef struct {
   // UCLK Spread Spectrum
   uint8_t  UclkSpreadPercent[MEM_VENDOR_COUNT];
 
+  uint8_t  GfxclkSpreadEnable;
+
   // FCLK Spread Spectrum
-  uint8_t  FclkSpreadPadding;
   uint8_t  FclkSpreadPercent;   // Q4.4
   uint16_t FclkSpreadFreq;  // kHz
 
@@ -1446,6 +1461,8 @@ typedef struct {
 
 
   uint8_t ThrottlingPercentage[THROTTLER_COUNT];
+  uint8_t VmaxThrottlingPercentage;
+  uint8_t Padding1[3];
 
   //metrics for D3hot entry/exit and driver ARM msgs
   uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
@@ -1465,7 +1482,7 @@ typedef struct {
 
 typedef struct {
   SmuMetrics_t SmuMetrics;
-  uint32_t Spare[30];
+  uint32_t Spare[29];
 
   // Padding - ignore
   uint32_t MmHubPadding[8]; // SMU internal use
-- 
2.34.1

[PATCH] drm/amd/pm: re-enable ac/dc on smu_v13_0_0/10

[Kenneth Feng]

re-enable ac/dc on smu_v13_0_0/10

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 7c906ab3ddd2..923a9fb3c887 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -147,6 +147,7 @@ static struct cmn2asic_msg_mapping 
smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,  
 0),
MSG_MAP(AllowGpo,   PPSMC_MSG_SetGpoAllow,  
 0),
MSG_MAP(AllowIHHostInterrupt,   PPSMC_MSG_AllowIHHostInterrupt, 
  0),
+   MSG_MAP(ReenableAcDcInterrupt,  
PPSMC_MSG_ReenableAcDcInterrupt,   0),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
-- 
2.25.1

[PATCH] drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10

[Kenneth Feng]

implement mode2 reset on smu_v13_0_10

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |   7 +
 drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c | 303 ++
 drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.h |  32 ++
 .../gpu/drm/amd/include/kgd_pp_interface.h|   1 +
 drivers/gpu/drm/amd/pm/amdgpu_dpm.c   |  18 ++
 drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |   1 +
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  18 ++
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |   1 +
 .../pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h  |   1 +
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |   3 +-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  27 ++
 12 files changed, 412 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 24d8a03091b9..a7a0e385298d 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -80,7 +80,7 @@ amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o 
vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o 
mxgpu_nv.o \
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o 
soc21.o \
-   sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o 
lsdma_v6_0.o
+   sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o 
hdp_v5_2.o lsdma_v6_0.o
 
 # add DF block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index f778466bb9db..6437ead87e5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -24,6 +24,7 @@
 #include "amdgpu_reset.h"
 #include "aldebaran.h"
 #include "sienna_cichlid.h"
+#include "smu_v13_0_10.h"
 
 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
 struct amdgpu_reset_handler *handler)
@@ -44,6 +45,9 @@ int amdgpu_reset_init(struct amdgpu_device *adev)
case IP_VERSION(11, 0, 7):
ret = sienna_cichlid_reset_init(adev);
break;
+   case IP_VERSION(13, 0, 10):
+   ret = smu_v13_0_10_reset_init(adev);
+   break;
default:
break;
}
@@ -62,6 +66,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev)
case IP_VERSION(11, 0, 7):
ret = sienna_cichlid_reset_fini(adev);
break;
+   case IP_VERSION(13, 0, 10):
+   ret = smu_v13_0_10_reset_fini(adev);
+   break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c 
b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
new file mode 100644
index ..ae29620b1ea4
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "smu_v13_0_10.h"
+#include "amdgpu_reset.h"
+#include "amdgpu_dpm.h"
+#include "amdgpu_job.h"
+#include "amdgpu_ring.h"
+#include "amdgpu_ras.h"
+#include "amdgpu_psp.h"
+
+static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control 
*reset_ctl)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
+   if (adev->pm.fw_version >= 0x00502005 && !amdgpu_sriov_vf(adev))
+   return true;
+
+   return false;
+}
+
+static struct amdgpu_reset_handler *
+smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
+   

[PATCH] drm/amd/amdgpu: enable athub cg on gc 11.0.3

[Kenneth Feng]

enable athub cg on gc 11.0.3

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 2ea0b9142868..0615fdbf0a64 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -677,7 +677,9 @@ static int soc21_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_REPEATER_FGCG |
-   AMD_CG_SUPPORT_GFX_MGCG;
+   AMD_CG_SUPPORT_GFX_MGCG |
+   AMD_CG_SUPPORT_ATHUB_MGCG |
+   AMD_CG_SUPPORT_ATHUB_LS;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG;
-- 
2.25.1

[PATCH] drm/amd/pm: skip disabling all smu features on smu_v13_0_10 in suspend

[Kenneth Feng]

skip disabling all smu features on smu_v13_0_10 in suspend

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 4fe75dd2b329..320cfce1fef5 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1449,6 +1449,7 @@ static int smu_disable_dpms(struct smu_context *smu)
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
return 0;
default:
break;
-- 
2.25.1

[PATCH v2] drm/amd/pm: enable mode1 reset on smu_v13_0_10

[Kenneth Feng]

enable mode1 reset and prioritize debug port on msu_v13_0_10
as a more reliable message processing

v2 - move mode1 reset callback to smu_v13_0_0_ppt.c

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c|  1 +
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  4 ++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 53 ++-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 18 +++
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h|  3 ++
 5 files changed, 77 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 1d4013ed0d10..b258e9aa0558 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -322,6 +322,7 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
return AMD_RESET_METHOD_MODE1;
case IP_VERSION(13, 0, 4):
return AMD_RESET_METHOD_MODE2;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index e2fa3b066b96..1bc26e93a83c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -568,6 +568,10 @@ struct smu_context
u32 param_reg;
u32 msg_reg;
u32 resp_reg;
+
+   u32 debug_param_reg;
+   u32 debug_msg_reg;
+   u32 debug_resp_reg;
 };
 
 struct i2c_adapter;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 29529328152d..588527310188 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -70,6 +70,26 @@
 
 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE  0x4000
 
+#define mmMP1_SMN_C2PMSG_66
0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_82
0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_90
0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_75
0x028b
+#define mmMP1_SMN_C2PMSG_75_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_53
0x0275
+#define mmMP1_SMN_C2PMSG_53_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_54
0x0276
+#define mmMP1_SMN_C2PMSG_54_BASE_IDX   
0
+
+#define DEBUGSMC_MSG_Mode1Reset2
+
 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] 
= {
MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,  
   1),
MSG_MAP(GetSmuVersion,  PPSMC_MSG_GetSmuVersion,
   1),
@@ -1763,6 +1783,35 @@ static int smu_v13_0_0_set_df_cstate(struct smu_context 
*smu,
   NULL);
 }
 
+static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
+{
+   int ret = 0;
+   struct amdgpu_device *adev = smu->adev;
+
+   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10))
+   ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);
+   else
+   ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
+
+   if (!ret)
+   msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
+
+   return ret;
+}
+
+static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+
+   smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+   smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+   smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+
+   smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
+   smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
+   smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
+}
+
 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_0_set_default

[PATCH] drm/amd/amdgpu: temporary workaround to skip ras error for gc_v11_0_3

[Kenneth Feng]

temporary workaround to skip ras error for gc_v11_0_3 until IFWI release later

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 84a76c36d9a7..dac236a6b3b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4688,10 +4688,10 @@ static int gfx_v11_0_ras_late_init(void *handle)
 
ret = amdgpu_ras_feature_enable(adev, gfx_common_if, true);
if (ret)
-   dev_err(adev->dev, "Failed to enable gfx11 ras feature\n");
+   dev_warn(adev->dev, "Failed to enable gfx11 ras feature\n");
 
kfree(gfx_common_if);
-   return ret;
+   return 0;
 }
 
 static int gfx_v11_0_late_init(void *handle)
-- 
2.25.1

[PATCH] drm/amd/amdgpu: skip ras late init if it is not supported

[Kenneth Feng]

skip ras late init on gc_11_0_3 if it is not supported,
in order to prevent the hardware init exception.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 84a76c36d9a7..afe1fadc1e9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4707,7 +4707,7 @@ static int gfx_v11_0_late_init(void *handle)
if (r)
return r;
 
-   if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) {
+   if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3) && 
adev->ras_enabled) {
r = gfx_v11_0_ras_late_init(handle);
if (r)
return r;
-- 
2.25.1

[PATCH] drm/amd/pm: allow gfxoff on gc_11_0_3

[Kenneth Feng]

allow gfxoff on gc_11_0_3

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index e3842dc100d6..5eefba2948a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5051,6 +5051,7 @@ static int gfx_v11_0_set_powergating_state(void *handle,
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 2):
+   case IP_VERSION(11, 0, 3):
amdgpu_gfx_off_ctrl(adev, enable);
break;
case IP_VERSION(11, 0, 1):
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index b7b59e04a44f..fff4d8307bb6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -840,6 +840,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool 
enable)
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 7):
case IP_VERSION(13, 0, 8):
+   case IP_VERSION(13, 0, 10):
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
if (enable)
-- 
2.25.1

[PATCH 2/2] drm/amd/pm: enable thermal alart on smu_v13_0_10

[Kenneth Feng]

enable thermal alart on smu_v13_0_10

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 3d436e7f6e95..4fe75dd2b329 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1312,12 +1312,10 @@ static int smu_smc_hw_setup(struct smu_context *smu)
return ret;
}
 
-   if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 10)) {
-   ret = smu_enable_thermal_alert(smu);
-   if (ret) {
-   dev_err(adev->dev, "Failed to enable thermal alert!\n");
-   return ret;
-   }
+   ret = smu_enable_thermal_alert(smu);
+   if (ret) {
+ dev_err(adev->dev, "Failed to enable thermal alert!\n");
+ return ret;
}
 
ret = smu_notify_display_change(smu);
-- 
2.25.1

[PATCH 1/2] drm/amd/pm: update driver-if header for smu_v13_0_10

[Kenneth Feng]

update driver-if header for smu_v13_0_10 and merge with smu_v13_0_0

Signed-off-by: Kenneth Feng 
---
 .../inc/pmfw_if/smu13_driver_if_v13_0_0.h | 87 +++
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  3 +-
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  6 +-
 3 files changed, 72 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
index 063f4a737605..9a0d899fd73f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
@@ -25,7 +25,7 @@
 #define SMU13_DRIVER_IF_V13_0_0_H
 
 //Increment this version if SkuTable_t or BoardTable_t change
-#define PPTABLE_VERSION 0x24
+#define PPTABLE_VERSION 0x26
 
 #define NUM_GFXCLK_DPM_LEVELS16
 #define NUM_SOCCLK_DPM_LEVELS8
@@ -109,6 +109,22 @@
 #define FEATURE_SPARE_63_BIT  63
 #define NUM_FEATURES  64
 
+#define ALLOWED_FEATURE_CTRL_DEFAULT 0xULL
+#define ALLOWED_FEATURE_CTRL_SCPM(1 << FEATURE_DPM_GFXCLK_BIT) | \
+ (1 << 
FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
+ (1 << FEATURE_DPM_UCLK_BIT) | \
+ (1 << FEATURE_DPM_FCLK_BIT) | \
+ (1 << FEATURE_DPM_SOCCLK_BIT) | \
+ (1 << FEATURE_DPM_MP0CLK_BIT) | \
+ (1 << FEATURE_DPM_LINK_BIT) | \
+ (1 << FEATURE_DPM_DCN_BIT) | \
+ (1 << FEATURE_DS_GFXCLK_BIT) | \
+ (1 << FEATURE_DS_SOCCLK_BIT) | \
+ (1 << FEATURE_DS_FCLK_BIT) | \
+ (1 << FEATURE_DS_LCLK_BIT) | \
+ (1 << FEATURE_DS_DCFCLK_BIT) | \
+ (1 << FEATURE_DS_UCLK_BIT)
+
 //For use with feature control messages
 typedef enum {
   FEATURE_PWR_ALL,
@@ -133,6 +149,7 @@ typedef enum {
 #define DEBUG_OVERRIDE_DISABLE_DFLL0x0200
 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE  0x0400
 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE0x0800
+#define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE   0x1000
 
 // VR Mapping Bit Defines
 #define VR_MAPPING_VR_SELECT_MASK  0x01
@@ -269,7 +286,7 @@ typedef enum {
   I2C_CONTROLLER_NAME_LIQUID0,
   I2C_CONTROLLER_NAME_LIQUID1,
   I2C_CONTROLLER_NAME_PLX,
-  I2C_CONTROLLER_NAME_OTHER,
+  I2C_CONTROLLER_NAME_FAN_INTAKE,
   I2C_CONTROLLER_NAME_COUNT,
 } I2cControllerName_e;
 
@@ -282,6 +299,7 @@ typedef enum {
   I2C_CONTROLLER_THROTTLER_LIQUID0,
   I2C_CONTROLLER_THROTTLER_LIQUID1,
   I2C_CONTROLLER_THROTTLER_PLX,
+  I2C_CONTROLLER_THROTTLER_FAN_INTAKE,
   I2C_CONTROLLER_THROTTLER_INA3221,
   I2C_CONTROLLER_THROTTLER_COUNT,
 } I2cControllerThrottler_e;
@@ -289,7 +307,7 @@ typedef enum {
 typedef enum {
   I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
   I2C_CONTROLLER_PROTOCOL_VR_IR35217,
-  I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
+  I2C_CONTROLLER_PROTOCOL_TMP_MAX31875,
   I2C_CONTROLLER_PROTOCOL_INA3221,
   I2C_CONTROLLER_PROTOCOL_COUNT,
 } I2cControllerProtocol_e;
@@ -658,13 +676,20 @@ typedef struct {
 
 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1
 
+typedef enum {
+  FAN_MODE_AUTO = 0,
+  FAN_MODE_MANUAL_LINEAR,
+} FanMode_e;
 
 typedef struct {
   uint32_t FeatureCtrlMask;
 
   //Voltage control
   int16_t
VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS];
-  uint16_t   reserved[2];
+  uint16_t   VddGfxVmax; // in mV
+
+  uint8_tIdlePwrSavingFeaturesCtrl;
+  uint8_tRuntimePwrSavingFeaturesCtrl;
 
   //Frequency changes
   int16_tGfxclkFmin;   // MHz
@@ -674,7 +699,7 @@ typedef struct {
 
   //PPT
   int16_tPpt; // %
-  int16_treserved1;
+  int16_tTdc;
 
   //Fan control
   uint8_tFanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
@@ -701,16 +726,19 @@ typedef struct {
   uint32_t FeatureCtrlMask;
 
   int16_t VoltageOffsetPerZoneBoundary;
-  uint16_t   reserved[2];
+  uint16_t   VddGfxVmax; // in mV
+
+  uint8_tIdlePwrSavingFeaturesCtrl;
+  uint8_tRuntimePwrSavingFeaturesCtrl;
 
-  uint16_t   GfxclkFmin;   // MHz
-  uint16_t   GfxclkFmax;   // MHz
+  int16_t   GfxclkFmin;   // MHz
+  int16_t   GfxclkFmax;   // MHz
   uint16_t   UclkFmin;

[PATCH] drm/amd/pm: improve BAMACO code for smu_v13_0

[Kenneth Feng]

For runtime pm case:
1. prompt in dmesg for BAMACO feature test
2. set BACO by defatul and the user can select BAMACO

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  7 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   | 10 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   |  3 ++-
 drivers/gpu/drm/amd/amdgpu/soc21.c|  1 +
 .../gpu/drm/amd/include/kgd_pp_interface.h|  1 +
 drivers/gpu/drm/amd/pm/amdgpu_dpm.c   | 23 +++
 drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |  2 ++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 16 +
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  1 +
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 17 +-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  1 +
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  |  1 +
 14 files changed, 83 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1372e2b47541..104bb62db830 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -598,6 +598,7 @@ struct amdgpu_asic_funcs {
uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
/* device supports BACO */
bool (*supports_baco)(struct amdgpu_device *adev);
+   bool (*supports_maco)(struct amdgpu_device *adev);
/* pre asic_init quirks */
void (*pre_asic_init)(struct amdgpu_device *adev);
/* enter/exit umd stable pstate */
@@ -1289,6 +1290,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define amdgpu_asic_need_reset_on_init(adev) 
(adev)->asic_funcs->need_reset_on_init((adev))
 #define amdgpu_asic_get_pcie_replay_count(adev) 
((adev)->asic_funcs->get_pcie_replay_count((adev)))
 #define amdgpu_asic_supports_baco(adev) 
(adev)->asic_funcs->supports_baco((adev))
+#define amdgpu_asic_supports_maco(adev) 
(adev)->asic_funcs->supports_maco((adev))
 #define amdgpu_asic_pre_asic_init(adev) 
(adev)->asic_funcs->pre_asic_init((adev))
 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
((adev)->asic_funcs->update_umd_stable_pstate ? 
(adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
@@ -1329,6 +1331,7 @@ bool amdgpu_device_supports_px(struct drm_device *dev);
 bool amdgpu_device_supports_boco(struct drm_device *dev);
 bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
 bool amdgpu_device_supports_baco(struct drm_device *dev);
+bool amdgpu_device_supports_maco(struct drm_device *dev);
 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
  struct amdgpu_device *peer_adev);
 int amdgpu_device_baco_enter(struct drm_device *dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ebb722811dcf..a034295fae71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -272,6 +272,13 @@ bool amdgpu_device_supports_baco(struct drm_device *dev)
return amdgpu_asic_supports_baco(adev);
 }
 
+bool amdgpu_device_supports_maco(struct drm_device *dev)
+{
+   struct amdgpu_device *adev = drm_to_adev(dev);
+
+   return amdgpu_asic_supports_maco(adev);
+}
+
 /**
  * amdgpu_device_supports_smart_shift - Is the device dGPU with
  * smart shift support
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 95bce47943bb..4c022785ded1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -171,13 +171,19 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, 
unsigned long flags)
adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
break;
default:
-   /* enable BACO as runpm mode on CI+ */
-   adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
+   /* enable BACO/BAMACO as runpm mode on CI+ */
+   if (amdgpu_runtime_pm == 2 && 
amdgpu_device_supports_maco(dev))
+   adev->pm.rpm_mode = AMDGPU_RUNPM_BAMACO;
+   else
+   adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
break;
}
 
if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
dev_info(adev->dev, "Using BACO for runtime pm\n");
+
+   if (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)
+   dev_info(adev->dev, "Using BAMACO for runtime pm\n");
}
 
/* Call ACPI methods: require modeset init
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index

[PATCH] drm/amd/pm: add mode1 support on smu_v13_0_7

[Kenneth Feng]

add mode1 support since it's missing on smu_v13_0_7

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index d78375d9a141..1016d1c216d8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1567,6 +1567,16 @@ static int smu_v13_0_7_set_mp1_state(struct smu_context 
*smu,
return ret;
 }
 
+static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+
+   /* SRIOV does not support SMU mode1 reset */
+   if (amdgpu_sriov_vf(adev))
+   return false;
+
+   return true;
+}
 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
@@ -1626,6 +1636,8 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = 
{
.baco_set_state = smu_v13_0_baco_set_state,
.baco_enter = smu_v13_0_baco_enter,
.baco_exit = smu_v13_0_baco_exit,
+   .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
+   .mode1_reset = smu_v13_0_mode1_reset,
.set_mp1_state = smu_v13_0_7_set_mp1_state,
 };
 
-- 
2.25.1

[PATCH] drm/amd/amdgpu: add ih cg and hdp sd on smu_v13_0_7

[Kenneth Feng]

add ih cg and hdp sd on smu_v13_0_7

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index bbbf760f8ad2..686e17770c63 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -575,7 +575,9 @@ static int soc21_common_early_init(void *handle)
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG |
AMD_CG_SUPPORT_ATHUB_MGCG |
-   AMD_CG_SUPPORT_ATHUB_LS;
+   AMD_CG_SUPPORT_ATHUB_LS |
+   AMD_CG_SUPPORT_IH_CG |
+   AMD_CG_SUPPORT_HDP_SD;
adev->pg_flags =
AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
@@ -690,6 +692,7 @@ static int soc21_common_set_clockgating_state(void *handle,
 
switch (adev->ip_versions[NBIO_HWIP][0]) {
case IP_VERSION(4, 3, 0):
+   case IP_VERSION(4, 3, 1):
adev->nbio.funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
adev->nbio.funcs->update_medium_grain_light_sleep(adev,
-- 
2.25.1

[PATCH] drm/amd/pm: skip pptable override for smu_v13_0_7

[Kenneth Feng]

skip pptable override for smu_v13_0_7 secure boards only.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 0370482dd52b..daf4dc9811af 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -212,6 +212,9 @@ int smu_v13_0_init_pptable_microcode(struct smu_context 
*smu)
if (!adev->scpm_enabled)
return 0;
 
+   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7))
+   return 0;
+
/* override pptable_id from driver parameter */
if (amdgpu_smu_pptable_id >= 0) {
pptable_id = amdgpu_smu_pptable_id;
@@ -219,13 +222,6 @@ int smu_v13_0_init_pptable_microcode(struct smu_context 
*smu)
} else {
pptable_id = smu->smu_table.boot_values.pp_table_id;
 
-   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
-   pptable_id == 3667)
-   pptable_id = 36671;
-
-   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
-   pptable_id == 3688)
-   pptable_id = 36881;
/*
 * Temporary solution for SMU V13.0.0 with SCPM enabled:
 *   - use 36831 signed pptable when pp_table_id is 3683
-- 
2.25.1

[PATCH] drm/amd/pm: update driver if header for smu_13_0_7

[Kenneth Feng]

update driver if header for smu_13_0_7

Signed-off-by: Kenneth Feng 
---
 .../inc/pmfw_if/smu13_driver_if_v13_0_7.h | 24 ---
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  2 +-
 2 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
index 132da684e379..25c08f963f49 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
@@ -25,10 +25,10 @@
 
 // *** IMPORTANT ***
 // PMFW TEAM: Always increment the interface version on any change to this file
-#define SMU13_DRIVER_IF_VERSION  0x2A
+#define SMU13_DRIVER_IF_VERSION  0x2C
 
 //Increment this version if SkuTable_t or BoardTable_t change
-#define PPTABLE_VERSION 0x1E
+#define PPTABLE_VERSION 0x20
 
 #define NUM_GFXCLK_DPM_LEVELS16
 #define NUM_SOCCLK_DPM_LEVELS8
@@ -152,6 +152,7 @@ typedef enum {
 #define DEBUG_OVERRIDE_DISABLE_DFLL0x0200
 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE  0x0400
 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE0x0800
+#define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE   0x1000
 
 // VR Mapping Bit Defines
 #define VR_MAPPING_VR_SELECT_MASK  0x01
@@ -1014,8 +1015,8 @@ typedef struct {
   uint16_tVmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT];   //In mV(Q2) 
End-of-life Vset to be used at hot.
   uint16_tVmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT];  //In mV(Q2) 
End-of-life Vset to be used at cold.
   uint16_tVmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT];  //In mV(Q2) 
Worst-case aging margin
-  uint16_tVmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT];   //In mV(Q2) 
Platform offset apply to T0 Hot
-  uint16_tVmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT];  //In mV(Q2) 
Platform offset apply to T0 Cold
+  uint16_tSpare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT];   //In 
mV(Q2) Platform offset apply to T0 Hot
+  uint16_tSpare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT];  //In 
mV(Q2) Platform offset apply to T0 Cold
 
   //This is a fixed/minimum VMIN aging degradation offset which is applied at 
T0. This reflects the minimum amount of aging already accounted for.
   uint16_tVcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT];
@@ -1081,11 +1082,15 @@ typedef struct {
 
   uint16_tGfxclkFreqGfxUlv; // in MHz
   uint8_t GfxIdlePadding2[2];
-
-  uint32_tGfxoffSpare[16];
+  uint32_tGfxOffEntryHysteresis; //For RLC to count after it enters 
CGCG, and before triggers GFXOFF entry
+  uint32_tGfxoffSpare[15];
 
   // GFX GPO
-  uint32_tGfxGpoSpare[16];
+  float   DfllBtcMasterScalerM;
+  int32_t DfllBtcMasterScalerB;
+  float   DfllBtcSlaveScalerM;
+  int32_t DfllBtcSlaveScalerB;
+  uint32_tGfxGpoSpare[12];
 
   // GFX DCS
 
@@ -1326,8 +1331,11 @@ typedef struct {
   uint32_tPostVoltageSetBacoDelay; // in microseconds. Amount of time FW 
will wait after power good is established or PSI0 command is issued
   uint32_tBacoEntryDelay; // in milliseconds. Amount of time FW will wait 
to trigger BACO entry after receiving entry notification from OS
 
+  uint8_t FuseWritePowerMuxPresent;
+  uint8_t FuseWritePadding[3];
+
   // SECTION: Board Reserved
-  uint32_t BoardSpare[64];
+  uint32_t BoardSpare[63];
 
   // SECTION: Structure Padding
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 038a8956de5b..3e5838346f02 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -31,7 +31,7 @@
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2A
-#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2A
+#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C
 
 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
 
-- 
2.25.1

[PATCH] drm/amd/pm: enable gfx ulv and gpo on smu_v13_0_7

[Kenneth Feng]

enable gfx ulv and gpo on smu_v13_0_7

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 6f0548714566..16eea2de8a2d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -251,6 +251,7 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
*smu,
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
+   *(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
}
 
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
@@ -271,6 +272,9 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
*smu,
if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 
+   if (adev->pm.pp_feature & PP_ULV_MASK)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
+
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
-- 
2.25.1

[PATCH] drm/amd/pm: enable mode1 reset for smu_v13_0_7

[Kenneth Feng]

enable mode1 reset for smu_v13_0_7 since it's missing.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c   | 1 +
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 765c3543ad18..00e9b7089feb 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -320,6 +320,7 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
 
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
+   case IP_VERSION(13, 0, 7):
return AMD_RESET_METHOD_MODE1;
case IP_VERSION(13, 0, 4):
return AMD_RESET_METHOD_MODE2;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 6259a85bc818..6f0548714566 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -118,6 +118,7 @@ static struct cmn2asic_msg_mapping 
smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize,   
   0),
MSG_MAP(AllowGfxOff,PPSMC_MSG_AllowGfxOff,  
   0),
MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff,   
   0),
+   MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset,  
0),
MSG_MAP(PrepareMp1ForUnload,PPSMC_MSG_PrepareMp1ForUnload,  
   0),
 };
 
-- 
2.25.1

[PATCH] drm/amd/pm: ac/dc change for smu_v13_0

[Kenneth Feng]

fixed the issue: gpu runs in dc mode but it is expected to be in ac mode.
this causes the lower performance on smu_v13_0

Signed-off-by: Kenneth Feng 
---
 .../pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h  |  9 --
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |  1 +
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 28 ++-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  |  2 ++
 4 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h
index 3f2d0a9e4745..6aaefca9b595 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h
@@ -128,7 +128,12 @@
 #define PPSMC_MSG_EnableAudioStutterWA   0x44
 #define PPSMC_MSG_PowerUpUmsch   0x45
 #define PPSMC_MSG_PowerDownUmsch 0x46
-#define PPSMC_Message_Count  0x4C
-
+#define PPSMC_MSG_SetDcsArch 0x47
+#define PPSMC_MSG_TriggerVFFLR   0x48
+#define PPSMC_MSG_SetNumBadMemoryPagesRetired0x49
+#define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4A
+#define PPSMC_MSG_SetPriorityDeltaGain   0x4B
+#define PPSMC_MSG_AllowIHHostInterrupt   0x4C
+#define PPSMC_Message_Count  0x4D
 
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index a1cb8e73e171..19084a4fcb2b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -74,6 +74,7 @@
__SMU_DUMMY_MAP(OverDriveSetPercentage),   \
__SMU_DUMMY_MAP(SetMinDeepSleepDcefclk),   \
__SMU_DUMMY_MAP(ReenableAcDcInterrupt),\
+   __SMU_DUMMY_MAP(AllowIHHostInterrupt),\
__SMU_DUMMY_MAP(NotifyPowerSource),\
__SMU_DUMMY_MAP(SetUclkFastSwitch),\
__SMU_DUMMY_MAP(SetUclkDownHyst),  \
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 0e59ab2192bf..0328bc12ca21 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1084,9 +1084,35 @@ int smu_v13_0_set_power_limit(struct smu_context *smu,
return 0;
 }
 
+static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
+{
+   return smu_cmn_send_smc_msg(smu,
+   SMU_MSG_AllowIHHostInterrupt,
+   NULL);
+}
+
+static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
+{
+   int ret = 0;
+
+   if (smu->dc_controlled_by_gpio &&
+   smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
+   ret = smu_v13_0_allow_ih_interrupt(smu);
+
+   return ret;
+}
+
 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
 {
-   return amdgpu_irq_get(smu->adev, >irq_source, 0);
+   int ret = 0;
+
+   if (smu->smu_table.thermal_controller_type) {
+   ret = amdgpu_irq_get(smu->adev, >irq_source, 0);
+   if (ret)
+   return ret;
+   }
+
+   return smu_v13_0_process_pending_interrupt(smu);
 }
 
 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 193222fdd1c4..6259a85bc818 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -111,6 +111,8 @@ static struct cmn2asic_msg_mapping 
smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(PowerDownJpeg,  PPSMC_MSG_PowerDownJpeg,
   0),
MSG_MAP(GetDcModeMaxDpmFreq,PPSMC_MSG_GetDcModeMaxDpmFreq,  
   1),
MSG_MAP(OverridePcieParameters, 
PPSMC_MSG_OverridePcieParameters,  0),
+   MSG_MAP(ReenableAcDcInterrupt,  
PPSMC_MSG_ReenableAcDcInterrupt,   0),
+   MSG_MAP(AllowIHHostInterrupt,   PPSMC_MSG_AllowIHHostInterrupt, 
  0),
MSG_MAP(DramLogSetDramAddrHigh, 
PPSMC_MSG_DramLogSetDramAddrHigh,  0),
MSG_MAP(DramLogSetDramAddrLow,  
PPSMC_MSG_DramLogSetDramAddrLow,   0),
MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize,   
   0),
-- 
2.25.1

[PATCH 5/5] drm/amd/pm: support BAMACO reset on smu_v13_0_7

[Kenneth Feng]

support BAMACO reset on smu_v13_0_7, take BAMACO as a subset of BACO
for the low latency, and it only happens on specific platforms.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 57 ++-
 2 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 6d51e4340aad..b81c657c7386 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -432,6 +432,7 @@ struct smu_baco_context
 {
uint32_t state;
bool platform_support;
+   bool maco_support;
 };
 
 struct smu_freq_info {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index b635c2b4f81c..369e84fef5a6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -303,6 +303,8 @@ static int smu_v13_0_7_check_powerplay_table(struct 
smu_context *smu)
struct smu_13_0_7_powerplay_table *powerplay_table =
table_context->power_play_table;
struct smu_baco_context *smu_baco = >smu_baco;
+   PPTable_t *smc_pptable = table_context->driver_pptable;
+   BoardTable_t *BoardTable = _pptable->BoardTable;
 
if (powerplay_table->platform_caps & 
SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
smu->dc_controlled_by_gpio = true;
@@ -311,6 +313,9 @@ static int smu_v13_0_7_check_powerplay_table(struct 
smu_context *smu)
powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
smu_baco->platform_support = true;
 
+   if (smu_baco->platform_support && (BoardTable->HsrEnabled || 
BoardTable->VddqOffEnabled))
+   smu_baco->maco_support = true;
+
table_context->thermal_controller_type =
powerplay_table->thermal_controller_type;
 
@@ -1537,6 +1542,54 @@ static int smu_v13_0_7_set_power_profile_mode(struct 
smu_context *smu, long *inp
return ret;
 }
 
+static int smu_v13_0_7_baco_set_state(struct smu_context *smu,
+enum smu_baco_state state)
+{
+   struct smu_baco_context *smu_baco = >smu_baco;
+   struct amdgpu_device *adev = smu->adev;
+   bool is_maco_support = smu_baco->maco_support;
+   int ret = 0;
+
+   if (smu_v13_0_baco_get_state(smu) == state)
+   return 0;
+
+   if (state == SMU_BACO_STATE_ENTER) {
+   ret = smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_EnterBaco,
+ (is_maco_support ? 2 : 0),
+ NULL);
+   } else {
+   ret = smu_cmn_send_smc_msg(smu,
+  SMU_MSG_ExitBaco,
+  NULL);
+   if (ret)
+   return ret;
+
+   /* clear vbios scratch 6 and 7 for coming asic reinit */
+   WREG32(adev->bios_scratch_reg_offset + 6, 0);
+   WREG32(adev->bios_scratch_reg_offset + 7, 0);
+   }
+
+   if (!ret)
+   smu_baco->state = state;
+
+   return ret;
+}
+
+static int smu_v13_0_7_baco_enter(struct smu_context *smu)
+{
+   int ret = 0;
+
+   ret = smu_v13_0_7_baco_set_state(smu,
+  SMU_BACO_STATE_ENTER);
+   if (ret)
+   return ret;
+
+   msleep(10);
+
+   return ret;
+}
+
 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
@@ -1591,8 +1644,8 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = 
{
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.baco_is_support = smu_v13_0_baco_is_support,
.baco_get_state = smu_v13_0_baco_get_state,
-   .baco_set_state = smu_v13_0_baco_set_state,
-   .baco_enter = smu_v13_0_baco_enter,
+   .baco_set_state = smu_v13_0_7_baco_set_state,
+   .baco_enter = smu_v13_0_7_baco_enter,
.baco_exit = smu_v13_0_baco_exit,
 };
 
-- 
2.25.1

[PATCH 4/5] drm/amd/pm: enable gfxoff on smu_v13_0_7

[Kenneth Feng]

enable gfxoff on smu_v13_0_7

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index dc614befcdf5..b635c2b4f81c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -249,6 +249,9 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
*smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
}
 
+   if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
+
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
-- 
2.25.1

[PATCH 3/5] drm/amd/pm: update the driver if header for smu_v13_0_7

[Kenneth Feng]

update the driver if header for smu_v13_0_7

Signed-off-by: Kenneth Feng 
---
 .../inc/pmfw_if/smu13_driver_if_v13_0_7.h | 62 +--
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  2 +-
 2 files changed, 45 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
index d99b4b47d49d..132da684e379 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
@@ -25,10 +25,10 @@
 
 // *** IMPORTANT ***
 // PMFW TEAM: Always increment the interface version on any change to this file
-#define SMU13_DRIVER_IF_VERSION  0x28
+#define SMU13_DRIVER_IF_VERSION  0x2A
 
 //Increment this version if SkuTable_t or BoardTable_t change
-#define PPTABLE_VERSION 0x1D
+#define PPTABLE_VERSION 0x1E
 
 #define NUM_GFXCLK_DPM_LEVELS16
 #define NUM_SOCCLK_DPM_LEVELS8
@@ -112,6 +112,22 @@
 #define FEATURE_SPARE_63_BIT  63
 #define NUM_FEATURES  64
 
+#define ALLOWED_FEATURE_CTRL_DEFAULT 0xULL
+#define ALLOWED_FEATURE_CTRL_SCPM(1 << FEATURE_DPM_GFXCLK_BIT) | \
+ (1 << 
FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
+ (1 << FEATURE_DPM_UCLK_BIT) | \
+ (1 << FEATURE_DPM_FCLK_BIT) | \
+ (1 << FEATURE_DPM_SOCCLK_BIT) | \
+ (1 << FEATURE_DPM_MP0CLK_BIT) | \
+ (1 << FEATURE_DPM_LINK_BIT) | \
+ (1 << FEATURE_DPM_DCN_BIT) | \
+ (1 << FEATURE_DS_GFXCLK_BIT) | \
+ (1 << FEATURE_DS_SOCCLK_BIT) | \
+ (1 << FEATURE_DS_FCLK_BIT) | \
+ (1 << FEATURE_DS_LCLK_BIT) | \
+ (1 << FEATURE_DS_DCFCLK_BIT) | \
+ (1 << FEATURE_DS_UCLK_BIT)
+
 //For use with feature control messages
 typedef enum {
   FEATURE_PWR_ALL,
@@ -662,7 +678,7 @@ typedef struct {
 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1
 
 
-#define PP_OD_FEATURE_VF_CURVE_BIT  0
+#define PP_OD_FEATURE_GFX_VF_CURVE_BIT  0
 #define PP_OD_FEATURE_VMAX_BIT  1
 #define PP_OD_FEATURE_PPT_BIT   2
 #define PP_OD_FEATURE_FAN_CURVE_BIT 3
@@ -671,6 +687,8 @@ typedef struct {
 #define PP_OD_FEATURE_TDC_BIT  6
 #define PP_OD_FEATURE_GFXCLK_BIT  7
 #define PP_OD_FEATURE_UCLK_BIT  8
+#define PP_OD_FEATURE_ZERO_FAN_BIT  9
+#define PP_OD_FEATURE_TEMPERATURE_BIT 10
 
 typedef enum {
   PP_OD_POWER_FEATURE_ALWAYS_ENABLED,
@@ -689,8 +707,8 @@ typedef struct {
   uint8_tRuntimePwrSavingFeaturesCtrl;
 
   //Frequency changes
-  uint16_t   GfxclkFmin;   // MHz
-  uint16_t   GfxclkFmax;   // MHz
+  int16_t   GfxclkFmin;   // MHz
+  int16_t   GfxclkFmax;   // MHz
   uint16_t   UclkFmin; // MHz
   uint16_t   UclkFmax; // MHz
 
@@ -701,17 +719,17 @@ typedef struct {
   //Fan control
   uint8_tFanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
   uint8_tFanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
-  uint16_t   FanMaximumRpm;
   uint16_t   FanMinimumPwm;
-  uint16_t   FanAcousticLimitRpm;
+  uint16_t   AcousticTargetRpmThreshold;
+  uint16_t   AcousticLimitRpmThreshold;
   uint16_t   FanTargetTemperature; // Degree Celcius
   uint8_tFanZeroRpmEnable;
   uint8_tFanZeroRpmStopTemp;
   uint8_tFanMode;
-  uint8_tPadding[1];
-
+  uint8_tMaxOpTemp;
+  uint8_tPadding[4];
 
-  uint32_t   Spare[13];
+  uint32_t   Spare[12];
   uint32_t   MmHubPadding[8]; // SMU internal use. Adding here 
instead of external as a workaround
 } OverDriveTable_t;
 
@@ -740,17 +758,17 @@ typedef struct {
 
   uint8_tFanLinearPwmPoints;
   uint8_tFanLinearTempPoints;
-  uint16_t   FanMaximumRpm;
   uint16_t   FanMinimumPwm;
-  uint16_t   FanAcousticLimitRpm;
+  uint16_t   AcousticTargetRpmThreshold;
+  uint16_t   AcousticLimitRpmThreshold;
   uint16_t   FanTargetTemperature; // Degree Celcius
   uint8_tFanZeroRpmEnable;
   uint8_tFanZeroRpmStopTemp;
   uint8_tFanMode;
-  uint8_tPadding[1];
+  uin

[PATCH 2/5] drm/amd/pm: enable BACO on smu_v13_0_7

[Kenneth Feng]

enable BACO on smu_v13_0_7

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 1 +
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index fb04d82f66e6..f57710790b8c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1456,6 +1456,7 @@ static int smu_disable_dpms(struct smu_context *smu)
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 5):
case IP_VERSION(11, 0, 9):
+   case IP_VERSION(13, 0, 7):
return 0;
default:
break;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 7da42cae5d6e..dc614befcdf5 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -97,6 +97,7 @@ static struct cmn2asic_msg_mapping 
smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(UseDefaultPPTable,  PPSMC_MSG_UseDefaultPPTable,
   0),
MSG_MAP(RunDcBtc,   PPSMC_MSG_RunDcBtc, 
   0),
MSG_MAP(EnterBaco,  PPSMC_MSG_EnterBaco,
   0),
+   MSG_MAP(ExitBaco,   PPSMC_MSG_ExitBaco, 
   0),
MSG_MAP(SetSoftMinByFreq,   PPSMC_MSG_SetSoftMinByFreq, 
   1),
MSG_MAP(SetSoftMaxByFreq,   PPSMC_MSG_SetSoftMaxByFreq, 
   1),
MSG_MAP(SetHardMinByFreq,   PPSMC_MSG_SetHardMinByFreq, 
   1),
@@ -281,6 +282,7 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
*smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
 
if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
@@ -1584,6 +1586,11 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs 
= {
.set_tool_table_location = smu_v13_0_set_tool_table_location,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
+   .baco_is_support = smu_v13_0_baco_is_support,
+   .baco_get_state = smu_v13_0_baco_get_state,
+   .baco_set_state = smu_v13_0_baco_set_state,
+   .baco_enter = smu_v13_0_baco_enter,
+   .baco_exit = smu_v13_0_baco_exit,
 };
 
 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
-- 
2.25.1

[PATCH 1/5] drm/amd/pm: add interface to deallocate power_context for smu_v13_0_7

[Kenneth Feng]

add interface to deallocate power_context for smu_v13_0_7

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index bdea7bca3805..7da42cae5d6e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1541,6 +1541,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = 
{
.load_microcode = smu_v13_0_load_microcode,
.init_smc_tables = smu_v13_0_7_init_smc_tables,
.init_power = smu_v13_0_init_power,
+   .fini_power = smu_v13_0_fini_power,
.check_fw_status = smu_v13_0_7_check_fw_status,
.setup_pptable = smu_v13_0_7_setup_pptable,
.check_fw_version = smu_v13_0_check_fw_version,
-- 
2.25.1

[PATCH] drm/amd/amdgpu: align the cg and pg settings

[Kenneth Feng]

align the cg and pg settings between gc_v11_0 and gc_v11_2

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 5566ddbfd188..26fda7a170da 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -546,12 +546,17 @@ static int soc21_common_early_init(void *handle)
adev->cg_flags =
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
+   AMD_CG_SUPPORT_REPEATER_FGCG |
AMD_CG_SUPPORT_VCN_MGCG |
-   AMD_CG_SUPPORT_JPEG_MGCG;
+   AMD_CG_SUPPORT_JPEG_MGCG |
+   AMD_CG_SUPPORT_ATHUB_MGCG |
+   AMD_CG_SUPPORT_ATHUB_LS;
adev->pg_flags =
AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
-   AMD_PG_SUPPORT_JPEG;
+   AMD_PG_SUPPORT_JPEG |
+   AMD_PG_SUPPORT_ATHUB |
+   AMD_PG_SUPPORT_MMHUB;
adev->external_rev_id = adev->rev_id + 0x10;
break;
default:
-- 
2.25.1

[PATCH] drm/amd/pm: fix the issue of uploading powerplay table

[Kenneth Feng]

fix the issue of uploading powerplay table due to the dependancy of rlc.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 3ab1ce4d3419..04863a797115 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1404,7 +1404,7 @@ static int smu_disable_dpms(struct smu_context *smu)
 */
if (smu->uploading_custom_pp_table &&
(adev->asic_type >= CHIP_NAVI10) &&
-   (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
+   (adev->asic_type <= CHIP_BEIGE_GOBY))
return smu_disable_all_features_with_exception(smu,
   true,
   
SMU_FEATURE_COUNT);
-- 
2.17.1

[PATCH 2/2] drm/amd/pm: change the workload type for some cards

[Kenneth Feng]

change the workload type for some cards as it is needed.

Signed-off-by: Kenneth Feng 
---
 .../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index a9bd8265b508..f3cd397cb56b 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -5127,6 +5127,13 @@ static int vega10_get_power_profile_mode(struct pp_hwmgr 
*hwmgr, char *buf)
return size;
 }
 
+static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr)
+{
+   struct amdgpu_device *adev = hwmgr->adev;
+
+   return (adev->pdev->device == 0x6860);
+}
+
 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, 
uint32_t size)
 {
struct vega10_hwmgr *data = hwmgr->backend;
@@ -5163,9 +5170,15 @@ static int vega10_set_power_profile_mode(struct pp_hwmgr 
*hwmgr, long *input, ui
}
 
 out:
-   smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
+   if (vega10_get_power_profile_mode_quirks(hwmgr))
+   smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_SetWorkloadMask,
1 << power_profile_mode,
NULL);
+   else
+   smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_SetWorkloadMask,
+   (!power_profile_mode) ? 0 : 1 
<< (power_profile_mode - 1),
+   NULL);
+
hwmgr->power_profile_mode = power_profile_mode;
 
return 0;
-- 
2.17.1

[PATCH 1/2] Revert "drm/amd/pm: fix workload mismatch on vega10"

[Kenneth Feng]

This reverts commit 0979d43259e13846d86ba17e451e17fec185d240.
Revert this because it does not apply to all the cards.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index 621a49f86b0c..a9bd8265b508 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -5164,7 +5164,7 @@ static int vega10_set_power_profile_mode(struct pp_hwmgr 
*hwmgr, long *input, ui
 
 out:
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
-   (!power_profile_mode) ? 0 : 1 
<< (power_profile_mode - 1),
+   1 << power_profile_mode,
NULL);
hwmgr->power_profile_mode = power_profile_mode;
 
-- 
2.17.1

[PATCH] drm/amd/pm: bug fix for the runtime pm BACO

[Kenneth Feng]

In some systems only MACO is supported. This is to fix the prolbem
that runtime pm is enabled but BACO is not supported. MACO will be
handled seperately.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 90e40aacb8f6..261ef8ca862e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -353,8 +353,7 @@ static void sienna_cichlid_check_bxco_support(struct 
smu_context *smu)
struct amdgpu_device *adev = smu->adev;
uint32_t val;
 
-   if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
-   powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) {
+   if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
smu_baco->platform_support =
(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
-- 
2.17.1

[PATCH] drm/amd/pm: enable ASPM by default

[Kenneth Feng]

enable ASPM by default

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 82a380be8368..2fcfd893edc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -598,7 +598,7 @@ static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 
 static void nv_program_aspm(struct amdgpu_device *adev)
 {
-   if (amdgpu_aspm != 1)
+   if (!amdgpu_aspm)
return;
 
if (!(adev->flags & AMD_IS_APU) &&
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 49ece2a7f9f0..4b660b2d1c22 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -817,7 +817,7 @@ static void soc15_pcie_gen3_enable(struct amdgpu_device 
*adev)
 
 static void soc15_program_aspm(struct amdgpu_device *adev)
 {
-   if (amdgpu_aspm != 1)
+   if (!amdgpu_aspm)
return;
 
if (!(adev->flags & AMD_IS_APU) &&
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 735ebbd1148f..3d21c0799037 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1136,7 +1136,7 @@ static void vi_program_aspm(struct amdgpu_device *adev)
bool bL1SS = false;
bool bClkReqSupport = true;
 
-   if (amdgpu_aspm != 1)
+   if (!amdgpu_aspm)
return;
 
if (adev->flags & AMD_IS_APU ||
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index d2fd44b903ca..270b2b0b8e8a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -302,7 +302,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
if (smu->dc_controlled_by_gpio)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 
-   if (amdgpu_aspm == 1)
+   if (amdgpu_aspm)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 
return 0;
-- 
2.17.1

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[PATCH] drm/amd/amdgpu: add cgls

[Kenneth Feng]

enable cgls to improve the runtime power efficiency.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 0142f6760ad2..9c4f232e81c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1065,6 +1065,7 @@ static int nv_common_early_init(void *handle)
case CHIP_SIENNA_CICHLID:
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
+   AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_VCN_MGCG |
@@ -1088,6 +1089,7 @@ static int nv_common_early_init(void *handle)
case CHIP_NAVY_FLOUNDER:
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
+   AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG |
@@ -1130,6 +1132,7 @@ static int nv_common_early_init(void *handle)
case CHIP_DIMGREY_CAVEFISH:
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
+   AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG |
-- 
2.17.1

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[PATCH 2/2] drm/amd/amdgpu: add ASPM support on polaris

[Kenneth Feng]

add ASPM support on polaris

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 193 +++-
 1 file changed, 191 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index ea338de5818a..735ebbd1148f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -81,6 +81,30 @@
 #include "mxgpu_vi.h"
 #include "amdgpu_dm.h"
 
+#define ixPCIE_LC_L1_PM_SUBSTATE   0x100100C6
+#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK   
0x0001L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK   0x0002L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK   0x0004L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 
0x0008L
+#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 
0x0010L
+#define ixPCIE_L1_PM_SUB_CNTL  0x378
+#define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x0004L
+#define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x0008L
+#define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK   0x0001L
+#define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK   0x0002L
+#define PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK0x0020L
+#define LINK_CAP   0x64
+#define PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x0004L
+#define ixCPM_CONTROL  0x1400118
+#define ixPCIE_LC_CNTL70x100100BC
+#define PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK  0x0400L
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT0x0007
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT 0x0009
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK  0x0100L
+#define PCIE_L1_PM_SUB_CNTL0x378
+#define ASIC_IS_P22(asic_type, rid)((asic_type >= CHIP_POLARIS10) && \
+   
(asic_type <= CHIP_POLARIS12) && \
+   (rid >= 
0x6E))
 /* Topaz */
 static const struct amdgpu_video_codecs topaz_video_codecs_encode =
 {
@@ -1091,13 +1115,178 @@ static void vi_pcie_gen3_enable(struct amdgpu_device 
*adev)
/* todo */
 }
 
+static void vi_enable_aspm(struct amdgpu_device *adev)
+{
+   u32 data, orig;
+
+   orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
+   data |= PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT <<
+   PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
+   data |= PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT <<
+   PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+   data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+   data |= PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK;
+   if (orig != data)
+   WREG32_PCIE(ixPCIE_LC_CNTL, data);
+}
+
 static void vi_program_aspm(struct amdgpu_device *adev)
 {
+   u32 data, data1, orig;
+   bool bL1SS = false;
+   bool bClkReqSupport = true;
 
-   if (amdgpu_aspm == 0)
+   if (amdgpu_aspm != 1)
return;
 
-   /* todo */
+   if (adev->flags & AMD_IS_APU ||
+   adev->asic_type < CHIP_POLARIS10)
+   return;
+
+   orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
+   data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
+   data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
+   data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+   if (orig != data)
+   WREG32_PCIE(ixPCIE_LC_CNTL, data);
+
+   orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
+   data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;
+   data |= 0x0024 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT;
+   data |= PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK;
+   if (orig != data)
+   WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data);
+
+   orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
+   data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;
+   if (orig != data)
+   WREG32_PCIE(ixPCIE_LC_CNTL3, data);
+
+   orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
+   data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;
+   if (orig != data)
+   WREG32_PCIE(ixPCIE_P_CNTL, data);
+
+   data = RREG32_PCIE(ixPCIE_LC_L1_PM_SUBSTATE);
+   pci_read_config_dword(adev->pdev, PCIE_L1_PM_SUB_CNTL, );
+   if (data & PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK &&
+   (data & (PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK |
+   PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK |
+   PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK |
+   PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK))) {
+   bL1SS = true;
+   } else if (data1 & (PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK |
+   PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK |
+   PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK |
+  

[PATCH 1/2] drm/amd/amdgpu: enable ASPM on navi1x and vega

[Kenneth Feng]

enable ASPM on navi1x and vega series

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 128 +
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 125 
 drivers/gpu/drm/amd/amdgpu/nv.c|  10 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c |   7 +-
 4 files changed, 259 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 83ea063388fd..0d2d629e2d6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -31,6 +31,28 @@
 #include "vega10_enum.h"
 #include 
 
+#define smnPCIE_LC_CNTL0x11140280
+#define smnPCIE_LC_CNTL3   0x111402d4
+#define smnPCIE_LC_CNTL6   0x111402ec
+#define smnPCIE_LC_CNTL7   0x111402f0
+#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK   0x1000L
+#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK   0xL
+#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xL
+#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL   0x10123530
+#define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2  0x1014008c
+#define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP  0x10140324
+#define smnPSWUSP0_PCIE_LC_CNTL2   0x111402c4
+#define smnRCC_BIF_STRAP2  0x10123488
+#define smnRCC_BIF_STRAP3  0x1012348c
+#define smnRCC_BIF_STRAP5  0x10123494
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK0x0400L
+#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK   0xL
+#define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK   0x4000L
+#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT   0x10
+#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+
 static void nbio_v6_1_remap_hdp_registers(struct amdgpu_device *adev)
 {
WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
@@ -256,6 +278,111 @@ static void nbio_v6_1_init_registers(struct amdgpu_device 
*adev)
WREG32_PCIE(smnPCIE_CI_CNTL, data);
 }
 
+static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
+{
+   uint32_t def, data;
+
+   WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB);
+
+   def = data = RREG32_PCIE(smnRCC_BIF_STRAP2);
+   data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
+   if (def != data)
+   WREG32_PCIE(smnRCC_BIF_STRAP2, data);
+
+   def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
+   data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
+   if (def != data)
+   WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
+
+   def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
+   data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+   if (def != data)
+   WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
+}
+
+static void nbio_v6_1_program_aspm(struct amdgpu_device *adev)
+{
+   uint32_t def, data;
+
+   def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
+   data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
+   data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
+   data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+   if (def != data)
+   WREG32_PCIE(smnPCIE_LC_CNTL, data);
+
+   def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
+   data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
+   if (def != data)
+   WREG32_PCIE(smnPCIE_LC_CNTL7, data);
+
+   def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
+   data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;
+   if (def != data)
+   WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
+
+   def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
+   data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
+   if (def != data)
+   WREG32_PCIE(smnPCIE_LC_CNTL3, data);
+
+   def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
+   data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
+   data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
+   if (def != data)
+   WREG32_PCIE(smnRCC_BIF_STRAP3, data);
+
+   def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
+   data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
+   if (def != data)
+   WREG32_PCIE(smnRCC_BIF_STRAP5, data);
+
+   def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
+   data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+   if (def != data)
+   WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
+
+   WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
+
+   def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
+   data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
+   PSWUSP0_PCIE_LC_CNTL

[PATCH] drm/amd/pm: enable ASPM on navi1x

[Kenneth Feng]

ASPM can be verified funtionally on navi1x.
And can be enabled for the benefit of the power consumption
without the performance hurt.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 46d4bbabce75..5edab56c6ab0 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -601,8 +601,7 @@ static void nv_program_aspm(struct amdgpu_device *adev)
if (amdgpu_aspm != 1)
return;
 
-   if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
-   !(adev->flags & AMD_IS_APU) &&
+   if (!(adev->flags & AMD_IS_APU) &&
(adev->nbio.funcs->program_aspm))
adev->nbio.funcs->program_aspm(adev);
 
@@ -938,8 +937,7 @@ static int nv_update_umd_stable_pstate(struct amdgpu_device 
*adev,
 * The ASPM function is not fully enabled and verified on
 * Navi yet. Temporarily skip this until ASPM enabled.
 */
-   if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
-   !(adev->flags & AMD_IS_APU) &&
+   if (!(adev->flags & AMD_IS_APU) &&
(adev->nbio.funcs->enable_aspm))
adev->nbio.funcs->enable_aspm(adev, !enter);
 
-- 
2.17.1

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[PATCH] drm/amd/pm: bug fix for baco reset

[Kenneth Feng]

On vega20, rocm-smi gets the wrong gfx voltage after baco reset.
This can be reproduced as below.
:~$ rocm-smi --showvoltage
GPU[0] : Voltage (mV): 737
:~$ rocm-smi -d0 --gpureset
GPU[0] : GPU reset was successful
:~$ rocm-smi --showvoltage
GPU[0] : Voltage (mV): 1550

Root cause: telemetry is disabled in the asic_init after baco exit.
This fix targets to re-enable telemetry then all the power and voltage
info can be fetched correctly, mp1 firmware also depends on this setting
for dpm arbitration.

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/pm/powerplay/hwmgr/vega20_baco.c| 17 +
 .../drm/amd/pm/powerplay/hwmgr/vega20_baco.h|  2 +-
 .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c   |  1 +
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
index 2a28c9df15a0..bb58097a925c 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c
@@ -28,9 +28,16 @@
 #include "vega20_ppsmc.h"
 #include "vega20_baco.h"
 #include "vega20_smumgr.h"
+#include "smuio/smuio_9_0_offset.h"
+#include "smuio/smuio_9_0_sh_mask.h"
 
 #include "amdgpu_ras.h"
 
+#define mmSMUSVI0_TFN 0x2
+#define SMUSVI0_TFN___PLANE0_MASK 0x1
+#define SMUSVI0_TFN___PLANE1_MASK 0x2
+#define mmSMUSVI0_TFN_BASE_IDX 0
+
 static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
 {
{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
@@ -120,3 +127,13 @@ int vega20_baco_apply_vdci_flush_workaround(struct 
pp_hwmgr *hwmgr)
 
return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI, 
NULL);
 }
+
+void vega20_baco_override_telemetry_parameters(struct pp_hwmgr *hwmgr)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   uint32_t data = RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TFN);
+
+   data &= (~SMUSVI0_TFN___PLANE0_MASK);
+   data |= SMUSVI0_TFN___PLANE1_MASK;
+   WREG32_SOC15(SMUIO, 0, mmSMUSVI0_TFN, data);
+}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h
index f06471e712dc..9ca39569ba0e 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h
@@ -29,5 +29,5 @@ extern int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, 
bool *cap);
 extern int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE 
*state);
 extern int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE 
state);
 extern int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr);
-
+extern void vega20_baco_override_telemetry_parameters(struct pp_hwmgr *hwmgr);
 #endif
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
index 213c9c6b4462..12830a8dd923 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
@@ -503,6 +503,7 @@ static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
if (ret)
pr_err("Failed to apply vega20 baco workaround!\n");
+   vega20_baco_override_telemetry_parameters(hwmgr);
}
 
return ret;
-- 
2.17.1

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[PATCH] drm/amd/pm: fix workload mismatch on vega10

[Kenneth Feng]

Workload number mapped to the correct one.
This issue is only on vega10.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index f5a32654cde7..31c61ac3bd5e 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -5160,7 +5160,7 @@ static int vega10_set_power_profile_mode(struct pp_hwmgr 
*hwmgr, long *input, ui
 
 out:
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
-   1 << power_profile_mode,
+   (!power_profile_mode) ? 0 : 1 
<< (power_profile_mode - 1),
NULL);
hwmgr->power_profile_mode = power_profile_mode;
 
-- 
2.17.1

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[PATCH v2] drm/amd/pm: workaround for audio noise issue

[Kenneth Feng]

On some Intel platforms, audio noise can be detected due to
high pcie speed switch latency.
This patch leaverages ppfeaturemask to fix to the highest pcie
speed then disable pcie switching.

v2:
coding style fix

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c   | 54 ++
 .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 74 ---
 .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 24 ++
 .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 25 +++
 4 files changed, 166 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index a58f92249c53..54bbee310e57 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -587,6 +587,48 @@ static int smu7_force_switch_to_arbf0(struct pp_hwmgr 
*hwmgr)
tmp, MC_CG_ARB_FREQ_F0);
 }
 
+static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   uint16_t pcie_gen = 0;
+
+   if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 &&
+   adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4)
+   pcie_gen = 3;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 &&
+   adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
+   pcie_gen = 2;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 &&
+   adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2)
+   pcie_gen = 1;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 &&
+   adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1)
+   pcie_gen = 0;
+
+   return pcie_gen;
+}
+
+static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   uint16_t pcie_width = 0;
+
+   if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+   pcie_width = 16;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
+   pcie_width = 12;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
+   pcie_width = 8;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
+   pcie_width = 4;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
+   pcie_width = 2;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
+   pcie_width = 1;
+
+   return pcie_width;
+}
+
 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 {
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -683,6 +725,11 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr 
*hwmgr)
PP_Min_PCIEGen),
get_pcie_lane_support(data->pcie_lane_cap,
PP_Max_PCIELane));
+
+   if (data->pcie_dpm_key_disabled)
+   
phm_setup_pcie_table_entry(>dpm_table.pcie_speed_table,
+   data->dpm_table.pcie_speed_table.count,
+   smu7_override_pcie_speed(hwmgr), 
smu7_override_pcie_width(hwmgr));
}
return 0;
 }
@@ -1248,6 +1295,13 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
NULL)),
"Failed to enable pcie DPM during DPM Start 
Function!",
return -EINVAL);
+   } else {
+   PP_ASSERT_WITH_CODE(
+   (0 == smum_send_msg_to_smc(hwmgr,
+   PPSMC_MSG_PCIeDPM_Disable,
+   NULL)),
+   "Failed to disble pcie DPM during DPM Start 
Function!",
+   return -EINVAL);
}
 
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index 408b35866704..f5a32654cde7 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -54,6 +54,9 @@
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
 
+#define smnPCIE_LC_SPEED_CNTL  0x11140290
+#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
+
 #define HBM_MEMORY_

[PATCH] drm/amd/pm: workaround for audio noise issue

[Kenneth Feng]

On some Intel platforms, audio noise can be detected due to
high pcie speed switch latency.
This patch leaverages ppfeaturemask to fix to the highest pcie
speed then disable pcie switching.

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c   | 54 ++
 .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 74 ---
 .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 25 +++
 .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 26 +++
 4 files changed, 168 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index a58f92249c53..54bbee310e57 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -587,6 +587,48 @@ static int smu7_force_switch_to_arbf0(struct pp_hwmgr 
*hwmgr)
tmp, MC_CG_ARB_FREQ_F0);
 }
 
+static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   uint16_t pcie_gen = 0;
+
+   if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 &&
+   adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4)
+   pcie_gen = 3;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 &&
+   adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
+   pcie_gen = 2;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 &&
+   adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2)
+   pcie_gen = 1;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 &&
+   adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1)
+   pcie_gen = 0;
+
+   return pcie_gen;
+}
+
+static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   uint16_t pcie_width = 0;
+
+   if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+   pcie_width = 16;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
+   pcie_width = 12;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
+   pcie_width = 8;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
+   pcie_width = 4;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
+   pcie_width = 2;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
+   pcie_width = 1;
+
+   return pcie_width;
+}
+
 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 {
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -683,6 +725,11 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr 
*hwmgr)
PP_Min_PCIEGen),
get_pcie_lane_support(data->pcie_lane_cap,
PP_Max_PCIELane));
+
+   if (data->pcie_dpm_key_disabled)
+   
phm_setup_pcie_table_entry(>dpm_table.pcie_speed_table,
+   data->dpm_table.pcie_speed_table.count,
+   smu7_override_pcie_speed(hwmgr), 
smu7_override_pcie_width(hwmgr));
}
return 0;
 }
@@ -1248,6 +1295,13 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
NULL)),
"Failed to enable pcie DPM during DPM Start 
Function!",
return -EINVAL);
+   } else {
+   PP_ASSERT_WITH_CODE(
+   (0 == smum_send_msg_to_smc(hwmgr,
+   PPSMC_MSG_PCIeDPM_Disable,
+   NULL)),
+   "Failed to disble pcie DPM during DPM Start 
Function!",
+   return -EINVAL);
}
 
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index 408b35866704..f5a32654cde7 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -54,6 +54,9 @@
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
 
+#define smnPCIE_LC_SPEED_CNTL  0x11140290
+#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
+
 #define HBM_MEMORY_CHANNEL_WIDTH128
 
 

[PATCH] drm/amd/pm: bug fix for pcie dpm

[Kenneth Feng]

Currently the pcie dpm has two problems.
1. Only the high dpm level speed/width can be overrided
if the requested values are out of the pcie capability.
2. The high dpm level is always overrided though sometimes
it's not necesarry.

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 48 ++
 .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 66 +++
 .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 48 --
 3 files changed, 141 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index 5e875ad8d633..408b35866704 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -1505,6 +1505,48 @@ static int vega10_populate_single_lclk_level(struct 
pp_hwmgr *hwmgr,
return 0;
 }
 
+static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   struct vega10_hwmgr *data =
+   (struct vega10_hwmgr *)(hwmgr->backend);
+   uint32_t pcie_gen = 0, pcie_width = 0;
+   PPTable_t *pp_table = &(data->smc_state_table.pp_table);
+   int i;
+
+   if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
+   pcie_gen = 3;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+   pcie_gen = 2;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
+   pcie_gen = 1;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
+   pcie_gen = 0;
+
+   if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+   pcie_width = 6;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
+   pcie_width = 5;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
+   pcie_width = 4;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
+   pcie_width = 3;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
+   pcie_width = 2;
+   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
+   pcie_width = 1;
+
+   for (i = 0; i < NUM_LINK_LEVELS; i++) {
+   if (pp_table->PcieGenSpeed[i] > pcie_gen)
+   pp_table->PcieGenSpeed[i] = pcie_gen;
+
+   if (pp_table->PcieLaneCount[i] > pcie_width)
+   pp_table->PcieLaneCount[i] = pcie_width;
+   }
+
+   return 0;
+}
+
 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
 {
int result = -1;
@@ -2556,6 +2598,11 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
"Failed to initialize Link Level!",
return result);
 
+   result = vega10_override_pcie_parameters(hwmgr);
+   PP_ASSERT_WITH_CODE(!result,
+   "Failed to override pcie parameters!",
+   return result);
+
result = vega10_populate_all_graphic_levels(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to initialize Graphics Level!",
@@ -2922,6 +2969,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, 
uint32_t bitmap)
return 0;
 }
 
+
 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, 
bool enable)
 {
struct vega10_hwmgr *data = hwmgr->backend;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
index a827f2bc7904..196ac2a4d145 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
@@ -481,6 +481,67 @@ static void vega12_init_dpm_state(struct vega12_dpm_state 
*dpm_state)
dpm_state->hard_max_level = 0x;
 }
 
+static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   struct vega12_hwmgr *data =
+   (struct vega12_hwmgr *)(hwmgr->backend);
+   uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, 
pcie_width_arg;
+   PPTable_t *pp_table = &(data->smc_state_table.pp_table);
+   int i;
+   int ret;
+
+   if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
+   pcie_gen = 3;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+   pcie_gen = 2;
+   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
+   pcie_gen = 1;
+   else if (adev->pm.pcie_ge

[PATCH v2] drm/amd/pm: enable LCLK DS

[Kenneth Feng]

v1:
Enable LCLK deep sleep and it works if we enable ASPM:
modprobe amdgpu aspm=1

v2:
Add the amdgpu_aspm flag check

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index b9e47f3b0231..af73e1430af5 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -302,6 +302,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
if (smu->dc_controlled_by_gpio)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 
+   if (amdgpu_aspm == 1)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
+
return 0;
 }
 
-- 
2.17.1

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[PATCH] drm/amd/pm: enable LCLK DS

[Kenneth Feng]

Enable LCLK deep sleep and it works if we enable ASPM:
modprobe amdgpu aspm=1

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index b9e47f3b0231..d208a434c7cc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -242,6 +242,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
| FEATURE_MASK(FEATURE_DS_FCLK_BIT)
| FEATURE_MASK(FEATURE_DS_UCLK_BIT)
+   | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
| FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
-- 
2.17.1

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[PATCH v3] drm/amd/pm: enable DCS

[Kenneth Feng]

Enable DCS

V1: Enable Async DCS.
V2: Add the ppfeaturemask bit to enable from the modprobe parameter.
V3:
1. add the flag to skip APU support.
2. remove the hunk for workload selection since
it doesn't impact the function.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++--
 drivers/gpu/drm/amd/include/amd_shared.h| 1 +
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 5 +
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 2fd3a80bb034..ca3dce6d463e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -131,8 +131,12 @@ uint amdgpu_pg_mask = 0x;
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-/* OverDrive(bit 14) disabled by default*/
-uint amdgpu_pp_feature_mask = 0xbfff;
+
+/*
+ * OverDrive(bit 14) disabled by default
+ * GFX DCS(bit 19) disabled by default
+ */
+uint amdgpu_pp_feature_mask = 0xfff7bfff;
 uint amdgpu_force_long_training;
 int amdgpu_job_hang_limit;
 int amdgpu_lbpw = -1;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 9676016a37ce..43ed6291b2b8 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -213,6 +213,7 @@ enum PP_FEATURE_MASK {
PP_ACG_MASK = 0x1,
PP_STUTTER_MODE = 0x2,
PP_AVFS_MASK = 0x4,
+   PP_GFX_DCS_MASK = 0x8,
 };
 
 enum DC_FEATURE_MASK {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index cf59f2218b7e..fd090d057d26 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -261,6 +261,11 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
}
 
+   if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
+   (adev->asic_type > CHIP_SIENNA_CICHLID) &&
+   !(adev->flags & AMD_IS_APU))
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
+
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
| 
FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
-- 
2.17.1

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[PATCH v3] drm/amd/pm: enable DCS

[Kenneth Feng]

Enable Async DCS

V3:
1. add the flag to skip APU support.
2. remove the hunk for workload selection since
it doesn't impact the function.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++--
 drivers/gpu/drm/amd/include/amd_shared.h| 1 +
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 5 +
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 2fd3a80bb034..ca3dce6d463e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -131,8 +131,12 @@ uint amdgpu_pg_mask = 0x;
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-/* OverDrive(bit 14) disabled by default*/
-uint amdgpu_pp_feature_mask = 0xbfff;
+
+/*
+ * OverDrive(bit 14) disabled by default
+ * GFX DCS(bit 19) disabled by default
+ */
+uint amdgpu_pp_feature_mask = 0xfff7bfff;
 uint amdgpu_force_long_training;
 int amdgpu_job_hang_limit;
 int amdgpu_lbpw = -1;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 9676016a37ce..43ed6291b2b8 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -213,6 +213,7 @@ enum PP_FEATURE_MASK {
PP_ACG_MASK = 0x1,
PP_STUTTER_MODE = 0x2,
PP_AVFS_MASK = 0x4,
+   PP_GFX_DCS_MASK = 0x8,
 };
 
 enum DC_FEATURE_MASK {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index cf59f2218b7e..fd090d057d26 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -261,6 +261,11 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
}
 
+   if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
+   (adev->asic_type > CHIP_SIENNA_CICHLID) &&
+   !(adev->flags & AMD_IS_APU))
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
+
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
| 
FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
-- 
2.17.1

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[PATCH] drm/amd/pm: enable ACDC feature

[Kenneth Feng]

The power limit and clock ragne are different in AC mode and DC mode.
Firmware does the setting after this feature is enabled.
Applied on mobile skus.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index dffdcebc80e1..faddfa9f5642 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
}
 
+   if (smu->dc_controlled_by_gpio)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
+
if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && adev->asic_type > 
CHIP_SIENNA_CICHLID)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
 
-- 
2.17.1

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[PATCH v2] drm/amd/pm: Enable gfx DCS feature

[Kenneth Feng]

Background:
Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
When the current/power/temperature exceeds the limit with the heavy workload,
the gfx core can be shut off and powered on back and forth.
The ON time and OFF time is determined by the firmware according to
the accumulated power credits.
This feature is different from gfxoff.Gfxoff is applied in the idle case
and DCS is applied in the case with heavey workload.There are two types of DCS:
Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D fullscreen
and VR workload.
Since we only supports Async DCS now,disalbe DCS when the 3D fullscreen or
the VR workload type is chosen.

Verification:
The power is lowerer or the perf/watt is increased in the throttling case.
To be simplified, the entry/exit counter can be observed from the firmware.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |  8 ++--
 drivers/gpu/drm/amd/include/amd_shared.h |  1 +
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 82c2fa8a67cd..186bbe139bde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -131,8 +131,12 @@ uint amdgpu_pg_mask = 0x;
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-/* OverDrive(bit 14) disabled by default*/
-uint amdgpu_pp_feature_mask = 0xbfff;
+
+/*
+ * OverDrive(bit 14) disabled by default
+ * GFX DCS(bit 19) disabled by default
+ */
+uint amdgpu_pp_feature_mask = 0xfff7bfff;
 uint amdgpu_force_long_training;
 int amdgpu_job_hang_limit;
 int amdgpu_lbpw = -1;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 9676016a37ce..43ed6291b2b8 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -213,6 +213,7 @@ enum PP_FEATURE_MASK {
PP_ACG_MASK = 0x1,
PP_STUTTER_MODE = 0x2,
PP_AVFS_MASK = 0x4,
+   PP_GFX_DCS_MASK = 0x8,
 };
 
 enum DC_FEATURE_MASK {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 24f3c96a5e5e..dffdcebc80e1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
}
 
+   if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && adev->asic_type > 
CHIP_SIENNA_CICHLID)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
+
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
| 
FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
@@ -1437,6 +1440,15 @@ static int sienna_cichlid_set_power_profile_mode(struct 
smu_context *smu, long *
smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1 << workload_type, NULL);
 
+   /* have to disable dcs if it's the 3D fullscreen or VR workload type */
+   if ((smu->adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
+   smu->adev->asic_type > CHIP_SIENNA_CICHLID) {
+   ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, 
(workload_type ==
+   WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == 
WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
+   if (ret)
+   return ret;
+   }
+
return ret;
 }
 
-- 
2.17.1

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[PATCH] drm/amd/pm: Enable gfx DCS feature

[Kenneth Feng]

Background:
Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
When the current/power/temperature exceeds the limit with the heavy workload,
the gfx core can be shut off and powered on back and forth.
The ON time and OFF time is determined by the firmware according to
the accumulated power credits.
This feature is different from gfxoff.Gfxoff is applied in the idle case
and DCS is applied in the case with heavey workload.There are two types of DCS:
Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D fullscreen
and VR workload.
Since we only supports Async DCS now,disalbe DCS when the 3D fullscreen or
the VR workload type is chosen.

Verification:
The power is lowerer or the perf/watt is increased in the throttling case.
To be simplified, the entry/exit counter can be observed from the firmware.

Signed-off-by: Kenneth Feng 
---
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 24f3c96a5e5e..436d94cbb166 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
}
 
+   if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == 
CHIP_DIMGREY_CAVEFISH)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
+
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
| 
FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
@@ -1437,6 +1440,15 @@ static int sienna_cichlid_set_power_profile_mode(struct 
smu_context *smu, long *
smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1 << workload_type, NULL);
 
+   /* have to disable dcs if it's the 3D fullscreen or VR workload type */
+   if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
+   smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
+   ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, 
(workload_type ==
+   WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == 
WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
+   if (ret)
+   return ret;
+   }
+
return ret;
 }
 
-- 
2.17.1

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[PATCH] drm/amd/amdgpu: skip unload message in reset

[Kenneth Feng]

This has been confirmed that unload message is not needed from SIENNA_CICHLID 
in reset.
Otherwise it will cause the fw wrong state after reset and no response for any 
messages.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 74cbaf212698..0f0ee7c5ffab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1925,7 +1925,8 @@ static int psp_load_smu_fw(struct psp_context *psp)
return 0;
 
 
-   if (amdgpu_in_reset(adev) && ras && ras->supported) {
+   if (amdgpu_in_reset(adev) && ras && ras->supported &&
+   adev->asic_type == CHIP_ARCTURUS) {
ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
if (ret) {
DRM_WARN("Failed to set MP1 state prepare for 
reload\n");
-- 
2.17.1

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[PATCH 1/2] drm/amd/amdgpu: fix null pointer in runtime pm

[Kenneth Feng]

fix the null pointer issue when runtime pm is triggered.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1fe850e0a94d..0ebba4380979 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4859,7 +4859,7 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
return -ENOTSUPP;
 
-   if (ras && ras->supported)
+   if (ras && ras->supported && 
adev->nbio.funcs->enable_doorbell_interrupt)
adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 
return amdgpu_dpm_baco_enter(adev);
@@ -4878,7 +4878,7 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
if (ret)
return ret;
 
-   if (ras && ras->supported)
+   if (ras && ras->supported && 
adev->nbio.funcs->enable_doorbell_interrupt)
adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 
return 0;
-- 
2.17.1

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[PATCH 2/2] drm/amd/pm: fix the crash after runtime pm resume

[Kenneth Feng]

Some features are still disabled after runtime pm resume. This can take the 
hardware back.
Unlike other projects, this doesn't need pptable retransfer.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 39990790ed67..ebd50f144c5d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -914,11 +914,14 @@ static int smu_smc_hw_setup(struct smu_context *smu)
 {
struct amdgpu_device *adev = smu->adev;
uint32_t pcie_gen = 0, pcie_width = 0;
-   int ret;
+   int ret = 0;
 
if (adev->in_suspend && smu_is_dpm_running(smu)) {
dev_info(adev->dev, "dpm has been enabled\n");
-   return 0;
+   /* this is needed specifically */
+   if (adev->asic_type == CHIP_SIENNA_CICHLID)
+   ret = smu_system_features_control(smu, true);
+   return ret;
}
 
ret = smu_init_display_count(smu, 0);
-- 
2.17.1

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[PATCH 0/2] runtime pm fix

[Kenneth Feng]

this 2 patches fix the runtime pm problems on SIENNA_CICHLID. 

Kenneth Feng (2):
  drm/amd/amdgpu: fix null pointer in runtime pm
  drm/amd/pm: fix the crash after runtime pm resume

 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c  | 7 +--
 2 files changed, 7 insertions(+), 4 deletions(-)

-- 
2.17.1

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[PATCH] drm/amd/pm: change the baco parameter

[Kenneth Feng]

For some products, baco parameter 1 is dummy and this doesn't trigger the baco 
entry/exit.
Parameter 0 is valid and these products don't depend on ras for baco sequence.

Signed-off-by: Kenneth Feng 
---
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 24 +--
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index b6453ee6f8e6..3e1a3cf44a69 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1495,15 +1495,25 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, 
enum smu_baco_state state)
mutex_lock(_baco->mutex);
 
if (state == SMU_BACO_STATE_ENTER) {
-   if (!ras || !ras->supported) {
-   data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
-   data |= 0x8000;
-   WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
-
+   switch (adev->asic_type) {
+   case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
+   case CHIP_DIMGREY_CAVEFISH:
ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_EnterBaco, 0, NULL);
-   } else {
-   ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_EnterBaco, 1, NULL);
+   break;
+   default:
+   if (!ras || !ras->supported) {
+   data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
+   data |= 0x8000;
+   WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+
+   ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_EnterBaco, 0, NULL);
+   } else {
+ ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_EnterBaco, 1, NULL);
+   }
+   break;
}
+
} else {
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
if (ret)
-- 
2.17.1

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[PATCH] drm/amd/amdgpu: specify the power strategy for vcn use

[Kenneth Feng]

The power/performance control strategy is specific for vcn use case.
Then this can optimize the power/performance when the workload is on vcn.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 0145504e408b..2c3e111bab43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -361,6 +361,8 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work)
amdgpu_gfx_off_ctrl(adev, true);
amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,
   AMD_PG_STATE_GATE);
+   amdgpu_dpm_switch_power_profile(adev, 
PP_SMC_POWER_PROFILE_VIDEO,
+   false);
} else {
schedule_delayed_work(>vcn.idle_work, VCN_IDLE_TIMEOUT);
}
@@ -372,8 +374,11 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 
atomic_inc(>vcn.total_submission_cnt);
 
-   if (!cancel_delayed_work_sync(>vcn.idle_work))
+   if (!cancel_delayed_work_sync(>vcn.idle_work)) {
amdgpu_gfx_off_ctrl(adev, false);
+   amdgpu_dpm_switch_power_profile(adev, 
PP_SMC_POWER_PROFILE_VIDEO,
+   true);
+   }
 
mutex_lock(>vcn.vcn_pg_lock);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
-- 
2.17.1

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[PATCH] drm/amd/pm: remove the average clock value in sysfs

[Kenneth Feng]

if it's fine-grained clock dpm, remove the average clock value and
reflects the real clock.

Signed-off-by: Kenneth Feng 
---
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index d2851f8e9c11..fa3842f460fc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -955,12 +955,16 @@ static int sienna_cichlid_print_clk_levels(struct 
smu_context *smu,
freq_values[1] = cur_value;
mark_index = cur_value == freq_values[0] ? 0 :
 cur_value == freq_values[2] ? 2 : 1;
-   if (mark_index != 1)
-   freq_values[1] = (freq_values[0] + 
freq_values[2]) / 2;
 
-   for (i = 0; i < 3; i++) {
+   count = 3;
+   if (mark_index != 1) {
+   count = 2;
+   freq_values[1] = freq_values[2];
+   }
+
+   for (i = 0; i < count; i++) {
size += sprintf(buf + size, "%d: %uMhz %s\n", 
i, freq_values[i],
-   i == mark_index ? "*" : "");
+   cur_value  == freq_values[i] ? 
"*" : "");
}
 
}
-- 
2.17.1

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[PATCH] drm/amd/pm: fix pp_dpm_fclk

[Kenneth Feng]

fclk value is missing in pp_dpm_fclk. add this to correctly show the current 
value.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 27b6cade9ade..d2851f8e9c11 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -456,6 +456,9 @@ static int sienna_cichlid_get_smu_metrics_data(struct 
smu_context *smu,
case METRICS_CURR_DCEFCLK:
*value = metrics->CurrClock[PPCLK_DCEFCLK];
break;
+   case METRICS_CURR_FCLK:
+   *value = metrics->CurrClock[PPCLK_FCLK];
+   break;
case METRICS_AVERAGE_GFXCLK:
if (metrics->AverageGfxActivity <= 
SMU_11_0_7_GFX_BUSY_THRESHOLD)
*value = metrics->AverageGfxclkFrequencyPostDs;
-- 
2.17.1

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[PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[Kenneth Feng]

fix the wrong fan speed in fan1_input when the fan control mode is manual.
the fan speed value is not correct when we set manual mode to fan1_enalbe - 1.
since the fan speed in the metrics table always reflects the real fan speed,we
can fetch the fan speed for both auto and manual mode.

Signed-off-by: Kenneth Feng 
---
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 11 +++
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 496abc31b07e..27b6cade9ade 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1171,14 +1171,9 @@ static int sienna_cichlid_get_fan_speed_rpm(struct 
smu_context *smu,
if (!speed)
return -EINVAL;
 
-   switch (smu_v11_0_get_fan_control_mode(smu)) {
-   case AMD_FAN_CTRL_AUTO:
-   return sienna_cichlid_get_smu_metrics_data(smu,
-  
METRICS_CURR_FANSPEED,
-  speed);
-   default:
-   return smu_v11_0_get_fan_speed_rpm(smu, speed);
-   }
+   return sienna_cichlid_get_smu_metrics_data(smu,
+   METRICS_CURR_FANSPEED,
+   speed);
 }
 
 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
-- 
2.17.1

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[PATCH] drm/amd/powerplay: remove the dpm checking in the boot sequence

[Kenneth Feng]

It's not necessary to retrieve the power features status when the
asic is booted up the first time. This patch can have the features
enablement status still checked in suspend/resume case and removed
from the first boot up sequence.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f778b00e49eb..6b03f750e63b 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -735,7 +735,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
uint32_t pcie_gen = 0, pcie_width = 0;
int ret;
 
-   if (smu_is_dpm_running(smu) && adev->in_suspend) {
+   if (adev->in_suspend && smu_is_dpm_running(smu)) {
dev_info(adev->dev, "dpm has been enabled\n");
return 0;
}
-- 
2.17.1

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[PATCH v2] drm/amd/powerplay: sw ctf for arcturus

[Kenneth Feng]

change the sw ctf setting to smu_v11_0_set_thermal_range()
since software_shutdown_temp shares the same definition and
name in all the smu11 project.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index e804f98..76bddd5 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1154,11 +1154,12 @@ static int smu_v11_0_set_thermal_range(struct 
smu_context *smu,
int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
uint32_t val;
+   struct smu_table_context *table_context = >smu_table;
+   struct smu_11_0_powerplay_table *powerplay_table = 
table_context->power_play_table;
 
low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
-   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
-   range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 
powerplay_table->software_shutdown_temp);
 
if (low > high)
return -EINVAL;
-- 
2.7.4

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[PATCH] drm/amd/powerplay: sw ctf for arcturus

[Kenneth Feng]

software ctf implementation on arcturs.
has been verified on the system by setting a fake software ctf
temperature limit like 40 degrees centigrade.
then the interrupt is triggered from ih ring and
the warning can be observed from dmesg.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 50b317f..330d5f4 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -846,11 +846,13 @@ static int arcturus_get_thermal_temperature_range(struct 
smu_context *smu,
struct smu_temperature_range 
*range)
 {
PPTable_t *pptable = smu->smu_table.driver_pptable;
+   struct smu_table_context *table_context = >smu_table;
+   struct smu_11_0_powerplay_table *powerplay_table = 
table_context->power_play_table;
 
-   if (!range)
+   if (!range || !powerplay_table)
return -EINVAL;
 
-   range->max = pptable->TedgeLimit *
+   range->max = powerplay_table->software_shutdown_temp *
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
-- 
2.7.4

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[PATCH] drm/amd/powerplay: read pcie speed/width info

[Kenneth Feng]

sysfs interface to read pcie speed info on navi1x.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 10 +++---
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  8 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 50 ++-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.h|  3 ++
 4 files changed, 66 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 57459a6..69243a8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1068,10 +1068,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return ret;
 
if (adev->asic_type != CHIP_ARCTURUS) {
-   ret = smu_override_pcie_parameters(smu);
-   if (ret)
-   return ret;
-
ret = smu_notify_display_change(smu);
if (ret)
return ret;
@@ -1100,6 +1096,12 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return ret;
}
 
+   if (adev->asic_type != CHIP_ARCTURUS) {
+   ret = smu_override_pcie_parameters(smu);
+   if (ret)
+   return ret;
+   }
+
ret = smu_set_default_od_settings(smu, initialize);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 0ba7a72..6061490 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -48,6 +48,8 @@
 
 #define SMU11_TOOL_SIZE0x19000
 
+#define MAX_PCIE_CONF 2
+
 #define CLK_MAP(clk, index) \
[SMU_##clk] = {1, (index)}
 
@@ -88,6 +90,11 @@ struct smu_11_0_dpm_table {
uint32_tmax;/* MHz */
 };
 
+struct smu_11_0_pcie_table {
+uint8_t  pcie_gen[MAX_PCIE_CONF];
+uint8_t  pcie_lane[MAX_PCIE_CONF];
+};
+
 struct smu_11_0_dpm_tables {
struct smu_11_0_dpm_tablesoc_table;
struct smu_11_0_dpm_tablegfx_table;
@@ -100,6 +107,7 @@ struct smu_11_0_dpm_tables {
struct smu_11_0_dpm_tabledisplay_table;
struct smu_11_0_dpm_tablephy_table;
struct smu_11_0_dpm_tablefclk_table;
+   struct smu_11_0_pcie_table   pcie_table;
 };
 
 struct smu_11_0_dpm_context {
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 36cf313..8855bcc 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -36,6 +36,7 @@
 #include "navi10_ppt.h"
 #include "smu_v11_0_pptable.h"
 #include "smu_v11_0_ppsmc.h"
+#include "nbio/nbio_7_4_sh_mask.h"
 
 #include "asic_reg/mp/mp_11_0_sh_mask.h"
 
@@ -599,6 +600,7 @@ static int navi10_set_default_dpm_table(struct smu_context 
*smu)
struct smu_table_context *table_context = >smu_table;
struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
PPTable_t *driver_ppt = NULL;
+   int i;
 
driver_ppt = table_context->driver_pptable;
 
@@ -629,6 +631,11 @@ static int navi10_set_default_dpm_table(struct smu_context 
*smu)
dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
dpm_context->dpm_tables.phy_table.max = 
driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 
+   for (i = 0; i < MAX_PCIE_CONF; i++) {
+   dpm_context->dpm_tables.pcie_table.pcie_gen[i] = 
driver_ppt->PcieGenSpeed[i];
+   dpm_context->dpm_tables.pcie_table.pcie_lane[i] = 
driver_ppt->PcieLaneCount[i];
+   }
+
return 0;
 }
 
@@ -710,6 +717,11 @@ static int navi10_print_clk_levels(struct smu_context *smu,
struct smu_table_context *table_context = >smu_table;
od_table = (OverDriveTable_t *)table_context->overdrive_table;
od_settings = smu->od_settings;
+   uint32_t gen_speed, lane_width;
+   struct smu_dpm_context *smu_dpm = >smu_dpm;
+   struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+   struct amdgpu_device *adev = smu->adev;
+   PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 
switch (clk_type) {
case SMU_GFXCLK:
@@ -760,6 +772,30 @@ static int navi10_print_clk_levels(struct smu_context *smu,
 
}
break;
+   case SMU_PCIE:
+   gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
+
PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
+   >> 
PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
+   lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
+ 

[PATCH v2] drm/amd/powerplay: dynamically disable ds and ulv for compute

[Kenneth Feng]

This is to improve the performance in the compute mode
for vega10. For example, the original performance for a rocm
bandwidth test: 2G internal GPU copy, is about 99GB/s.
With the idle power features disabled dynamically, the porformance
is promoted to about 215GB/s.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  |  7 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 55 ++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  2 +
 3 files changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 0314476..bd35f65 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -969,6 +969,13 @@ static int pp_dpm_switch_power_profile(void *handle,
workload = hwmgr->workload_setting[index];
}
 
+   if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
+   
hwmgr->hwmgr_func->disable_power_features_for_compute_performance)
+   if 
(hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) {
+   mutex_unlock(>smu_lock);
+   return -EINVAL;
+   }
+
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, , 0);
mutex_unlock(>smu_lock);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 4ea63a2..d3229c2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -5263,6 +5263,59 @@ static int vega10_get_performance_level(struct pp_hwmgr 
*hwmgr, const struct pp_
return 0;
 }
 
+static int vega10_disable_power_features_for_compute_performance(struct 
pp_hwmgr *hwmgr, bool disable)
+{
+   struct vega10_hwmgr *data = hwmgr->backend;
+   uint32_t feature_mask = 0;
+
+   if (disable) {
+   feature_mask |= data->smu_features[GNLD_ULV].enabled ?
+   data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
+   feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ?
+   data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 
0;
+   feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ?
+   data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 
0;
+   feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ?
+   data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
+   feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ?
+   data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap 
: 0;
+   } else {
+   feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
+   data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
+   feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ?
+   data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 
0;
+   feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ?
+   data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 
0;
+   feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ?
+   data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
+   feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ?
+   data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap 
: 0;
+   }
+
+   if (feature_mask)
+   PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
+   !disable, feature_mask),
+   "enable/disable power features for compute 
performance Failed!",
+   return -EINVAL);
+
+   if (disable) {
+   data->smu_features[GNLD_ULV].enabled = false;
+   data->smu_features[GNLD_DS_GFXCLK].enabled = false;
+   data->smu_features[GNLD_DS_SOCCLK].enabled = false;
+   data->smu_features[GNLD_DS_LCLK].enabled = false;
+   data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
+   } else {
+   data->smu_features[GNLD_ULV].enabled = true;
+   data->smu_features[GNLD_DS_GFXCLK].enabled = true;
+   data->smu_features[GNLD_DS_SOCCLK].enabled = true;
+   data->smu_features[GNLD_DS_LCLK].enabled = true;
+   data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
+   }
+
+   return 0;
+
+}
+
 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.backend_init = vega10_hwmg

[PATCH] drm/amd/powerplay: disable ds and ulv for compute

[Kenneth Feng]

This is to improve the performance in the compute mode
for vega10. For example, the original performance for a rocm
bandwidth test: 2G internal GPU copy, is about 99GB/s.
With the idle power features disabled dynamically, the porformance
is promoted to about 215GB/s.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 62 +-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 4ea63a2..c0dbb26 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4940,6 +4940,59 @@ static int vega10_get_power_profile_mode(struct pp_hwmgr 
*hwmgr, char *buf)
return size;
 }
 
+static int vega10_disable_power_features_for_compute_performance(struct 
pp_hwmgr *hwmgr, bool disable)
+{
+   struct vega10_hwmgr *data = hwmgr->backend;
+   uint32_t feature_mask = 0;
+
+   if (disable) {
+   feature_mask |= data->smu_features[GNLD_ULV].enabled ?
+   data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
+   feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ?
+   data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 
0;
+   feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ?
+   data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 
0;
+   feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ?
+   data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
+   feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ?
+   data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap 
: 0;
+   } else {
+   feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
+   data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
+   feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ?
+   data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 
0;
+   feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ?
+   data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 
0;
+   feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ?
+   data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
+   feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ?
+   data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap 
: 0;
+   }
+
+   if (feature_mask)
+   PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
+   !disable, feature_mask),
+   "enable/disable power features for compute 
performance Failed!",
+   return -EINVAL);
+
+   if (disable) {
+   data->smu_features[GNLD_ULV].enabled = false;
+   data->smu_features[GNLD_DS_GFXCLK].enabled = false;
+   data->smu_features[GNLD_DS_SOCCLK].enabled = false;
+   data->smu_features[GNLD_DS_LCLK].enabled = false;
+   data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
+   } else {
+   data->smu_features[GNLD_ULV].enabled = true;
+   data->smu_features[GNLD_DS_GFXCLK].enabled = true;
+   data->smu_features[GNLD_DS_SOCCLK].enabled = true;
+   data->smu_features[GNLD_DS_LCLK].enabled = true;
+   data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
+   }
+
+   return 0;
+
+}
+
 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, 
uint32_t size)
 {
struct vega10_hwmgr *data = hwmgr->backend;
@@ -4948,6 +5001,7 @@ static int vega10_set_power_profile_mode(struct pp_hwmgr 
*hwmgr, long *input, ui
uint8_t use_rlc_busy;
uint8_t min_active_level;
uint32_t power_profile_mode = input[size];
+   int ret = 0;
 
if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
if (size != 0 && size != 4)
@@ -4975,11 +5029,17 @@ static int vega10_set_power_profile_mode(struct 
pp_hwmgr *hwmgr, long *input, ui
}
 
 out:
+   if (power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE)
+   ret = 
vega10_disable_power_features_for_compute_performance(hwmgr, true);
+   else
+   ret = 
vega10_disable_power_features_for_compute_performance(hwmgr, false);
+
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
1 << power_profile_mode);
+
hwmgr->power_profile_mode = power_profile_mode;
 
-   return 0;
+   return ret;
 }
 
 
-- 
2.7.4

_

[PATCH] drm/amd/powerplay: bug fix for memory clock request from display

[Kenneth Feng]

In some cases, display fixes memory clock frequency to a high value
rather than the natural memory clock switching.
When we comes back from s3 resume, the request from display is not reset,
this causes the bug which makes the memory clock goes into a low value.
Then due to the insuffcient memory clock, the screen flicks.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e2a03f4..ee374df 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1354,6 +1354,8 @@ static int smu_resume(void *handle)
if (smu->is_apu)
smu_set_gfx_cgpg(>smu, true);
 
+   smu->disable_uclk_switch = 0;
+
mutex_unlock(>mutex);
 
pr_info("SMU is resumed successfully!\n");
-- 
2.7.4

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[PATCH v2] drm/amd/powerplay: bug fix for pcie parameters override

[Kenneth Feng]

Bug fix for pcie paramerers override on swsmu.
Below is a scenario to have this problem.
pptable definition on pcie dpm:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:4, pcie lanes: *16
Then if we have a system only have the capbility:
pcie gen speed: 3, pcie lanes: *8,
we will override dpm 1 to pcie gen speed 3, pcie lanes *8.
But the code skips the dpm 0 configuration.
So the real pcie dpm parameters are:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:3, pcie lanes: *8
Then the wrong pcie lanes will be toggled.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 44 --
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  8 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 23 ++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 44 ++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 25 ++-
 5 files changed, 99 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c9266ea..de54da2 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -945,50 +945,6 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
return 0;
 }
 
-static int smu_override_pcie_parameters(struct smu_context *smu)
-{
-   struct amdgpu_device *adev = smu->adev;
-   uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
-   int ret;
-
-   if (adev->flags & AMD_IS_APU)
-   return 0;
-
-   if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
-   pcie_gen = 3;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-   pcie_gen = 2;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-   pcie_gen = 1;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
-   pcie_gen = 0;
-
-   /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
-* Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
-* Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
-*/
-   if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
-   pcie_width = 6;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
-   pcie_width = 5;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
-   pcie_width = 4;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
-   pcie_width = 3;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
-   pcie_width = 2;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
-   pcie_width = 1;
-
-   smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
-   ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_OverridePcieParameters,
- smu_pcie_arg);
-   if (ret)
-   pr_err("[%s] Attempt to override pcie params failed!\n", 
__func__);
-   return ret;
-}
-
 static int smu_smc_table_hw_init(struct smu_context *smu,
 bool initialize)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ccf711c..809de0d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -468,6 +468,7 @@ struct pptable_funcs {
int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool 
asic_default);
int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type 
clk_type,
   uint32_t dpm_level, uint32_t *freq);
+   int (*update_pcie_parameters)(struct smu_context *smu, uint32_t 
pcie_gen_cap, uint32_t pcie_width_cap);
 };
 
 struct smu_funcs
@@ -550,6 +551,7 @@ struct smu_funcs
int (*mode2_reset)(struct smu_context *smu);
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type 
clk_type, uint32_t *min, uint32_t *max);
int (*set_soft_freq_limited_range)(struct smu_context *smu, enum 
smu_clk_type clk_type, uint32_t min, uint32_t max);
+   int (*override_pcie_parameters)(struct smu_context *smu);
 };
 
 #define smu_init_microcode(smu) \
@@ -782,6 +784,12 @@ struct smu_funcs
 #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
((smu)->funcs->set_soft_freq_limited_range ? 
(smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : 
-EINVAL)
 
+#define smu_override_pcie_parameters(smu) \
+   ((smu)->funcs->override_pcie_parameters ? 
(smu)->funcs->overrid

[PATCH] drm/amd/powerplay: bug fix for pcie parameters override

[Kenneth Feng]

Bug fix for pcie paramerers override on swsmu.
Below is a scenario to have this problem.
pptable definition on pcie dpm:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:4, pcie lanes: *16
Then if we have a system only have the capbility:
pcie gen speed: 3, pcie lanes: *8,
we will override dpm 1 to pcie gen speed 3, pcie lanes *8.
But the code skips the dpm 0 configuration.
So the real pcie dpm parameters are:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:3, pcie lanes: *8
Then the wrong pcie lanes will be toggled.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c  |   44 -
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h  |8 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c  |   23 +
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c   |   44 +
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c_mi100 | 1404 +++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c  |   25 +-
 6 files changed, 1503 insertions(+), 45 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/smu_v11_0.c_mi100

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c9266ea..de54da2 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -945,50 +945,6 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
return 0;
 }
 
-static int smu_override_pcie_parameters(struct smu_context *smu)
-{
-   struct amdgpu_device *adev = smu->adev;
-   uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
-   int ret;
-
-   if (adev->flags & AMD_IS_APU)
-   return 0;
-
-   if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
-   pcie_gen = 3;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-   pcie_gen = 2;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-   pcie_gen = 1;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
-   pcie_gen = 0;
-
-   /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
-* Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
-* Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
-*/
-   if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
-   pcie_width = 6;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
-   pcie_width = 5;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
-   pcie_width = 4;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
-   pcie_width = 3;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
-   pcie_width = 2;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
-   pcie_width = 1;
-
-   smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
-   ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_OverridePcieParameters,
- smu_pcie_arg);
-   if (ret)
-   pr_err("[%s] Attempt to override pcie params failed!\n", 
__func__);
-   return ret;
-}
-
 static int smu_smc_table_hw_init(struct smu_context *smu,
 bool initialize)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ccf711c..809de0d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -468,6 +468,7 @@ struct pptable_funcs {
int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool 
asic_default);
int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type 
clk_type,
   uint32_t dpm_level, uint32_t *freq);
+   int (*update_pcie_parameters)(struct smu_context *smu, uint32_t 
pcie_gen_cap, uint32_t pcie_width_cap);
 };
 
 struct smu_funcs
@@ -550,6 +551,7 @@ struct smu_funcs
int (*mode2_reset)(struct smu_context *smu);
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type 
clk_type, uint32_t *min, uint32_t *max);
int (*set_soft_freq_limited_range)(struct smu_context *smu, enum 
smu_clk_type clk_type, uint32_t min, uint32_t max);
+   int (*override_pcie_parameters)(struct smu_context *smu);
 };
 
 #define smu_init_microcode(smu) \
@@ -782,6 +784,12 @@ struct smu_funcs
 #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
((smu)->funcs->set_soft_freq_limited_range ? 
(smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : 
-EINVAL)
 
+#define smu_override_pcie_parameters(s

[PATCH] drm/amd/amdgpu: add IH cg support on soc15 project

[Kenneth Feng]

enable/disable IH clock gating on soc15 projects.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c |  3 +-
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 39 ++
 .../amd/include/asic_reg/oss/osssys_4_0_sh_mask.h  |  4 +++
 3 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 58818761..e40410e 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1166,7 +1166,8 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_MC_MGCG |
-   AMD_CG_SUPPORT_MC_LS;
+   AMD_CG_SUPPORT_MC_LS |
+   AMD_CG_SUPPORT_IH_CG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x32;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 14e0b04..5cb7e23 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -675,10 +675,49 @@ static int vega10_ih_soft_reset(void *handle)
return 0;
 }
 
+static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,
+  bool enable)
+{
+   uint32_t data, def, field_val;
+
+   if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
+   def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
+   field_val = enable ? 0 : 1;
+   /**
+* Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE
+* and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field.
+*/
+   if (adev->asic_type > CHIP_VEGA10) {
+   data = REG_SET_FIELD(data, IH_CLK_CTRL,
+IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, 
field_val);
+   data = REG_SET_FIELD(data, IH_CLK_CTRL,
+IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, 
field_val);
+   }
+
+   data = REG_SET_FIELD(data, IH_CLK_CTRL,
+DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
+   data = REG_SET_FIELD(data, IH_CLK_CTRL,
+OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
+   data = REG_SET_FIELD(data, IH_CLK_CTRL,
+LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
+   data = REG_SET_FIELD(data, IH_CLK_CTRL,
+DYN_CLK_SOFT_OVERRIDE, field_val);
+   data = REG_SET_FIELD(data, IH_CLK_CTRL,
+REG_CLK_SOFT_OVERRIDE, field_val);
+   if (def != data)
+   WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
+   }
+}
+
 static int vega10_ih_set_clockgating_state(void *handle,
  enum amd_clockgating_state state)
 {
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   vega10_ih_update_clockgating_state(adev,
+   state == AMD_CG_STATE_GATE ? true : false);
return 0;
+
 }
 
 static int vega10_ih_set_powergating_state(void *handle,
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
index dc9895a..096d878 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
@@ -588,11 +588,15 @@
 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK   
   0x4000L
 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK   
   0x8000L
 //IH_CLK_CTRL
+#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT 
0x19
+#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT
  0x1a
 #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 
   0x1b
 #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 
   0x1c
 #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT
   0x1d
 #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT  
   0x1e
 #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT  
   0x1f
+#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK   
 

[PATCH v2] drm/amd/amdgpu: disable MMHUB PG for navi10

[Kenneth Feng]

Disable MMHUB PG for navi10 according to the production requirement.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index d4a2012..46f402a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -616,7 +616,6 @@ static int nv_common_early_init(void *handle)
AMD_CG_SUPPORT_BIF_LS;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
-   AMD_PG_SUPPORT_MMHUB |
AMD_PG_SUPPORT_ATHUB;
adev->external_rev_id = adev->rev_id + 0x1;
break;
-- 
2.7.4

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[PATCH v2] drm/amd/amdgpu: disable MMHUB PG for navi10

[Kenneth Feng]

Disable MMHUB PG for navi10 according to the production requirement.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index d4a2012..46f402a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -616,7 +616,6 @@ static int nv_common_early_init(void *handle)
AMD_CG_SUPPORT_BIF_LS;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
-   AMD_PG_SUPPORT_MMHUB |
AMD_PG_SUPPORT_ATHUB;
adev->external_rev_id = adev->rev_id + 0x1;
break;
-- 
2.7.4

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[PATCH] drm/amd/powerplay: disable MMHUB PG on navi10/14

[Kenneth Feng]

Disable MMHUB PG on navi10 and navi14 according to the
production requirement.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 920156e..8b306d1 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -361,9 +361,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask &= 
~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
}
 
-   if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
-   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
-
if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 
-- 
2.7.4

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[PATCH] drm/amd/amdgpu: workaround for UVD busy status

[Kenneth Feng]

On Vega20, tools depends on UVD_STATUS.VCPU_REPORT bit0
to decide if UVD instances are in busy state or idle state.
This workaround fixes the issue that tools always fetch the
UVD instances state as busy state no matter if there is a UVD work.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c| 30 --
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  | 19 +++
 drivers/gpu/drm/amd/include/amd_shared.h   |  1 +
 5 files changed, 74 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4d096ff..6e5a41b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -259,6 +259,9 @@ int amdgpu_device_ip_set_clockgating_state(void *dev,
 int amdgpu_device_ip_set_powergating_state(void *dev,
   enum amd_ip_block_type block_type,
   enum amd_powergating_state state);
+int amdgpu_device_ip_set_instance_state(void *dev,
+  enum amd_ip_block_type block_type,
+  bool busy_state, int inst);
 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
u32 *flags);
 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 93ed3cb..e65e251 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1127,6 +1127,29 @@ int amdgpu_device_ip_set_powergating_state(void *dev,
return r;
 }
 
+int amdgpu_device_ip_set_instance_state(void *dev,
+  enum amd_ip_block_type block_type,
+  bool busy_state, int inst)
+{
+   struct amdgpu_device *adev = dev;
+   int i, r = 0;
+
+   for (i = 0; i < adev->num_ip_blocks; i++) {
+   if (!adev->ip_blocks[i].status.valid)
+   continue;
+   if (adev->ip_blocks[i].version->type != block_type)
+   continue;
+   if (!adev->ip_blocks[i].version->funcs->set_instance_state)
+   continue;
+   r = adev->ip_blocks[i].version->funcs->set_instance_state(
+   (void *)adev, busy_state, inst);
+   if (r)
+   DRM_ERROR("set_instance_state of IP block <%s> failed 
%d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+   }
+   return r;
+}
+
 /**
  * amdgpu_device_ip_get_clockgating_state - get the CG state
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 4e5d13e4..d3496ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -1180,13 +1180,22 @@ static void amdgpu_uvd_idle_work_handler(struct 
work_struct *work)
struct amdgpu_device *adev =
container_of(work, struct amdgpu_device, uvd.idle_work.work);
unsigned fences = 0, i, j;
+   unsigned *fences_inst = (unsigned 
*)kzalloc(adev->uvd.num_uvd_inst*sizeof(unsigned), GFP_KERNEL);
 
for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
if (adev->uvd.harvest_config & (1 << i))
continue;
-   fences += amdgpu_fence_count_emitted(>uvd.inst[i].ring);
+   fences_inst[i] = 
amdgpu_fence_count_emitted(>uvd.inst[i].ring);
+   fences += fences_inst[i];
for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
-   fences += 
amdgpu_fence_count_emitted(>uvd.inst[i].ring_enc[j]);
+   fences_inst[i] += 
amdgpu_fence_count_emitted(>uvd.inst[i].ring_enc[j]); 
+   fences += fences_inst[i];
+   }
+   /* workaround for the tools to show UVD busy status */
+   if (fences_inst[i] == 0) {
+   amdgpu_device_ip_set_instance_state(adev, 
AMD_IP_BLOCK_TYPE_UVD,
+  false, i);
+   printk("Kenneth - set instance idle!\n");
}
}
 
@@ -1210,10 +1219,27 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
 {
struct amdgpu_device *adev = ring->adev;
bool set_clocks;
+   unsigned i,j;
+   unsigned *fences_inst = (unsigned 
*)kzalloc(adev->uvd.num_uvd_inst*sizeof(unsigned), GFP_KERNEL);
 
if (amdgpu_sriov_vf(adev))
return;

[PATCH v2] drm/amdgpu/powerplay: provide the interface to disable uclk switch for DAL

[Kenneth Feng]

provide the interface for DAL to disable uclk switch on navi10.
in this case, the uclk will be fixed to maximum.
this is a workaround when display configuration causes underflow issue.

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c   | 14 
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  5 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 25 ++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  |  7 ++
 4 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 7bc7abc..583f8fb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -802,6 +802,19 @@ enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct 
pp_smu *pp, int mhz)
return PP_SMU_RESULT_OK;
 }
 
+enum pp_smu_status pp_nv_set_pstate_handshake_support(
+   struct pp_smu *pp, BOOLEAN pstate_handshake_supported)
+{
+   const struct dc_context *ctx = pp->dm;
+   struct amdgpu_device *adev = ctx->driver_context;
+   struct smu_context *smu = >smu;
+
+   if (smu_display_disable_memory_clock_switch(smu, 
!pstate_handshake_supported))
+   return PP_SMU_RESULT_FAIL;
+
+   return PP_SMU_RESULT_OK;
+}
+
 enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
enum pp_smu_nv_clock_id clock_id, int mhz)
 {
@@ -917,6 +930,7 @@ void dm_pp_get_funcs(
funcs->nv_funcs.get_maximum_sustainable_clocks = 
pp_nv_get_maximum_sustainable_clocks;
/*todo  compare data with window driver */
funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
+   funcs->nv_funcs.set_pstate_handshake_support = 
pp_nv_set_pstate_handshake_support;
break;
 #endif
default:
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 33d2d75..8242cd1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -549,6 +549,8 @@ struct smu_context
 #define WATERMARKS_EXIST   (1 << 0)
 #define WATERMARKS_LOADED  (1 << 1)
uint32_t watermarks_bitmap;
+   uint32_t hard_min_uclk_req_from_dal;
+   bool disable_uclk_switch;
 
uint32_t workload_mask;
uint32_t workload_prority[WORKLOAD_POLICY_MAX];
@@ -632,6 +634,7 @@ struct pptable_funcs {
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t 
*clocks_in_khz, uint32_t *num_states);
int (*set_default_od_settings)(struct smu_context *smu, bool 
initialize);
int (*set_performance_level)(struct smu_context *smu, enum 
amd_dpm_forced_level level);
+   int (*display_disable_memory_clock_switch)(struct smu_context *smu, 
bool disable_memory_clock_switch);
 };
 
 struct smu_funcs
@@ -884,6 +887,8 @@ struct smu_funcs
((smu)->ppt_funcs->get_clock_by_type_with_voltage ? 
(smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
 #define smu_display_clock_voltage_request(smu, clock_req) \
((smu)->funcs->display_clock_voltage_request ? 
(smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
+#define smu_display_disable_memory_clock_switch(smu, 
disable_memory_clock_switch) \
+   ((smu)->ppt_funcs->display_disable_memory_clock_switch ? 
(smu)->ppt_funcs->display_disable_memory_clock_switch((smu), 
(disable_memory_clock_switch)) : -EINVAL)
 #define smu_get_dal_power_level(smu, clocks) \
((smu)->funcs->get_dal_power_level ? 
(smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
 #define smu_get_perf_level(smu, designation, level) \
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c873228..a8c98c4 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1655,6 +1655,30 @@ static int navi10_get_thermal_temperature_range(struct 
smu_context *smu,
return 0;
 }
 
+static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
+   bool 
disable_memory_clock_switch)
+{
+   int ret = 0;
+   struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
+   (struct smu_11_0_max_sustainable_clocks *)
+   smu->smu_table.max_sustainable_clocks;
+   uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
+   uint32_t max_memory_clock = max_sustainable_clocks->uclock;
+
+   if(smu->disable_uclk_switch == disable_memory_clock_switch)
+   return 0;
+
+   if(disable_memory_clock_switch)
+   ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_m

[PATCH] drm/amdgpu/powerplay: provide the interface to disable uclk switch for DAL

[Kenneth Feng]

provide the interface for DAL to disable uclk switch on navi10.
in this case, the uclk will be fixed to maximum.
this is a workaround when display configuration causes underflow issue.

Signed-off-by: Kenneth Feng 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c   | 17 +++
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  5 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 25 ++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  |  7 ++
 4 files changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 7bc7abc..5b4323b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -802,6 +802,22 @@ enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct 
pp_smu *pp, int mhz)
return PP_SMU_RESULT_OK;
 }
 
+enum pp_smu_status pp_nv_set_pstate_handshake_support(struct pp_smu *pp,
+   
BOOLEAN pstate_handshake_supported)
+{
+   const struct dc_context *ctx = pp->dm;
+   struct amdgpu_device *adev = ctx->driver_context;
+   struct smu_context *smu = >smu;
+
+   if (!smu->ppt_funcs)
+   return PP_SMU_RESULT_UNSUPPORTED;
+
+   if (smu_display_disable_memory_clock_switch(smu, 
!pstate_handshake_supported))
+   return PP_SMU_RESULT_FAIL;
+
+   return PP_SMU_RESULT_OK;
+}
+
 enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
enum pp_smu_nv_clock_id clock_id, int mhz)
 {
@@ -917,6 +933,7 @@ void dm_pp_get_funcs(
funcs->nv_funcs.get_maximum_sustainable_clocks = 
pp_nv_get_maximum_sustainable_clocks;
/*todo  compare data with window driver */
funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
+   funcs->nv_funcs.set_pstate_handshake_support = 
pp_nv_set_pstate_handshake_support;
break;
 #endif
default:
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 33d2d75..642a1b1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -549,6 +549,8 @@ struct smu_context
 #define WATERMARKS_EXIST   (1 << 0)
 #define WATERMARKS_LOADED  (1 << 1)
uint32_t watermarks_bitmap;
+   uint32_t hard_min_uclk_req_from_dal;
+   bool disable_uclk_switch;
 
uint32_t workload_mask;
uint32_t workload_prority[WORKLOAD_POLICY_MAX];
@@ -632,6 +634,7 @@ struct pptable_funcs {
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t 
*clocks_in_khz, uint32_t *num_states);
int (*set_default_od_settings)(struct smu_context *smu, bool 
initialize);
int (*set_performance_level)(struct smu_context *smu, enum 
amd_dpm_forced_level level);
+   int (*display_disable_memory_clock_switch)(struct smu_context *smu, 
bool disable_memory_clock_switch);
 };
 
 struct smu_funcs
@@ -884,6 +887,8 @@ struct smu_funcs
((smu)->ppt_funcs->get_clock_by_type_with_voltage ? 
(smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
 #define smu_display_clock_voltage_request(smu, clock_req) \
((smu)->funcs->display_clock_voltage_request ? 
(smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
+#define smu_display_disable_memory_clock_switch(smu, 
disable_memory_clock_switch) \
+   ((smu)->ppt_funcs->display_disable_memory_clock_switch ? 
(smu)->ppt_funcs->display_disable_memory_clock_switch((smu), 
(disable_memory_clock_switch)) : 0)
 #define smu_get_dal_power_level(smu, clocks) \
((smu)->funcs->get_dal_power_level ? 
(smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
 #define smu_get_perf_level(smu, designation, level) \
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c873228..a8c98c4 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1655,6 +1655,30 @@ static int navi10_get_thermal_temperature_range(struct 
smu_context *smu,
return 0;
 }
 
+static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
+   bool 
disable_memory_clock_switch)
+{
+   int ret = 0;
+   struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
+   (struct smu_11_0_max_sustainable_clocks *)
+   smu->smu_table.max_sustainable_clocks;
+   uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
+   uint32_t max_memory_clock = max_sustainable_clocks->uclock;
+
+ 

[PATCH] drm/amd/powerplay: change smu_read_sensor sequence in smu

[Kenneth Feng]

change the smu_read_sensor sequence to:

asic specific sensor read -> smu v11 specific sensor read -> smu v11 common 
sensor read

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++--
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 -
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 8 
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 5 -
 5 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 416f9a8..8ff18c8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -315,6 +315,9 @@ int smu_common_read_sensor(struct smu_context *smu, enum 
amd_pp_sensors sensor,
 {
int ret = 0;
 
+   if(!data || !size)
+   return -EINVAL;
+
switch (sensor) {
case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
*((uint32_t *)data) = smu->pstate_sclk;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index b702c9e..fabb373 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -819,9 +819,9 @@ struct smu_funcs
 #define smu_start_thermal_control(smu) \
((smu)->funcs->start_thermal_control? 
(smu)->funcs->start_thermal_control((smu)) : 0)
 #define smu_read_sensor(smu, sensor, data, size) \
-   ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), 
(data), (size)) : 0)
-#define smu_asic_read_sensor(smu, sensor, data, size) \
((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), 
(sensor), (data), (size)) : 0)
+#define smu_smc_read_sensor(smu, sensor, data, size) \
+   ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), 
(data), (size)) : -EINVAL)
 #define smu_get_power_profile_mode(smu, buf) \
((smu)->ppt_funcs->get_power_profile_mode ? 
(smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
 #define smu_set_power_profile_mode(smu, param, param_size) \
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c8ce9bb..6409718 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1366,6 +1366,9 @@ static int navi10_read_sensor(struct smu_context *smu,
struct smu_table_context *table_context = >smu_table;
PPTable_t *pptable = table_context->driver_pptable;
 
+   if(!data || !size)
+   return -EINVAL;
+
switch (sensor) {
case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
*(uint32_t *)data = pptable->FanMaximumRpm;
@@ -1387,7 +1390,7 @@ static int navi10_read_sensor(struct smu_context *smu,
*size = 4;
break;
default:
-   return -EINVAL;
+   ret = smu_smc_read_sensor(smu, sensor, data, size);
}
 
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index e3a1784..5267b68 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1267,6 +1267,10 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
 void *data, uint32_t *size)
 {
int ret = 0;
+
+   if(!data || !size)
+   return -EINVAL;
+
switch (sensor) {
case AMDGPU_PP_SENSOR_GFX_MCLK:
ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
@@ -1289,10 +1293,6 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
break;
}
 
-   /* try get sensor data by asic */
-   if (ret)
-   ret = smu_asic_read_sensor(smu, sensor, data, size);
-
if (ret)
*size = 0;
 
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c 
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 9ead361..e864a54 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -3163,6 +3163,9 @@ static int vega20_read_sensor(struct smu_context *smu,
struct smu_table_context *table_context = >smu_table;
PPTable_t *pptable = table_context->driver_pptable;
 
+   if(!data || !size)
+   return -EINVAL;
+
switch (sensor) {
case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
*(uint32_t *)data = pptable->FanMaximumRpm;
@@ -3186,7 +3189,7 @@ static int vega20_read_sensor(struct smu_context *smu,
*size = 4;
break;
default:
-   return -EINVAL;
+   ret = smu_smc_read_sensor(smu, sensor, data, size);
}
 
return ret;
-- 
2.7.4

_

[PATCH] drm/amd/powerplay: enable fw ctf,apcc dfll and gfx ss

[Kenneth Feng]

enable fw ctf, apcc dfll and gfx ss on navi10.
fw ctf: when the fw ctf is triggered, the gfx and soc power domain
are shut down. fan speed is boosted to the maximum.
gfx ss: hardware feature, sanity check has been done.
apcc dfll: can check the scoreboard in smu fw to confirm if it's enabled.
no need to do furhter check since the gfx hardware control the frquency once
a pcc signal comes.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 895a4e5..fa636d2 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -331,7 +331,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_BACO_BIT)
-   | FEATURE_MASK(FEATURE_ACDC_BIT);
+   | FEATURE_MASK(FEATURE_ACDC_BIT)
+   | FEATURE_MASK(FEATURE_GFX_SS_BIT)
+   | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
+   | FEATURE_MASK(FEATURE_FW_CTF_BIT);
 
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
@@ -339,8 +342,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 
if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
-   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
-   | FEATURE_MASK(FEATURE_GFXOFF_BIT);
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
/* TODO: remove it once fw fix the bug */
*(uint64_t *)feature_mask &= 
~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
}
@@ -465,9 +467,6 @@ static int navi10_append_powerplay_table(struct smu_context 
*smu)
smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 
if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
-   *(uint64_t *)smc_pptable->FeaturesToRun |= 
FEATURE_MASK(FEATURE_GFX_SS_BIT)
-   | FEATURE_MASK(FEATURE_GFXOFF_BIT);
-
/* TODO: remove it once SMU fw fix it */
smc_pptable->DebugOverrides |= 
DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
}
-- 
2.7.4

___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/powerplay: bug fix for sysfs

[Kenneth Feng]

when we set profile_peak to sysfs:power_dpm_force_performance_level,
we gets the wrong socclk level and mclk level.this patch fix this issue.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 5ee6508..cd32b20 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1157,14 +1157,14 @@ static int navi10_get_profiling_clk_mask(struct 
smu_context *smu,
ret = smu_get_dpm_level_count(smu, SMU_MCLK, 
_count);
if (ret)
return ret;
-   *sclk_mask = level_count - 1;
+   *mclk_mask = level_count - 1;
}
 
if(soc_mask) {
ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, 
_count);
if (ret)
return ret;
-   *sclk_mask = level_count - 1;
+   *soc_mask = level_count - 1;
}
}
 
-- 
2.7.4

___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/powerplay: update soc boot and max level on vega10

[Kenneth Feng]

update soc boot and max level,then uclk isn't stuck
at minimum.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 0d38ac2..5479125 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3579,6 +3579,10 @@ static int vega10_generate_dpm_level_enable_mask(

vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
data->smc_state_table.mem_max_level =

vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
+   data->smc_state_table.soc_boot_level =
+   
vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table));
+   data->smc_state_table.soc_max_level =
+   
vega10_find_highest_dpm_level(&(data->dpm_table.soc_table));
 
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
"Attempt to upload DPM Bootup Levels Failed!",
@@ -3593,6 +3597,9 @@ static int vega10_generate_dpm_level_enable_mask(
for(i = data->smc_state_table.mem_boot_level; i < 
data->smc_state_table.mem_max_level; i++)
data->dpm_table.mem_table.dpm_levels[i].enabled = true;
 
+   for (i = data->smc_state_table.soc_boot_level; i < 
data->smc_state_table.soc_max_level; i++)
+   data->dpm_table.soc_table.dpm_levels[i].enabled = true;
+
return 0;
 }
 
-- 
2.7.4

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[PATCH] Revert "Revert "drm/amd/powerplay: support Vega10 SOCclk and DCEFclk dpm level settings""

[Kenneth Feng]

This reverts commit ea37fc706e4cde83b39ad2104eec0241e752b8ea.
Since we have another patch to fix the below problem,
we need to revert the 'revert'
https://bugs.freedesktop.org/show_bug.cgi?id=109462
Acked by Alex Deucher

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 83 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |  1 +
 2 files changed, 84 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index ddf8b20..0d38ac2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -72,6 +72,21 @@ static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 
0, 16, 2};
 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 
   0x0700L
 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 
   0xF000L
 
+typedef enum {
+   CLK_SMNCLK = 0,
+   CLK_SOCCLK,
+   CLK_MP0CLK,
+   CLK_MP1CLK,
+   CLK_LCLK,
+   CLK_DCEFCLK,
+   CLK_VCLK,
+   CLK_DCLK,
+   CLK_ECLK,
+   CLK_UCLK,
+   CLK_GFXCLK,
+   CLK_COUNT,
+} CLOCK_ID_e;
+
 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
 
 struct vega10_power_state *cast_phw_vega10_power_state(
@@ -3486,6 +3501,17 @@ static int vega10_upload_dpm_bootup_level(struct 
pp_hwmgr *hwmgr)
}
}
 
+   if (!data->registry_data.socclk_dpm_key_disabled) {
+   if (data->smc_state_table.soc_boot_level !=
+   
data->dpm_table.soc_table.dpm_state.soft_min_level) {
+   smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_SetSoftMinSocclkByIndex,
+   data->smc_state_table.soc_boot_level);
+   data->dpm_table.soc_table.dpm_state.soft_min_level =
+   data->smc_state_table.soc_boot_level;
+   }
+   }
+
return 0;
 }
 
@@ -3517,6 +3543,17 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr 
*hwmgr)
}
}
 
+   if (!data->registry_data.socclk_dpm_key_disabled) {
+   if (data->smc_state_table.soc_max_level !=
+   data->dpm_table.soc_table.dpm_state.soft_max_level) {
+   smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_SetSoftMaxSocclkByIndex,
+   data->smc_state_table.soc_max_level);
+   data->dpm_table.soc_table.dpm_state.soft_max_level =
+   data->smc_state_table.soc_max_level;
+   }
+   }
+
return 0;
 }
 
@@ -4029,6 +4066,24 @@ static int vega10_force_clock_level(struct pp_hwmgr 
*hwmgr,
 
break;
 
+   case PP_SOCCLK:
+   data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 
0;
+   data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 
0;
+
+   PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
+   "Failed to upload boot level to lowest!",
+   return -EINVAL);
+
+   PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
+   "Failed to upload dpm max level to highest!",
+   return -EINVAL);
+
+   break;
+
+   case PP_DCEFCLK:
+   pr_info("Setting DCEFCLK min/max dpm level is not 
supported!\n");
+   break;
+
case PP_PCIE:
default:
break;
@@ -4373,6 +4428,8 @@ static int vega10_print_clock_levels(struct pp_hwmgr 
*hwmgr,
struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_single_dpm_table *sclk_table = 
&(data->dpm_table.gfx_table);
struct vega10_single_dpm_table *mclk_table = 
&(data->dpm_table.mem_table);
+   struct vega10_single_dpm_table *soc_table = 
&(data->dpm_table.soc_table);
+   struct vega10_single_dpm_table *dcef_table = 
&(data->dpm_table.dcef_table);
struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
 
@@ -4403,6 +4460,32 @@ static int vega10_print_clock_levels(struct pp_hwmgr 
*hwmgr,
i, mclk_table->dpm_levels[i].value / 
100,
(i == now) ? "*" : "");
break;
+   case PP_SOCCLK:
+   if (data->registry_data.socclk_dpm_key_disabled)
+   break;
+
+   smum_send_msg_to_smc(hwmgr,

[PATCH] drm/amd/powerplay: OD setting fix on Vega10

[Kenneth Feng]

gfxclk for OD setting is limited to 1980M for non-acg
ASICs of Vega10

Signed-off-by: Kenneth Feng 
---
 .../amd/powerplay/hwmgr/vega10_processpptables.c   | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index b8747a5..99d596d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -32,6 +32,7 @@
 #include "vega10_pptable.h"
 
 #define NUM_DSPCLK_LEVELS 8
+#define VEGA10_ENGINECLOCK_HARDMAX 198000
 
 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
enum phm_platform_caps cap)
@@ -258,7 +259,26 @@ static int init_over_drive_limits(
struct pp_hwmgr *hwmgr,
const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
 {
-   hwmgr->platform_descriptor.overdriveLimit.engineClock =
+   const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
+   (const ATOM_Vega10_GFXCLK_Dependency_Table *)
+   (((unsigned long) powerplay_table) +
+   
le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
+   bool is_acg_enabled = false;
+   ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
+
+   if (gfxclk_dep_table->ucRevId == 1) {
+   patom_record_v2 =
+   (ATOM_Vega10_GFXCLK_Dependency_Record_V2 
*)gfxclk_dep_table->entries;
+   is_acg_enabled =
+   
(bool)patom_record_v2[gfxclk_dep_table->ucNumEntries-1].ucACGEnable;
+   }
+
+   if (powerplay_table->ulMaxODEngineClock > VEGA10_ENGINECLOCK_HARDMAX &&
+   !is_acg_enabled)
+   hwmgr->platform_descriptor.overdriveLimit.engineClock =
+   VEGA10_ENGINECLOCK_HARDMAX;
+   else
+   hwmgr->platform_descriptor.overdriveLimit.engineClock =
le32_to_cpu(powerplay_table->ulMaxODEngineClock);
hwmgr->platform_descriptor.overdriveLimit.memoryClock =
le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
-- 
2.7.4

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[PATCH] drm/amd/powerplay: run acg btc for Vega12

[Kenneth Feng]

acg btc was added to Vega12

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 5436444..0c82129 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -753,6 +753,22 @@ static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
return 0;
 }
 
+static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr)
+{
+   uint32_t result;
+
+   PP_ASSERT_WITH_CODE(
+   smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc) == 0,
+   "[Run_ACG_BTC] Attempt to run ACG BTC failed!",
+   return -EINVAL);
+
+   result = smum_get_argument(hwmgr);
+   PP_ASSERT_WITH_CODE(result == 1,
+   "Failed to run ACG BTC!", return -EINVAL);
+
+   return 0;
+}
+
 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 {
struct vega12_hwmgr *data =
@@ -931,6 +947,11 @@ static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
"Failed to initialize SMC table!",
result = tmp_result);
 
+   tmp_result = vega12_run_acg_btc(hwmgr);
+   PP_ASSERT_WITH_CODE(!tmp_result,
+   "Failed to run ACG BTC!",
+   result = tmp_result);
+
result = vega12_enable_all_smu_features(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to enable all smu features!",
-- 
2.7.4

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